WO2023071765A1 - 转移基板、制备方法和led芯片的巨量转移方法 - Google Patents

转移基板、制备方法和led芯片的巨量转移方法 Download PDF

Info

Publication number
WO2023071765A1
WO2023071765A1 PCT/CN2022/124419 CN2022124419W WO2023071765A1 WO 2023071765 A1 WO2023071765 A1 WO 2023071765A1 CN 2022124419 W CN2022124419 W CN 2022124419W WO 2023071765 A1 WO2023071765 A1 WO 2023071765A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor layer
led chips
substrate
epitaxial wafer
Prior art date
Application number
PCT/CN2022/124419
Other languages
English (en)
French (fr)
Inventor
戴广超
马非凡
王子川
赵世雄
Original Assignee
重庆康佳光电技术研究院有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 重庆康佳光电技术研究院有限公司 filed Critical 重庆康佳光电技术研究院有限公司
Publication of WO2023071765A1 publication Critical patent/WO2023071765A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the field of display technology, in particular to a hole-digging transfer substrate, a preparation method of the transfer substrate and a mass transfer method of LED chips.
  • Micro LED Micro Light Emitting Diode
  • TVs and mobile phone screens Due to the low tolerance of display products for pixel errors, the lifting transfer Micro
  • the yield rate of LED chips is particularly important to improve the yield rate of display products.
  • the commonly used transfer methods for Micro LED chips include: electrostatic force, van der Waals force, magnetic force, laser selective transfer, fluid transfer, and direct transfer.
  • the most commonly used transfer method is van der Waals force.
  • Selective pick-up and transfer of LED chips to the substrate due to Micro The LED chip is tightly bonded to the substrate, resulting in Micro The LED chip cannot be grasped by the elastic die, so the Micro The contact force between the LED chip and the substrate is weakened, which makes the Micro The LED chip can be grasped by the elastic die.
  • the Micro LED chip cannot be easily grasped by the elastic die.
  • a transfer substrate comprising: a temporary substrate and a bonding layer, wherein the bonding layer is arranged on the temporary substrate, and a plurality of grooves are provided on the side of the bonding layer facing away from the temporary substrate, the The above groove is used for accommodating LED chips.
  • the bonding layer is a silicon oxide layer formed by bonding a plurality of silicon oxide spheres through glue, wherein the diameter of the silicon oxide spheres is 10-100 um.
  • the etching depth of the groove is smaller than the thickness of the LED chip.
  • the present application also provides a method for preparing a transfer substrate, which is used to prepare the above-mentioned transfer substrate.
  • the preparation method includes: providing a temporary substrate; preparing a bonding layer on the temporary substrate; A plurality of grooves are provided on the side of the bonding layer facing away from the temporary substrate.
  • the present application also provides a mass transfer method of LED chips, the mass transfer method includes: providing an epitaxial wafer, and obtaining a plurality of LED chips through the epitaxial wafer; preparing the transfer substrate; A plurality of the LED chips are accommodated in the groove of the transfer substrate, and the substrate layer of the epitaxial wafer is removed; the plurality of the LED chips obtained by the epitaxial wafer are transferred to the back plate, and the plurality of the The first electrode and the second electrode of the LED chip are electrically connected to the backplane.
  • the providing an epitaxial wafer, and obtaining a plurality of LED chips through the epitaxial wafer includes: providing an epitaxial wafer comprising a plurality of epitaxial structures, forming a plurality of openings on the epitaxial wafer, and each of the openings corresponds to one
  • the epitaxial structure is arranged, and the epitaxial structure is formed into a first region and a second region; a plurality of slots are formed on the epitaxial wafer, and each of the slots is arranged between two adjacent epitaxial structures between; forming a metal layer on the second semiconductor layer located in the first region in the epitaxial wafer; forming an insulating protective layer covering the epitaxial wafer and the metal layer; partially removing the metal layer and the first semiconductor layer The insulating protective layer at the layer to partially expose the metal layer and the first semiconductor layer; the first electrode and the second electrode are respectively formed at the positions where the metal layer and the first semiconductor layer are exposed. electrodes, the first electrode is electrically connected to the metal layer, and
  • a plurality of the epitaxial structures are arranged in an array, and each of the epitaxial structures includes the substrate layer, the first semiconductor layer, the multi-quantum well light-emitting layer and the second semiconductor layer that are sequentially stacked, wherein, The first semiconductor layer is arranged on the substrate layer for providing electrons; the second semiconductor layer is arranged on the multi-quantum well light-emitting layer for providing holes; the multi-quantum well light-emitting layer is arranged Between the first semiconductor layer and the second semiconductor layer, a place is provided for recombination reaction of electrons provided by the first semiconductor layer and holes provided by the second semiconductor layer to generate photons.
  • each of the openings passes through the second semiconductor layer and the multi-quantum well light-emitting layer, and communicates with the first semiconductor layer, wherein the area of the first region is larger than that of the second region area.
  • each of the slots passes through the second semiconductor layer, the multi-quantum well light-emitting layer and the first semiconductor layer in sequence, and the slots are opened in a second region of the epitaxial structure Between the first region of another adjacent epitaxial structure.
  • the thickness of the metal layer is 200-2000A
  • the thickness of the insulating protection layer is 1-4um
  • the thickness of the first electrode and the second electrode is 1-4um.
  • the transfer substrate of the present application adopts a hole-digging transfer substrate design, and the transfer substrate is beneficial for the elastic die to grasp and transfer the LED chip. Moreover, the LED chip will not be shifted in the groove of the transfer substrate, which also makes it easy for the elastic die to grasp and transfer the LED chip, thereby increasing the size of the LED chip. Quantity transfer yield.
  • the transfer substrate of the present application adopts a hole-digging transfer substrate design, the silicon oxide sphere in the transfer substrate has a small contact area with the LED chip, and has no adhesion to the LED chip, so that the elastic stamp is convenient for the LED chips are grasped and transferred. At the same time, the LED chip will not be offset in the groove of the transfer substrate, which also makes it easy for the elastic die to grab and transfer the LED chip, thereby increasing the size of the LED chip. Quantity transfer yield.
  • the transfer substrate prepared by the preparation method of the present application adopts a hole-digging transfer substrate design, and the transfer substrate is beneficial to the elastic stamp to facilitate the grasping and transferring of the LED chip.
  • the LED chip will not be offset in the groove of the transfer substrate, which also makes it easy for the elastic die to grab and transfer the LED chip, thereby increasing the size of the LED chip. Quantity transfer yield.
  • the LED chips are transferred through a hole-digging transfer substrate, and the adhesive material in the transfer substrate is etched, and the silicon oxide in the transfer substrate
  • the sphere has no adhesion to the LED chip, so that the elastic stamp is convenient for grasping and transferring the LED chip.
  • the LED chip will not be shifted in the groove of the transfer substrate, which also makes it easy for the elastic die to grasp and transfer the LED chip, thereby increasing the size of the LED chip. Quantity transfer yield.
  • FIG. 1 is a schematic structural diagram of a transfer substrate disclosed in an embodiment of the present application.
  • FIG. 2 is a schematic flow diagram of a method for preparing a transfer substrate disclosed in an embodiment of the present application
  • Fig. 3 is a schematic diagram of the corresponding structure formed in step S10 in the preparation method shown in Fig. 2;
  • Fig. 4 is a schematic diagram of the corresponding structure formed in step S20 in the preparation method shown in Fig. 2;
  • FIG. 5 is a schematic diagram of the corresponding structure formed in step S30 in the preparation method shown in FIG. 2;
  • FIG. 6 is a schematic flow diagram of a mass transfer method for LED chips disclosed in an embodiment of the present application.
  • FIG. 7 is a schematic flow chart of step S100 in the mass transfer method shown in FIG. 5;
  • FIG. 8 is a schematic diagram of the corresponding structure formed in step S110 in the mass transfer method shown in FIG. 7;
  • FIG. 9 is a schematic diagram of the corresponding structure formed in step S120 in the mass transfer method shown in FIG. 7;
  • FIG. 10 is a schematic diagram of the corresponding structure formed in step S130 in the mass transfer method shown in FIG. 7;
  • FIG. 11 is a schematic diagram of the corresponding structure formed in step S140 in the mass transfer method shown in FIG. 7;
  • FIG. 12 is a schematic diagram of the corresponding structure formed in step S150 in the mass transfer method shown in FIG. 7;
  • FIG. 13 is a schematic diagram of the corresponding structure formed in step S160 in the mass transfer method shown in FIG. 7;
  • FIG. 14 is a schematic diagram of the corresponding structure formed in step S300 in the mass transfer method shown in FIG. 6;
  • FIG. 15 is a schematic diagram of the corresponding structure formed in step S400 in the mass transfer method shown in FIG. 6 .
  • step S110-S160- The step of step S100 in the mass transfer method of LED chips.
  • Micro LED Micro Light Emitting Diode
  • Micro LED has higher photoelectric efficiency, higher brightness, higher contrast and lower power consumption than traditional LEDs.
  • display products related to LED chips such as TVs and mobile phone screens. Due to the low tolerance of display products for pixel errors, the lifting transfer Micro
  • the yield rate of LED chips is particularly important to improve the yield rate of display products.
  • Micro Commonly used transfer methods for LED chips include: electrostatic force, van der Waals force, magnetic force, laser selective transfer, fluid transfer, and direct transfer.
  • the most commonly used transfer method is van der Waals force, which uses elastic impressions to micro Selective pick-up and transfer of LED chips to the substrate.
  • Due to Micro The LED chip is tightly bonded to the substrate, resulting in Micro The LED chip cannot be grasped by the elastic die, so the Micro The contact force between the LED chip and the substrate is weakened, which makes the Micro The LED chip can be grasped by the elastic die. Therefore, how to solve the problem due to Micro The tight combination between the LED chip and the substrate leads to Micro It is a problem that those skilled in the art urgently need to solve that the LED chip cannot be easily grasped by the elastic die.
  • this application hopes to provide a solution that can solve the above technical problems, which can solve the problem that the Micro LED chip cannot be easily grasped by the elastic die due to the tight combination of the Micro LED chip and the substrate.
  • the details will be in It is illustrated in the subsequent examples.
  • FIG. 1 is a schematic structural diagram of a transfer substrate disclosed in an embodiment of the present application.
  • the present application provides a transfer substrate 100 , which may adopt a hole-digging transfer substrate design.
  • the transfer substrate 100 may at least include a temporary substrate 110 and a bonding layer 120 .
  • the bonding layer 120 is disposed on the temporary substrate 110, and a plurality of grooves 121 are provided on the side of the bonding layer 120 facing away from the temporary substrate 110, and the grooves 121 are used for accommodating LEDs. chip.
  • the LED chip is a micro LED chip.
  • the depth of the groove 121 is 3-6um, such as 3um, 4um, 5um, 6um, or other values.
  • the bonding layer 120 is a silicon oxide layer formed by bonding a plurality of silicon oxide spheres through glue, wherein the diameter of the silicon oxide spheres is 10-100um, such as 20um, 30um, 40um, 50um, 60um, or other values.
  • the bonding layer 120 is formed by uniformly bonding a plurality of silicon oxide spheres through glue, and the bonding layer 120 is deposited on one side surface of the temporary substrate 110 .
  • the pattern of the groove 121 is formed on the side of the bonding layer 120 facing away from the temporary base 110 by photolithography. It can be understood that the etching depth of the groove 121 is smaller than the thickness of the LED chip.
  • the transfer substrate 100 of the present application adopts a hole-digging transfer substrate design
  • the silicon oxide spheres in the transfer substrate 100 have a small contact area with the LED chip, and have no adhesion to the LED chip 300, thus
  • the elastic stamp is made to be convenient for grasping and transferring the LED chip 300 .
  • the LED chip 300 will not be offset in the groove 121 of the transfer substrate 100, which also makes the elastic die easy to grasp and transfer the LED chip 300, thereby increasing the Mass transfer yield of LED chips 300 .
  • FIG. 2 is a schematic flowchart of a method for preparing a transfer substrate disclosed in an embodiment of the present application.
  • the method for preparing the transfer substrate is used to prepare the transfer substrate in the above embodiment shown in FIG. 1 , so as to facilitate the grasping and transfer of the LED chips by the elastic stamp.
  • the method for preparing the transfer substrate includes at least the following steps.
  • the temporary substrate 110 is prepared for subsequent growth of other layer structures of the transfer substrate 100 .
  • silicon oxide spheres are deposited on one side of the temporary substrate 110, and a plurality of silicon oxide spheres are uniformly bonded by glue to form the bonding layer 120. .
  • the silicon oxide spheres may have a diameter of 10-100 um, such as 10 um, 20 um, 30 um, 40 um, 50 um, 60 um, 80 um, or other values.
  • the pattern of the groove 121 is formed by photolithography on the side of the bonding layer 120 facing away from the temporary base 110.
  • the groove 121 is used for accommodating LED chips.
  • the depth of the groove 121 is 3-6um, such as 3um, 4um, 5um, 6um, or other values.
  • the photolithography is an inductively coupled plasma (Inductively Coupled Plasma) Coupled Plasma, ICP) dry etching
  • the etching gas of the ICP dry etching is CF4/O2/Ar
  • the etching depth of the groove 121 is 3-6um, such as 3um, 4um, 5um, 6um , or other values. It can be understood that the etching depth of the groove 121 is smaller than the thickness of the LED chip.
  • the transfer substrate 100 prepared by the preparation method of the present application adopts a hole-digging transfer substrate design
  • the silicon oxide spheres in the transfer substrate 100 have a small contact area with the LED chip, and have no adhesion to the LED chip 300. Adhesion, so that the elastic stamp is convenient for grabbing and transferring the LED chip 300 .
  • the LED chip 300 will not be offset in the groove 121 of the transfer substrate 100, which also makes the elastic die easy to grasp and transfer the LED chip 300, thereby increasing the Mass transfer yield of LED chips 300 .
  • FIG. 6 is a schematic flowchart of a method for mass transfer of LED chips disclosed in an embodiment of the present application.
  • the mass transfer method is used for mass transfer of LED chips, so as to achieve the effect of increasing the yield rate of mass transfer of LED chips.
  • the method for mass transfer of LED chips may at least include the following steps.
  • the step S100 includes at least the following steps.
  • S110 providing an epitaxial wafer 200 including a plurality of epitaxial structures 260, forming a plurality of openings 262 on the epitaxial wafer 200, each of the openings 262 corresponding to one of the epitaxial structures 260, and forming the epitaxial structures into a second area one and area two.
  • the epitaxial wafer 200 includes a substrate layer 210 , a first semiconductor layer 220 , a multi-quantum well light-emitting layer 230 and a second semiconductor layer 240 stacked in sequence.
  • the first semiconductor layer 220 is disposed on the substrate layer 210 for providing electrons
  • the second semiconductor layer 240 is disposed on the multi-quantum well light-emitting layer 230 for providing holes, thereby being compatible with
  • the electrons provided by the first semiconductor layer 220 undergo a recombination reaction to generate photons.
  • the multi-quantum well light-emitting layer 230 is disposed between the first semiconductor layer 220 and the second semiconductor layer 240 to provide a place for the electrons provided by the first semiconductor layer 220 and the electrons provided by the second semiconductor layer 240.
  • the holes recombine to produce photons.
  • the first semiconductor layer 220 is an N-type semiconductor material, for example, N-type gallium nitride (GaN).
  • the second semiconductor layer 240 is a P-type semiconductor material, for example, P-type gallium nitride (GaN).
  • the epitaxial wafer 200 includes a plurality of epitaxial structures 260 arranged in an array, and each epitaxial structure 260 also includes a substrate layer 210 and a first semiconductor layer 220 stacked in sequence. , the multi-quantum well light-emitting layer 230 and the second semiconductor layer 240 .
  • the epitaxial wafer 200 is opened to form a plurality of openings 262 , and each opening 262 is disposed corresponding to one of the epitaxial structures 260 .
  • the opening 262 penetrates through the second semiconductor layer 240 and the multi-quantum well light-emitting layer 230 until the first semiconductor layer 220 , that is, the opening 262 and the first semiconductor layer 220 and form a groove with the first semiconductor layer 220 as the bottom, so that the epitaxial structure 260 forms a first region 264 and a second region 265, wherein the area of the first region 264 is larger than that of the second region 265 area.
  • the plurality of openings 262 on the epitaxial wafer 200 may be formed by photolithography, and the plurality of openings 262 on the epitaxial wafer 200 form a first pattern.
  • the first pattern may be a MESA (step etching) pattern.
  • the photolithography is dry etching, and the etching gas of the dry etching is BCl3/Cl2.
  • each of the slots 266 is disposed between two adjacent epitaxial structures 260 .
  • a plurality of slots 266 are formed on the epitaxial wafer 200 , and each of the slots 266 is arranged on two adjacent epitaxial structures 260 between.
  • the slot 266 passes through the second semiconductor layer 240 , the multi-quantum well light-emitting layer 230 and the first semiconductor layer 220 in sequence. It can also be understood that the slot 266 is opened between the second region 265 of one epitaxial structure 260 and the first region 264 of another adjacent epitaxial structure 260 .
  • the plurality of grooves 266 on the epitaxial wafer 200 may be formed by photolithography, and the plurality of grooves 266 on the epitaxial wafer 200 form the second pattern.
  • the second pattern may be an ISO (GaN deep etch) pattern.
  • the photolithography is dry etching, and the etching gas of the dry etching is BCl3/Cl2.
  • the etching depth is 4-8um, such as 4um, 5um, 6um, 7um, or other values.
  • the opening 262 penetrates through the second semiconductor layer 240 and the multi-quantum well light-emitting layer 230 until the first semiconductor layer 220, so that the The epitaxial structure 260 forms a first region 264 and a second region 265 , and an indium tin oxide (ITO) layer 310 is formed on the second semiconductor layer 240 located in the first region 264 in the epitaxial wafer 200 .
  • ITO indium tin oxide
  • the metal layer 310 may have a thickness of 200-2000A, such as 200A, 300A, 400A, 500A, 800A, 1500A, 1800A, or other values.
  • the metal layer 310 may be made of indium tin oxide (ITO).
  • the insulating protection layer 320 can be a stack of silicon oxide and silicon nitride, for example, the insulating protection layer 320 can also be a distributed Bragg reflector (Distributed Bragg Reflection, DBR).
  • DBR distributed Bragg Reflection
  • the insulating protection layer 320 is formed on the epitaxial wafer 200 and the metal layer 310 by vapor-depositing a stack of silicon oxide and silicon nitride (DBR).
  • the insulating protection layer 320 may have a thickness of 1-4um, such as 1um, 1.5um, 2um, 3.5um, 4um, or other values.
  • partially removing the insulating protection layer 320 refers to partially removing the insulating protection layer 320 at the metal layer 310 and the first semiconductor layer 220 , so as to partially expose the metal layer 310 and the first semiconductor layer 220 .
  • the insulating protection layer 320 may be partially removed by, but not limited to, dry etching using a dry etching tool.
  • the etching gas for the dry etching may be CF4/O2/Ar, and the etching depth needs to penetrate the insulating protection layer 320 .
  • the The first semiconductor layer 220 partially exposes the insulating protection layer 320 , and the first electrode 340 and the second electrode 350 are respectively formed at the positions where the metal layer 310 and the first semiconductor layer 220 are exposed.
  • the first electrode is electrically connected to the metal layer
  • the second electrode is electrically connected to the first semiconductor layer and exposed to the insulating protection layer 320 .
  • the first electrode and the second electrode in this step are used as metal layers for bonding, and a complete micro LED chip 300 is obtained.
  • a negative photoresist electrode pattern can be used on the insulating protection layer 320, and the electrode pattern is evaporated using an evaporation machine, and the first electrode and the second electrode are obtained after peeling off the glue through the blue film.
  • two electrodes to prepare a plurality of LED chips 300 two electrodes to prepare a plurality of LED chips 300 .
  • the thickness of the first electrode 340 and the second electrode 350 may be 1-4um, such as 1um, 2um, 3um, 4um, or other values.
  • the step S200 includes at least the following steps.
  • the temporary substrate 110 is prepared for subsequent growth of other layer structures of the transfer substrate 100 .
  • silicon oxide spheres are deposited on one side of the temporary substrate 110, and a plurality of silicon oxide spheres are uniformly bonded by glue to form the bonding layer 120. .
  • the silicon oxide spheres may have a diameter of 10-100 um, such as 10 um, 20 um, 30 um, 40 um, 50 um, 60 um, 80 um, or other values.
  • the pattern of the groove 121 is formed by photolithography on the side of the bonding layer 120 facing away from the temporary base 110.
  • the groove 121 is used for accommodating LED chips.
  • the depth of the groove 121 is 3-6um, such as 3um, 4um, 5um, 6um, or other values.
  • the photolithography is an inductively coupled plasma (Inductively Coupled Plasma) Coupled Plasma, ICP) dry etching
  • the etching gas of the ICP dry etching is CF4/O2/Ar
  • the etching depth of the groove 121 is 3-6um, such as 3um, 4um, 5um, 6um , or other values. It can be understood that the etching depth of the groove 121 is smaller than the thickness of the LED chip.
  • the substrate layer 210 is ground and polished, the first electrode 340 and the second electrode 350 of the LED chip 300 are bonded with an adhesive, and the adhesive
  • the LED chip 300 of the material is accommodated in the groove 121 corresponding to the transfer substrate 100, and the first electrode 340 and the second electrode 350 of the LED chip 300 are respectively bonded to the bottom of the groove 121, And the substrate layer 210 is removed by laser lift off.
  • the size of the groove 121 is larger than the size of the first electrode 340 and the second electrode 350 .
  • the adhesive material in the LED chip 300 and the transfer substrate 100 is etched, and the LED chip 300 is transferred to the On the backplane 400 , the first electrodes 340 and the second electrodes 350 of the plurality of LED chips 300 are electrically connected to the backplane 400 .
  • the etching method is dry etching, and the etching gas of the dry etching is CF4/O2/Ar.
  • the LED chips 300 are transferred through the hole-digging transfer substrate 100, and the adhesive material in the transfer substrate 100 is etched,
  • the silicon oxide spheres in the transfer substrate 100 have no adhesion to the LED chip 300 , so that the elastic stamp is convenient for grabbing and transferring the LED chip 300 .
  • the LED chip 300 will not be offset in the groove 121 of the transfer substrate 100, which also makes the elastic die easy to grasp and transfer the LED chip 300, thereby increasing the Mass transfer yield of LED chips 300 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)

Abstract

本申请涉及一种转移基板，其包括：临时基板以及键合层，其中，所述键合层设置于所述临时基板上，所述键合层背对所述临时基板的一侧开设多个凹槽，所述凹槽用于容置LED芯片。本申请还提供了一种转移基板的制备方法以及一种LED芯片的巨量转移方法。

Description

转移基板、制备方法和LED芯片的巨量转移方法 技术领域
本申请涉及显示技术领域，特别涉及一种挖孔式的转移基板、一种转移基板的制备方法以及一种LED芯片的巨量转移方法。
 背景技术
微型发光二极管(Micro Light Emitting Diode，Micro LED)作为新一代的显示技术，与传统LED相比，其具有更高的光电效率、更高的亮度、更高的对比度以及更低的功耗。随着制程的成熟和价格的下降，近年来基于Micro LED芯片的相关显示产品越来越多，例如电视机、手机屏等。由于显示产品对于像素错误的容忍度较低，因此提升转移Micro LED芯片的良率对提高显示产品的良率尤为重要。
目前，Micro LED芯片常用的转移方法包括：静电力、范德华力、磁力、激光选择转移、流体转移以及直接转移，其中，当前使用较多的转移方式就是范德华力，范德华力使用弹性印模对Micro LED芯片进行选择性拾取转移至衬底。然而，由于Micro LED芯片与衬底紧密结合，导致Micro LED芯片无法被弹性印模抓取，因此需要将Micro LED芯片与衬底的接触力弱化，从而使得Micro LED芯片能够被弹性印模抓取。
 技术问题
由于Micro LED芯片与衬底紧密结合导致Micro LED芯片无法便捷地被弹性印模抓取等问题。
 技术解决方案
一种转移基板，包括：临时基板以及键合层，其中，所述键合层设置于所述临时基板上，所述键合层背对所述临时基板的一侧开设多个凹槽，所述凹槽用于容置LED芯片。
可选地，所述键合层是由多个氧化硅球体通过胶材键合形成的氧化硅层，其中，所述氧化硅球体的球径为10-100um。
可选地，所述凹槽的刻蚀深度小于所述LED芯片的厚度。
基于同样的发明构思，本申请还提供一种转移基板的制备方法，用于制备上述的转移基板，所述制备方法包括：提供一临时基板；在所述临时基板上制备键合层；在所述键合层背对所述临时基板的一侧开设多个凹槽。
基于同样的发明构思，本申请还提供一种LED芯片的巨量转移方法，所述巨量转移方法包括：提供外延片，通过所述外延片得到多个LED芯片；制备所述的转移基板；将多个所述LED芯片容置于所述转移基板的凹槽内，去除所述外延片的衬底层；将所述外延片得到的多个所述LED芯片转移至背板上，多个所述LED芯片的第一电极和第二电极与所述背板电连接。
可选地，所述提供外延片，通过所述外延片得到多个LED芯片，包括：提供包括多个外延结构的外延片，在所述外延片上形成多个开口，每个所述开口对应一个所述外延结构设置，且将所述外延结构形成第一区域和第二区域；在所述外延片上形成多个开槽，每个所述开槽设置于相邻的两个所述外延结构之间；在所述外延片中位于所述第一区域的第二半导体层上形成金属层；形成覆盖所述外延片和所述金属层的绝缘保护层；部分去除所述金属层和第一半导体层处的所述绝缘保护层以部分露出所述金属层和所述第一半导体层；在露出所述金属层和所述第一半导体层的位置分别形成所述第一电极和所述第二电极，所述第一电极与所述金属层电连接，所述第二电极与所述第一半导体层电连接，以得到多个所述LED芯片。
可选地，多个所述外延结构呈阵列排布设置，每个所述外延结构包括依次层叠设置的所述衬底层、第一半导体层、多量子阱发光层以及第二半导体层，其中，所述第一半导体层设置于所述衬底层上，用于提供电子；所述第二半导体层设置于所述多量子阱发光层上，用于提供空穴；所述多量子阱发光层设置于所述第一半导体层与所述第二半导体层之间，用于提供场所让所述第一半导体层提供的电子与第二半导体层提供的空穴发生复合反应产生光子。
可选地，每个所述开口贯通所述第二半导体层和所述多量子阱发光层，并与所述第一半导体层相通，其中，所述第一区域的面积大于所述第二区域的面积。
可选地，每个所述开槽依次贯通所述第二半导体层、所述多量子阱发光层和所述第一半导体层，且所述开槽开设于一个所述外延结构的第二区域与相邻的另一所述外延结构的第一区域之间。
可选地，所述金属层的厚度为200-2000A，所述绝缘保护层的厚度为1-4um，所述第一电极和所述第二电极的厚度为1-4um。
 有益效果
本申请的所述转移基板采用挖孔式转移基板设计，该转移基板有利于弹性印模对所述LED芯片进行抓取转移。而且，所述LED芯片在所述转移基板的所述凹槽中不会出现偏移等情况，也使得弹性印模便于对所述LED芯片进行抓取转移，从而增加了所述LED芯片的巨量转移良率。
本申请的所述转移基板采用挖孔式转移基板设计，该转移基板中的氧化硅球体与LED芯片的接触面积小，对所述LED芯片无粘附力，从而使得弹性印模便于对所述LED芯片进行抓取转移。同时，所述LED芯片在所述转移基板的所述凹槽中不会出现偏移等情况，也使得弹性印模便于对所述LED芯片进行抓取转移，从而增加了所述LED芯片的巨量转移良率。
本申请的制备方法制备的所述转移基板采用挖孔式转移基板设计，该转移基板有利于弹性印模便于对所述LED芯片进行抓取转移。同时，所述LED芯片在所述转移基板的所述凹槽中不会出现偏移等情况，也使得弹性印模便于对所述LED芯片进行抓取转移，从而增加了所述LED芯片的巨量转移良率。
在本申请的LED芯片的巨量转移方法中，通过挖孔式的转移基板对所述LED芯片进行转移，并对所述转移基板中的胶材进行刻蚀，所述转移基板中的氧化硅球体对所述LED芯片无粘附力，从而使得弹性印模便于对所述LED芯片进行抓取转移。而且，所述LED芯片在所述转移基板的所述凹槽中不会出现偏移等情况，也使得弹性印模便于对所述LED芯片进行抓取转移，从而增加了所述LED芯片的巨量转移良率。
 附图说明
图1为本申请实施例公开的一种转移基板的结构示意图；
图2为本申请实施例公开的一种转移基板的制备方法的流程示意图；
图3为图2所示的制备方法中步骤S10形成的对应结构示意图；
图4为图2所示的制备方法中步骤S20形成的对应结构示意图；
图5为图2所示的制备方法中步骤S30形成的对应结构示意图；
图6为本申请实施例公开的一种LED芯片的巨量转移方法的流程示意图；
图7为图5所示巨量转移方法中步骤S100的流程示意图；
图8为图7所示的巨量转移方法中步骤S110形成的对应结构示意图；
图9为图7所示巨量转移方法中步骤S120形成的对应结构示意图；
图10为图7所示巨量转移方法中步骤S130形成的对应结构示意图；
图11为图7所示的巨量转移方法中步骤S140形成的对应结构示意图；
图12为图7所示的巨量转移方法中步骤S150形成的对应结构示意图；
图13为图7所示的巨量转移方法中步骤S160形成的对应结构示意图；
图14为图6所示的巨量转移方法中步骤S300形成的对应结构示意图；
图15为图6所示的巨量转移方法中步骤S400形成的对应结构示意图。
附图标记说明：
100-转移基板；
110-临时基板；
120-键合层；
121-凹槽；
200-外延片；
210-衬底层；
220-第一半导体层；
230-多量子阱发光层；
240-第二半导体层；
260-外延结构；
262-开口；
264-第一区域；
265-第二区域；
266-开槽；
300-LED芯片；
310-金属层；
320-绝缘保护层；
340-第一电极；
350-第二电极；
400-背板；
S10-S30-转移基板的制备方法的步骤；
S100-S400-LED芯片的巨量转移方法的步骤；
S110-S160-LED芯片的巨量转移方法中步骤S100的步骤。
 本发明的实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体地实施方式的目的，不是旨在于限制本申请。
微型发光二极管(Micro Light Emitting Diode，Micro LED)作为新一代的显示技术，与传统LED相比，其具有更高的光电效率、更高的亮度、更高的对比度以及更低的功耗。随着制程的成熟和价格的下降，近年来基于Micro LED芯片的相关显示产品越来越多，例如电视机、手机屏等。由于显示产品对于像素错误的容忍度较低，因此提升转移Micro LED芯片的良率对提高显示产品的良率尤为重要。目前，Micro LED芯片常用的转移方法包括：静电力、范德华力、磁力、激光选择转移、流体转移以及直接转移，其中，当前使用较多的转移方式就是范德华力，范德华力使用弹性印模对Micro LED芯片进行选择性拾取转移至衬底。然而，由于Micro LED芯片与衬底紧密结合，导致Micro LED芯片无法被弹性印模抓取，因此需要将Micro LED芯片与衬底的接触力弱化，从而使得Micro LED芯片能够被弹性印模抓取。因此，如何解决由于Micro LED芯片与衬底之间紧密结合导致Micro LED芯片无法方便地被弹性印模抓取是本领域技术人员亟需解决的问题。
基于此，本申请希望提供一种能够解决上述技术问题的方案，其可以解决由于Micro LED芯片与衬底紧密结合导致Micro LED芯片无法便捷地被弹性印模抓取的问题，其详细内容将在后续实施例中得以阐述。
本申请方案的详细阐述转移基板、所述转移基板的制备方法以及LED芯片的巨量转移方法。
请参阅图1，其为本申请实施例公开的一种转移基板的结构示意图。如图1所示，本申请提供一种转移基板100，其可采用挖孔式转移基板设计。所述转移基板100至少可以包括临时基板110以及键合层120。其中，所述键合层120设置于所述临时基板110上，所述键合层120背对所述临时基板110的一侧开设多个凹槽121，所述凹槽121用于容置LED芯片。
在本申请实施例中，所述LED芯片为微型LED芯片。
在示例性实施方式中，所述凹槽121的深度为3-6um，例如3um、4um、5um、6um、或其他数值。所述键合层120由多个氧化硅球体通过胶材键合形成的氧化硅层，其中，所述氧化硅球体的球径为10-100um，例如20um、30um、40um、50um、60um、或其他数值。
在示例性实施方式中，对多个氧化硅球体通过胶材均匀键合形成所述键合层120，所述键合层120沉积在所述临时基板110的一侧表面。在所述键合层120背对所述临时基本110的一侧通过光刻的方式形成所述凹槽121的图形。可以理解的是，所述凹槽121的刻蚀深度小于LED芯片的厚度。
综上所述，本申请的所述转移基板100采用挖孔式转移基板设计，该转移基板100中的氧化硅球体与LED芯片的接触面积小，对所述LED芯片300无粘附力，从而使得弹性印模便于对所述LED芯片300进行抓取转移。同时，所述LED芯片300在所述转移基板100的所述凹槽121中不会出现偏移等情况，也使得弹性印模便于对所述LED芯片300进行抓取转移，从而增加了所述LED芯片300的巨量转移良率。
请参阅图2，其为本申请实施例公开的一种转移基板的制备方法的流程示意图。所述转移基板的制备方法用于制备上述图1所示实施例中的转移基板，以实现便于弹性印模对LED芯片进行抓取并转移的效果。如图2所示，所述转移基板的制备方法至少包括以下步骤。
S10、提供一临时基板110。
具体的，请参阅图3，在本实施例中，所述临时基板110为后续生长所述转移基板100的其他层结构做准备。
S20、在所述临时基板110上制备键合层120。
具体的，请参阅图4，在本申请实施例中，在所述临时基板110的一侧表面上沉积氧化硅球体，对多个氧化硅球体通过胶材均匀键合形成所述键合层120。
在示例性实施方式中，所述氧化硅球体的球径可为10-100um，例如10um、20um、30um、40um、50um、60um、80um、或其他数值。
S30、在所述键合层120背对所述临时基板110的一侧开设多个凹槽121。
具体的，请参阅图5，在本申请实施方式中，在所述键合层120背对所述临时基本110的一侧通过光刻的方式形成所述凹槽121的图形，所述凹槽121用于容置LED芯片。所述凹槽121的深度为3-6um，例如3um、4um、5um、6um、或其他数值。其中，所述光刻为电感耦合等离子体(Inductive Coupled Plasma，ICP)干法刻蚀，所述ICP干法刻蚀的刻蚀气体为CF4/O2/Ar，所述凹槽121的刻蚀深度为3-6um，例如3um、4um、5um、6um、或其他数值。可以理解的是，所述凹槽121的刻蚀深度小于LED芯片的厚度。
综上所述，本申请的制备方法制备的所述转移基板100采用挖孔式转移基板设计，该转移基板100中的氧化硅球体与LED芯片的接触面积小，对所述LED芯片300无粘附力，从而使得弹性印模便于对所述LED芯片300进行抓取转移。同时，所述LED芯片300在所述转移基板100的所述凹槽121中不会出现偏移等情况，也使得弹性印模便于对所述LED芯片300进行抓取转移，从而增加了所述LED芯片300的巨量转移良率。
请参阅图6，其为本申请实施例公开的一种LED芯片的巨量转移方法的流程示意图。在本申请实施例中，所述巨量转移方法用于对LED芯片进行巨量转移，以达到增加LED芯片巨量转移的良率的效果。请一并参阅图7至图15所示，在本申请实施方式中，所述LED芯片的巨量转移方法至少可以包括以下步骤。
S100、提供外延片200，通过所述外延片200得到多个LED芯片300。
请参阅图7，在本实施方式中，所述步骤S100至少包括以下步骤。
S110、提供包括多个外延结构260的外延片200，在所述外延片200上形成多个开口262，每个所述开口262对应一个所述外延结构260设置，且将所述外延结构形成第一区域和第二区域。
具体地，在本申请实施方式中，如图8所示，所述外延片200包括依次层叠设置的衬底层210、第一半导体层220、多量子阱发光层230以及第二半导体层240。其中，所述第一半导体层220设置于所述衬底层210上，用于提供电子，所述第二半导体层240设置于所述多量子阱发光层230上，用于提供空穴，从而与所述第一半导体层220提供的电子发生复合反应产生光子。所述多量子阱发光层230设置于所述第一半导体层220与所述第二半导体层240之间，用于提供场所让所述第一半导体层220提供的电子与第二半导体层240提供的空穴发生复合反应产生光子。
在本申请实施方式中，所述第一半导体层220为N型半导体材料，例如，N型氮化镓（GaN）。所述第二半导体层240为P型半导体材料，例如，P型氮化镓（GaN）。
在示例性实施方式中，所述外延片200包括多个外延结构260，多个外延结构260呈阵列排布设置，每个外延结构260也包括依次层叠设置的衬底层210、第一半导体层220、多量子阱发光层230以及第二半导体层240。所述外延片200开设形成多个开口262，每个开口262对应一个所述外延结构260设置。在本申请实施例中，所述开口262贯通所述第二半导体层240和所述多量子阱发光层230直至所述第一半导体层220，即所述开口262与所述第一半导体层220相通，并形成以所述第一半导体层220为底部的凹槽，从而将所述外延结构260形成第一区域264和第二区域265，其中，第一区域264的面积大于所述第二区域265的面积。
在示例性实施方式中，所述外延片200上的多个开口262可通过光刻形成，所述外延片200上的多个开口262形成了第一图形。在本申请实施例中，所述第一图形可为MESA（台阶刻蚀）图形。所述光刻为干法刻蚀，所述干法刻蚀的刻蚀气体为BCl3/Cl2。
S120、在所述外延片200上形成多个开槽266，每个所述开槽266设置于相邻的两个所述外延结构260之间。
具体地，在本申请实施方式中，如图9所示，在所述外延片200上开设形成多个开槽266，每个所述开槽266设置于相邻的两个所述外延结构260之间。所述开槽266依次贯通所述第二半导体层240、所述多量子阱发光层230和所述第一半导体层220。也可以理解为，所述开槽266开设于一个外延结构260的第二区域265与相邻的另一个外延结构260的第一区域264之间。
在示例性实施方式中，所述外延片200上的多个开槽266可通过光刻形成，所述外延片200上的多个开槽266形成了第二图形。例如，通过使用干法刻蚀机台刻蚀贯穿所述第二半导体层240、所述多量子阱发光层230和所述第一半导体层220至所述衬底层210，即所述开槽266与所述衬底层210相通。在本申请实施例中，所述第二图形可为ISO（氮化镓深刻蚀）图形。所述光刻为干法刻蚀，所述干法刻蚀的刻蚀气体为BCl3/Cl2。
在本申请实施方式中，所述刻蚀深度为4-8um，例如4um、5um、6um、7um、或其他数值。
S130、在所述外延片200中位于所述第一区域264的第二半导体层240上形成金属层310。
具体地，在示例性实施方式中，如图10所示，所述开口262贯通所述第二半导体层240和所述多量子阱发光层230直至所述第一半导体层220，从而将所述外延结构260形成第一区域264和第二区域265，在所述外延片200中位于所述第一区域264的第二半导体层240上形成氧化铟锡（Indium tin oxide，ITO）层310。此时，所述金属层310与所述第二半导体层240电连接。
在示例性实施方式中，所述金属层310的厚度可为200-2000A，例如200A、300A、400A、500A、800A、1500A、1800A、或其他数值。所述金属层310可由氧化铟锡（Indium tin oxide，ITO）制成。
S140、形成覆盖所述外延片200和所述金属层310的绝缘保护层320。
具体地，在本申请实施方式中，如图11所示，所述绝缘保护层320可为氧化硅与氮化硅的叠层，例如，所述绝缘保护层320还可为分布式布拉格反射镜（Distributed Bragg Reflection，DBR）。示例性地，在所述外延片200和所述金属层310上通过蒸镀氧化硅与氮化硅的叠层（DBR）形成所述绝缘保护层320。
在示例性实施方式中，所述绝缘保护层320的厚度可为1-4um，例如1um、1.5um、2um、3.5um、4um、或其他数值。
S150、部分去除所述金属层310和所述第一半导体层220处的所述绝缘保护层320以部分露出所述金属层310和所述第一半导体层220。
具体地，在本申请实施方式中，如图12所示，将所述绝缘保护层320部分去除指的是将所述金属层310和所述第一半导体层220处的绝缘保护层320部分去除，以部分露出所述金属层310和所述第一半导体层220。
在示例性实施方式中，所述绝缘保护层320可使用干法刻蚀机台通过但不限于干法蚀刻的方式部分去除。其中，所述干法刻蚀的刻蚀气体可为CF4/O2/Ar，所述刻蚀深度需要贯穿绝缘保护层320。
S160、在露出所述金属层310和所述第一半导体层220的位置分别形成第一电极340和第二电极350，所述第一电极340与所述金属层310电连接，所述第二电极350与所述第一半导体层220电连接，以得到多个LED芯片300。
具体地，在本申请实施方式中，如图13所示，在部分去除所述金属层310和所述第一半导体层220处的所述绝缘保护层320后，所述金属层310和所述第一半导体层220部分露出所述绝缘保护层320，则在露出所述金属层310和所述第一半导体层220的位置分别形成第一电极340和第二电极350。其中，所述第一电极与所述金属层电连接，所述第二电极与所述第一半导体层电连接，且外露于所述绝缘保护层320。例如，本步骤中的第一电极和第二电极作为Bonding用的金属层，得到了完整的微型LED芯片300。
在示例性实施方式中，在所述绝缘保护层320上可采用负胶光刻电极图形，使用蒸镀机台蒸镀电极图形，并通过蓝膜剥离去胶后得到所述第一电极和第二电极，以制备得到多个LED芯片300。其中，所述第一电极340和所述第二电极350的厚度可为1-4um，例如1um、2um、3um、4um、或其他数值。
S200、制备转移基板100。
请参阅图2至图5所示，在本实施方式中，所述步骤S200至少包括以下步骤。
S10、提供一临时基板110。
具体的，请参阅图3，在本实施例中，所述临时基板110为后续生长所述转移基板100的其他层结构做准备。
S20、在所述临时基板110上制备键合层120。
具体的，请参阅图4，在本申请实施例中，在所述临时基板110的一侧表面上沉积氧化硅球体，对多个氧化硅球体通过胶材均匀键合形成所述键合层120。
在示例性实施方式中，所述氧化硅球体的球径可为10-100um，例如10um、20um、30um、40um、50um、60um、80um、或其他数值。
S30、在所述键合层120背对所述临时基板110的一侧开设多个凹槽121。
具体的，请参阅图5，在本申请实施方式中，在所述键合层120背对所述临时基本110的一侧通过光刻的方式形成所述凹槽121的图形，所述凹槽121用于容置LED芯片。所述凹槽121的深度为3-6um，例如3um、4um、5um、6um、或其他数值。其中，所述光刻为电感耦合等离子体(Inductive Coupled Plasma，ICP)干法刻蚀，所述ICP干法刻蚀的刻蚀气体为CF4/O2/Ar，所述凹槽121的刻蚀深度为3-6um，例如3um、4um、5um、6um、或其他数值。可以理解的是，所述凹槽121的刻蚀深度小于LED芯片的厚度。
S300、将多个所述LED芯片300容置于所述转移基板100的凹槽121内，去除所述衬底层210。
具体地，在本申请实施方式中，如图14所示，对所述衬底层210进行研磨抛光，将所述LED芯片300的第一电极340和第二电极350键合胶材，将附着胶材的所述LED芯片300容置于所述转移基板100对应的凹槽121内，则所述LED芯片300的第一电极340和第二电极350分别与所述凹槽121的底部键合，并通过激光剥离的方式将所述衬底层210移除。其中，所述凹槽121的尺寸均大于所述第一电极340和第二电极350的尺寸。
S400、将所述外延片200得到的所述LED芯片300转移至背板400上，多个所述LED芯片300的第一电极340和所述第二电极350与所述背板400电连接。
具体地，在本申请实施方式中，如图15所示，将所述LED芯片300与所述转移基板100中的胶材进行刻蚀，通过弹性印模将所述LED芯片300转移至所述背板400上，多个所述LED芯片300的第一电极340和所述第二电极350与所述背板400电连接。
在示例性实施方式中，所述刻蚀方法为干法刻蚀，所述干法刻蚀的刻蚀气体为CF4/O2/Ar。
综上所述，在本申请的LED芯片的巨量转移方法中，通过挖孔式的转移基板100对所述LED芯片300进行转移，并对所述转移基板100中的胶材进行刻蚀，所述转移基板100中的氧化硅球体对所述LED芯片300无粘附力，从而使得弹性印模便于对所述LED芯片300进行抓取转移。而且，所述LED芯片300在所述转移基板100的所述凹槽121中不会出现偏移等情况，也使得弹性印模便于对所述LED芯片300进行抓取转移，从而增加了所述LED芯片300的巨量转移良率。
应当理解的是，本申请的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本申请所附权利要求的保护范围。

Claims (20)

  1. 一种转移基板，其中，所述转移基板包括：临时基板以及键合层，其中，所述键合层设置于所述临时基板上，所述键合层背对所述临时基板的一侧开设多个凹槽，所述凹槽用于容置LED芯片。
  2. 如权利要求1所述的转移基板，其中，所述键合层是由多个氧化硅球体通过胶材键合形成的氧化硅层，其中，所述氧化硅球体的球径为10-100um。
  3. 如权利要求1所述的转移基板，其中，所述凹槽的刻蚀深度小于所述LED芯片的厚度。
  4. 一种转移基板的制备方法，用于制备如权利要求1所述的转移基板，其中，所述制备方法包括：
    提供一临时基板；
    在所述临时基板上制备键合层；
    在所述键合层背对所述临时基板的一侧开设多个凹槽。
  5. 如权利要求4所述的转移基板的制备方法，其中，所述键合层是由多个氧化硅球体通过胶材键合形成的氧化硅层，其中，所述氧化硅球体的球径为10-100um。
  6. 如权利要求4所述的转移基板的制备方法，其中，所述凹槽的刻蚀深度小于所述LED芯片的厚度。
  7. 一种LED芯片的巨量转移方法，其中，所述巨量转移方法包括：
    提供外延片，通过所述外延片得到多个LED芯片；
    制备如权利要求1所述的转移基板；
    将多个所述LED芯片容置于所述转移基板的凹槽内，去除所述外延片的衬底层；
    将所述外延片得到的多个所述LED芯片转移至背板上，多个所述LED芯片的第一电极和第二电极与所述背板电连接。
  8. 如权利要求7所述的LED芯片的巨量转移方法，其中，所述转移基板的键合层是由多个氧化硅球体通过胶材键合形成的氧化硅层，其中，所述氧化硅球体的球径为10-100um。
  9. 如权利要求7所述的LED芯片的巨量转移方法，其中，所述凹槽的刻蚀深度小于所述LED芯片的厚度。
  10. 如权利要求7所述的LED芯片的巨量转移方法，其中，所述提供外延片，通过所述外延片得到多个LED芯片，包括：
    提供包括多个外延结构的外延片，在所述外延片上形成多个开口，每个所述开口对应一个所述外延结构设置，且将所述外延结构形成第一区域和第二区域；
    在所述外延片上形成多个开槽，每个所述开槽设置于相邻的两个所述外延结构之间；
    在所述外延片中位于所述第一区域的第二半导体层上形成金属层；
    形成覆盖所述外延片和所述金属层的绝缘保护层；
    部分去除所述金属层和第一半导体层处的所述绝缘保护层以部分露出所述金属层和所述第一半导体层；
    在露出所述金属层和所述第一半导体层的位置分别形成所述第一电极和所述第二电极，所述第一电极与所述金属层电连接，所述第二电极与所述第一半导体层电连接，以得到多个所述LED芯片。
  11. 如权利要求8所述的LED芯片的巨量转移方法，其中，所述提供外延片，通过所述外延片得到多个LED芯片，包括：
    提供包括多个外延结构的外延片，在所述外延片上形成多个开口，每个所述开口对应一个所述外延结构设置，且将所述外延结构形成第一区域和第二区域；
    在所述外延片上形成多个开槽，每个所述开槽设置于相邻的两个所述外延结构之间；
    在所述外延片中位于所述第一区域的第二半导体层上形成金属层；
    形成覆盖所述外延片和所述金属层的绝缘保护层；
    部分去除所述金属层和第一半导体层处的所述绝缘保护层以部分露出所述金属层和所述第一半导体层；
    在露出所述金属层和所述第一半导体层的位置分别形成所述第一电极和所述第二电极，所述第一电极与所述金属层电连接，所述第二电极与所述第一半导体层电连接，以得到多个所述LED芯片。
  12. 如权利要求9所述的LED芯片的巨量转移方法，其中，所述提供外延片，通过所述外延片得到多个LED芯片，包括：
    提供包括多个外延结构的外延片，在所述外延片上形成多个开口，每个所述开口对应一个所述外延结构设置，且将所述外延结构形成第一区域和第二区域；
    在所述外延片上形成多个开槽，每个所述开槽设置于相邻的两个所述外延结构之间；
    在所述外延片中位于所述第一区域的第二半导体层上形成金属层；
    形成覆盖所述外延片和所述金属层的绝缘保护层；
    部分去除所述金属层和第一半导体层处的所述绝缘保护层以部分露出所述金属层和所述第一半导体层；
    在露出所述金属层和所述第一半导体层的位置分别形成所述第一电极和所述第二电极，所述第一电极与所述金属层电连接，所述第二电极与所述第一半导体层电连接，以得到多个所述LED芯片。
  13. 如权利要求10所述的LED芯片的巨量转移方法，其中，多个所述外延结构呈阵列排布设置，每个所述外延结构包括依次层叠设置的所述衬底层、第一半导体层、多量子阱发光层以及第二半导体层，其中，所述第一半导体层设置于所述衬底层上，用于提供电子；所述第二半导体层设置于所述多量子阱发光层上，用于提供空穴；所述多量子阱发光层设置于所述第一半导体层与所述第二半导体层之间，用于提供场所让所述第一半导体层提供的电子与第二半导体层提供的空穴发生复合反应产生光子。
  14. 如权利要求11所述的LED芯片的巨量转移方法，其中，多个所述外延结构呈阵列排布设置，每个所述外延结构包括依次层叠设置的所述衬底层、第一半导体层、多量子阱发光层以及第二半导体层，其中，所述第一半导体层设置于所述衬底层上，用于提供电子；所述第二半导体层设置于所述多量子阱发光层上，用于提供空穴；所述多量子阱发光层设置于所述第一半导体层与所述第二半导体层之间，用于提供场所让所述第一半导体层提供的电子与第二半导体层提供的空穴发生复合反应产生光子。
  15. 如权利要求12所述的LED芯片的巨量转移方法，其中，多个所述外延结构呈阵列排布设置，每个所述外延结构包括依次层叠设置的所述衬底层、第一半导体层、多量子阱发光层以及第二半导体层，其中，所述第一半导体层设置于所述衬底层上，用于提供电子；所述第二半导体层设置于所述多量子阱发光层上，用于提供空穴；所述多量子阱发光层设置于所述第一半导体层与所述第二半导体层之间，用于提供场所让所述第一半导体层提供的电子与第二半导体层提供的空穴发生复合反应产生光子。
  16. 如权利要求13所述的LED芯片的巨量转移方法，其中，每个所述开口贯通所述第二半导体层和所述多量子阱发光层，并与所述第一半导体层相通，其中，所述第一区域的面积大于所述第二区域的面积。
  17. 如权利要求16所述的LED芯片的巨量转移方法，其中，每个所述开槽依次贯通所述第二半导体层、所述多量子阱发光层和所述第一半导体层，且所述开槽开设于一个所述外延结构的第二区域与相邻的另一所述外延结构的第一区域之间。
  18. 如权利要求10所述的LED芯片的巨量转移方法，其中，所述金属层的厚度为200-2000A，所述绝缘保护层的厚度为1-4um，所述第一电极和所述第二电极的厚度为1-4um。
  19. 如权利要求11所述的LED芯片的巨量转移方法，其中，所述金属层的厚度为200-2000A，所述绝缘保护层的厚度为1-4um，所述第一电极和所述第二电极的厚度为1-4um。
  20. 如权利要求12所述的LED芯片的巨量转移方法，其中，所述金属层的厚度为200-2000A，所述绝缘保护层的厚度为1-4um，所述第一电极和所述第二电极的厚度为1-4um。
PCT/CN2022/124419 2021-10-28 2022-10-10 转移基板、制备方法和led芯片的巨量转移方法 WO2023071765A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111260882.1 2021-10-28
CN202111260882.1A CN116053361A (zh) 2021-10-28 2021-10-28 转移基板、制备方法和led芯片的巨量转移方法

Publications (1)

Publication Number Publication Date
WO2023071765A1 true WO2023071765A1 (zh) 2023-05-04

Family

ID=86116874

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/124419 WO2023071765A1 (zh) 2021-10-28 2022-10-10 转移基板、制备方法和led芯片的巨量转移方法

Country Status (2)

Country Link
CN (1) CN116053361A (zh)
WO (1) WO2023071765A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231968A (zh) * 2017-12-11 2018-06-29 厦门市三安光电科技有限公司 微发光二极管及其转移方法
CN108364971A (zh) * 2018-03-20 2018-08-03 厦门市三安光电科技有限公司 微发光元件、微发光二极管及其转印方法
CN110581203A (zh) * 2019-08-09 2019-12-17 康佳集团股份有限公司 一种Micro-LED微元件的巨量转移方法及装置
CN111430404A (zh) * 2020-04-26 2020-07-17 厦门乾照半导体科技有限公司 可用于微转移的微元件及其制作和转移方法、显示装置
JP2021019082A (ja) * 2019-07-19 2021-02-15 株式会社ジャパンディスプレイ 転写用基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231968A (zh) * 2017-12-11 2018-06-29 厦门市三安光电科技有限公司 微发光二极管及其转移方法
CN108364971A (zh) * 2018-03-20 2018-08-03 厦门市三安光电科技有限公司 微发光元件、微发光二极管及其转印方法
JP2021019082A (ja) * 2019-07-19 2021-02-15 株式会社ジャパンディスプレイ 転写用基板
CN110581203A (zh) * 2019-08-09 2019-12-17 康佳集团股份有限公司 一种Micro-LED微元件的巨量转移方法及装置
CN111430404A (zh) * 2020-04-26 2020-07-17 厦门乾照半导体科技有限公司 可用于微转移的微元件及其制作和转移方法、显示装置

Also Published As

Publication number Publication date
CN116053361A (zh) 2023-05-02

Similar Documents

Publication Publication Date Title
CN110034218B (zh) 一种微型led芯片和显示面板
CN110911537B (zh) 共阴极led芯片及其制作方法
CN108878468B (zh) 一种显示基板及其制作方法、显示面板、显示装置
CN211480078U (zh) 一种led芯片、生长基板、led芯片转移装置
CN113299803B (zh) 一种Micro LED芯片单体器件的制备方法、显示模块及显示装置
TW202042287A (zh) 用於表面貼裝微型led流體組裝的發光顯示基板及製備方法
CN111129062B (zh) Led显示模组、led显示屏及制作方法
WO2023082971A1 (zh) 芯片转移方法、显示面板及显示装置
US11569116B2 (en) Light emitting diode
CN113451352A (zh) 芯片弱化结构及其制作方法、巨量转移方法、显示面板
WO2023071765A1 (zh) 转移基板、制备方法和led芯片的巨量转移方法
US20230154903A1 (en) Light-emitting diode (led) chip assembly and prepraing method thereof, and preparing method of display panel
TW202349745A (zh) 製造微型元件的方法
CN113745376B (zh) 发光芯片处理方法、发光芯片组件、显示装置及发光装置
CN214898480U (zh) 一种Micro LED芯片单体器件、显示模块及显示装置
CN116169152A (zh) 发光芯片的转移方法、显示面板和显示装置
TW202315158A (zh) 發光二極體晶片及其製造方法
CN112133719A (zh) 一种微型发光二极管的制造方法
WO2023220993A1 (zh) 发光芯片及其制备方法、发光基板、显示装置
CN112510029B (zh) 一种rgb-led芯片及其制造方法和应用
US20230395749A1 (en) Micro light-emitting element, micro light-emitting array, transfer method, and display
CN219716889U (zh) 一种倒装mini LED芯片
CN113690349B (zh) 防断裂发光二极管芯片及其制造方法
CN113471339B (zh) 一种Micro-LED芯片的巨量转移方法
CN109920887B (zh) 一种发光二极管芯片及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22885644

Country of ref document: EP

Kind code of ref document: A1