WO2023220993A1 - 发光芯片及其制备方法、发光基板、显示装置 - Google Patents

发光芯片及其制备方法、发光基板、显示装置 Download PDF

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Publication number
WO2023220993A1
WO2023220993A1 PCT/CN2022/093680 CN2022093680W WO2023220993A1 WO 2023220993 A1 WO2023220993 A1 WO 2023220993A1 CN 2022093680 W CN2022093680 W CN 2022093680W WO 2023220993 A1 WO2023220993 A1 WO 2023220993A1
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Prior art keywords
light
emitting
silicon
sub
based substrate
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PCT/CN2022/093680
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English (en)
French (fr)
Inventor
王明星
李伟
闫华杰
孙倩
袁广才
董学
齐琪
梁轩
王飞
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京东方科技集团股份有限公司
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Priority to CN202280001270.7A priority Critical patent/CN117480612A/zh
Priority to PCT/CN2022/093680 priority patent/WO2023220993A1/zh
Publication of WO2023220993A1 publication Critical patent/WO2023220993A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to light-emitting chips and preparation methods thereof, light-emitting substrates, and display devices.
  • Micro-sized inorganic light-emitting diode display is a new display technology that has developed rapidly in recent years.
  • Micro-sized inorganic light-emitting diode chips have many advantages such as small size, controllable luminous wavelength, high luminous efficiency, long service life, and no pollution of the luminescent materials to the environment.
  • the application of light-emitting diodes in displays has developed.
  • An embodiment of the present disclosure provides a light-emitting chip.
  • the light-emitting chip includes:
  • a silicon-based substrate including a plurality of sub-pixel openings
  • a plurality of light-emitting devices are arranged on one side of the silicon-based substrate; the light-emitting devices correspond to the sub-pixel openings one-to-one, and the orthographic projection of the light-emitting devices on the silicon-based substrate overlaps with the sub-pixel openings;
  • a plurality of photoluminescent light films located within at least part of the sub-pixel openings.
  • the light-emitting chip further includes:
  • the microlens is located on the side of the silicon-based substrate away from the light-emitting device, and the microlens covers the sub-pixel opening.
  • the light-emitting chip further includes:
  • the first distributed Bragg reflection structure is located between the silicon-based substrate and the microlens and covers at least a plurality of photoluminescent films; it is used to transmit the light emitted from each photoluminescent film and reflect the light emitted from the light-emitting device.
  • the orthographic projection of the first distributed Bragg reflection structure on the silicon-based substrate does not overlap with the sub-pixel opening.
  • the light-emitting chip further includes:
  • the filter film is located on the side of the microlens facing away from the silicon-based substrate.
  • the light-emitting device is a micro-sized inorganic light-emitting diode.
  • the light-emitting device includes: N-type gallium nitride, a multi-quantum well layer, and P-type gallium nitride stacked on one side of the silicon-based substrate;
  • the N-type semi-gallium nitrides of multiple light-emitting devices are integrally connected.
  • the light-emitting chip further includes:
  • a plurality of first connection electrodes are located on the side of the P-type gallium nitride away from the multi-quantum well layer; the first connection electrodes are electrically connected to the P-type gallium nitride in a one-to-one correspondence, and the first connection electrodes are located in the orthographic projection of the silicon-based substrate Into the orthographic projection of P-type gallium nitride on the silicon-based substrate;
  • the second connection electrode is electrically connected to the N-type gallium nitride in the area outside the light-emitting device and on the side of the N-type gallium nitride away from the silicon-based substrate;
  • the protective layer located on the side of the first connection electrode and the second connection electrode away from the silicon-based substrate, includes a plurality of first via holes that run through its thickness and expose the first connection electrode, and a plurality of first via holes that run through its thickness and expose the second connection electrode. Two vias;
  • a plurality of binding pads located on the side of the protective layer away from the first connection electrode and the second connection electrode, including: a first binding pad electrically connected to the first connection electrode in a one-to-one correspondence through the first via hole, and a second binding pad through the second via hole.
  • the via hole is electrically connected to the second bonding pad of the second connection electrode.
  • the plurality of light-emitting devices included in the light-emitting chip are all blue light-emitting devices
  • the plurality of sub-pixel openings include: a red sub-pixel opening, a blue sub-pixel opening and a green sub-pixel opening;
  • Multiple photoluminescent color films include: a red quantum dot color film that absorbs red light emitted from blue light, and a green quantum dot color film that absorbs green light emitted from blue light; the red quantum dot color film is located in the red sub-pixel opening, and the green quantum dot color film is located in the red sub-pixel opening. Located in the green sub-pixel opening.
  • the plurality of light-emitting devices included in the light-emitting chip are all ultraviolet light-emitting devices
  • the plurality of sub-pixel openings include: a red sub-pixel opening, a blue sub-pixel opening and a green sub-pixel opening;
  • Multiple photoluminescent films include: red quantum dot color films that absorb ultraviolet light and emit red light, blue quantum dot color films that absorb ultraviolet light and emit blue light, and green quantum dot color films that absorb ultraviolet light and emit green light; red light quantum dot color films The point color film is located at the red sub-pixel opening, the blue light quantum dot color film is located at the blue sub-pixel opening, and the green light quantum dot color film is located at the green sub-pixel opening.
  • the thickness of the silicon-based substrate is greater than or equal to 5 microns and less than or equal to 50 microns.
  • the distance between the light-emitting device and the photoluminescent film is greater than or equal to 0.1 micrometer and less than or equal to 50 micrometer.
  • the orthographic projection of the light-emitting device on the silicon-based substrate falls within the sub-pixel opening.
  • An embodiment of the present disclosure provides a method for preparing a light-emitting chip.
  • the method includes:
  • a photoluminescent light film is formed within at least part of the sub-pixel opening.
  • growing a light-emitting device film layer on a silicon-based substrate specifically includes:
  • N-type gallium nitride layer, a multi-quantum well layer, a P-type gallium nitride layer, and a first connection electrode layer are sequentially grown on one side of the silicon-based substrate;
  • the light-emitting device film layer Before performing a patterning process on the light-emitting device film layer to form multiple light-emitting devices, it also includes:
  • Perform a patterning process on the film layer of the light-emitting device to form multiple light-emitting devices including:
  • the light-emitting device film layer After performing a patterning process on the light-emitting device film layer to form multiple light-emitting devices, it also includes:
  • a bonding pad layer is formed on the side of the protective layer facing away from the first connection electrode and the second connection electrode, and a patterning process is performed on the bonding pad layer to form a first bonding layer that is electrically connected to the first connection electrode through the first via hole. pad and a second bonding pad electrically connected to the second connection electrode through the second via hole.
  • the method before forming sub-pixel openings corresponding to the light-emitting devices on the silicon-based substrate, the method further includes:
  • the method After forming the filter film on the side of the microlens facing away from the silicon-based substrate, the method also includes:
  • bonding the first substrate on the side of the first binding pad and the second binding pad away from the protective layer specifically includes:
  • Peeling off the first substrate specifically includes:
  • the first substrate is peeled off from the first binding pad and the second binding pad using a laser dissociation process.
  • sub-pixel openings corresponding to the light-emitting devices are formed on the silicon-based substrate, specifically including:
  • a dry etching process or a wet etching process is used on the thinned silicon-based substrate to form sub-pixel openings corresponding to the light-emitting devices.
  • a light-emitting substrate provided by an embodiment of the present disclosure includes a plurality of light-emitting chips provided by an embodiment of the present disclosure arranged in an array.
  • a display device provided by an embodiment of the present disclosure includes a light-emitting substrate provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic structural diagram of a light-emitting chip provided by an embodiment of the present disclosure
  • Figure 2 is a top view of a light-emitting chip provided by an embodiment of the present disclosure
  • Figure 3 is a top view of a silicon-based substrate provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of another light-emitting chip provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of another light-emitting chip provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of another light-emitting chip provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of another light-emitting chip provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic flow chart of a method for preparing a light-emitting chip provided by an embodiment of the present disclosure
  • 9a to 9h are schematic flow diagrams of another method for manufacturing a light-emitting chip provided by an embodiment of the present disclosure.
  • the light-emitting chip includes:
  • a silicon-based substrate 1 includes a plurality of sub-pixel openings 2;
  • a plurality of light-emitting devices 3 are arranged on one side of the silicon-based substrate 1; the light-emitting devices 3 correspond to the sub-pixel openings 2 one-to-one, and the orthographic projection of the light-emitting devices 3 on the silicon-based substrate 1 overlaps with the sub-pixel opening 2;
  • a plurality of photoluminescent films 4 are located in at least part of the sub-pixel openings 2 .
  • the photoluminescent color film is disposed in the sub-pixel opening of the silicon-based substrate, that is, the silicon-based substrate is used as a light-shielding black matrix, thereby eliminating the need for an additional layer on the side of the silicon-based substrate away from the light-emitting device.
  • Providing a black matrix layer can save the light-emitting chip preparation process and save costs.
  • the process of forming sub-pixel openings on the silicon-based substrate is simple and can avoid increasing the difficulty of preparing sub-pixel openings.
  • the light-emitting chip provided by the embodiment of the present disclosure will light-induced
  • the luminescent light film is arranged in the sub-pixel opening of the silicon-based substrate, instead of the photoluminescent light film being arranged in the additional black matrix layer opening on the side of the silicon-based substrate away from the light-emitting device, which can reduce photoluminescence.
  • the distance between the luminous film and the light-emitting device avoids crosstalk problems between different sub-pixels.
  • the light-emitting chip provided by the embodiment of the present disclosure includes a plurality of light-emitting devices formed on one side of the silicon-based substrate. That is, the light-emitting devices included in the light-emitting chip all emit the same color, and then the color conversion is achieved through a photoluminescent color film.
  • the light-emitting chip can achieve full color, thereby reducing the difficulty of transferring the light-emitting chip.
  • Multiple light-emitting devices are formed on one side of the silicon-based substrate, eliminating the need to grow each film layer of the light-emitting device on a temporary substrate, and then transferring each film layer of the light-emitting device to a substrate with higher support strength, which can further save light. Chip preparation process and cost savings.
  • the length and width of the light-emitting device are smaller than the length and width of the sub-pixel opening, and the area of the light-emitting device is smaller than the area of the sub-pixel opening.
  • the width h2 of the light-emitting device is smaller than the width h1 of the sub-pixel opening, and the orthographic projection of the light-emitting device 3 on the silicon-based substrate 1 falls into the sub-pixel opening 2 .
  • the light-emitting device is a micro-sized inorganic light-emitting diode.
  • the micro-sized inorganic light-emitting diode may be, for example, a mini-light emitting diode (Mini Light Emitting Diode, Mini-LED) or a micro-light emitting diode (Micro Light Emitting Diode, Micro-LED).
  • Mini-LED Mini Light Emitting Diode
  • Micro-LED Micro Light Emitting Diode
  • Mini-LED and Micro-LED are small in size and high in brightness, and can be widely used in display devices or their backlight modules.
  • the typical size (such as length) of Micro-LED is less than 100 microns; the typical size (such as length) of Mini-LED is 80 microns to 350 microns.
  • the light-emitting device 3 includes: N-type gallium nitride (N-GaN) 5 and a multi-quantum well layer (MQW) 6 stacked on one side of the silicon-based substrate 1 , P-type gallium nitride (P-GaN)7;
  • the N-type semi-gallium nitrides of multiple light-emitting devices are integrally connected.
  • the entire layer of N-type semi-gallium nitride in the light-emitting chip is arranged.
  • the light-emitting chip includes three light-emitting devices 3 .
  • the area corresponding to the pattern of the N-type gallium nitride and the multi-quantum well layer in the light-emitting device 3 is the light-emitting area 22 of the light-emitting chip, and the area outside the light-emitting device 3 is the non-light-emitting area 12 of the light-emitting chip. That is, the N-type semi-gallium nitride extends to the non-emitting area and is connected integrally.
  • the thickness of N-GaN 5 in the non-emitting region 12 is smaller than the thickness of N-GaN 5 in the light-emitting device 3 region. That is, N-GaN is also subjected to patterning processes such as etching, but the N-GaN in the non-emitting area is not completely removed.
  • the silicon-based substrate includes three sub-pixel openings.
  • the plurality of sub-pixel openings 2 include: red sub-pixel openings R, blue sub-pixel openings B and green sub-pixel openings G.
  • the length and/or width of the sub-pixel opening is greater than or equal to 10 microns and less than or equal to 100 microns; the length and width of the sub-pixel opening can be set to 50 um, for example.
  • the size of the sub-pixel opening is not larger than the size of its corresponding light-emitting area. For example, it can be set so that the length and width of the sub-pixel opening are both smaller than the length and width of the light-emitting area, that is, the area of the sub-pixel opening is smaller than the area of the light-emitting area, and The orthographic projection of the sub-pixel opening falls into the light-emitting area.
  • the light-emitting chip further includes: a buffer layer 8 located between the silicon-based substrate 1 and the N-type gallium nitride 5; U-shaped gallium nitride (U-GaN)9 between.
  • a buffer layer and a U-GaN leveling layer are provided.
  • the buffer layer is a multi-layer epitaxial structure, and the buffer layer includes, for example, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and gallium nitride (GaN) stacked in sequence.
  • AlN aluminum nitride
  • AlGaN aluminum gallium nitride
  • GaN gallium nitride
  • U-shaped gallium nitride is used to form a high-quality GaN layer to sequentially grow N-GaN, MQW, and P-GaN.
  • the total thickness of the buffer layer and U-GaN is greater than or equal to 0.1 microns and less than or equal to 10 microns. That is, the distance between the light-emitting device and the photoluminescent film is greater than or equal to 0.1 micron and less than or equal to 50 micron.
  • the photoluminescent color film is arranged in the sub-pixel opening of the silicon-based substrate, so that the distance between the photoluminescence color film and the light-emitting device is small and can avoid interference between different sub-pixels. Crosstalk problem.
  • the light-emitting chip further includes:
  • a plurality of first connection electrodes 10 are located on the side of the P-type gallium nitride 7 away from the multi-quantum well layer 6; the first connection electrodes 19 are electrically connected to the P-type gallium nitride 7 in a one-to-one correspondence.
  • the first connection electrodes 10 are on the silicon base.
  • the orthographic projection of the substrate 1 falls within the orthographic projection of the P-type gallium nitride 7 on the silicon-based substrate 1;
  • the second connection electrode 11 is electrically connected to the N-type gallium nitride 5 in the area outside the light-emitting device 3 and on the side of the N-type gallium nitride 5 facing away from the silicon-based substrate;
  • the protective layer 13 is located on the side of the first connection electrode 10 and the second connection electrode 11 away from the silicon-based substrate 1 , and includes a plurality of first via holes 14 that run through its thickness and expose the first connection electrode 10 and a plurality of first via holes 14 that run through its thickness and expose the first connection electrode 10 . the second via hole 15 of the second connection electrode 11;
  • a plurality of binding pads 16 are located on the side of the protective layer 13 away from the first connection electrode 10 and the second connection electrode 11 , including: first binding pads that are electrically connected to the first connection electrode 10 through the first via holes 14 in a one-to-one correspondence. pad 17, and a second bonding pad 18 electrically connected to the second connection electrode 11 through the second via hole 15.
  • the light-emitting chip when the light-emitting chip includes three light-emitting devices 3 , the light-emitting chip includes three first connection electrodes 10 and three first binding pads 17 , so that through the first binding pads 17 And the first connection electrode 10 provides current to the P-type gallium nitride. Since the entire layer of N-type gallium nitride in the light-emitting chip is arranged, only one second connection electrode and a second bonding pad need to be provided to provide current to the N-type gallium nitride through the second bonding pad and the second connection electrode. .
  • the second binding pad 18 is in a 2 ⁇ 2 array in the area where the orthographic projection of the silicon-based substrate is located, and the three light-emitting devices 3 are in the area where the orthographic projection of the silicon-based substrate is located. .
  • the orthographic projection of the second connection electrode 11 on the silicon-based substrate falls into the non-light-emitting area 12.
  • the second connection electrode 11 is not only disposed in the area corresponding to the second binding pad 18, but also extends to the adjacent light-emitting area.
  • the area between the devices 3 and the distance between the orthographic projection of the second connection electrode 11 on the silicon-based substrate and each light-emitting device 3 are all equal. Therefore, there is a larger contact area between the second connection electrode and the N-type gallium nitride, which can improve the current transmission effect between the second connection electrode and the N-type gallium nitride.
  • the material of the first connection electrode is indium tin oxide (ITO).
  • ITO indium tin oxide
  • the second connection electrode is an alloy structure of titanium, aluminum, nickel, chromium, platinum, and gold.
  • a typical structure is an alloy structure of titanium, aluminum, nickel, and gold or an alloy structure of chromium, platinum, and gold. .
  • the material of the protective layer includes, for example, silicon oxide (SiO 2 ) or silicon nitride (SiN x ).
  • the protective layer may also be a Bragg reflection structure protective layer, wherein the Bragg reflection structure protective layer may be a stack of SiO 2 /SiN x or a stack of SiO 2 /titanium oxide (TiO 2 ), etc. .
  • the protective layer is a Bragg reflective structure protective layer
  • the Bragg reflective structure protective layer is used to reflect the light emitted by the light-emitting device, so that the light emitted by the light-emitting device will be reflected toward the sub-pixel opening side after reaching the protective layer, thereby improving the efficiency of the light-emitting chip. Light utilization.
  • the distance between adjacent binding pads in the first direction X, the distance between adjacent binding pads is equal, and in the second direction Y, the distance between adjacent binding pads is equal, wherein the first direction Direction Y is vertical.
  • the length and/or width of the binding pad is greater than or equal to 10um and less than or equal to 100um.
  • the shape of the binding pad can be a square with a length and width of 50um. This ensures that the distance between each binding pad is equal and that the distance between binding pads is as large as possible.
  • the silicon-based substrate can be thinned so that the thickness of the silicon-based substrate is greater than or equal to 5 microns and less than or equal to 50 microns. This can reduce the overall thickness of the product. And because the silicon-based substrate serves as a light-shielding layer between the photoluminescent films, light absorption caused by too thick a silicon-based substrate can be avoided.
  • the thickness of the photoluminescent light film layer is no greater than the thickness of the silicon-based substrate; for example, the thickness of the photoluminescent light film layer can be set to be the same as the thickness of the silicon-based substrate. That is, the thickness of the photoluminescent light film layer is greater than or equal to 5 microns and less than or equal to 50 microns. The thickness of the photoluminescent light film layer and the thickness of the silicon-based substrate can be set to 15 microns, for example.
  • the plurality of light-emitting devices included in the light-emitting chip are all blue light-emitting devices
  • Multiple photoluminescent color films only include: red quantum dot color film that absorbs red light emitted from blue light, and green quantum dot color film that absorbs green light emitted from blue light; the red quantum dot color film is located in the red sub-pixel opening, and the green quantum dot color film is located in the red sub-pixel opening.
  • the membrane is located at the green subpixel opening. That is, as shown in Figure 4, there is no photoluminescent film in the blue sub-pixel opening B.
  • the light-emitting chip further includes: a scattering particle layer 30 disposed in the blue sub-pixel opening B.
  • the scattering particle layer 30 includes scattering particles, which can improve the brightness distribution of the blue sub-pixel at each viewing angle.
  • the plurality of light-emitting devices included in the light-emitting chip are all ultraviolet light-emitting devices
  • Multiple photoluminescent films include: red quantum dot color films that absorb ultraviolet light and emit red light, blue quantum dot color films that absorb ultraviolet light and emit blue light, and green quantum dot color films that absorb ultraviolet light and emit green light; red light quantum dot color films The point color film is located at the red sub-pixel opening, the blue light quantum dot color film is located at the blue sub-pixel opening, and the green light quantum dot color film is located at the green sub-pixel opening.
  • the light-emitting chip further includes:
  • the microlens 19 is located on the side of the silicon-based substrate 1 away from the light-emitting device 3, and the microlens 19 covers the sub-pixel opening 2.
  • the light-emitting chip provided by the embodiment of the present disclosure is provided with a microlens on the side of the silicon-based substrate away from the light-emitting device, thereby improving the mechanical strength of the light-emitting chip, avoiding the thinning process of the silicon-based substrate and the formation of sub-pixels on the silicon-based substrate.
  • the opening results in lower mechanical strength of the light-emitting chip. It can also improve the light extraction efficiency of the light-emitting chip.
  • the light-emitting chip further includes:
  • the first distributed Bragg reflection structure 20 is located between the silicon-based substrate 1 and the microlens 19 and covers at least a plurality of photoluminescent films; it is used to transmit the light emitted from each photoluminescent film and reflect the light emitted from the light-emitting device. of light.
  • the first Bragg reflective structure covers the non-opening area of the silicon-based substrate and the photoluminescent light film.
  • the first Bragg structure and the Bragg reflective structure protective layer may be made of the same material.
  • the front projection of the first distributed Bragg reflection structure 20 on the silicon-based substrate 1 is in contact with the sub-pixel opening 2 Do not overlap with each other.
  • the first Bragg reflection structure 20 is formed on the silicon substrate.
  • the orthographic projection of bottom 1 does not overlap with the blue sub-pixel opening B.
  • the first Bragg reflective structure transmits red light and green light and reflects blue light.
  • the first Bragg reflective structure may be a TiO 2 /SiO 2 stack.
  • the first Bragg reflection structure when a photoluminescent light film is disposed in each sub-pixel opening, can be disposed to cover all sub-pixel opening areas and non-opening areas of the silicon-based substrate.
  • the light-emitting device is an ultraviolet light-emitting device
  • all sub-pixel opening areas covering the silicon-based substrate are provided with quantum dot color films
  • the first Bragg reflection structure can be provided to cover all sub-pixel opening areas of the silicon-based substrate. and non-opening areas.
  • the first Bragg reflective structure transmits red light, green light, and blue light and reflects ultraviolet light.
  • the light-emitting chip further includes:
  • the filter film 21 is located on the side of the microlens 19 facing away from the silicon-based substrate 1 .
  • the light-emitting chip provided by the embodiment of the present disclosure is provided with a filter film on the side of the microlens facing away from the silicon-based substrate, thereby improving the color purity of the light emitted by the light-emitting chip.
  • the filter film may be an ultraviolet (UV) filter film or a blue film.
  • UV ultraviolet
  • embodiments of the present disclosure also provide a method for preparing a light-emitting chip, as shown in Figure 8, including:
  • the method for preparing a light-emitting chip includes forming sub-pixel openings in a silicon-based substrate that correspond to the light-emitting devices one-to-one, and disposing a photoluminescent light film in the sub-pixel openings of the silicon-based substrate.
  • the base substrate serves as a light-shielding black matrix, so there is no need to set up an additional black matrix layer on the side of the silicon-based substrate away from the light-emitting device. This can save the light-emitting chip preparation process and cost, and the process of forming sub-pixel openings on the silicon-based substrate is simple. , which can avoid increasing the difficulty of preparing sub-pixel openings.
  • the light-emitting chip provided by the embodiment of the present disclosure will light-induced
  • the luminescent light film is arranged in the sub-pixel opening of the silicon-based substrate, instead of the photoluminescent light film being arranged in the additional black matrix layer opening on the side of the silicon-based substrate away from the light-emitting device, which can reduce photoluminescence.
  • the distance between the luminous film and the light-emitting device avoids crosstalk problems between different sub-pixels.
  • step S101 grows a light-emitting device film layer on a silicon-based substrate, as shown in Figure 9a, specifically including:
  • N-type gallium nitride layer 23, a multi-quantum well layer 24, a P-type gallium nitride layer 25, and a first connection electrode layer 26 are sequentially grown on one side of the silicon-based substrate 1;
  • step S102 Before performing a patterning process on the light-emitting device film layer to form multiple light-emitting devices in step S102, as shown in Figure 9b, it also includes:
  • the N-type semi-gallium nitride 5 of multiple light-emitting devices are integrally connected;
  • a protective layer 13 covering the first connection electrode 10 and the second connection electrode 11 is formed, and the protective layer 13 is patterned to form a first via hole 14 exposing the first connection electrode 10 and a second via hole exposing the second connection electrode 11 .
  • a bonding pad layer 27 is formed on the side of the protective layer 13 away from the first connection electrode 10 and the second connection electrode 11 , and a patterning process is performed on the bonding pad layer 27 to form an electrical connection with the first connection electrode through the first via hole 14 .
  • the first bonding pad 17 of the connection 10 and the second bonding pad 18 are electrically connected to the second connection electrode 11 through the second via hole 15 .
  • a patterning process is first performed on the P-type gallium nitride layer 25, the multiple quantum well layer 24, and the N-type gallium nitride layer 23 to form the P-type gallium nitride 7 and multiple quantum wells.
  • 6 pattern, remove part of the N-type gallium nitride layer 23 in the non-light-emitting area 12, thereby realizing the division of the light-emitting area 22 and the non-light-emitting area 12 of the light-emitting chip; then perform a patterning process on the N-type gallium nitride layer 23. More N-type gallium nitride layer 23 in the non-emitting area 12 is removed again, but a certain thickness of N-type gallium nitride is still retained in the non-emitting area 12 .
  • a dry etching process or a wet etching process can be used to pattern the first connection electrode layer.
  • the dry etching process can be used to pattern the P-type gallium nitride layer, multiple quantum well layer, and N-type gallium nitride layer.
  • a SiO 2 layer or a SiN x layer covering the first connection electrode and the second connection electrode may be formed to form a protective layer.
  • a Bragg reflection structure covering the first connection electrode and the second connection electrode can also be formed to form a Bragg reflection structure protective layer, wherein the Bragg reflection structure protective layer can be a stack of SiO 2 /SiN x or SiO 2 /TiO 2 of lamination, etc.
  • the first substrate 28 is bonded on the side of the first binding pad 17 and the second binding pad 18 facing away from the protective layer 13 .
  • bonding the first substrate on the side of the first binding pad and the second binding pad away from the protective layer specifically includes:
  • the laser detachable temporary bonding glue 29 is coated on the first substrate 28 side, and the side where the laser detachable temporary bonding glue 29 is applied is in contact with the first binding pad 17 and the second binding pad 19, so that The first bonding pad 17 and the second bonding pad 18 are bonded to the first substrate 28 .
  • the first substrate is, for example, a quartz substrate, a sapphire substrate, a glass substrate, etc.
  • the laser dissociation temporary bonding glue is a double-layer bonding glue including a laser action layer and an adhesion layer.
  • the thickness of the laser dissociation temporary bonding glue is greater than or equal to 1 micron and less than or equal to 30 microns.
  • laser The thickness of the dissociated temporary bonding glue is 5 microns.
  • sub-pixel openings corresponding to the light-emitting devices are formed on the silicon-based substrate, as shown in Figure 9f, specifically including:
  • a dry etching process or a wet etching process is used on the thinned silicon-based substrate 1 to form sub-pixel openings 2 corresponding to the light-emitting devices.
  • a chemical mechanical polishing (CMP) process or a dry etching process can be used to thin the silicon-based substrate. Wet etching or dry etching processes can then be used to form the sub-pixel openings.
  • CMP chemical mechanical polishing
  • dry etching processes can then be used to form the sub-pixel openings.
  • the substrate is sapphire or other substrates
  • a laser lift-off process is required to form the sub-pixel openings.
  • the laser lift-off process involves thermal stress, which easily affects the production yield of the light-emitting chip.
  • the method for preparing a light-emitting chip uses a silicon-based substrate and forms sub-pixel openings through a dry or wet etching process on the silicon-based substrate, thereby eliminating the need to use a laser lift-off process, that is, the process of forming sub-pixel openings. There is no thermal stress, which can improve the production yield of light-emitting chips.
  • a printing process or a photolithography process may be used to form a quantum dot color film in at least part of the sub-pixel openings.
  • a red quantum dot color film can be printed on the red sub-pixel opening, and a green quantum dot color film can be printed on the green sub-pixel opening.
  • a red light quantum dot color film can be printed on the red sub-pixel opening, a green light quantum dot color film can be printed on the green sub-pixel opening, and a blue light quantum dot color film can be printed on the blue sub-pixel opening.
  • the method further includes:
  • a microlens 19 is formed on the side of the silicon-based substrate 1 facing away from the light-emitting device.
  • microlens on the side of the silicon-based substrate away from the light-emitting device as shown in Figure 9g, it also includes:
  • a first distributed Bragg reflection structure 20 is formed on the side of the silicon-based substrate 1 away from the light-emitting device; the first distributed Bragg reflection structure 20 at least covers a plurality of photoluminescent light films 4 .
  • the front projection of the first distributed Bragg reflection structure 20 on the silicon-based substrate 1 is in contact with the sub-pixel opening 2 Do not overlap with each other.
  • the light-emitting device is a blue light-emitting device
  • the red sub-pixel opening and the green sub-pixel opening are provided with photoluminescent light films
  • the orthographic projection of the first Bragg reflection structure on the silicon-based substrate and the blue Subpixel openings do not overlap each other.
  • microlens after the microlens is formed on the side of the silicon-based substrate away from the light-emitting device, as shown in Figure 9g, it also includes:
  • a filter film 21 is formed on the side of the microlens 19 facing away from the silicon-based substrate.
  • the filter film after forming the filter film on the side of the microlens away from the silicon-based substrate, as shown in Figure 9h, it also includes:
  • the first substrate 28 is peeled off.
  • peeling off the first substrate specifically includes:
  • the first substrate is peeled off from the first binding pad and the second binding pad using a laser dissociation process.
  • the laser dissociation process when used to dissociate the double-layer laser dissociation temporary bonding glue, for example, laser dissociation with a wavelength of 308 nanometers (nm) is used, and the dissociation energy is 100 millijoules/square centimeter (mJ/ cm 2 ) ⁇ 500mJ/cm 2 , for example, it can be 250mJ/cm 2 .
  • a light-emitting substrate provided by an embodiment of the present disclosure includes a plurality of light-emitting chips provided by an embodiment of the present disclosure arranged in an array.
  • the light-emitting substrate further includes a driving backplane; a plurality of light-emitting chips are bound to the driving backplane.
  • the driving backplane includes a driving circuit
  • the driving circuit includes a pixel driving unit corresponding to a light-emitting chip, and a light-emitting chip is bound to a pixel driving unit.
  • the light-emitting chip of the first binding pad and the second binding pad can be bound to the driving backplane, thereby providing signals to the first binding pad and the second binding pad through the driving backplane to drive
  • the light-emitting device emits light.
  • the light-emitting chip and the driving backplane can be bound through a transfer process.
  • the light-emitting chip provided by the embodiments of the present disclosure includes multiple light-emitting devices, and color conversion is performed through a photoluminescent color film to achieve a full-color light-emitting chip. That is, one light-emitting chip can correspond to one pixel, which can reduce the number of light-emitting chips transferred, reduce the difficulty of light-emitting chip transfer, reduce the cost of light-emitting chip transfer, and increase the pixel density of the light-emitting substrate.
  • a display device provided by an embodiment of the present disclosure includes a light-emitting substrate provided by an embodiment of the present disclosure.
  • the display device further includes a display panel located on the light-emitting side of the light-emitting substrate. That is, the light-emitting substrate serves as the backlight module of the display panel.
  • the display panel is a liquid crystal display panel.
  • a display device provided by an embodiment of the present disclosure includes a display substrate provided by an embodiment of the present disclosure.
  • the display device provided by the embodiment of the present disclosure is: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • the photoluminescent color film is disposed in the sub-pixel opening of the silicon-based substrate, that is, the silicon-based substrate is used as a light-shielding black matrix, so there is no need to set up an additional black matrix layer on the side of the silicon-based substrate away from the light-emitting device, which can save the light-emitting chip preparation process and save costs.
  • the process of forming sub-pixel openings on the silicon-based substrate is simple and can avoid increasing sub-pixel openings. Difficulty of preparation.
  • the light-emitting chip provided by the embodiment of the present disclosure will light-induced
  • the luminescent light film is arranged in the sub-pixel opening of the silicon-based substrate, instead of the photoluminescent light film being arranged in the additional black matrix layer opening on the side of the silicon-based substrate away from the light-emitting device, which can reduce photoluminescence.
  • the distance between the luminous film and the light-emitting device avoids crosstalk problems between different sub-pixels.

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Abstract

一种发光芯片及其制备方法、发光基板、显示装置，发光芯片包括：硅基衬底（1），包括多个子像素开口（2，R，G，B）；多个发光器件（3），在硅基衬底（1）的一侧形成；发光器件（3）与子像素开口（2，R，G，B）一一对应，发光器件（3）在硅基衬底（1）的正投影与子像素开口（2，R，G，B）具有交叠；多个光致发光彩膜（4），位于至少部分子像素开口（2，R，G，B）内。

Description

发光芯片及其制备方法、发光基板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及发光芯片及其制备方法、发光基板、显示装置。
背景技术
微尺寸无机发光二极管显示是近年来发展迅速的一种新型显示技术，微尺寸无机发光二极管芯片尺寸小、发光波长可控、发光效率高、使用寿命长、发光材料对环境无污染等众多优点使得发光二极管在显示器方面的应用得以发展。
发明内容
本公开实施例提供的一种发光芯片，发光芯片包括：
硅基衬底，包括多个子像素开口；
多个发光器件，设置在硅基衬底的一侧；发光器件与子像素开口一一对应，发光器件在硅基衬底的正投影与子像素开口具有交叠；
多个光致发光彩膜，位于至少部分子像素开口内。
在一些实施例中，发光芯片还包括：
微透镜，位于硅基衬底背离发光器件一侧，微透镜覆盖子像素开口。
在一些实施例中，发光芯片还包括：
第一分布式布拉格反射结构，位于硅基衬底与微透镜之间，至少覆盖多个光致发光彩膜；用于透过各光致发光彩膜出射的光且反射发光器件出射的光。
在一些实施例中，当子像素开口内不包括光致发光彩膜时，第一分布式布拉格反射结构在硅基衬底的正投影与该子像素开口互不交叠。
在一些实施例中，发光芯片还包括：
滤光膜，位于微透镜背离硅基衬底一侧。
在一些实施例中，发光器件为微尺寸无机发光二极管。
在一些实施例中，发光器件包括：在硅基衬底的一侧叠层设置的N型氮化镓、多量子阱层、P型氮化镓；
多个发光器件的N型半氮化镓之间一体连接。
在一些实施例中，发光芯片还包括：
多个第一连接电极，位于P型氮化镓背离多量子阱层一侧；第一连接电极与P型氮化镓一一对应电连接，第一连接电极在硅基衬底的正投影落入P型氮化镓在硅基衬底的正投影落内；
第二连接电极，在发光器件之外的区域、且在N型氮化镓背离硅基衬底一侧与N型氮化镓电连接；
保护层，位于第一连接电极以及第二连接电极背离硅基衬底一侧，包括多个贯穿其厚度且露出第一连接电极的第一过孔以及贯穿其厚度且露出第二连接电极的第二过孔；
多个绑定垫，位于保护层背离第一连接电极以及第二连接电极一侧，包括：通过第一过孔与第一连接电极一一对应电连接的第一绑定垫，以及通过第二过孔与第二连接电极电连接的第二绑定垫。
在一些实施例中，发光芯片包括的多个发光器件均为蓝光发光器件；
多个子像素开口包括：红色子像素开口、蓝色子像素开口以及绿色子像素开口；
多个光致发光彩膜包括：吸收蓝光出射红光的红光量子点彩膜，以及吸收蓝光出射绿光的绿光量子点彩膜；红光量子点彩膜位于红色子像素开口，绿光量子点彩膜位于绿色子像素开口。
在一些实施例中，发光芯片包括的多个发光器件均为紫外光发光器件；
多个子像素开口包括：红色子像素开口、蓝色子像素开口以及绿色子像素开口；
多个光致发光彩膜包括：吸收紫外光出射红光的红光量子点彩膜，吸收 紫外光出射蓝光的蓝光量子点彩膜，以及吸收紫外光出射绿光的绿光量子点彩膜；红光量子点彩膜位于红色子像素开口，蓝光量子点彩膜位于蓝色子像素开口，绿光量子点彩膜位于绿色子像素开口。
在一些实施例中，硅基衬底的厚度大于等于5微米且小于等于50微米。
在一些实施例中，发光器件与光致发光彩膜之间的距离大于等于0.1微米且小于等于50微米。
在一些实施例中，发光器件在硅基衬底的正投影落入子像素开口内。
本公开实施例提供的一种发光芯片的制备方法，方法包括：
在硅基衬底上生长发光器件膜层；
对发光器件膜层进行图形化工艺形成多个发光器件；
在硅基衬底形成与发光器件一一对应的子像素开口；
在至少部分子像素开口内形成光致发光彩膜。
在一些实施例中，在硅基衬底上生长发光器件膜层，具体包括：
在硅基衬底一侧依次生长N型氮化镓层、多量子阱层、P型氮化镓层、第一连接电极层；
对发光器件膜层进行图形化工艺形成多个发光器件之前，还包括：
对第一连接电极层进行图形化工艺形成多个第一连接电极的图案；
对发光器件膜层进行图形化工艺形成多个发光器件，具体包括：
对P型氮化镓层、多量子阱层、N型氮化镓层进行图形化工艺，形成与发光区对应的P型氮化镓的图案、多量子阱层的图案；其中，多个发光器件的N型半氮化镓之间一体连接；
对发光器件膜层进行图形化工艺形成多个发光器件之后，还包括：
在发光器件之外的区域且在N型氮化镓层背离硅基衬底一侧形成第二连接电极的图案；
形成覆盖第一连接电极和第二连接电极的保护层，并对保护层进行图形化工艺形成露出第一连接电极的第一过孔以及露出第二连接电极的第二过孔；
在保护层背离第一连接电极和第二连接电极一侧形成绑定垫层，并对绑 定垫层进行图形化工艺，形成通过第一过孔与第一连接电极电连接的第一绑定垫以及通过第二过孔与第二连接电极电连接的第二绑定垫。
在一些实施例中，在硅基衬底形成与发光器件一一对应的子像素开口之前，方法还包括：
在第一绑定垫和第二绑定垫背离保护层一侧键合第一衬底；
在微透镜背离硅基衬底一侧形成滤光膜之后，方法还包括：
剥离第一衬底。
在一些实施例中，在第一绑定垫和第二绑定垫背离保护层一侧键合第一衬底，具体包括：
在第一衬底一侧涂覆激光解离临时键合胶，并在涂覆激光解离临时键合胶一侧与第一绑定垫和第二绑定垫接触，使得第一绑定垫和第二绑定垫与第一衬底键合；
剥离第一衬底，具体包括：
采用激光解离工艺将第一衬底与第一绑定垫和第二绑定垫剥离。
在一些实施例中，在硅基衬底形成与发光器件一一对应的子像素开口，具体包括：
在硅基衬底背离发光芯片一侧对硅基衬底进行减薄工艺；
对减薄后的硅基衬底采用干刻工艺或湿刻工艺形成与发光器件一一对应的子像素开口。
本公开实施例提供的一种发光基板，包括阵列排布的多个本公开实施例提供的发光芯片。
本公开实施例提供的一种显示装置，包括本公开实施例提供的发光基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的 前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种发光芯片的结构示意图；
图2为本公开实施例提供的一种发光芯片的俯视图；
图3为本公开实施例提供的一种硅基衬底的俯视图；
图4为本公开实施例提供的另一种发光芯片的结构示意图；
图5为本公开实施例提供的又一种发光芯片的结构示意图；
图6为本公开实施例提供的又一种发光芯片的结构示意图；
图7为本公开实施例提供的又一种发光芯片的结构示意图；
图8为本公开实施例提供的一种发光芯片的制备方法的流程示意图；
图9a～图9h为本公开实施例提供的另一种发光芯片的制备方法的流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是 示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供了的一种发光芯片，如图1所示，发光芯片包括：
硅基衬底1，包括多个子像素开口2；
多个发光器件3，设置在硅基衬底1的一侧；发光器件3与子像素开口2一一对应，发光器件3在硅基衬底1的正投影与子像素开口2具有交叠；
多个光致发光彩膜4，位于至少部分子像素开口2内。
本公开实施例提供的发光芯片，光致发光彩膜设置于硅基衬底的子像素开口内，即将硅基衬底作为遮光的黑矩阵，从而无需在硅基衬底背离发光器件一侧额外设置黑矩阵层，可以节省发光芯片制备工艺流程、节省成本，在硅基衬底上形成子像素开口工艺简单，可以避免增加子像素开口制备难度。并且，由于与发光器件发光侧的距离越远，发光器件发出的光的发散程度越大，部分光线在发光芯片各个界面间反射容易形成串扰，而本公开实施例提供的发光芯片，将光致发光彩膜设置于硅基衬底的子像素开口内，而不是将光致发光彩膜设置于在硅基衬底背离发光器件一侧额外设置的黑矩阵层开口内，可以减小光致发光彩膜与发光器件之间的距离，避免不同子像素之间的串扰问题。
此外，本公开实施例提供的发光芯片包括在硅基衬底一侧形成的多个发光器件，即发光芯片包括的各发光器件的发光颜色均相同，再通过光致发光彩膜实现色转换以使发光芯片实现全彩，从而可以减小发光芯片的转移难度。在硅基衬底一侧形成的多个发光器件，从而无需在临时衬底上生长发光器件各膜层，之后再将发光器件各膜层转移到支撑强度较高的基板上，可以进一步节省发光芯片的制备工艺流程、节省成本。
在一些实施例中，发光器件的长宽小于子像素开口的长宽，发光器件的面积小于子像素开口的面积。如图1所示，发光器件的宽度h2小于子像素开口的宽度h1，发光器件3在硅基衬底1的正投影落入子像素开口2内。
在一些实施例中，发光器件为微尺寸无机发光二极管。
在一些实施例中，微尺寸无机发光二极管例如可以是迷你发光二极管(Mini Light Emitting Diode，Mini-LED)或微型发光二极管(Micro Light Emitting Diode，Micro-LED)。
需要说明的是，Mini-LED以及Micro-LED的尺寸小且亮度高，可以大量应用于显示装置或其背光模组中。例如，Micro-LED的典型尺寸(例如长度)小于100微米；Mini-LED的典型尺寸(例如长度)为80微米～350微米。
在一些实施例中，如图1所示，发光器件3包括：在硅基衬底1的一侧叠层设置的N型氮化镓(N-GaN)5、多量子阱层(MQW)6、P型氮化镓(P-GaN)7；
多个发光器件的N型半氮化镓之间一体连接。
即发光芯片中N型半氮化镓整层设置。
在一些实施例中，如图2所示，发光芯片包括3个发光器件3。发光器件3中N型氮化镓以及多量子阱层的图案对应的区域即为发光芯片的发光区22，发光器件3之外的区域即为发光芯片的非发光区12。即N型半氮化镓延伸至非发光区并一体连接。
在一些实施例中，如图1所示，N-GaN 5在非发光区12的厚度小于N-GaN 5在发光器件3区域的厚度。即对N-GaN也进行刻蚀等图形化工艺，但非发光区的N-GaN并未完全去除。
当发光芯片包括3个发光器件，相应的，硅基衬底包括3个子像素开口。在一些实施例中，如图3所示，多个子像素开口2包括：红色子像素开口R、蓝色子像素开口B以及绿色子像素开口G。
在具体实施时，子像素开口的长度和/或宽度大于等于10微米且小于等于100微米；子像素开口的长度和宽度例如可以设置为50um。在具体实施时，子像素开口的尺寸不大于其对应的发光区尺寸，例如可以设置为子像素开口的长度和宽度均小于发光区的长度和宽度，即子像素开口面积小于发光区面积，且子像素开口的正投影落入发光区内。
在一些实施例中，如图1所示，发光芯片还包括：位于硅基衬底1与N 型氮化镓5之间的缓冲层8，以及位于缓冲层8与N型氮化镓5之间的U型氮化镓(U-GaN)9。
在具体实施时，缓冲层以及U-GaN均整层设置。缓冲层为多层外延结构，缓冲层例如包括依次叠层设置的氮化铝(AlN)、铝镓氮(AlGaN)、氮化镓(GaN)。U型氮化镓用于形成高质量GaN层以依次生长N-GaN、MQW、P-GaN。
在一些实施例中，缓冲层以及U-GaN的总厚度大于等于0.1微米且小于等于10微米。即发光器件与光致发光彩膜之间的距离大于等于0.1微米且小于等于50微米。
本公开实施例提供的发光芯片，将光致发光彩膜设置于硅基衬底的子像素开口内，使得光致发光彩膜与发光器件之间的距离较小可以避免不同子像素之间的串扰问题。
在一些实施例中，如图1、图2所示，发光芯片还包括：
多个第一连接电极10，位于P型氮化镓7背离多量子阱层6一侧；第一连接电极19与P型氮化镓7一一对应电连接，第一连接电极10在硅基衬底1的正投影落入P型氮化镓7在硅基衬底1的正投影内；
第二连接电极11，在发光器件3之外的区域、且在N型氮化镓5背离硅基衬底一侧与N型氮化镓5电连接；
保护层13，位于第一连接电极10以及第二连接电极11背离硅基衬底1一侧，包括多个贯穿其厚度且露出第一连接电极10的第一过孔14以及贯穿其厚度且露出第二连接电极11的第二过孔15；
多个绑定垫16，位于保护层13背离第一连接电极10以及第二连接电极11一侧，包括：通过第一过孔14与第一连接电极10一一对应电连接的第一绑定垫17，以及通过第二过孔15与第二连接电极11电连接的第二绑定垫18。
在具体实施时，如图2所示，当发光芯片包括3个发光器件3时，发光芯片包括3个第一连接电极10以及3个第一绑定垫17，从而通过第一绑定垫17以及第一连接电极10向P型氮化镓提供电流。由于发光芯片中的N型氮化镓整层设置，因此仅需要设置一个第二连接电极以及第二绑定垫，一通过 第二绑定垫以及第二连接电极向N型氮化镓提供电流。
在一些实施例中，如图2所示，第二绑定垫18在硅基衬底的正投影所在的区域以及3个发光器件3在硅基衬底的正投影的区域呈2×2阵列。第二连接电极11在硅基衬底的正投影落入非发光区12内，第二连接电极11不仅设置在第二绑定垫18对应的区域，第二连接电极11还延伸至相邻发光器件3之间的区域，且第二连接电极11在硅基衬底的正投影与各发光器件3之间的距离均相等。从而第二连接电极与N型氮化镓之间具有较大的接触面积，可以提高第二连接电极与N型氮化镓之间的电流传输效果。
在一些实施例中，第一连接电极的材料为氧化铟锡(ITO)。ITO的厚度为
Figure PCTCN2022093680-appb-000001
在一些实施例中，第二连接电极的为钛、铝、镍、铬、铂、金的合金结构，典型的结构为钛、铝、镍、金的合金结构或者铬、铂、金的合金结构。
在一些实施例中，保护层的材料例如包括氧化硅(SiO 2)或氮化硅(SiN x)。
或者，在一些实施例中，保护层还可以为布拉格反射结构保护层，其中布拉格反射结构保护层可以为SiO 2/SiN x的叠层或者为SiO 2/氧化钛(TiO 2)的叠层等。
当保护层为布拉格反射结构保护层时，布拉格反射结构保护层用于反射发光器件发出的光，从而发光器件发出的光到达保护层后会朝向子像素开口一侧反射，从而可以提高发光芯片的光利用率。
在具体实施时，在第一方向X上，相邻绑定垫之间的距离相等，且在第二方向Y上，相邻绑定垫之间的距离相等，其中第一方向X与第二方向Y垂直。在具体实施时，绑定垫的长度和/或宽度大于等于10um且小于等于100um，例如，绑定垫的形状可以为正方形，长宽为50um。从而可以确保各绑定垫之间的距离均等且绑定垫之间的距离尽可能大。
在具体实施时，可以对硅基衬底进行减薄工艺，使得硅基衬底的厚度大于等于5微米且小于等于50微米。从而可以减小产品整体的厚度。并且由于硅基衬底作为光致发光彩膜之间的遮光层，还可以避免硅基衬底厚度太厚造 成光的吸收。
在一些实施例中，光致发光彩膜层的厚度不大于硅基衬底的厚度；例如可以设置为光致发光彩膜层的厚度与硅基衬底的厚度相同。即光致发光彩膜层的厚度大于等于5微米且小于等于50微米。光致发光彩膜层的厚度与硅基衬底的厚度例如可以设置为15微米。
在一些实施例中，发光芯片包括的多个发光器件均为蓝光发光器件；
多个光致发光彩膜仅包括：吸收蓝光出射红光的红光量子点彩膜，以及吸收蓝光出射绿光的绿光量子点彩膜；红光量子点彩膜位于红色子像素开口，绿光量子点彩膜位于绿色子像素开口。即如图4所示，蓝色子像素开口B内未设置光致发光彩膜。
在一些实施例中，如图4所示，发光芯片还包括：设置在蓝色子像素开口B内的散射粒子层30。散射粒子层30包括散射粒子，可以改善蓝色子像素的各视角亮度分布。
或者，在一些实施例中，发光芯片包括的多个发光器件均为紫外光发光器件；
多个光致发光彩膜包括：吸收紫外光出射红光的红光量子点彩膜，吸收紫外光出射蓝光的蓝光量子点彩膜，以及吸收紫外光出射绿光的绿光量子点彩膜；红光量子点彩膜位于红色子像素开口，蓝光量子点彩膜位于蓝色子像素开口，绿光量子点彩膜位于绿色子像素开口。
在一些实施例中，如图5所示，发光芯片还包括：
微透镜19，位于硅基衬底1背离发光器件3一侧，微透镜19覆盖子像素开口2。
本公开实施例提供的发光芯片在硅基衬底背离发光器件一侧设置了微透镜，从而可以提升发光芯片的机械强度，避免硅基衬底进行减薄工艺以及在硅基衬底形成子像素开口导致发光芯片机械强度较低。还可以提升发光芯片的光提取效率。
在一些实施例中，如图6所示，发光芯片还包括：
第一分布式布拉格反射结构20，位于硅基衬底1与微透镜19之间，至少覆盖多个光致发光彩膜；用于透过各光致发光彩膜出射的光且反射发光器件出射的光。
在具体实施时，第一布拉格反射结构覆盖硅基衬底的非开口区与以及光致发光彩膜。
在具体实施时，当保护层为布拉格反射结构保护层时，第一布拉格结构以及布拉格反射结构保护层的材料可以相同。
在一些实施例中，如图6所示，当子像素开口2内不包括光致发光彩膜时，第一分布式布拉格反射结构20在硅基衬底1的正投影与该子像素开口2互不交叠。
在具体实施时，当发光器件为蓝光发光器件，且仅红色子像素开口以及绿色子像素开口内设置有光致发光彩膜时，如图6所示，第一布拉格反射结构20在硅基衬底1的正投影与蓝色子像素开口B互不交叠。第一布拉格反射结构透过红光、绿光而反射蓝光。第一布拉格反射结构可以为TiO 2/SiO 2叠层。
在具体实施时，当每一子像素开口内均设置有光致发光彩膜时，则第一布拉格反射结构可以设置为覆盖硅基衬底的所有子像素开口区以及非开口区域。例如，当发光器件为紫外光发光器件，覆盖硅基衬底的所有子像素开口区均设置有量子点彩膜，则第一布拉格反射结构可以设置为覆盖硅基衬底的所有子像素开口区以及非开口区域。第一布拉格反射结构透过红光、绿光、蓝光而反射紫外光。
在一些实施例中，如图7所示，发光芯片还包括：
滤光膜21，位于微透镜19背离硅基衬底1一侧。
本公开实施例提供的发光芯片在微透镜背离硅基衬底一侧设置有滤光膜，从而可以提高发光芯片的出光色纯度。
在具体实施时，滤光膜可以为紫外(UV)滤光膜或者蓝膜。
基于同一发明构思，本公开实施例还提供了一种发光芯片的制备方法，如图8所示，包括：
S101、在硅基衬底上生长发光器件膜层；
S102、对发光器件膜层进行图形化工艺形成多个发光器件；
S103、在硅基衬底形成与发光器件一一对应的子像素开口；
S104、在至少部分子像素开口内形成光致发光彩膜。
本公开实施例提供的发光芯片的制备方法，在硅基衬底形成与发光器件一一对应的子像素开口，并将光致发光彩膜设置于硅基衬底的子像素开口内，即将硅基衬底作为遮光的黑矩阵，从而无需在硅基衬底背离发光器件一侧额外设置黑矩阵层，可以节省发光芯片制备工艺流程、节省成本，在硅基衬底上形成子像素开口工艺简单，可以避免增加子像素开口制备难度。并且，由于与发光器件发光侧的距离越远，发光器件发出的光的发散程度越大，部分光线在发光芯片各个界面间反射容易形成串扰，而本公开实施例提供的发光芯片，将光致发光彩膜设置于硅基衬底的子像素开口内，而不是将光致发光彩膜设置于在硅基衬底背离发光器件一侧额外设置的黑矩阵层开口内，可以减小光致发光彩膜与发光器件之间的距离，避免不同子像素之间的串扰问题。
在一些实施例中，步骤S101在硅基衬底上生长发光器件膜层，如图9a所示，具体包括：
在硅基衬底1一侧依次生长N型氮化镓层23、多量子阱层24、P型氮化镓层25、第一连接电极层26；
在步骤S102对发光器件膜层进行图形化工艺形成多个发光器件之前，如图9b所示，还包括：
对第一连接电极层26进行图形化工艺形成多个第一连接电极10的图案；
对发光器件膜层进行图形化工艺形成多个发光器件，如图9c所示，具体包括：
对P型氮化镓层25、多量子阱层24、N型氮化镓层23进行图形化工艺，形成与发光器件对应的P型氮化镓7的图案、多量子阱层6的图案；其中，多个发光器件的N型半氮化镓5之间一体连接；
对发光器件膜层进行图形化工艺形成多个发光器件之后，如图9d所示， 还包括：
在发光器件之外的区域且在N型氮化镓5背离硅基衬底1一侧形成第二连接电极11的图案；
形成覆盖第一连接电极10和第二连接电极11的保护层13，并对保护层13进行图形化工艺形成露出第一连接电极10的第一过孔14以及露出第二连接电极11的第二过孔15；
在保护层13背离第一连接电极10和第二连接电极11一侧形成绑定垫层27，并对绑定垫层27进行图形化工艺，形成通过第一过孔14与第一连接电极电连接10的第一绑定垫17以及通过第二过孔15与第二连接电极11电连接的第二绑定垫18。
在具体实施时，如图9c所示，先对P型氮化镓层25、多量子阱层24、N型氮化镓层23进行图形化工艺，形成P型氮化镓7、多量子阱6的图案，去除非发光区12的部分N型氮化镓层23，从而实现对发光芯片发光区22和非发光区12的划分；之后再对N型氮化镓层23进行图形化工艺，再次去除非发光区12的更多N型氮化镓层23，但在非发光区12仍保留一定厚度的N型氮化镓。
在具体实施时，对第一连接电极层进行图形化工艺可以采用干刻工艺或湿刻工艺。对P型氮化镓层、多量子阱层、N型氮化镓层进行图形化工艺可以采用干刻工艺。
在具体实施时，可以形成覆盖第一连接电极和第二连接电极的SiO 2层或SiN x层以形成保护层。或者，还可以形成覆盖第一连接电极和第二连接电极的布拉格反射结构以形成布拉格反射结构保护层，其中布拉格反射结构保护层可以为SiO 2/SiN x的叠层或者为SiO 2/TiO 2的叠层等。
在一些实施例中，在硅基衬底形成与发光器件一一对应的子像素开口之前，如图9e所示，还包括：
在第一绑定垫17和第二绑定垫18背离保护层13一侧键合第一衬底28。
在一些实施例中，在第一绑定垫和第二绑定垫背离保护层一侧键合第一 衬底，如图9e所示，具体包括：
在第一衬底28一侧涂覆激光解离临时键合胶29，并在涂覆激光解离临时键合胶29一侧与第一绑定垫17和第二绑定垫19接触，使得第一绑定垫17和第二绑定垫18与第一衬底28键合。
在具体实施时，第一衬底例如为石英衬底、蓝宝石衬底、玻璃衬底等。
在具体实施时，激光解离临时键合胶为包含激光作用层和粘附层的双层键合胶，激光解离临时键合胶的厚度大于等于1微米且小于等于30微米，例如，激光解离临时键合胶的厚度为5微米。
在一些实施例中，在硅基衬底形成与发光器件一一对应的子像素开口，如图9f所示，具体包括：
在硅基衬底1背离发光器件一侧对硅基衬底1进行减薄工艺；
对减薄后的硅基衬底1采用干刻工艺或湿刻工艺形成与发光器件一一对应的子像素开口2。
在具体实施时，可以采用化学机械抛光(Chemical Mechanical Polishing，CMP)工艺或者干法刻蚀工艺对硅基衬底进行减薄。之后可以采用湿法刻蚀或者干法刻蚀工艺形成子像素开口。
需要说明的是，若衬底为蓝宝石等其他衬底，则需要采用激光剥离工艺形成子像素开口，激光剥离工艺过程存在热应力，容易影响发光芯片制备良率。而本公开实施例提供的发光芯片的制备方法，采用硅基衬底并对硅基衬底通过干刻或湿刻工艺形成子像素开口，从而无需采用激光剥离工艺，即形成子像素开口的过程不存在热应力，可以提高发光芯片制备良率。
形成子像素开口之后，在具体实施时，可以采用打印工艺或光刻工艺在至少部分子像素开口内形成量子点彩膜。
当发光器件为蓝光器件时，则可以在红色子像素开口打印红光量子点彩膜，在绿色子像素开口打印绿光量子点彩膜。当发光器件为紫外光器件时，则可以在红色子像素开口打印红光量子点彩膜，在绿色子像素开口打印绿光量子点彩膜，在蓝色子像素开口打印蓝光量子点彩膜。
在一些实施例中，在至少部分子像素开口内形成光致发光彩膜之后，如图9g所示，还包括：
在硅基衬底1背离发光器件一侧形成微透镜19。
在一些实施例中，在硅基衬底背离发光器件一侧形成微透镜之前，如图9g所示还包括：
在硅基衬底1背离发光器件一侧形成第一分布式布拉格反射结构20；第一分布式布拉格反射结构20至少覆盖多个光致发光彩膜4。
在一些实施例中，如图6所示，当子像素开口2内不包括光致发光彩膜时，第一分布式布拉格反射结构20在硅基衬底1的正投影与该子像素开口2互不交叠。
在具体实施时，当发光器件为蓝光发光器件，且仅红色子像素开口以及绿色子像素开口内设置有光致发光彩膜时，第一布拉格反射结构在硅基衬底的正投影与蓝色子像素开口互不交叠。
在一些实施例中，在硅基衬底背离发光器件一侧形成微透镜之后，如图9g所示还包括：
在微透镜19背离硅基衬底一侧形成滤光膜21。
在一些实施例中，在微透镜背离硅基衬底一侧形成滤光膜之后，如图9h所示，还包括：
剥离第一衬底28。
在一些实施例中，剥离第一衬底，具体包括：
采用激光解离工艺将第一衬底与第一绑定垫和第二绑定垫剥离。
在具体实施时，采用激光解离工艺解离双层激光解离临时键合胶时，例如采用波长为308纳米(nm)的激光解离，解离能量为100毫焦/平方厘米(mJ/cm 2)～500mJ/cm 2，例如可以为250mJ/cm 2。
本公开实施例提供的一种发光基板，包括阵列排布的多个本公开实施例提供的发光芯片。
在一些实施例中，发光基板还包括驱动背板；多个发光芯片与驱动背板 绑定。
在具体实施是，驱动背板包括驱动电路，驱动电路包括与发光芯片一一对应的像素驱动单元，一个发光芯片与一个像素驱动单元绑定。
在具体实施时，可以通过第一绑定垫以及第二绑定垫是的发光芯片与驱动背板绑定，从而通过驱动背板向第一绑定垫、第二绑定垫提供信号以驱动发光器件发光。
在具体实施时，可以通过转移工艺将发光芯片与驱动背板进行绑定。
在具体实施时，由于本公开实施例提供的发光芯片包括多个发光器件，并通过光致发光彩膜进行色转以实现发光芯片全彩化。即一个发光芯片便可以对应一个像素，从而可以减少发光芯片转移的数量，降低发光芯片转移难度，减发光小芯片转移成本，提高发光基板的像素密度。
本公开实施例提供的一种显示装置，包括本公开实施例提供的发光基板。
在一些实施例中，显示装置还包括位于发光基板出光侧的显示面板。即发光基板作为显示面板的背光模组。在具体实施时，显示面板为液晶显示面板。
本公开实施例提供的一种显示装置包括本公开实施例提供的显示基板。
本公开实施例提供的显示装置为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述发光芯片的实施例，重复之处不再赘述。
综上所述，本公开实施例提供的发光芯片及其制备方法、发光基板、显示装置，光致发光彩膜设置于硅基衬底的子像素开口内，即将硅基衬底作为遮光的黑矩阵，从而无需在硅基衬底背离发光器件一侧额外设置黑矩阵层，可以节省发光芯片制备工艺流程、节省成本，在硅基衬底上形成子像素开口工艺简单，可以避免增加子像素开口制备难度。并且，由于与发光器件发光侧的距离越远，发光器件发出的光的发散程度越大，部分光线在发光芯片各 个界面间反射容易形成串扰，而本公开实施例提供的发光芯片，将光致发光彩膜设置于硅基衬底的子像素开口内，而不是将光致发光彩膜设置于在硅基衬底背离发光器件一侧额外设置的黑矩阵层开口内，可以减小光致发光彩膜与发光器件之间的距离，避免不同子像素之间的串扰问题。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (20)

  1. 一种发光芯片，其中，所述发光芯片包括：
    硅基衬底，包括多个子像素开口；
    多个发光器件，设置在所述硅基衬底的一侧；所述发光器件与所述子像素开口一一对应，所述发光器件在所述硅基衬底的正投影与所述子像素开口具有交叠；
    多个光致发光彩膜，位于至少部分所述子像素开口内。
  2. 根据权利要求1所述的发光芯片，其中，所述发光芯片还包括：
    微透镜，位于所述硅基衬底背离所述发光器件一侧，所述微透镜覆盖所述子像素开口。
  3. 根据权利要求2所述的发光芯片，其中，所述发光芯片还包括：
    第一分布式布拉格反射结构，位于所述硅基衬底与所述微透镜之间，至少覆盖所述多个光致发光彩膜；用于透过各所述光致发光彩膜出射的光且反射所述发光器件出射的光。
  4. 根据权利要求3所述的发光芯片，其中，当所述子像素开口内不包括所述光致发光彩膜时，所述第一分布式布拉格反射结构在所述硅基衬底的正投影与该所述子像素开口互不交叠。
  5. 根据权利要求2～4任一项所述的发光芯片，其中，所述发光芯片还包括：
    滤光膜，位于所述微透镜背离所述硅基衬底一侧。
  6. 根据权利要求1～5任一项所述的发光芯片，其中，所述发光器件为微尺寸无机发光二极管。
  7. 根据权利要求6所述的发光芯片，其中，所述发光器件包括：在所述硅基衬底的一侧叠层设置的N型氮化镓、多量子阱层、P型氮化镓；
    多个所述发光器件的所述N型半氮化镓之间一体连接。
  8. 根据权利要求7所述的发光芯片，其中，所述发光芯片还包括：
    多个第一连接电极，位于所述P型氮化镓背离所述多量子阱层一侧；所述第一连接电极与所述P型氮化镓一一对应电连接，所述第一连接电极在所述硅基衬底的正投影落入所述P型氮化镓在所述硅基衬底的正投影落内；
    第二连接电极，在所述发光器件之外的区域、且在所述N型氮化镓背离所述硅基衬底一侧与所述N型氮化镓电连接；
    保护层，位于所述第一连接电极以及所述第二连接电极背离所述硅基衬底一侧，包括多个贯穿其厚度且露出所述第一连接电极的第一过孔以及贯穿其厚度且露出所述第二连接电极的第二过孔；
    多个绑定垫，位于所述保护层背离所述第一连接电极以及第二连接电极一侧，包括：通过所述第一过孔与所述第一连接电极一一对应电连接的第一绑定垫，以及通过所述第二过孔与所述第二连接电极电连接的第二绑定垫。
  9. 根据权利要求1～8任一项所述的发光芯片，其中，所述发光芯片包括的多个所述发光器件均为蓝光发光器件；
    所述多个子像素开口包括：红色子像素开口、蓝色子像素开口以及绿色子像素开口；
    所述多个光致发光彩膜包括：吸收蓝光出射红光的红光量子点彩膜，以及吸收蓝光出射绿光的绿光量子点彩膜；所述红光量子点彩膜位于所述红色子像素开口，所述绿光量子点彩膜位于所述绿色子像素开口。
  10. 根据权利要求1～8任一项所述的发光芯片，其中，所述发光芯片包括的多个所述发光器件均为紫外光发光器件；
    所述多个子像素开口包括：红色子像素开口、蓝色子像素开口以及绿色子像素开口；
    所述多个光致发光彩膜包括：吸收紫外光出射红光的红光量子点彩膜，吸收紫外光出射蓝光的蓝光量子点彩膜，以及吸收紫外光出射绿光的绿光量子点彩膜；所述红光量子点彩膜位于所述红色子像素开口，所述蓝光量子点彩膜位于所述蓝色子像素开口，所述绿光量子点彩膜位于所述绿色子像素开口。
  11. 根据权利要求1～10任一项所述的发光芯片，其中，所述硅基衬底的厚度大于等于5微米且小于等于50微米。
  12. 根据权利要求1～11任一项所述的发光芯片，其中，所述发光器件与所述光致发光彩膜之间的距离大于等于0.1微米且小于等于50微米。
  13. 根据权利要求1～12任一项所述的发光芯片，其中，所述发光器件在所述硅基衬底的正投影落入所述子像素开口内。
  14. 一种发光芯片的制备方法，其中，所述方法包括：
    在硅基衬底上生长发光器件膜层；
    对所述发光器件膜层进行图形化工艺形成多个发光器件；
    在所述硅基衬底形成与所述发光器件一一对应的子像素开口；
    在至少部分所述子像素开口内形成光致发光彩膜。
  15. 根据权利要求14所述的方法，其中，所述在硅基衬底上生长发光器件膜层，具体包括：
    在所述硅基衬底一侧依次生长N型氮化镓层、多量子阱层、P型氮化镓层、第一连接电极层；
    所述对所述发光器件膜层进行图形化工艺形成多个发光器件之前，还包括：
    对所述第一连接电极层进行图形化工艺形成多个第一连接电极的图案；
    所述对所述发光器件膜层进行图形化工艺形成多个发光器件，具体包括：
    对所述P型氮化镓层、多量子阱层、N型氮化镓层进行图形化工艺，形成与所述发光器件对应的P型氮化镓的图案、多量子阱层的图案；其中，多个所述发光器件的所述N型半氮化镓之间一体连接；
    所述对所述发光器件膜层进行图形化工艺形成多个发光器件之后，还包括：
    在所述发光器件之外的区域且在所述N型氮化镓层背离所述硅基衬底一侧形成第二连接电极的图案；
    形成覆盖所述第一连接电极和所述第二连接电极的保护层，并对所述保 护层进行图形化工艺形成露出所述第一连接电极的第一过孔以及露出所述第二连接电极的第二过孔；
    在所述保护层背离所述第一连接电极和所述第二连接电极一侧形成绑定垫层，并对所述绑定垫层进行图形化工艺，形成通过所述第一过孔与所述第一连接电极电连接的第一绑定垫以及通过所述第二过孔与所述第二连接电极电连接的第二绑定垫。
  16. 根据权利要求15所述的方法，其中，所述在所述硅基衬底形成与所述发光器件一一对应的子像素开口之前，所述方法还包括：
    在所述第一绑定垫和所述第二绑定垫背离所述保护层一侧键合第一衬底；
    所述在所述微透镜背离所述硅基衬底一侧形成滤光膜之后，所述方法还包括：
    剥离所述第一衬底。
  17. 根据权利要求16所述的方法，其中，所述在所述第一绑定垫和所述第二绑定垫背离所述保护层一侧键合第一衬底，具体包括：
    在所述第一衬底一侧涂覆激光解离临时键合胶，并在涂覆所述激光解离临时键合胶一侧与所述第一绑定垫和所述第二绑定垫接触，使得所述第一绑定垫和所述第二绑定垫与所述第一衬底键合；
    所述剥离所述第一衬底，具体包括：
    采用激光解离工艺将所述第一衬底与所述第一绑定垫和所述第二绑定垫剥离。
  18. 根据权利要求14～17任一项所述的方法，其中，所述在所述硅基衬底形成与所述发光器件一一对应的子像素开口，具体包括：
    在所述硅基衬底背离所述发光器件一侧对所述硅基衬底进行减薄工艺；
    对减薄后的所述硅基衬底采用干刻工艺或湿刻工艺形成与所述发光器件一一对应的子像素开口。
  19. 一种发光基板，其中，包括阵列排布的多个根据权利要求1～13任一项所述的发光芯片。
  20. 一种显示装置，其中，包括根据权利要求19所述的发光基板。
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