WO2023024997A1 - 一种显示基板及其制备方法、显示装置 - Google Patents

一种显示基板及其制备方法、显示装置 Download PDF

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WO2023024997A1
WO2023024997A1 PCT/CN2022/113036 CN2022113036W WO2023024997A1 WO 2023024997 A1 WO2023024997 A1 WO 2023024997A1 CN 2022113036 W CN2022113036 W CN 2022113036W WO 2023024997 A1 WO2023024997 A1 WO 2023024997A1
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Prior art keywords
layer
sub
light
backplane
optical
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PCT/CN2022/113036
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English (en)
French (fr)
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王灿
齐琪
李伟
张粲
玄明花
牛晋飞
张晶晶
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京东方科技集团股份有限公司
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Publication of WO2023024997A1 publication Critical patent/WO2023024997A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, and in particular, relate to a display substrate, a manufacturing method thereof, and a display device.
  • LED Light Emitting Diode
  • the present disclosure provides a method for preparing a display substrate, the method comprising:
  • a first substrate is provided, and a light-emitting chip layer is formed on the first substrate to form a first backplane.
  • the light-emitting chip layer includes: light-emitting chips arranged in an array, and the light-emitting chips are arranged to emit light of a first color , the light-emitting chip includes: N sub-pixels, N is a positive integer greater than or equal to 1;
  • a second substrate is provided, and a driving circuit layer is formed on the second substrate to form a second backplane.
  • the driving circuit layer includes: connection electrodes arranged in an array, and the light-emitting chips correspond to the connection electrodes one by one;
  • An optical film layer is formed on the side of the light-emitting chip layer away from the second backplane, and the optical film layer is configured to scatter light of the first color, convert light of the first color into light of the second color and The light of the color is converted into the light of the third color.
  • each sub-pixel includes: a first pixel semiconductor layer, a second pixel semiconductor layer, a pixel multi-quantum well layer, a first electrode, and a second electrode;
  • the forming the light-emitting chip layer on the first substrate includes:
  • a buffer layer, a first semiconductor layer, a multiple quantum well layer, a second semiconductor layer, a transparent conductive layer, a first insulating layer, and a pad layer are sequentially grown; wherein, the first semiconductor layer includes : the first pixel semiconductor layer, the multi-quantum well layer includes: the pixel multi-quantum well layer, the second semiconductor layer includes: the second pixel semiconductor layer, the transparent conductive layer includes: the first electrode, and the pad layer includes: the second electrode and the welding pad layer pad, the pad is connected to the first electrode;
  • the first pixel semiconductor layers of different sub-pixels are the same film layer, the pixel multi-quantum well layer, the second pixel semiconductor layer and the first electrode of different sub-pixels are all spaced apart from each other, and the second pixel semiconductor layers of different sub-pixels are arranged at intervals.
  • the electrodes are the same electrode, and the first electrodes of different sub-pixels are connected to different pads;
  • the orthographic projection of the pad on the first substrate and the orthographic projection of the first electrode connected to the pad on the substrate at least partially overlap or there is no overlapping area.
  • the forming the driving circuit layer on the second substrate includes:
  • a driving structure layer, a first flat layer, a metal conductive layer, a second insulating layer, a second flat layer and a solder paste layer are sequentially formed on the second substrate;
  • the metal conductive layer includes: connecting electrodes;
  • a solder paste layer Including: solder paste structure arranged in an array;
  • each connection electrode includes: a first sub-connection electrode and a second sub-connection electrode, the first sub-connection electrode is electrically connected to the first electrode in the corresponding light-emitting chip, and the second sub-connection electrode is connected to the corresponding The second electrode in the light emitting chip is electrically connected;
  • each connection electrode includes: N first sub-connection electrodes and one second sub-connection electrode; the N first sub-connection electrodes are respectively connected to the first electrodes of N sub-pixels in the corresponding light-emitting chip Electrically connected, the second connection electrode is electrically connected to the second electrodes of the N sub-pixels in the corresponding light-emitting chip;
  • Each sub-connection electrode is connected to a solder paste structure, and different sub-connection electrodes are connected to different solder paste structures.
  • the transferring the first backplane from which the first substrate has been peeled off to the second backplane includes:
  • the first substrate is lifted off by using a laser lift-off process.
  • the transferring the first backplane from which the first substrate has been peeled off to the second backplane includes:
  • the third backplane is peeled off, and the light-emitting chip layer bonded to the third backplane is transferred to the second backplane.
  • forming the optical film layer on the side of the light-emitting chip layer away from the second backplane includes:
  • a colloidal layer is formed by coating or dispensing on the side of the light-emitting chip layer away from the second backplane;
  • a black matrix layer is formed on the colloid layer; the black matrix layer is provided with a first via hole exposing each sub-pixel in the light-emitting chip;
  • the optical film layer includes: a first optical sub-film layer, a second optical sub-film layer and a third optical sub-film layer;
  • the first optical sub-film layer is set to Convert the light of the first color to the light of the second color
  • the second optical sub-film layer is set to convert the light of the first color into the light of the third color
  • the third optical sub-film layer is set to convert the light of the first color scatter out;
  • each sub-pixel includes: one of the first optical sub-film layer, the second optical sub-film layer and the third optical sub-film layer; the optical sub-film included in the sub-pixel of the adjacent light-emitting chip layers are different;
  • the three sub-pixels located in the same light-emitting chip respectively include the first optical sub-film layer, the second optical sub-film layer and the third optical sub-film layer, and the optical sub-films included in the three sub-pixels located in different light-emitting chips
  • the layers are the same, or the three sub-pixels located in the same light-emitting chip include the same optical sub-film layer, and the three sub-pixels located in different light-emitting chips include different optical sub-film layers;
  • N is a positive integer not equal to 1 and not equal to 3
  • the three sub-pixels located on the same light-emitting chip include the same optical sub-film layer, and the three sub-pixels located on different light-emitting chips include different optical sub-film layers;
  • the orthographic projection of the optical sub-film layer in each sub-pixel on the second backplane is at least partially overlapped with the orthographic projection of the multi-quantum well layer in each sub-pixel on the second backplane.
  • the sequentially forming the barrier and the optical film layer on the black matrix layer includes:
  • the retaining wall is provided with a second via hole exposing the first via hole;
  • the sequentially forming the barrier and the optical film layer on the black matrix layer includes:
  • a blocking wall is formed on the black matrix layer; the orthographic projection of the blocking wall on the second backplane covers the orthographic projection of the first via hole on the second backplane;
  • the first optical particle, the second optical particle and the third optical particle are injected into the barrier to form the first optical sub-film layer, the second optical sub-film layer and the third optical sub-film layer.
  • the method further includes:
  • An organic encapsulation layer and a first inorganic encapsulation layer are sequentially formed on the optical film layer.
  • the method further includes:
  • a color filter layer is formed on the second inorganic encapsulation layer, and the color filter layer includes: a first color filter layer, a second color filter layer and a third color filter layer; the first color filter layer and the first optical sub-film layer One-to-one correspondence, the orthographic projection of the first color filter layer on the second backplane covers the orthographic projection of the corresponding first optical sub-film layer on the second backplane, and the second color filter layer and the second optical sub-film layer are one by one Correspondingly, the orthographic projection of the second color filter layer on the second backplane covers the orthographic projection of the corresponding second optical sub-film layer on the second backplane, and the third color filter layer corresponds to the third optical sub-film layer one-to-one , the orthographic projection of the third color filter layer on the second backplane covers the orthographic projection of the corresponding third optical sub-film layer on the second backplane;
  • An organic encapsulation layer and a first inorganic encapsulation layer are sequentially formed on the color filter layer.
  • the first substrate is a sapphire substrate.
  • the present disclosure also provides a display substrate, which is prepared by the above method for preparing a display substrate.
  • the present disclosure further provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a flowchart of a method for preparing a display substrate provided by an embodiment of the present disclosure
  • Fig. 2A is a cross-sectional view of a first backplane provided by an exemplary embodiment
  • Fig. 2B is a cross-sectional view of a first backplane provided by another exemplary embodiment
  • Fig. 2C is a cross-sectional view of a first backplane provided by yet another exemplary embodiment
  • Fig. 2D is a cross-sectional view of a first backplane provided by yet another exemplary embodiment
  • FIG. 2E is a schematic diagram of an arrangement of sub-pixels in an exemplary embodiment
  • FIG. 2F is a top view of a pad layer in an exemplary embodiment
  • 3A is a schematic diagram after forming a buffer layer
  • 3B is a schematic diagram after forming the first semiconductor layer
  • FIG. 3C is a schematic diagram after forming a multi-quantum well layer
  • 3D is a schematic diagram after forming a second semiconductor layer
  • 3E is a schematic diagram after forming a transparent conductive layer
  • FIG. 3F is a schematic diagram after forming an insulating layer
  • Fig. 4A is a schematic diagram of a second backplane provided by an exemplary embodiment
  • FIG. 4B is a schematic diagram of a second backplane provided by another exemplary embodiment
  • 5A is a schematic diagram after forming a driving structure layer
  • 5B is a schematic diagram after forming the first flat layer
  • 5C is a schematic diagram after forming a metal conductive layer
  • 5D is a schematic diagram after forming a second insulating layer
  • FIG. 5E is a schematic diagram after forming a second flat layer
  • 6A to 6B are schematic diagrams of step S3 provided by an exemplary embodiment
  • FIGS. 7A to 7B are schematic diagrams of step S3 provided by another exemplary embodiment
  • 8A is a schematic diagram of forming a colloidal layer
  • FIG. 8B is a schematic diagram after forming a black matrix layer
  • Figure 8C is a schematic diagram after forming a retaining wall
  • Fig. 8D is a schematic diagram 2 after forming a retaining wall
  • 8E is a schematic diagram after forming an optical film layer
  • FIG. 8F is a second schematic diagram after forming an optical film layer
  • Fig. 9A is a first schematic diagram after forming the first inorganic encapsulation layer provided by an exemplary embodiment
  • Fig. 9B is a second schematic diagram after forming the first inorganic encapsulation layer provided by an exemplary embodiment
  • FIG. 9C is a third schematic diagram after forming the first inorganic encapsulation layer provided by an exemplary embodiment
  • Fig. 9D is a schematic diagram 4 after forming the first inorganic encapsulation layer provided by an exemplary embodiment
  • Fig. 9E is a schematic diagram 5 after forming the first inorganic encapsulation layer provided by an exemplary embodiment
  • FIG. 9F is a sixth schematic diagram after forming the first inorganic encapsulation layer provided by an exemplary embodiment
  • Fig. 10A is a first schematic diagram after forming the first inorganic encapsulation layer provided by another exemplary embodiment
  • Fig. 10B is a second schematic diagram after forming the first inorganic encapsulation layer provided by another exemplary embodiment
  • FIG. 10C is a third schematic diagram after forming the first inorganic encapsulation layer provided by another exemplary embodiment
  • FIG. 10D is a fourth schematic diagram after forming the first inorganic encapsulation layer provided by another exemplary embodiment
  • Fig. 10E is a schematic diagram 5 after forming the first inorganic encapsulation layer provided by another exemplary embodiment
  • FIG. 10F is a sixth schematic diagram after forming the first inorganic encapsulation layer provided by another exemplary embodiment.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • Micro LEDs can include Micro Light Emitting Diodes (Micro LEDs) and submillimeter Light Emitting Diodes (Mini Light Emitting Diodes, Mini LEDs), which have the advantages of small size and high brightness, and can be widely used in backlight modules of display devices.
  • the screen contrast of display products using micro-LEDs can reach the level of organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) display products, improve the display effect of the screen, and provide users with a better visual experience.
  • OLED Organic Light-Emitting Diode
  • micro-LED display has gradually become a hot spot of display panels, mainly used in AR/VR, TV and outdoor display fields.
  • micro-LEDs are usually miniaturized, arrayed, and thin-filmed with LED chips using micro-miniature process technology, and LED chips are transferred to the driver backplane in batches through mass transfer technology.
  • Typical dimensions (such as length) of Micro LEDs can be less than 100 ⁇ m, such as 10 ⁇ m to 50 ⁇ m.
  • Typical dimensions (eg length) of Mini LEDs can be around 100 ⁇ m to 300 ⁇ m, eg 120 ⁇ m to 260 ⁇ m.
  • a micro-LED display substrate includes a sapphire substrate and light-emitting chips arranged in an array arranged on the sapphire substrate. Due to the existence of sapphire on the light-emitting chip, the distance between different light-emitting chips is relatively large, which reduces the micro-LED display. The resolution and display effect of the substrate.
  • FIG. 1 is a flowchart of a method for preparing a display substrate provided by an embodiment of the present disclosure. As shown in FIG. 1 , the method for preparing a display substrate provided by an embodiment of the present disclosure may include the following steps:
  • Step S1 providing a first substrate, and forming a light-emitting chip layer on the first substrate to form a first backplane.
  • the light-emitting chip layer includes: light-emitting chips arranged in an array, the light-emitting chips are configured to emit light of a first color, and the light-emitting chips include: N sub-pixels, where N is a positive integer greater than or equal to 1.
  • the light emitting chip can be a Micro LED or a Mini LED.
  • the first color may be blue, or may be red or green, which is not limited in this disclosure.
  • the at least one sub-pixel may be arranged in an array.
  • the light-emitting chip exists in the form of a pixel island.
  • the first substrate may include one of: a sapphire substrate, a silicon carbide substrate, a silicon substrate or a gallium nitride substrate.
  • the thickness of the first substrate may be about 55 microns to 65 microns, for example, the thickness of the first substrate is 60 microns.
  • Step S2 providing a second substrate, and forming a driving circuit layer on the second substrate to form a second backplane.
  • the driving circuit layer includes: connecting electrodes arranged in an array, and the light emitting chips correspond to the connecting electrodes one by one.
  • the driving circuit layer may be configured to drive the light-emitting chip to emit light, and the second backplane is the driving backplane.
  • Step S3 transferring the first backplane from which the first substrate has been peeled off to the second backplane, so that the light emitting chips are electrically connected to the corresponding connection electrodes.
  • the first backplane from which the first substrate has been peeled off includes a light emitting chip layer.
  • Step S4 forming an optical film layer on the side of the light-emitting chip layer away from the second backplane.
  • the optical film layer can be configured to scatter light of the first color, convert light of the first color into light of the second color, and convert light of the first color into light of the third color. light.
  • the arrangement of the optical film layer can make the display substrate present various colors, thereby improving the display effect of the display substrate.
  • the disclosure can realize at least one or two sub-pixels in one light-emitting chip, which is beneficial to realize high PPI design, can reduce the size pressure of multiple times of die bonding, can reduce the number of bonding times, and improves the product yield.
  • the method for preparing a display substrate includes: providing a first substrate, and forming a light-emitting chip layer on the first substrate to form a first backplane.
  • the light-emitting chip layer includes: light-emitting chips arranged in an array, emitting light The chip is set to emit light of the first color, and the light-emitting chip includes: N sub-pixels, where N is a positive integer greater than or equal to 1; a second substrate is provided, and a driving circuit layer is formed on the second substrate to form a second back plate, the driving circuit layer includes: connecting electrodes arranged in an array, and the light-emitting chips correspond to the connecting electrodes one by one; the first backplane with the first substrate peeled off is transferred to the second backplane, so that the light-emitting chips and the corresponding The connecting electrodes are electrically connected; an optical film layer is formed on the side of the light-emitting chip layer away from the second backplane, and the optical film layer is set to
  • the present disclosure can reduce light emission by transferring the first backplane from which the first substrate has been peeled off to the second backplane, and forming an optical film layer on the side of the first backplane from which the first substrate has been peeled away from the second backplane.
  • the distance between the chips improves the resolution and display effect of the display substrate.
  • FIG. 2A is a cross-sectional view of a first backplane provided in an exemplary embodiment
  • FIG. 2B is a cross-sectional view of a first backplane provided in another exemplary embodiment
  • FIG. 2C is A cross-sectional view of the first backplane provided in yet another exemplary embodiment
  • FIG. 2D is a cross-sectional view of the first backplane provided in yet another exemplary embodiment. As shown in Figure 2A to Figure 2D.
  • Each light-emitting chip includes: at least one sub-pixel 100 , and each sub-pixel includes: a first pixel semiconductor layer 12 , a second pixel semiconductor layer 140 , a pixel multi-quantum well layer 130 , a first electrode 150 and a second electrode 18 .
  • FIG. 2A and FIG. 2B are illustrated by taking each light emitting chip including three sub-pixels as an example.
  • FIG. 2C is illustrated by taking each light-emitting chip as an example to include one sub-pixel.
  • FIG. 2E is a schematic diagram of an arrangement of sub-pixels in an exemplary embodiment. As shown in FIG. 2E , when the number of sub-pixels is multiple, the sub-pixels may be arranged horizontally, vertically, in a pattern or in a positive direction, which is not limited in this disclosure. FIG. 2 is illustrated by taking three sub-pixels arranged in a character pattern as an example.
  • the sizes of different sub-pixels in the same light-emitting chip may be different, or may be the same. Different sub-pixels located in the same light-emitting chip in FIG. 2A have different sizes, and sub-pixels located in the same light-emitting chip in FIG. 2B have the same size.
  • step S1 may include: sequentially growing a buffer layer 19, a first semiconductor layer 12, a multi-quantum well layer 13, a second semiconductor layer 14, and a transparent conductive layer 15 on one side of the first substrate. , the first insulating layer 16 and the pad layer 17 .
  • the multi-quantum well layer 13 includes: a pixel multi-quantum well layer 130
  • the second semiconductor layer 14 includes: a second pixel semiconductor layer 140
  • the transparent conductive layer 15 includes: a first electrode 150
  • the pad layer 17 includes: a second electrode 18 and the pad 170 , the pad 170 is connected to the first electrode 150 .
  • the first semiconductor layer of different sub-pixels is the same film layer, and the multi-quantum well layer, second semiconductor layer and first electrode of different sub-pixels are all arranged at intervals from each other,
  • the second electrodes of different sub-pixels are the same electrode, and the first electrodes of different sub-pixels are connected to different pads.
  • the orthographic projection of the pad 170 on the first substrate 11 and the orthographic projection of the first electrode 150 connected to the pad 170 on the substrate may at least partially overlap or there may be no overlapping area.
  • . 2A to 2C are illustrated by taking an example that the orthographic projection of the pad 170 on the first substrate 11 and the orthographic projection of the first electrode 150 connected to the pad 170 on the substrate may at least partially overlap.
  • FIG. 2D is illustrated by taking an example that the orthographic projection of the pad 170 on the first substrate 11 does not overlap with the orthographic projection of the first electrode 150 connected to the pad 170 on the substrate.
  • 2D is illustrated by taking the light-emitting chip including one sub-pixel as an example, and the light-emitting chip may also include multiple sub-pixels, which is not taken as an example in the present disclosure.
  • the positional relationship between the pad and the first electrode in the present disclosure can make the arrangement of the display substrate more flexible.
  • FIG. 2F is a top view of a pad layer in an exemplary embodiment. As shown in FIG. 2F , when the number of sub-pixels is three, the pads 170 and the second electrodes 18 may be distributed in a square or other shapes, which is not limited in this disclosure. As shown in FIG. 2F , the distribution of the bonding pads 170 and the second electrodes 18 is a square as an example for illustration.
  • step S1 may further include: forming a connecting wire configured to connect the pad and the first electrode.
  • the buffer layer 19 may have a refractive index ranging from 2 to 3.
  • the buffer layer 72 may have a refractive index of approximately 2.54.
  • the buffer layer 72 may be made of gallium nitride (GaN).
  • the buffer layer 18 may have a thickness of about 2 ⁇ m.
  • the first semiconductor layer 12 may be N-type doped gallium nitride
  • the second electrode may be an N electrode
  • the second semiconductor layer 14 may be P-type doped gallium nitride.
  • One electrode can be a P electrode, or the first semiconductor layer 12 can be P-type doped gallium nitride, the second electrode can be a P electrode, and the second semiconductor layer 14 can be N-type doped gallium nitride.
  • the electrodes may be N electrodes.
  • the thickness of the first semiconductor layer 12 may be about 2 ⁇ m.
  • the thickness of the first semiconductor layer 14 may be about 2 ⁇ m.
  • the thickness of the multiple quantum well layer 13 may be about 0.3 ⁇ m.
  • the thickness of the first semiconductor layer 12 , the thickness of the multi-quantum well layer 13 , and the thickness of the second semiconductor layer 14 can all be set according to actual process requirements.
  • the first insulating layer 16 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer , multi-layer or composite layer.
  • patterning process when the patterned material is an inorganic material or metal, “patterning” includes coating photoresist, mask exposure, development, etching, stripping Processes such as photoresist, when the patterned material is an organic material, “patterning” includes processes such as mask exposure and development.
  • the vapor deposition, deposition, coating, coating, etc. mentioned in this disclosure are all related technologies Medium and mature preparation technology.
  • Step S11 providing a first substrate 11, depositing a buffer film on one side of the first substrate 11, and forming a buffer layer 19 on the first substrate through a patterning process, as shown in FIG. 3A, which is a diagram for forming a buffer layer After the schematic diagram.
  • Step S12 depositing a first semiconductor film on the buffer layer 19 , and processing the buffer film through a patterning process to form the first semiconductor layer 12 , as shown in FIG. 3B , which is a schematic diagram of the formation of the first semiconductor layer.
  • the surface of the first semiconductor layer away from the first substrate is uneven.
  • Step S13 depositing a multi-quantum well film on the first semiconductor layer 12, and processing the multi-quantum well film through a patterning process to form a multi-quantum well layer 13, as shown in FIG. 3C, which is after the multi-quantum well layer is formed.
  • FIG. 3C schematic diagram.
  • Step S14 depositing a second semiconductor thin film on the multi-quantum well layer 13, and processing the second semiconductor thin film through a patterning process to form a second semiconductor layer 14, as shown in FIG. 3D.
  • Step S15 deposit a transparent conductive film on the second semiconductor layer 14 , and process the transparent conductive film through a patterning process to form a transparent conductive layer 15 , as shown in FIG. 3E , which is a schematic diagram after forming the transparent conductive layer.
  • Step S16 deposit a first insulating film on the transparent conductive layer 15 , and process the insulating film through a patterning process to form a first insulating layer 16 , as shown in FIG. 3F , which is a schematic diagram after forming the insulating layer.
  • Step S17 deposit a conductive layer on the first insulating layer 16 , and process the conductive layer through a patterning process to form a pad layer 17 , as shown in FIG. 2A .
  • FIG. 4A is a schematic diagram of a second backplane provided in an exemplary embodiment
  • FIG. 4B is a schematic diagram of a second backplane provided in another exemplary embodiment
  • the second backplane includes: a driving structure layer 22 disposed on a second substrate 21, a first planar layer 23, a metal conductive layer 24, a second insulating layer 25, a second planar layer 26 and solder paste layer 27.
  • step S2 may include: sequentially forming a driving structure layer, a first planar layer, a metal conductive layer, a second insulating layer, a second planar layer and a solder paste layer on the second substrate.
  • the metal conductive layer includes: connecting electrodes 200 and power lines 243; the solder paste layer includes: solder paste structures 700 arranged in an array. Different light-emitting chips have different structures of connecting electrodes connected to the light-emitting chips.
  • the power line 243 is configured to continuously provide a high level signal.
  • each connection electrode 200 includes: a first sub-connection electrode 241 and a second sub-connection electrode 242 .
  • the first sub-connection electrode is electrically connected to the first electrode in the corresponding light-emitting chip
  • the second sub-connection electrode is electrically connected to the second electrode in the corresponding light-emitting chip.
  • each connection electrode includes: N first sub-connection electrodes 241 and one second sub-connection electrode 242; the N first sub-connection electrodes are respectively connected to the corresponding The first electrodes of the N sub-pixels in the light-emitting chip are electrically connected, and the second connection electrodes are electrically connected with the second electrodes of the N sub-pixels in the corresponding light-emitting chip;
  • each sub-connection electrode is connected to a solder paste structure, and different sub-connection electrodes are connected to different solder paste structures.
  • the driving structure layer includes a plurality of thin film transistors.
  • the thin film transistor includes: an active layer, a gate electrode, a source electrode and a drain electrode.
  • the thin film transistor may have a top-gate structure or a bottom-gate structure, which is not limited in this disclosure.
  • organic materials may be used as materials for the first planar layer and the second planar layer.
  • the metal conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above metals Alloy materials, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be single-layer structure, or multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above metals Alloy materials, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the second insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, Multiple layers or composite layers.
  • Step S21 providing a second substrate 21 , and forming a driving structure layer 22 on one side of the second substrate 21 , as shown in FIG. 5A , which is a schematic diagram after forming the driving structure layer.
  • forming the driving structure layer may include: sequentially forming an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source-drain electrode, and a passivation layer, or sequentially forming a gate electrode, a gate insulating layer, active layer, source and drain electrodes and passivation layer.
  • Step S22 coating the first flat film on the driving structure layer 22, and processing the first flat film through a patterning process to form the first flat layer 23, as shown in FIG. 5B, which is after the first flat layer is formed.
  • Step S23 deposit a conductive metal film on the first planar layer 23 , and process the conductive metal film through a patterning process to form a conductive metal layer 24 , as shown in FIG. 5C , which is a schematic diagram after forming the conductive metal layer.
  • Step S24 deposit a second insulating film on the metal conductive layer 24, and process the second insulating film through a patterning process to form a second insulating layer 25, as shown in FIG. 5D, which is the result of forming the second insulating layer.
  • FIG. 5D is the result of forming the second insulating layer.
  • the second insulating layer is provided with a via hole exposing the connection portion in the metal conductive layer.
  • Step S25 coating a second flat film on the second insulating layer 25, and processing the second flat film through a patterning process to form a second flat layer 26, as shown in FIG. 5E, and FIG. After the schematic diagram.
  • a via hole exposing the via hole of the insulating layer 25 may be opened on the second planar layer 26 .
  • Step S26 forming a solder paste layer 27 on the second flat layer 26 by spot welding, as shown in FIG. 4A .
  • step S3 may include: transferring the first backplane to the second backplane; electrically connecting the light-emitting chips to corresponding connection electrodes; and peeling off the first substrate by using a laser lift-off process.
  • step S3 may include: transferring the first backplane to a third backplane, so that the third backplane is bonded to the light-emitting chip layer; using a laser lift-off process to lift off the first substrate; The third backplane is peeled off, and the light-emitting chip layer bonded to the third backplane is transferred to the second backplane.
  • Both of the above two embodiments can peel off the first substrate on the first backplane.
  • the first embodiment is to peel off after the first backplane is transferred to the second backplane.
  • the second embodiment is to peel off the first substrate on the first backplane.
  • the plates were peeled off before being transferred to a second backing plate.
  • Step S3 provided by an exemplary embodiment will be described below with reference to FIG. 6A to FIG. 6B .
  • Step S310 transferring the first backplane 10 to the second backplane 20 , so that the light emitting chips are electrically connected to the corresponding connection electrodes, as shown in FIG. 6A .
  • Step S311 using a laser lift-off process to lift off the first substrate, as shown in FIG. 6B .
  • step S3 provided by another exemplary embodiment is described below through FIG. 7A to FIG. 7B .
  • Step S320 transferring the first backplane 10 to the third backplane 30 , as shown in FIG. 7A .
  • Step S321 using a laser lift-off process to lift off the first substrate, as shown in FIG. 7B .
  • Step S322 peel off the third backplane, and transfer the light-emitting chip layer bonded to the third backplane to the second backplane, as shown in FIG. 6B .
  • the first backplane in FIG. 6 and FIG. 7 is a simplified first backplane, and the actual structure is the structure in FIG. 2A .
  • the first backplane can also be the structure in FIG. 2B or FIG. 2C .
  • the intermediate film layer 110 includes: a buffer layer, a first semiconductor layer, a multiple quantum well layer, a second semiconductor layer, a transparent conductive layer and an insulating layer arranged in sequence from top to bottom.
  • step S4 may include the following steps:
  • Step S41 forming a colloid layer on the side of the light-emitting chip layer away from the second backplane by coating or dispensing process.
  • the thickness of the colloidal layer may be about 10 um, and the colloidal layer may protect and fix the light-emitting chip layer.
  • the colloidal layer can be made of silicone potting glue or epoxy resin.
  • Step S42 forming a black matrix layer on the colloid layer.
  • the black matrix layer is provided with a first via hole exposing each sub-pixel in the light emitting chip.
  • Step S43 sequentially forming a barrier wall and an optical film layer on the black matrix layer.
  • the optical film layer includes: a first optical sub-film layer, a second optical sub-film layer and a third optical sub-film layer; the first optical sub-film layer is configured to convert light of the first color For light of the second color, the second optical sub-film layer is configured to convert the light of the first color into light of the third color, and the third optical sub-film layer is configured to scatter the light of the first color.
  • the first optical sub-film layer may include: a quantum dot material of a second color.
  • the second optical sub-film layer may include: a third color quantum dot material.
  • the third optical sub-film layer may include scattering particles, the scattering particles may be high refractive index material particles, the refractive index of the scattering particles may be greater than or equal to 1.7, and the material of the scattering particles may be silane-containing Resin material.
  • the light of the second color is generated by the first optical sub-film layer under the excitation of the light-emitting chip
  • the light of the third color is generated by the second optical sub-film layer under the excitation of the light-emitting chip, so , the generated light types of the second color and the third color are consistent, while the first color is directly generated by the light-emitting chip, therefore, the light type of the first color is inconsistent with the light type of the second color and the third color.
  • the third optical sub-film layer By arranging the third optical sub-film layer, the light type of the displayed first color can be improved, the light intensity consistency of the first color, the second color and the third color at the same angle can be improved, and the display effect can be improved.
  • the first optical sub-film layer, the second optical sub-film layer and the third optical sub-film layer may have the same thickness. In this way, the optical path consistency of the first color, the second color and the third color can be improved, and the display effect can be improved.
  • the sub-pixels include different optical sub-film layers.
  • the three sub-pixels located in the same light-emitting chip respectively include the first optical sub-film layer, the second optical sub-film layer and the third optical sub-film layer, and are located in different light-emitting chips
  • the three sub-pixels include the same optical sub-film layer, or the three sub-pixels located in the same light-emitting chip include the same optical sub-film layer, and the three sub-pixels located in different light-emitting chips include different optical sub-film layers.
  • N is a positive integer not equal to 1 and not equal to 3
  • three sub-pixels located on the same light-emitting chip include the same optical sub-film layer
  • three sub-pixels located on different light-emitting chips include The optical sub-layers are different.
  • the orthographic projection of the optical sub-film layer in each sub-pixel on the second backplane at least partially overlaps the orthographic projection of the multi-quantum well layer in each sub-pixel on the second backplane.
  • the distance between the optical sub-film layers of adjacent sub-pixels is about 20 microns.
  • step S43 may include: forming a retaining wall on the black matrix layer, the retaining wall is provided with a second via hole exposing the first via hole; depositing a first optical film on the retaining wall , the second optical film and the third optical film, the first optical film is processed by a patterning process to form a first optical sub-film layer, and the second optical film is processed by a patterning process to form a second optical sub-film layer , processing the third optical thin film through a patterning process to form a third optical sub-film layer.
  • step S43 may include: forming a blocking wall on the black matrix layer; the orthographic projection of the blocking wall on the second backplane covers the orthographic projection of the first via hole on the second backplane ; Injecting the first optical particle, the second optical particle and the third optical particle into the barrier to form the first optical sub-film layer, the second optical sub-film layer and the third optical sub-film layer.
  • the first optical particle may be a quantum dot particle of a second color
  • the second optical particle may be a quantum dot particle of a third color
  • the third optical particle may be a scattering particle.
  • step S410 forming a colloidal layer 31 on the side of the light-emitting chip layer away from the second backplane by coating or dispensing process, as shown in FIG. 8A , which is a schematic diagram of forming the colloidal layer.
  • Step S411 coating the black matrix film on the colloidal layer 31 , and processing the black matrix film through a patterning process to form the black matrix layer 32 , as shown in FIG. 8B , which is a schematic diagram after forming the black matrix layer.
  • the black matrix layer is provided with a first via hole exposing each sub-pixel in the light emitting chip.
  • Step S412 depositing a barrier film on the black matrix layer, patterning the barrier film through a patterning process to form a barrier 33, as shown in Figure 8C and Figure 8D,
  • Figure 8C is a schematic diagram after forming the barrier 1
  • FIG. 8D is the second schematic diagram after forming the retaining wall.
  • the blocking wall 33 may be opened with a second via hole exposing the first via hole, or the orthographic projection of the blocking wall 33 on the second backplane covers the first via hole on the second backplane Orthographic projection on .
  • FIG. 8C is an example of a second via hole exposing the first via hole in the retaining wall 33.
  • FIG. 8D is an orthographic projection of the retaining wall 33 on the second backplane covering the first via hole on the second The orthographic projection on the backplane is used as an example for illustration.
  • step S413 depositing the first optical film, the second optical film and the third optical film on the barrier wall, and patterning the first optical film through the patterning process.
  • the thin film is processed to form the first optical sub-film layer
  • the second optical film is processed through a patterning process to form a second optical sub-film layer
  • the third optical film is processed through a patterning process to form a third optical sub-film layer layer, as shown in FIG. 8E
  • FIG. 8E is a schematic diagram after forming an optical film layer.
  • step S413 injecting the first optical particle, the second optical particle and the third optical particle into the blocking wall 33
  • the optical particles form the first optical sub-film layer 341 , the second optical sub-film layer 342 and the third optical sub-film layer 343 , as shown in FIG. 8F .
  • FIG. 8F is a second schematic diagram after forming the optical film layer.
  • FIG. 9 is a schematic diagram after forming the encapsulation layer.
  • the method for preparing the display substrate may further include: sequentially forming an organic encapsulation layer 351 and a first inorganic encapsulation layer on the optical film layer 352.
  • FIG. 9A is a first schematic diagram after forming the first inorganic encapsulation layer provided by an exemplary embodiment
  • FIG. 9B is a schematic diagram after forming the first inorganic encapsulation layer provided by an exemplary embodiment.
  • Schematic diagram 2 FIG. 9C is a schematic diagram 3 provided by an exemplary embodiment after forming the first inorganic encapsulation layer
  • FIG. 9D is a schematic diagram 4 provided by an exemplary embodiment after forming the first inorganic encapsulation layer
  • FIG. 9E is The fifth schematic diagram provided by an exemplary embodiment after forming the first inorganic encapsulation layer
  • FIG. 9F is the sixth schematic diagram after the formation of the first inorganic encapsulation layer provided by an exemplary embodiment.
  • the manufacturing method of the display substrate may further include: sequentially forming an organic encapsulation layer 351 and a first inorganic encapsulation layer 352 on the optical film layer.
  • FIG. 9A takes the first backplane as the first backplane in FIG. 2A , the second backplane as the second backplane in FIG. 4A , and the retaining wall 33 is provided with a second via hole exposing the first via hole as an example. of.
  • FIG. 9B is that the first backplane is the first backplane of FIG. 2A , the second backplane is the second backplane of FIG.
  • Fig. 9C is an example to illustrate that the first backplane is the first backplane in Fig. 2C, the second backplane is the second backplane in Fig. 4B, and the retaining wall is provided with a second via hole exposing the first via hole .
  • the first backplane is the first backplane in Fig. 2C
  • the second backplane is the second backplane in Fig. 4B
  • the orthographic projection of the blocking wall on the second backplane covers the first via hole on the second backplane.
  • the orthographic projection on the board is used as an example for illustration.
  • Fig. 9E is illustrated by taking the first backplane as the first backplane in Fig. 2B, the second backplane as the second backplane in Fig. 4A and the retaining wall with the second via hole exposing the first via hole as an example.
  • the first backplane is the first backplane in Fig. 2B
  • the second backplane is the second backplane in Fig. 4A
  • the orthographic projection of the blocking wall on the second backplane covers the first via hole on the second backplane.
  • the orthographic projection on the board is used as an example for illustration.
  • FIG. 10A is a first schematic diagram after forming the first inorganic encapsulation layer provided by another exemplary embodiment
  • FIG. 10B is a schematic diagram after forming the first inorganic encapsulation layer provided by another exemplary embodiment.
  • Schematic diagram 2 FIG. 10C is a schematic diagram 3 provided by another exemplary embodiment after forming a first inorganic encapsulation layer
  • FIG. 10D is a schematic diagram 4 provided by another exemplary embodiment after forming a first inorganic encapsulation layer
  • FIG. 10E is Another exemplary embodiment provides the fifth schematic diagram after the formation of the first inorganic encapsulation layer
  • FIG. 10A is a first schematic diagram after forming the first inorganic encapsulation layer provided by another exemplary embodiment
  • FIG. 10B is a schematic diagram after forming the first inorganic encapsulation layer provided by another exemplary embodiment.
  • Schematic diagram 2 FIG. 10C is a schematic diagram 3 provided by another exemplary embodiment after forming a first inorganic encapsul
  • the preparation method of the display substrate may further include: forming a second inorganic encapsulation layer 353 on the optical film layer; forming a color filter layer on the second inorganic encapsulation layer 353; An organic encapsulation layer 351 and a first inorganic encapsulation layer 352 are sequentially formed on the color filter layer.
  • the color filter layer may include: a first color filter layer 361 , a second color filter layer 362 and a third color filter layer 363 .
  • the first color filter layer 361 corresponds to the first optical sub-film layer 341 one by one, and the orthographic projection of the first color filter layer 361 on the second backplane 20 covers the corresponding first optical sub-film layer. An orthographic projection of the film layer 341 on the second backplane 20 .
  • the second color filter layer 362 corresponds to the second optical sub-film layer 342 one by one, and the orthographic projection of the second color filter layer 362 on the second backplane 20 covers the corresponding second optical sub-film layer Orthographic projection of the film layer 342 on the second backplane 20 .
  • the third color filter layer 363 corresponds to the third optical sub-film layer 343 one by one, and the orthographic projection of the third color filter layer 363 on the second backplane 20 covers the corresponding third optical sub-film layer An orthographic projection of the film layer 343 on the second backplane 20 .
  • FIG. 10A takes the first backplane as the first backplane in FIG. 2A , the second backplane as the second backplane in FIG. 4A , and the retaining wall 33 is provided with a second via hole exposing the first via hole as an example.
  • Fig. 10B is that the first backplane is the first backplane of Fig. 2A, the second backplane is the second backplane of Fig. 4A and the orthographic projection of the retaining wall 33 on the second backplane covers the first via hole on the second backplane.
  • the orthographic projection on the backplane is used as an example for illustration.
  • Fig. 10C is an example of the first backplane being the first backplane in Fig.
  • the second backplane being the second backplane in Fig. 4B and the retaining wall having a second via hole exposing the first via hole.
  • the first backplane is the first backplane in Fig. 2C
  • the second backplane is the second backplane in Fig. 4B
  • the orthographic projection of the blocking wall on the second backplane covers the first via hole on the second backplane.
  • the orthographic projection on the board is used as an example for illustration.
  • Fig. 10E is illustrated by taking the first backplane as the first backplane in Fig. 2B, the second backplane as the second backplane in Fig. 4A and the retaining wall with the second via hole exposing the first via hole as an example. .
  • the first backplane is the first backplane in Fig. 2B
  • the second backplane is the second backplane in Fig. 4A
  • the orthographic projection of the blocking wall on the second backplane covers the first via hole on the second backplane.
  • the orthographic projection on the board is used as an example for illustration.
  • An embodiment of the present disclosure also provides a display substrate, which is prepared by a method for preparing a display substrate.
  • the method for preparing the display substrate is the method for preparing the display substrate provided in any one of the above-mentioned embodiments, and the realization principle and effect are similar, and will not be repeated here.
  • Embodiments of the present disclosure also provide a display device, which includes the display substrate provided by any embodiment.
  • the display substrate includes the display substrate provided by any one of the embodiments, and the implementation principle and effect are similar, and will not be repeated here.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种显示基板及其制备方法、显示装置，其中，显示基板的制备方法包括：提供第一衬底，在第一衬底上形成发光芯片层，以形成第一背板，发光芯片层包括：阵列排布的发光芯片，发光芯片设置为发射第一颜色的光线，发光芯片包括：N个子像素，N为大于或者等于1的正整数；提供第二衬底，在第二衬底上形成驱动电路层，以形成第二背板，驱动电路层包括：阵列排布的连接电极，发光芯片与连接电极一一对应；将剥离了第一衬底的第一背板转移至第二背板上；在发光芯片层远离第二背板的一侧形成光学膜层，光学膜层设置为将第一颜色的光线散射出去、将第一颜色的光线转换为第二颜色的光线和将第一颜色的光线转换为第三颜色的光线。

Description

一种显示基板及其制备方法、显示装置
本申请要求于2021年8月26日提交中国专利局、申请号为202110990952.2、发明名称为“一种显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引入的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，特别涉及一种显示基板及其制备方法、显示装置。
背景技术
半导体发光二极管(Light Emitting Diode，LED)技术发展了近三十年，从最初的固态照明电源到显示领域的背光源再到LED显示屏，为其更广泛的应用提供了坚实的基础。其中，随着芯片制作及封装技术的发展，采用亚毫米量级甚至微米量级的微LED的背光源得到了广泛的应用。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板的制备方法，所述方法包括：
提供第一衬底，在所述第一衬底上形成发光芯片层，以形成第一背板，发光芯片层包括：阵列排布的发光芯片，所述发光芯片设置为发射第一颜色的光线，所述发光芯片包括：N个子像素，N为大于或者等于1的正整数；
提供第二衬底，在所述第二衬底上形成驱动电路层，以形成第二背板，驱动电路层包括：阵列排布的连接电极，发光芯片与连接电极一一对应；
将剥离了第一衬底的第一背板转移至第二背板上，以使得发光芯片与对应的连接电极电连接；
在发光芯片层远离第二背板的一侧形成光学膜层，所述光学膜层设置为将第一颜色的光线散射出去、将第一颜色的光线转换为第二颜色的光线和将 第一颜色的光线转换为第三颜色的光线。
在一些可能的实现方式中，每个子像素包括：第一像素半导体层、第二像素半导体层、像素多量子阱层、第一电极和第二电极；
所述在所述第一衬底上形成发光芯片层包括：
在所述第一衬底的一侧依次生长缓冲层、第一半导体层、多量子阱层、第二半导体层、透明导电层、第一绝缘层和焊盘层；其中，第一半导体层包括:第一像素半导体层，多量子阱层包括：像素多量子阱层，第二半导体层包括：第二像素半导体层，透明导电层包括：第一电极，焊盘层包括：第二电极和焊盘，焊盘与第一电极连接；
当N大于1时，不同子像素的第一像素半导体层为同一膜层，不同子像素的像素多量子阱层、第二像素半导体层和第一电极均相互间隔设置，不同子像素的第二电极为同一电极，不同子像素的第一电极连接不同焊盘；
其中，焊盘在第一衬底上的正投影与焊盘所连接的第一电极在衬底上的正投影至少部分重叠或者不存在重叠区域。
在一些可能的实现方式中，所述在所述第二衬底上形成驱动电路层包括：
在所述第二衬底上依次形成驱动结构层、第一平坦层、金属导电层、第二绝缘层、第二平坦层和锡膏层；所述金属导电层包括：连接电极；锡膏层包括：阵列排布的锡膏结构；
当N＝1时，每个连接电极包括：第一子连接电极和第二子连接电极，第一子连接电极与对应的发光芯片中的第一电极电连接，第二子连接电极与对应的发光芯片中的第二电极电连接；
当N不等于1时，每个连接电极包括：N个第一子连接电极和一个第二子连接电极；N个第一子连接电极分别与对应的发光芯片中的N个子像素的第一电极电连接，第二连接电极与对应的发光芯片中的N个子像素的第二电极电连接；
每个子连接电极连接一个锡膏结构，不同子连接电极连接不同锡膏结构。
在一些可能的实现方式中，所述将剥离了第一衬底的第一背板转移至第二背板上包括：
将第一背板转移至第二背板上，以使得发光芯片与对应的连接电极电连接；
采用激光剥离工艺剥离第一衬底。
在一些可能的实现方式中，所述将剥离了第一衬底的第一背板转移至第二背板上包括：
将第一背板转移至第三背板上，以使得第三背板与发光芯片层键合；
采用激光剥离工艺剥离第一衬底；
剥离第三背板，将与第三背板键合的发光芯片层转移至第二背板上。
在一些可能的实现方式中，所述在发光芯片层远离第二背板的一侧形成光学膜层包括：
在发光芯片层远离第二背板的一侧采用涂覆或者点胶工艺形成胶体层；
在胶体层上形成黑矩阵层；所述黑矩阵层开设有暴露出发光芯片中的每个子像素的第一过孔；
在黑矩阵层上依次形成挡墙和光学膜层；所述光学膜层包括：第一光学子膜层、第二光学子膜层和第三光学子膜层；第一光学子膜层设置为将第一颜色的光线转换为第二颜色的光线，第二光学子膜层设置为将第一颜色的光线转换为第三颜色的光线，第三光学子膜层设置为将第一颜色的光线散射出去；
当N＝1时，每个子像素包括：第一光学子膜层、第二光学子膜层和第三光学子膜层中的其中一个膜层；相邻发光芯片的子像素包括的光学子膜层不同；
当N＝3时，位于同一发光芯片的三个子像素分别包括第一光学子膜层、第二光学子膜层和第三光学子膜层，位于不同发光芯片的三个子像素包括的光学子膜层相同，或者位于同一发光芯片的三个子像素包括同一光学子膜层，位于不同发光芯片的三个子像素包括的光学子膜层不同；
当N为不等于1，且不等于3的正整数时，位于同一发光芯片的三个子像素包括同一光学子膜层，位于不同发光芯片的三个子像素包括的光学子膜层不同；
每个子像素中的光学子膜层在第二背板上的正投影与每个子像素中的多量子阱层在第二背板上的正投影至少部分重叠。
在一些可能的实现方式中，所述在黑矩阵层上依次形成挡墙和光学膜层包括：
在黑矩阵层上形成挡墙，所述挡墙开设有暴露出第一过孔的第二过孔；
在挡墙上沉积第一光学薄膜、第二光学薄膜和第三光学薄膜，通过图案化工艺对第一光学薄膜进行处理，形成第一光学子膜层，通过图案化工艺对第二光学薄膜进行处理，形成第二光学子膜层，通过图案化工艺对第三光学薄膜进行处理，形成第三光学子膜层。
在一些可能的实现方式中，所述在黑矩阵层上依次形成挡墙和光学膜层包括：
在黑矩阵层上形成挡墙；所述挡墙在第二背板上的正投影覆盖第一过孔在第二背板上的正投影；
在挡墙中注入第一光学粒子，第二光学粒子和第三光学粒子，形成第一光学子膜层、第二光学子膜层和第三光学子膜层。
在一些可能的实现方式中，所述在发光芯片层远离第二背板的一侧形成光学膜层之后，所述方法还包括：
在光学膜层上依次形成有机封装层和第一无机封装层。
在一些可能的实现方式中，所述在发光芯片层远离第二背板的一侧形成光学膜层之后，所述方法还包括：
在光学膜层上形成第二无机封装层；
在第二无机封装层上形成彩膜层，所述彩膜层包括：第一彩膜层、第二彩膜层和第三彩膜层；第一彩膜层与第一光学子膜层一一对应，第一彩膜层在第二背板上的正投影覆盖对应的第一光学子膜层在第二背板上的正投影，第二彩膜层与第二光学子膜层一一对应，第二彩膜层在第二背板上的正投影覆盖对应的第二光学子膜层在第二背板上的正投影，第三彩膜层与第三光学子膜层一一对应，第三彩膜层在第二背板上的正投影覆盖对应的第三光学子膜层在第二背板上的正投影；
在彩膜层上依次形成有机封装层和第一无机封装层。
在一些可能的实现方式中，所述第一衬底为蓝宝石衬底。
第二方面，本公开还提供了一种显示基板，采用上述显示基板的制备方法制备。
第三方面，本公开还提供了一种显示装置，包括上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的显示基板的制备方法的流程图；
图2A为一种示例性实施例提供的第一背板的截面图；
图2B为另一示例性实施例提供的第一背板的截面图；
图2C为再一示例性实施例提供的第一背板的截面图；
图2D为又一示例性实施例提供的第一背板的截面图；
图2E为一种示例性实施例中子像素的排布方式的示意图；
图2F为一种示例性实施例中焊盘层的俯视图；
图3A为形成缓冲层后的示意图；
图3B为形成第一半导体层后的示意图；
图3C为形成多量子阱层后的示意图；
图3D为形成第二半导体层后的示意图；
图3E为形成透明导电层后的示意图；
图3F为形成绝缘层后的示意图；
图4A为一种示例性实施例提供的第二背板的示意图；
图4B为另一示例性实施例提供的第二背板的示意图；
图5A为形成驱动结构层后的示意图；
图5B为形成第一平坦层后的示意图；
图5C为形成金属导电层后的示意图；
图5D为形成第二绝缘层后的示意图；
图5E为形成第二平坦层后的示意图；
图6A至图6B为一种示例性实施例提供的步骤S3的示意图；
图7A至图7B为另一示例性实施例提供的步骤S3的示意图；
图8A为形成胶体层的示意图；
图8B为形成黑矩阵层后的示意图；
图8C为形成挡墙后的示意图一；
图8D为形成挡墙后的示意图二；
图8E为形成光学膜层后的示意图一；
图8F为形成光学膜层后的示意图二；
图9A为一种示例性实施例提供的形成第一无机封装层后的示意图一；
图9B为一种示例性实施例提供的形成第一无机封装层后的示意图二；
图9C为一种示例性实施例提供的形成第一无机封装层后的示意图三；
图9D为一种示例性实施例提供的形成第一无机封装层后的示意图四；
图9E为一种示例性实施例提供的形成第一无机封装层后的示意图五；
图9F为一种示例性实施例提供的形成第一无机封装层后的示意图六；
图10A为另一示例性实施例提供的形成第一无机封装层后的示意图一；
图10B为另一示例性实施例提供的形成第一无机封装层后的示意图二；
图10C为另一示例性实施例提供的形成第一无机封装层后的示意图三；
图10D为另一示例性实施例提供的形成第一无机封装层后的示意图四；
图10E为另一示例性实施例提供的形成第一无机封装层后的示意图五；
图10F为另一示例性实施例提供的形成第一无机封装层后的示意图六。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
微LED可以包括微型发光二极管(Micro Light Emitting Diode，Micro LED)和次毫米发光二极管(Mini Light Emitting Diode，Mini LED)，具有尺寸小、亮度高等优点，可以广泛应用于显示装置的背光模组中，利用微LED的显示产品的画面对比度可以达到有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示产品的水平，提升画面的显示效果，为用户提供更优质的视觉体验。此外，微LED显示逐渐成为显示面板的一个热点，主要应用在AR/VR、TV及户外显示等领域。
目前，微LED通常是通过将LED芯片用微缩制程技术进行微缩化、阵列化、薄膜化，通过巨量转移技术将LED芯片批量转移到驱动背板上。Micro LED的典型尺寸(例如长度)可以小于100μm，例如10μm至50μm。Mini LED 的典型尺寸(例如长度)可以约为100μm至300μm，例如120μm至260μm。
一种微LED显示基板中包括蓝宝石衬底以及设置在蓝宝石衬底上的阵列排布的发光芯片，由于发光芯片上蓝宝石的存在，使得不同发光芯片之间的距离较大，降低了微LED显示基板的分辨率和显示效果。
图1为本公开实施例提供的显示基板的制备方法的流程图。如图1所示，本公开实施例提供的显示基板的制备方法可以包括以下步骤：
步骤S1、提供第一衬底，在第一衬底上形成发光芯片层，以形成第一背板。
在一种示例性实施例中，发光芯片层包括：阵列排布的发光芯片，发光芯片设置为发射第一颜色的光线，发光芯片包括：N个子像素，N为大于或者等于1的正整数。
在一种示例性实施例中，发光芯片可以为Micro LED，或者Mini LED。
在一种示例性实施例中，第一颜色可以为蓝色，或者可以为红色或者绿色，本公开对此不作任何限定。
在一种示例性实施例中，发光芯片包括至少一个子像素时，至少一个子像素可以呈阵列排布，此时，发光芯片是以像素岛的形式存在。
在一种示例性实施例中，第一衬底可以包括：蓝宝石衬底、碳化硅衬底、硅衬底或者氮化镓衬底之一。当第一衬底为蓝宝石衬底时，第一衬底的厚度可以约为55微米至65微米，示例性地，第一衬底的厚度为60微米。
步骤S2、提供第二衬底，在第二衬底上形成驱动电路层，以形成第二背板。
在一种示例性实施例中，驱动电路层包括：阵列排布的连接电极，发光芯片与连接电极一一对应。
在一种示例性实施例中，驱动电路层可以设置为驱动发光芯片发光，第二背板即为驱动背板。
步骤S3、将剥离了第一衬底的第一背板转移至第二背板上，以使得发光芯片与对应的连接电极电连接。
在一种示例性实施例中，剥离了第一衬底的第一背板包括发光芯片层。
步骤S4、在发光芯片层远离第二背板的一侧形成光学膜层。
在一种示例性实施例中，光学膜层可以设置为将第一颜色的光线散射出去、将第一颜色的光线转换为第二颜色的光线和将第一颜色的光线转换为第三颜色的光线。
本公开通过光学膜层设置可以使得显示基板呈现各种不同的颜色，提升了显示基板的显示效果。
本公开在一个发光芯片可以实现了至少一个两个子像素，有利于实现高PPI设计，可以减轻多次固晶的尺寸压力，可以减少绑定次数，提高了产品良率。
本公开实施例提供的显示基板的制备方法包括：提供第一衬底，在第一衬底上形成发光芯片层，以形成第一背板，发光芯片层包括：阵列排布的发光芯片，发光芯片设置为发射第一颜色的光线，发光芯片包括：N个子像素，N为大于或者等于1的正整数；提供第二衬底，在第二衬底上形成驱动电路层，以形成第二背板，驱动电路层包括：阵列排布的连接电极，发光芯片与连接电极一一对应；将剥离了第一衬底的第一背板转移至第二背板上，以使得发光芯片与对应的连接电极电连接；在发光芯片层远离第二背板的一侧形成光学膜层，光学膜层设置为将第一颜色的光线散射出去、将第一颜色的光线转换为第二颜色的光线和将第一颜色的光线转换为第三颜色的光线。本公开通过将剥离了第一衬底的第一背板转移至第二背板上，在剥离了第一衬底的第一背板远离第二背板的一侧形成光学膜层可以减少发光芯片之间的距离，提升显示基板的分辨率和显示效果。
在一种示例性实施例中，图2A为一种示例性实施例提供的第一背板的截面图，图2B为另一示例性实施例提供的第一背板的截面图，图2C为再一示例性实施例提供的第一背板的截面图，图2D为又一示例性实施例提供的第一背板的截面图。如图2A至图2D所示。每个发光芯片包括：至少一个子像素100，每个子像素包括：第一像素半导体层12、第二像素半导体层140、像素多量子阱层130、第一电极150和第二电极18。图2A和图2B是以每个发光芯片包括三个子像素为例进行说明的。图2C是以每个发光芯片包括一 个子像素为例进行说明的。
图2E为一种示例性实施例中子像素的排布方式的示意图。如图2E所示，当子像素的数量为多个时，子像素可以采用水平并列、竖直并列、品字方式或者正方向方式排列，本公开在此不做限定。图2是以三个子像素采用品字方式排列为例进行说明的。
在一种示例性实施例中，当发光芯片包括的子像素为至少两个时，位于同一发光芯片中的不同子像素的尺寸可以不同，或者可以相同。图2A中的位于同一发光芯片中的不同子像素的尺寸不同，图2B中位于同一发光芯片中的子像素的尺寸相同。
在一种示例性实施例中，步骤S1可以包括：在第一衬底的一侧依次生长缓冲层19、第一半导体层12、多量子阱层13、第二半导体层14、透明导电层15、第一绝缘层16和焊盘层17。其中，多量子阱层13包括：像素多量子阱层130，第二半导体层14包括：第二像素半导体层140，透明导电层15包括：第一电极150，焊盘层17包括：第二电极18和焊盘170，焊盘170与第一电极150连接。
如图2A和图2B所示，当N大于1时，不同子像素的第一半导体层为同一膜层，不同子像素的多量子阱层、第二半导体层和第一电极均相互间隔设置，不同子像素的第二电极为同一电极，不同子像素的第一电极连接不同焊盘。
在一种示例性实施例中，焊盘170在第一衬底11上的正投影与焊盘170所连接的第一电极150在衬底上的正投影可以至少部分重叠或者可以不存在重叠区域。图2A至图2C是以焊盘170在第一衬底11上的正投影与焊盘170所连接的第一电极150在衬底上的正投影可以至少部分重叠为例进行说明的。图2D是以焊盘170在第一衬底11上的正投影与焊盘170所连接的第一电极150在衬底上的正投影不存在重叠区域为例进行说明的。其中，图2D是以发光芯片包括一个子像素为例进行说明的，发光芯片还可以包括多个子像素，本公开并不以此为例。本公开中焊盘和第一电极的位置关系可以使得显示基板的设置更加灵活。
图2F为一种示例性实施例中焊盘层的俯视图。如图2F所示，当子像素 的数量为三个时，焊盘170与第二电极18的分布方式可以为方形或者其他形状，本公开对此不作任何限定。如图2F是以焊盘170与第二电极18的分布方式为方形为例进行说明的。
在一种示例性实施例中，当焊盘170在第一衬底11上的正投影与焊盘170所连接的第一电极150在衬底上的正投影不存在重叠区域时，在形成焊盘层之间，步骤S1还可以包括：形成配置为连接焊盘和第一电极的连接导线。
在一种示例性实施例中，缓冲层19的折射率范围可以为2至3，示例性地，缓冲层72的折射率可以约为2.54。缓冲层72的制作材料可以包括氮化镓(GaN)。缓冲层18的厚度可以约为2μm。
在一种示例性实施例中，第一半导体层12可以为N型掺杂的氮化镓，第二电极可以为N电极，第二半导体层14可以为P型掺杂的氮化镓，第一电极可以为P电极，或者第一半导体层12可以为P型掺杂的氮化镓，第二电极可以为P电极，第二半导体层14可以为N型掺杂的氮化镓，第一电极可以为N电极。第一半导体层12的厚度可以约为2μm。第一半导体层14的厚度可以约为2μm。
在一种示例性实施例中，多量子阱层13的厚度可以约为0.3μm。
在一种示例性实施例中，第一半导体层12的厚度、多量子阱层13的厚度、第二半导体层14的厚度均可以根据实际工艺需求设置。
在一种示例性实施例中，第一绝缘层16可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。
下面以形成图2A所示的第一背板为例，结合通过图3A至图3F说明本公开实施例的技术方案。可以理解的是，本公开中所说的“图案化工艺”，当图案化的材质为无机材质或金属时，“图案化”包括涂覆光刻胶、掩膜曝光、显影、刻蚀、剥离光刻胶等工艺，当图案化的材质为有机材质时，“图案化”包括掩模曝光、显影等工艺，本公开中所说的蒸镀、沉积、涂覆、涂布等均是相关技术中成熟的制备工艺。
步骤S11、提供第一衬底11，在第一衬底11的一侧沉积缓冲薄膜，通过图案化工艺在第一衬底上生成缓冲层19，如图3A所示，图3A为形成缓冲层后的示意图。
步骤S12、在缓冲层19上沉积第一半导体薄膜，通过图案化工艺对缓冲薄膜进行处理，形成第一半导体层12，如图3B所示，图3B为形成第一半导体层后的示意图。
在一种示例性实施例中，第一半导体层远离第一衬底的表面不平坦。
步骤S13、在第一半导体层12上沉积多量子阱薄膜，通过图案化工艺对多量子阱薄膜进行处理，形成多量子阱层13，如图3C所示，图3C为形成多量子阱层后的示意图。
步骤S14、在多量子阱层13上沉积第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行处理，形成第二半导体层14，如图3D所示，图3D为形成第二半导体层后的示意图。
步骤S15、在第二半导体层14上沉积透明导电薄膜，通过图案化工艺对透明导电薄膜进行处理，形成透明导电层15，如图3E所示，图3E为形成透明导电层后的示意图。
步骤S16、在透明导电层15上沉积第一绝缘薄膜，通过图案化工艺对绝缘薄膜进行处理，形成第一绝缘层16，如图3F所示，图3F为形成绝缘层后的示意图。
步骤S17、在第一绝缘层16上沉积导电层，通过图案化工艺对导电层进行处理，形成焊盘层17，如图2A所示。
在一种示例性实施例中，图4A为一种示例性实施例提供的第二背板的示意图，图4B为另一示例性实施例提供的第二背板的示意图。如图4A和图4B所示，第二背板包括：设置在第二衬底21上的驱动结构层22、第一平坦层23、金属导电层24、第二绝缘层25、第二平坦层26和锡膏层27。
在一种示例性实施例中，步骤S2可以包括：在第二衬底上依次形成驱动结构层、第一平坦层、金属导电层、第二绝缘层、第二平坦层和锡膏层。金属导电层包括：连接电极200和电源线243；锡膏层包括：阵列排布的锡 膏结构700。发光芯片不同，发光芯片连接的连接电极的结构也不相同。
在一种示例性实施例中，电源线243设置为持续地提供高电平信号。
当N＝1时，即发光芯片包括一个子像素时，每个连接电极200包括：第一子连接电极241和第二子连接电极242。第一子连接电极与对应的发光芯片中的第一电极电连接，第二子连接电极与对应的发光芯片中的第二电极电连接。图2B是以N＝1为例进行说明的。
当N不等于1时，即发光芯片包括至少两个子像素时，每个连接电极包括：N个第一子连接电极241和一个第二子连接电极242；N个第一子连接电极分别与对应的发光芯片中的N个子像素的第一电极电连接，第二连接电极与对应的发光芯片中的N个子像素的第二电极电连接；图2A是以N不等于1为例进行说明的。
在一种示例性实施例中，每个子连接电极连接一个锡膏结构，不同子连接电极连接不同锡膏结构。
在一种示例性实施例中，驱动结构层包括多个薄膜晶体管。薄膜晶体管包括：有源层、栅电极、源电极和漏电极。薄膜晶体管可以为顶栅结构或者可以为底栅结构，本公开对此不作任何限定。
在一种示例性实施例中，第一平坦层和第二平坦层的制作材料可以采用有机材料。
在一种示例性实施例中，金属导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在一种示例性实施例中，第二绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。
下面以形成图4A所示的第二背板为例，结合通过图5A至图5E说明本公开实施例的技术方案。
步骤S21、提供第二衬底21，在第二衬底21的一侧形成驱动结构层22， 如图5A所示，图5A为形成驱动结构层后的示意图。
在一种示例性实施例中，形成驱动结构层可以包括：依次形成有源层、栅绝缘层、栅电极、层间绝缘层、源漏电极和钝化层，或者依次形成栅电极、栅绝缘层、有源层、源漏电极和钝化层。
步骤S22、在驱动结构层22上涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行处理，形成第一平坦层23，如图5B所示，图5B为形成第一平坦层后的示意图。
步骤S23、在第一平坦层23上沉积金属导电薄膜，通过图案化工艺对金属导电薄膜进行处理，形成金属导电层24，如图5C所示，图5C为形成金属导电层后的示意图。
步骤S24、在金属导电层24上沉积第二绝缘薄膜，通过图案化工艺对第二绝缘薄膜进行处理，形成第二绝缘层25，如图5D所示，图5D为形成第二绝缘层后的示意图。
在一种示例性实施例中，第二绝缘层开设有暴露出金属导电层中的连接部的过孔。
步骤S25、在第二绝缘层25上涂覆第二平坦薄膜，通过图案化工艺对第二平坦薄膜进行处理，形成第二平坦层26，如图5E所示，图5E为形成第二平坦层后的示意图。
在一种示例性实施例中，第二平坦层26上可以开设有暴露出绝缘层25过孔的过孔。
步骤S26、在第二平坦层26上采用点焊工艺形成锡膏层27，如图4A所示。
在一种示例性实施例中，步骤S3可以包括：将第一背板转移至第二背板；使得发光芯片与对应的连接电极电连接；采用激光剥离工艺剥离第一衬底。
在另一示例性实施例中，步骤S3可以包括：将第一背板转移至第三背板上，以使得第三背板与发光芯片层键合；采用激光剥离工艺剥离第一衬底；剥离第三背板，将与第三背板键合的发光芯片层转移至第二背板上。
以上两种实施例均可以剥离第一背板上的第一衬底，第一个实施例是在第一背板转移至第二背板之后进行剥离，第二个实施例是在第一背板转移至第二背板之前进行剥离。
下面通过图6A至图6B说明一种示例性实施例提供的步骤S3。
步骤S310、将第一背板10转移至第二背板20上，以使得发光芯片与对应的连接电极电连接，如图6A所示。
步骤S311、采用激光剥离工艺剥离第一衬底，如图6B所示。
下面通过图7A至图7B说明另一示例性实施例提供的步骤S3。
步骤S320、将第一背板10转移至第三背板30上，如图7A所示。
步骤S321、采用激光剥离工艺剥离第一衬底，如图7B所示。
步骤S322、剥离第三背板，将与第三背板键合的发光芯片层转移至第二背板上，如图6B所示。
图6和图7中的第一背板为简化后的第一背板，实际上结构为图2A的结构，第一背板还可以是图2B或者图2C的结构。其中，中间膜层110包括：从上到下依次设置的缓冲层、第一半导体层、多量子阱层、第二半导体层、透明导电层和绝缘层。
在一种示例性实施例中，步骤S4可以包括以下步骤：
步骤S41、在发光芯片层远离第二背板的一侧采用涂覆或者点胶工艺形成胶体层。
在一种示例性实施例中，胶体层的厚度可以约为10um，胶体层可以起到保护固定发光芯片层的作用。胶体层的制作材料可以为有机硅灌封胶或者环氧树脂。
步骤S42、在胶体层上形成黑矩阵层。
在一种示例性实施例中，黑矩阵层开设有暴露出发光芯片中的每个子像素的第一过孔。
步骤S43、在黑矩阵层上依次形成挡墙和光学膜层。
在一种示例性实施例中，光学膜层包括：第一光学子膜层、第二光学子 膜层和第三光学子膜层；第一光学子膜层设置为将第一颜色的光线转换为第二颜色的光线，第二光学子膜层设置为将第一颜色的光线转换为第三颜色的光线，第三光学子膜层设置为将第一颜色的光线散射出去。
在一种示例性实施例中，第一光学子膜层可以包括：第二颜色量子点材料。第二光学子膜层可以包括：第三颜色量子点材料。
在一种示例性实施例中，第三光学子膜层可以包括散射粒子，散射粒子可以为高折射率材料颗粒，散射粒子的折射率可以大于或等于1.7，散射粒子的材质可以为含硅烷的树脂材料。
在一种示例性实施例中，第二颜色的光线由第一光学子膜层在发光芯片的激发下产生，第三颜色的光线由第二光学子膜层在发光芯片的激发下产生，所以，产生的第二颜色和第三颜色的光型一致，而第一颜色由发光芯片直接产生，因此，第一颜色的光型与第二颜色和第三颜色光型存在不一致。通过设置第三光学子膜层，可以改善显示的第一颜色的光型，提高第一颜色、第二颜色和第三颜色在同一角度的光强一致性，提高显示效果。
在一种示例性实施例中，第一光学子膜层、第二光学子膜层和第三光学子膜层的厚度可以相同。这样可以提高第一颜色、第二颜色和第三颜色的光程一致性，可以提高显示效果。
在一种示例性实施例中，N＝1时，每个子像素包括：第一光学子膜层、第二光学子膜层和第三光学子膜层中的其中一个膜层；相邻发光芯片的子像素包括的光学子膜层不同。
在一种示例性实施例中，当N＝3时，位于同一发光芯片的三个子像素分别包括第一光学子膜层、第二光学子膜层和第三光学子膜层，位于不同发光芯片的三个子像素包括的光学子膜层相同，或者位于同一发光芯片的三个子像素包括同一光学子膜层，位于不同发光芯片的三个子像素包括的光学子膜层不同。
在一种示例性实施例中，当N为不等于1，且不等于3的正整数时，位于同一发光芯片的三个子像素包括同一光学子膜层，位于不同发光芯片的三个子像素包括的光学子膜层不同。
在一种示例性实施例中，每个子像素中的光学子膜层在第二背板上的正投影与每个子像素中的多量子阱层在第二背板上的正投影至少部分重叠。
在一种示例性实施例中，相邻子像素的光学子膜层之间的距离约为20微米。
在一种示例性实施例中，步骤S43可以包括：在黑矩阵层上形成挡墙，所述挡墙开设有暴露出第一过孔的第二过孔；在挡墙上沉积第一光学薄膜、第二光学薄膜和第三光学薄膜，通过图案化工艺对第一光学薄膜进行处理，形成第一光学子膜层，通过图案化工艺对第二光学薄膜进行处理，形成第二光学子膜层，通过图案化工艺对第三光学薄膜进行处理，形成第三光学子膜层。
在另一示例性实施例中，步骤S43可以包括：在黑矩阵层上形成挡墙；所述挡墙在第二背板上的正投影覆盖第一过孔在第二背板上的正投影；在挡墙中注入第一光学粒子，第二光学粒子和第三光学粒子，形成第一光学子膜层、第二光学子膜层和第三光学子膜层。
在一种示例性实施例中，第一光学粒子可以为第二颜色量子点粒子，第二光学粒子可以为第三颜色量子点粒子，第三光学粒子可以为散射粒子。
下面通过图8A至图8F说明一种示例性实施例提供的步骤S4的技术方案。步骤S410、在发光芯片层上远离第二背板的一侧采用涂覆或者点胶工艺形成胶体层31，如图8A所示，图8A为形成胶体层的示意图。
步骤S411、在胶体层31上涂覆黑矩阵薄膜，通过图案化工艺对黑矩阵薄膜进行处理，形成黑矩阵层32，如图8B所示，图8B为形成黑矩阵层后的示意图。
一种示例性实施例中，黑矩阵层开设有暴露出发光芯片中的每个子像素的第一过孔。
步骤S412、在黑矩阵层上沉积挡墙薄膜，通过构图工艺对挡墙薄膜进行图案化处理，形成挡墙33，如图8C和图8D所示，图8C为形成挡墙后的示意图一，图8D为形成挡墙后的示意图二。
在一种示例性实施例中，挡墙33可以开设有暴露出第一过孔的第二过孔， 或者挡墙33在第二背板上的正投影覆盖第一过孔在第二背板上的正投影。图8C是以挡墙33开设有暴露出第一过孔的第二过孔为例进行说明的，图8D是以挡墙33在第二背板上的正投影覆盖第一过孔在第二背板上的正投影为例进行说明的。
当挡墙33开设有暴露出第一过孔的第二过孔时，步骤S413、在挡墙上沉积第一光学薄膜、第二光学薄膜和第三光学薄膜，通过图案化工艺对第一光学薄膜进行处理，形成第一光学子膜层，通过图案化工艺对第二光学薄膜进行处理，形成第二光学子膜层，通过图案化工艺对第三光学薄膜进行处理，形成第三光学子膜层，如图8E所示，图8E为形成光学膜层后的示意图一。
当挡墙33在第二背板上的正投影覆盖第一过孔在第二背板上的正投影时，步骤S413、在挡墙33中注入第一光学粒子，第二光学粒子和第三光学粒子，形成第一光学子膜层341、第二光学子膜层342和第三光学子膜层343，如图8F所示，图8F为形成光学膜层后的示意图二。
在一种示例性实施例中，图9为形成封装层后的示意图一，步骤S4之后，显示基板的制备方法还可以包括：在光学膜层上依次形成有机封装层351和第一无机封装层352。
在一种示例性实施例中，图9A为一种示例性实施例提供的形成第一无机封装层后的示意图一，图9B为一种示例性实施例提供的形成第一无机封装层后的示意图二，图9C为一种示例性实施例提供的形成第一无机封装层后的示意图三，图9D为一种示例性实施例提供的形成第一无机封装层后的示意图四，图9E为一种示例性实施例提供的形成第一无机封装层后的示意图五，图9F为一种示例性实施例提供的形成第一无机封装层后的示意图六。如图9A至图9F所示，步骤S4之后，显示基板的制备方法还可以包括：在光学膜层上依次形成有机封装层351和第一无机封装层352。图9A是以第一背板为图2A的第一背板，第二背板为图4A的第二背板以及挡墙33开设有暴露出第一过孔的第二过孔为例进行说明的。图9B是以第一背板为图2A的第一背板，第二背板为图4A的第二背板以及挡墙33在第二背板上的正投影覆盖第一过孔在第二背板上的正投影为例进行说明的。图9C是以第一背板为图2C的第一背板，第二背板为图4B的第二背板以及挡墙开设有暴露出第 一过孔的第二过孔为例进行说明的。图9D是以第一背板为图2C的第一背板，第二背板为图4B的第二背板以及挡墙在第二背板上的正投影覆盖第一过孔在第二背板上的正投影为例进行说明的。图9E是以第一背板为图2B的第一背板，第二背板为图4A的第二背板以及挡墙开设有暴露出第一过孔的第二过孔为例进行说明的。图9F是以第一背板为图2B的第一背板，第二背板为图4A的第二背板以及挡墙在第二背板上的正投影覆盖第一过孔在第二背板上的正投影为例进行说明的。
在一种示例性实施例中，图10A为另一示例性实施例提供的形成第一无机封装层后的示意图一，图10B为另一示例性实施例提供的形成第一无机封装层后的示意图二，图10C为另一示例性实施例提供的形成第一无机封装层后的示意图三，图10D为另一示例性实施例提供的形成第一无机封装层后的示意图四，图10E为另一示例性实施例提供的形成第一无机封装层后的示意图五，图10F为另一示例性实施例提供的形成第一无机封装层后的示意图六。如图10A至图10F所示，步骤S4之后，显示基板的制备方法还可以包括：在在光学膜层上形成第二无机封装层353；在第二无机封装层353上形成彩膜层；在彩膜层上依次形成有机封装层351和第一无机封装层352。
在一种示例性实施例中，如图10A至图10F所示，彩膜层可以包括：第一彩膜层361、第二彩膜层362和第三彩膜层363。
在一种示例性实施例中，第一彩膜层361与第一光学子膜层341一一对应，第一彩膜层361在第二背板20上的正投影覆盖对应的第一光学子膜层341在第二背板20上的正投影。
在一种示例性实施例中，第二彩膜层362与第二光学子膜层342一一对应，第二彩膜层362在第二背板20上的正投影覆盖对应的第二光学子膜层342在第二背板20上的正投影。
在一种示例性实施例中，第三彩膜层363与第三光学子膜层343一一对应，第三彩膜层363在第二背板20上的正投影覆盖对应的第三光学子膜层343在第二背板20上的正投影。
图10A是以第一背板为图2A的第一背板，第二背板为图4A的第二背板以及挡墙33开设有暴露出第一过孔的第二过孔为例进行说明的。图10B 是以第一背板为图2A的第一背板，第二背板为图4A的第二背板以及挡墙33在第二背板上的正投影覆盖第一过孔在第二背板上的正投影为例进行说明的。图10C是以第一背板为图2C的第一背板，第二背板为图4B的第二背板以及挡墙开设有暴露出第一过孔的第二过孔为例进行说明的。图10D是以第一背板为图2C的第一背板，第二背板为图4B的第二背板以及挡墙在第二背板上的正投影覆盖第一过孔在第二背板上的正投影为例进行说明的。图10E是以第一背板为图2B的第一背板，第二背板为图4A的第二背板以及挡墙开设有暴露出第一过孔的第二过孔为例进行说明的。图10F是以第一背板为图2B的第一背板，第二背板为图4A的第二背板以及挡墙在第二背板上的正投影覆盖第一过孔在第二背板上的正投影为例进行说明的。
本公开实施例还提供了一种显示基板，显示基板采用显示基板的制备方法制备。
显示基板的制备方法为上述任一个实施例提供的显示基板的制备方法，实现原理和实现效果类似，在此不再赘述。
本公开实施例还提供了一种显示装置，显示装置包括任一个实施例提供的显示基板。
显示基板包括任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人 员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种显示基板的制备方法，所述方法包括：
    提供第一衬底，在所述第一衬底上形成发光芯片层，以形成第一背板，发光芯片层包括：阵列排布的发光芯片，所述发光芯片设置为发射第一颜色的光线，所述发光芯片包括：N个子像素，N为大于或者等于1的正整数；
    提供第二衬底，在所述第二衬底上形成驱动电路层，以形成第二背板，驱动电路层包括：阵列排布的连接电极，发光芯片与连接电极一一对应；
    将剥离了第一衬底的第一背板转移至第二背板上，以使得发光芯片与对应的连接电极电连接；
    在发光芯片层远离第二背板的一侧形成光学膜层，所述光学膜层设置为将第一颜色的光线散射出去、将第一颜色的光线转换为第二颜色的光线和将第一颜色的光线转换为第三颜色的光线。
  2. 根据权利要求1所述的方法，其中，每个子像素包括：第一像素半导体层、第二像素半导体层、像素多量子阱层、第一电极和第二电极；
    所述在所述第一衬底上形成发光芯片层包括：
    在所述第一衬底的一侧依次生长缓冲层、第一半导体层、多量子阱层、第二半导体层、透明导电层、第一绝缘层和焊盘层；其中，第一半导体层包括：第一像素半导体层，多量子阱层包括：像素多量子阱层，第二半导体层包括：第二像素半导体层，透明导电层包括：第一电极，焊盘层包括：第二电极和焊盘，焊盘与第一电极连接；
    当N大于1时，不同子像素的第一像素半导体层为同一膜层，不同子像素的像素多量子阱层、第二像素半导体层和第一电极均相互间隔设置，不同子像素的第二电极为同一电极，不同子像素的第一电极连接不同焊盘；
    其中，焊盘在第一衬底上的正投影与焊盘所连接的第一电极在衬底上的正投影至少部分重叠或者不存在重叠区域。
  3. 根据权利要求2所述的方法，其中，所述在所述第二衬底上形成驱动电路层包括：
    在所述第二衬底上依次形成驱动结构层、第一平坦层、金属导电层、第二绝缘层、第二平坦层和锡膏层；所述金属导电层包括：连接电极；锡膏层包括：阵列排布的锡膏结构；
    当N＝1时，每个连接电极包括：第一子连接电极和第二子连接电极，第一子连接电极与对应的发光芯片中的第一电极电连接，第二子连接电极与对应的发光芯片中的第二电极电连接；
    当N不等于1时，每个连接电极包括：N个第一子连接电极和一个第二子连接电极；N个第一子连接电极分别与对应的发光芯片中的N个子像素的第一电极电连接，第二连接电极与对应的发光芯片中的N个子像素的第二电极电连接；
    每个子连接电极连接一个锡膏结构，不同子连接电极连接不同锡膏结构。
  4. 根据权利要求1所述的方法，其中，所述将剥离了第一衬底的第一背板转移至第二背板上包括：
    将第一背板转移至第二背板上，以使得发光芯片与对应的连接电极电连接；
    采用激光剥离工艺剥离第一衬底。
  5. 根据权利要求1所述的方法，其中，所述将剥离了第一衬底的第一背板转移至第二背板上包括：
    将第一背板转移至第三背板上，以使得第三背板与发光芯片层键合；
    采用激光剥离工艺剥离第一衬底；
    剥离第三背板，将与第三背板键合的发光芯片层转移至第二背板上。
  6. 根据权利要求1所述的方法，其中，所述在发光芯片层远离第二背板的一侧形成光学膜层包括：
    在发光芯片层远离第二背板的一侧采用涂覆或者点胶工艺形成胶体层；
    在胶体层上形成黑矩阵层；所述黑矩阵层开设有暴露出发光芯片中的每个子像素的第一过孔；
    在黑矩阵层上依次形成挡墙和光学膜层；所述光学膜层包括：第一光学 子膜层、第二光学子膜层和第三光学子膜层；第一光学子膜层设置为将第一颜色的光线转换为第二颜色的光线，第二光学子膜层设置为将第一颜色的光线转换为第三颜色的光线，第三光学子膜层设置为将第一颜色的光线散射出去；
    当N＝1时，每个子像素包括：第一光学子膜层、第二光学子膜层和第三光学子膜层中的其中一个膜层；相邻发光芯片的子像素包括的光学子膜层不同；
    当N＝3时，位于同一发光芯片的三个子像素分别包括第一光学子膜层、第二光学子膜层和第三光学子膜层，位于不同发光芯片的三个子像素包括的光学子膜层相同，或者位于同一发光芯片的三个子像素包括同一光学子膜层，位于不同发光芯片的三个子像素包括的光学子膜层不同；
    当N为不等于1，且不等于3的正整数时，位于同一发光芯片的三个子像素包括同一光学子膜层，位于不同发光芯片的三个子像素包括的光学子膜层不同；
    每个子像素中的光学子膜层在第二背板上的正投影与每个子像素中的多量子阱层在第二背板上的正投影至少部分重叠。
  7. 根据权利要求6所述的方法，其中，所述在黑矩阵层上依次形成挡墙和光学膜层包括：
    在黑矩阵层上形成挡墙，所述挡墙开设有暴露出第一过孔的第二过孔；
    在挡墙上沉积第一光学薄膜、第二光学薄膜和第三光学薄膜，通过图案化工艺对第一光学薄膜进行处理，形成第一光学子膜层，通过图案化工艺对第二光学薄膜进行处理，形成第二光学子膜层，通过图案化工艺对第三光学薄膜进行处理，形成第三光学子膜层。
  8. 根据权利要求6所述的方法，其中，所述在黑矩阵层上依次形成挡墙和光学膜层包括：
    在黑矩阵层上形成挡墙；所述挡墙在第二背板上的正投影覆盖第一过孔在第二背板上的正投影；
    在挡墙中注入第一光学粒子，第二光学粒子和第三光学粒子，形成第一 光学子膜层、第二光学子膜层和第三光学子膜层。
  9. 根据权利要求1所述的方法，其中，所述在发光芯片层远离第二背板的一侧形成光学膜层之后，所述方法还包括：
    在光学膜层上依次形成有机封装层和第一无机封装层。
  10. 根据权利要求1所述的方法，其中，所述在发光芯片层远离第二背板的一侧形成光学膜层之后，所述方法还包括：
    在光学膜层上形成第二无机封装层；
    在第二无机封装层上形成彩膜层，所述彩膜层包括：第一彩膜层、第二彩膜层和第三彩膜层；第一彩膜层与第一光学子膜层一一对应，第一彩膜层在第二背板上的正投影覆盖对应的第一光学子膜层在第二背板上的正投影，第二彩膜层与第二光学子膜层一一对应，第二彩膜层在第二背板上的正投影覆盖对应的第二光学子膜层在第二背板上的正投影，第三彩膜层与第三光学子膜层一一对应，第三彩膜层在第二背板上的正投影覆盖对应的第三光学子膜层在第二背板上的正投影；
    在彩膜层上依次形成有机封装层和第一无机封装层。
  11. 根据权利要求1所述的方法，其中，所述第一衬底为蓝宝石衬底。
  12. 一种显示基板，采用权利要求1至10任一项所述的显示基板的制备方法制备。
  13. 一种显示装置，包括权利要求12所述的显示基板。
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