WO2023071560A1 - Module d'affichage et dispositif d'affichage - Google Patents

Module d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2023071560A1
WO2023071560A1 PCT/CN2022/118386 CN2022118386W WO2023071560A1 WO 2023071560 A1 WO2023071560 A1 WO 2023071560A1 CN 2022118386 W CN2022118386 W CN 2022118386W WO 2023071560 A1 WO2023071560 A1 WO 2023071560A1
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WO
WIPO (PCT)
Prior art keywords
pixel
circuit
sub
display module
layer
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PCT/CN2022/118386
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English (en)
Chinese (zh)
Inventor
叶成亮
刘长瑜
郭天福
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Oppo广东移动通信有限公司
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Publication of WO2023071560A1 publication Critical patent/WO2023071560A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, in particular to a display module and a display device.
  • a display module and a display device are provided.
  • a display module comprising:
  • a pixel circuit array including a plurality of first pixel sub-circuits, a plurality of second pixel sub-circuits and circuit wiring, each of the second pixel sub-circuits is respectively located in two adjacent first pixels in the first direction Between the sub-circuits, the first direction is perpendicular to the thickness direction of the display module;
  • a light emitting device array the size of the light emitting device array in the first direction is larger than the size of the pixel circuit array in the first direction, the light emitting device array includes a plurality of light emitting devices, the light emitting device includes a cathode and an anode, The anodes of the plurality of light-emitting devices are respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence;
  • the circuit wiring is connected to the cathodes of a plurality of the light emitting devices.
  • a display device comprising: the above-mentioned display module.
  • FIG. 1 is one of the structural schematic diagrams of a display module of an embodiment
  • FIG. 2 is one of the structural schematic diagrams of a pixel circuit array according to an embodiment
  • Fig. 3 is a schematic structural diagram of a light emitting device array according to an embodiment
  • FIG. 4 is a schematic structural diagram of a display module without a second pixel sub-circuit
  • FIG. 5 is a schematic cross-sectional view of a display module according to an embodiment
  • Fig. 6 is a schematic structural view of a first repeating unit and a corresponding light-emitting device in an embodiment
  • FIG. 7 is a circuit diagram of a first pixel sub-circuit according to an embodiment
  • FIG. 8 is one of partial structural schematic diagrams of a display module of an embodiment
  • FIG. 9 is a schematic cross-sectional view of the display module of the embodiment in FIG. 8;
  • FIG. 10 is a second schematic diagram of a partial structure of a display module of an embodiment
  • FIG. 11 is a schematic cross-sectional view of the display module of the embodiment in FIG. 10;
  • FIG. 12 is a third schematic diagram of a partial structure of a display module of an embodiment
  • FIG. 13 is a schematic cross-sectional view of the display module of the embodiment in FIG. 12;
  • FIG. 14 is one of the simplified cross-sectional schematic diagrams of a display module according to an embodiment
  • FIG. 15 is a second simplified cross-sectional schematic diagram of a display module of an embodiment
  • FIG. 16 is the second structural schematic diagram of a pixel circuit array in an embodiment
  • FIG. 17 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 16;
  • FIG. 18 is a third schematic structural diagram of a pixel circuit array in an embodiment
  • FIG. 19 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 18;
  • FIG. 20 is a fourth schematic structural diagram of a pixel circuit array in an embodiment
  • FIG. 21 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 20 .
  • Pixel circuit array 100; circuit routing: 101; first sub-array area: 110; first pixel circuit: 111; first gate layer: 1101a; second gate layer: 1101b; first source: 1102; First drain: 1103; source contact structure: 1104; drain contact structure: 1105; pixel definition layer: 1106; anode layer: 1107; luminescent material layer: 1108; cathode layer: 1109; substrate: 1110; polyimide Amine (PI) substrate layer: 1110a; first buffer layer: 1110b; first gate insulating layer: 1111; second gate insulating layer: 1112; interlayer insulating layer: 1113; planarization layer: 1114; second pixel circuit: 112; the first metallization hole: 1121; the second metallization hole: 1122; the third metallization hole: 1123; the first repeating unit: 113; the second sub-array area: 120; the third sub-array area: 130; Three-pixel circuit: 131; fourth sub-array area: 140; fourth
  • first, second and the like used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.
  • a first direction could be termed a second direction, and, similarly, a second direction could be termed a first direction, without departing from the scope of the present application.
  • Both the first direction and the second direction are directions, but they are not the same direction.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • plural means at least two, such as two, three, etc., unless otherwise specifically defined.
  • severeal means at least one, such as one, two, etc., unless otherwise specifically defined.
  • FIG. 1 is one of the structural schematic diagrams of a display module according to an embodiment.
  • the display module according to this embodiment includes a pixel circuit array and a light emitting device array.
  • the display module of the embodiment of the present application is applied to a display device with a narrow frame.
  • the display device may be a smart phone, a tablet computer, a game device, an augmented reality (Augmented Reality, AR) device, a notebook, a desktop computing device, a wearable device, and the like.
  • AR Augmented Reality
  • FIG. 2 is one of the structural schematic diagrams of a pixel circuit array in an embodiment
  • FIG. 3 is a structural schematic diagram of a light emitting device array in an embodiment.
  • the pixel circuit array 100 and the light emitting device array 200 are stacked in the thickness direction of the display device to form Display mods.
  • the size of the light emitting device array 200 in the first direction is larger than the size of the pixel circuit array 100 in the first direction. It can be understood that, compared with the 1:1 arrangement of the size of the light emitting device array 200 and the pixel circuit array 100, based on the size setting method of this embodiment, the size of the light emitting device array 200 can be kept unchanged, By relatively reducing the size of the pixel circuit array 100 , a certain space is provided for arranging other peripheral circuits.
  • Other peripheral circuits include but are not limited to gate drive circuits, fan-out wire group 500 and so on.
  • other peripheral circuits and the pixel circuit array 100 can be arranged in the same layer, and the light emitting device array 200 can be partially arranged on other peripheral circuits.
  • the size difference between the light emitting device array 200 and the pixel circuit array 100 determines the specific area where other peripheral circuits can be arranged under the light emitting device array 200 . That is, the smaller the size of the pixel circuit array 100 compared with the light emitting device array 200, the larger the specific area that other peripheral circuits can be arranged under the light emitting device array 200.
  • other peripheral circuits are exposed to the light emitting device in the first direction. The smaller the area outside the array 200 is, the smaller the width of the frame used to shield the above-mentioned other peripheral circuits is. Therefore, based on the above arrangement, the frame width of the display module in the first direction can be narrowed.
  • the pixel circuit array 100 includes a plurality of first pixel sub-circuits and a plurality of second pixel sub-circuits.
  • Each of the second pixel sub-circuits is respectively located between two adjacent first pixel sub-circuits in a first direction, and the first direction is perpendicular to the thickness direction of the display module.
  • the first pixel sub-circuit can be understood as a pixel sub-circuit that is actually used to control characteristics such as light-emitting brightness and light-emitting color of the light-emitting device array 200 .
  • the second pixel sub-circuit can be understood as a dummy pixel sub-circuit (dummy pixel). As shown in FIG.
  • the light emitting device array 200 includes a plurality of light emitting devices 201 including cathodes and anodes.
  • the anodes of each of the plurality of light-emitting devices 201 are respectively connected to the plurality of first pixel sub-circuits in a one-to-one correspondence.
  • the dot structure located at the lower part of each first pixel sub-circuit in FIG. 2 is the node for connecting the first pixel sub-circuit to the light emitting device 201.
  • the circle structure in each light emitting device 201 in FIG. 3 is is used to connect the anode of the first pixel sub-circuit. It should be noted that the circle structures in the embodiments in FIG. 2 and FIG.
  • the second pixel sub-circuit can fill the gap between the first pixel sub-circuits caused by size reduction, so as to achieve the above-mentioned purpose of position correspondence, improve the arrangement uniformity of the first pixel sub-circuit, thereby improving the display uniformity of the display module. sex.
  • Fig. 4 is a schematic structural diagram of a display module without a second pixel sub-circuit.
  • the wiring refers to the wiring connected between the light emitting device and the corresponding first pixel sub-circuit.
  • the light emitting device on the left side in FIG. 4 can be understood as the light emitting device near the center of the display module, and the light emitting device on the right side in FIG. 4 can be understood as the light emitting device near the frame of the display module.
  • the length difference between the two driving wires is large, which will lead to the difference in the performance of the light emitting device such as response speed or luminous brightness, resulting in uneven display of the display module in the first direction.
  • the length of the driving trace changes gradually, that is, the closer to the frame, the longer the length of the driving trace. Therefore, there is no region in FIG. 4 where the lengths of the driving traces are set in the same manner.
  • the display module of this embodiment further includes a circuit trace 101 .
  • the first pixel sub-circuit needs to connect a large number of signal lines (that is, a plurality of thin wires 102 extending along the second direction in the figure) to realize the required light emission control function, while the second pixel sub-circuit does not need Therefore, the second pixel sub-circuit does not need to be provided with corresponding signal lines.
  • this will result in a relatively high routing density in the area corresponding to the first pixel sub-circuit, and a relatively small routing density in the area corresponding to the second pixel sub-circuit, and metal routing usually has a certain reflective characteristic.
  • the routing density is different , will lead to different luminous characteristics of the display module in different areas, which will lead to the problem of screen mura.
  • mura refers to the phenomenon that the display module displays unevenly. Therefore, in this embodiment, by setting the circuit traces 101, the traces in the display module are relatively evenly arranged, which can improve the distribution uniformity of the trace density in the display module, thereby avoiding the density difference of the circuit traces 101. The problem of the screen Mura.
  • a display module with a better distribution of wiring density is also conducive to stabilizing the process, ensuring the electrical consistency of the circuit structure in the display module, and ensuring the uniformity of the display.
  • the length of the circuit trace 101 may be equal to the length of the signal line 102 in the first pixel sub-circuit, so as to further improve the consistency between the circuit trace 101 and the signal line 102 .
  • the circuit traces 101 can also be respectively connected to a plurality of second pixel sub-circuits, and the connection mode is corresponding to the connection mode between the first pixel sub-circuits and the signal lines.
  • the types of signal lines connected to the first pixel sub-circuit may be but not limited to data signal lines, gate lines and light emission control lines. Taking the signal line as the data signal line as an example, if the circuit trace 101 is parallel to the data signal line, the connection mode between the circuit trace 101 and the plurality of second pixel sub-circuits may correspond to the connection between the data signal line and the first pixel sub-circuit.
  • connection mode that is, the data signal line is connected to the data signal end of the first pixel sub-circuit, and then the circuit wiring 101 is connected to the data signal end of the second pixel sub-circuit, so as to further improve the flexibility of each wiring structure in the display module. consistency.
  • the cathodes of each light emitting device can be isolated from each other, the cathodes of each light emitting device are connected to the corresponding cathode signal lines, and the electrical signals of the cathodes are respectively obtained from the connected cathode signal lines, wherein the electrical signals of the cathodes can be driven by the display chip output.
  • the cathode of each light-emitting device can also adopt a common cathode design, that is, the cathodes of the light-emitting devices are connected to each other, and the brightness of each light-emitting device is controlled separately by adjusting the electrical signal of the anode, so as to achieve a simpler manufacturing process and control method. It should be noted that the above examples are only for illustration, and are not intended to limit the scope of protection of this embodiment, and the technical solutions of this embodiment can be applied to any of the above cathode structures.
  • the size of the conductive structure used to connect the cathode signal line and the cathode of the light-emitting device will also be relatively reduced, which will easily lead to poor electrical contact or increased contact resistance between the cathode signal line and the cathode of the light-emitting device, and then each emits light.
  • the cathode of the device is electrically non-uniform and may even cause a display mura.
  • the cathode of each light-emitting device can be equivalent to a resistor R1
  • the cathodes of multiple connected light-emitting devices can be equivalent to multiple resistors connected in series, that is, nR1.
  • the circuit traces are respectively connected to the cathodes of a plurality of the light-emitting devices, wherein the extending direction of the circuit traces may be parallel to the gate lines of the display module
  • One of the initialization signal line and the data signal line is not limited in this embodiment.
  • the equivalent resistance of the circuit traces is connected in parallel with the equivalent resistance of the cathodes of the light emitting devices.
  • the impedance of the overall structure after parallel connection is R1R2/(R1+R2), which is less than that of the cathode of a light-emitting device
  • the equivalent resistance R1 reduces the obstruction and loss of the cathode voltage signal during transmission, and improves the consistency of the cathode voltage of each light emitting device.
  • connection between the circuit trace and the cathode of the light emitting device may be a direct connection or an indirect connection.
  • the cathode of the light emitting device may be connected to the circuit trace via a conductive structure, which may be but not limited to a metallized hole, a conductive plug, a trace, and the like.
  • this embodiment does not limit the number of circuit wires.
  • the number of circuit traces may be one, and the cathodes of all light emitting devices in the light emitting device array 200 are connected to the same circuit trace.
  • the number of circuit traces can also be multiple, so when adopting the aforementioned mutually isolated cathode design, the cathodes of some light-emitting devices can be connected to the same circuit traces, and the cathodes of another part of the light-emitting devices can be connected to another same circuit traces . Moreover, when there are multiple circuit traces, multiple light emitting devices connected to the same circuit trace can be selected according to preset rules. As an example, continuing to refer to FIG. 2, FIG. 2 shows cathode nodes (circular structures in FIG. 2) of eight first pixel sub-circuits, and each circuit trace 101 can be respectively connected to the same number of first pixel sub-circuits.
  • a cathode of a pixel sub-circuit, and a plurality of first pixel sub-circuits connected to the same circuit trace 101 are arranged axially symmetrically, and the axis of symmetry is the connected circuit trace 101 . That is, as shown in FIG. 2 , each circuit trace 101 is used to connect the first pixel sub-circuits located in four columns, and two columns are located on the left side of the circuit trace 101, and the other two columns are located on the circuit trace 101 to the right of the . Further, the cathodes of the light emitting devices corresponding to the plurality of first pixel sub-circuits in the same column may be connected to the same circuit wiring 101 .
  • the width of other peripheral circuits exposed to the outside of the light emitting device array 200 in the first direction is reduced, that is, the frame width of the display module is narrowed.
  • the second pixel sub-circuit it is possible to avoid the difference in the response speed or luminance of the light-emitting device caused by the difference in the driving distance of different light-emitting devices, thereby improving the display uniformity of the display module.
  • a circuit wiring 101 connected to the second pixel sub-circuit is also provided to improve the consistency between the first pixel sub-circuit and the second pixel sub-circuit and suppress the screen mura problem, and the above-mentioned circuit wiring 101 It is connected to the cathode of the light-emitting device, and the resistance of the cathode is connected in parallel with the resistance of the circuit trace 101, which is equivalent to reducing the impedance of the overall structure of the cathode and the circuit trace 101.
  • the obstruction and loss of the cathode voltage signal in the transmission process are reduced, thereby improving the consistency of the cathode voltage of each light emitting device, avoiding the influence of the cathode voltage on the display brightness of each light emitting device, and further improving the display mode.
  • Group display uniformity
  • the pixel circuit array 100 includes a plurality of circuit traces 101 , and the plurality of circuit traces 101 are parallel to each other.
  • this embodiment does not limit the specific shape of the circuit traces 101, and the circuit traces 101 may be in a straight line structure, or may be in a zigzag structure or the like.
  • the consistency of the multiple circuit traces 101 can be improved. It can avoid the different reflective states of the circuit traces 101 with different shapes, thereby improving the mura problem of the display module. It can also avoid poor process consistency of circuit traces 101 with different shapes, thereby improving the manufacturing yield of the display module.
  • the display module is provided with a first sub-array area 110, and a plurality of first pixel circuits 111 and a plurality of second pixels are arranged in the first sub-array area 110.
  • a circuit 112 the first pixel circuit 111 includes a plurality of the first pixel sub-circuits
  • the second pixel circuit 112 includes a plurality of the second pixel sub-circuits, and any two in the first direction
  • One second pixel circuit 112 is provided between adjacent first pixel circuits 111 .
  • the projection of the circuit trace 101 on the virtual plane is located in the projection of the second pixel sub-circuit on the virtual plane, and the virtual plane is perpendicular to the thickness direction of the display module.
  • all the projections of the circuit traces 101 on the virtual plane are located in the projections of the second pixel circuit 112 on the virtual plane. That is, a plurality of said circuit traces 101 all extending along the second direction can be arranged correspondingly, so that the extending direction of the circuit traces 101 corresponds to the arrangement direction of the second pixel sub-circuits, thereby avoiding the pairing of the circuit traces 101
  • the first pixel sub-circuit causes shading, that is, avoids affecting the signal line path of the first pixel sub-circuit.
  • the circuit trace 101 can also realize the connection function with the cathode, so as to reduce the overall impedance and improve the connection between the cathodes. voltage uniformity.
  • a plurality of circuit traces 101 are arranged at equal intervals.
  • the equivalent resistance of each circuit trace 101 can be relatively close, and the equivalent resistance of the cathode connected in parallel to each circuit trace 101 can be relatively close, so that After the parallel connection, the impedances of all places on the display module are similar, thereby further improving the consistency of the cathode voltage of the display module.
  • the light emitting device array 200 is divided into a plurality of light emitting repeating units 210 , and each of the light emitting repeating units 210 includes a plurality of light emitting devices 201 respectively.
  • the light emitting repeating unit 210 includes a plurality of repeating subunits 2101.
  • the light emitting repeating unit 210 includes 4n red light emitting devices, 8n green light emitting devices and 4n blue light emitting devices, where n is an integer greater than or equal to 1.
  • two adjacent pixels can share the red light-emitting device or the blue light-emitting device, thereby improving the resolution of the display module, suppressing the color fringing problem of the display module, and further improving the display quality.
  • this embodiment does not specifically limit the arrangement of the red light-emitting devices, green light-emitting devices and blue light-emitting devices, as long as the above-mentioned technical solutions for improving the resolution of the display module can be realized, they all belong to this embodiment. protected range.
  • each of the repeating subunits 2101 includes one of the red light emitting devices, two of the green light emitting devices and one of the blue light emitting devices that are separated from each other, wherein the One of the green light-emitting devices and one of the red light-emitting devices in the repeating subunit 2101 respectively have the centers of the two first vertices of the virtual quadrilateral 2102, and the two first vertices are located on one side of the virtual quadrilateral 2102. on the diagonal.
  • the other green light-emitting device and one blue light-emitting device in the repeating subunit 2101 respectively have the centers of two second vertices located in the virtual quadrilateral 2102, and the two second vertices are located in the virtual quadrilateral 2102 on the other diagonal.
  • each light-emitting device 201 in this embodiment may be, but not limited to, organic light-emitting diodes (Organic light-emitting diodes, OLEDs), quantum dot light-emitting diodes (Quantum Dot Light Emitting Diodes, QLEDs) and micron-scale light-emitting diodes (Micro LED), etc.
  • organic light-emitting diodes Organic light-emitting diodes, OLEDs
  • quantum dot light-emitting diodes Quantum Dot Light Emitting Diodes, QLEDs
  • Micro LED micron-scale light-emitting diodes
  • each light-emitting device 201 can be an organic light-emitting diode of different colors, such as red OLED, green OLED and blue OLED, etc., and the driving circuit of each light-emitting device 201 can be the same, but the materials of the light-emitting layers of the light-emitting devices 201 of different colors are different. , so as to realize the display of different colors, so that the display device can realize full-color display.
  • a larger number of light emitting devices 201 may be provided, for example, light emitting devices 201 including four different colors.
  • the display module includes three light emitting devices 201 of different colors, and the three colors may be red (R), green (G) and blue (B) respectively. It can be understood that the above numbers are only used for exemplary description, and are not used to limit the protection scope of this embodiment.
  • FIG. 5 is a schematic cross-sectional view of a display module according to an embodiment, and the cross-sectional direction of FIG. 5 is perpendicular to the display surface of the display module.
  • the display module includes a pixel definition layer 1106 , an anode layer 1107 , a luminescent material layer 1108 and a cathode layer 1109 .
  • the pixel definition layer 1106 is provided with a plurality of pixel openings isolated from each other.
  • the pixel definition layer 1106 can limit the deposition position of the luminescent material layer 1108, thereby improving the positional accuracy when forming a light emitting device, and can also prevent adjacent light emission when emitting light. Color crosstalk occurs between devices, thereby improving the display quality of the display module.
  • the anode layer 1107 is respectively disposed in the plurality of pixel openings, and a part of the anode layer 1107 is buried under the pixel definition layer 1106 .
  • the luminescent material layer 1108 is respectively disposed on the surface of the anode layer 1107 in the plurality of pixel openings.
  • the cathode layer 1109 covers the surfaces of the luminescent material layer 1108 and the pixel definition layer 1106 , and the cathode layer 1109 can be understood as continuously and completely covering the surfaces of the luminescent material layer 1108 and the pixel definition layer 1106 .
  • the anode layer 1107, the light emitting material layer 1108 and the cathode layer 1109 located in the same pixel opening constitute one light emitting device. That is, this embodiment provides a display module with a common cathode structure. Specifically, two light-emitting devices are shown in FIG. , the cathodes of the two light-emitting devices are connected.
  • the cathode preparation method of the display module with a common cathode structure is simple. After forming a complete cathode material film layer, the entire film layer can be used as the cathode of each light-emitting device without complicated patterning process, and it will not affect the performance of the display module. Display quality.
  • the display module further includes a pixel circuit layer 1100 and a planarization layer 1114.
  • the pixel circuit layer 1100 is used to set up the pixel circuit array, that is, the first pixels corresponding to different light emitting devices
  • the sub-circuits are located in the same pixel circuit layer 1100.
  • the two dashed boxes in FIG. In 1100 this embodiment only takes one of the first pixel sub-circuits as an example for illustration.
  • the pixel circuit layer 1100 is formed on the surface of the substrate 1110.
  • the substrate 1110 may include polyimide (PI) substrate layers 1110a and first buffer layers 1110b arranged alternately in sequence. In the embodiment shown in FIG.
  • PI polyimide
  • the substrate 1110 includes Two polyimide (PI) substrate layers 1110a and two first buffer layers 1110b are arranged alternately in sequence. It can be understood that the substrate 1110 may also include more polyimide (PI) substrate layers 1110 a and first buffer layers 1110 b.
  • PI polyimide
  • the pixel circuit layer 1100 essentially includes a plurality of sub-functional layers stacked, each sub-functional layer is respectively formed with structures of different shapes and different materials, and together constitutes the pixel circuit array 100 .
  • the pixel circuit layer 1100 specifically includes a first gate layer 1101a, a second gate layer 1101b, a first source 1102, a drain region 1103, a source contact structure 1104 and a drain contact structure 1105 , wherein the first source 1102 and the drain region 1103 are located in the same sub-functional layer, and the source contact structure 1104 and the drain contact structure 1105 are located in another same sub-functional layer.
  • the display module may also include a first gate insulating layer 1111 for isolating the first source 1102, the drain region 1103 and the first gate layer 1101a, and a first gate insulating layer 1111 for isolating the first gate layer 1101a from the second The second gate insulating layer 1112 of the gate layer 1101b, and the interlayer insulating layer 1113 for isolating the second gate layer 1101b, the source contact structure 1104 and the drain contact structure 1105.
  • the first source 1102 and the drain region 1103 are turned on or off under the control of the first gate 1101 .
  • the first gate layer 1101a is provided with signal traces such as initialization signal lines, gate drive signal lines, and light emission control signal lines, as well as a first gate 1101 and a plate of a storage capacitor (not shown).
  • the second gate layer 1101b is provided with signal traces such as initial signal wires, and is also provided with another plate of the storage capacitor (not shown in the figure).
  • the source-drain layer is used to set the data signal line 430, and is also provided with a source contact structure 1104 and a drain contact structure 1105.
  • the source contact structure 1104 is connected to the first source electrode 1102 located in the active layer, and the drain contact structure 1105 connected to the first source 1102 on the active layer.
  • the voltage on the first gate 1101 controls the conduction of the first source 1102 and the drain region 1103, the voltage signal on the drain contact structure 1105 can pass through the drain region 1103, the first source 1102, and drive away in sequence.
  • the wire is transmitted to the anode 1107 of the light emitting device 201 to drive the light emitting device 201 to emit light.
  • the planarization layer 1114 is arranged between the pixel circuit layer 1100 and the pixel definition layer 1106, and the planarization layer 1114 is provided with a plurality of driving wires L, since the positions of the plurality of light-emitting devices are different, and each light-emitting device The positions of the first pixel sub-circuits corresponding to the devices are also different, therefore, it is necessary to set the driving traces L with different lengths to achieve accurate connection.
  • the planarization layer 1114 can protect the driving wires L, and can also ensure the flatness of the display module structure.
  • One ends of the plurality of driving lines L are respectively connected to the anodes 1107 of the plurality of light-emitting devices in one-to-one correspondence, and the other ends of the plurality of driving lines L are respectively connected to the plurality of first pixel sub-circuits.
  • One-to-one connection so that the anodes 1107 of the plurality of light-emitting devices are electrically connected to the plurality of first pixel sub-circuits in a one-to-one correspondence.
  • the length difference of the driving wires L corresponding to the light-emitting devices of the same color is within the first preset range, and the length difference refers to the difference between the length of the longest driving wire L and the length of the shortest driving wire L. difference between.
  • the first preset range may be, for example, 0 um to 200 um. It can be understood that the first preset range may be jointly determined according to the type and resolution of the display device. For example, the types may include mobile phone, tablet computer and television, and the first preset range of the tablet computer may be larger than the first preset range of the mobile phone and smaller than the first preset range of the TV.
  • the driving wire L may be a transparent metal wire, for example, an indium tin oxide (Indium Tin Oxide, ITO) metal wire, an aluminum zinc oxide (Alumina zinc oxide, AZO) metal wire, or the like.
  • Fig. 6 is a schematic structural diagram of a first repeating unit and a corresponding light-emitting device in an embodiment.
  • one of the adjacent first pixel circuits 111 and one of the second pixel circuits 112 collectively serve as a first repeating unit 113.
  • this embodiment takes the first pixel circuit 111 on the left and the second pixel circuit 112 on the right as an example to divide to form the first repeating unit 113. In other embodiments, it can also be The first pixel circuit 111 on the right and the second pixel circuit 112 on the left are divided as an example. Referring to FIG. 3 and FIG.
  • the plurality of light-emitting repeating units 210 are in one-to-one correspondence with the plurality of first pixel circuits 111 .
  • the difference between the size of the light-emitting repeating unit 210 in the first direction and the size of the first repeating unit 113 in the first direction is within the second preset range, that is, it can be understood that the light-emitting repeating unit 210
  • the size in the first direction is similar to the size of the first repeating unit 113 in the first direction.
  • the second preset range may be, for example, 0 um to 5 um.
  • the correspondence between the positions of the light-emitting repeating unit 210 and the first repeating unit 113 can be realized, thereby setting a shorter driving line, To improve the stability and reliability of the driving current.
  • the size of the first pixel sub-circuit may be the same as that of the second pixel sub-circuit, and the film layer structure of the second pixel sub-circuit may be the same as that of the first pixel sub-circuit, so as to reduce
  • the design difficulty of the pixel circuit array 100 can also reduce the differential influence of various optical effects on the dimensional structure during the exposure preparation process, thereby improving the manufacturing yield of the pixel circuit array 100 and improving the off-screen caused by uneven reflection of the traces. mura.
  • FIG. 7 is a circuit diagram of a first pixel sub-circuit in an embodiment.
  • the first pixel sub-circuit includes a drive transistor T1, an anode initialization unit 1511, a gate initialization unit 1512, and a data writing unit 1513 , a threshold compensation unit 1514 and a light emission control unit 1515 .
  • the driving transistor T1 is used to generate a driving current.
  • the gate of the driving transistor T1 is connected to the gate initialization unit 1512, the first pole of the driving transistor T1 is used to receive the signal of the data signal terminal Data, and the second pole of the driving transistor T1 can output the driving current correspondingly.
  • the current value of the driving current is determined by the signal of the data signal terminal Data, and directly affects the light-emitting brightness of the light-emitting device.
  • the control terminal of the anode initialization unit 1511 is used to receive the signal of the second gate signal terminal Scan(n), the input terminal of the anode initialization unit 1511 is used to receive the initialization signal, and the output terminal of the anode initialization unit 1511 is connected to the anode of the light emitting device.
  • the anode initialization unit 1511 is used to receive an initialization signal through the input terminal after the gate of the driving transistor T1 is initialized, and pull down the anode of the light emitting device connected thereto to the initialization signal, so as to initialize the anode of the light emitting device.
  • the initialization signal can be understood as an initial charging voltage of the anode of the light emitting device.
  • the anode initialization unit 1511 may include a seventh transistor T7, the first pole of the seventh transistor T7 is used to receive the signal of the initialization signal terminal Vinit, the output terminal of the anode initialization unit 1511 is connected to the anode of the light emitting device, and the seventh transistor T7 The gate of is used to receive the signal of the second gate signal terminal Scan(n).
  • the control terminal of the gate initialization unit 1512 is connected to the gate control terminal for receiving the signal of the first gate signal terminal Scan(n-1); the input terminal of the gate initialization unit 1512 is connected to the initialization signal terminal Vinit for Receive the initialization signal; the output terminal of the gate initialization unit 1512 is connected to the gate of the driving transistor T1.
  • the gate initialization unit 1512 can pull down the gate voltage of the driving transistor T1 to the initialization signal according to the signal of the first gate signal terminal Scan(n-1) received by the control terminal, so as to control the gate of the driving transistor T1 to initialize.
  • the data writing unit 1513 includes a second transistor T2, the gate of the second transistor T2 is connected to the second gate signal terminal Scan(n), the first pole of the second transistor T2 is connected to the data signal terminal Data, and the second transistor T2 The second pole of the drive transistor T1 is connected to the first pole, and the second transistor T2 is used to control the connection between the second gate signal line and the first pole of the drive transistor T1 according to the signal of the second gate signal terminal Scan(n). The on-off of the signal transmission path.
  • the second transistor T2 when the signal at the second gate signal terminal Scan(n) is at a low level, the second transistor T2 is turned on and transmits the signal at the data signal terminal Data to The first pole of the driving transistor T1; when the signal of the second gate signal terminal Scan(n) is at low level, the second transistor T2 is turned off.
  • the data writing unit 1513 is not limited to the second transistor T2 in this embodiment, and may also be other circuit structures capable of realizing the signal transmission function according to the enable control signal.
  • the threshold compensation unit 1514 is respectively connected to the gate and the second pole of the driving transistor T1, and is used to control the signal transmission path between the gate and the second pole of the driving transistor T1 according to the signal of the second gate signal terminal Scan(n) on and off. Specifically, by setting the threshold compensation unit 1514, the threshold voltage of the driving transistor T1 can be compensated, so as to prevent the threshold voltage of the driving transistor T1 from affecting the brightness of the light emitting device.
  • the threshold compensation unit 1514 includes a third transistor T3 and a storage capacitor C1.
  • the storage capacitor C1 is connected to the second power supply voltage terminal VDD and the gate of the driving transistor T1 respectively.
  • the gate of the third transistor T3 is connected to the first gate signal line, the first pole of the third transistor T3 is connected to the second pole of the driving transistor T1, and the second pole of the third transistor T3 is connected to the gate of the driving transistor T1 .
  • the third transistor T3 is used for controlling the on-off of the signal transmission path between the gate of the driving transistor T1 and the second electrode according to the signal of the second gate signal terminal Scan(n).
  • the third transistor T3 as a P-type transistor as an example, when the signal of the second gate signal terminal Scan(n) is at a low level, threshold compensation is performed and the storage capacitor C1 is charged, so that the compensation result is stored in storage capacitor C1.
  • the third transistor T3 may be a double-gate transistor.
  • the third transistor T3 with a double-gate transistor structure can effectively improve the reliability of threshold compensation, thereby improving the display quality of the display device. It can be understood that other transistors in the first pixel sub-circuit may also be double-gate transistors to further improve display quality.
  • the light emission control unit 1515 includes a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is used to receive the light-emitting control signal
  • the first pole of the fifth transistor T5 is connected to the second power supply voltage terminal
  • the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor T1
  • the fifth transistor T5 is used for controlling the on-off of the signal transmission path between the second power supply voltage terminal and the first pole of the driving transistor T1 according to the light emission control signal EM.
  • the gate of the sixth transistor T6 is used to receive the light emission control signal EM, the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T1, the second pole of the sixth transistor T6 is connected to the anode of the light emitting device, and the sixth transistor T6 T6 is used for controlling the on-off of the signal transmission path between the second pole of the driving transistor T1 and the anode of the light-emitting device according to the light-emitting control signal EM.
  • the fifth transistor T5 and the sixth transistor T6 are both P-type transistors as an example for illustration.
  • the fifth transistor T5 and the sixth transistor T6 are turned on to drive the transistor T1
  • the voltage of the first pole of the first driving transistor T1 is pulled up to the second power supply voltage VDD, and the gate-source voltage difference of the first driving transistor T1 changes to generate a driving current and output the driving current to the light-emitting device, thereby controlling the light-emitting device to emit light.
  • various transistors in this embodiment are not limited to the P-type transistors in the foregoing embodiments, and may also be N-type transistors and the like. For different types of transistors, their corresponding driving methods can also be adaptively adjusted.
  • the first pixel sub-circuit of this embodiment is not limited to the 7T1C first pixel sub-circuit in the foregoing embodiments, that is, the first pixel sub-circuit may also have other numbers of transistors, so that A light-weight display device, or a more flexible display function with a larger number of transistors, for example, can also be other types of driving circuits such as 3T1C, 6T1C, and 6T2C.
  • the first pixel subcircuit in the embodiment of FIG. 7 can be implemented based on the structure shown in the embodiment in FIG. 5, and the type of the first pixel subcircuit can be a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) type, that is, All transistors in the first pixel sub-circuit are low temperature polysilicon thin film transistors.
  • some transistors in the first pixel sub-circuit may be oxide thin film transistors, and accordingly, the type of the first pixel sub-circuit is a low temperature poly-silicon oxide (Low Temperature Poly-silicon Oxide, LTPO) type.
  • the oxide thin film transistor has a better performance of suppressing electric leakage, so it is suitable as a switching transistor to achieve more reliable switching performance.
  • FIG. 8 is one of the partial structural schematic diagrams of a display module according to an embodiment.
  • FIG. 9 is a schematic cross-sectional view of the display module according to the embodiment shown in FIG. 8 .
  • the display module further includes gate lines 410 and a plurality of first metallized holes 1121 .
  • the metallized hole refers to a hole-like structure in which a conductive material is plated on the inner wall of the hole, and the conductive material of the plated film may be but not limited to copper. It should be noted that the thickness of the gate line 410 and the circuit trace 101 in FIG. 8 are different, but the difference in thickness in FIG.
  • the gate lines 410 and the circuit traces 101 are defined, that is, the dimensions of the gate lines 410 and the circuit traces 101 may be the same.
  • the position of the first metallization hole 1121 is staggered from the initialization signal line in the second gate layer 1101b, so it can be directly connected to the gate line in the first gate layer 1101a.
  • the gate lines 410 extend along the row direction of the display module.
  • the gate lines 410 are used to transmit gate signals, and the gate lines 410 are respectively connected to the gate signal terminals of a plurality of the first pixel sub-circuits, and the gate signal terminals include Scan(n) and Scan(n) in FIG. 7 . -1). Referring to FIG.
  • the pixel sub-circuit on the left side connected to the anode 1107 is the first pixel sub-circuit
  • the pixel sub-circuit on the right side not connected to the light-emitting device is the second pixel sub-circuit
  • the circuit in the second pixel sub-circuit The line 101 and the gate line are disposed in the same sub-functional layer, ie, the first gate layer 1101a.
  • Each of the first metallization holes 1121 penetrates through the pixel definition layer 1106 and the planarization layer 1114 along the thickness direction of the display module, and one end of the first metallization hole 1121 is connected to the cathode layer 1109 The other end of the first metallized hole 1121 is connected to the circuit trace 101 .
  • the connection reliability between the circuit trace 101 and the cathode of the light-emitting device can be ensured, the problem of poor conduction of a single first metallized hole 1121 can be avoided, and The voltage consistency among the cathodes of each light emitting device is improved.
  • the circuit traces 101 and the gate lines 410 on the same sub-functional layer, the circuit traces 101 do not need to occupy a separate sub-functional layer, thereby providing a thinner display module.
  • a plurality of first metallized holes 1121 may be arranged at equal intervals along the extending direction of the circuit trace 101, so as to improve the uniform impedance distribution of the overall structure composed of the circuit trace 101, the first metallized hole 1121 and the cathode. To improve the uniformity of the voltage distribution on the cathode, thereby improving the display uniformity of the display module.
  • the second pixel sub-circuit is also configured with a gate signal terminal.
  • the circuit trace 101 may be arranged parallel to the gate line 410 . That is, the extending direction of the circuit traces 101 is parallel to the row direction of the display module, and the first direction in this embodiment can be understood as the row direction of the display module.
  • the circuit trace 101 is connected to the gate signal terminals Scan(n) and Scan(n ⁇ 1) of the second pixel sub-circuit.
  • the structure and connection relationship of the circuit traces 101 are the same as those of the gate lines 410 , therefore, the circuit traces 101 can be prepared directly using the mask of the gate lines 410 , thereby reducing design difficulty and manufacturing cost of the mask.
  • one circuit trace 101 is arranged between two adjacent gate lines 410 in the second direction, and between the circuit trace 101 and one adjacent gate line 410 The distance is equal to the distance between the circuit trace 101 and another adjacent gate line 410 . Based on the above arrangement, the gate lines 410 and the circuit traces 101 can be evenly arranged, thereby further suppressing the mura problem of the screen.
  • FIG. 10 is the second schematic diagram of the partial structure of the display module of an embodiment
  • FIG. 11 is a schematic cross-sectional view of the display module of the embodiment of FIG. 10
  • the display module further includes an initialization signal line 420 and a plurality of second metallized holes 1122 .
  • the thickness of the initialization signal line 420 and the circuit trace 101 in FIG. 10 are different, but the difference in thickness in FIG.
  • the specific dimensions of the initialization signal lines 420 and the circuit traces 101 are limited, that is, the dimensions of the initialization signal lines 420 and the circuit traces 101 may be the same.
  • the initialization signal line 420 extends along the row direction of the display module.
  • the initialization signal line 420 is used to transmit an initialization signal, and the initialization signal can be used to initialize the gate of the driving transistor or to initialize the anode of the light emitting device, and the initialization signal line 420 is respectively connected to the plurality of first pixel sub-circuits. Initialize the connection of the signal terminal, the initialization signal terminal includes Vinit in Figure 7. Referring to FIG.
  • the pixel subcircuit on the left side connected to the anode 1107 is the first pixel subcircuit
  • the pixel subcircuit on the right side not connected to the light emitting device is the second pixel subcircuit
  • the circuit in the second pixel subcircuit The line 101 and the initialization signal line are provided in the same sub-functional layer, ie, the second gate layer 1101b.
  • Each second metallization hole 1122 penetrates through the pixel definition layer 1106 and the planarization layer 1114 along the thickness direction of the display module, and one end of the second metallization hole 1122 is connected to the cathode layer 1109 The other end of the second metallized hole 1122 is connected to the circuit trace 101 .
  • the connection reliability between the circuit trace 101 and the cathode of the light emitting device can be ensured, the problem of poor conduction of a single second metallization hole 1122 can be avoided, and The voltage consistency among the cathodes of each light emitting device is improved.
  • the circuit wiring 101 and the initial signal line on the same sub-functional layer, the circuit wiring 101 does not need to occupy a separate sub-functional layer, thereby providing a thinner display module.
  • the circuit routing 101 is arranged in parallel with the initialization signal line 420, one circuit routing 101 is arranged between two initialization signal lines 420 adjacent in the second direction, and the circuit The distance between the trace 101 and the adjacent one of the initialization signal lines 420 is equal to the distance between the circuit trace 101 and the other adjacent initialization signal line 420 . Based on the above arrangement, the initialization signal lines 420 and the circuit traces 101 can be evenly arranged, thereby further suppressing the mura of the screen.
  • a plurality of second metallization holes 1122 can be arranged at equal intervals in the extending direction of the circuit trace 101, so as to improve the impedance distribution of the overall structure composed of the circuit trace 101, the second metallization hole 1122 and the cathode. Uniformity, thereby improving the uniformity of voltage distribution on the cathode, thereby improving the display uniformity of the display module.
  • the circuit trace 101 connected to the first metallized hole 1121 is called a first trace
  • the circuit trace 101 connected to the second metallized hole 1122 is called a second trace.
  • the display module may include multiple first wires and multiple second wires to further reduce the impedance on the cathode, improve the uniformity of the voltage distribution on the cathode, and further improve the display module. display uniformity.
  • Figure 12 is the third schematic diagram of the partial structure of the display module of an embodiment
  • Figure 13 is a schematic cross-sectional view of the display module of the embodiment of Figure 12
  • the display module also includes data signal lines 430 and a plurality of third metal Blowhole 1123.
  • the thickness of the data signal line 430 and the circuit trace 101 in FIG. 12 are different, but the difference in thickness in FIG.
  • the specific dimensions of the data signal line 430 and the circuit trace 101 are limited, that is, the dimensions of the data signal line 430 and the circuit trace 101 may be the same.
  • the data signal lines 430 extend along the column direction of the display module.
  • the data signal line 430 is used to transmit the data signal, and the data signal is used to control the brightness of the light-emitting device.
  • the data signal line 430 is respectively connected to the data signal terminals of a plurality of the first pixel sub-circuits, and the data signal terminal includes the Data in FIG. 7 .
  • the pixel subcircuit on the left side connected to the anode 1107 is the first pixel subcircuit
  • the pixel subcircuit on the right side not connected to the light-emitting device is the second pixel subcircuit
  • the circuit trace 101 in the second pixel subcircuit The same sub-functional layer as the data signal line, that is, the source-drain layer.
  • Each of the third metallization holes 1123 penetrates through the pixel definition layer 1106 and the planarization layer 1114 along the thickness direction of the display module, and one end of the third metallization hole 1123 is connected to the cathode layer 1109 The other end of the third metallized hole 1123 is connected to the circuit trace 101 in the pixel circuit layer.
  • the connection reliability between the circuit trace 101 and the cathode of the light emitting device can be ensured, the problem of poor conduction of a single third metallized hole 1123 can be avoided, and The voltage consistency among the cathodes of each light emitting device is improved.
  • circuit traces 101 and the data signal lines 430 do not need to occupy a separate sub-functional layer, thereby providing a thinner display module.
  • a plurality of third metallization holes 1123 may be arranged at equal intervals along the extending direction of the circuit traces 101, so as to improve the uniform impedance distribution of the overall structure composed of the circuit traces 101, the third metallization holes 1123 and the cathode. To improve the uniformity of the voltage distribution on the cathode, thereby improving the display uniformity of the display module.
  • the second pixel sub-circuit is also configured with a data signal terminal, and the circuit trace 101 may be arranged in parallel with the data signal line 430 . That is, the extending direction of the circuit traces 101 is parallel to the column direction of the display module, and the first direction in this embodiment can be understood as the column direction of the display module. Moreover, the circuit wiring 101 is connected to the data signal terminal Data of the second pixel sub-circuit. That is, the structure and connection relationship of the circuit traces 101 are the same as those of the data signal lines 430 , therefore, the circuit traces 101 can be prepared directly using the photomask of the data signal lines 430 , thereby reducing design difficulty and manufacturing cost of the photomask.
  • one circuit trace 101 is arranged between two adjacent data signal lines 430 in the first direction, and between the circuit trace 101 and one adjacent data signal line 430 The distance is equal to the distance between the circuit trace 101 and another adjacent data signal line 430 . Based on the above arrangement, the data signal lines 430 and the circuit traces 101 can be evenly arranged, thereby further suppressing the mura problem of the screen.
  • the display module includes not only a plurality of first wires, but also a plurality of third wires.
  • the multiple first traces extend along the row direction of the display module
  • the multiple third traces extend along the column direction of the display module
  • both the multiple first traces and the multiple third traces are connected to the light emitting
  • the common cathode of the device is connected to form a parallel mesh trace.
  • the square resistance of the cathode is 12 ⁇ /sq-20 ⁇ /sq; if Ti/Al/Ti or Mo
  • the first wire and the third wire are made of metal, and the first wire and the third wire are respectively connected to the cathode, then the overall square resistance of the above structure after parallel connection is 0.2 ⁇ /sq-0.6 ⁇ /sq, thus greatly
  • the voltage uniformity on the cathode is improved, thereby improving the display uniformity of the display module, especially the display uniformity under low grayscale.
  • the impedance on the cathode can be greatly reduced, the uniformity of the voltage distribution on the cathode can be improved, and the display uniformity of the display module can be further improved.
  • FIG. 14 is one of the simplified cross-sectional diagrams of a display module according to an embodiment.
  • the display module further includes a gate driving circuit 300 .
  • the first direction is the row direction of the display module
  • the third direction is the thickness direction of the display module.
  • the gate drive circuit 300 is arranged adjacent to the pixel circuit array 100 in the first direction, and the projection of the gate drive circuit 300 on the virtual plane 600 along the third direction is along the line of the light emitting device array 200 The projections of the third direction on the virtual plane 600 partially overlap, the third direction is the thickness direction of the display module, and the virtual plane 600 is a plane perpendicular to the third direction.
  • the plane 600 is not a feature that actually exists in the display module, but a reference plane introduced for the convenience of explaining the features of the display module.
  • a display module with a narrower border can be provided.
  • FIG. 15 is a second simplified cross-sectional schematic diagram of a display module according to an embodiment.
  • the display module further includes a fan-out wiring group 500 .
  • the first direction is the column direction of the display module
  • the third direction is the thickness direction of the display module.
  • the fan-out routing group 500 is arranged adjacent to the pixel circuit array 100 in the second direction, and the projection of the fan-out routing group 500 on the virtual plane 600 along the third direction is the same as that of the light emitting device array 200 along the third direction.
  • the projections of the directions on a virtual plane 600 which is a plane perpendicular to the third direction, partially coincide.
  • the display driving unit located in the non-display area is connected to the pixel circuit array 100 through the fan-out wire group 500 to transmit control signals to the pixel circuit array 100 .
  • the display driving unit may be a display driver chip (Display Driver IC, DDIC).
  • DDIC Display Driver IC
  • FIG. 16 is the second structural schematic diagram of a pixel circuit array in an embodiment. Referring to FIG. Adjacent to the first sub-array area 110 in the first direction, a plurality of the first pixel circuits 111 are disposed in the second sub-array area 120 .
  • FIG. 17 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 16. Referring to FIG. In the second sub-array region 120 , a larger number of light emitting devices can be arranged correspondingly, thereby increasing the overlapping area between the light emitting device array 200 and other peripheral circuits (such as the gate driving circuit 300 ).
  • the overlapping area refers to the overlapping area in the third direction, that is, the projection of the light emitting device array 200 on the virtual plane 600 perpendicular to the third direction and the projection of other peripheral circuits on the virtual plane 600 perpendicular to the third direction the overlapping area between.
  • the first sub-array region 110 structure is adopted in the middle area, and
  • the structure of the second sub-array area 120 can not only achieve the purpose of narrowing the display frame to a large extent, but also reduce the impact on user experience. For example, when one layer is used to drive the wiring, a space of 200um to 400um can be obtained at the left and right borders to provide a display module with a narrower border.
  • the second sub-array area 120 in the embodiment of FIG. 16 only shows 8 columns of first pixel sub-circuits, the second sub-array area 120 can actually have more columns of first pixels as required. sub-circuits to further optimize narrow bezel performance.
  • one side edge of the second sub-array region 120 is aligned with the first side edge of the first sub-array region 110 in a second direction, and the second direction perpendicular to the first direction and perpendicular to the thickness direction of the display module.
  • the method of defining the side edges of the first sub-array region 110 in this embodiment is the same as that of the side edges of the first pixel circuit 111 in the foregoing embodiments, and details are not repeated here.
  • the design difficulty of the first pixel sub-circuit can be reduced without affecting the display function.
  • FIG. 18 is the third schematic diagram of the structure of the pixel circuit array of an embodiment.
  • the third sub-array area 130 can be understood as being relatively close to the center of the display module, while the first sub-array area 110 is relatively close to the display module border.
  • a plurality of repeating units and a plurality of third pixel circuits 131 are provided in the third sub-array area 130, and the repeating units include one first pixel circuit 111 and one second pixel circuit 111 adjacent in the first direction.
  • Two pixel circuits 112, and one third pixel circuit 131 is provided between any two adjacent repeating units in the second direction, and the third pixel circuit 131 includes A plurality of the second pixel sub-circuits arranged.
  • a plurality of first wiring lines, a plurality of second wiring lines and a plurality of second wiring lines can be simultaneously set in the display module.
  • a plurality of third wires extend along the column direction of the display module, and the projection of the second wires on the virtual plane is located in the projection of the second pixel circuit on the virtual plane, so that the multiple first wires and the multiple The third routing forms a mesh structure.
  • the specific setting manners of the first routing, the second routing and the third routing can refer to the above-mentioned embodiments, which will not be repeated here.
  • FIG. 19 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 18.
  • the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module.
  • the third sub-array area 130 includes a plurality of first repeating units 113 and a plurality of third pixel circuits 131 .
  • the third pixel circuit 131 includes a plurality of third pixel sub-circuits, the structure of the third pixel sub-circuit may be the same as that of the first pixel sub-circuit, and the third pixel sub-circuit is not the same as the first pixel sub-circuit.
  • the light emitting device is electrically connected.
  • the third pixel sub-circuit identical to the first pixel sub-circuit, it is possible to ensure that the structure and size of each pixel sub-circuit inside the pixel circuit array 100 are consistent, and to avoid the mura problem caused by the inconsistent density of circuit traces 101 .
  • the consistent size and structure of the pixel sub-circuits is also conducive to the stability of the manufacturing process, ensuring the consistency of the electrical properties of the thin film transistors and the uniformity of the display.
  • one side edge of the third sub-array region 130 is aligned with the second side edge of the first sub-array region 110 in the first direction, and the second side edge is connected to the first side edge, and the plurality of third pixel sub-circuits in the third pixel circuit 131 are arranged along the first direction.
  • the difference between the sum of the sizes of the first repeating unit 113 and the third pixel circuit 131 in the second direction and the size of the light emitting repeating unit 210 in the second direction is within a fourth preset range .
  • the fourth preset range may be, for example, 0um to 10um.
  • FIG. 20 is the fourth schematic diagram of the structure of the pixel circuit array in an embodiment.
  • the sub-array area 130 and the fourth sub-array area 140 are adjacent to the third sub-array area 130 in the first direction, and is adjacent to the second sub-array area 120 in the second direction.
  • a plurality of the first pixel circuits 111 and a plurality of fourth pixel circuits 141 are arranged in the fourth sub-array area 140, and any two adjacent first pixel circuits 111 in the second direction There is a fourth pixel circuit 141 between them, and the fourth pixel circuit 141 includes a plurality of second pixel sub-circuits arranged along the first direction, and the fourth pixel circuit 141 in the fourth pixel circuit 141 The number of the second pixel sub-circuits is less than the number of the second pixel sub-circuits in the third pixel circuit 131 .
  • FIG. 21 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 20. Referring to FIG. A larger number of light emitting devices increases the overlapping area of the light emitting device array 200 and other peripheral circuits (such as the gate driving circuit 300 ) in the third direction.
  • the present application also provides a display device, including: the above-mentioned display module.
  • the frame of the display device can be narrowed, and the display uniformity of the display device can be optimized, thereby improving the comprehensive display performance of the display device.

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Abstract

Un module d'affichage comprend : un réseau de circuits de pixels (100) comprenant une pluralité de premiers sous-circuits de pixels, une pluralité de seconds sous-circuits de pixels et des fils de circuit (101), les seconds sous-circuits de pixels étant chacun situés entre deux premiers sous-circuits de pixels adjacents dans une première direction, et la première direction étant perpendiculaire au sens de l'épaisseur du module d'affichage ; et un réseau de dispositifs électroluminescents (200), la taille du réseau de dispositifs électroluminescents dans la première direction étant supérieure à la taille du réseau de circuits de pixels (100) dans la première direction, le réseau de dispositifs électroluminescents (200) comprenant une pluralité de dispositifs électroluminescents (201), les dispositifs électroluminescents (201) comprenant des cathodes et des anodes, et les anodes de la pluralité de dispositifs électroluminescents (201) étant respectivement connectés à la pluralité de premiers sous-circuits de pixels selon une correspondance biunivoque, les fils de circuit (101) étant connectés aux cathodes de la pluralité de dispositifs électroluminescents (201).
PCT/CN2022/118386 2021-10-27 2022-09-13 Module d'affichage et dispositif d'affichage WO2023071560A1 (fr)

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CN113506539B (zh) * 2021-07-19 2022-09-09 Oppo广东移动通信有限公司 显示模组和显示设备
CN113823214B (zh) * 2021-10-27 2023-11-10 Oppo广东移动通信有限公司 显示模组和显示设备
CN114512499A (zh) * 2022-01-28 2022-05-17 昆山国显光电有限公司 显示面板及显示设备
CN115136317B (zh) * 2022-05-24 2023-04-18 京东方科技集团股份有限公司 显示基板及其制造方法和显示装置
CN114942709A (zh) * 2022-06-07 2022-08-26 Oppo广东移动通信有限公司 触控显示屏和触控显示设备
CN115188314B (zh) * 2022-09-08 2023-01-31 惠科股份有限公司 异形屏的显示电路及显示设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109410823A (zh) * 2018-12-27 2019-03-01 厦门天马微电子有限公司 显示面板及显示装置
CN111584757A (zh) * 2020-05-27 2020-08-25 京东方科技集团股份有限公司 显示母板和显示基板的制作方法
CN113506539A (zh) * 2021-07-19 2021-10-15 Oppo广东移动通信有限公司 显示模组和显示设备
CN113539130A (zh) * 2021-07-19 2021-10-22 Oppo广东移动通信有限公司 显示模组和显示设备
CN113823214A (zh) * 2021-10-27 2021-12-21 Oppo广东移动通信有限公司 显示模组和显示设备
CN114512499A (zh) * 2022-01-28 2022-05-17 昆山国显光电有限公司 显示面板及显示设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI537928B (zh) * 2014-01-27 2016-06-11 友達光電股份有限公司 顯示面板及其驅動方法
KR20210109709A (ko) * 2020-02-27 2021-09-07 삼성디스플레이 주식회사 표시 장치
CN113380190B (zh) * 2021-06-07 2023-01-31 Oppo广东移动通信有限公司 显示面板和显示设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109410823A (zh) * 2018-12-27 2019-03-01 厦门天马微电子有限公司 显示面板及显示装置
CN111584757A (zh) * 2020-05-27 2020-08-25 京东方科技集团股份有限公司 显示母板和显示基板的制作方法
CN113506539A (zh) * 2021-07-19 2021-10-15 Oppo广东移动通信有限公司 显示模组和显示设备
CN113539130A (zh) * 2021-07-19 2021-10-22 Oppo广东移动通信有限公司 显示模组和显示设备
CN113823214A (zh) * 2021-10-27 2021-12-21 Oppo广东移动通信有限公司 显示模组和显示设备
CN114512499A (zh) * 2022-01-28 2022-05-17 昆山国显光电有限公司 显示面板及显示设备

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