WO2023071439A1 - 多相开关变换器及其控制电路 - Google Patents

多相开关变换器及其控制电路 Download PDF

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Publication number
WO2023071439A1
WO2023071439A1 PCT/CN2022/113210 CN2022113210W WO2023071439A1 WO 2023071439 A1 WO2023071439 A1 WO 2023071439A1 CN 2022113210 W CN2022113210 W CN 2022113210W WO 2023071439 A1 WO2023071439 A1 WO 2023071439A1
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Prior art keywords
control circuit
signal
state
control
circuit
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PCT/CN2022/113210
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English (en)
French (fr)
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谭磊
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圣邦微电子（北京）股份有限公司
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Publication of WO2023071439A1 publication Critical patent/WO2023071439A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to the technical field of power supplies, and more specifically, to a multi-phase switching converter and a control circuit thereof.
  • the multi-phase switching converter is a technology that connects multiple switching circuits in parallel and distributes the switching modulation process to different phases to realize the adjustment and control of the power supply.
  • the PWM (pulse width modulation, pulse width modulation) signals between the phases in the multi-phase power supply can be the same or staggered by a certain phase, so that the fluctuation frequency seen by the output and input is the switching frequency and the number of phases in each phase.
  • the product which can reduce the need for filter capacitors and reduce the current impact on the input, while speeding up the response to load changes. With its superior performance, multi-phase switching converters are widely used in power solutions for high-performance CPUs.
  • the purpose of the present disclosure is to provide a multi-phase switching converter and a control circuit thereof.
  • a multi-phase switching converter including: a plurality of switching circuits coupled in parallel, wherein each switching circuit has an input terminal coupled to an input voltage and a load coupled to an output terminal for providing an output voltage; and a plurality of control circuits connected in a daisy-chain architecture, respectively coupled to the plurality of switch circuits, wherein each control circuit has a first terminal, a second terminal and a third terminal , wherein the first end is coupled to the second end of the previous control circuit to receive the ready state input signal, the second end is coupled to the first end of the latter control circuit to provide the ready state output signal, and the third end is coupled to a communication bus to receive a clock signal, wherein each control circuit is configured to operate in a ready state when receiving said ready state input signal, and to generate a ready state output signal when said ready state receives said clock signal, and A switch control signal corresponding to the switch circuit is controlled.
  • the first end of the first control circuit among the plurality of control circuits and the second end of the last control circuit among the plurality of control circuits are coupled to the loopback line, so that the The multiple control circuits described above form a circular chain.
  • the switch control signal has a high level state, a low level state, and an intermediate level state
  • the corresponding switch circuit can respond to the above three states of the switch control signal, including turning on the upper transistor, turning on Action through the downtube and in a high-resistance state.
  • the ready-state input signal includes a turn-on ready-state input signal and a freewheeling ready-state input signal.
  • the ready state output signal includes an on ready state output signal and a freewheeling ready state output signal.
  • the clock signal includes a turn-on clock signal and a freewheeling clock signal.
  • each control circuit includes: a configuration register, configured to configure whether the corresponding control circuit participates in the loop chain, whether it is the first control circuit, and whether it is the last control circuit.
  • each control circuit includes: a reset control module, configured to transmit a state feedback signal to the upper controller via the communication bus, and the upper controller judges whether there is only one control circuit in the loop chain according to the state feedback signal.
  • the circuit is in the ready state, wherein when no or more than one control circuit in the loop chain is in the ready state, the reset control module receives a reset signal from the upper controller via the communication bus to execute circuit reset.
  • each control circuit includes: a counting module, configured to count the pulses of the clock signal in the preparation state, judge the total number of phases in the cycle chain at the current moment, and count the total number of phases It is transmitted to the host controller through the communication bus.
  • a counting module configured to count the pulses of the clock signal in the preparation state, judge the total number of phases in the cycle chain at the current moment, and count the total number of phases It is transmitted to the host controller through the communication bus.
  • each control circuit includes: a phase-cutting control module, configured to receive a phase-cutting instruction from an upper controller via the communication bus in the preparation state, and judge whether to enable the corresponding switching circuit based on the phase-cutting instruction Stop power output or start power output.
  • a phase-cutting control module configured to receive a phase-cutting instruction from an upper controller via the communication bus in the preparation state, and judge whether to enable the corresponding switching circuit based on the phase-cutting instruction Stop power output or start power output.
  • each control circuit includes: a detection and control module configured to compare the current sampling signal of the corresponding switch circuit with the current threshold, and judge whether the inductor current in the corresponding switch circuit is reversed according to the comparison result, And the inductance current reverse indication signal is transmitted to the host controller through the communication bus.
  • the detection and control module is further configured to receive a threshold setting signal from the host controller via the communication bus, and set the current threshold according to the threshold setting signal.
  • a control circuit for a multi-phase switching converter which is connected together with other control circuits to form a daisy-chain architecture, the multi-phase switching converter includes a plurality of parallel-coupled The switch circuit, the control circuit includes: a first end, coupled to the second end of the previous control circuit in the daisy chain architecture to receive the ready state input signal; a second end, coupled to the daisy chain architecture A first end of the latter control circuit to provide a ready state output signal; and a third end coupled to the communication bus to receive a clock signal, wherein the control circuit is configured to receive the ready state input signal It works in a ready state, and generates a ready state output signal and a switch control signal for controlling a corresponding switch circuit when the ready state receives the clock signal.
  • control circuit when the control circuit is configured as the first control circuit in the daisy chain architecture, its first end is coupled to the loopback connection, and the control circuit is configured as the first control circuit in the daisy chain architecture
  • the control circuit When the last control circuit in the control circuit, its second end is coupled to the loopback connection, so that the control circuit and the remaining control circuits form a loop chain.
  • the switch control signal has a high level state, a low level state, and an intermediate level state
  • the corresponding switch circuit can respond to the above three states of the switch control signal, including turning on the upper transistor, turning on Action through the downtube and in a high-resistance state.
  • the ready-state input signal includes a turn-on ready-state input signal and a freewheeling ready-state input signal.
  • the ready state output signal includes an on ready state output signal and a freewheeling ready state output signal.
  • the clock signal includes a turn-on clock signal and a freewheeling clock signal.
  • control circuit includes: a configuration register, configured to configure whether the corresponding control circuit participates in the loop chain, whether it is the first control circuit, and whether it is the last control circuit.
  • control circuit includes: a reset control module, configured to transmit a state feedback signal to the upper controller via the communication bus, and the upper controller judges whether there is only one control in the loop chain according to the state feedback signal.
  • the circuit is in the ready state, wherein when no or more than one control circuit in the loop chain is in the ready state, the reset control module receives a reset signal from the upper controller via the communication bus to execute circuit reset.
  • control circuit includes: a counting module, configured to count the pulses of the clock signal in the preparation state, determine the total number of phases in the cycle chain at the current moment, and count the total number of phases It is transmitted to the host controller through the communication bus.
  • a counting module configured to count the pulses of the clock signal in the preparation state, determine the total number of phases in the cycle chain at the current moment, and count the total number of phases It is transmitted to the host controller through the communication bus.
  • control circuit includes: a phase-cutting control module, configured to receive a phase-cutting instruction from a host controller via the communication bus in the preparation state, and judge whether to enable the corresponding switching circuit based on the phase-cutting instruction Stop power output or start power output.
  • a phase-cutting control module configured to receive a phase-cutting instruction from a host controller via the communication bus in the preparation state, and judge whether to enable the corresponding switching circuit based on the phase-cutting instruction Stop power output or start power output.
  • control circuit includes: a detection and control module configured to compare the current sampling signal of the corresponding switch circuit with the current threshold, and judge whether the inductor current in the corresponding switch circuit is reversed according to the comparison result, And the inductance current reverse indication signal is transmitted to the host controller through the communication bus.
  • the detection and control module is further configured to receive a threshold setting signal from the host controller via the communication bus, and set the current threshold according to the threshold setting signal.
  • the multi-phase switching converter of the embodiment of the present disclosure includes a plurality of control circuits connected in a daisy-chain architecture, wherein the control circuits are configured to work in the standby state when receiving the standby input signal, and receive signals from the communication bus in the standby state When the clock signal is generated, the ready state output signal and the switch control signal for controlling the corresponding switch circuit are generated. Due to the daisy chain architecture, users can easily adjust the total number of phases of the multi-phase switch according to the needs of specific applications. If the number of phases needs to be increased, only new control circuits and corresponding external components need to be added to the daisy chain architecture.
  • the multiple control circuits in the loop chain only transmit the ready state signal, and the signal started by the control circuit is participated by the clock signal generated by the upper controller, so the upper controller does not need to track the current unit in real time during the control process of all units
  • the location can greatly simplify the design of the host controller and reduce the circuit cost.
  • the multi-phase switching converters in the embodiments of the present disclosure use unified and simple chips or circuits to build a circular chain, which only requires the control circuits in the circular chain to maintain the sequence, and does not require them to be connected in sequence, which simplifies the difficulty of circuit modification , greatly reducing the cost of the circuit.
  • FIG. 1 is a schematic block diagram of a multi-phase switching converter 100 according to an embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of a control circuit 101A according to an embodiment of the present disclosure
  • 3 is an analog and logic combination detection circuit for detecting more than one control circuit entering a ready state according to an embodiment of the present disclosure
  • FIG. 4 is a state transition diagram of the control circuit 101A according to an embodiment of the disclosure.
  • FIG. 1 is a schematic block diagram of a multi-phase switching converter 100 according to an embodiment of the present disclosure, including switching circuits 111-11N (N is an integer greater than 1) coupled in parallel and connected in a daisy chain (daisy chain) architecture. Control circuits 101 to 10N. Wherein, each switch circuit has an input terminal coupled to the input voltage Vin and an output terminal coupled to the load to provide the output voltage Vout.
  • the control circuit 101i is configured to enter the ready state upon receiving the ready state input signals Takei_on and Takei_off, and when the pulses of the clock signals CP_on and CP_off are detected in the ready state, generate the ready state output signals Passi_on and Passi_off and control the corresponding switch circuit 11i
  • the switch control signal PWMi is a synchronous step-down circuit, including a high-side switch HSi, a low-side switch LSi, an inductor Li, and an output capacitor Coi.
  • the switch control signal PWMi has three level states.
  • the switch control signal PWMi When the switch control signal PWMi is in the high level state, the upper tube HSi is turned on and the lower tube LSi is turned off; when the switch control signal PWMi is in the low level state, the upper tube HSi is in the low level state.
  • the lower switch LSi When the switch is turned off, the lower switch LSi is turned on; when the switch control signal PWMi is in the middle level state, the freewheeling diode of the upper switch HSi enters a high-impedance state, causing the output current to drop rapidly.
  • control circuit 101i when the control circuit 101i receives the input signal Takei_on of the ready state, it enters the ready state for turning on, and the ready state refers to a state between the shutdown and the full start of the control circuit 101i.
  • the control circuit 101i generally completes the configuration of relevant parameters and settings in the ready state, and at the same time, the control circuit 101i also judges whether the pulse of the clock signal CP_on is detected in the ready state for turning on.
  • the control circuit 101i 101i When the pulse of the clock signal CP_on is detected, the control circuit 101i 101i is officially started and enters the ON state, and outputs the ON-ready output signal Passi_on and the switch control signal PWMi in a high level state, so that the upper switch HSi in the switch circuit 11i is turned on, and the lower switch LSi is turned off.
  • control circuit 101i When the control circuit 101i receives the freewheeling preparation state input signal Takei_off, it enters the freewheeling preparation state, and the control circuit 101i judges whether the freewheeling clock signal CP_off is detected in the freewheeling preparation state, and when the freewheeling clock signal CP_off is detected, The control circuit 101i enters the freewheeling state, and outputs the freewheeling ready state output signal Passi_off and the switch control signal PWMi at low level, so that the upper switch HSi in the switch circuit 11i is turned off, and the lower switch LSi is turned on.
  • the switch control signals PWM1 ⁇ PWMN are synchronized with the pulses of the on-clock signal CP_on and the free-wheeling clock signal CP_off respectively.
  • the rising edge of the switch control signal PWMi is synchronized with the on-clock signal CP_on, so that when the on-clock signal CP_on is detected, the upper switch HSi is turned on and the lower switch LSi is turned off; the falling edge of the switch control signal PWMi is synchronized with the freewheeling
  • the clock signal CP_off is synchronized, so that when the freewheeling clock signal CP_off is detected, the upper switch HSi is turned off, the lower switch LSi is turned on, and the corresponding switch circuit 11i is triggered to provide power output to the load.
  • the duty cycles of the switching control signals PWM1 ⁇ PWMN are modulated based on the time intervals of the on clock signal CP_on and the freewheeling clock signal CP_off .
  • the first end of the first control circuit among the plurality of control circuits 101-10N and the second end of the last control circuit among the plurality of control circuits 101-10N are coupled to the loopback line , so that a plurality of control circuits 101-10N form a loop chain.
  • Any one of the plurality of control circuits 101-10N can be used as the first control circuit and the last control circuit without corresponding to its physical position in the daisy chain architecture.
  • a control circuit is configured as the first control circuit Or the last control circuit, you only need to connect it to the loopback connection through the internal logic to form a circular chain. It only requires that the control circuits in the circular chain maintain the sequence, and it does not require that they must be connected in sequence. Therefore, It can greatly improve the convenience for users to design circuits according to specific applications.
  • the daisy chain architecture Due to the daisy chain architecture, users can easily adjust the total number of phases of the multi-phase switch according to the needs of specific applications. If the number of phases needs to be increased, only new control circuits and corresponding external components need to be added to the daisy chain architecture. In addition, the multiple control circuits in the loop chain only transmit the ready state signal, and the signal started by the control circuit is participated by the clock signal generated by the upper controller, so the upper controller does not need to distinguish the current unit’s position, can greatly simplify the design of the upper controller and reduce the circuit cost.
  • each control circuit is coupled to a communication bus, and can communicate with an upper controller via the communication bus.
  • the upper controller can judge whether only one control circuit in the current loop chain is in the ready state based on the state feedback signals transmitted by each control circuit, and perform circuit reset based on the judgment result.
  • the host controller decides whether to perform phase cut based on the current sampling signals transmitted by each control circuit, the total number of phases in the current cycle chain and/or the load current, and generates a phase cut command.
  • Each control circuit receives the phase-cutting instruction from the host controller through the communication bus, and judges based on the phase-cutting instruction whether to make the corresponding switch circuit stop power output or start power output, and make the corresponding switch circuit stop power output while making the ready state input signal Equal to the ready state output signal.
  • the communication bus here can use common buses such as I2C, SPI, SCI, UART, and CAN.
  • I2C I2C
  • SPI SPI
  • SCI SCI
  • UART UART
  • CAN CAN-based communication protocol
  • FIG. 2 is a schematic block diagram of a control circuit 101A according to an embodiment of the present disclosure, including a switch control module 1011 and a configuration register 1012 .
  • the switch control module 1011 generates the on-ready output signal Pass1_on based on the on-ready input signal Take1_on and the on-clock signal CP_on, and simultaneously outputs the switch control signal PWM1 at a high level.
  • the switch control module 1011 generates the freewheel ready state output signal Passi_off based on the freewheel ready state input signal Take1_off and the freewheel clock signal CP_off, and simultaneously outputs the switch control signal PWM1 in a low level state.
  • the configuration register 1012 is used to configure whether the control circuit 101A participates in the loop chain (Nonuse bit), whether it is the first control circuit (Head bit) and whether it is the last control circuit (Tail bit).
  • the configuration register 1012 is configured as the Nonuse bit, the control circuit 101A does not participate in the loop chain, and the circuit is short-circuited internally, and is only used to transmit the ready state signal, that is, the ready state input signal is equal to the ready state output signal.
  • the configuration register 1012 is configured as the Head bit
  • the control circuit 101A couples the first end to the loopback line through internal logic.
  • the configuration register 1012 is configured as the Tail bit
  • the control circuit 101A couples the first terminal to the loopback line through internal logic.
  • the control circuit 101A further includes a reset control module 1013 .
  • the reset control module 1013 is used to transmit status feedback signals Wired_OR_on>0, Wired_AND_on ⁇ 2, Wired_OR_off>0 and Wired_AND_off ⁇ 2 to the host controller via the communication bus, and the host controller judges whether there is only one in the loop chain based on the status feedback signal
  • the control circuit is in the ready state.
  • the upper controller provides a reset signal to the first control circuit via the communication bus (that is, the signal Nomal is low), and the first
  • the reset control module 1013 of each control circuit executes circuit reset based on the reset signal, and restarts the entire loop chain.
  • Wired_OR_on>0 and Wired_OR_off>0 indicate whether there is a control circuit in the current loop chain in the ready state.
  • Wired_OR_on>0 and Wired_OR_off>0 are high, it means that the control circuit in the current loop chain is in the ready state.
  • Wired_OR_on> When 0 and Wired_OR_off>0 are low level, it means that no control circuit in the current circuit is in the ready state.
  • Wired_AND_on ⁇ 2 and Wired_AND_off ⁇ 2 indicate whether the number of control circuits in the preparatory state in the current loop chain is less than 2.
  • Wired_AND_on ⁇ 2 and Wired_AND_off ⁇ 2 When Wired_AND_on ⁇ 2 and Wired_AND_off ⁇ 2 are high, it represents the number of control circuits in the preparatory state in the current loop chain is less than 2, when Wired_AND_on ⁇ 2 and Wired_AND_off ⁇ 2 are low, it indicates that the number of control circuits in the ready state in the current loop chain is greater than 2.
  • Figure 3 is an analog and logic combination detection circuit for detecting more than one control circuit entering a ready state according to an embodiment of the present disclosure.
  • the transistors M1-MN in Figure 3 are equivalent to a plurality of control circuits 101-10N, in The control circuit in the ready state outputs a line AND output with a positive constant current I, and the corresponding output of other control circuits is connected to the pull-up load M0 with a positive constant pull-up current of 1.5*I. If only one control circuit is in the ready state , the signal Wired_AND_on ⁇ 2 cannot be made to be at a logic low level, and if more than one control circuit is in a ready state, then Wired_AND_on ⁇ 2 is at a logic low level. Utilizing this analog circuit can not only realize the detection of the parasitic state in the preparatory state in the loop chain, but also has a simple circuit, which can greatly reduce the scale of the circuit.
  • the control circuit 101A further includes a counting module 1014 , a phase cutting control module 1015 and a detection and control module 1016 .
  • the counting module 1014 is used to count the pulses of the clock signal CP_on and/or CP_off in the preparation state, and obtain the number of pulses at the current moment, thereby judging the total phase number Total_NO in the cycle chain at the current moment, and counting the total phase number The number Total_NO is transmitted to the host controller through the communication bus.
  • the multi-phase switching converter 100 further includes a common pulse counter, and each control circuit acquires the count value of the common pulse counter when it is in the standby state, and subtracts it from the last acquired count value, Get the total number of phases in the current cycle chain.
  • the phase cut control module 1015 is used to receive the phase cut instructions Add and Drop from the host controller via the communication bus in the ready state, and judge whether to exit or join the cycle based on the phase cut instructions. For example, when the load is too light, the upper controller provides a phase cut command Drop to perform a phase subtraction operation; when the load is too heavy, the upper controller provides a phase cut command Add to perform a phase addition operation.
  • FIG. 4 is a state transition diagram of the control circuit 101A according to an embodiment of the disclosure. As shown in FIG.
  • the control circuit 101A enters the standby state when it receives the input signal Take1_on to turn on the standby state, and judges in the standby state whether to detect The phase-cut command Drop, if the phase-cut command Drop is received in the ready state, it will exit the loop when it receives the on-clock signal CP_on, so that the corresponding switch circuit 111 stops power output, and makes the ready state input signal equal to the ready state Output signal; when the control circuit 101A is in the disengagement state, it enters the preparation state when it receives the input signal Take1_on of the connection preparation state, and judges whether the phase-cutting command Add is detected in the preparation state, if received in the preparation state When the phase cut instruction Add is received, it adds a cycle when receiving the clock signal CP_on, so that the corresponding switch circuit 111 starts to output power.
  • the transition of the control circuit 101A in FIG. 4 between the freewheeling state and the on state has been described above, and will not be repeated here.
  • the detection and control module 1016 is configured to compare the current sampling signal Irc of the switch circuit 111 with the current threshold, and judge whether the inductor current in the corresponding switch circuit is reversed according to the comparison result, and reverse the inductor current
  • the indication signal DCM is transmitted to the upper controller through the communication bus.
  • the detection and control module 1016 is also configured to receive the threshold setting signal U and the high-impedance state control signal Z from the upper controller via the communication bus, and set the high and low currents of the circuit according to the threshold setting signal U The threshold and the switching between the two control the switch control module 1011 to output the switch control signal PWM1 to an intermediate level according to the high-impedance control signal Z, so that the switch circuit 111 works in the high-impedance state.
  • control circuits 101-10N in FIG. 1 can respectively have the same structure as the circuit shown in FIG. 2, so a simple and unified chip or circuit can be used to construct the loop chain in FIG. Circuit design reduces circuit cost.
  • the multi-phase switching converter includes a plurality of control circuits connected in a daisy-chain architecture, wherein the control circuits are configured to work in the standby state when receiving the standby input signal, and When the ready state receives the clock signal from the communication bus, the ready state output signal and the switch control signal for controlling the corresponding switch circuit are generated. Due to the daisy chain architecture, users can easily adjust the total number of phases of the multi-phase switch according to the needs of specific applications. If the number of phases needs to be increased, only new control circuits and corresponding external components need to be added to the daisy chain architecture.
  • the multiple control circuits in the loop chain only transmit the ready state signal, and the signal started by the control circuit is participated by the clock signal generated by the upper controller, so the upper controller does not need to track the current unit in real time during the control process of all units
  • the location can greatly simplify the design of the host controller and reduce the circuit cost.
  • the multi-phase switching converters in the embodiments of the present disclosure use unified and simple chips or circuits to build a circular chain, which only requires the control circuits in the circular chain to maintain the sequence, and does not require them to be connected in sequence, which simplifies the difficulty of circuit modification , greatly reducing the cost of the circuit.
  • Embodiments according to the present disclosure are as above, and these embodiments do not describe all details in detail, nor do they limit the disclosure to only specific embodiments. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and its modifications based on the present disclosure. The protection scope of the present disclosure should be defined by the claims of the present disclosure.

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Abstract

本申请公开了一种多相开关变换器及其控制电路，包括连接为菊花链架构的多个控制电路，其中控制电路被配置为在接收到预备态输入信号时工作于预备状态，并在预备状态接收到来自通信总线的时钟信号时产生预备态输出信号以及控制对应开关电路的开关控制信号。多个控制电路之间仅传递预备态信号，控制电路启动的信号由上位控制器生成的时钟信号参与，因此上位控制器对所有的单元的控制过程中不必实时跟踪当前单元的位置，可以大大简化上位控制器的设计，降低电路成本。

Description

多相开关变换器及其控制电路
本申请要求了申请日为2021年10月28日、申请号为202111261865.X、名称为“多相开关变换器及其控制电路”的中国发明申请的优先权，并且通过参照上述中国发明申请的全部说明书、权利要求、附图和摘要的方式，将其引用于本申请。
技术领域
本公开涉及电源技术领域，更具体地，涉及一种多相开关变换器及其控制电路。
背景技术
物联网(IoT)云端服务规模的指数级增长推动了数据中心、网络和电信设备的显著进步，同时持续增加的数据和信息对数据中心的服务器的处理效率提出了新的挑战，因此如何高效地为这些设备供电和散热，同时将用电量降到最低，成为现有的电源技术领域的重要课题。
多相开关变换器是将多个开关电路并联，并把开关调制过程分配到不同的相来实现对电源的调整控制的技术。多相电源中的相与相之间的PWM(pulse width modulation，脉宽调制)信号可以相同或者错开一定的相位，使得输出和输入看到的波动频率是每一相中的开关频率与相数的乘积，从而可以减少滤波电容的需要和降低对输入的电流冲击，同时可以加快对负载变化的响应。多相开关变换器以其优越的性能，被广泛应用于高性能CPU的电源解决方案。
对于采用单个控制器的多相开关变换器而言，如果负载电流需求增大，控制电路变换器的相数需随之增加，相应地，控制器的逻辑、电路、控制电路结构与尺寸也需随之进行调整，控制电路这无疑极大地增加了系统的开发难度与整体成本。
发明内容
鉴于上述问题，本公开的目的在于提供一种多相开关变换器及其控制电路。
根据本公开实施例的一方面，提供了一种多相开关变换器，包括：多个并联耦接的开关电路，其中每个开关电路均具有耦接至输入电压的输入端和耦接至负载以提供输出电压的输出端；以及连接为菊花链架构的多个控制电路，分别耦接至所述多个开关电路，其中，每个控制电路均具有第一端、第二端与第三端，其中第一端耦接至前一控制电路的第二端以接收预备态输入信号，第二端耦接至后一控制电路的第一端以提供预备态输出信号，第三端耦接至通信总线以接收时钟信号，其中，每个控制电路被配置为在接收到所述预备态输入信号时工作于预备状态，并在所述预备状态接收到所述时钟信号时产生预备态输出信号以及控制对应开关电路的开关控制信号。
可选的，所述多个控制电路中的第一个控制电路的第一端以及所述多个控制电路中的最后一个控制电路的第二端耦接至环回连线上，以将所述多个控制电路构成一个循环链。
可选的，所述开关控制信号具有高电平状态、低电平状态以及中间电平状态，对应的开关电路能够响应于所述开关控制信号的上述三种状态执行包括导通上管、导通下管以及处于高阻状态的动作。
可选的，所述预备态输入信号包括接通预备态输入信号和续流预备态输入信号。
可选的，所述预备态输出信号包括接通预备态输出信号和续流预备态输出信号。
可选的，所述时钟信号包括接通时钟信号和续流时钟信号。
可选的，每个控制电路包括：配置寄存器，用于配置对应的控制电路是否参与循环链、是否为第一个控制电路以及是否为最后一个控制电路。
可选的，每个控制电路包括：复位控制模块，用于经所述通信总线向上位控制器传递状态反馈信号，所述上位控制器根据所述状态反馈信 号判断循环链中是否仅有一个控制电路处于预备状态，其中，当所述循环链中没有或超过一个控制电路处于预备状态时，所述复位控制模块经所述通信总线接收来自所述上位控制器的复位信号，执行电路复位。
可选的，每个控制电路包括：计数模块，用于在所述预备状态对所述时钟信号的脉冲进行计数，判断当前时刻所述循环链中的总相数，并将所述总相数经所述通信总线传递至上位控制器。
可选的，每个控制电路包括：切相控制模块，用于在所述预备状态经所述通信总线接收来自上位控制器的切相指令，并基于所述切相指令判断是否使对应开关电路停止功率输出或开始功率输出。
可选的，每个控制电路包括：检测和控制模块，被配置为将对应的开关电路的电流采样信号与电流阈值进行比较，并根据比较结果判断对应的开关电路中的电感电流是否反向，并将电感电流反向指示信号经所述通信总线传递至上位控制器。
可选的，所述检测和控制模块还被配置为经所述通信总线接收来自所述上位控制器的阈值设置信号，并根据所述阈值设置信号设置所述电流阈值。
根据本公开实施例的另一方面，提供了一种用于多相开关变换器的控制电路，与其余控制电路连接在一起形成菊花链架构，所述多相开关变换器包括多个并联耦接的开关电路，所述控制电路包括：第一端，耦接至所述菊花链架构中前一控制电路的第二端以接收预备态输入信号；第二端，耦接至所述菊花链架构中后一控制电路的第一端以提供预备态输出信号；以及第三端，耦接至通信总线以接收时钟信号，其中，所述控制电路被配置为在接收到所述预备态输入信号时工作于预备状态，并在所述预备状态接收到所述时钟信号时产生预备态输出信号以及控制对应开关电路的开关控制信号。
可选的，所述控制电路被设置为所述菊花链架构中的第一个控制电路时，其第一端耦接至环回连线上，所述控制电路被设置为所述菊花链架构中的最后一个控制电路时，其第二端耦接至环回连线上，以将所述控制电路与其余多个控制电路构成一个循环链。
可选的，所述开关控制信号具有高电平状态、低电平状态以及中间电平状态，对应的开关电路能够响应于所述开关控制信号的上述三种状态执行包括导通上管、导通下管以及处于高阻状态的动作。
可选的，所述预备态输入信号包括接通预备态输入信号和续流预备态输入信号。
可选的，所述预备态输出信号包括接通预备态输出信号和续流预备态输出信号。
可选的，所述时钟信号包括接通时钟信号和续流时钟信号。
可选的，所述的控制电路包括：配置寄存器，用于配置对应的控制电路是否参与循环链、是否为第一个控制电路以及是否为最后一个控制电路。
可选的，所述控制电路包括：复位控制模块，用于经所述通信总线向上位控制器传递状态反馈信号，所述上位控制器根据所述状态反馈信号判断循环链中是否仅有一个控制电路处于预备状态，其中，当所述循环链中没有或超过一个控制电路处于预备状态时，所述复位控制模块经所述通信总线接收来自所述上位控制器的复位信号，执行电路复位。
可选的，所述控制电路包括：计数模块，用于在所述预备状态对所述时钟信号的脉冲进行计数，判断当前时刻所述循环链中的总相数，并将所述总相数经所述通信总线传递至上位控制器。
可选的，所述控制电路包括：切相控制模块，用于在所述预备状态经所述通信总线接收来自上位控制器的切相指令，并基于所述切相指令判断是否使对应开关电路停止功率输出或开始功率输出。
可选的，所述控制电路包括：检测和控制模块，被配置为将对应的开关电路的电流采样信号与电流阈值进行比较，并根据比较结果判断对应的开关电路中的电感电流是否反向，并将电感电流反向指示信号经所述通信总线传递至上位控制器。
可选的，所述检测和控制模块还被配置为经所述通信总线接收来自所述上位控制器的阈值设置信号，并根据所述阈值设置信号设置所述电流阈值。
本公开实施例的多相开关变换器包括连接为菊花链架构的多个控制电路，其中控制电路被配置为在接收到预备态输入信号时工作于预备状态，并在预备状态接收到来自通信总线的时钟信号时产生预备态输出信号以及控制对应开关电路的开关控制信号。由于采用了菊花链架构，用户可以根据具体应用的需要轻松调节多相开关其的总相数，如果需要增加相数，只需要在菊花链架构中加入新的控制电路及对应外部元件即可。
此外，循环链中的多个控制电路之间仅传递预备态信号，控制电路启动的信号由上位控制器生成的时钟信号参与，因此上位控制器对所有的单元的控制过程中不必实时跟踪当前单元的位置，可以大大简化上位控制器的设计，降低电路成本。
此外，本公开实施例的多相开关变换器采用统一、简单的芯片或电路构建循环链，只要求循环链中的控制电路保持先后顺序，并不要求其必须顺序连接，简化了电路修改的难度，大大降低了电路的成本。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1为根据本公开实施例的多相开关变换器100的示意性框图；
图2为根据本公开实施例的控制电路101A的示意性框图；
图3为根据本公开实施例的一种用于检测超过一个控制电路进入预备状态的模拟和逻辑组合检测电路；
图4为根据本公开实施例的控制电路101A的状态转移图。
具体实施方式
下面将结合附图详细描述本公开的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本公开。在以下描述中，为了便于对本公开的透彻理解，阐述了大量特定细节。然而，本领域普通技术人员可以理解，这些特定细节并非为实施本公开所必需。此外，在 一些实施例中，为了避免混淆本公开，未对公知的电路、材料或方法做具体描述。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本公开至少一个实施例中。闪此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图均是为了说明的目的，其中相同的附图标记指示相同的元件。应当理解，当称元件“连接到”或“耦接”到另一元件时，它可以是直接连接或耦接到另一元件或者可以存在中间元件。相反，当称元件“直接连接到”或“直接耦接到”另一元件吋，不存在中间元件。此外，说明书中所指的相互同步或相等的信号，在实际应用中，由于信号处理造成的延时，彼此之间也许存在少许时差。
图1为根据本公开实施例的多相开关变换器100的示意性框图，包括并联耦接的开关电路111～11N(N为大于1的整数)、以及连接为菊花链(daisy chain)架构的控制电路101～10N。其中，其中每个开关电路均具有耦接至输入电压Vin的输入端和耦接至负载以提供输出电压Vout的输出端。控制电路101～10N分别耦接至开关电路111～11N，其中每个控制电路10i(i＝1,2,……N)均具有第一端、第二端与第三端，其中第一端耦接至前一控制电路的第二端以接收接通预备态输入信号Takei_on和续流预备态输入信号Takei_off，第二端耦接至后一控制电路的第一端以提供接通预备态输出信号Passi_on和续流预备态输出信号Passi_off，第三端耦接至通信总线以接收接通时钟信号CP_on和续流时钟信号CP_off(图中未示出)。控制电路101i被配置为在接收到预备态输入信号Takei_on和Takei_off进入预备状态，并在预备状态当检测到时钟信号CP_on和CP_off的脉冲时，产生预备态输出信号Passi_on和Passi_off以及控制对应开关电路11i的开关控制信号PWMi。在一些实施例中，开关电路11i为同步降压电路，包括上管HSi、下管LSi、电感Li和输 出电容器Coi。开关控制信号PWMi具有三种电平状态，当开关控制信号PWMi为高电平状态时，上管HSi导通，下管LSi关断；当开关控制信号PWMi为低电平状态时，上管HSi关断，下管LSi导通；当开关控制信号PWMi为中间电平状态时，上管HSi的续流二极管进入高阻态，让输出电流快速下降。
在一些实施例中，控制电路101i在接收到接通预备态输入信号Takei_on时，进入接通预备状态，所述的预备状态是指控制电路101i介于关闭和完全启动之间的状态，控制电路101i一般在预备状态完成相关参数和设置的配置，同时控制电路101i还在该接通预备状态判断是否检测到接通时钟信号CP_on的脉冲，当检测到接通时钟信号CP_on的脉冲时，控制电路101i正式启动，并进入接通状态，输出接通预备态输出信号Passi_on和开关控制信号PWMi为高电平状态，使得开关电路11i中的上管HSi导通，下管LSi关断。当控制电路101i接收到续流预备态输入信号Takei_off时，进入续流预备状态，同时控制电路101i在续流预备状态判断是否检测到续流时钟信号CP_off，当检测到续流时钟信号CP_off时，控制电路101i进入续流状态，输出续流预备态输出信号Passi_off和开关控制信号PWMi为低电平，使得开关电路11i中的上管HSi关断，下管LSi导通。
一般的，开关控制信号PWM1～PWMN分别与接通时钟信号CP_on和续流时钟信号CP_off的脉冲同步。例如，开关控制信号PWMi的上升沿与接通时钟信号CP_on同步，从而在检测到接通时钟信号CP_on时使得上管HSi导通，下管LSi关断；开关控制信号PWMi的下降沿与续流时钟信号CP_off同步，从而在检测到续流时钟信号CP_off时使得上管HSi关断，下管LSi导通，触发对应开关电路11i向负载提供功率输出。在一些实施例中，基于接通时钟信号CP_on和续流时钟信号CP_off的时间间隔来调制开关控制信号PWM1～PWMN的占空比。
在一些实施例中，多个控制电路101～10N中的第一个控制电路的第一端以及多个控制电路101～10N中的最后一个控制电路的第二端耦接至环回连线上，以将多个控制电路101～10N构成一个循环链。其中多个控 制电路101～10N中的任何一个都可以作为第一个控制电路和最后一个控制电路，无需与其在菊花链架构的物理位置相对应，当一个控制电路被配置为第一个控制电路或最后一个控制电路时，只需要通过内部逻辑将其连接到环回连线上，即可构成一个循环链，只要求循环链中的控制电路保持先后顺序，并不要求其必须顺序连接，因此可以大大提高用户根据具体应用设计电路的便捷性。
由于采用了菊花链架构，用户可以根据具体应用的需要轻松调节多相开关其的总相数，如果需要增加相数，只需要在菊花链架构中加入新的控制电路及对应外部元件即可。此外，循环链中的多个控制电路之间仅传递预备态信号，控制电路启动的信号由上位控制器生成的时钟信号参与，因此上位控制器对所有的单元的控制过程中无需区分当前单元的位置，可以大大简化上位控制器的设计，降低电路成本。
在一个实施例中，各控制电路均耦接至通信总线，可以经过通信总线与上位控制器进行通信。上位控制器可以基于各个控制电路传递的状态反馈信号判断当前循环链中是否仅有一个控制电路处于预备状态，并基于判断结果来执行电路复位。或者上位控制器基于各个控制电路传递的电流采样信号、当前循环链中的总相数和/或负载电流决定是否进行切相，并产生切相指令。各控制电路通过通信总线接收来自上位控制器的切相指令，并基于切相指令判断是否使得对应开关电路停止功率输出或开始功率输出，在使得对应开关电路停止功率输出的同时使得预备态输入信号等于预备态输出信号。
此处的通信总线可以采用I2C、SPI、SCI、UART、CAN等常用总线。当采用I2C总线时，可以选用PMBUS或SMBUS协议。
图2为根据本公开实施例的控制电路101A的示意性框图，包括开关控制模块1011和配置寄存器1012。开关控制模块1011基于接通预备态输入信号Take1_on和接通时钟信号CP_on产生接通预备态输出信号Pass1_on，同时输出开关控制信号PWM1为高电平状态。开关控制模块1011基于续流预备态输入信号Take1_off和续流时钟信号CP_off产生续流预备态输出信号Passi_off，同时输出开关控制信号PWM1为低电平状 态。
配置寄存器1012用于配置控制电路101A是否参与循环链(Nonuse位)、是否为第一个控制电路(Head位)以及是否为最后一个控制电路(Tail位)。其中当配置寄存器1012配置为Nonuse位时，控制电路101A不参与循环链，电路内部短接，仅用于传递预备态信号，即使得预备态输入信号等于预备态输出信号。当配置寄存器1012配置为Head位时，控制电路101A通过内部逻辑将第一端耦接至环回连线上。当配置寄存器1012配置为Tail位时，控制电路101A通过内部逻辑将第一端耦接至环回连线上。
在一些实施例中，控制电路101A还包括复位控制模块1013。复位控制模块1013用于经通信总线向上位控制器传递状态反馈信号Wired_OR_on>0,Wired_AND_on<2,Wired_OR_off>0和Wired_AND_off<2，上位控制器基于所述状态反馈信号判断循环链中是否仅有一个控制电路处于预备状态，当所述循环链中没有或超过一个控制电路处于预备状态时，上位控制器经通信总线向第一个控制电路提供复位信号(即信号Nomal为低电平)，第一个控制电路的复位控制模块1013基于该复位信号执行电路复位，重启整个循环链。其中，Wired_OR_on>0和Wired_OR_off>0表征当前循环链中是否存在控制电路处于预备状态，当Wired_OR_on>0和Wired_OR_off>0为高电平时，表征当前循环链中存在控制电路处于预备状态，当Wired_OR_on>0和Wired_OR_off>0为低电平时，表征当前电路中没有控制电路处于预备状态。Wired_AND_on<2和Wired_AND_off<2表征当前循环链中处于预备状态的控制电路的数量是否小于2，当Wired_AND_on<2和Wired_AND_off<2为高电平时，表征当前循环链中处于预备状态的控制电路的数量小于2，当Wired_AND_on<2和Wired_AND_off<2为低电平时，表征当前循环链中处于预备状态的控制电路的数量大于2。
如图3为根据本公开实施例的一种用于检测超过一个控制电路进入预备状态的模拟和逻辑组合检测电路，图3中的晶体管M1～MN等效于多个控制电路101～10N，处于预备状态的控制电路输出一个正定电流为I 的线与输出，与其他的控制电路的相应输出连接在正定上拉电流为1.5*I的上拉负载M0上，如果仅有一个控制电路处于预备状态，则无法使得信号Wired_AND_on<2呈现为逻辑低电平，如果超过一个控制电路处于预备状态，则Wired_AND_on<2呈现为逻辑低电平。利用这个模拟电路不仅可以实现循环链中处于预备状态的寄生状态检测，而且电路简单，可以大大减小电路规模。
继续参照图2，在一些实施例中，控制电路101A还包括计数模块1014、切相控制模块1015以及检测和控制模块1016。计数模块1014用于在所述预备状态对时钟信号CP_on和/或CP_off的脉冲进行计数，获取当前时刻的脉冲个数，从而判断当前时刻循环链中的总相数Total_NO，并将所述总相数Total_NO经通信总线传递至上位控制器。在另外一些实施例中，多相开关变换器100还包括一个公共脉冲计数器，每个控制电路在处于预备状态时获取该公共脉冲计数器的计数值，将其与上一次获取的计数值相减，获得当前循环链中的总相数。
切相控制模块1015用于在预备状态经通信总线接收来自上位控制器的切相指令Add和Drop，并基于切相指令判断是否退出或加入循环。例如，当负载过轻时，上位控制器提供切相指令Drop，进行减相操作；当负载过重时，上位控制器提供切相指令Add，进行加相操作。图4为根据本公开实施例的控制电路101A的状态转移图，如图4所示，控制电路101A在接收到接通预备态输入信号Take1_on时进入预备状态，并在预备状态下判断是否检测到切相指令Drop，若在预备状态下接收到切相指令Drop，则其在接收到接通时钟信号CP_on时退出循环，使得对应的开关电路111停止功率输出，并使得预备态输入信号等于预备态输出信号；当控制电路101A在脱离状态下时，其在接收到接通预备态输入信号Take1_on时进入预备状态，并在预备状态下判断是否检测到切相指令Add，若在该预备状态下接收到切相指令Add，则其在接收到时钟信号CP_on时加入循环，使得对应的开关电路111开始输出功率。此外，图4中控制电路101A在续流状态和接通状态之间的转移在上面已经说明过，在此不再赘述。
继续参照图2，检测和控制模块1016配置为将开关电路111的电流采样信号Irc与电流阈值进行比较，并根据比较结果判断对应的开关电路中的电感电流是否反向，并将电感电流反向指示信号DCM经所述通信总线传递至上位控制器。此外，检测和控制模块1016还配置为经所述通信总线接收来自所述上位控制器的阈值设置信号U和高阻态控制信号Z，并根据所述阈值设置信号U设置电路的高、低电流阈值以及二者之间的切换，根据高阻态控制信号Z控制开关控制模块1011输出开关控制信号PWM1为中间电平，以使得开关电路111工作于高阻状态。
需要说明的是，图1中的多个控制电路101～10N可以分别具有和图2所示电路相同的结构，因此可以采用简单、统一的芯片或电路构建图1中的循环链，大大简化了电路的设计，降低电路成本。
综上所述，根据本公开实施例的多相开关变换器，包括连接为菊花链架构的多个控制电路，其中控制电路被配置为在接收到预备态输入信号时工作于预备状态，并在预备状态接收到来自通信总线的时钟信号时产生预备态输出信号以及控制对应开关电路的开关控制信号。由于采用了菊花链架构，用户可以根据具体应用的需要轻松调节多相开关其的总相数，如果需要增加相数，只需要在菊花链架构中加入新的控制电路及对应外部元件即可。
此外，循环链中的多个控制电路之间仅传递预备态信号，控制电路启动的信号由上位控制器生成的时钟信号参与，因此上位控制器对所有的单元的控制过程中不必实时跟踪当前单元的位置，可以大大简化上位控制器的设计，降低电路成本。
此外，本公开实施例的多相开关变换器采用统一、简单的芯片或电路构建循环链，只要求循环链中的控制电路保持先后顺序，并不要求其必须顺序连接，简化了电路修改的难度，大大降低了电路的成本。
在以上的描述中，对公知的结构要素和步骤并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来实现相应的结构要素和步骤。另外，为了形成相同的结构要素，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上 分别描述各实施例，但是这不意味着各个实施例中的措施不能有利地结合使用。
依照本公开的实施例如上文，这些实施例并没有详尽叙述所有的细节，也不限制该公开仅为的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本公开的原理和实际应用，从而使所属技术领域技术人员能很好地利用本公开以及在本公开基础上的修改使用。本公开的保护范围应当以本公开权利要求所界定的范围为准。

Claims (24)

  1. 一种多相开关变换器，包括：
    多个并联耦接的开关电路，其中每个开关电路均具有耦接至输入电压的输入端和耦接至负载以提供输出电压的输出端；以及
    连接为菊花链架构的多个控制电路，分别耦接至所述多个开关电路，其中，每个控制电路均具有第一端、第二端与第三端，其中第一端耦接至前一控制电路的第二端以接收预备态输入信号，第二端耦接至后一控制电路的第一端以提供预备态输出信号，第三端耦接至通信总线以接收时钟信号，
    其中，每个控制电路被配置为在接收到所述预备态输入信号时工作于预备状态，并在所述预备状态接收到所述时钟信号时产生预备态输出信号以及控制对应开关电路的开关控制信号。
  2. 根据权利要求1所述的多相开关变换器，其中，所述多个控制电路中的第一个控制电路的第一端以及所述多个控制电路中的最后一个控制电路的第二端耦接至环回连线上，以将所述多个控制电路构成一个循环链。
  3. 根据权利要求1所述的多相开关变换器，其中，所述开关控制信号具有高电平状态、低电平状态以及中间电平状态，对应的开关电路能够响应于所述开关控制信号的上述三种状态执行包括导通上管、导通下管以及处于高阻状态的动作。
  4. 根据权利要求1所述的多相开关变换器，其中，所述预备态输入信号包括接通预备态输入信号和续流预备态输入信号。
  5. 根据权利要求1所述的多相开关变换器，其中，所述预备态输出信号包括接通预备态输出信号和续流预备态输出信号。
  6. 根据权利要求1所述的多相开关变换器，其中，所述时钟信号包括接通时钟信号和续流时钟信号。
  7. 根据权利要求1所述的多相开关变换器，其中，每个控制电路包括：
    配置寄存器，用于配置对应的控制电路是否参与循环链、是否为第一个控制电路以及是否为最后一个控制电路。
  8. 根据权利要求1所述的多相开关变换器，其中，每个控制电路包括：
    复位控制模块，用于经所述通信总线向上位控制器传递状态反馈信号，所述上位控制器根据所述状态反馈信号判断循环链中是否仅有一个控制电路处于预备状态，
    其中，当所述循环链中没有或超过一个控制电路处于预备状态时，所述复位控制模块经所述通信总线接收来自所述上位控制器的复位信号，执行电路复位。
  9. 根据权利要求1所述的多相开关变换器，其中，每个控制电路包括：
    计数模块，用于在所述预备状态对所述时钟信号的脉冲进行计数，判断当前时刻所述循环链中的总相数，并将所述总相数经所述通信总线传递至上位控制器。
  10. 根据权利要求1所述的多相开关变换器，其中，每个控制电路包括：
    切相控制模块，用于在所述预备状态经所述通信总线接收来自上位控制器的切相指令，并基于所述切相指令判断是否使对应开关电路停止功率输出或开始功率输出。
  11. 根据权利要求1所述的多相开关变换器，其中，每个控制电路包括：
    检测和控制模块，被配置为将对应的开关电路的电流采样信号与电流阈值进行比较，并根据比较结果判断对应的开关电路中的电感电流是否反向，并将电感电流反向指示信号经所述通信总线传递至上位控制器。
  12. 根据权利要求11所述的多相开关变换器，其中，所述检测和控制模块还被配置为经所述通信总线接收来自所述上位控制器的阈值设置信号，并根据所述阈值设置信号设置所述电流阈值。
  13. 一种用于多相开关变换器的控制电路，与其余控制电路连接在 一起形成菊花链架构，所述多相开关变换器包括多个并联耦接的开关电路，所述控制电路包括：
    第一端，耦接至所述菊花链架构中前一控制电路的第二端以接收预备态输入信号；
    第二端，耦接至所述菊花链架构中后一控制电路的第一端以提供预备态输出信号；以及
    第三端，耦接至通信总线以接收时钟信号，
    其中，所述控制电路被配置为在接收到所述预备态输入信号时工作于预备状态，并在所述预备状态接收到所述时钟信号时产生预备态输出信号以及控制对应开关电路的开关控制信号。
  14. 根据权利要求13所述的控制电路，其中，所述控制电路被设置为所述菊花链架构中的第一个控制电路时，其第一端耦接至环回连线上，所述控制电路被设置为所述菊花链架构中的最后一个控制电路时，其第二端耦接至环回连线上，以将所述控制电路与其余多个控制电路构成一个循环链。
  15. 根据权利要求13所述的控制电路，其中，所述开关控制信号具有高电平状态、低电平状态以及中间电平状态，对应的开关电路能够响应于所述开关控制信号的上述三种状态执行包括导通上管、导通下管以及处于高阻状态的动作。
  16. 根据权利要求13所述的控制电路，其中，所述预备态输入信号包括接通预备态输入信号和续流预备态输入信号。
  17. 根据权利要求13所述的控制电路，其中，所述预备态输出信号包括接通预备态输出信号和续流预备态输出信号。
  18. 根据权利要求13所述的控制电路，其中，所述时钟信号包括接通时钟信号和续流时钟信号。
  19. 根据权利要求13所述的控制电路，包括：
    配置寄存器，用于配置对应的控制电路是否参与循环链、是否为第一个控制电路以及是否为最后一个控制电路。
  20. 根据权利要求13所述的控制电路，包括：
    复位控制模块，用于经所述通信总线向上位控制器传递状态反馈信号，所述上位控制器根据所述状态反馈信号判断循环链中是否仅有一个控制电路处于预备状态，
    其中，当所述循环链中没有或超过一个控制电路处于预备状态时，所述复位控制模块经所述通信总线接收来自所述上位控制器的复位信号，执行电路复位。
  21. 根据权利要求13所述的控制电路，包括：
    计数模块，用于在所述预备状态对所述时钟信号的脉冲进行计数，判断当前时刻所述循环链中的总相数，并将所述总相数经所述通信总线传递至上位控制器。
  22. 根据权利要求13所述的控制电路，包括：
    切相控制模块，用于在所述预备状态经所述通信总线接收来自上位控制器的切相指令，并基于所述切相指令判断是否使对应开关电路停止功率输出或开始功率输出。
  23. 根据权利要求13所述的控制电路，包括：
    检测和控制模块，被配置为将对应的开关电路的电流采样信号与电流阈值进行比较，并根据比较结果判断对应的开关电路中的电感电流是否反向，并将电感电流反向指示信号经所述通信总线传递至上位控制器。
  24. 根据权利要求23所述的控制电路，其中，所述检测和控制模块还被配置为经所述通信总线接收来自所述上位控制器的阈值设置信号，并根据所述阈值设置信号设置所述电流阈值。
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