WO2023071309A1 - 数据传输的方法、装置、设备、系统及可读存储介质 - Google Patents

数据传输的方法、装置、设备、系统及可读存储介质 Download PDF

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Publication number
WO2023071309A1
WO2023071309A1 PCT/CN2022/106516 CN2022106516W WO2023071309A1 WO 2023071309 A1 WO2023071309 A1 WO 2023071309A1 CN 2022106516 W CN2022106516 W CN 2022106516W WO 2023071309 A1 WO2023071309 A1 WO 2023071309A1
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data
path
codewords
channels
channel
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PCT/CN2022/106516
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English (en)
French (fr)
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何向
王心远
任浩
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华为技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0803—Configuration setting
    • H04L41/0823—Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability
    • H04L41/083—Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability for increasing network speed

Definitions

  • the embodiments of the present application relate to the field of communication technologies, and in particular, to a data transmission method, device, device, system, and readable storage medium.
  • the present application provides a data transmission method, device, device, system and readable storage medium, which are used to increase the data transmission rate.
  • a data transmission method includes: a first module acquires at least one path of first data encoded by a first forward error correction code (FEC); performs conversion processing on the at least one path of first data, and obtains At least one path of second data, the sum of the rates of the at least one path of second data is not less than the sum of the rates of the at least one path of first data; and transmitting the obtained at least one path of second data.
  • FEC forward error correction code
  • the method converts at least one path of first data to obtain at least one path of second data whose sum of rates is not less than the sum of rates of at least one path of first data, thereby enabling data transmission at a higher rate.
  • the first module converts at least one path of first data to obtain at least one path of second data, including: the first module aligns at least one path of first data, and obtains multiple second data according to the alignment result.
  • a codeword decoding a plurality of first codewords, and obtaining at least one path of second data according to decoding results.
  • obtaining at least one channel of second data according to the decoding result includes: encoding the decoding result according to the second FEC pattern to obtain multiple second codewords; obtaining at least one channel of second data according to the multiple second codewords All the way to the second data.
  • the first module may use the same or different second FEC patterns to encode the decoding results, so as to flexibly adapt to transmission scenarios and transmission requirements.
  • obtaining at least one path of second data according to multiple second codewords includes: performing interleaving on multiple second codewords, and obtaining at least one path of second data according to an interleaving result.
  • the first data includes an alignment mark AM, and AM is used to align at least one path of the first data;
  • the decoding result is encoded according to the second FEC pattern to obtain a plurality of second codewords, including : Delete AM in the decoding result, encode the decoding result after deleting AM according to the second FEC code pattern, and obtain multiple second codewords.
  • the decoding result after AM deletion is encoded according to the second FEC code pattern to obtain a plurality of second codewords, including: combining the decoding results after AM deletion into one channel in a sequential manner
  • one path of third data is encoded to obtain a plurality of second codewords; or, the decoding result after AM is deleted is converted into at least two paths of third data, and at least two paths of third data are encoded to obtain multiple second codewords. a second codeword.
  • converting the decoding result after deleting AM into at least two channels of third data includes: merging the decoding result after deleting AM into one channel of fourth data, and converting one channel of fourth data into at least two channels road third data.
  • encoding one path of third data to obtain multiple second codewords includes: performing overall encoding on one path of third data according to the second FEC code pattern to obtain multiple second codewords; Alternatively, one path of third data is converted into at least two paths of fifth data, and at least two paths of fifth data are respectively encoded according to the second FEC pattern to obtain a plurality of second codewords, wherein the rate of the fifth data is lower than that of the first Three data rates.
  • the method can encode the third data in different ways to obtain a plurality of second codewords, so that the method is more flexible in transmission scenarios and transmission requirements.
  • the number of channels of the third data is multi-channel, the number of channels of the third data and the second FEC pattern used for encoding the third data can be flexibly set to be applicable to different transmission scenarios and transmission need.
  • encoding at least two channels of third data to obtain multiple second codewords includes: performing overall encoding on at least two channels of third data according to the second FEC code pattern to obtain multiple second codewords. Two codewords; or encode at least two channels of third data according to the second FEC pattern to obtain multiple second codewords.
  • At least two channels of third data are respectively encoded according to the second FEC code pattern to obtain a plurality of second codewords, including: respectively encoding at least two channels of third data according to the second FEC code pattern Perform overall encoding to obtain multiple second codewords; or, convert at least two channels of third data into at least two channels of sixth data respectively, and encode at least two channels of sixth data according to the second FEC pattern to obtain multiple codewords second codewords, wherein the rate of the sixth data is less than the rate of the third data.
  • obtaining at least one path of second data according to the decoding result includes: marking an error code block among the plurality of code blocks included in the decoding result, and obtaining at least one path of second data according to the marked decoding result. Since the first module can mark the error code block in the decoding result, when the subsequent receiving side module receives the second data obtained based on the decoding result, it can effectively correct the data based on the marked error code block, so as to improve the error correction performance , to improve the quality of data transmission.
  • the first module converts at least one path of first data to obtain at least one path of second data, including: the first module aligns at least one path of first data, and obtains multiple second data according to the alignment result.
  • a codeword; at least one path of second data is obtained according to multiple first codewords.
  • obtaining at least one path of second data according to a plurality of first codewords includes: combining the plurality of first codewords, and obtaining at least one path of second data according to a combination result.
  • combining multiple first codewords, and obtaining at least one path of second data according to the combination result includes: combining multiple first codewords into one path of second data in a manner of sequential transmission; Alternatively, multiple first codewords are combined into at least two channels of second data.
  • At least one channel of first data is data obtained through interleaving
  • obtaining multiple first codewords according to the alignment result includes: performing deinterleaving on the alignment result, and obtaining multiple first codewords according to the deinterleaving result Codeword.
  • the first module converts at least one channel of first data to obtain at least one channel of second data, including: the first module encodes at least one channel of first data according to the second FEC pattern to obtain a plurality of third codewords; the first module obtains at least one channel of second data according to the plurality of third codewords. Since the first module can re-encode the obtained first data encoded with the first FEC code pattern through the second FEC code pattern, the second data has a higher coding gain, and when it is transmitted in a channel prone to bit errors , can effectively correct the error data, thereby improving the quality of data transmission.
  • obtaining at least one path of second data according to multiple third codewords includes: performing interleaving on multiple third codewords, and obtaining at least one path of second data according to an interleaving result.
  • the first module encodes at least one path of first data according to the second FEC pattern to obtain multiple third codewords, including: combining at least one path of first data into One path of seventh data, encoding one path of seventh data to obtain multiple third codewords; or converting at least one path of first data into at least two paths of seventh data, encoding at least two paths of seventh data to obtain multiple a third codeword.
  • the method can encode the seventh data in different ways to obtain multiple third codewords, so that the method is more flexible in transmission scenarios and transmission requirements.
  • the number of channels of the seventh data is multi-channel
  • the number of channels of the seventh data and the second FEC pattern used for encoding the seventh data can be flexibly set to be suitable for different transmission scenarios and transmission need.
  • converting at least one path of first data into at least two paths of seventh data includes: merging at least one path of first data into one path of eighth data, converting one path of eighth data into at least two paths of seventh data Seven data.
  • encoding one path of seventh data to obtain multiple third codewords includes: performing overall encoding on one path of seventh data according to the second FEC code pattern to obtain multiple third codewords; Alternatively, one path of seventh data is converted into at least two paths of ninth data, and at least two paths of ninth data are respectively encoded according to the second FEC pattern to obtain a plurality of third codewords, wherein the rate of the ninth data is lower than that of the first Seven data rates.
  • encoding at least two channels of seventh data to obtain multiple third codewords includes: performing overall encoding on at least two channels of seventh data according to the second FEC code pattern to obtain multiple third codewords. Three codewords; or encode at least two channels of seventh data according to the second FEC pattern to obtain multiple third codewords.
  • At least two channels of seventh data are respectively encoded according to the second FEC code pattern to obtain a plurality of third codewords, including: respectively encoding at least two channels of seventh data according to the second FEC code pattern Perform overall encoding to obtain a plurality of third codewords; or convert at least two paths of seventh data into at least two paths of tenth data respectively, and encode at least two paths of tenth data according to the second FEC pattern to obtain multiple third codewords, wherein the rate of the tenth data is less than the rate of the seventh data.
  • the transmission of at least one path of second data by the first module includes: inserting synchronization data into at least one path of second data by the first module, and transmitting the data after the synchronization data is inserted.
  • the first module inserts the synchronous data into at least one path of second data, including: determining the AM corresponding to each path of second data in at least one path of second data; inserting the AM corresponding to each path of second data Each channel of second data is inserted as synchronous data.
  • the AM corresponding to each path of second data is obtained by adjusting the AM included in the corresponding first data; or, the AM corresponding to each path of second data is the AM included in the corresponding first data.
  • the entire content; or, the AM corresponding to each channel of second data is part of the content in the AM included in the corresponding first data.
  • a data transmission method includes: a third module acquires at least one path of second data, the at least one path of second data is obtained by converting at least one path of first data, and at least one path of first data
  • the sum of the rates of the two data is not less than the sum of the rates of at least one channel of the first data, the first data is data encoded by the first forward error correction code (FEC) pattern
  • the third module converts at least one channel of the second data, At least one path of first data is obtained.
  • FEC forward error correction code
  • a device for data transmission is provided, the device is applied to the first module, and the device includes:
  • An acquisition unit configured to acquire at least one path of first data, where the first data is data encoded by a first forward error correction code (FEC);
  • FEC forward error correction code
  • a converting unit configured to convert at least one channel of first data to obtain at least one channel of second data, and the sum of the rates of at least one channel of second data is not less than the sum of the rates of at least one channel of first data;
  • a transmission unit configured to transmit at least one channel of second data.
  • the conversion unit is configured to align at least one path of first data, obtain multiple first codewords according to the alignment result; decode multiple first codewords, and obtain at least one path according to the decoding result second data.
  • the conversion unit is configured to encode the decoding result according to the second FEC pattern to obtain multiple second codewords; and obtain at least one channel of second data according to the multiple second codewords.
  • the conversion unit is configured to perform interleaving on a plurality of second codewords, and obtain at least one channel of second data according to an interleaving result.
  • the first data includes an alignment mark AM, and AM is used to align at least one path of first data; the conversion unit is used to delete AM in the decoding result, and delete AM according to the second FEC pattern The subsequent decoding results are encoded to obtain multiple second codewords.
  • the conversion unit is configured to combine the decoding results after the AM is deleted into one path of third data in a sequential manner, and encode one path of third data to obtain multiple second codewords; or , converting the decoding result after AM is deleted into at least two channels of third data, and encoding the at least two channels of third data to obtain multiple second codewords.
  • the conversion unit is configured to combine the decoding results after AM deletion into one path of fourth data, and convert one path of fourth data into at least two paths of third data.
  • the conversion unit is configured to encode one channel of third data as a whole according to the second FEC code pattern to obtain multiple second codewords; or, convert one channel of third data into at least two channels of the third data For five data, at least two channels of fifth data are respectively encoded according to the second FEC code pattern to obtain multiple second codewords, wherein the rate of the fifth data is lower than the rate of the third data.
  • the conversion unit is configured to perform integral encoding on at least two channels of third data according to the second FEC code pattern to obtain multiple second codewords; or to encode at least two channels of third data according to the second FEC code pattern The third data are respectively encoded to obtain multiple second codewords.
  • the conversion unit is configured to respectively perform integral encoding on at least two channels of third data according to the second FEC pattern to obtain a plurality of second codewords; or, separately encode at least two channels of third data Converting to at least two channels of sixth data, respectively encoding the at least two channels of sixth data according to the second FEC pattern to obtain a plurality of second codewords, wherein the rate of the sixth data is lower than the rate of the third data.
  • the converting unit is configured to mark an erroneous code block among the plurality of code blocks included in the decoding result, and obtain at least one channel of second data according to the marked decoding result.
  • the conversion unit is configured to align at least one channel of first data, obtain multiple first codewords according to the alignment result; obtain at least one channel of second data according to the multiple first codewords.
  • the conversion unit is configured to combine a plurality of first codewords, and obtain at least one channel of second data according to a combination result.
  • the conversion unit is configured to combine multiple first codewords into one path of second data in a manner of sequential transmission; or, combine multiple first codewords into at least two paths of second data .
  • the converting unit is configured to perform deinterleaving on the alignment result, and obtain multiple first codewords according to the deinterleaving result.
  • the conversion unit is configured to encode at least one path of first data according to the second FEC pattern to obtain multiple third codewords; obtain at least one path of second data according to the multiple third codewords .
  • the converting unit is configured to perform interleaving on a plurality of third codewords, and obtain at least one channel of second data according to an interleaving result.
  • the conversion unit is configured to combine at least one path of first data into one path of seventh data in a sequential manner, and encode one path of seventh data to obtain multiple third codewords; or, converting at least one path of first data into at least two paths of seventh data, and encoding at least two paths of seventh data to obtain multiple third codewords.
  • the converting unit is configured to combine at least one path of first data into one path of eighth data, and convert one path of eighth data into at least two paths of seventh data.
  • the conversion unit is configured to encode one path of seventh data as a whole according to the second FEC code pattern to obtain multiple third codewords; or, convert one path of seventh data into at least two paths of the first For nine data, encode at least two channels of ninth data respectively according to the second FEC code pattern to obtain a plurality of third codewords, wherein the rate of the ninth data is lower than the rate of the seventh data.
  • the conversion unit is configured to perform integral encoding on at least two channels of seventh data according to the second FEC code pattern to obtain multiple third codewords; or to encode at least two channels of seventh data according to the second FEC code pattern
  • the seventh data is coded respectively to obtain a plurality of third codewords.
  • the conversion unit is configured to respectively perform overall encoding on at least two channels of seventh data according to the second FEC code pattern to obtain multiple third codewords; or, separately encode at least two channels of seventh data Converting to at least two channels of tenth data, respectively encoding at least two channels of tenth data according to the second FEC code pattern to obtain a plurality of third codewords, wherein the rate of the tenth data is lower than the rate of the seventh data.
  • the transmission unit is configured to insert the synchronization data into at least one path of second data, and transmit the data after the synchronization data is inserted.
  • the transmission unit is configured to determine an AM corresponding to each path of second data in at least one path of second data; and insert the AM corresponding to each path of second data as synchronization data into each path of second data.
  • the AM corresponding to each path of second data is obtained by adjusting the AM included in the corresponding first data; or, the AM corresponding to each path of second data is the AM included in the corresponding first data.
  • the entire content; or, the AM corresponding to each channel of second data is part of the content in the AM included in the corresponding first data.
  • a device for data transmission is provided, the device is applied to the third module, and the device includes:
  • An acquisition unit configured to acquire at least one channel of second data, at least one channel of second data is data obtained by converting at least one channel of first data, and the sum of the rates of at least one channel of second data is not less than the sum of the rates of at least one channel of first data
  • the first data is data encoded by a first forward error correction code (FEC) pattern
  • the converting unit is configured to convert at least one channel of second data to obtain at least one channel of first data.
  • a device for data transmission includes: a processor, the processor is coupled to a memory, at least one program instruction or code is stored in the memory, at least one program instruction or code is loaded and executed by the processor, A method for enabling a device to implement data transmission according to any one of the first aspect or the second aspect.
  • a data transmission system in the sixth aspect, includes: a first data transmission device, configured to perform the first aspect or the method described in any one of the first aspects, and a second data transmission device, using In performing the second aspect or the method described in any one of the second aspect.
  • a computer-readable storage medium is provided, and at least one program instruction or code is stored in the computer-readable storage medium, and when the program instruction or code is loaded and executed by a processor, the computer can realize the following aspects of the first aspect or The method of data transmission according to any one of the second aspects.
  • the device includes: a communication interface, a memory, and a processor.
  • the memory and the processor communicate with each other through an internal connection path, the memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the communication interface to receive data and control the communication interface to send data, and when the When the processor executes the instruction stored in the memory, the processor executes the method in the first aspect or any possible implementation manner of the first aspect, or executes the second aspect or any possible implementation manner of the second aspect methods in methods.
  • processors there are one or more processors, and one or more memories.
  • the memory may be integrated with the processor, or the memory may be separated from the processor.
  • the memory can be a non-transitory (non-transitory) memory, such as a read-only memory (read only memory, ROM), which can be integrated with the processor on the same chip, or can be respectively arranged in different On the chip, the application does not limit the type of the memory and the arrangement of the memory and the processor.
  • a non-transitory memory such as a read-only memory (read only memory, ROM)
  • ROM read only memory
  • a computer program (product) is provided, and the computer program (product) includes: computer program code, when the computer program code is run by a computer, it causes the computer to execute the methods in the above aspects.
  • a chip including a processor, configured to call from a memory and execute instructions stored in the memory, so that a device equipped with the chip executes the methods in the above aspects.
  • Another chip including: an input interface, an output interface, a processor, and a memory, the input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the processor is used to execute the codes in the memory, and when the codes are executed, the processor is configured to perform the methods in the above aspects.
  • a device including the chip described in any one of the solutions above.
  • a device including the first module described in any one of the above schemes, and/or the third module described in any one of the above schemes.
  • FIG. 1 is a schematic diagram of an implementation scenario of a data transmission method provided in an embodiment of the present application
  • FIG. 2 is a flow chart of a data transmission method provided by an embodiment of the present application.
  • Fig. 3 is a schematic diagram of a kind of first data and second data provided by the embodiment of the present application.
  • Fig. 4 is a schematic diagram of another first data and second data provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of a process for obtaining at least one path of second data provided by an embodiment of the present application
  • FIG. 6 is a schematic diagram of another process for obtaining at least one channel of second data provided by the embodiment of the present application.
  • Fig. 7 is a schematic diagram of a process of marking an error code block provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of another process of marking an error code block provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another process of marking an error code block provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of another process of marking an error code block provided by an embodiment of the present application.
  • Fig. 11 is a schematic diagram of a process of merging into third data provided by the embodiment of the present application.
  • Fig. 12 is a schematic diagram of another first data and second data provided by the embodiment of the present application.
  • Fig. 13 is a schematic diagram of another first data and second data provided by the embodiment of the present application.
  • Fig. 14 is a schematic diagram of an implementation environment of an application scenario provided by an embodiment of the present application.
  • Fig. 15 is a schematic diagram of the implementation environment of another application scenario provided by the embodiment of the present application.
  • Fig. 16 is a schematic diagram of an implementation environment of another application scenario provided by the embodiment of the present application.
  • Fig. 17 is a schematic diagram of an implementation environment of another application scenario provided by the embodiment of the present application.
  • FIG. 18 is a flow chart of another data transmission method provided by the embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of a data transmission device provided by an embodiment of the present application.
  • Fig. 20 is a schematic structural diagram of another data transmission device provided by an embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of another data transmission device provided by an embodiment of the present application.
  • the embodiment of the present application provides a method of data transmission, the method converts at least one channel of first data to obtain at least one channel of second data, and the sum of the rates of the at least one channel of second data is not less than at least one channel The sum of the rates of the first data, so that data transmission can be performed at a higher rate.
  • the method provided in the embodiment of the present application is applicable to end-to-end forward error correction (forward error correction, FEC) architecture, segment-by-segment architecture and concatenated (concatenated) architecture. ) any FEC architecture in the FEC architecture.
  • the method of the embodiment of the present application can reuse the current module to save the optical fiber, module and device expenses.
  • Fig. 1 shows an implementation scenario of a data transmission method provided by an embodiment of the present application.
  • the implementation scenario includes a plurality of modules, each module can perform information interaction to realize data transmission.
  • data can be transmitted between the first module 101 and the second module 102 and between the first module 101 and the third module 103 .
  • the implementation scenario shown in FIG. 1 may include N modules, where N is a positive integer greater than or equal to 2.
  • N is a positive integer greater than or equal to 2.
  • each module can be located in the same chip or in different chips.
  • FIG. 2 the data transmission method provided by the embodiment of the present application is shown in FIG. 2 , including but not limited to S201 to S203.
  • the first module acquires at least one channel of first data, where the first data is encoded using a first FEC pattern.
  • the embodiment of the present application does not limit the rate of the first data.
  • the rate of the first data is 50 gigabit per second (Gb/s), 100Gb/s, 200Gb/s, 400Gb /s, 800Gb/s, 1.6 terabit per second (Tb/s), 3.2Tb/s, 6.4Tb/s or any of other non-standard rates.
  • Gb/s gigabit per second
  • Tb/s 1.6 terabit per second
  • Tb/s 1.6 terabit per second
  • 3.2Tb/s 3.2Tb/s
  • 6.4Tb/s any of other non-standard rates.
  • rates of multiple channels of first data may be the same or different.
  • the first module acquires four channels of first data, and the rates of the four channels of first data are all 200GE.
  • the first module acquires four channels of first data, and the rates of the four channels of first data are 100GE, 100GE, 200GE and 400GE respectively.
  • the first FEC code type is a Reed-Solomon (Reed-Solomon, RS) code, a Bose-Johry-Hockewenheim (Bose- Chaudhuri-Hocquenghem, BCH) code, Farr (fire) code, turbo (turbo) code, turbo product code (turbo product code, TPC), ladder (staircase) code and low-density parity check (low-density parity-check) , LDPC) codes in any one.
  • Reed-Solomon RS
  • Bose-Johry-Hockewenheim Bose- Chaudhuri-Hocquenghem, BCH
  • BCH Bose-Johry-Hockewenheim
  • the embodiment of the present application does not limit the way the first module acquires at least one piece of first data.
  • the first module and the second module can perform data transmission, and the first module receives at least one piece of first data sent by the second module.
  • the first module is located on the first chip
  • the second module is located on the second chip
  • the first module receives at least one path of first data sent by the second module, including but not limited to the first module receiving the second module through the attachment unit interface (attachment The first data sent by the channel of unit interface, AUI).
  • the first data may also undergo other processing.
  • the embodiment of the present application does not limit the processing manner of the first data other than the first FEC pattern encoding.
  • the first data is encoded using a first FEC pattern and distributed through a physical medium access sublayer (physical medium attachment sublayer, PMA), or the first data is encoded using a first FEC pattern and passed Interleaved processing and data distributed by PMA, etc.
  • PMA physical medium access sublayer
  • the first module converts at least one path of first data to obtain at least one path of second data, and the sum of rates of at least one path of second data is not less than the sum of rates of at least one path of first data.
  • the embodiment of the present application does not limit the rate of the second data.
  • the sum of the rates of the converted second data is not less than the sum of the rates of the first data before conversion, that is, the rate of the first data before conversion
  • the sum of the rates of all the first data is not greater than the sum of the converted rates of all the second data.
  • the rate of the second data is any one of 400Gb/s, 800Gb/s, 1.6Tb/s, 3.2Tb/s, 6.4Tb/s or other non-standard rates.
  • rates of multiple channels of second data may be the same or different.
  • the first module converts at least one piece of first data to obtain at least one piece of second data including but not limited to the following three situations.
  • the first module converts at least one channel of first data to obtain at least one channel of second data including: the first module aligns at least one channel of first data, and obtains according to the alignment result A plurality of first codewords; decoding the plurality of first codewords, and obtaining at least one channel of second data according to the decoding results.
  • the first module aligns at least one path of first data, including but not limited to respectively aligning at least one path of first data.
  • the first module converts at least one path of first data into at least one path of first sub-data, and aligns at least one path of first sub-data belonging to the same path of first data.
  • the first data includes an alignment marker (alignment marker, AM), and the AM is used to align at least one path of the first data.
  • aligning at least one path of first data includes but not limited to AM locking and deskewing.
  • AM locking is used to find the codeword boundary, that is, to align at least one path of the first data. After finding the codeword boundary, it can follow the standard, such as the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronics Engineers, IEEE)
  • Various versions or future versions of 802.3 perform de-skew in a defined manner, and then obtain multiple first codewords.
  • the first module aligning at least one path of first data includes: the first module converts at least one path of first data into at least one path of first sub-data, and performs AM locking and debiasing on at least one path of first sub-data incline.
  • the first module converts at least one path of first data into at least one path of first sub-data, and performs AM locking and debiasing on at least one path of first sub-data incline.
  • AM locking/deskewing steps shown in FIG. 5 and FIG. 6 Exemplarily, for aligning at least one channel of first data, reference may be made to the AM locking/deskewing steps shown in FIG. 5 and FIG. 6 .
  • the alignment result of aligning at least one path of first data includes at least one first codeword sequence, and one first codeword sequence corresponds to one path of first data.
  • multiple first codewords are obtained according to the alignment result, including but not limited to each first codeword in at least one first codeword sequence sequence, and obtain a plurality of first codewords according to code length intervals.
  • multiple first codewords are obtained according to the alignment result, including but not limited to de-interleaving the alignment result, and according to the de-interleaving result A plurality of first codewords are obtained.
  • deinterleaving is performed on each first codeword sequence in at least one first codeword sequence, and multiple first codewords are obtained according to the deinterleaving result.
  • the interleaving manner of at least one channel of first data includes but is not limited to at least one of codeword interleaving or interlane interleaving.
  • corresponding deinterleaving is performed according to the interleaving mode of at least one channel of first data.
  • the step of obtaining a plurality of first codewords may refer to FIG. 5 and FIG. 6 to illustrate the step of obtaining an FEC1 (first FEC code pattern) codeword.
  • the first module After acquiring the multiple first codewords, the first module decodes the multiple first codewords to obtain a decoding result. For example, the FEC1 decoding steps shown in FIG. 5 and FIG. 6 .
  • decoding the multiple first codewords to obtain a decoding result includes but not limited to decoding the multiple first codewords, discarding check bits of the multiple first codewords, and obtaining the decoding result. That is to say, the decoding result may include the information bits of the multiple first codewords and not include the check bits of the multiple first codewords.
  • the first module when the first module decodes the multiple first codewords, it decodes the multiple first codewords according to the first FEC pattern.
  • At least one channel of second data is obtained according to the decoding result, including but not limited to S1-1 and S1-2.
  • the embodiment of the present application does not limit the second FEC code type.
  • the second FEC code type is any one of RS code, BCH code, Farr code, turbo code, turbo product code, ladder code and LDPC code .
  • the decoding results include decoding results obtained based on each channel of first data.
  • the second FEC code pattern performs encoding, which is not limited in this embodiment of the present application.
  • the decoding result is encoded according to the second FEC code pattern to obtain a plurality of second codewords, including: deleting the AM in the decoding result, according to the second FEC code
  • the type encodes the decoding result after AM is deleted to obtain a plurality of second codewords.
  • the embodiment of the present application does not limit the manner of deleting the AM in the decoding result. For example, when the codeword boundary is obtained through AM locking, the position of the AM is obtained, so that the AM can be deleted according to the position of the AM.
  • obtaining at least one path of second data according to the decoding result includes: marking an erroneous code block among the plurality of code blocks included in the decoding result, and obtaining at least one path of second data according to the marked decoding result.
  • reverse coding is performed on multiple code blocks included in the decoding result, and the error code blocks in the multiple code blocks obtained by the reverse coding are marked, and according to the multiple code blocks marked with error code blocks The block obtains at least one path of second data.
  • the decoding result includes n 257-bit (bit) code block streams, and the multiple 257-bit (bit) code block streams are reverse-coded to obtain n 66-bit code block streams, marked Obtaining at least one path of second data according to the n 66-bit code block streams marked with error code blocks for the error code blocks in the n 66-bit code block streams.
  • reverse coding is performed on multiple code blocks included in the decoding result, and the error code blocks in the multiple code blocks obtained by the reverse coding are marked, and the multiple code blocks marked with error code blocks The code blocks are transcoded, and at least one path of second data is obtained according to the multiple code blocks obtained through transcoding.
  • the decoding result includes n 257-bit (bit) code block streams, and the n 257-bit (bit) code block streams are reverse-coded to obtain n 66-bit code block streams, marked Error code blocks in n 66-bit code block streams, transcode the n 66-bit code block streams marked with error code blocks to obtain n 257-bit code block streams, and obtain at least one second code block stream according to the n 257-bit code block streams data.
  • the operation of marking the erroneous code block may be performed on the basis of the decoding result after AM is deleted. That is, after the AM in the decoding result is deleted, the erroneous code block in the decoding result after the AM is deleted is marked, and at least one channel of second data is obtained according to the decoding result after the AM is deleted and the erroneous code block is marked.
  • marking the erroneous code blocks it can deal with the bit errors introduced by AUI transmission and system noise.
  • the decoding result after AM is deleted is coded according to the second FEC pattern to obtain multiple second codewords, including but not limited to the following two manners.
  • the first method of obtaining multiple second codewords is to combine the decoded results after AM deletion into one path of third data in a sequential manner, and encode one path of third data to obtain multiple second codewords.
  • the decoding results after AM deletion are combined into one third data in a sequential sending manner, the decoding results after AM deletion based on each channel of first data included in the third data may appear periodically.
  • the decoding result after AM is deleted includes n 257-bit code block streams, and the n 257-bit code block streams are sent in sequence, so that the data belonging to the n 257-bit code block streams in the combined third data obtained periodically appear .
  • the embodiment of the present application does not limit the granularity of sequential sending, including but not limited to 5440-bit, 5140-bit, 257-bit, 66-bit, 10-bit, 2-bit or 1-bit.
  • the decoding results after the AM deletion corresponding to each channel of the first data are sent sequentially and combined into one channel of third data .
  • the decoding result after AM is deleted includes four code block streams, namely code block stream A, code block stream B, code block stream C and code block stream D, wherein code block stream A includes code block A.1, A.2, A.3, A.4, A.5, A.6, A.7, etc., code block stream B includes code blocks B.1, B.2, B.3, B.4, B .5, B.6, B.7, etc., the code block stream C includes code blocks C.1, C.2, C.3, C.4, C.5, C.6, C.7, etc.,
  • the code block stream D comprises code blocks D.1, D.2, D.3, D.4, D.5, D.6, D.7 and so on.
  • the code blocks of the respective code block streams included in the third data are as shown in (a) of FIG. 11 As shown, the order of the code blocks included in the third data is A.1, B.1, C.1, D.1, A.2, B.2, C.2, D.2, A.3, etc. .
  • the decoding results after AM deletion are combined into one third data in a sequential manner, including but not limited to: the decoding results after AM deletion are combined into one third data at a reference rate in sequential transmission. data.
  • the decoding result after AM deletion and the first reference data are combined into one channel of third data of the reference rate.
  • the decoding result after AM deletion and the first reference data of 400GE are combined into a third data of 800GE.
  • the first reference data can be idle
  • the (idle) data can be set based on the application scenario, and this embodiment of the present application does not limit the content of the first reference data.
  • the reference rate may be set according to experience or actual requirements, which is not limited in this embodiment of the present application.
  • the embodiment of the present application does not limit the manner of combining the decoding result after AM deletion and the first reference data into one channel of third data at a reference rate. For example, the decoding result after AM deletion and the first reference data are combined into the third data of one reference rate in a sequential manner, or the decoding result after AM deletion is combined, and the combined data and the first reference data The third data of one reference rate is merged into one channel in the manner of sequential transmission.
  • the decoding results after the AM deletion are combined into a channel of third data at a reference rate in a sequential manner
  • the method includes: sequentially sending the decoding results and filling data blocks corresponding to each channel of first data after AM deletion, and merging them into one channel of third data.
  • the padding data block can be meaningless data, such as pseudorandom binary sequence (pseudo random binary sequence) -random binary sequence, PRBS) data can also be a meaningful overhead.
  • the embodiment of the present application does not limit the content of the filled data block, which can be flexibly set based on the application scenario.
  • the code blocks of each code block stream included in the third data are as shown in Figure 11
  • the order of the code blocks included in the third data is A.1, B.1, C.1, D.1, A.2, filling data blocks, B.2, C.2, D. 2, A.3 and so on.
  • the decoding results after AM deletion are combined into one third data in a sequential manner, including but not limited to interleaving the decoding results after AM deletion, and the interleaved decoding results after AM deletion are combined with The method of sequential sending is combined into one third data.
  • This application does not limit the interleaving mode of the decoding result after AM is deleted.
  • the manner of combining the decoding results after AM deletion into one path of third data may refer to the steps of data interleaving and distribution shown in FIG. 5 .
  • encoding one path of third data to obtain multiple second codewords includes but not limited to: performing overall encoding on one path of third data according to the second FEC code pattern to obtain multiple second codewords; or, converting one path of third data into at least two paths of fifth data, and encoding at least two paths of fifth data respectively according to the second FEC code pattern to obtain a plurality of second codewords, wherein the rate of the fifth data is lower than that of the third data s speed.
  • the third data is one channel of 800GE data, and the third data is encoded as a whole according to the second FEC code pattern to obtain multiple second codewords; or, the third data is converted into two channels of 400GE fifth data , respectively encode the two channels of fifth data according to the second FEC code pattern to obtain multiple second codewords.
  • the overall encoding is used to encode the data to be encoded as a data line.
  • the present application does not limit the method of converting one channel of third data into at least two channels of fifth data, for example, converting one channel of third data into at least two channels of fifth data in a manner of sequential transmission.
  • the step of encoding one channel of third data to obtain multiple second codewords refer to the FEC2 (second FEC code type) encoding and processing steps shown in FIG. 5 .
  • overall encoding refers to combining multiple channels of data into one channel of data for encoding, or in other words, overall encoding is used to encode data to be encoded as one channel of data. Therefore, encoding one piece of third data as a whole according to the second FEC code pattern refers to encoding one piece of third data as one piece of data.
  • the second way of obtaining multiple second codewords is to convert the decoding result after AM deletion into at least two channels of third data, and encode the at least two channels of third data to obtain multiple second codewords.
  • the rate of the third data may be a reference rate, and the number of channels of the third data and the reference rate may be set according to experience or actual requirements, which are not limited in this embodiment of the present application.
  • the decoding result after AM deletion is converted into at least two channels of third data in a manner of sequential transmission.
  • the decoding result after AM deletion is converted into at least two channels of third data, including but not limited to interleaving the decoding result after AM deletion, and converting the interleaved decoding result after AM deletion into at least two channels of third data Three data. This application does not limit the interleaving mode of the decoding result after AM is deleted.
  • the manner of converting the decoding result after AM deletion into at least two channels of third data may refer to the steps of data interleaving and distribution shown in FIG. 6 .
  • the decoding result after AM deletion and the second reference data are jointly converted into at least two paths of reference rates.
  • third data For example, the rates of the obtained four channels of first data are 400GE, 400GE, 400GE, and 200GE, and the reference rate is 800GE.
  • the decoding result after AM deletion and the second reference data of 200GE are converted into two channels of 800GE third data.
  • the acquired first data rate is 1.6TE
  • the reference rate is 800GE.
  • the decoding result after AM deletion and the second reference data of 1.6TE are jointly converted into four channels of 800GE third data.
  • the second reference data may be idle (idle) data, and may be set based on an application scenario. This embodiment of the present application does not limit the content of the second reference data.
  • the second reference data may include multiple stuffing data blocks, and this embodiment of the present application does not limit the stuffing data blocks included in each path of third data in at least two paths of third data.
  • the decoding result after AM is deleted is converted into at least two paths of third data.
  • the obtained four channels of first data all have a rate of 400GE, and the decoding result after AM is deleted is converted into two channels of third data with a rate of 800GE.
  • the acquired rate of one channel of first data is 1.6TE, and the decoding result after AM is deleted is converted into two channels of 800GE third data.
  • the third data of any path may only include part of the deleted AM of the first data
  • the decoding result after AM is deleted includes code block stream A, code block stream B, code block stream C, and code block stream D.
  • the code blocks of the respective code block streams included in the two channels of third data are shown in (c) of Figure 11
  • the order of the code blocks included in the third data all the way is A.1, C.1, A.2, C2, A.3, C.3, A.4, C.4, A.5, etc.
  • the order of the code blocks included in the other third data path is B.1, D.1, B.2, D.2, B.3, D.3, B.4, D.4, B.5 and so on.
  • each channel of third data may be formed by gathering two optional code block streams.
  • the code blocks of the respective code block streams included in the two channels of third data are shown in (d) of Figure 11 ), the order of the code blocks included in the third data is A.1, B.1, C.1, D.1, A.3, B.3, C.3, D.3, C5, A .5 and so on, the order of the code blocks included in the third data of the other way is A.2, B.2, C2, D.2, A.4, B.4, C.4, D.4, B.6 etc.
  • the methods shown in (a), (c) and (d) of Figure 11 above may also include sequentially sending the padding data block and the data to be combined in the process of merging to obtain the third data.
  • the padding data blocks are not necessarily sent periodically, and may also be sent at different intervals, for example, one padding data block is sent after a certain number of data intervals, or multiple padding data blocks are inserted after a certain number of data intervals.
  • converting the decoding result after AM deletion into at least two channels of third data includes: merging the decoding result after AM deletion into one channel of fourth data, and converting one channel of fourth data into at least two channels of third data.
  • the obtained four channels of first data are all 400GE data
  • the decoding results after AM deletion are combined into one channel of 1.6TE fourth data
  • the channel of 1.6TE fourth data is converted into two channels of 800GE third data .
  • encoding at least two channels of third data When encoding at least two channels of third data, an overall encoding or separate encoding may also be used.
  • encoding at least two channels of third data to obtain multiple second codewords includes: performing overall encoding on at least two channels of third data according to the second FEC code pattern to obtain multiple second codewords; or At least two channels of third data are respectively encoded according to the second FEC code pattern to obtain multiple second codewords.
  • FEC2 second FEC code type
  • At least two channels of third data are respectively encoded according to the second FEC pattern to obtain a plurality of second codewords, including: respectively performing integral encoding of at least two paths of third data according to the second FEC pattern , to obtain multiple second codewords; or, at least two channels of third data are respectively converted into at least two channels of sixth data, and at least two channels of sixth data are respectively encoded according to the second FEC pattern to obtain multiple second codewords A codeword, wherein the rate of the sixth data is less than the rate of the third data.
  • the process of encoding at least two channels of sixth data according to the second FEC code pattern is the same as the above-mentioned method for obtaining multiple second codewords.
  • One channel of third data is converted into at least two channels of fifth data, and the relevant processes of encoding at least two channels of fifth data according to the second FEC code pattern are the same, and will not be repeated here.
  • overall encoding refers to combining multiple channels of data into one channel of data for encoding, or in other words, overall encoding is used to encode data to be encoded as one channel of data. Therefore, encoding the at least two channels of third data as a whole according to the second FEC code pattern refers to encoding all the third data in the at least two channels of third data as one channel of data.
  • the method provided in the embodiment of the present application can encode the third data in different ways to obtain multiple second codewords, so that the method is more flexible in transmission scenarios and transmission requirements.
  • the number of channels of the third data is multi-channel
  • the number of channels of the third data and the second FEC pattern used for encoding the third data can be flexibly set to be applicable to different transmission scenarios and transmission need.
  • obtaining at least one path of second data according to multiple second codewords includes but not limited to performing interleaving on multiple second codewords, and obtaining at least one path of second data according to an interleaving result.
  • the embodiment of the present application does not limit the manner of performing interleaving on multiple second codewords, for example, performing at least one of codeword interleaving or interlane interleaving on multiple second codewords.
  • Case 2 the first module aligns at least one path of first data, obtains multiple first codewords according to the alignment result; obtains at least one path of second data according to the multiple first codewords.
  • the first module aligns at least one channel of first data, and the manner of obtaining multiple first codewords according to the alignment result is the same as the principle of the relevant process in the above-mentioned manner 1, and will not be repeated here.
  • obtaining at least one path of second data according to a plurality of first codewords includes: combining the plurality of first codewords, and obtaining at least one path of second data according to a combination result.
  • combining multiple first codewords to obtain at least one channel of second data according to the combining result includes but is not limited to the following two ways.
  • Combining mode one combining multiple first codewords into one channel of second data in a manner of sequentially sending.
  • first codewords Since multiple first codewords are combined into one channel of second data in a manner of sequential transmission, multiple first codewords obtained based on each channel of first data included in the second data may appear periodically.
  • the principle of combining a plurality of first codewords into one path of second data in a manner of sequentially sending is the same as the above-mentioned relevant process principle of merging the decoding results after AM is deleted into one path of third data in a manner of sequentially sending, here No longer.
  • Combining manner 2 combining multiple first codewords into at least two channels of second data.
  • the principle of combining multiple first codewords into at least two channels of second data is the same as the related process principle of converting the decoding result after AM deletion into at least two channels of third data, and will not be repeated here.
  • the second data may be interleaved data, and the embodiment of the present application does not limit the interleaving method.
  • the first module encodes at least one channel of first data according to the second FEC pattern to obtain multiple third codewords; the first module obtains at least one channel of second data according to the multiple third codewords.
  • the first module encodes at least one channel of first data according to the second FEC pattern to obtain multiple third codewords, including but not limited to the following two ways.
  • the first way of obtaining multiple third codewords is to combine at least one piece of first data into one piece of seventh data in a sequential manner, and encode one piece of seventh data to obtain multiple third codewords.
  • At least one path of first data is combined into one path of seventh data in a sequential manner, including but not limited to, the first module aligns at least one path of first data, and obtains multiple first codewords according to the alignment result , combining multiple first codewords into one path of seventh data in a manner of sequential transmission.
  • the embodiment of the present application does not limit the granularity of sequential sending, including but not limited to 5440-bit, 5140-bit, 257-bit, 66-bit, 10-bit, 2-bit or 1-bit.
  • the manner of obtaining multiple first codewords according to the alignment result is the same as the principle of the relevant process in the above-mentioned manner 1, and will not be repeated here.
  • At least one piece of first data is combined into one piece of seventh data in a manner of sequential transmission, including but not limited to: combining at least one piece of first data into one piece of seventh data of a reference rate in a manner of sequential transmission. For example, in response to the sum of the acquired rates of the first data being less than the reference rate, at least one path of first data and the third reference data are combined into one path of seventh data of the reference rate.
  • the embodiment of the present application does not limit the content of the third reference data, for example, the third reference data is determined based on the application scenario. It should be noted that the reference rate may be set according to experience or actual requirements, which is not limited in this embodiment of the present application. The embodiment of the present application also does not limit the manner of combining at least one piece of first data and the third reference data into one piece of seventh data at a reference rate.
  • At least one path of first data and third reference data is combined into one path of seventh data at a reference rate in a sequential manner, or at least one path of first data is combined, and the combined data and third reference data are sequentially sent The way of sending is combined into the seventh data of one reference rate.
  • encoding one path of seventh data to obtain multiple third codewords includes but not limited to: performing overall encoding on one path of seventh data according to the second FEC code pattern to obtain multiple third codewords; or, Converting one path of seventh data into at least two paths of ninth data, encoding at least two paths of ninth data respectively according to the second FEC code pattern to obtain a plurality of third codewords, wherein the rate of the ninth data is lower than that of the seventh data s speed.
  • the seventh data is one channel of 800GE data, and the seventh data is encoded as a whole according to the second FEC code pattern to obtain multiple third codewords; or, the seventh data is converted into two channels of 400GE ninth data , respectively encode the two channels of ninth data according to the second FEC code pattern to obtain a plurality of third codewords.
  • the overall coding is used to code the data to be coded as one piece of data. The present application does not limit the method of converting one channel of seventh data into at least two channels of ninth data, for example, converting one channel of first data into at least two channels of ninth data in a manner of sequential transmission.
  • the second way of obtaining multiple third codewords is to convert at least one path of first data into at least two paths of seventh data, and encode at least two paths of seventh data to obtain multiple third codewords.
  • the rate of the seventh data may be a reference rate, and the number of channels and the reference rate of the seventh data may be set according to experience or actual requirements, which are not limited in this embodiment of the present application.
  • at least one channel of first data is converted into at least two channels of seventh data in a manner of sequential transmission.
  • the sum of the rates of at least one path of first data is less than the sum of the rates of at least two paths of seventh data
  • at least one path of first data and the fourth reference data are jointly converted into at least two paths of the seventh path of reference rates.
  • Seven data the rates of the obtained four channels of first data are 400GE, 400GE, 400GE, and 200GE, and the reference rate is 800GE, and at least one channel of first data and the fourth reference data of 200GE are jointly converted into two channels of seventh data of 800GE.
  • the obtained rate of one channel of first data is 1.6TE
  • the reference rate is 800GE
  • at least one channel of first data and the fourth reference data of 1.6TE are jointly converted into four channels of seventh data of 800GE.
  • At least one path of first data is converted into at least two paths of seventh data.
  • the seventh data of any path may only include part of the data of the first data or Data including the first data of each channel.
  • converting at least one path of first data into at least two paths of seventh data includes: merging at least one path of first data into one path of eighth data, and converting one path of eighth data into at least two paths of seventh data.
  • the obtained four channels of first data are all 400GE data
  • the four channels of first data are combined into one channel of 1.6TE eighth data
  • the channel of 1.6TE eighth data is converted into two channels of 800GE seventh data .
  • encoding at least two channels of seventh data When encoding at least two channels of seventh data, an overall encoding or separate encoding may also be used.
  • encoding at least two channels of seventh data to obtain multiple third codewords includes: performing overall encoding on at least two channels of seventh data according to the second FEC code pattern to obtain multiple third codewords; or At least two channels of seventh data are respectively encoded according to the second FEC code pattern to obtain multiple third codewords.
  • At least two channels of seventh data are respectively encoded according to the second FEC pattern to obtain a plurality of third codewords, including: performing overall encoding of at least two paths of seventh data according to the second FEC pattern , to obtain multiple third codewords; or, at least two channels of seventh data are respectively converted into at least two channels of tenth data, and at least two channels of tenth data are respectively encoded according to the second FEC pattern to obtain multiple third codewords. codewords, wherein the rate of the tenth data is less than the rate of the seventh data.
  • the process of respectively encoding at least two channels of tenth data according to the second FEC code pattern is the same as the above-mentioned method for obtaining multiple third codewords.
  • One channel of seventh data is converted into at least two channels of ninth data, and the principle of the related process of encoding at least two channels of ninth data respectively according to the second FEC code pattern is the same, and will not be repeated here.
  • obtaining at least one path of second data according to a plurality of third codewords includes but not limited to performing interleaving on a plurality of third codewords, and obtaining at least one path of second data according to an interleaving result.
  • the embodiment of the present application does not limit the manner of performing interleaving on multiple third codewords, for example, performing at least one of codeword interleaving or interlane interleaving on multiple third codewords.
  • the method provided in the embodiment of the present application can encode the seventh data in different ways to obtain multiple third codewords, so that the method is more flexible in transmission scenarios and transmission requirements.
  • the number of channels of the seventh data is multi-channel
  • the number of channels of the seventh data and the second FEC pattern used for encoding the seventh data can be flexibly set to be suitable for different transmission scenarios and transmission need.
  • the first module transmits at least one channel of second data.
  • the transmission of at least one path of second data by the first module includes: inserting synchronization data into at least one path of second data by the first module, and transmitting the data after the synchronization data is inserted.
  • the synchronization data includes but not limited to at least one of AM, coherent digital signal processing (digital signal processing, DSP) frame header, training symbols or pilot symbols.
  • the first module inserts the synchronization data into at least one path of second data, including: determining the AM corresponding to each path of second data in at least one path of second data; using the AM corresponding to each path of second data as the synchronization data Insert the second data of each channel.
  • the AM corresponding to each channel of second data is obtained by adjusting the AM included in the corresponding first data; or, the AM corresponding to each channel of second data is the entire content of the AM included in the corresponding first data; or, The AM corresponding to each channel of second data is part of the content of the AM included in the corresponding first data.
  • adjusting the AM included in the corresponding first data includes but is not limited to adjusting AM content or length according to different granularities.
  • the AM included in any one channel of the first data among the multiple channels of first data may be used as the AM corresponding to any channel of the second data.
  • the AMs corresponding to the channels of the second data may be the same or different, for example, the AMs of the channels of the second data may be respectively determined according to actual needs.
  • the first module when it transmits at least one path of second data, it can also perform other processing, such as multiplexing (mux) and training sequence (training sequence, TS)/pilot symbol (pilot symbol) for at least one path of second data Insertion, frequency point adjustment, optical modulation and other processing, and at least one channel of second data after processing is transmitted.
  • multiplexing multiplexing
  • training sequence training sequence
  • TS training sequence
  • pilot symbol pilot symbol
  • the multiplexing granularity adopted by the first module to transmit data includes but is not limited to FEC codeword (codeword), 257-bit, 66 -bit, 10-bit or 1-bit, which is not limited in this embodiment of the present application.
  • the first module can encode the acquired first data encoded with the first FEC code pattern by the second FEC code pattern again, the second data has higher coding gain, and in channels prone to bit errors During transmission, it is possible to effectively correct errors for data with bit errors, thereby improving the quality of data transmission.
  • Scenario 1 the first chip and the second chip are applied to a segmented FEC architecture.
  • the scene one corresponds to the case one in the embodiment shown in FIG. 2 .
  • the implementation environment of this scenario can be shown in Figure 14, and the process of data transmission is as follows.
  • the second chip transmits eight channels of first data to the first chip through the AUI, the media access control (media access control, MAC) rate of the first data is 100Gb/s, and the first data all adopt RS (544, 514) FEC pattern encoded data.
  • the second chip transmits one channel of first data through one AUI, and the transmission rate is 106.25Gb/s.
  • the first chip includes eight processing units, and each processing unit is used to process one channel of first data. After receiving the eight channels of first data, the first chip performs AM locking on each channel of first data to align the first data to obtain multiple first codewords.
  • the plurality of first codewords are codewords encoded by the RS (544, 514) FEC pattern.
  • the first chip performs AM locking on the first data, and after obtaining the alignment result, performs deinterleaving on the alignment result, and obtains multiple first codes according to the deinterleaving Character. After obtaining the multiple first codewords, the first chip decodes the multiple first codewords. In a possible implementation manner, the first chip interleaves the decoding result, and obtains at least one channel of second data according to the interleaved decoding result.
  • the first chip After obtaining the decoding result, the first chip deletes the AM in the decoding result, wherein the AM can be used to determine the AM corresponding to each channel of second data in at least one channel of second data. It should be noted that the first chip can process each channel of first data at the same time or execute a certain channel of first data before processing other channels of first data, which is not limited in this embodiment of the present application. .
  • the first chip performs data combination on the decoding result after AM is deleted.
  • the decoding result after AM deletion is combined into one channel of 800GE third data in a sequential manner, or the decoding result after AM deletion is converted into at least two channels of 800GE third data.
  • the first chip performs data processing on the third data, for example, encodes the third data to obtain a plurality of second codewords, and obtains at least one channel of second data according to the plurality of second codewords.
  • the first chip inserts AM as synchronous data into at least one channel of second data; the data inserted into the synchronous data is processed by a transmitter (transmitter, TX) DSP to obtain 800G coherent light.
  • TX transmitter
  • the implementation environment of this scenario is shown in FIG. 15 , and the data transmission process is as follows.
  • the second chip transmits a channel of first data to the first chip through the AUI, the MAC rate of the first data is 1.6Tb/s, and the first data is 2xRS (544,514) FEC pattern coded interleaved data.
  • the second chip transmits one channel of first data through 16 AUIs, wherein one AUI is used for one channel of first sub-data, and the transmission rate is 106.25Gb/s.
  • the first chip After receiving the first data, the first chip performs AM locking/deskewing on the first data to align the first data to obtain multiple first codewords. Since the first data is data encoded by using the RS (544, 514) FEC pattern, the plurality of first codewords are codewords encoded by the RS (544, 514) FEC pattern.
  • the first chip when the first data is data obtained through interleaving, the first chip performs AM locking on the first data, and after obtaining the alignment result, performs deinterleaving on the alignment result, and obtains multiple first codes according to the deinterleaving Character. After obtaining the multiple first codewords, the first chip decodes the multiple first codewords. In a possible implementation manner, the first chip interleaves the decoding result, and obtains at least one channel of second data according to the interleaved decoding result. After obtaining the decoding result, the first chip deletes the AM in the decoding result, wherein the AM can be used to determine the AM corresponding to each channel of second data in at least one channel of second data.
  • the first chip distributes the decoding result after the AM is deleted.
  • the decoding result after AM deletion is converted into the third data of two channels of 800GE.
  • the first chip performs data processing on the two channels of third data, for example, encodes the two channels of third data to obtain multiple second codewords, and obtains two channels of second data according to the multiple second codewords. It should be noted that the processing of the two channels of third data may be the same or different.
  • the first chip inserts AM as synchronous data into two channels of second data; performs TX DSP on the data after inserting synchronous data to obtain two channels of 800G coherent light.
  • the processing of the two channels of second data may be the same or different, so that the wavelengths of the two channels of 800G coherent light obtained may be the same or different.
  • the first chip and the second chip are applied to an end-to-end FEC architecture.
  • the second scenario corresponds to the second scenario in the embodiment shown in FIG. 2 .
  • the implementation environment of this scenario is shown in Figure 16, and the data transmission process is as follows.
  • the second chip transmits eight channels of first data to the first chip through the AUI, the MAC rates of the first data are all 100Gb/s, and the first data are all data encoded by RS(544,514) FEC code pattern.
  • the second chip transmits one channel of first data through one AUI, and the transmission rate is 106.25Gb/s.
  • the first chip includes eight processing units, and each processing unit is used to process one channel of first data. After receiving the eight channels of first data, the first chip performs AM locking on each channel of first data to align the first data to obtain multiple first codewords. Since the first data is data encoded by using the RS (544, 514) FEC pattern, the multiple first codewords are codewords encoded by the RS (544, 514) FEC pattern.
  • the first chip when the first data is data obtained through interleaving, the first chip performs AM locking on the first data, and after obtaining the alignment result, performs deinterleaving on the alignment result, and obtains multiple first codes according to the deinterleaving Character.
  • the processing of each channel of first data by the first chip may be performed at the same time, or the processing of a certain channel of first data may be performed first, and then the processing of other channels of first data shall be performed, which is not limited in this embodiment of the present application.
  • the first chip performs data combination of multiple first codewords. For example, multiple first codewords are combined into one channel of 800GE second data in a manner of sequential transmission, or multiple first codewords are converted into at least two channels of 800GE second data.
  • the second data may be data that has undergone data processing, for example, the second data is data that has undergone interleaving.
  • the first chip performs TX DSP on at least one channel of second data to obtain 800G coherent light.
  • the first chip and the second chip are applied to a cascaded FEC architecture.
  • the third scenario corresponds to the third scenario in the embodiment shown in FIG. 2 .
  • the implementation environment of this scenario is shown in Figure 17, and the data transmission process is as follows.
  • the second chip transmits eight channels of first data to the first chip through the AUI, the MAC rates of the first data are all 100Gb/s, and the first data are all data encoded by RS(544,514) FEC code pattern.
  • the second chip transmits one channel of first data through one AUI, and the transmission rate is 106.25Gb/s.
  • the first chip includes eight processing units, and each processing unit is used to process one channel of first data. After receiving the eight channels of first data, the first chip performs AM locking on each channel of first data to align the first data to obtain multiple first codewords. Since the first data is data encoded by using the RS (544, 514) FEC pattern, the plurality of first codewords are codewords encoded by the RS (544, 514) FEC pattern.
  • the first chip when the first data is data obtained through interleaving, the first chip performs AM locking on the first data, and after obtaining the alignment result, performs deinterleaving on the alignment result, and obtains multiple first codes according to the deinterleaving Character.
  • the first chip may further interleave the obtained multiple first codewords to obtain multiple interleaved first codewords.
  • the processing of each channel of first data by the first chip may be performed at the same time, or the processing of a certain channel of first data may be performed first, and then the processing of other channels of first data shall be performed, which is not limited in this embodiment of the present application.
  • the first chip performs data combination on a plurality of first codewords obtained based on each channel of first data. For example, multiple first codewords are combined into one channel of 800GE seventh data, or multiple first codewords are converted into at least two channels of 800GE seventh data.
  • the first chip performs data processing on the seventh data, for example, encodes the seventh data to obtain a plurality of third codewords, and obtains at least one channel of second data according to the plurality of third codewords.
  • the first chip performs TX DSP on at least one channel of second data to obtain 800G coherent light.
  • the data transmission method includes the following steps.
  • the third module acquires at least one path of second data, at least one path of second data is data obtained by converting at least one path of first data, and the sum of the rates of at least one path of second data is not less than the sum of the rates of at least one path of first data and, the first data is data encoded using the first FEC code pattern.
  • the third module obtains at least one channel of second data sent by the first module.
  • the first module obtains at least one channel of second data, which will not be described in detail in this embodiment of the present application. Refer to the content of the above-mentioned embodiment shown in FIG. 2 .
  • the third module converts at least one channel of second data to obtain at least one channel of first data.
  • the third module can process different situations for different situations of the second data. For example, in the case that the second data is encoded by using the second FEC pattern, the third module decodes the second data according to the second FEC pattern to obtain decoded data.
  • the third module may further process the decoded data, and this embodiment of the present application does not limit the manner in which the third module processes the second data. For example, continue to send the decoded data to other modules.
  • the third module may be located in the third chip, the first module is located in the first chip, and the third module receives at least one channel of second data sent by the first module through the AUI.
  • the second data can be encoded by using the first FEC code pattern and the second FEC code pattern, it can be decoded by the second FEC code pattern, and when it is transmitted in a channel that is prone to code errors, it can prevent code errors from occurring. Effective error correction of the data, thereby improving the quality of data transmission.
  • Fig. 19 is a schematic structural diagram of a data transmission device provided by an embodiment of the present application. Based on the following multiple units shown in FIG. 19 , the device for data transmission shown in FIG. 19 can perform all or part of the operations performed by the first module. It should be understood that the device may include more additional units than the units shown or omit some units shown therein, which is not limited in the embodiment of the present application. As shown in Figure 19, the device includes:
  • An acquisition unit 1901 configured to acquire at least one path of first data, where the first data is data encoded using a first FEC pattern;
  • the converting unit 1902 is configured to convert at least one channel of first data to obtain at least one channel of second data, and the sum of the rates of at least one channel of second data is not less than the sum of the rates of at least one channel of first data;
  • a transmission unit 1903 configured to transmit at least one path of second data.
  • the conversion unit 1902 is configured to align at least one path of first data, obtain multiple first codewords according to the alignment result; decode multiple first codewords, and obtain at least All the way to the second data.
  • the conversion unit 1902 is configured to encode the decoding result according to the second FEC pattern to obtain multiple second codewords; obtain at least one channel of second data according to the multiple second codewords.
  • the conversion unit 1902 is configured to perform interleaving on multiple second codewords, and obtain at least one channel of second data according to the interleaving result.
  • the first data includes an alignment mark AM, and AM is used to align at least one path of first data; the conversion unit 1902 is used to delete AM in the decoding result, and delete the AM according to the second FEC pattern.
  • the decoding result after AM is encoded to obtain a plurality of second codewords.
  • the conversion unit 1902 is configured to combine the decoding results after the AM is deleted into one path of third data in a manner of sequential transmission, and encode one path of third data to obtain multiple second codewords; Alternatively, convert the decoding result after AM is deleted into at least two channels of third data, and encode the at least two channels of third data to obtain multiple second codewords.
  • the conversion unit 1902 is configured to combine the decoding results after AM deletion into one path of fourth data, and convert one path of fourth data into at least two paths of third data.
  • the converting unit 1902 is configured to encode one channel of third data as a whole according to the second FEC pattern to obtain multiple second codewords; or, convert one channel of third data into at least two channels
  • For the fifth data at least two channels of fifth data are respectively encoded according to the second FEC code pattern to obtain multiple second codewords, wherein the rate of the fifth data is lower than the rate of the third data.
  • the conversion unit 1902 is configured to perform integral encoding on at least two channels of third data according to the second FEC code pattern to obtain multiple second codewords; or to encode at least two channels of third data according to the second FEC code pattern
  • the third data of the roads are respectively encoded to obtain a plurality of second codewords.
  • the converting unit 1902 is configured to respectively perform integral encoding on at least two channels of third data according to the second FEC pattern to obtain multiple second codewords; or, convert at least two channels of third data Each is converted into at least two channels of sixth data, and the at least two channels of sixth data are respectively encoded according to the second FEC code pattern to obtain a plurality of second codewords, wherein the rate of the sixth data is lower than the rate of the third data.
  • the conversion unit 1902 is configured to mark an erroneous code block among the multiple code blocks included in the decoding result, and acquire at least one path of second data according to the marked decoding result.
  • the converting unit 1902 is configured to align at least one path of first data, obtain multiple first codewords according to the alignment result; obtain at least one path of second data according to the multiple first codewords.
  • the conversion unit 1902 is configured to combine a plurality of first codewords, and obtain at least one channel of second data according to a combination result.
  • the conversion unit 1902 is configured to combine multiple first codewords into one channel of second data in a manner of sequential transmission; or, combine multiple first codewords into at least two channels of second data data.
  • the conversion unit 1902 is configured to perform deinterleaving on the alignment result, and obtain multiple first codewords according to the deinterleaving result.
  • the conversion unit 1902 is configured to encode at least one path of first data according to the second FEC pattern to obtain multiple third codewords; obtain at least one path of second data according to the multiple third codewords. data.
  • the conversion unit 1902 is configured to perform interleaving on a plurality of third codewords, and obtain at least one channel of second data according to an interleaving result.
  • the conversion unit 1902 is configured to combine at least one piece of first data into one piece of seventh data in a sequential manner, and encode one piece of seventh data to obtain multiple third codewords; or , converting at least one path of first data into at least two paths of seventh data, and encoding at least two paths of seventh data to obtain multiple third codewords.
  • the transforming unit 1902 is configured to combine at least one path of first data into one path of eighth data, and convert one path of eighth data into at least two paths of seventh data.
  • the converting unit 1902 is configured to encode one channel of seventh data as a whole according to the second FEC pattern to obtain multiple third codewords; or, convert one channel of seventh data into at least two channels
  • For the ninth data at least two channels of ninth data are respectively encoded according to the second FEC code pattern to obtain a plurality of third codewords, wherein the rate of the ninth data is lower than the rate of the seventh data.
  • the conversion unit 1902 is configured to perform integral encoding on at least two channels of seventh data according to the second FEC code pattern to obtain multiple third codewords; or to encode at least two channels of seventh data according to the second FEC code pattern The seventh data of the road are respectively encoded to obtain a plurality of third codewords.
  • the converting unit 1902 is configured to respectively perform overall encoding on at least two channels of seventh data according to the second FEC code pattern to obtain multiple third codewords; or, convert at least two channels of seventh data Each is converted into at least two channels of tenth data, and the at least two channels of tenth data are respectively encoded according to the second FEC pattern to obtain a plurality of third codewords, wherein the rate of the tenth data is lower than the rate of the seventh data.
  • the transmission unit 1903 is configured to insert the synchronization data into at least one path of second data, and transmit the data after the synchronization data is inserted.
  • the transmission unit 1903 is configured to determine the AM corresponding to each path of second data in at least one path of second data; insert the AM corresponding to each path of second data as synchronous data into each path of second data .
  • the AM corresponding to each path of second data is obtained by adjusting the AM included in the corresponding first data; or, the AM corresponding to each path of second data is the AM included in the corresponding first data.
  • the entire content; or, the AM corresponding to each channel of second data is part of the content in the AM included in the corresponding first data.
  • FIG. 20 is a schematic structural diagram of a data transmission device provided by an embodiment of the present application. Based on the following multiple units shown in FIG. 20 , the device for data transmission shown in FIG. 20 can perform all or part of the operations performed by the third module. It should be understood that the device may include more additional units than the units shown or omit some units shown therein, which is not limited in the embodiment of the present application. As shown in Figure 20, the device includes:
  • the acquisition unit 2001 is configured to acquire at least one channel of second data, at least one channel of second data is data obtained by converting at least one channel of first data, and the sum of the rates of at least one channel of second data is not less than the rate of at least one channel of first data
  • the sum, the first data is the data encoded by the first forward error correction code FEC pattern
  • the converting unit 2002 is configured to convert at least one channel of second data to obtain at least one channel of first data.
  • An embodiment of the present application provides a device for data transmission, which includes: a processor, the processor is coupled to a memory, and at least one program instruction or code is stored in the memory, and the at least one program instruction or code is executed by the processor Load and execute, so that the device for data transmission implements the methods in the above method embodiments.
  • FIG. 21 shows a schematic structural diagram of a data transmission device 1100 provided by an exemplary embodiment of the present application, and the data transmission device 1100 is a sending-side/receiving-side device.
  • the data transmission device 1100 shown in FIG. 21 is configured to perform the operations involved in the above-mentioned data transmission method shown in FIG. 2 .
  • the device 1100 for data transmission is, for example, network devices such as switches and routers, and other devices (such as servers, PCs, etc.) that include this chip cascading mode.
  • the hardware structure of the data transmission device 1100 includes a communication interface 1101 and a processor 1102 .
  • the communication interface 1101 and the processor 1102 are connected through a bus 1104 .
  • the communication interface 1101 is used to obtain the first data and transmit the second data
  • the processor may store instructions or program codes, and execute the functions performed by the above-mentioned first module by calling the instructions or program codes, or the functions performed by the third module. function performed.
  • the data transmission device 1100 further includes a memory 1103, and the memory 1103 stores instructions or program codes, and the processor 1102 is used to call the instructions or program codes in the memory 1103 so that the data transmission device 1100 executes the above method embodiment The relevant processing steps of the first module in .
  • the data transmission device 1100 of the embodiment of the present application may include the first module in each of the above method embodiments, the processor 1102 in the data transmission device 1100 reads the instructions or program codes in the memory 1103, The device 1100 for data transmission shown in FIG. 21 is enabled to perform all or part of the operations performed by the first module.
  • the data transmission device 1100 of the embodiment of the present application includes the third module in each of the above-mentioned method embodiments, and the processor 1102 in the data transmission device 1100 reads the instructions or program codes in the memory 1103, so that The device 1100 for data transmission shown in FIG. 21 can perform all or part of the operations performed by the third module.
  • the processor 1102 is, for example, a general-purpose central processing unit (central processing unit, CPU), a digital signal processor (digital signal processor, DSP), a network processor (network processor, NP), a graphics processing unit (graphics processing unit , GPU), neural-network processing units (neural-network processing units, NPU), data processing unit (data processing unit, DPU), microprocessor or one or more integrated circuits for implementing the solution of this application.
  • the processor 1102 includes an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • the PLD is, for example, a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof. It can realize or execute various logical blocks, modules and circuits described in conjunction with the disclosure of the embodiments of the present application.
  • the processor can also be a combination of computing functions, for example, a combination of one or more microprocessors, a combination of DSP and a microprocessor, and so on.
  • the data transmission device 1100 further includes a bus 1104 .
  • the bus 1104 is used to transfer information between the various components of the device 1100 for data transfer.
  • the bus 1104 may be a peripheral component interconnect standard (PCI for short) bus or an extended industry standard architecture (EISA for short) bus or the like.
  • PCI peripheral component interconnect standard
  • EISA extended industry standard architecture
  • the bus 1104 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in FIG. 21 , but it does not mean that there is only one bus or one type of bus.
  • the components of the device 1100 for data transmission in FIG. 21 may be connected in other ways besides using the bus 1104 , and the embodiment of the present application does not limit the connection mode of the components.
  • the memory 1103 is, for example, a read-only memory (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (random access memory, RAM) or a memory that can store information and instructions.
  • Other types of dynamic storage devices such as electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc Storage (including Compact Disc, Laser Disc, Optical Disc, Digital Versatile Disc, Blu-ray Disc, etc.), magnetic disk storage medium, or other magnetic storage device, or is capable of carrying or storing desired program code in the form of instructions or data structures and capable of Any other medium accessed by a computer, but not limited to.
  • the memory 1103 exists independently, for example, and is connected to the processor 1102 through the bus 1104 .
  • the memory 1103 can also be integrated with the processor 1102 .
  • the communication interface 1101 uses any device such as a transceiver to communicate with other devices or a communication network.
  • the communication network can be Ethernet, radio access network (RAN) or wireless local area networks (wireless local area networks, WLAN).
  • the communication interface 1101 may include a wired communication interface, and may also include a wireless communication interface.
  • the communication interface 1101 can be an Ethernet (ethernet) interface, a fast ethernet (fast ethernet, FE) interface, a gigabit ethernet (gigabit ethernet, GE) interface, an asynchronous transfer mode (asynchronous transfer mode, ATM) interface, a wireless local area network ( wireless local area networks, WLAN) interface, cellular network communication interface or a combination thereof.
  • the Ethernet interface can be an optical interface, an electrical interface or a combination thereof.
  • the communication interface 1101 may be used for the device 1100 for data transmission to communicate with other devices.
  • the processor 1102 may include one or more CPUs. Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the data transmission device 1100 may include multiple processors.
  • processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU).
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data such as computer program instructions.
  • the data transmission device 1100 may further include an output device and an input device.
  • Output devices are in communication with processor 1102 and can display information in a variety of ways.
  • the output device may be a liquid crystal display (liquid crystal display, LCD), a light emitting diode (light emitting diode, LED) display device, a cathode ray tube (cathode ray tube, CRT) display device, or a projector (projector).
  • the input device is in communication with the processor 1102 and can receive user input in a variety of ways.
  • the input device may be a mouse, a keyboard, a touch screen device, or a sensing device, among others.
  • the memory 1103 is used to store program codes for implementing the solutions of the present application, and the processor 1102 can execute the program codes stored in the memory 1103 . That is, the data transmission device 1100 can implement the data transmission method provided by the method embodiment through the processor 1102 and the program code in the memory 1103 .
  • the program code may include one or more software modules.
  • the processor 1102 itself may also store program codes or instructions for executing the solutions of the present application.
  • the data transmission device 1100 of the embodiment of the present application may include the first module in each of the above method embodiments, and the processor 1102 in the data transmission device 1100 reads the program code or the processor in the memory 1103
  • the program code or instruction stored in 1102 itself enables the data transmission device 1100 shown in FIG. 21 to perform all or part of the operations performed by the first module.
  • the data transmission device 1100 of the embodiment of the present application may include the third module in each of the above method embodiments, and the processor 1102 in the data transmission device 1100 reads the program code or the processor in the memory 1103
  • the program codes or instructions stored in 1102 enable the data transmission device 1100 shown in FIG. 21 to perform all or part of the operations performed by the third module.
  • the data transmission device 1100 may also correspond to the above-mentioned devices shown in FIGS. 19 and 20 , and each functional unit in the devices shown in FIGS. 19 and 20 is implemented by software of the data transmission device 1100 .
  • the functional units included in the apparatus shown in FIGS. 19 and 20 are generated after the processor 1102 of the data transmission device 1100 reads the program code stored in the memory 1103 .
  • each step of the data transmission method shown in FIGS. 2-18 is completed by an integrated logic circuit of hardware in a processor of the data transmission device 1100 or an instruction in the form of software.
  • the steps of the methods disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
  • the software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware. To avoid repetition, no detailed description is given here.
  • the embodiment of the present application also provides a data transmission system, the system includes: a first data transmission device and a second data transmission device; the first data transmission device is used to execute the first module shown in Figure 2 In the executed method, the second data transmission device is used to execute the method executed by the third module shown in FIG. 18 .
  • processor may be a CPU, or other general-purpose processors, DSP, ASIC, FPGA or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like.
  • a general purpose processor may be a microprocessor or any conventional processor or the like. It should be noted that the processor may be a processor supporting advanced RISC machines (ARM) architecture.
  • ARM advanced RISC machines
  • the above-mentioned memory may include a read-only memory and a random-access memory, and provide instructions and data to the processor.
  • Memory may also include non-volatile random access memory.
  • the memory may also store device type information.
  • the memory can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
  • the non-volatile memory may be ROM, programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), EEPROM or flash memory.
  • Volatile memory can be RAM, which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available.
  • static random access memory static random access memory
  • dynamic random access memory dynamic random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • double data rate synchronous dynamic random access Memory double data date SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • synchronous link dynamic random access memory direct memory bus random access memory (direct rambus) RAM, DR RAM).
  • the present application provides a computer program.
  • the processor or the computer can execute the corresponding steps and/or processes in the above method embodiments.
  • a chip including a processor, configured to call from a memory and execute instructions stored in the memory, so that a device equipped with the chip executes the methods in the above aspects.
  • Provide another chip including: input interface, output interface, processor and memory, the input interface, output interface, processor and memory are connected through internal connection paths, the processor is used to execute the code in the memory, when the code is executed When, the processor is configured to execute the methods in the foregoing aspects.
  • a device including the chip in any one of the above schemes.
  • a device including the first chip in any of the above schemes, and/or, the third chip in any of the above schemes.
  • the second chip can be a sending-side device, such as a physical layer (PHY) chip in a router, a switch, or a server, and the first chip can be an interface of a receiving-side device, such as an optical module Chips in or clock data recovery (clock data recovery, CDR) / retimer (retimer) chips.
  • the first chip may be a sending-side device, such as a PHY chip in a router, switch, or server, and the third chip may be an interface of a receiving-side device, such as a chip in an optical module or a CDR/retimer chip.
  • the PHY chip may be a chip located on a single board of the computing device, and the chip may be one of CPU, NP, NPU, FPGA, programmable logic controller (programmable logic controller, PLC), etc. or any combination thereof.
  • the communication between the first chip and the second chip is through the AUI; in some embodiments, the communication between the third chip and the first chip is through the AUI.
  • a computer program product includes one or more computer instructions.
  • Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g. Coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) to another website site, computer, server or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server, a data center, etc. integrated with one or more available media.
  • the usable medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a digital versatile disc (DVD)), or a semiconductor medium (such as a solid state disk (solid state disk)).
  • the computer program product includes one or more computer program instructions.
  • the methods of embodiments of the present application may be described in the context of machine-executable instructions, such as program modules included in a device executed on a real or virtual processor of a target.
  • program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data structures.
  • the functionality of the program modules may be combined or divided between the described program modules.
  • Machine-executable instructions for program modules may be executed locally or in distributed devices. In a distributed device, program modules may be located in both local and remote storage media.
  • Computer program codes for implementing the methods of the embodiments of the present application may be written in one or more programming languages. These computer program codes can be provided to processors of general-purpose computers, special-purpose computers, or other programmable data processing devices, so that when the program codes are executed by the computer or other programmable data processing devices, The functions/operations specified in are implemented.
  • the program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.
  • computer program codes or related data may be carried by any appropriate carrier, so that a device, apparatus or processor can perform various processes and operations described above.
  • Examples of carriers include signals, computer readable media, and the like.
  • Examples of signals may include electrical, optical, radio, sound, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.
  • a machine-readable medium may be any tangible medium that contains or stores a program for or related to an instruction execution system, apparatus, or device.
  • a machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include electrical connections with one or more wires, portable computer disks, hard disks, RAM, ROM, Erasable Programmable Read-Only Memory (EPROM or Flash), optical storage devices, magnetic storage devices, or any suitable combination thereof.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the modules is only a logical function division. In actual implementation, there may be other division methods.
  • multiple modules or components can be combined or can be Integrate into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or modules, and may also be electrical, mechanical or other forms of connection.
  • the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple network modules. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present application.
  • each functional module in each embodiment of the present application may be integrated into one processing module, each module may exist separately physically, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.
  • the integrated module is realized in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of software products, and the computer software products are stored in a storage medium
  • several instructions are included to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods in the various embodiments of the present application.
  • the aforementioned storage medium includes: various media capable of storing program codes such as U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk.
  • first, second and other words in this application are used to distinguish the same or similar items with basically the same function and function. It should be understood that the words “first”, “second” and “nth” There is no logical or chronological dependency between them, and there is no limitation on the number and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, a first module could be termed a second module, and, similarly, a second module could be termed a first module, without departing from the scope of the various described examples.
  • if and “if” may be construed to mean “when” ("when” or “upon”) or “in response to determining” or “in response to detecting”.
  • phrases “if it is determined" or “if [the stated condition or event] is detected” may be construed to mean “when determining” or “in response to determining... ” or “upon detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • determining B according to A does not mean determining B only according to A, and B may also be determined according to A and/or other information.

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Abstract

本申请公开了数据传输的方法、装置、设备、系统及可读存储介质。该数据传输的方法包括：第一模块获取采用第一FEC编码的至少一路第一数据；对该至少一路第一数据进行转化处理，得到至少一路第二数据，该至少一路第二数据的速率之和不小于该至少一路第一数据的速率之和；传输得到的至少一路第二数据。该方法通过对至少一路第一数据进行转化处理，得到速率之和不小于至少一路第一数据的速率之和的至少一路第二数据，进而能够以较高的速率进行数据传输。

Description

数据传输的方法、装置、设备、系统及可读存储介质
本申请要求于2021年10月30日提交的申请号为202111278595.3、发明名称为“数据传输的方法、装置、设备、系统及可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信技术领域，尤其涉及一种数据传输的方法、装置、设备、系统及可读存储介质。
背景技术
随着对数据传输的需求不断增加，对传输速率的要求不断提高。例如，对于数据中心等要求低时延传输的场景，需要以较高的传输速率进行数据传输。因此，亟需一种数据传输的方法，以实现较高的传输速率。
发明内容
本申请提供一种数据传输的方法、装置、设备、系统及可读存储介质，用于提高数据传输速率。
第一方面，提供了一种数据传输的方法，该方法包括：第一模块获取采用第一前向纠错码FEC编码的至少一路第一数据；对该至少一路第一数据进行转化处理，得到至少一路第二数据，该至少一路第二数据的速率之和不小于该至少一路第一数据的速率之和；传输得到的至少一路第二数据。
该方法通过对至少一路第一数据进行转化处理，得到速率之和不小于至少一路第一数据的速率之和的至少一路第二数据，进而能够以较高的速率进行数据传输。
在一种可能的实施方式中，第一模块对至少一路第一数据进行转化处理，得到至少一路第二数据，包括：第一模块对至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；对多个第一码字进行解码，根据解码结果获取至少一路第二数据。
在一种可能的实施方式中，根据解码结果获取至少一路第二数据，包括：按照第二FEC码型对解码结果进行编码，得到多个第二码字；根据多个第二码字得到至少一路第二数据。对于基于不同第一数据得到的解码结果，第一模块可以采用相同或不同的第二FEC码型对解码结果进行编码，以灵活适用于传输场景和传输要求。
在一种可能的实施方式中，根据多个第二码字得到至少一路第二数据，包括：对多个第二码字进行交织，根据交织结果得到至少一路第二数据。
在一种可能的实施方式中，第一数据包括对齐标志AM，AM用于对至少一路第一数据进行对齐；按照第二FEC码型对解码结果进行编码，得到多个第二码字，包括：删除解码结果中的AM，按照第二FEC码型对删除AM之后的解码结果进行编码，得到多个第二码字。
在一种可能的实施方式中，按照第二FEC码型对删除AM之后的解码结果进行编码，得 到多个第二码字，包括：将删除AM之后的解码结果以依次发送的方式合并成一路第三数据，对一路第三数据进行编码，得到多个第二码字；或者，将删除AM之后的解码结果转换成至少两路第三数据，对至少两路第三数据进行编码，得到多个第二码字。
在一种可能的实施方式中，将删除AM之后的解码结果转换成至少两路第三数据，包括：将删除AM之后的解码结果合并成一路第四数据，将一路第四数据转换成至少两路第三数据。
在一种可能的实施方式中，对一路第三数据进行编码，得到多个第二码字，包括：按照第二FEC码型对一路第三数据进行整体编码，得到多个第二码字；或者，将一路第三数据转化为至少两路第五数据，按照第二FEC码型对至少两路第五数据分别进行编码，得到多个第二码字，其中，第五数据的速率小于第三数据的速率。该方法能够采用不同的方式对第三数据进行编码，以得到多个第二码字，从而该方法适用的传输场景和传输要求较为灵活。此外，在第三数据的路数为多路的情况下，第三数据的路数以及对第三数据编码所采用的第二FEC码型可以进行灵活设置，以适用于不同的传输场景和传输需求。
在一种可能的实施方式中，对至少两路第三数据进行编码，得到多个第二码字，包括：按照第二FEC码型对至少两路第三数据进行整体编码，得到多个第二码字；或者按照第二FEC码型对至少两路第三数据分别进行编码，得到多个第二码字。
在一种可能的实施方式中，按照第二FEC码型对至少两路第三数据分别进行编码，得到多个第二码字，包括：按照第二FEC码型对至少两路第三数据分别进行整体编码，得到多个第二码字；或者，将至少两路第三数据各自转换成至少两路第六数据，按照第二FEC码型对至少两路第六数据分别进行编码，得到多个第二码字，其中，第六数据的速率小于第三数据的速率。
在一种可能的实施方式中，根据解码结果获取至少一路第二数据，包括：标记解码结果包括的多个码块中的错误码块，根据标记后的解码结果获取至少一路第二数据。由于第一模块能够标记解码结果中的错误码块，后续接收侧模块接收到基于该解码结果获取的第二数据时能够基于标记的错误码块对数据进行有效的纠错，以提高纠错性能，提高数据传输的质量。
在一种可能的实施方式中，第一模块对至少一路第一数据进行转化处理，得到至少一路第二数据，包括：第一模块对至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；根据多个第一码字得到至少一路第二数据。
在一种可能的实施方式中，根据多个第一码字得到至少一路第二数据，包括：对多个第一码字进行合并，根据合并结果得到至少一路第二数据。
在一种可能的实施方式中，对多个第一码字进行合并，根据合并结果得到至少一路第二数据，包括：将多个第一码字以依次发送的方式合并成一路第二数据；或者，将多个第一码字合并成至少两路第二数据。
在一种可能的实施方式中，至少一路第一数据为经过交织得到的数据，根据对齐结果获取多个第一码字，包括：对对齐结果进行解交织，根据解交织结果得到多个第一码字。
在一种可能的实施方式中，第一模块对至少一路第一数据进行转化处理，得到至少一路第二数据，包括：第一模块按照第二FEC码型对至少一路第一数据进行编码，得到多个第三码字；第一模块根据多个第三码字得到至少一路第二数据。由于第一模块可以将获取的采用第一FEC码型编码的第一数据通过第二FEC码型进行再一次编码，第二数据具有更高的编码增益，在容易出现误码的通道中传输时，能够对出现误码的数据进行有效的纠错，从而提 高数据传输的质量。
在一种可能的实施方式中，根据多个第三码字得到至少一路第二数据，包括：对多个第三码字进行交织，根据交织结果得到至少一路第二数据。
在一种可能的实施方式中，第一模块按照第二FEC码型对至少一路第一数据进行编码，得到多个第三码字，包括：将至少一路第一数据以依次发送的方式合并成一路第七数据，对一路第七数据进行编码，得到多个第三码字；或者，将至少一路第一数据转换成至少两路第七数据，对至少两路第七数据进行编码，得到多个第三码字。该方法能够采用不同的方式对第七数据进行编码，以得到多个第三码字，从而该方法适用的传输场景和传输要求较为灵活。此外，在第七数据的路数为多路的情况下，第七数据的路数以及对第七数据编码所采用的第二FEC码型可以进行灵活设置，以适用于不同的传输场景和传输需求。
在一种可能的实施方式中，将至少一路第一数据转换成至少两路第七数据，包括：将至少一路第一数据合并成一路第八数据，将一路第八数据转换成至少两路第七数据。
在一种可能的实施方式中，对一路第七数据进行编码，得到多个第三码字，包括：按照第二FEC码型对一路第七数据进行整体编码，得到多个第三码字；或者，将一路第七数据转化为至少两路第九数据，按照第二FEC码型对至少两路第九数据分别进行编码，得到多个第三码字，其中，第九数据的速率小于第七数据的速率。
在一种可能的实施方式中，对至少两路第七数据进行编码，得到多个第三码字，包括：按照第二FEC码型对至少两路第七数据进行整体编码，得到多个第三码字；或者按照第二FEC码型对至少两路第七数据分别进行编码，得到多个第三码字。
在一种可能的实施方式中，按照第二FEC码型对至少两路第七数据分别进行编码，得到多个第三码字，包括：按照第二FEC码型对至少两路第七数据分别进行整体编码，得到多个第三码字；或者，将至少两路第七数据各自转换成至少两路第十数据，按照第二FEC码型对至少两路第十数据分别进行编码，得到多个第三码字，其中，第十数据的速率小于第七数据的速率。
在一种可能的实施方式中，第一模块传输至少一路第二数据，包括：第一模块将同步数据插入至少一路第二数据，传输插入同步数据后的数据。
在一种可能的实施方式中，第一模块将同步数据插入至少一路第二数据，包括：确定至少一路第二数据中的各路第二数据对应的AM；将各路第二数据对应的AM作为同步数据插入各路第二数据。
在一种可能的实施方式中，各路第二数据对应的AM通过调整对应的第一数据包括的AM得到；或者，各路第二数据对应的AM为对应的第一数据包括的AM中的全部内容；或者，各路第二数据对应的AM为对应的第一数据包括的AM中的部分内容。
第二方面，提供了一种数据传输的方法，该方法包括：第三模块获取至少一路第二数据，该至少一路第二数据为对至少一路第一数据进行转化处理得到的数据，至少一路第二数据的速率之和不小于至少一路第一数据的速率之和，第一数据为采用第一前向纠错码FEC码型编码的数据；第三模块对至少一路第二数据进行转化处理，得到至少一路第一数据。
第三方面，提供了一种数据传输的装置，该装置应用于第一模块，该装置包括：
获取单元，用于获取至少一路第一数据，第一数据为采用第一前向纠错码FEC码型编码的数据；
转化单元，用于对至少一路第一数据进行转化处理，得到至少一路第二数据，至少一路第二数据的速率之和不小于至少一路第一数据的速率之和；
传输单元，用于传输至少一路第二数据。
在一种可能的实施方式中，转化单元，用于对至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；对多个第一码字进行解码，根据解码结果获取至少一路第二数据。
在一种可能的实施方式中，转化单元，用于按照第二FEC码型对解码结果进行编码，得到多个第二码字；根据多个第二码字得到至少一路第二数据。
在一种可能的实施方式中，转化单元，用于对多个第二码字进行交织，根据交织结果得到至少一路第二数据。
在一种可能的实施方式中，第一数据包括对齐标志AM，AM用于对至少一路第一数据进行对齐；转化单元，用于删除解码结果中的AM，按照第二FEC码型对删除AM之后的解码结果进行编码，得到多个第二码字。
在一种可能的实施方式中，转化单元，用于将删除AM之后的解码结果以依次发送的方式合并成一路第三数据，对一路第三数据进行编码，得到多个第二码字；或者，将删除AM之后的解码结果转换成至少两路第三数据，对至少两路第三数据进行编码，得到多个第二码字。
在一种可能的实施方式中，转化单元，用于将删除AM之后的解码结果合并成一路第四数据，将一路第四数据转换成至少两路第三数据。
在一种可能的实施方式中，转化单元，用于按照第二FEC码型对一路第三数据进行整体编码，得到多个第二码字；或者，将一路第三数据转化为至少两路第五数据，按照第二FEC码型对至少两路第五数据分别进行编码，得到多个第二码字，其中，第五数据的速率小于第三数据的速率。
在一种可能的实施方式中，转化单元，用于按照第二FEC码型对至少两路第三数据进行整体编码，得到多个第二码字；或者按照第二FEC码型对至少两路第三数据分别进行编码，得到多个第二码字。
在一种可能的实施方式中，转化单元，用于按照第二FEC码型对至少两路第三数据分别进行整体编码，得到多个第二码字；或者，将至少两路第三数据各自转换成至少两路第六数据，按照第二FEC码型对至少两路第六数据分别进行编码，得到多个第二码字，其中，第六数据的速率小于第三数据的速率。
在一种可能的实施方式中，转化单元，用于标记解码结果包括的多个码块中的错误码块，根据标记后的解码结果获取至少一路第二数据。
在一种可能的实施方式中，转化单元，用于对至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；根据多个第一码字得到至少一路第二数据。
在一种可能的实施方式中，转化单元，用于对多个第一码字进行合并，根据合并结果得到至少一路第二数据。
在一种可能的实施方式中，转化单元，用于将多个第一码字以依次发送的方式合并成一路第二数据；或者，将多个第一码字合并成至少两路第二数据。
在一种可能的实施方式中，转化单元，用于对对齐结果进行解交织，根据解交织结果得到多个第一码字。
在一种可能的实施方式中，转化单元，用于按照第二FEC码型对至少一路第一数据进行编码，得到多个第三码字；根据多个第三码字得到至少一路第二数据。
在一种可能的实施方式中，转化单元，用于对多个第三码字进行交织，根据交织结果得到至少一路第二数据。
在一种可能的实施方式中，转化单元，用于将至少一路第一数据以依次发送的方式合并成一路第七数据，对一路第七数据进行编码，得到多个第三码字；或者，将至少一路第一数据转换成至少两路第七数据，对至少两路第七数据进行编码，得到多个第三码字。
在一种可能的实施方式中，转化单元，用于将至少一路第一数据合并成一路第八数据，将一路第八数据转换成至少两路第七数据。
在一种可能的实施方式中，转化单元，用于按照第二FEC码型对一路第七数据进行整体编码，得到多个第三码字；或者，将一路第七数据转化为至少两路第九数据，按照第二FEC码型对至少两路第九数据分别进行编码，得到多个第三码字，其中，第九数据的速率小于第七数据的速率。
在一种可能的实施方式中，转化单元，用于按照第二FEC码型对至少两路第七数据进行整体编码，得到多个第三码字；或者按照第二FEC码型对至少两路第七数据分别进行编码，得到多个第三码字。
在一种可能的实施方式中，转化单元，用于按照第二FEC码型对至少两路第七数据分别进行整体编码，得到多个第三码字；或者，将至少两路第七数据各自转换成至少两路第十数据，按照第二FEC码型对至少两路第十数据分别进行编码，得到多个第三码字，其中，第十数据的速率小于第七数据的速率。
在一种可能的实施方式中，传输单元，用于将同步数据插入至少一路第二数据，传输插入同步数据后的数据。
在一种可能的实施方式中，传输单元，用于确定至少一路第二数据中的各路第二数据对应的AM；将各路第二数据对应的AM作为同步数据插入各路第二数据。
在一种可能的实施方式中，各路第二数据对应的AM通过调整对应的第一数据包括的AM得到；或者，各路第二数据对应的AM为对应的第一数据包括的AM中的全部内容；或者，各路第二数据对应的AM为对应的第一数据包括的AM中的部分内容。
第四方面，提供了一种数据传输的装置，该装置应用于第三模块，该装置包括：
获取单元，用于获取至少一路第二数据，至少一路第二数据为对至少一路第一数据进行转化处理得到的数据，至少一路第二数据的速率之和不小于至少一路第一数据的速率之和，第一数据为采用第一前向纠错码FEC码型编码的数据；
转化单元，用于对至少一路第二数据进行转化处理，得到至少一路第一数据。
第五方面，提供了一种数据传输的设备，该设备包括：处理器，处理器与存储器耦合，存储器中存储有至少一条程序指令或代码，至少一条程序指令或代码由处理器加载并执行，以使设备实现如第一方面或第二方面中任一的数据传输的方法。
第六方面，提供了一种数据传输的系统，该系统包括：第一数据传输的设备，用于执行 上述第一方面或第一方面任一所述的方法，第二数据传输的设备，用于执行上述第二方面或第二方面任一所述的方法。
第七方面，提供了一种计算机可读存储介质，该计算机可读存储介质中存储有至少一条程序指令或代码，程序指令或代码由处理器加载并执行时以使计算机实现如第一方面或第二方面中任一的数据传输的方法。
提供了另一种通信装置，该装置包括：通信接口、存储器和处理器。其中，该存储器和该处理器通过内部连接通路互相通信，该存储器用于存储指令，该处理器用于执行该存储器存储的指令，以控制通信接口接收数据，并控制通信接口发送数据，并且当该处理器执行该存储器存储的指令时，使得该处理器执行第一方面或第一方面的任一种可能的实施方式中的方法，或者执行第二方面或第二方面的任一种可能的实施方式中的方法。
示例性地，处理器为一个或多个，存储器为一个或多个。
示例性地，存储器可以与处理器集成在一起，或者存储器与处理器分离设置。
在具体实现过程中，存储器可以为非瞬时性(non-transitory)存储器，例如只读存储器(read only memory，ROM)，其可以与处理器集成在同一块芯片上，也可以分别设置在不同的芯片上，本申请对存储器的类型以及存储器与处理器的设置方式不做限定。
提供了一种计算机程序(产品)，所述计算机程序(产品)包括：计算机程序代码，当所述计算机程序代码被计算机运行时，使得所述计算机执行上述各方面中的方法。
提供了一种芯片，包括处理器，用于从存储器中调用并运行所述存储器中存储的指令，使得安装有所述芯片的设备执行上述各方面中的方法。
提供另一种芯片，包括：输入接口、输出接口、处理器和存储器，所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连，所述处理器用于执行所述存储器中的代码，当所述代码被执行时，所述处理器用于执行上述各方面中的方法。
提供一种设备，包括上述方案中任一所述的芯片。
提供一种设备，包括上述方案中任一所述的第一模块，和/或，上述方案中任一所述的第三模块。
应当理解的是，本申请实施例的第三方面至第七方面的技术方案及对应的可能的实现方式所取得的有益效果可以参见上述对第一方面和第二方面及其对应的可能的实现方式的技术效果，此处不再赘述。
附图说明
图1是本申请实施例提供的一种数据传输的方法的实施场景示意图；
图2是本申请实施例提供的一种数据传输的方法流程图；
图3是本申请实施例提供的一种第一数据和第二数据的示意图；
图4是本申请实施例提供的另一种第一数据和第二数据的示意图；
图5是本申请实施例提供的一种得到至少一路第二数据的过程示意图；
图6是本申请实施例提供的另一种得到至少一路第二数据的过程示意图；
图7是本申请实施例提供的一种标记错误码块的过程示意图；
图8是本申请实施例提供的另一种标记错误码块的过程示意图；
图9是本申请实施例提供的另一种标记错误码块的过程示意图；
图10是本申请实施例提供的另一种标记错误码块的过程示意图；
图11是本申请实施例提供的一种合并成第三数据的过程示意图；
图12是本申请实施例提供的另一种第一数据和第二数据的示意图；
图13是本申请实施例提供的另一种第一数据和第二数据的示意图；
图14是本申请实施例提供的一种应用场景的实施环境示意图；
图15是本申请实施例提供的另一种应用场景的实施环境示意图；
图16是本申请实施例提供的另一种应用场景的实施环境示意图；
图17是本申请实施例提供的另一种应用场景的实施环境示意图；
图18是本申请实施例提供的另一种数据传输的方法流程图；
图19是本申请实施例提供的一种数据传输的装置的结构示意图；
图20是本申请实施例提供的另一种数据传输的装置的结构示意图；
图21是本申请实施例提供的另一种数据传输的设备的结构示意图。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。下面结合附图，对本申请的实施例进行描述。
在通信技术领域中，随着对数据传输的需求不断增加，对于传输速率的要求不断提高，当前的传输速率逐渐难以满足要求。例如，对于数据中心等要求低时延传输的场景，200吉比特以太网(gigabit ethernet，GE)/400GE逐渐难以满足时延要求，需要更高的传输速率来进行数据传输，例如800GE/1.6T太比特以太网(terabit ethernet，TE)。
对此，本申请实施例提供了一种数据传输的方法，该方法通过对至少一路第一数据进行转化处理，得到至少一路第二数据，该至少一路第二数据的速率之和不小于至少一路第一数据的速率之和，进而能够以较高的速率进行数据传输。本申请实施例提供的方法可适用于端到端(end-to-end)前向纠错(forward error correction，FEC)架构、分段式(segment-by-segment)架构和级联式(concatenated)FEC架构中的任一种FEC架构。并且，对于分段式FEC架构和级联式FEC架构，本申请实施例的方法可复用当前的模块，以节约光纤、模块和器件开销。
图1示出了本申请实施例提供的一种数据传输的方法的实施场景，该实施场景包括多个模块，各个模块之间能够进行信息的交互，实现数据的传输。如图1所示，第一模块101与第二模块102之间，第一模块101与第三模块103之间均可以进行数据的传输。需要说明的是，如图1所示的实施场景可以包括N个模块，N为大于等于2的正整数，图1中仅以模块数量为3个为例进行说明。此外，各个模块可以位于同一芯片内，也可以位于不同芯片内。
结合图1所示的实施场景，本申请实施例提供的数据传输的方法如图2所示，包括但不限于S201至S203。
S201，第一模块获取至少一路第一数据，第一数据为采用第一FEC码型编码的数据。
本申请实施例不对第一数据的速率进行限定，在一些实施例中，第一数据的速率为50千兆比特/秒(gigabit per second，Gb/s)、100Gb/s、200Gb/s、400Gb/s、800Gb/s、1.6太比特/秒(terabit per second，Tb/s)、3.2Tb/s、6.4Tb/s或其他非标速率中的任一种。示例性地，在第一数据为多路的情况下，多路第一数据的速率可以相同或不同。例如，如图3所示，第一模块获取四路第一数据，该四路第一数据的速率均为200GE。又例如，如图4所示，第一模块获 取四路第一数据，该四路第一数据的速率分别为100GE，100GE，200GE和400GE。
此外，至少一路第一数据为采用相同或不同的第一FEC码型编码的数据。本申请实施例不对第一FEC码型进行限定，示例性地，第一FEC码型为里德-所罗门(Reed-Solomon，RS)码、博斯-乔赫里-霍克文黑姆(Bose-Chaudhuri-Hocquenghem，BCH)码、法尔(fire)码、涡轮(turbo)码、涡轮乘积码(turbo product code，TPC)、阶梯(staircase)码以及低密度奇偶校验(low-density parity-check，LDPC)码中的任一种。
本申请实施例不对第一模块获取至少一路第一数据的方式进行限定，示例性地，第一模块与第二模块能够进行数据的传输，第一模块接收第二模块发送的至少一路第一数据。例如，第一模块位于第一芯片，第二模块位于第二芯片，第一模块接收第二模块发送的至少一路第一数据，包括但不限于第一模块接收第二模块通过附件单元接口(attachment unit interface，AUI)的通道发送的第一数据。
第一数据除了采用第一FEC码型编码外，还可经过其他处理。本申请实施例不对第一数据除了第一FEC码型编码之外的其他处理的处理方式进行限定。例如，该第一数据为采用第一FEC码型编码且经过物理介质接入子层(physical medium attachment sublayer，PMA)分发的数据，或者，该第一数据为采用第一FEC码型编码且经过交织处理及PMA分发的数据等。
S202，第一模块对至少一路第一数据进行转化处理，得到至少一路第二数据，至少一路第二数据的速率之和不小于至少一路第一数据的速率之和。
本申请实施例不对第二数据的速率进行限定，为了实现以更高速率传输数据，转化得到的第二数据的速率之和不小于转化前的第一数据的速率之和，也即转化前的所有第一数据的速率之和不大于转化后的所有第二数据的速率之和。在一些实施例中，第二数据的速率为400Gb/s、800Gb/s、1.6Tb/s、3.2Tb/s、6.4Tb/s或其他非标速率中的任一种。示例性地，在第二数据为多路的情况下，多路第二数据的速率可以相同或不同。
示例性地，第一模块对至少一路第一数据进行转化处理，得到至少一路第二数据包括但不限于如下三种情况。
情况一，针对segment-by-segment的FEC架构，第一模块对至少一路第一数据进行转化处理，得到至少一路第二数据包括：第一模块对至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；对多个第一码字进行解码，根据解码结果获取至少一路第二数据。
示例性地，第一模块对至少一路第一数据进行对齐，包括但不限于对至少一路第一数据分别进行对齐。例如，第一模块将至少一路第一数据各自转换为至少一路第一子数据，对于属于同一路第一数据的至少一路第一子数据进行对齐。
在一些实施例中，第一数据包括对齐标志(alignment marker，AM)，该AM用于对至少一路第一数据进行对齐。例如，针对第一数据包括AM的情况，对至少一路第一数据进行对齐包括但不限于AM锁定和去偏斜。其中，AM锁定用于寻找码字边界，也即对至少一路第一数据进行对齐，寻找到码字边界后，即可按照标准，比如电气与电子工程师协会(Institute of Electrical and Electronics Engineers，IEEE)802.3的各个版本或未来版本，定义的方式进行去偏斜，进而获得多个第一码字。在一些实施例中，第一模块对至少一路第一数据进行对齐包括：第一模块将至少一路第一数据转换为至少一路第一子数据，对至少一路第一子数据进行AM锁定和去偏斜。示例性地，对至少一路第一数据进行对齐可参照图5和图6示出的AM锁定/去偏斜步骤。
示例性地，对于至少一路第一数据进行对齐的对齐结果包括至少一个第一码字序列，一个第一码字序列对应一路第一数据。示例性地，在至少一路第一数据为未经过交织的数据的情况下，根据对齐结果获取多个第一码字，包括但不限于对于至少一个第一码字序列中的各个第一码字序列，按照码长间隔得到多个第一码字。示例性地，在至少一路第一数据为经过交织的数据的情况下，根据对齐结果获取多个第一码字，包括但不限于对对齐结果进行解交织(de-interleave)，根据解交织结果得到多个第一码字。例如，对于至少一个第一码字序列中的各个第一码字序列进行解交织，根据解交织结果得到多个第一码字。关于至少一路第一数据的交织方式，本申请对此不加以限定。例如，至少一路第一数据的交织方式包括但不限于码字交织或通道(lane)间交织的至少一种。对对齐结果进行解交织时，根据至少一路第一数据的交织方式进行对应的解交织。示例性地，该获取多个第一码字的步骤可参照图5和图6示出获取FEC1(第一FEC码型)码字的步骤。
在获取多个第一码字后，第一模块对多个第一码字进行解码，得到解码结果。例如，如图5和图6示出的FEC1解码步骤。在一些实施例中，对多个第一码字进行解码，得到解码结果包括但不限于对多个第一码字进行解码，丢弃多个第一码字的校验位，得到解码结果。也就是说，解码结果可以包括多个第一码字的信息位且不包括多个第一码字的校验位。示例性地，第一模块对多个第一码字进行解码时，按照第一FEC码型对多个第一码字进行解码。
在一些实施例中，根据解码结果获取至少一路第二数据，包括但不限于S1-1和S1-2。
S1-1，按照第二FEC码型对解码结果进行编码，得到多个第二码字。
本申请实施例不对第二FEC码型进行限定，示例性地，第二FEC码型为RS码、BCH码、法尔码、涡轮码、涡轮乘积码、阶梯码以及LDPC码中的任一种。示例性地，该解码结果包括分别基于各路第一数据得到的解码结果，按照第二FEC码型对解码结果进行编码时，对于基于不同第一数据得到的解码结果，可以采用相同或不同的第二FEC码型进行编码，本申请实施例对此不加以限定。
在一些实施例中，在第一数据包括AM的情况下，按照第二FEC码型对解码结果进行编码，得到多个第二码字，包括：删除解码结果中的AM，按照第二FEC码型对删除AM之后的解码结果进行编码，得到多个第二码字。关于删除解码结果中的AM的方式，本申请实施例对此不加以限定，例如，在通过AM锁定获得码字边界时，得到了AM的位置，从而可根据AM的位置对AM进行删除。
在一些实施例中，根据解码结果获取至少一路第二数据，包括：标记解码结果包括的多个码块中的错误码块，根据标记后的解码结果获取至少一路第二数据。在一种可能的实现方式中，将解码结果包括的多个码块进行反转码，标记反转码得到的多个码块中的错误码块，根据该标记了错误码块的多个码块获取至少一路第二数据。例如，如图7和图8所示，解码结果包括n个257比特(bit)码块流，将该多个257比特(bit)码块流进行反转码获得n个66bit码块流，标记n个66bit码块流中的错误码块，根据该标记了错误码块的n个66bit码块流获取至少一路第二数据。
在另一种可能的实现方式中，将解码结果包括的多个码块进行反转码，标记反转码得到的多个码块中的错误码块，将该标记了错误码块的多个码块进行转码，根据转码得到的多个码块获取至少一路第二数据。例如，如图9和图10所示，解码结果包括n个257比特(bit)码块流，将该n个257比特(bit)码块流进行反转码获得n个66bit码块流，标记n个66bit 码块流中的错误码块，将该标记了错误码块的n个66bit码块流进行转码获得n个257bit码块流，根据该n个257bit码块流获取至少一路第二数据。
可选地，对错误码块进行标记的操作可以在删除AM之后的解码结果的基础上执行。也即，对解码结果中的AM进行删除之后，对该删除AM之后的解码结果中的错误码块进行标记，根据删除AM且标记了错误码块后的解码结果获取至少一路第二数据。通过对错误码块进行标记，以应对AUI传输、系统噪声等引入的误码。
示例性地，按照第二FEC码型对删除AM之后的解码结果进行编码，得到多个第二码字，包括但不限于如下两种方式。
得到多个第二码字的方式一，将删除AM之后的解码结果以依次发送的方式合并成一路第三数据，对一路第三数据进行编码，得到多个第二码字。
由于采用依次发送的方式将删除AM之后的解码结果合并成一路第三数据，该第三数据中包括的基于各路第一数据的删除AM之后的解码结果可以周期性出现。例如，删除AM之后的解码结果包括n个257bit码块流，将该n个257bit码块流进行依次发送，使合并得到的一路第三数据中属于该n个257bit码块流的数据周期性出现。本申请实施例对于依次发送的粒度不加以限定，包括但不限于5440-bit，5140-bit，257-bit，66-bit，10-bit，2-bit或1-bit。
示例性地，针对删除AM之后包括对应于多路第一数据的删除AM之后的解码结果的情况，将对应于各路第一数据的删除AM之后的解码结果依次发送，合并成一路第三数据。例如，删除AM之后的解码结果包括四个码块流，分别为码块流A、码块流B、码块流C和码块流D，其中，码块流A包括码块A.1、A.2、A.3、A.4、A.5、A.6、A.7等等，码块流B包括码块B.1、B.2、B.3、B.4、B.5、B.6、B.7等等，码块流C包括码块C.1、C.2、C.3、C.4、C.5、C.6、C.7等等，码块流D包括码块D.1、D.2、D.3、D.4、D.5、D.6、D.7等等。则在一些实施例中，将删除AM之后的解码结果以依次发送的方式合并成一路第三数据时，该路第三数据中包括的各个码块流的码块情况如图11的(a)所示，第三数据包括的码块的顺序为A.1、B.1、C.1、D.1、A.2、B.2、C.2、D.2、A.3等等。
在一些实施例中，将删除AM之后的解码结果以依次发送的方式合并成一路第三数据，包括但不限于：将删除AM之后的解码结果以依次发送的方式合并成一路参考速率的第三数据。例如，响应于获取的第一数据的速率之和小于参考速率，将删除AM之后的解码结果与第一参考数据合并成一路参考速率的第三数据。以获取的第一数据速率之和为400GE，参考速率为800GE为例，则将删除AM之后的解码结果与400GE的第一参考数据合并成一路800GE的第三数据，第一参考数据可以为空闲(idle)数据，可以基于应用场景设置，本申请实施例不对第一参考数据的内容进行限定。其中，参考速率可以根据经验或实际需求进行设置，本申请实施例对此不加以限定。关于将删除AM之后的解码结果与第一参考数据合并成一路参考速率的第三数据的方式，本申请实施例也不加以限定。例如，将删除AM之后的解码结果和第一参考数据以依次发送的方式合并成一路参考速率的第三数据，或将删除AM之后的解码结果进行合并，将合并后的数据与第一参考数据以依次发送的方式合并成一路参考速率的第三数据。
在一些实施例中，针对删除AM之后包括对应于多路第一数据的删除AM之后的解码结果的情况，将删除AM之后的解码结果以依次发送的方式合并成一路参考速率的第三数据，包括：将对应于各路第一数据的删除AM之后的解码结果和填充数据块依次发送，合并成一 路第三数据。例如，仍以删除AM之后的解码结果包括码块流A、码块流B、码块流C和码块流D为例，填充数据块可以是无意义的数据，比如伪随机二进制序列(pseudo-random binary sequence，PRBS)数据，也可以是有意义的开销，本申请实施例不对填充数据块的内容进行限定，可基于应用场景灵活设置。在一些实施例中，将删除AM之后的解码结果和填充数据块以依次发送的方式合并成一路第三数据时，该路第三数据中包括的各个码块流的码块情况如图11的(b)所示，第三数据包括的码块的顺序为A.1、B.1、C.1、D.1、A.2、填充数据块、B.2、C.2、D.2、A.3等等。
在一些实施例中，将删除AM之后的解码结果以依次发送的方式合并成一路第三数据，包括但不限于将删除AM之后的解码结果进行交织，对交织后的删除AM之后的解码结果以依次发送的方式合并成一路第三数据。本申请不对删除AM之后的解码结果的交织方式加以限定。示例性地，该将删除AM之后的解码结果合并成一路第三数据的方式可参照图5示出的数据交织与分发的步骤。
示例性地，对一路第三数据进行编码，得到多个第二码字，包括但不限于：按照第二FEC码型对一路第三数据进行整体编码，得到多个第二码字；或者，将一路第三数据转化为至少两路第五数据，按照第二FEC码型对至少两路第五数据分别进行编码，得到多个第二码字，其中，第五数据的速率小于第三数据的速率。例如，第三数据为一路800GE的数据，按照第二FEC码型对该第三数据进行整体编码，得到多个第二码字；或者，将该第三数据转化为两路400GE的第五数据，按照第二FEC码型对该两路第五数据分别进行编码，得到多个第二码字。示例性地，整体编码用于将待编码的数据作为一路数据进行编码。本申请不对将一路第三数据转化为至少两路第五数据的方式加以限定，例如，将一路第三数据以依次发送的方式转化为至少两路第五数据。该对一路第三数据进行编码，得到多个第二码字的步骤可参照图5示出的FEC2(第二FEC码型)编码及处理步骤。
其中，整体编码是指将多路数据合并为一路数据进行编码，或者说整体编码用于将待编码的数据作为一路数据进行编码。因此，按照第二FEC码型对一路第三数据进行整体编码，是指将一路第三数据作为一路数据进行编码。
得到多个第二码字的方式二，将删除AM之后的解码结果转换成至少两路第三数据，对至少两路第三数据进行编码，得到多个第二码字。
示例性地，第三数据的速率可以为参考速率，第三数据的路数和参考速率可以根据经验或实际需求进行设置，本申请实施例不加以限定。在一些实施例中，将删除AM之后的解码结果以依次发送的方式转换成至少两路第三数据。示例性地，将删除AM之后的解码结果转换成至少两路第三数据，包括但不限于将删除AM之后的解码结果进行交织，将交织后的删除AM之后的解码结果转换成至少两路第三数据。本申请不对删除AM之后的解码结果的交织方式加以限定。示例性地，该将删除AM之后的解码结果转换成至少两路第三数据的方式可参照图6示出的数据交织与分发的步骤。
示例性地，在至少一路第一数据的速率之和小于至少两路第三数据的速率之和的情况下，将删除AM之后的解码结果与第二参考数据共同转换成至少两路参考速率的第三数据。例如，获取的四路第一数据的速率为400GE、400GE、400GE和200GE，参考速率为800GE，将删除AM之后的解码结果与200GE的第二参考数据共同转换成两路800GE的第三数据。又例如，获取的一路第一数据的速率为1.6TE，参考速率为800GE，将删除AM之后的解码结果 与1.6TE的第二参考数据共同转换成四路800GE的第三数据。第二参考数据可以为空闲(idle)数据，可以基于应用场景设置，本申请实施例不对第二参考数据的内容进行限定。示例性地，该第二参考数据可以包括多个填充数据块，本申请实施例不对至少两路第三数据中各路第三数据包括的填充数据块的情况加以限定。
示例性地，在至少一路第一数据的速率之和等于至少两路第三数据的速率之和的情况下，将删除AM之后的解码结果转换成至少两路第三数据。例如，如图12所示，获取的四路第一数据的速率均为400GE，将删除AM之后的解码结果转换成两路速率为800GE的第三数据。又例如，如图13所示，获取的一路第一数据的速率为1.6TE，将删除AM之后的解码结果转换成两路800GE的第三数据。
在一些实施例中，针对第一数据的路数为多路的情况，对于至少两路第三数据中的任一路第三数据，该任一路第三数据可以仅包括部分第一数据的删除AM之后的解码结果，或包括每路第一数据的删除AM之后的解码结果。例如，仍以删除AM之后的解码结果包括码块流A、码块流B、码块流C和码块流D为例。在一些实施例中，将删除AM之后的解码结果以依次发送的方式合并成两路第三数据时，两路第三数据中包括的各个码块流的码块情况如图11的(c)所示，一路第三数据包括的码块的顺序为A.1、C.1、A.2、C2、A.3、C.3、A.4、C.4、A.5等等，另一路第三数据包括的码块的顺序为B.1、D.1、B.2、D.2、B.3、D.3、B.4、D.4、B.5等等。需要说明的是，图11的(c)仅是将码块流A和码块流C合并到一路第三数据，而码块流B和码块流D合并成一路第三数据为例进行举例说明，但并不用于限制实现方式，每一路第三数据可以是任选两条码块流汇聚成的。
在另一些实施例中，将删除AM之后的解码结果以依次发送的方式合并成两路第三数据时，两路第三数据中包括的各个码块流的码块情况如图11的(d)所示，一路第三数据包括的码块的顺序为A.1、B.1、C.1、D.1、A.3、B.3、C.3、D.3、C5、A.5等等，另一路第三数据包括的码块的顺序为A.2、B.2、C2、D.2、A.4、B.4、C.4、D.4、B.6等等。
此外，上述图11的(a)、(c)和(d)所示的方式在合并得到第三数据的过程中，也可以包括将填充数据块与待合并的数据依次发送，具体过程可参考图11的(b)的方式，此处不再一一赘述。可选地，填充数据块不一定是周期发送，也可以采用不同间隔发送，例如间隔一定数量个数据之后发送一个填充数据块，或者间隔一定数量个数据之后插入多个填充数据块。
示例性地，将删除AM之后的解码结果转换成至少两路第三数据，包括：将删除AM之后的解码结果合并成一路第四数据，将一路第四数据转换成至少两路第三数据。例如，获取的四路第一数据均为400GE的数据，将删除AM之后的解码结果合并成一路1.6TE的第四数据，将该一路1.6TE的第四数据转换成两路800GE的第三数据。
对至少两路第三数据进行编码时，也可以采用整体编码或分别编码的方式。示例性地，对至少两路第三数据进行编码，得到多个第二码字，包括：按照第二FEC码型对至少两路第三数据进行整体编码，得到多个第二码字；或者按照第二FEC码型对至少两路第三数据分别进行编码，得到多个第二码字。该对至少两路第三数据进行编码，得到多个第二码字的步骤可参照图6示出的FEC2(第二FEC码型)编码及处理步骤。
在一些实施例中，按照第二FEC码型对至少两路第三数据分别进行编码，得到多个第二码字，包括：按照第二FEC码型对至少两路第三数据分别进行整体编码，得到多个第二码字； 或者，将至少两路第三数据各自转换成至少两路第六数据，按照第二FEC码型对至少两路第六数据分别进行编码，得到多个第二码字，其中，第六数据的速率小于第三数据的速率。关于将至少两路第三数据各自转换成至少两路第六数据，按照第二FEC码型对至少两路第六数据分别进行编码的过程与上述得到多个第二码字的方式一中将一路第三数据转化为至少两路第五数据，按照第二FEC码型对至少两路第五数据分别进行编码的相关过程原理相同，此处不再赘述。其中，整体编码是指将多路数据合并为一路数据进行编码，或者说整体编码用于将待编码的数据作为一路数据进行编码。因此，按照第二FEC码型对至少两路第三数据进行整体编码，是指将至少两路第三数据中的所有第三数据作为一路数据进行编码。
本申请实施例提供的方法能够采用不同的方式对第三数据进行编码，以得到多个第二码字，从而该方法适用的传输场景和传输要求较为灵活。此外，在第三数据的路数为多路的情况下，第三数据的路数以及对第三数据编码所采用的第二FEC码型可以进行灵活设置，以适用于不同的传输场景和传输需求。
S1-2，根据多个第二码字得到至少一路第二数据。
示例性地，根据多个第二码字得到至少一路第二数据包括但不限于对多个第二码字进行交织，根据交织结果得到至少一路第二数据。关于对多个第二码字进行交织的方式，本申请实施例不加以限定，例如，对多个第二码字进行码字交织或lane间交织的至少一种。
情况二，第一模块对至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；根据多个第一码字得到至少一路第二数据。
其中，第一模块对至少一路第一数据进行对齐，根据对齐结果获取多个第一码字的方式与上述方式一中的相关过程原理相同，此处不再赘述。
示例性地，根据多个第一码字得到至少一路第二数据，包括：对多个第一码字进行合并，根据合并结果得到至少一路第二数据。例如，对多个第一码字进行合并，根据合并结果得到至少一路第二数据，包括但不限于如下两种方式。
合并方式一，将多个第一码字以依次发送的方式合并成一路第二数据。
由于采用依次发送的方式将多个第一码字合并成一路第二数据，该第二数据中包括的基于各路第一数据得到的多个第一码字可以周期性出现。其中，将多个第一码字以依次发送的方式合并成一路第二数据的方式与上述将删除AM之后的解码结果以依次发送的方式合并成一路第三数据的相关过程原理相同，此处不再赘述。
合并方式二，将多个第一码字合并成至少两路第二数据。
示例性地，将多个第一码字合并成至少两路第二数据的方式与上述将删除AM之后的解码结果转换成至少两路第三数据的相关过程原理相同，此处不再赘述。
需要说明的是，无论是上述哪种合并方式，该第二数据可以为经过交织的数据，本申请实施例不对交织的方式加以限定。
情况三，第一模块按照第二FEC码型对至少一路第一数据进行编码，得到多个第三码字；第一模块根据多个第三码字得到至少一路第二数据。
示例性地，第一模块按照第二FEC码型对至少一路第一数据进行编码，得到多个第三码字，包括但不限于如下两种方式。
得到多个第三码字的方式一，将至少一路第一数据以依次发送的方式合并成一路第七数据，对一路第七数据进行编码，得到多个第三码字。
在一些实施例中，将至少一路第一数据以依次发送的方式合并成一路第七数据，包括但不限于第一模块对至少一路第一数据进行对齐，根据对齐结果得到多个第一码字，将多个第一码字以依次发送的方式合并成一路第七数据。本申请实施例对于依次发送的粒度不加以限定，包括但不限于5440-bit，5140-bit，257-bit，66-bit，10-bit，2-bit或1-bit。关于第一模块对至少一路第一数据进行对齐，根据对齐结果得到多个第一码字的方式与上述方式一中的相关过程原理相同，此处不再赘述。
在一些实施例中，将至少一路第一数据以依次发送的方式合并成一路第七数据，包括但不限于：将至少一路第一数据以依次发送的方式合并成一路参考速率的第七数据。例如，响应于获取的第一数据的速率之和小于参考速率，将至少一路第一数据与第三参考数据合并成一路参考速率的第七数据。以获取的第一数据速率之和为400GE，参考速率为800GE为例，则将至少一路第一数据与400GE的第三参考数据合并成一路800GE的第七数据，第三参考数据可以为空闲(idle)数据，本申请实施例不对第三参考数据的内容进行限定，例如基于应用场景确定第三参考数据。需要说明的是，参考速率可以根据经验或实际需求进行设置，本申请实施例对此不加以限定。关于将至少一路第一数据与第三参考数据合并成一路参考速率的第七数据的方式，本申请实施例也不加以限定。例如，将至少一路第一数据和第三参考数据以依次发送的方式合并成一路参考速率的第七数据，或将至少一路第一数据进行合并，将合并后的数据与第三参考数据以依次发送的方式合并成一路参考速率的第七数据。
示例性地，对一路第七数据进行编码，得到多个第三码字，包括但不限于：按照第二FEC码型对一路第七数据进行整体编码，得到多个第三码字；或者，将一路第七数据转化为至少两路第九数据，按照第二FEC码型对至少两路第九数据分别进行编码，得到多个第三码字，其中，第九数据的速率小于第七数据的速率。例如，第七数据为一路800GE的数据，按照第二FEC码型对该第七数据进行整体编码，得到多个第三码字；或者，将该第七数据转化为两路400GE的第九数据，按照第二FEC码型对该两路第九数据分别进行编码，得到多个第三码字。示例性地，整体编码用于将待编码的数据作为一路数据进行编码。本申请不对将一路第七数据转化为至少两路第九数据的方式加以限定，例如，将一路第一数据以依次发送的方式转化为至少两路第九数据。
得到多个第三码字的方式二，将至少一路第一数据转换成至少两路第七数据，对至少两路第七数据进行编码，得到多个第三码字。
示例性地，第七数据的速率可以为参考速率，第七数据的路数和参考速率可以根据经验或实际需求进行设置，本申请实施例不加以限定。在一些实施例中，将至少一路第一数据以依次发送的方式转换成至少两路第七数据。
示例性地，在至少一路第一数据的速率之和小于至少两路第七数据的速率之和的情况下，将至少一路第一数据与第四参考数据共同转换成至少两路参考速率的第七数据。例如，获取的四路第一数据的速率为400GE、400GE、400GE和200GE，参考速率为800GE，将至少一路第一数据与200GE的第四参考数据共同转换成两路800GE的第七数据。又例如，获取的一路第一数据的速率为1.6TE，参考速率为800GE，将至少一路第一数据与1.6TE的第四参考数据共同转换成四路800GE的第七数据。
示例性地，在至少一路第一数据的速率之和等于至少两路第七数据的速率之和的情况下，将至少一路第一数据转换成至少两路第七数据。
在一些实施例中，针对第一数据的路数为多路的情况，对于至少两路第七数据中的任一路第七数据，该任一路第七数据可以仅包括部分第一数据的数据或包括每路第一数据的数据。
示例性地，将至少一路第一数据转换成至少两路第七数据，包括：将至少一路第一数据合并成一路第八数据，将一路第八数据转换成至少两路第七数据。例如，获取的四路第一数据均为400GE的数据，将该四路第一数据合并成一路1.6TE的第八数据，将该一路1.6TE的第八数据转换成两路800GE的第七数据。
对至少两路第七数据进行编码时，也可以采用整体编码或分别编码的方式。示例性地，对至少两路第七数据进行编码，得到多个第三码字，包括：按照第二FEC码型对至少两路第七数据进行整体编码，得到多个第三码字；或者按照第二FEC码型对至少两路第七数据分别进行编码，得到多个第三码字。
在一些实施例中，按照第二FEC码型对至少两路第七数据分别进行编码，得到多个第三码字，包括：按照第二FEC码型对至少两路第七数据分别进行整体编码，得到多个第三码字；或者，将至少两路第七数据各自转换成至少两路第十数据，按照第二FEC码型对至少两路第十数据分别进行编码，得到多个第三码字，其中，第十数据的速率小于第七数据的速率。关于将至少两路第七数据各自转换成至少两路第十数据，按照第二FEC码型对至少两路第十数据分别进行编码的过程与上述得到多个第三码字的方式一中将一路第七数据转化为至少两路第九数据，按照第二FEC码型对至少两路第九数据分别进行编码的相关过程原理相同，此处不再赘述。
示例性地，根据多个第三码字得到至少一路第二数据包括但不限于对多个第三码字进行交织，根据交织结果得到至少一路第二数据。关于对多个第三码字进行交织的方式，本申请实施例不加以限定，例如，对多个第三码字进行码字交织或lane间交织的至少一种。
本申请实施例提供的方法能够采用不同的方式对第七数据进行编码，以得到多个第三码字，从而该方法适用的传输场景和传输要求较为灵活。此外，在第七数据的路数为多路的情况下，第七数据的路数以及对第七数据编码所采用的第二FEC码型可以进行灵活设置，以适用于不同的传输场景和传输需求。
S203，第一模块传输至少一路第二数据。
示例性地，第一模块传输至少一路第二数据，包括：第一模块将同步数据插入至少一路第二数据，传输插入同步数据后的数据。其中，同步数据包括但不限于AM、相干数字信号处理(digital signal processing，DSP)帧头、训练符号或导频符号中的至少一种。
在一些实施例中，第一模块将同步数据插入至少一路第二数据，包括：确定至少一路第二数据中的各路第二数据对应的AM；将各路第二数据对应的AM作为同步数据插入各路第二数据。示例性地，各路第二数据对应的AM通过调整对应的第一数据包括的AM得到；或者，各路第二数据对应的AM为对应的第一数据包括的AM中的全部内容；或者，各路第二数据对应的AM为对应的第一数据包括的AM中的部分内容。其中，调整对应的第一数据包括的AM包括但不限于按照不同粒度调整AM内容或长度。
在一些实施例中，在获取的第一数据为多路第一数据的情况下，可以将多路第一数据中任一路第一数据包括的AM作为任一路第二数据对应的AM。需要说明的是，各路第二数据对应的AM可以相同或不同，例如，可以根据实际需求，分别确定各路第二数据的AM。
示例性地，第一模块传输至少一路第二数据时还可以进行其他处理，例如对至少一路第 二数据进行复用(mux)、训练序列(training sequence，TS)/导频符号(pilot symbol)插入、频点调整、光调制等处理，传输处理后的至少一路第二数据。例如，如图5和图6示出的调制输出步骤。无论第一模块传输的数据为插入同步数据之后的数据，或经过其他处理的数据，该第一模块传输数据时采用的复用粒度包括但不限于FEC码字(codeword)，257-bit，66-bit，10-bit或1-bit，本申请实施例对此不加以限定。
本申请实施例提供的方法，通过对至少一路第一数据进行转化处理，得到速率之和不小于至少一路第一数据的速率之和的至少一路第二数据，进而能够以较高的速率进行数据传输。另外，由于第一模块可以将获取的采用第一FEC码型编码的第一数据通过第二FEC码型进行再一次编码，第二数据具有更高的编码增益，在容易出现误码的通道中传输时，能够对出现误码的数据进行有效的纠错，从而提高数据传输的质量。
接下来，结合上述图2所示的方法流程，以第一模块位于第一芯片，第二模块位于第二芯片，针对如下几种场景为例，对本申请实施例提供的数据传输方法进行举例说明。
场景一，第一芯片和第二芯片应用于分段式FEC架构。
示例性地，该场景一对应图2所示的实施例中的情况一。该场景的实施环境可如图14所示，数据传输的过程如下。
第二芯片通过AUI向第一芯片传输八路第一数据，第一数据的媒体接入控制(media access control，MAC)速率均为100Gb/s，且第一数据均为采用RS(544，514)FEC码型编码的数据。第二芯片通过一条AUI传输一路第一数据，传输速率为106.25Gb/s。第一芯片包括八个处理单元，每个处理单元用于处理一路第一数据。第一芯片接收到该八路第一数据后，分别对各路第一数据进行AM锁定，以将第一数据进行对齐，得到多个第一码字。由于该第一数据为采用RS(544，514)FEC码型编码的数据，该多个第一码字为RS(544，514)FEC码型编码的码字。示例性地，在第一数据为经过交织得到的数据的情况下，第一芯片对第一数据进行AM锁定，得到对齐结果后，对对齐结果进行解交织，根据解交织得到多个第一码字。第一芯片得到多个第一码字后，对该多个第一码字进行解码。在一种可能的实现方式中，第一芯片对解码结果进行交织，根据交织后的解码结果得到至少一路第二数据。第一芯片得到解码结果后，删除解码结果中的AM，其中，该AM可以用于确定至少一路第二数据中的各路第二数据对应的AM。需要说明的是，第一芯片对于各路第一数据的处理可以同时执行或先执行对某一路第一数据的处理再执行对其他路第一数据的处理，本申请实施例对此不加以限定。
进一步地，第一芯片将删除AM后的解码结果进行数据合并。例如，将删除AM之后的解码结果以依次发送的方式合并成一路800GE的第三数据，或将删除AM之后的解码结果转换成至少两路800GE的第三数据。第一芯片对该第三数据进行数据处理，例如，对第三数据进行编码，得到多个第二码字，根据多个第二码字得到至少一路第二数据。
最后，第一芯片将AM作为同步数据插入至少一路第二数据；对插入同步数据后的数据进行发送端(transmitter，TX)DSP，得到800G相干光。
在另一种可能的实现方式中，该场景的实施环境如图15所示，数据传输的过程如下。
第二芯片通过AUI向第一芯片传输一路第一数据，第一数据的MAC速率为1.6Tb/s，且第一数据为2xRS(544，514)FEC码型编码交织的数据。第二芯片通过16条AUI传输一路 第一数据，其中，一条AUI用于一路第一子数据，传输速率为106.25Gb/s。第一芯片接收到该第一数据后，对第一数据进行AM锁定/去偏斜，以将第一数据进行对齐，得到多个第一码字。由于该第一数据为采用RS(544，514)FEC码型编码的数据，该多个第一码字为RS(544，514)FEC码型编码的码字。示例性地，在第一数据为经过交织得到的数据的情况下，第一芯片对第一数据进行AM锁定，得到对齐结果后，对对齐结果进行解交织，根据解交织得到多个第一码字。第一芯片得到多个第一码字后，对该多个第一码字进行解码。在一种可能的实现方式中，第一芯片对解码结果进行交织，根据交织后的解码结果得到至少一路第二数据。第一芯片得到解码结果后，删除解码结果中的AM，其中，该AM可以用于确定至少一路第二数据中的各路第二数据对应的AM。
进一步地，第一芯片将删除AM后的解码结果进行数据分发。例如，将删除AM之后的解码结果转换成两路800GE的第三数据。第一芯片对该两路第三数据进行数据处理，例如，对两路第三数据进行编码，得到多个第二码字，根据多个第二码字得到两路第二数据。需要说明的是，对两路第三数据的处理可以相同或不同。
之后，第一芯片将AM作为同步数据插入两路第二数据；对插入同步数据后的数据进行TX DSP，得到两路800G相干光。其中，对两路第二数据的处理可以相同或不同，从而得到的两路800G相干光的波长可以相同或不同。
场景二，第一芯片和第二芯片应用于端到端FEC架构。
示例性地，该场景二对应图2所示的实施例中的情况二。该场景的实施环境如图16所示，数据传输的过程如下。
第二芯片通过AUI向第一芯片传输八路第一数据，第一数据的MAC速率均为100Gb/s，且第一数据均为采用RS(544，514)FEC码型编码的数据。第二芯片通过一条AUI传输一路第一数据，传输速率为106.25Gb/s。第一芯片包括八个处理单元，每个处理单元用于处理一路第一数据。第一芯片接收到该八路第一数据后，分别对各路第一数据进行AM锁定，以将第一数据进行对齐，得到多个第一码字。由于第一数据为采用RS(544，514)FEC码型编码的数据，多个第一码字为RS(544，514)FEC码型编码的码字。示例性地，在第一数据为经过交织得到的数据的情况下，第一芯片对第一数据进行AM锁定，得到对齐结果后，对对齐结果进行解交织，根据解交织得到多个第一码字。第一芯片对于各路第一数据的处理可以同时执行或先执行对某一路第一数据的处理再执行对其他路第一数据的处理，本申请实施例不加以限定。
进一步地，第一芯片将多个第一码字进行数据合并。例如，多个第一码字以依次发送的方式合并成一路800GE的第二数据，或将多个第一码字转换成至少两路800GE的第二数据。示例性地，第二数据可以为经过数据处理的数据，例如，第二数据为经过交织的数据。最后，第一芯片对至少一路第二数据进行TX DSP，得到800G相干光。
场景三，第一芯片和第二芯片应用于级联式FEC架构。
示例性地，该场景三对应图2所示的实施例中的情况三。该场景的实施环境如图17所示，数据传输的过程如下。
第二芯片通过AUI向第一芯片传输八路第一数据，第一数据的MAC速率均为100Gb/s，且第一数据均为采用RS(544，514)FEC码型编码的数据。第二芯片通过一条AUI传输一路第一数据，传输速率为106.25Gb/s。第一芯片包括八个处理单元，每个处理单元用于处理 一路第一数据。第一芯片接收到该八路第一数据后，分别对各路第一数据进行AM锁定，以将第一数据进行对齐，得到多个第一码字。由于该第一数据为采用RS(544，514)FEC码型编码的数据，该多个第一码字为RS(544，514)FEC码型编码的码字。示例性地，在第一数据为经过交织得到的数据的情况下，第一芯片对第一数据进行AM锁定，得到对齐结果后，对对齐结果进行解交织，根据解交织得到多个第一码字。示例性地，第一芯片还可以将得到的多个第一码字进行交织，得到经过交织的多个第一码字。第一芯片对于各路第一数据的处理可以同时执行或先执行对某一路第一数据的处理再执行对其他路第一数据的处理，本申请实施例不加以限定。
进一步地，第一芯片将基于各路第一数据得到的多个第一码字进行数据合并。例如，将多个第一码字合并成一路800GE的第七数据，或将多个第一码字转换成至少两路800GE的第七数据。第一芯片对该第七数据进行数据处理，例如，对第七数据进行编码，得到多个第三码字，根据多个第三码字得到至少一路第二数据。
之后，第一芯片对至少一路第二数据进行TX DSP，得到800G相干光。
以上以第一模块为例，对数据传输的方法进行了说明，接下来，以第一模块传输至少一路第二数据之后，第三模块对数据传输的过程进行说明。如图18所示，该数据传输的方法包括如下几个步骤。
S1801，第三模块获取至少一路第二数据，至少一路第二数据为对至少一路第一数据进行转化处理得到的数据，至少一路第二数据的速率之和不小于至少一路第一数据的速率之和，第一数据为采用第一FEC码型编码的数据。
结合图1所示的实施环境，第三模块获取第一模块发送的至少一路第二数据。结合图2所示的实施例，第一模块得到至少一路第二数据的方式有多种，本申请实施例在此不再一一赘述，可参见上述图2所示实施例的内容。
S1802，第三模块对至少一路第二数据进行转化处理，得到至少一路第一数据。
由于第一模块得到至少一路第二数据的方式有多种，因而第二数据的情况也有多种，针对第二数据的不同情况，第三模块可采用不同的情况进行处理。例如，针对第二数据为采用第二FEC码型编码的数据的情况，第三模块按照第二FEC码型对第二数据进行解码，得到解码后的数据。
之后，第三模块还可以对解码后的数据进行进一步的处理，本申请实施例不对第三模块对第二数据的处理方式进行限定。例如，将解码后的数据继续向其他模块发送。另外，第三模块可以位于第三芯片中，第一模块位于第一芯片中，第三模块接收第一模块通过AUI发送的至少一路第二数据。
本申请实施例提供的方法，通过对至少一路第二数据进行转化处理，得到速率之和不大于至少一路第二数据的速率之和的至少一路第一数据，进而能够以较高的速率进行数据传输。另外，由于第二数据可以是采用第一FEC码型和第二FEC码型编码的数据，因而通过第二FEC码型进行解码，在容易出现误码的通道中传输时，能够对出现误码的数据进行有效的纠错，从而提高数据传输的质量。
本申请实施例还提供了一种数据传输的装置。图19是本申请实施例提供的一种数据传输 的装置的结构示意图。基于图19所示的如下多个单元，图19所示的数据传输的装置能够执行第一模块执行的全部或部分操作。应理解到，该装置可以包括比所示单元更多的附加单元或者省略其中所示的一部分单元，本申请实施例对此并不进行限制。如图19所示，该装置包括：
获取单元1901，用于获取至少一路第一数据，第一数据为采用第一FEC码型编码的数据；
转化单元1902，用于对至少一路第一数据进行转化处理，得到至少一路第二数据，至少一路第二数据的速率之和不小于至少一路第一数据的速率之和；
传输单元1903，用于传输至少一路第二数据。
在一种可能的实施方式中，转化单元1902，用于对至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；对多个第一码字进行解码，根据解码结果获取至少一路第二数据。
在一种可能的实施方式中，转化单元1902，用于按照第二FEC码型对解码结果进行编码，得到多个第二码字；根据多个第二码字得到至少一路第二数据。
在一种可能的实施方式中，转化单元1902，用于对多个第二码字进行交织，根据交织结果得到至少一路第二数据。
在一种可能的实施方式中，第一数据包括对齐标志AM，AM用于对至少一路第一数据进行对齐；转化单元1902，用于删除解码结果中的AM，按照第二FEC码型对删除AM之后的解码结果进行编码，得到多个第二码字。
在一种可能的实施方式中，转化单元1902，用于将删除AM之后的解码结果以依次发送的方式合并成一路第三数据，对一路第三数据进行编码，得到多个第二码字；或者，将删除AM之后的解码结果转换成至少两路第三数据，对至少两路第三数据进行编码，得到多个第二码字。
在一种可能的实施方式中，转化单元1902，用于将删除AM之后的解码结果合并成一路第四数据，将一路第四数据转换成至少两路第三数据。
在一种可能的实施方式中，转化单元1902，用于按照第二FEC码型对一路第三数据进行整体编码，得到多个第二码字；或者，将一路第三数据转化为至少两路第五数据，按照第二FEC码型对至少两路第五数据分别进行编码，得到多个第二码字，其中，第五数据的速率小于第三数据的速率。
在一种可能的实施方式中，转化单元1902，用于按照第二FEC码型对至少两路第三数据进行整体编码，得到多个第二码字；或者按照第二FEC码型对至少两路第三数据分别进行编码，得到多个第二码字。
在一种可能的实施方式中，转化单元1902，用于按照第二FEC码型对至少两路第三数据分别进行整体编码，得到多个第二码字；或者，将至少两路第三数据各自转换成至少两路第六数据，按照第二FEC码型对至少两路第六数据分别进行编码，得到多个第二码字，其中，第六数据的速率小于第三数据的速率。
在一种可能的实施方式中，转化单元1902，用于标记解码结果包括的多个码块中的错误码块，根据标记后的解码结果获取至少一路第二数据。
在一种可能的实施方式中，转化单元1902，用于对至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；根据多个第一码字得到至少一路第二数据。
在一种可能的实施方式中，转化单元1902，用于对多个第一码字进行合并，根据合并结果得到至少一路第二数据。
在一种可能的实施方式中，转化单元1902，用于将多个第一码字以依次发送的方式合并成一路第二数据；或者，将多个第一码字合并成至少两路第二数据。
在一种可能的实施方式中，转化单元1902，用于对对齐结果进行解交织，根据解交织结果得到多个第一码字。
在一种可能的实施方式中，转化单元1902，用于按照第二FEC码型对至少一路第一数据进行编码，得到多个第三码字；根据多个第三码字得到至少一路第二数据。
在一种可能的实施方式中，转化单元1902，用于对多个第三码字进行交织，根据交织结果得到至少一路第二数据。
在一种可能的实施方式中，转化单元1902，用于将至少一路第一数据以依次发送的方式合并成一路第七数据，对一路第七数据进行编码，得到多个第三码字；或者，将至少一路第一数据转换成至少两路第七数据，对至少两路第七数据进行编码，得到多个第三码字。
在一种可能的实施方式中，转化单元1902，用于将至少一路第一数据合并成一路第八数据，将一路第八数据转换成至少两路第七数据。
在一种可能的实施方式中，转化单元1902，用于按照第二FEC码型对一路第七数据进行整体编码，得到多个第三码字；或者，将一路第七数据转化为至少两路第九数据，按照第二FEC码型对至少两路第九数据分别进行编码，得到多个第三码字，其中，第九数据的速率小于第七数据的速率。
在一种可能的实施方式中，转化单元1902，用于按照第二FEC码型对至少两路第七数据进行整体编码，得到多个第三码字；或者按照第二FEC码型对至少两路第七数据分别进行编码，得到多个第三码字。
在一种可能的实施方式中，转化单元1902，用于按照第二FEC码型对至少两路第七数据分别进行整体编码，得到多个第三码字；或者，将至少两路第七数据各自转换成至少两路第十数据，按照第二FEC码型对至少两路第十数据分别进行编码，得到多个第三码字，其中，第十数据的速率小于第七数据的速率。
在一种可能的实施方式中，传输单元1903，用于将同步数据插入至少一路第二数据，传输插入同步数据后的数据。
在一种可能的实施方式中，传输单元1903，用于确定至少一路第二数据中的各路第二数据对应的AM；将各路第二数据对应的AM作为同步数据插入各路第二数据。
在一种可能的实施方式中，各路第二数据对应的AM通过调整对应的第一数据包括的AM得到；或者，各路第二数据对应的AM为对应的第一数据包括的AM中的全部内容；或者，各路第二数据对应的AM为对应的第一数据包括的AM中的部分内容。
图20是本申请实施例提供的一种数据传输的装置的结构示意图。基于图20所示的如下多个单元，该图20所示的数据传输的装置能够执行第三模块所执行的全部或部分操作。应理解到，该装置可以包括比所示单元更多的附加单元或者省略其中所示的一部分单元，本申请实施例对此并不进行限制。如图20所示，该装置包括：
获取单元2001，用于获取至少一路第二数据，至少一路第二数据为对至少一路第一数据进行转化处理得到的数据，至少一路第二数据的速率之和不小于至少一路第一数据的速率之 和，第一数据为采用第一前向纠错码FEC码型编码的数据；
转化单元2002，用于对至少一路第二数据进行转化处理，得到至少一路第一数据。
应理解的是，上述图19、图20提供的装置在实现其功能时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元完成，即将设备的内部结构划分成不同的功能单元，以完成以上描述的全部或者部分功能。另外，上述实施例提供的装置与方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
本申请实施例提供了一种数据传输的设备，该设备包括：处理器，该处理器与存储器耦合，该存储器中存储有至少一条程序指令或代码，该至少一条程序指令或代码由该处理器加载并执行，以使该数据传输的设备实现如上述方法实施例中的方法。
参见图21，图21示出了本申请一个示例性实施例提供的数据传输的设备1100的结构示意图，该数据传输的设备1100为发送侧/接收侧设备。图21所示的数据传输的设备1100用于执行上述图2所示的数据传输的方法所涉及的操作。该数据传输的设备1100例如是交换机、路由器等网络设备以及其他包含这种芯片级联模式的设备(例如服务器、PC等)。该数据传输的设备1100的硬件结构包括通信接口1101和处理器1102。可选地，通信接口1101和处理器1102之间通过总线1104连接。其中，通信接口1101用于获取第一数据和传输第二数据，处理器可存储有指令或程序代码，通过调用该指令或程序代码来执行上述第一模块所执行的功能，或者第三模块所执行的功能。可选地，该数据传输的设备1100还包括存储器1103，由存储器1103存放指令或程序代码，处理器1102用于调用存储器1103中的指令或程序代码使得该数据传输的设备1100执行上述方法实施例中第一模块的相关处理步骤。在具体实施例中，本申请实施例的数据传输的设备1100可包括上述各个方法实施例中的第一模块，数据传输的设备1100中的处理器1102读取存储器1103中的指令或程序代码，使图21所示的数据传输的设备1100能够执行第一模块所执行的全部或部分操作。
在具体实施例中，本申请实施例的数据传输的设备1100包括上述各个方法实施例中的第三模块，数据传输的设备1100中的处理器1102读取存储器1103中的指令或程序代码，使图21所示的数据传输的设备1100能够执行第三模块所执行的全部或部分操作。
示例性地，处理器1102例如是通用中央处理器(central processing unit，CPU)、数字信号处理器(digital signal processor，DSP)、网络处理器(network processer，NP)、图形处理器(graphics processing unit，GPU)、神经网络处理器(neural-network processing units，NPU)、数据处理单元(data processing unit，DPU)、微处理器或者一个或多个用于实现本申请方案的集成电路。例如，处理器1102包括专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。PLD例如是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。其可以实现或执行结合本申请实施例公开内容所描述的各种逻辑方框、模块和电路。处理器也可以是实现计算功能的组合，例如包括一个或多个微处理器组合，DSP和微处理器的组合等等。
可选的，数据传输的设备1100还包括总线1104。总线1104用于在数据传输的设备1100的各组件之间传送信息。总线1104可以是外设部件互连标准(peripheral component interconnect， 简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。总线1104可以分为地址总线、数据总线、控制总线等。为便于表示，图21中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。图21中数据传输的设备1100的各组件之间除了采用总线1104连接，还可采用其他方式连接，本申请实施例不对各组件的连接方式进行限定。
存储器1103例如是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，又如是随机存取存储器(random access memory，RAM)或者可存储信息和指令的其它类型的动态存储设备，又如是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。存储器1103例如是独立存在，并通过总线1104与处理器1102相连接。存储器1103也可以和处理器1102集成在一起。
通信接口1101使用任何收发器一类的装置，用于与其它设备或通信网络通信，通信网络可以为以太网、无线接入网(RAN)或无线局域网(wireless local area networks，WLAN)等。通信接口1101可以包括有线通信接口，还可以包括无线通信接口。具体的，通信接口1101可以为以太(ethernet)接口、快速以太(fast ethernet，FE)接口、千兆以太(gigabit ethernet，GE)接口，异步传输模式(asynchronous transfer mode，ATM)接口，无线局域网(wireless local area networks，WLAN)接口，蜂窝网络通信接口或其组合。以太网接口可以是光接口，电接口或其组合。在本申请实施例中，通信接口1101可以用于数据传输的设备1100与其他设备进行通信。
在具体实现中，作为一种实施例，处理器1102可以包括一个或多个CPU。这些处理器中的每一个可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，数据传输的设备1100可以包括多个处理器。这些处理器中的每一个可以是一个单核处理器(single-CPU)，也可以是一个多核处理器(multi-CPU)。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，数据传输的设备1100还可以包括输出设备和输入设备。输出设备和处理器1102通信，可以以多种方式来显示信息。例如，输出设备可以是液晶显示器(liquid crystal display，LCD)、发光二级管(light emitting diode，LED)显示设备、阴极射线管(cathode ray tube，CRT)显示设备或投影仪(projector)等。输入设备和处理器1102通信，可以以多种方式接收用户的输入。例如，输入设备可以是鼠标、键盘、触摸屏设备或传感设备等。
在一些实施例中，存储器1103用于存储执行本申请方案的程序代码，处理器1102可以执行存储器1103中存储的程序代码。也即是，数据传输的设备1100可以通过处理器1102以及存储器1103中的程序代码，来实现方法实施例提供的数据传输的方法。程序代码中可以包 括一个或多个软件模块。可选地，处理器1102自身也可以存储执行本申请方案的程序代码或指令。
在具体实施例中，本申请实施例的数据传输的设备1100可包括上述各个方法实施例中的第一模块，数据传输的设备1100中的处理器1102读取存储器1103中的程序代码或处理器1102自身存储的程序代码或指令，使图21所示的数据传输的设备1100能够执行第一模块所执行的全部或部分操作。
在具体实施例中，本申请实施例的数据传输的设备1100可包括上述各个方法实施例中的第三模块，数据传输的设备1100中的处理器1102读取存储器1103中的程序代码或处理器1102自身存储的程序代码或指令，使图21所示的数据传输的设备1100能够执行第三模块所执行的全部或部分操作。
数据传输的设备1100还可以对应于上述图19、20所示的装置，图19、20所示的装置中的每个功能单元采用数据传输的设备1100的软件实现。换句话说，图19、20所示的装置包括的功能单元为数据传输的设备1100的处理器1102读取存储器1103中存储的程序代码后生成的。
其中，图2-18所示的数据传输的方法的各步骤通过数据传输的设备1100的处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤，为避免重复，这里不再详细描述。
本申请实施例还提供了一种数据传输的系统，该系统包括：第一数据传输的设备和第二数据传输的设备；第一数据传输的设备用于执行图2所示的第一模块所执行的方法，第二数据传输的设备用于执行图18所示的第三模块所执行的方法。
该系统的第一数据传输的设备和第二数据传输的设备各自的功能可参考上述图2和图18所示的相关描述，此处不再一一赘述。
应理解的是，上述处理器可以是CPU，还可以是其他通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。值得说明的是，处理器可以是支持进阶精简指令集机器(advanced RISC machines，ARM)架构的处理器。
进一步地，在一种可选的实施例中，上述存储器可以包括只读存储器和随机存取存储器，并向处理器提供指令和数据。存储器还可以包括非易失性随机存取存储器。例如，存储器还可以存储设备类型的信息。
该存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是ROM、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、EEPROM或闪存。易失性存储器可以是RAM，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用。例如，静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic random access memory，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data date SDRAM，DDR SDRAM)、增强型同步动态随机 存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
还提供了一种计算机可读存储介质，存储介质中存储有至少一条程序指令或代码，程序指令或代码由处理器加载并执行时以使计算机实现如上图2-18所示的数据传输的方法。
本申请提供了一种计算机程序，当计算机程序被计算机执行时，可以使得处理器或计算机执行上述方法实施例中对应的各个步骤和/或流程。
提供了一种芯片，包括处理器，用于从存储器中调用并运行存储器中存储的指令，使得安装有芯片的设备执行上述各方面中的方法。
提供另一种芯片，包括：输入接口、输出接口、处理器和存储器，输入接口、输出接口、处理器以及存储器之间通过内部连接通路相连，处理器用于执行存储器中的代码，当代码被执行时，处理器用于执行上述各方面中的方法。
提供一种设备，包括上述方案中任一的芯片。
提供一种设备，包括上述方案中任一的第一芯片，和/或，上述方案中任一的第三芯片。
在一些实施例中，图14-17中，第二芯片可以是发送侧设备，比如路由器、交换机、服务器中的物理层(PHY)芯片，第一芯片可以是接收侧设备的接口，比如光模块中的芯片或者时钟数据恢复(clock data recovery，CDR)/重定时(retimer)芯片。在一些实施例中，第一芯片可以是发送侧设备，比如路由器、交换机、服务器中的PHY芯片，第三芯片可以是接收侧设备的接口，比如光模块中的芯片或者CDR/retimer芯片。PHY芯片可以是位于计算设备的单板上的芯片，该芯片可以是CPU、NP、NPU、FPGA、可编程逻辑控制器(programmable logic controller，PLC)等中的一个或其任意组合。
在一些实施例中，第一芯片和第二芯片之间通过AUI通信；在一些实施例中，第三芯片和第一芯片之间通过AUI通信。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。可用介质可以是磁性介质，(例如软盘、硬盘、磁带)、光介质(例如数字通用光盘(digital versatile disc，DVD))或者半导体介质(例如固态硬盘(solid state disk))等。
以上的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。
本领域普通技术人员可以意识到，结合本文中所公开的实施例中描述的各方法步骤和模块，能够以软件、硬件、固件或者其任意组合来实现，为了清楚地说明硬件和软件的可互换 性，在上述说明中已经按照功能一般性地描述了各实施例的步骤及组成。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域普通技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，该程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机程序指令。作为示例，本申请实施例的方法可以在机器可执行指令的上下文中被描述，机器可执行指令诸如包括在目标的真实或者虚拟处理器上的器件中执行的程序模块中。一般而言，程序模块包括例程、程序、库、对象、类、组件、数据结构等，其执行特定的任务或者实现特定的抽象数据结构。在各实施例中，程序模块的功能可以在所描述的程序模块之间合并或者分割。用于程序模块的机器可执行指令可以在本地或者分布式设备内执行。在分布式设备中，程序模块可以位于本地和远程存储介质二者中。
用于实现本申请实施例的方法的计算机程序代码可以用一种或多种编程语言编写。这些计算机程序代码可以提供给通用计算机、专用计算机或其他可编程的数据处理装置的处理器，使得程序代码在被计算机或其他可编程的数据处理装置执行的时候，引起在流程图和/或框图中规定的功能/操作被实施。程序代码可以完全在计算机上、部分在计算机上、作为独立的软件包、部分在计算机上且部分在远程计算机上或完全在远程计算机或服务器上执行。
在本申请实施例的上下文中，计算机程序代码或者相关数据可以由任意适当载体承载，以使得设备、装置或者处理器能够执行上文描述的各种处理和操作。载体的示例包括信号、计算机可读介质等等。
信号的示例可以包括电、光、无线电、声音或其它形式的传播信号，诸如载波、红外信号等。
机器可读介质可以是包含或存储用于或有关于指令执行系统、装置或设备的程序的任何有形介质。机器可读介质可以是机器可读信号介质或机器可读存储介质。机器可读介质可以包括但不限于电子的、磁的、光学的、电磁的、红外的或半导体系统、装置或设备，或其任意合适的组合。机器可读存储介质的更详细示例包括带有一根或多根导线的电气连接、便携式计算机磁盘、硬盘、RAM、ROM、可擦除可编程只读存储器(EPROM或闪存)、光存储设备、磁存储设备，或其任意合适的组合。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、设备和模块的具体工作过程，可以参见前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，该模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、设备或模块的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
该作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件 可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以是两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
该集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例中方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
本申请中术语“第一”、“第二”等字样用于对作用和功能基本相同的相同项或相似项进行区分，应理解，“第一”、“第二”、“第n”之间不具有逻辑或时序上的依赖关系，也不对数量和执行顺序进行限定。还应理解，尽管以下描述使用术语第一、第二等来描述各种元素，但这些元素不应受术语的限制。这些术语只是用于将一元素与另一元素区别分开。例如，在不脱离各种所述示例的范围的情况下，第一模块可以被称为第二模块，并且类似地，第二模块可以被称为第一模块。
还应理解，在本申请的各个实施例中，各个过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本申请中术语“至少一个”的含义是指一个或多个，本申请中术语“多个”的含义是指两个或两个以上，例如，多个第二报文是指两个或两个以上的第二报文。本文中术语“系统”和“网络”经常可互换使用。
应理解，在本文中对各种所述示例的描述中所使用的术语只是为了描述特定示例，而并非旨在进行限制。如在对各种所述示例的描述和所附权利要求书中所使用的那样，单数形式“一个(“a”，“an”)”和“该”旨在也包括复数形式，除非上下文另外明确地指示。
还应理解，术语“包括”(也称“includes”、“including”、“comprises”和/或“comprising”)当在本说明书中使用时指定存在所陈述的特征、整数、步骤、操作、元素、和/或部件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元素、部件、和/或其分组。
还应理解，术语“若”和“如果”可被解释为意指“当...时”(“when”或“upon”)或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“若确定...”或“若检测到[所陈述的条件或事件]”可被解释为意指“在确定...时”或“响应于确定...”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
还应理解，说明书通篇中提到的“一个实施例”、“一实施例”、“一种可能的实现方式”意味着与实施例或实现方式有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”、“一种可能的实现 方式”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。

Claims (56)

  1. 一种数据传输的方法，其特征在于，包括：
    第一模块获取至少一路第一数据，所述第一数据为采用第一前向纠错码FEC码型编码的数据；
    所述第一模块对所述至少一路第一数据进行转化处理，得到至少一路第二数据，所述至少一路第二数据的速率之和不小于所述至少一路第一数据的速率之和；
    所述第一模块传输所述至少一路第二数据。
  2. 根据权利要求1所述的方法，其特征在于，所述第一模块对所述至少一路第一数据进行转化处理，得到至少一路第二数据，包括：
    所述第一模块对所述至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；
    对所述多个第一码字进行解码，根据解码结果获取所述至少一路第二数据。
  3. 根据权利要求2所述的方法，其特征在于，所述根据解码结果获取所述至少一路第二数据，包括：
    按照第二FEC码型对所述解码结果进行编码，得到多个第二码字；
    根据所述多个第二码字得到所述至少一路第二数据。
  4. 根据权利要求3所述的方法，其特征在于，所述根据所述多个第二码字得到所述至少一路第二数据，包括：
    对所述多个第二码字进行交织，根据交织结果得到所述至少一路第二数据。
  5. 根据权利要求3或4所述的方法，其特征在于，所述第一数据包括对齐标志AM，所述AM用于对所述至少一路第一数据进行对齐；所述按照第二FEC码型对所述解码结果进行编码，得到多个第二码字，包括：
    删除所述解码结果中的AM，按照第二FEC码型对删除AM之后的解码结果进行编码，得到多个第二码字。
  6. 根据权利要求5所述的方法，其特征在于，所述按照第二FEC码型对删除AM之后的解码结果进行编码，得到多个第二码字，包括：
    将所述删除AM之后的解码结果以依次发送的方式合并成一路第三数据，对所述一路第三数据进行编码，得到多个第二码字；
    或者，将所述删除AM之后的解码结果转换成至少两路第三数据，对所述至少两路第三数据进行编码，得到多个第二码字。
  7. 根据权利要求6所述方法，其特征在于，所述将所述删除AM之后的解码结果转换成至少两路第三数据，包括：
    将所述删除AM之后的解码结果合并成一路第四数据，将所述一路第四数据转换成所述至少两路第三数据。
  8. 根据权利要求6所述的方法，其特征在于，所述对所述一路第三数据进行编码，得到多个第二码字，包括：
    按照所述第二FEC码型对所述一路第三数据进行整体编码，得到多个第二码字；
    或者，将所述一路第三数据转化为至少两路第五数据，按照所述第二FEC码型对所述至少两路第五数据分别进行编码，得到多个第二码字，其中，所述第五数据的速率小于所述第三数据的速率。
  9. 根据权利要求6或7所述的方法，其特征在于，所述对所述至少两路第三数据进行编码，得到多个第二码字，包括：
    按照所述第二FEC码型对所述至少两路第三数据进行整体编码，得到多个第二码字；
    或者按照所述第二FEC码型对所述至少两路第三数据分别进行编码，得到多个第二码字。
  10. 根据权利要求9所述的方法，其特征在于，所述按照所述第二FEC码型对所述至少两路第三数据分别进行编码，得到多个第二码字，包括：
    按照所述第二FEC码型对所述至少两路第三数据分别进行整体编码，得到多个第二码字；
    或者，将所述至少两路第三数据各自转换成至少两路第六数据，按照所述第二FEC码型对所述至少两路第六数据分别进行编码，得到多个第二码字，其中，所述第六数据的速率小于所述第三数据的速率。
  11. 根据权利要求2-10任一所述的方法，其特征在于，所述根据解码结果获取所述至少一路第二数据，包括：
    标记所述解码结果包括的多个码块中的错误码块，根据标记后的解码结果获取所述至少一路第二数据。
  12. 根据权利要求1所述的方法，其特征在于，所述第一模块对所述至少一路第一数据进行转化处理，得到至少一路第二数据，包括：
    所述第一模块对所述至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；
    根据所述多个第一码字得到所述至少一路第二数据。
  13. 根据权利要求12所述的方法，其特征在于，所述根据所述多个第一码字得到所述至少一路第二数据，包括：
    对所述多个第一码字进行合并，根据合并结果得到所述至少一路第二数据。
  14. 根据权利要求13所述的方法，其特征在于，所述对所述多个第一码字进行合并，根据合并结果得到所述至少一路第二数据，包括：
    将所述多个第一码字以依次发送的方式合并成一路第二数据；
    或者，将所述多个第一码字合并成至少两路第二数据。
  15. 根据权利要求2-14任一所述的方法，其特征在于，所述至少一路第一数据为经过交织得到的数据，所述根据对齐结果获取多个第一码字，包括：
    对所述对齐结果进行解交织，根据解交织结果得到多个第一码字。
  16. 根据权利要求1所述的方法，其特征在于，所述第一模块对所述至少一路第一数据进行转化处理，得到至少一路第二数据，包括：
    所述第一模块按照第二FEC码型对所述至少一路第一数据进行编码，得到多个第三码字；
    所述第一模块根据所述多个第三码字得到所述至少一路第二数据。
  17. 根据权利要求16所述的方法，其特征在于，所述根据所述多个第三码字得到所述至少一路第二数据，包括：
    对所述多个第三码字进行交织，根据交织结果得到所述至少一路第二数据。
  18. 根据权利要求16或17所述的方法，其特征在于，所述第一模块按照第二FEC码型对所述至少一路第一数据进行编码，得到多个第三码字，包括：
    将所述至少一路第一数据以依次发送的方式合并成一路第七数据，对所述一路第七数据进行编码，得到多个第三码字；
    或者，将所述至少一路第一数据转换成至少两路第七数据，对所述至少两路第七数据进行编码，得到多个第三码字。
  19. 根据权利要求18所述方法，其特征在于，所述将所述至少一路第一数据转换成至少两路第七数据，包括：
    将所述至少一路第一数据合并成一路第八数据，将所述一路第八数据转换成所述至少两路第七数据。
  20. 根据权利要求18所述的方法，其特征在于，所述对所述一路第七数据进行编码，得到多个第三码字，包括：
    按照所述第二FEC码型对所述一路第七数据进行整体编码，得到多个第三码字；
    或者，将所述一路第七数据转化为至少两路第九数据，按照所述第二FEC码型对所述至少两路第九数据分别进行编码，得到多个第三码字，其中，所述第九数据的速率小于所述第七数据的速率。
  21. 根据权利要求18或19所述的方法，其特征在于，所述对所述至少两路第七数据进行编码，得到多个第三码字，包括：
    按照所述第二FEC码型对所述至少两路第七数据进行整体编码，得到多个第三码字；
    或者按照所述第二FEC码型对所述至少两路第七数据分别进行编码，得到多个第三码字。
  22. 根据权利要求21所述的方法，其特征在于，所述按照所述第二FEC码型对所述至少两路第七数据分别进行编码，得到多个第三码字，包括：
    按照所述第二FEC码型对所述至少两路第七数据分别进行整体编码，得到多个第三码字；
    或者，将所述至少两路第七数据各自转换成至少两路第十数据，按照所述第二FEC码型对所述至少两路第十数据分别进行编码，得到多个第三码字，其中，所述第十数据的速率小于所述第七数据的速率。
  23. 根据权利要求1-22任一所述的方法，其特征在于，所述第一模块传输所述至少一路第二数据，包括：
    所述第一模块将同步数据插入所述至少一路第二数据，传输插入所述同步数据后的数据。
  24. 根据权利要求23所述的方法，其特征在于，所述第一模块将同步数据插入所述至少一路第二数据，包括：
    确定所述至少一路第二数据中的各路第二数据对应的AM；
    将所述各路第二数据对应的AM作为同步数据插入所述各路第二数据。
  25. 根据权利要求24所述的方法，其特征在于，所述各路第二数据对应的AM通过调整对应的第一数据包括的AM得到；
    或者，所述各路第二数据对应的AM为对应的第一数据包括的AM中的全部内容；
    或者，所述各路第二数据对应的AM为对应的第一数据包括的AM中的部分内容。
  26. 一种数据传输的方法，其特征在于，包括：
    第三模块获取至少一路第二数据，所述至少一路第二数据为对至少一路第一数据进行转化处理得到的数据，所述至少一路第二数据的速率之和不小于所述至少一路第一数据的速率之和，所述第一数据为采用第一前向纠错码FEC码型编码的数据；
    所述第三模块对所述至少一路第二数据进行转化处理，得到所述至少一路第一数据。
  27. 一种数据传输的装置，其特征在于，所述装置应用于第一模块，所述装置包括：
    获取单元，用于获取至少一路第一数据，所述第一数据为采用第一前向纠错码FEC码型编码的数据；
    转化单元，用于对所述至少一路第一数据进行转化处理，得到至少一路第二数据，所述至少一路第二数据的速率之和不小于所述至少一路第一数据的速率之和；
    传输单元，用于传输所述至少一路第二数据。
  28. 根据权利要求27所述的装置，其特征在于，所述转化单元，用于对所述至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；对所述多个第一码字进行解码，根据解码结果获取所述至少一路第二数据。
  29. 根据权利要求28所述的装置，其特征在于，所述转化单元，用于按照第二FEC码型 对所述解码结果进行编码，得到多个第二码字；根据所述多个第二码字得到所述至少一路第二数据。
  30. 根据权利要求29所述的装置，其特征在于，所述转化单元，用于对所述多个第二码字进行交织，根据交织结果得到所述至少一路第二数据。
  31. 根据权利要求29或30所述的装置，其特征在于，所述第一数据包括对齐标志AM，所述AM用于对所述至少一路第一数据进行对齐；所述转化单元，用于删除所述解码结果中的AM，按照第二FEC码型对删除AM之后的解码结果进行编码，得到多个第二码字。
  32. 根据权利要求31所述的装置，其特征在于，所述转化单元，用于将所述删除AM之后的解码结果以依次发送的方式合并成一路第三数据，对所述一路第三数据进行编码，得到多个第二码字；或者，将所述删除AM之后的解码结果转换成至少两路第三数据，对所述至少两路第三数据进行编码，得到多个第二码字。
  33. 根据权利要求32所述装置，其特征在于，所述转化单元，用于将所述删除AM之后的解码结果合并成一路第四数据，将所述一路第四数据转换成所述至少两路第三数据。
  34. 根据权利要求32所述的装置，其特征在于，所述转化单元，用于按照所述第二FEC码型对所述一路第三数据进行整体编码，得到多个第二码字；或者，将所述一路第三数据转化为至少两路第五数据，按照所述第二FEC码型对所述至少两路第五数据分别进行编码，得到多个第二码字，其中，所述第五数据的速率小于所述第三数据的速率。
  35. 根据权利要求32或33所述的装置，其特征在于，所述转化单元，用于按照所述第二FEC码型对所述至少两路第三数据进行整体编码，得到多个第二码字；或者按照所述第二FEC码型对所述至少两路第三数据分别进行编码，得到多个第二码字。
  36. 根据权利要求35所述的装置，其特征在于，所述转化单元，用于按照所述第二FEC码型对所述至少两路第三数据分别进行整体编码，得到多个第二码字；或者，将所述至少两路第三数据各自转换成至少两路第六数据，按照所述第二FEC码型对所述至少两路第六数据分别进行编码，得到多个第二码字，其中，所述第六数据的速率小于所述第三数据的速率。
  37. 根据权利要求28-36任一所述的装置，其特征在于，所述转化单元，用于标记所述解码结果包括的多个码块中的错误码块，根据标记后的解码结果获取所述至少一路第二数据。
  38. 根据权利要求27所述的装置，其特征在于，所述转化单元，用于对所述至少一路第一数据进行对齐，根据对齐结果获取多个第一码字；根据所述多个第一码字得到所述至少一路第二数据。
  39. 根据权利要求38所述的装置，其特征在于，所述转化单元，用于对所述多个第一码字进行合并，根据合并结果得到所述至少一路第二数据。
  40. 根据权利要求39所述的装置，其特征在于，所述转化单元，用于将所述多个第一码字以依次发送的方式合并成一路第二数据；或者，将所述多个第一码字合并成至少两路第二数据。
  41. 根据权利要求28-40任一所述的装置，其特征在于，所述转化单元，用于对所述对齐结果进行解交织，根据解交织结果得到多个第一码字。
  42. 根据权利要求27所述的装置，其特征在于，所述转化单元，用于按照第二FEC码型对所述至少一路第一数据进行编码，得到多个第三码字；根据所述多个第三码字得到所述至少一路第二数据。
  43. 根据权利要求42所述的装置，其特征在于，所述转化单元，用于对所述多个第三码字进行交织，根据交织结果得到所述至少一路第二数据。
  44. 根据权利要求42或43所述的装置，其特征在于，所述转化单元，用于将所述至少一路第一数据以依次发送的方式合并成一路第七数据，对所述一路第七数据进行编码，得到多个第三码字；或者，将所述至少一路第一数据转换成至少两路第七数据，对所述至少两路第七数据进行编码，得到多个第三码字。
  45. 根据权利要求44所述装置，其特征在于，所述转化单元，用于将所述至少一路第一数据合并成一路第八数据，将所述一路第八数据转换成所述至少两路第七数据。
  46. 根据权利要求44所述的装置，其特征在于，所述转化单元，用于按照所述第二FEC码型对所述一路第七数据进行整体编码，得到多个第三码字；或者，将所述一路第七数据转化为至少两路第九数据，按照所述第二FEC码型对所述至少两路第九数据分别进行编码，得到多个第三码字，其中，所述第九数据的速率小于所述第七数据的速率。
  47. 根据权利要求44或45所述的装置，其特征在于，所述转化单元，用于按照所述第二FEC码型对所述至少两路第七数据进行整体编码，得到多个第三码字；或者按照所述第二FEC码型对所述至少两路第七数据分别进行编码，得到多个第三码字。
  48. 根据权利要求47所述的装置，其特征在于，所述转化单元，用于按照所述第二FEC码型对所述至少两路第七数据分别进行整体编码，得到多个第三码字；或者，将所述至少两路第七数据各自转换成至少两路第十数据，按照所述第二FEC码型对所述至少两路第十数据分别进行编码，得到多个第三码字，其中，所述第十数据的速率小于所述第七数据的速率。
  49. 根据权利要求27-48任一所述的装置，其特征在于，所述传输单元，用于将同步数据插入所述至少一路第二数据，传输插入所述同步数据后的数据。
  50. 根据权利要求49所述的装置，其特征在于，所述传输单元，用于确定所述至少一路第二数据中的各路第二数据对应的AM；将所述各路第二数据对应的AM作为同步数据插入所述各路第二数据。
  51. 根据权利要求50所述的装置，其特征在于，所述各路第二数据对应的AM通过调整对应的第一数据包括的AM得到；或者，所述各路第二数据对应的AM为对应的第一数据包括的AM中的全部内容；或者，所述各路第二数据对应的AM为对应的第一数据包括的AM中的部分内容。
  52. 一种数据传输的装置，其特征在于，所述装置应用于第三模块，所述装置包括：
    获取单元，用于获取至少一路第二数据，所述至少一路第二数据为对至少一路第一数据进行转化处理得到的数据，所述至少一路第二数据的速率之和不小于所述至少一路第一数据的速率之和，所述第一数据为采用第一前向纠错码FEC码型编码的数据；
    转化单元，用于对所述至少一路第二数据进行转化处理，得到所述至少一路第一数据。
  53. 一种数据传输的设备，其特征在于，包括：处理器，所述处理器与存储器耦合，所述存储器中存储有至少一条程序指令或代码，所述至少一条程序指令或代码由所述处理器加载并执行，以使所述数据传输的设备实现如权利要求1-26中任一所述的方法。
  54. 一种数据传输的系统，其特征在于，包括第一数据传输的设备和第二数据传输的设备，所述第一数据传输的设备用于执行如权利要求1-25任一所述的方法，所述第二数据传输的设备用于执行如权利要求26所述的方法。
  55. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有至少一条程序指令或代码，所述程序指令或代码由计算机加载并执行，以使硕士计算机实现如权利要求1-26中任一所述的方法。
  56. 一种计算机程序产品，其特征在于，所述计算机程序产品包括：计算机程序代码，当所述计算机程序代码被计算机运行时，使得所述计算机执行如权利要求1-26中任一所述的方法。
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