WO2022156767A1 - 数据传输的方法、装置、设备、系统及计算机可读存储介质 - Google Patents

数据传输的方法、装置、设备、系统及计算机可读存储介质 Download PDF

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Publication number
WO2022156767A1
WO2022156767A1 PCT/CN2022/073180 CN2022073180W WO2022156767A1 WO 2022156767 A1 WO2022156767 A1 WO 2022156767A1 CN 2022073180 W CN2022073180 W CN 2022073180W WO 2022156767 A1 WO2022156767 A1 WO 2022156767A1
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Prior art keywords
data
chip
fec
fec code
pattern
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PCT/CN2022/073180
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English (en)
French (fr)
Inventor
何向
任浩
王心远
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22742246.6A priority Critical patent/EP4274127A1/en
Priority to JP2023544457A priority patent/JP2024505862A/ja
Priority to AU2022211512A priority patent/AU2022211512A1/en
Priority to CA3206435A priority patent/CA3206435A1/en
Priority to MX2023008660A priority patent/MX2023008660A/es
Priority to KR1020237027975A priority patent/KR20230129554A/ko
Publication of WO2022156767A1 publication Critical patent/WO2022156767A1/zh
Priority to US18/357,494 priority patent/US20230370193A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L2001/0092—Error control systems characterised by the topology of the transmission link
    • H04L2001/0097—Relays

Definitions

  • the embodiments of the present application relate to the field of communications technologies, and in particular, to a data transmission method, apparatus, device, system, and computer-readable storage medium.
  • Forward error correction is a data encoding method that improves the data transmission rate and transmission distance in the channel by providing check bits for the transmitted data.
  • the sender encodes the original data through a specific FEC code pattern, and sends the encoded data to the receiver end, and the receiver end decodes the received data through the same FEC code pattern to obtain the original data.
  • the present application proposes a data transmission method, apparatus, device, system, and computer-readable storage medium, which are used to enhance the FEC code pattern to adapt to high-rate and/or long-distance data transmission.
  • a method for data transmission comprising: acquiring first data encoded by a first FEC code pattern by a first chip; outputting an output corresponding to the first FEC code pattern based on a reference clock frequency of the first chip The rate determines the second FEC code pattern; then, the first chip encodes the first data according to the second FEC code pattern, obtains second data, and transmits the second data.
  • the method determines the second FEC code pattern based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code pattern, and performs the second FEC code pattern on the acquired first data encoded by the first FEC code pattern through the second FEC code pattern.
  • Encoding to obtain the second data of cascade encoding so that the second data has a higher coding gain, and when transmitted in the channel prone to errors, the data with errors can be effectively corrected, thereby improving the data quality of transmission.
  • the second data is obtained by encoding directly on the basis of the first data, the implementation process of the method is relatively simple, and the efficiency of data transmission is improved.
  • the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, the codeword length of the second data, and the codeword of the second data The information length satisfies the overhead proportional relationship;
  • the determining the second FEC pattern based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC pattern includes: based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type, and determine the second FEC code type according to the overhead proportional relationship.
  • the overhead proportional relationship includes:
  • the n is the codeword length of the second data
  • the k is the information length in the codeword of the second data
  • the v 1 is the output rate corresponding to the first FEC code type
  • the p In order to adjust the parameters, the f is the reference clock frequency of the first chip, and the p is a positive integer.
  • the codeword length of the second data is in an integer multiple relationship with the number of logical channels when the second data is distributed.
  • the determined second FEC code type is more suitable for the transmission scenario, and the performance of data transmission is improved.
  • the first chip encodes the first data according to the second FEC code pattern to obtain the second data, including: the first chip distributes the first data to obtain a plurality of first sub-data, the first chip encodes the plurality of first sub-data respectively according to the second FEC code pattern to obtain a plurality of second sub-data; the first chip transmits the first sub-data;
  • the second data includes: the first chip transmits the plurality of second sub-data.
  • the first chip distributing the first data to obtain multiple first sub-data includes: the first chip distributing the first data through a physical coding sub-layer PCS channel to obtain multiple first sub-data or, the first chip distributes the first data stream through the physical medium access sublayer PMA to obtain a plurality of first sub-data.
  • transmitting the second data by the first chip includes: the first chip distributes the second data to obtain a plurality of third sub-data, and transmits the second data through a plurality of logic channels The plurality of third sub-data are transmitted.
  • the method before the determining the second FEC pattern based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC pattern, the method further includes: the first FEC pattern A chip performs auto-negotiation with a third chip that receives data sent by the first chip; in response to an auto-negotiation result indicating that concatenated coding is required, the first chip executes the reference clock frequency based on the first chip and the The output rate corresponding to the first FEC code type determines the second FEC code type.
  • the self-negotiation is used to determine whether to perform concatenated coding, which is more applicable and more in line with the needs of actual scenarios.
  • the first data is data inside the first chip, or the first data is data received by the first chip and sent by the second chip. Since the first data may be the data inside the first chip or the received data transmitted by other chips, the data transmission scenario applied by this method is relatively flexible.
  • a data transmission method includes: a third chip receives second data, where the second data is obtained by encoding the first data by using a second forward error correction code (FEC pattern) data, the first data is the data encoded by the first FEC code pattern; the third chip decodes the second data according to the second FEC code pattern to obtain the decoded data. Since the second data is obtained by encoding the first data using the second FEC code pattern, and the first data is obtained by encoding the first FEC code pattern, the encoding gain of the second data received by the third chip is higher , the error correction capability is higher, and by decoding the second data, the accuracy of the decoded data obtained is higher.
  • FEC pattern forward error correction code
  • the third chip decodes the second data according to the second FEC code pattern, including: the third chip decodes the second data according to the second FEC code pattern
  • the second data is soft-decision decoded.
  • the third chip decodes the second data according to the second FEC code pattern, and after obtaining the decoded data, the method further includes: the third chip according to The third FEC code type re-encodes the decoded data, and transmits the re-encoded data.
  • the third chip decodes the second data according to the second FEC code pattern
  • the method further includes: the third chip according to The third FEC code type re-encodes the decoded data, and transmits the re-encoded data.
  • the third FEC code pattern is the second FEC code pattern.
  • an apparatus for data transmission comprising:
  • an acquisition module configured to acquire first data, where the first data is data encoded by the first forward error correction code (FEC) code pattern;
  • FEC forward error correction code
  • a determining module configured to determine a second FEC code pattern based on a reference clock frequency of the first chip and an output rate corresponding to the first FEC code pattern
  • an encoding module configured to encode the first data according to the second FEC code pattern to obtain second data
  • a transmission module for transmitting the second data.
  • the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, the codeword length of the second data, and the codeword of the second data The information length satisfies an overhead proportional relationship; the determining module is configured to determine the second FEC code according to the overhead proportional relationship based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type type.
  • the overhead proportional relationship includes:
  • the n is the codeword length of the second data
  • the k is the information length in the codeword of the second data
  • the v 1 is the output rate corresponding to the first FEC code type
  • the p For adjusting parameters, the f is the reference clock frequency of the first chip, and the p is a positive integer.
  • the codeword length of the second data is in an integer multiple relationship with the number of logical channels when the second data is distributed.
  • the encoding module is configured to distribute the first data to obtain multiple first sub-data, and encode the multiple first sub-data respectively according to the second FEC code pattern , to obtain a plurality of second sub-data; the transmission module is configured to transmit the plurality of second sub-data.
  • the encoding module is configured to distribute the first data through a physical encoding sublayer PCS channel to obtain multiple first subdata; or distribute the first sublayer through a physical medium access sublayer PMA The first data stream obtains a plurality of first sub-data.
  • the transmission module is configured to distribute the second data to obtain multiple third sub-data, and send the multiple third sub-data through multiple logical channels.
  • the apparatus further includes: an auto-negotiation module configured to perform auto-negotiation with a third chip that receives data sent by the first chip; in response to the auto-negotiation result indicating that concatenated coding is required, The determining module performs the determining of the second FEC pattern based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC pattern.
  • the first data is data inside the first chip, or the first data is data received by the first chip and sent by the second chip.
  • an apparatus for data transmission comprising:
  • a receiving module configured to receive second data, where the second data is data obtained by using the second forward error correction code (FEC pattern) to encode the first data, and the first data is encoded by using the first FEC pattern The data;
  • FEC pattern forward error correction code
  • a decoding module configured to decode the second data according to the second FEC code pattern to obtain decoded data.
  • the decoding module is configured to perform soft-decision decoding on the second data according to the second FEC code pattern to obtain decoded data.
  • the apparatus further includes: an encoding module, configured to re-encode the decoded data according to the third FEC code pattern; and a transmission module, configured to transmit the re-encoded data.
  • the third FEC code pattern is the second FEC code pattern.
  • a data transmission device comprising: a processor, the processor is coupled to a memory, the memory stores at least one program instruction or code, and at least one program instruction or code is loaded and executed by the processor, To enable a device to implement the data transmission method according to any one of the first aspect or the second aspect.
  • a data transmission system comprising: a first data transmission device configured to execute the method described in the first aspect or any one of the first aspects; a second data transmission device using performing the method described in the second aspect or any one of the second aspects.
  • a computer-readable storage medium is provided, and at least one program instruction or code is stored in the computer-readable storage medium, and when the program instruction or code is loaded and executed by a processor, a computer can implement the first aspect or The data transmission method of any one of the second aspect.
  • Another communication apparatus includes a communication interface, a memory, and a processor.
  • the memory and the processor communicate with each other through an internal connection path, the memory is used for storing instructions, and the processor is used for executing the instructions stored in the memory to control the communication interface to receive data, and control the communication interface to send data, and when the When the processor executes the instructions stored in the memory, the processor causes the processor to execute the method in the first aspect or any possible implementation manner of the first aspect, or execute the second aspect or any possible implementation of the second aspect method in method.
  • the processor is one or more
  • the memory is one or more.
  • the memory may be integrated with the processor, or the memory may be provided separately from the processor.
  • the memory can be a non-transitory memory, such as a read only memory (ROM), which can be integrated with the processor on the same chip, or can be separately set in different On the chip, the embodiment of the present application does not limit the type of the memory and the setting manner of the memory and the processor.
  • ROM read only memory
  • a computer program (product) comprising: computer program code which, when executed by a computer, causes the computer to perform the methods of the above aspects.
  • a chip including a processor for invoking and executing instructions stored in a memory to cause a device on which the chip is installed to perform the methods of the above aspects.
  • Another chip including: an input interface, an output interface, a processor, and a memory, the input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the processor is used to execute all The code in the memory, when the code is executed, the processor is configured to perform the methods of the above aspects.
  • a device comprising the chip described in any one of the above solutions.
  • a device comprising the first chip described in any one of the above solutions, and/or the third chip described in any one of the above solutions.
  • the confidence (also called reliability) of each bit in the received codeword is first calculated based on the received quantized soft decision information, and a confidence sequence is obtained, from which the M least likely to be selected.
  • Reliable bit positions, in the M least reliable bit positions try all combinations of 0, 1, 2, .
  • Perform hard decoding and error correction on each test codeword then calculate the Euclidean distance between all corrected test codewords and the confidence sequence, and select the corrected test codeword corresponding to the smallest distance as the final post-correction codeword output. If there is no correctable codeword in the test codeword, the hard decision result corresponding to the original received codeword is used as the output codeword.
  • FIG. 1 is a schematic diagram of an implementation scenario of a method for data transmission provided by an embodiment of the present application
  • FIG. 2 is a flowchart of a method for data transmission provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of encoding the first data according to a second FEC code pattern according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of distributing first data according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of distributing first data through a PCS channel according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of distributing second data according to an embodiment of the present application.
  • FIG. 7 is another schematic diagram of distributing second data provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an implementation scenario of another data transmission method provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an apparatus for data transmission provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another apparatus for data transmission provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a data transmission device provided by an embodiment of the present application.
  • FEC FEC with higher coding gain may be required.
  • PAM4 pulse amplitude modulation 4 pulse amplitude modulation
  • an embodiment of the present application provides a method for data transmission.
  • the method determines a second FEC pattern based on a reference clock frequency of a first chip that transmits data and an output rate corresponding to the first FEC pattern.
  • the obtained first data encoded by the first FEC code pattern is encoded again by the second FEC code pattern to obtain the second data of concatenated encoding, so that the second data has a higher coding gain.
  • the error-corrected data can be effectively corrected, thereby improving the quality of data transmission.
  • the implementation process of the method is relatively simple, and the efficiency of data transmission is improved.
  • the process of concatenated encoding can be performed under certain trigger conditions. For example, this method performs auto-negotiation between chips, indicates that concatenated encoding is required according to the auto-negotiation result, and executes the reference clock frequency based on the first chip and the first FEC.
  • the process of determining the second FEC code by the output rate corresponding to the code type enables the chips to actively determine whether the cascaded coding is required, and is more flexible for coding of data transmitted in different channels.
  • the implementation scenario includes multiple chips, and information can be exchanged between the chips. , to realize data transmission.
  • data can be transmitted between the first chip 101 and the second chip 102 and between the first chip 101 and the third chip 103 .
  • the implementation scenario shown in FIG. 1 may include N chips, where N is a positive integer greater than or equal to 2. In FIG. 1 , only the number of chips is 3 as an example for description.
  • the data transmission method provided by the embodiment of the present application is shown in FIG. 2 , including but not limited to steps 201 to 206 .
  • Step 201 The first chip acquires first data, where the first data is data encoded by using the first FEC code pattern.
  • the first data is data inside the first chip, or data received by the first chip and sent by the second chip.
  • the first chip uses the first FEC code pattern to encode the original data to obtain the first data
  • the second chip uses the first FEC code pattern to encode the original data to obtain the encoded data
  • the second chip encodes the encoded data.
  • the latter data is scrambled to form first data
  • the first chip receives the first data sent by the second chip.
  • the second chip sends the first data to the first chip through a physical channel. Regardless of whether the first data is data within the first chip or data sent by the second chip, the first data may undergo other processing in addition to the first FEC encoding.
  • the first data is sent to the first chip by the second chip after passing through a physical medium attachment sublayer (PMA) and/or a physical media dependent (PMD) interface.
  • the data may also be data after passing through the PMA and/or a physical coding sublayer (physical coding sublayer, PCS) inside the first chip.
  • the first data may also be data that has undergone other processing, for example, the first data is data obtained after interleaving and distribution.
  • the first FEC code type is Reed-Solomon (Reed-Solomon, RS) code, Bosch-Crochri-Hawkwen Bose-Chaudhuri-Hocquenghem (BCH) codes, Fire codes, turbo codes, turbo product codes (TPC), staircase codes, and low-density parity-check (low-density parity-check) codes Any of -density parity-check, LDPC) codes.
  • the first chip after the first chip receives the first data, it can directly transmit the first data. In order to improve the quality of data transmission, the first data can also be encoded again.
  • the embodiment of the present application does not perform cascade encoding on the first chip.
  • the trigger method is limited.
  • the first chip performs auto-negotiation with a third chip that receives data sent by the first chip; in response to the auto-negotiation result indicating that cascaded coding is required, the first chip executes a reference clock based on the first chip The frequency and the output rate corresponding to the first FEC pattern determine the second FEC pattern.
  • the auto-negotiation process may be performed after receiving the first data, or may be performed before the method is performed. This embodiment of the present application does not limit the timing of the auto-negotiation, and the auto-negotiation may be performed before transmitting the first data.
  • Step 202 Determine the second FEC code pattern based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code pattern.
  • the reference clock frequency of the first chip, the output rate corresponding to the first FEC code pattern, the codeword length of the second data, and the information length in the codeword of the second data satisfy an overhead proportional relationship; based on The reference clock frequency of the first chip and the output rate corresponding to the first FEC code type determine the second FEC code type, including: based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type, according to the overhead proportional relationship.
  • the second FEC pattern By determining the second FEC code pattern according to the overhead proportional relationship, the overhead encoded by the second FEC code pattern can be guaranteed, and the performance of data transmission is further improved.
  • the overhead proportional relationship includes:
  • n is the code word length of the second data
  • k is the information length in the code word of the second data
  • v 1 is the output rate corresponding to the first FEC code type
  • p is the adjustment parameter
  • f is the reference clock of the first chip frequency
  • p is a positive integer.
  • the adjustment parameter is a reference value, for example, the adjustment parameter is an integer multiple of 10 or an integer multiple of 20; based on the reference value, a second FEC code pattern that satisfies the overhead proportional relationship is determined.
  • the reference clock frequency of the first chip is 156.25 megahertz (MHz)
  • the output rate corresponding to the first FEC code pattern is 106.25 gigabits per second (Gbps)
  • Gbps gigabits per second
  • the second FEC code type when the second FEC code type is determined according to the overhead proportional relationship, the second FEC code type may be determined with reference to Table 1, where the code types in Table 1 all belong to BCH codes.
  • n is the length of the codeword
  • k is the length of the information in the codeword
  • m is the finite field or Galois Field where the code is located, and is GF(2 m ), t for error correction capability.
  • the other BCH code types in Table 1 are the same as the above-mentioned BCH code types, and will not be repeated here.
  • the codeword length of the second data is in an integer multiple relationship with the number of logical channels when the second data is distributed.
  • the logical channel may be a PCS channel or an FEC channel.
  • the codeword length of the second data is an integer multiple of 8.
  • the number of the logical channels can also be 1, that is, the second data is transmitted through one logical channel. Since the codeword length of the second data is a positive integer, the codeword length of the second data is also the same as the distributed logical channel. Quantity is an integer multiple.
  • the manners of determining the second FEC pattern based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC pattern include but are not limited to the following three manners.
  • Mode 1 The first chip first determines a first set based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC pattern according to the overhead ratio relationship, and the first set includes a plurality of FEC patterns that satisfy the overhead ratio relationship. ; and then determine the second FEC code pattern from the first set according to the integer multiple relationship between the length of the code word and the logical channel during distribution.
  • Mode 2 The first chip first determines a second set according to the integer multiple relationship between the length of the code word and the logical channel during distribution, and the second set includes a plurality of FEC code patterns that satisfy the integer multiple relationship; and then based on the reference of the first chip The clock frequency and the output rate corresponding to the first FEC pattern are determined from the second set according to the overhead proportional relationship.
  • Mode 3 The first chip first determines a first set based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC pattern according to the overhead proportional relationship, and the first set includes a plurality of FEC patterns that satisfy the overhead proportional relationship. ; Determine the second set according to the length of the codeword and the logical channel during distribution into an integer multiple relationship, and the second set includes a plurality of FEC code patterns that satisfy the integer multiple relationship; Determine the second FEC based on the first set and the second set pattern. For example, based on the intersection of the first set and the second set, the first chip determines a second FEC pattern.
  • the second FEC code type may be any one of an RS code, a BCH code, a Farr code, a turbo code, a turbo product code, a ladder code, and an LDPC code.
  • the type is not limited.
  • Step 203 The first chip encodes the first data according to the second FEC code pattern to obtain the second data.
  • the first chip encodes the first data according to the second FEC code pattern to obtain the second data; if the first data is the first data
  • the first chip can directly encode the data according to the second FEC code pattern to obtain the second data.
  • the first chip can perform simple operations other than decoding, such as bit multiplexing (bit mux) or bit demultiplexing (bit demux), on the received data.
  • the first chip encodes the first data according to the second FEC code pattern to obtain second data, where the first data may be data directly received by the first chip, or It is data obtained by interleaving the plurality of sub-data after being distributed into a plurality of sub-data through the first chip.
  • the second FEC code pattern is used to encode the first data.
  • the first chip encodes each piece of first data according to the second FEC code pattern to obtain multiple pieces of first data. Two data. As shown in FIG.
  • the first chip receives the third data through the attachment unit interface (AUI), and processes it through the physical medium attachment sublayer (PMA) to obtain a plurality of first data.
  • a chip encodes the plurality of first data respectively to obtain a plurality of second data.
  • the obtained plurality of second data may be transmitted through a plurality of physical channels (physical channels 1-N in FIG. 5 ), and then transmitted to the outside through PMA and a physical media dependent interface (physical media dependent, PMD).
  • the second chip may be a network device, such as a physical layer (PHY) chip in a router or switch, and the first chip may be a chip in an optical module, or a clock data recovery (clock data recovery) chip.
  • PHY physical layer
  • the PHY chip may be a chip located on a single board of a network device, and the chip may be a central processing unit (CPU), a network processor (NP), a neural network processing unit (neural network processing unit) , NPU), field programmable gate array (field programmable gate array, FPGA), programmable logic controller (programmable logic controller, PLC) one or any combination thereof.
  • CPU central processing unit
  • NP network processor
  • NPU neural network processing unit
  • NPU field programmable gate array
  • FPGA field programmable gate array
  • PLC programmable logic controller
  • the first chip encodes the first data according to the second FEC code pattern to obtain the second data, including: the first chip distributes The first data obtains a plurality of first sub-data, and the first chip respectively encodes the plurality of first sub-data according to the second FEC code pattern to obtain a plurality of second sub-data.
  • the process may be as shown in FIG. 4 .
  • the manner in which the first chip distributes the first data to obtain a plurality of first sub-data includes but is not limited to the following two manners.
  • Mode 1 The first chip distributes the first data through the logic channel to obtain a plurality of first sub-data.
  • the first chip distributes the first data through N logical channels to obtain multiple first sub-data, wherein each logical channel is used to transmit one first sub-data, and the logical channel may be a PCS channel or an FEC channel.
  • the first chip encodes the plurality of first sub-data respectively according to the second FEC code pattern to obtain a plurality of second sub-data.
  • the process may be as shown in FIG. 5 , and the obtained multiple second sub-data may be transmitted to the outside through PMA and PMD, respectively.
  • Manner 2 The first chip distributes the first data through PMA to obtain a plurality of first sub-data.
  • Step 204 the first chip transmits the second data.
  • the first chip transmits the second data through a logic channel
  • the logic channel may be a PCS channel or an FEC channel.
  • the transmission of the second data by the first chip includes but is not limited to the following two situations.
  • the first chip transmits second data through the channel, and the second data may be single data or include multiple second sub-data.
  • the first chip distributes the second data to obtain a plurality of third sub-data, and sends the plurality of third sub-data through a plurality of logical channels.
  • the first chip distributes the second data by polling.
  • the number of logical channels is N, and N is a positive integer greater than or equal to 2.
  • the first chip distributes the second data through polling, and obtains N third sub-data.
  • the N third sub-data are sent through logical channels.
  • each of the N logical channels sends one third sub-data correspondingly.
  • the N third sub-data include but are not limited to being sent to the next chip via PMA and PMD.
  • the first data is single data
  • the second data is distributed to obtain a plurality of third sub-data
  • the multiple third sub-data are sent through multiple logical channels; if the first data is distributed as multiple first sub-data, any first sub-data in the multiple first sub-data is encoded by the second FEC code type to obtain
  • the first chip distributes a plurality of second sub-data to obtain a plurality of third sub-data, and sends the plurality of third sub-data through a plurality of logical channels.
  • the first chip distributes any second sub-data in the plurality of second sub-data by polling. Taking the system shown in FIG.
  • a plurality of second sub-data are obtained by encoding the second FEC code pattern, and for each second sub-data, the first chip distributes the second sub-data to obtain N third sub-data.
  • Sub-data where N is a positive integer greater than or equal to 2, and distributes the plurality of third sub-data through N logical channels.
  • each of the N logical channels sends one third sub-data correspondingly.
  • the above steps 201 to 204 are all processes performed by the first chip side to perform the data transmission.
  • the data transmission method is described by taking the third chip side as an example.
  • Step 205 The third chip receives second data, where the second data is data obtained by encoding the first data by using the second FEC code pattern, and the first data is data encoded by using the first FEC code pattern.
  • the third chip receives the second data sent by the first chip through the logic channel.
  • Step 206 The third chip decodes the second data according to the second FEC code pattern to obtain decoded data.
  • the second data is obtained by encoding the first data using the second FEC code pattern
  • the first data is obtained by encoding the first FEC code pattern
  • the encoding gain of the second data received by the third chip is higher
  • the error correction capability is higher
  • by decoding the second data the accuracy of the decoded data obtained is higher.
  • the third chip performs auto-negotiation with the first chip that sends the second data; in response to the auto-negotiation result indicating that decoding is required, the third chip decodes the second data according to the second FEC code pattern , to get the decoded data.
  • the third chip decodes the second data according to the second FEC code pattern, including but not limited to: the third chip performs soft decision decoding on the second data according to the second FEC code pattern.
  • the third chip performs soft-decision decoding on the second data according to the second FEC code pattern, and obtains the decoded data, including: the third chip obtains the first sequence of the second FEC code pattern according to the second data, the first sequence of the second FEC code pattern is obtained by the third chip.
  • the sequence includes a plurality of symbols; the third chip assigns a reliability measure to each of the plurality of symbols, respectively; based on the reliability measure, the third chip determines at least one least reliable location; based on the at least one least reliable location , the third chip obtains an error pattern, and corrects the first sequence according to the error pattern; the third chip obtains the first codeword set by performing algebraic decoding on the corrected first sequence, and by performing algebraic decoding on the corrected first sequence
  • the codeword is mapped, and based on the mapping result, the third chip obtains the decoded data.
  • the third chip decodes the second data according to the second FEC code pattern, and after obtaining the decoded data, the method further includes: the third chip decodes the decoded data according to the third FEC code pattern The data is re-encoded, and the re-encoded data is transmitted. By re-encoding the decoded data according to the third FEC code pattern, the data transmission quality of the next link can be protected.
  • This embodiment of the present application does not limit the third FEC code type.
  • the third FEC code type is a second FEC code type, where the second FEC code type may be the same as the second FEC code type used to encode the second data. , and can also be other second FEC code types that satisfy the above-mentioned overhead proportional relationship and the relationship between the length of the code word and the number of logical channels to be distributed is an integer multiple.
  • the third chip decodes the second data according to the second FEC code pattern, and after obtaining the decoded data, the third chip needs to transmit the decoded data to the fourth chip, and the fourth chip needs to transmit the decoded data to the fourth chip.
  • the chip may process the received data according to the processing method of the first chip, for example, according to the process of the above steps 202 to 204, re-encode the decoded data, and transmit the re-encoded data.
  • the fourth chip may also decode the received data according to the first FEC code pattern to obtain service data.
  • the second FEC code pattern is determined based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code pattern, and the acquired first data encoded by the first FEC code pattern is passed through the second FEC code pattern.
  • the FEC code pattern is encoded again to obtain the second data of concatenated encoding, so that the second data has a higher encoding gain, and when transmitted in the channel prone to bit errors, the data with bit errors can be effectively processed. Error correction, thereby improving the quality of data transmission.
  • the implementation process of the method is relatively simple, and the efficiency of data transmission is improved.
  • this method can perform auto-negotiation between chips, according to the auto-negotiation result indicating that cascade coding is required, the process of determining the second FEC code based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type is performed. , so that the chips can actively determine whether the cascade encoding is required, and the encoding of the data transmitted in different channels is more flexible.
  • FIG. 9 is a schematic structural diagram of an apparatus for data transmission provided by an embodiment of the present application. Based on the following multiple modules shown in FIG. 9 , the apparatus for data transmission shown in FIG. 9 can perform all or part of the operations performed by the first chip. It should be understood that the apparatus may include more additional modules than the shown modules or omit a part of the modules shown therein, which is not limited in this embodiment of the present application. As shown in Figure 9, the device includes:
  • an obtaining module 901 configured to obtain first data, where the first data is data encoded by the first FEC code pattern;
  • a determination module 902 configured to determine the second FEC code pattern based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code pattern;
  • an encoding module 903 configured to encode the first data according to the second FEC code pattern to obtain the second data
  • the transmission module 904 is used for transmitting the second data.
  • the reference clock frequency of the first chip, the output rate corresponding to the first FEC code pattern, the codeword length of the second data, and the information length in the codeword of the second data satisfy an overhead proportional relationship; determine The module 902 is configured to determine the second FEC code type according to the overhead proportional relationship based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type.
  • the overhead proportional relationship includes:
  • n is the code word length of the second data
  • k is the information length in the code word of the second data
  • v 1 is the output rate corresponding to the first FEC code type
  • p is the adjustment parameter
  • f is the reference clock of the first chip frequency
  • p is a positive integer.
  • the codeword length of the second data is in an integer multiple relationship with the number of logical channels when the second data is distributed.
  • the encoding module 903 is configured to distribute the first data to obtain a plurality of first sub-data, respectively encode the plurality of first sub-data according to the second FEC code pattern to obtain a plurality of second sub-data data; the transmission module 904 is configured to transmit a plurality of second sub-data.
  • the encoding module 903 is configured to distribute the first data through the PCS channel to obtain multiple first sub-data; or distribute the first data stream through the PMA to obtain multiple first sub-data.
  • the transmission module 904 is configured to distribute the second data, obtain a plurality of third sub-data, and send the plurality of third sub-data through a plurality of logical channels.
  • the apparatus further includes: an auto-negotiation module configured to perform auto-negotiation with a third chip that receives data sent by the first chip; in response to the auto-negotiation result indicating that concatenated coding is required, a determination module 902 The second FEC pattern is determined based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC pattern.
  • the first data is data inside the first chip, or the first data is data received by the first chip and sent by the second chip.
  • FIG. 10 is a schematic structural diagram of an apparatus for data transmission provided by an embodiment of the present application. Based on the following multiple modules shown in FIG. 10 , the apparatus for data transmission shown in FIG. 10 can perform all or part of the operations performed by the third chip. It should be understood that the apparatus may include more additional modules than the shown modules or omit a part of the modules shown therein, which is not limited in this embodiment of the present application. As shown in Figure 10, the device includes:
  • a receiving module 1001 configured to receive second data, where the second data is data obtained by using the second FEC code pattern to encode the first data, and the first data is data encoded by the first FEC code pattern;
  • the decoding module 1002 is configured to decode the second data according to the second FEC code pattern to obtain decoded data.
  • the decoding module 1002 is configured to perform soft-decision decoding on the second data according to the second FEC code pattern to obtain decoded data.
  • the apparatus further includes: an encoding module for re-encoding the decoded data according to the third FEC code pattern; and a transmission module for transmitting the re-encoded data.
  • the third FEC code pattern is the first FEC code pattern or the second FEC code pattern.
  • An embodiment of the present application provides a device for data transmission.
  • the device includes: a processor coupled to a memory, where at least one program instruction or code is stored in the memory, and the at least one program instruction or code is executed by the processor Load and execute, so that the device for data transmission implements the method in the above method embodiment.
  • FIG. 11 shows a schematic structural diagram of a data transmission device 1100 provided by an exemplary embodiment of the present application, where the data transmission device 1100 is a sending side/receiving side device.
  • the data transmission device 1100 shown in FIG. 11 is configured to perform the operations involved in the data transmission method shown in the above-mentioned FIG. 2 .
  • the data transmission device 1100 is, for example, network devices such as switches, routers, and other devices (such as servers, PCs, etc.) that include this chip cascade mode.
  • the hardware structure of the data transmission device 1100 includes a communication interface 1101 and a processor 1102 .
  • the communication interface 1101 and the processor 1102 are connected through a bus 1104 .
  • the communication interface 1101 is used to obtain the first data and transmit the second data
  • the processor may store an instruction or program code. function performed.
  • the network device further includes a memory 1103, where instructions or program codes are stored in the memory 1103, and the processor 1102 is configured to call the instructions or program codes in the memory 1103 to make the network device perform the related processing of the first chip in the above method embodiments. step.
  • the device 1100 for data transmission in this embodiment of the present application may include the first chip in each of the above method embodiments, the processor 1102 in the device 1100 for data transmission reads instructions or program codes in the memory 1103, The device 1100 for data transmission shown in FIG. 11 is enabled to perform all or part of the operations performed by the first chip.
  • the device 1100 for data transmission in this embodiment of the present application includes the third chip in each of the above method embodiments, and the processor 1102 in the device 1100 for data transmission reads the instructions or program codes in the memory 1103 to make
  • the device 1100 for data transmission shown in FIG. 11 can perform all or part of the operations performed by the third chip.
  • the processor 1102 is, for example, a general-purpose central processing unit (central processing unit, CPU), a digital signal processor (digital signal processor, DSP), a network processor (network processor, NP), a graphics processing unit (graphics processing unit) , GPU), neural network processor (neural-network processing units, NPU), data processing unit (data processing unit, DPU), microprocessor or one or more integrated circuits for implementing the solution of the present application.
  • the processor 1102 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • the PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It may implement or execute the various logical blocks, modules and circuits described in connection with the disclosure of the embodiments of the present invention.
  • a processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.
  • the device 1100 for data transmission further includes a bus.
  • the bus is used to transfer information between the various components of the device 1100 for data transfer.
  • the bus may be a peripheral component interconnect (PCI for short) bus or an extended industry standard architecture (EISA for short) bus or the like.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of presentation, only one thick line is used in FIG. 11, but it does not mean that there is only one bus or one type of bus.
  • the components of the data transmission device 1100 in FIG. 11 may also be connected in other manners, and the embodiment of the present invention does not limit the connection manner of the components.
  • the memory 1103 is, for example, a read-only memory (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (random access memory, RAM) or a memory device that can store information and instructions.
  • Other types of dynamic storage devices such as electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, optical disks storage (including compact discs, laser discs, compact discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or capable of carrying or storing desired program code in the form of instructions or data structures and capable of Any other medium accessed by a computer without limitation.
  • the memory 1103 exists independently, for example, and is connected to the processor 1102 through a bus.
  • the memory 1103 may also be integrated with the processor 1102.
  • the communication interface 1101 uses any device such as a transceiver for communicating with other devices or a communication network.
  • the communication network may be Ethernet, a radio access network (RAN), or a wireless local area network (wireless local area network, WLAN).
  • the communication interface 1101 may include a wired communication interface, and may also include a wireless communication interface.
  • the communication interface 1101 may be an ethernet (ethernet) interface, a fast ethernet (FE) interface, a gigabit ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a wireless local area network ( wireless local area networks, WLAN) interfaces, cellular network communication interfaces, or a combination thereof.
  • the Ethernet interface can be an optical interface, an electrical interface or a combination thereof.
  • the communication interface 1101 may be used for the device 1100 for data transmission to communicate with other devices.
  • the processor 1102 may include one or more CPUs. Each of these processors can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the device 1100 for data transmission may include multiple processors.
  • Each of these processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU).
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the device 1100 for data transmission may further include an output device and an input device.
  • the output device communicates with the processor 1102 and can display information in a variety of ways.
  • the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, a projector, or the like.
  • the input device communicates with the processor 1102 and can receive user input in a variety of ways.
  • the input device may be a mouse, a keyboard, a touch screen device, or a sensor device, or the like.
  • the memory 1103 is used to store program codes for executing the solutions of the present application, and the processor 1102 can execute the program codes stored in the memory 1103 . That is, the device 1100 for data transmission can implement the data transmission method provided by the method embodiment through the processor 1102 and the program codes in the memory 1103 . One or more software modules may be included in the program code.
  • the processor 1102 itself may also store program codes or instructions for executing the solutions of the present application.
  • the device 1100 for data transmission in this embodiment of the present application may include the first chip in each of the above method embodiments, and the processor 1102 in the device 1100 for data transmission reads the program code or the processor in the memory 1103
  • the program codes or instructions stored in 1102 itself enable the device 1100 for data transmission shown in FIG. 11 to perform all or part of the operations performed by the first chip.
  • the device 1100 for data transmission in this embodiment of the present application may include the third chip in each of the above method embodiments, and the processor 1102 in the device 1100 for data transmission reads the program code or the processor in the memory 1103
  • the program codes or instructions stored in 1102 itself enable the device 1100 for data transmission shown in FIG. 11 to perform all or part of the operations performed by the third chip.
  • the apparatus 1100 for data transmission may also correspond to the apparatuses shown in FIGS. 9 and 10 above, and each functional module in the apparatuses shown in FIGS. 9 and 10 is implemented by software of the apparatus 1100 for data transmission.
  • the functional modules included in the apparatuses shown in FIGS. 9 and 10 are generated after the processor 1102 of the data transmission device 1100 reads the program codes stored in the memory 1103 .
  • each step of the data transmission method shown in FIG. 2 is completed by the hardware integrated logic circuit in the processor of the data transmission device 1100 or the instructions in the form of software.
  • the steps of the methods disclosed in conjunction with the embodiments of the present application may be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
  • the software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware, which will not be described in detail here to avoid repetition.
  • An embodiment of the present application further provides a data transmission system, the system includes: a first data transmission device and a second data transmission device; the first data transmission device is used to execute the first data transmission device shown in FIG. 2 .
  • the second data transmission device is used to execute the method executed by the third chip shown in FIG. 2 .
  • processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (digital signal processing, DSP), application specific integrated circuits (application specific integrated circuits, ASIC), field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or any conventional processor or the like. It should be noted that the processor may be a processor supporting an advanced RISC machine (ARM) architecture.
  • ARM advanced RISC machine
  • the above-mentioned memory may include read-only memory and random access memory, and provide instructions and data to the processor.
  • the memory may also include non-volatile random access memory.
  • the memory may also store device type information.
  • the memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM), which acts as an external cache. By way of example and not limitation, many forms of RAM are available.
  • SRAM static RAM
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • double data rate synchronous dynamic random access Memory double data date SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • synchronous link dynamic random access memory direct memory bus random access memory
  • direct rambus RAM direct rambus RAM
  • a computer-readable storage medium is also provided, and at least one program instruction or code is stored in the storage medium.
  • the program instruction or code is loaded and executed by the processor, the computer realizes the method for data transmission as shown in FIG. 2 above. .
  • the present application provides a computer program.
  • the processor or the computer can execute the corresponding steps and/or processes in the foregoing method embodiments.
  • a chip including a processor for invoking and executing instructions stored in a memory to cause a device on which the chip is installed to perform the methods of the above aspects.
  • Another chip including: an input interface, an output interface, a processor, and a memory, the input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the processor is used to execute all The code in the memory, when the code is executed, the processor is configured to perform the methods of the above aspects.
  • a device comprising the chip described in any one of the above solutions.
  • a device comprising the first chip described in any one of the above solutions, and/or the third chip described in any one of the above solutions.
  • the second chip may be a transmitting-side device, such as a physical layer (PHY) chip in a router, switch, or server, and the first chip may be an interface of the transmitting-side device, such as an optical module chip or CDR/retimer chip.
  • the third chip may be an interface of the receiving-side device, such as a chip in an optical module or a CDR/retimer chip, and the fourth chip may be a physical layer (PHY) chip in the receiving-side device.
  • the PHY chip may be a chip located on a single board of a computing device, and the chip may be a CPU, a network processor (NP), a neural network processing unit (NPU), a field programmable logic gate One or any combination of field programmable gate array (FPGA), programmable logic controller (PLC), etc.
  • NP network processor
  • NPU neural network processing unit
  • FPGA field programmable logic controller
  • the first chip and the second chip communicate through AUI; in some embodiments, the third chip and the fourth chip communicate through AUI.
  • the confidence (also called reliability) of each bit in the received codeword is first calculated based on the received quantized soft decision information, and a confidence sequence is obtained, from which the M least likely to be selected.
  • Reliable bit positions, in the M least reliable bit positions try all combinations of 0, 1, 2, .
  • Perform hard decoding and error correction on each test codeword then calculate the Euclidean distance between all corrected test codewords and the confidence sequence, and select the corrected test codeword corresponding to the smallest distance as the final post-correction codeword output. If there is no correctable codeword in the test codeword, the hard decision result corresponding to the original received codeword is used as the output codeword.
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions when loaded and executed on a computer, result in whole or in part of the processes or functions described herein.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, optical fiber, digital subscriber line) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes an integration of one or more available media.
  • the available media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media (eg, solid state disks), and the like.
  • the computer program product includes one or more computer program instructions.
  • the methods of the embodiments of the present application may be described in the context of machine-executable instructions, such as included in program modules executed in a device on a target's real or virtual processor.
  • program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data structures.
  • the functionality of the program modules may be combined or divided among the described program modules.
  • Machine-executable instructions for program modules may be executed within local or distributed devices. In a distributed facility, program modules may be located in both local and remote storage media.
  • Computer program code for implementing the methods of the embodiments of the present application may be written in one or more programming languages. Such computer program code may be provided to a processor of a general purpose computer, special purpose computer or other programmable data processing apparatus such that the program code, when executed by the computer or other programmable data processing apparatus, causes the flowchart and/or block diagrams The functions/operations specified in are implemented.
  • the program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.
  • computer program code or related data may be carried by any suitable carrier to enable a device, apparatus or processor to perform the various processes and operations described above.
  • suitable carriers include signals, computer-readable media, and the like.
  • Examples of signals may include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.
  • a machine-readable medium may be any tangible medium that contains or stores a program for or in connection with an instruction execution system, apparatus, or device.
  • the machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or devices, or any suitable combination thereof. More detailed examples of machine-readable storage media include electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only Memory (EPROM or flash memory), optical storage devices, magnetic storage devices, or any suitable combination thereof.
  • the disclosed systems, devices and methods may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the modules is only a logical function division. In actual implementation, there may be other division methods.
  • multiple modules or components may be combined or Integration into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or modules, and may also be electrical, mechanical or other forms of connection.
  • modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, may be located in one place, or may be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solutions of the embodiments of the present application.
  • each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically alone, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules.
  • the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may be stored in a computer-readable storage medium.
  • the technical solutions of the present application are essentially or part of contributions to the prior art, or all or part of the technical solutions can be embodied in the form of software products, and the computer software products are stored in a storage medium , including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program codes .
  • first, second and other words are used to distinguish the same or similar items with basically the same function and function, and it should be understood that between “first”, “second” and “nth” There are no logical or timing dependencies, and no restrictions on the number and execution order. It will also be understood that, although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another.
  • a first network device may be referred to as a second network device, and similarly, a second network device may be referred to as a first network device, without departing from the scope of various described examples.
  • Both the first network and device and the second network device may be network devices, and in some cases may be separate and distinct network devices.
  • the size of the sequence number of each process does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not be used in the embodiment of the present application. Implementation constitutes any limitation.
  • the meaning of the term “at least one” refers to one or more, and the meaning of the term “plurality” in this application refers to two or more.
  • a plurality of second messages refers to two or more more than one second message.
  • system and “network” are often used interchangeably herein.
  • determining B according to A does not mean that B is only determined according to A, and B may also be determined according to A and/or other information.
  • references throughout the specification to "one embodiment,” “an embodiment,” and “one possible implementation” mean that a particular feature, structure, or characteristic associated with the embodiment or implementation is included herein. in at least one embodiment of the application. Thus, appearances of "in one embodiment” or “in an embodiment” or “one possible implementation” in various places throughout this specification are not necessarily necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

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Abstract

本申请公开了数据传输的方法、装置、设备、系统及计算机可读存储介质。该数据传输的方法包括：第一芯片获取采用第一FEC码型编码的第一数据，基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型；按照第二FEC码型对第一数据进行编码得到第二数据，传输第二数据；第三芯片接收该第二数据，按照第二FEC码型对第二数据进行解码，得到解码后的数据。该方法能够使传输的数据具有更高的编码增益，在容易出现误码的通道中传输时，能够对出现误码的数据进行有效的纠错，从而提高数据传输的质量。

Description

数据传输的方法、装置、设备、系统及计算机可读存储介质
本申请要求于2021年1月25日提交的申请号为202110099748.1、发明名称为“编解码方法、设备及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中；本申请还要求于2021年2月10日提交的申请号为202110185631.5、发明名称为“数据传输的方法、装置、设备、系统及可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信技术领域，尤其涉及一种数据传输的方法、装置、设备、系统及计算机可读存储介质。
背景技术
前向纠错码(forward error correction，FEC)是一种通过为被传递的数据提供校验位，提高信道中的数据传输速率以及传输距离的数据编码方法。在数据传输过程中，发送端通过特定的FEC码型将原始数据进行编码，将编码后的数据发送至接收端，接收端通过相同的FEC码型将接收的数据进行解码，得到原始数据。
发明内容
本申请提出一种数据传输的方法、装置、设备、系统及计算机可读存储介质，用于对FEC码型进行增强，以适配高速率和/或远距离的数据传输。
第一方面，提供了一种数据传输的方法，该方法包括：第一芯片获取采用第一FEC码型编码的第一数据；基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型；之后，该第一芯片按照第二FEC码型对第一数据进行编码，得到第二数据，传输该第二数据。
该方法基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型，将获取的采用第一FEC码型编码的第一数据通过第二FEC码型进行再一次编码，得到级联编码的第二数据，使该第二数据具有更高的编码增益，在容易出现误码的通道中传输时，能够对出现误码的数据进行有效的纠错，从而提高数据传输的质量。其次，由于第二数据为在第一数据的基础上直接编码获得的数据，该方法的实现过程较为简便，提高了数据传输的效率。
在一种可能的实现方式中，所述第一芯片的参考时钟频率、所述第一FEC码型对应的输出速率与所述第二数据的码字长度以及所述第二数据的码字内信息长度满足开销比例关系；所述基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型，包括：基于所述第一芯片的参考时钟频率及所述第一FEC码型对应的输出速率，按照所述开销比例关系确定所述第二FEC码型。通过按照开销比例关系来确定第二FEC码型，可以保证采用第二FEC码型编码后的开销，进一步提高了数据传输的性能。
在一种可能的实现方式中，所述开销比例关系，包括：
Figure PCTCN2022073180-appb-000001
其中，所述n为第二数据的码字长度，所述k为所述第二数据的码字内信息长度，所述v 1为所述第一FEC码型对应的输出速率，所述p为调整参数，所述f为所述第一芯片的参考时钟频率，所述p为正整数。
在一种可能的实现方式中，所述第二数据的码字长度与所述第二数据被分发时的逻辑通道数量成整数倍关系。在确定第二FEC码型时，通过考虑该整数倍关系，使得确定出的第二FEC码型更加适合传输场景，提高了数据传输的性能。
在一种可能的实现方式中，所述第一芯片按照所述第二FEC码型对所述第一数据进行编码，得到第二数据，包括：所述第一芯片分发所述第一数据得到多个第一子数据，所述第一芯片按照所述第二FEC码型分别对所述多个第一子数据进行编码，得到多个第二子数据；所述第一芯片传输所述第二数据，包括：所述第一芯片对所述多个第二子数据进行传输。
在一种可能的实现方式中，所述第一芯片分发所述第一数据得到多个第一子数据，包括：所述第一芯片通过物理编码子层PCS通道分发所述第一数据得到多个第一子数据；或者，所述第一芯片通过物理介质接入子层PMA分发所述第一数据流得到多个第一子数据。
在一种可能的实现方式中，所述第一芯片传输所述第二数据，包括：所述第一芯片对所述第二数据进行分发，得到多个第三子数据，通过多条逻辑通道发送所述多个第三子数据。
在一种可能的实现方式中，所述基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型之前，所述方法还包括：所述第一芯片与接收所述第一芯片发送的数据的第三芯片进行自协商；响应于自协商结果指示需要级联编码，所述第一芯片执行所述基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型。通过自协商来确定是否进行级联编码，适用性更强，更加符合实际场景需求。
在一种可能的实现方式中，所述第一数据为所述第一芯片内部的数据，或所述第一数据为所述第一芯片接收的由第二芯片发送的数据。由于第一数据可以为第一芯片内部的数据，也可以为接收的其他芯片传输的数据，该方法应用的数据传输场景较为灵活。
第二方面，提供了一种数据传输的方法，该方法包括：第三芯片接收第二数据，所述第二数据为采用第二前向纠错码FEC码型对第一数据进行编码得到的数据，所述第一数据为采用第一FEC码型编码的数据；所述第三芯片按照所述第二FEC码型对所述第二数据进行解码，得到解码后的数据。由于第二数据是对第一数据采用第二FEC码型编码得到的，而第一数据又是采用第一FEC码型编码得到的，因而第三芯片收到的第二数据的编码增益更高，纠错能力更高，通过对该第二数据进行解码，得到的解码后的数据的准确性更高。
在一种可能的实现方式中，所述第三芯片按照所述第二FEC码型对所述第二数据进行解码，包括：所述第三芯片按照所述第二FEC码型对所述第二数据进行软判决解码。
在一种可能的实现方式中，所述第三芯片按照所述第二FEC码型对所述第二数据进行解码，得到解码后的数据之后，所述方法还包括：所述第三芯片按照第三FEC码型对所述解码后的数据进行再次编码，传输经过再次编码后的数据。通过按照第三FEC码型对解码后的数据进行再次编码，可以保护下一段链路的数据传输质量。
在一种可能的实现方式中，所述第三FEC码型为所述第二FEC码型。
第三方面，提供了一种数据传输的装置，所述装置包括：
获取模块，用于获取第一数据，所述第一数据为采用第一前向纠错码FEC码型编码的数据；
确定模块，用于基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型；
编码模块，用于按照所述第二FEC码型对所述第一数据进行编码，得到第二数据；
传输模块，用于传输所述第二数据。
在一种可能的实现方式中，所述第一芯片的参考时钟频率、所述第一FEC码型对应的输出速率与所述第二数据的码字长度以及所述第二数据的码字内信息长度满足开销比例关系；所述确定模块，用于基于所述第一芯片的参考时钟频率及所述第一FEC码型对应的输出速率，按照所述开销比例关系确定所述第二FEC码型。
在一种可能的实现方式中，所述开销比例关系，包括：
Figure PCTCN2022073180-appb-000002
其中，所述n为第二数据的码字长度，所述k为所述第二数据的码字内信息长度，所述v 1为所述第一FEC码型对应的输出速率，所述p为调整参数，所述f为所述第一芯片的参考时钟频率，所述p为正整数。
在一种可能的实现方式中，所述第二数据的码字长度与所述第二数据被分发时的逻辑通道数量成整数倍关系。
在一种可能的实现方式中，所述编码模块，用于分发所述第一数据得到多个第一子数据，按照所述第二FEC码型分别对所述多个第一子数据进行编码，得到多个第二子数据；所述传输模块，用于对所述多个第二子数据进行传输。
在一种可能的实现方式中，所述编码模块，用于通过物理编码子层PCS通道分发所述第一数据得到多个第一子数据；或者，通过物理介质接入子层PMA分发所述第一数据流得到多个第一子数据。
在一种可能的实现方式中，所述传输模块，用于对所述第二数据进行分发，得到多个第三子数据，通过多条逻辑通道发送所述多个第三子数据。
在一种可能的实现方式中，所述装置还包括：自协商模块，用于与接收所述第一芯片发送的数据的第三芯片进行自协商；响应于自协商结果指示需要级联编码，所述确定模块执行所述基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型。
在一种可能的实现方式中，所述第一数据为所述第一芯片内部的数据，或所述第一数据为所述第一芯片接收的由第二芯片发送的数据。
第四方面，提供了一种数据传输的装置，所述装置包括：
接收模块，用于接收第二数据，所述第二数据为采用第二前向纠错码FEC码型对第一数据进行编码得到的数据，所述第一数据为采用第一FEC码型编码的数据；
解码模块，用于按照所述第二FEC码型对所述第二数据进行解码，得到解码后的数据。
在一种可能的实现方式中，所述解码模块，用于按照所述第二FEC码型对所述第二数据进行软判决解码，得到解码后的数据。
在一种可能的实现方式中，所述装置还包括：编码模块，用于按照第三FEC码型对所述解码后的数据进行再次编码；传输模块，用于传输经过再次编码后的数据。
在一种可能的实现方式中，所述第三FEC码型为所述第二FEC码型。
第五方面，提供了一种数据传输的设备，该设备包括：处理器，处理器与存储器耦合，存储器中存储有至少一条程序指令或代码，至少一条程序指令或代码由处理器加载并执行，以使设备实现如第一方面或第二方面中任一的数据传输的方法。
第六方面，提供了一种数据传输的系统，该系统包括：第一数据传输的设备，用于执行上述第一方面或第一方面任一所述的方法，第二数据传输的设备，用于执行上述第二方面或第二方面任一所述的方法。
第七方面，提供了一种计算机可读存储介质，该计算机可读存储介质中存储有至少一条程序指令或代码，程序指令或代码由处理器加载并执行时以使计算机实现如第一方面或第二方面中任一的数据传输的方法。
提供了另一种通信装置，该装置包括：通信接口、存储器和处理器。其中，该存储器和该处理器通过内部连接通路互相通信，该存储器用于存储指令，该处理器用于执行该存储器存储的指令，以控制通信接口接收数据，并控制通信接口发送数据，并且当该处理器执行该存储器存储的指令时，使得该处理器执行第一方面或第一方面的任一种可能的实施方式中的方法，或者执行第二方面或第二方面的任一种可能的实施方式中的方法。
作为一种示例性实施例，所述处理器为一个或多个，所述存储器为一个或多个。
作为一种示例性实施例，所述存储器可以与所述处理器集成在一起，或者所述存储器与处理器分离设置。
在具体实现过程中，存储器可以为非瞬时性(non-transitory)存储器，例如只读存储器(read only memory，ROM)，其可以与处理器集成在同一块芯片上，也可以分别设置在不同的芯片上，本申请实施例对存储器的类型以及存储器与处理器的设置方式不做限定。
提供了一种计算机程序(产品)，所述计算机程序(产品)包括：计算机程序代码，当所述计算机程序代码被计算机运行时，使得所述计算机执行上述各方面中的方法。
提供了一种芯片，包括处理器，用于从存储器中调用并运行所述存储器中存储的指令，使得安装有所述芯片的设备执行上述各方面中的方法。
提供另一种芯片，包括：输入接口、输出接口、处理器和存储器，所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连，所述处理器用于执行所述存储器中的代码，当所述代码被执行时，所述处理器用于执行上述各方面中的方法。
提供一种设备，包括上述方案中任一所述的芯片。
提供一种设备，包括上述方案中任一所述的第一芯片，和/或，上述方案中任一所述的第三芯片。
在以上实施例中，软解码时，先基于接收的量化软判决信息计算接收码字中的每个比特的置信度(也称可靠度，reliability)，获得置信度序列，从中选取M个最不可靠比特位置，在这M个最不可靠比特位置中，依次尝试对0，1，2，…，N(N≤M)个比特位置取反的所有组合，即得到多个测试码字，并对每个测试码字进行硬解码纠错，然后计算所有已纠正的测试码字与置信度序列的欧氏距离，选择最小距离对应的已纠正测试码字作为最终纠后码字输出。如果测试码字中没有可纠码字，则将原始接收码字对应的硬判决结果作为输出码字。
附图说明
图1是本申请实施例提供的一种数据传输的方法的实施场景示意图；
图2是本申请实施例提供的一种数据传输的方法流程图；
图3是本申请实施例提供的一种按照第二FEC码型对第一数据进行编码的示意图；
图4是本申请实施例提供的一种对第一数据进行分发的示意图；
图5是本申请实施例提供的一种通过PCS通道对第一数据进行分发的示意图；
图6是本申请实施例提供的一种对第二数据进行分发的示意图；
图7是本申请实施例提供的另一种对第二数据进行分发的示意图；
图8是本申请实施例提供的另一种数据传输的方法的实施场景示意图；
图9是本申请实施例提供的一种数据传输的装置的结构示意图；
图10是本申请实施例提供的另一种数据传输的装置的结构示意图；
图11是本申请实施例提供的一种数据传输的设备的结构示意图。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。下面结合附图，对本发明的实施例进行描述。
在通信技术领域中，通过使用FEC对数据进行编码，是降低数据传输过程中的误码率，进而提高数据传输质量的重要技术手段。而对于链路速率提高、信道更为挑战的场景，可能需要更高编码增益的FEC。例如，对于800吉比特以太网(gigabyte ethernet，GE)/1.6太比特以太网(trillion-byte ethernet，TE)的以太接口，或者200G第四代脉冲幅度调制(4 pulse amplitude modulation，PAM4)光链路等，更高速率的传输往往面对更为严苛的信道和误码率要求，而更强的FEC可以在纠前误码率升高之后，使纠后的误码率保持在一个好的水平。对此，本申请实施例提供了一种数据传输的方法，该方法基于传输数据的第一芯片的参考时钟频率(reference clock frequency)以及第一FEC码型对应的输出速率确定第二FEC码型，将获取的采用第一FEC码型编码的第一数据通过第二FEC码型进行再一次编码，得到级联编码的第二数据，使该第二数据具有更高的编码增益，在容易出现误码的通道中传输时，能够对出现误码的数据进行有效的纠错，从而提高数据传输的质量。其次，由于第二数据为在第一数据的基础上直接编码获得的数据，该方法的实现过程较为简便，提高了数据传输的效率。此外，级联编码的过程可在一定触发条件下执行，例如，该方法通过芯片之间进行自协商，根据自协商结果指示需要级联编码，执行基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码的过程，使芯片之间能够主动确定是否需要进行级联编码的过程，对于在不同通道中传输的数据的编码更为灵活。
本申请实施例的方法可适用于当前的以太接口或者其他需要传输数据的场景下，以图1所示的实施场景为例，该实施场景包括多个芯片，各个芯片之间能够进行信息的交互，实现数据的传输。如图1所示，第一芯片101与第二芯片102之间，第一芯片101与第三芯片103之间均可以进行数据的传输。需要说明的是，如图1所示的实施场景可以包括N个芯片，N为大于等于2的正整数，图1中仅以芯片数量为3个为例进行说明。
结合图1所示的实施场景，本申请实施例提供的数据传输的方法如图2所示，包括但不限于步骤201至步骤206。
步骤201、第一芯片获取第一数据，第一数据为采用第一FEC码型编码的数据。
在一种可能的实现方式中，第一数据为第一芯片内部的数据，或为第一芯片接收的由第二芯片发送的数据。示例性地，第一芯片采用第一FEC码型对原始数据进行编码得到第一数据，或第二芯片采用第一FEC码型对原始数据进行编码得到编码后的数据，第二芯片对该编码后的数据进行扰码形成第一数据，第一芯片接收由第二芯片发送的第一数据。示例性地，第二芯片通过物理通道将第一数据发送至第一芯片。无论第一数据是第一芯片内部的数据，还是由第二芯片发送的数据，该第一数据除了采用第一FEC编码外，还可以经过了其他处理。例如，该第一数据是由第二芯片经过物理介质接入子层(physical medium attachment sublayer，PMA)，和/或，物理介质关联层接口(physical media dependent，PMD)之后发送至第一芯片的数据，也可以是在第一芯片内部经过PMA和/或物理编码子层(physical coding sublayer，PCS)之后的数据。此外，该第一数据还可以是经过其他处理的数据，例如该第一数据是经过交织、分发之后得到的数据。
本申请实施例不对第一FEC码型进行限定，在一种可能的实现方式中，第一FEC码型为里德-所罗门(Reed-Solomon，RS)码、博斯-乔赫里-霍克文黑姆(Bose-Chaudhuri-Hocquenghem，BCH)码、法尔(fire)码、涡轮(turbo)码、涡轮乘积码(turbo product code，TPC)、阶梯(staircase)码以及低密度奇偶校验(low-density parity-check，LDPC)码中的任一种。
此外，第一芯片接收到第一数据后，可直接传输该第一数据，为了提高数据传输的质量，也可以对第一数据进行再次编码，本申请实施例不对第一芯片进行级联编码的触发方式进行限定。在一种可能的实现方式中，第一芯片与接收第一芯片发送的数据的第三芯片进行自协商；响应于自协商结果指示需要级联编码，第一芯片执行基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型。该自协商过程可以在接收到第一数据之后执行，也可以在执行该方法之前执行，本申请实施例不对自协商的时机进行限定，在传输第一数据前进行自协商即可。
步骤202、基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型。
在一种可能的实现方式中，第一芯片的参考时钟频率、第一FEC码型对应的输出速率与第二数据的码字长度以及第二数据的码字内信息长度满足开销比例关系；基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型，包括：基于第一芯片的参考时钟频率及第一FEC码型对应的输出速率，按照开销比例关系确定第二FEC码型。通过按照开销比例关系来确定第二FEC码型，可以保证采用第二FEC码型编码后的开销，进一步提高了数据传输的性能。
在一种可能的实现方式中，该开销比例关系，包括：
Figure PCTCN2022073180-appb-000003
其中，n为第二数据的码字长度，k为第二数据的码字内信息长度，v 1为第一FEC码型对应的输出速率，p为调整参数，f为第一芯片的参考时钟频率，p为正整数。
需要说明的是，n、k、p存在不同组合，能够满足上述开销比例关系即可。示例性地，该调整参数为参考值，例如，调整参数为10的整数倍或20的整数倍；基于该参考值，确定满足开销比例关系的第二FEC码型。
示例性地，以第一FEC码型为RS(544，514)，第一芯片的参考时钟频率为156.25兆赫(MHz)，第一FEC码型对应的输出速率为106.25吉比特/秒(Gbps)为例进行说明；例如，当p＝705时，n＝282，k＝272；当p＝720时，n＝144，k＝136，或n＝180，k＝170。又例如，若调整参数为720，则n＝144，k＝136，或n＝180，k＝170。
在一种可能的实现方式中，按照开销比例关系确定第二FEC码型时，可以参照表一确定第二FEC码型，其中，表一中的码型均属于BCH码。
表一
Figure PCTCN2022073180-appb-000004
在上述表一中，n为码字长度，k为码字内信息长度，m表示该编码所处的有限域(finite filed)或者伽罗华域(Galois Field)为GF(2 m)，t为纠错能力。例如，BCH(180，170，m＝10，t＝1)表示该BCH码型的码字长度为180比特(bit)，该长度中包括0个扩展的比特(extended bit)，码字内信息长度为170bit，m＝10，纠错能力为1；eBCH(161+1，153，m＝8，t＝1)表示该BCH码型为包括extended bit的BCH码型，码字长度为162bit，该长度中包括1个extended bit，m＝8，纠错能力为1。表一中的其他BCH码型与上述BCH码型原理相同，此处不再赘述。
在一种可能的实现方式中，第二数据的码字长度与第二数据被分发时的逻辑通道数量成整数倍关系。其中，该逻辑通道可以为PCS通道或FEC通道。在确定第二FEC码型时，通过考虑该整数倍关系，使得确定出的第二FEC码型更加适合传输场景，提高了数据传输的性能。示例性地，当第二数据被分发时的逻辑通道数量为8时，第二数据的码字长度为8的整数倍。当然，该逻辑通道的数量也可以为1，即第二数据的通过1条逻辑通道传输，由于第二数据的码字长度为正整数，第二数据的码字长度也与被分发的逻辑通道数量成整数倍关系。
综上，基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型的方式包括但不限于如下三种方式。
方式一、第一芯片先基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率按照开销比例关系确定第一集合，该第一集合中包括多个满足开销比例关系的FEC码型；再按照码字长度与分发时的逻辑通道成整数倍关系，从第一集合中确定第二FEC码型。
方式二、第一芯片先按照码字长度与分发时的逻辑通道成整数倍关系确定第二集合，该第二集合中包括多个满足整数倍关系的FEC码型；再基于第一芯片的参考时钟频率以及第一 FEC码型对应的输出速率按照开销比例关系，从第二集合中确定第二FEC码型。
方式三、第一芯片先基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率按照开销比例关系确定第一集合，该第一集合中包括多个满足开销比例关系的FEC码型；再按照码字长度与分发时的逻辑通道成整数倍关系确定第二集合，该第二集合中包括多个满足整数倍关系的FEC码型；基于第一集合与第二集合确定第二FEC码型。例如，基于第一集合与第二集合的交集，第一芯片确定第二FEC码型。
需要说明的是，第二FEC码型可以为RS码、BCH码、法尔码、涡轮码、涡轮乘积码、阶梯码以及LDPC码中的任一种，本申请实施例对第二FEC码型的类型不做限定。
步骤203、第一芯片按照第二FEC码型对第一数据进行编码，得到第二数据。
在一种可能的实现方式中，若第一数据为第一芯片内部的数据，第一芯片对该第一数据按照第二FEC码型进行编码，得到第二数据；若第一数据为第一芯片接收的由第二芯片发送的数据，第一芯片可以对该数据直接按照第二FEC码型进行编码，得到第二数据。需要说明的是，第一芯片可以对接收到的数据进行除解码外的简单操作，例如比特复用(bit mux)或者比特解复用(bit demux)等。
示例性地，如果第一数据为单个数据，第一芯片按照第二FEC码型对第一数据进行编码，得到第二数据，其中，该第一数据可以为第一芯片直接接收的数据，或为经由第一芯片分发为多个子数据后，对该多个子数据进行交织得到的数据。该种情况下，将第一数据作为一个整体，采用第二FEC码型对第一数据进行编码。可选地，如果第一数据是多个，例如是从第二芯片发送的多个第一数据，则第一芯片按照第二FEC码型分别对每个第一数据进行编码，得到多个第二数据。如图3所示，第一芯片通过附件单元接口(attachment unit interface，AUI)接收第三数据，通过物理介质接入子层(physical medium attachment sublayer，PMA)处理，得到多个第一数据，第一芯片分别对该多个第一数据进行编码，得到多个第二数据。得到的多个第二数据可通过多个物理通道(图5中的物理通道1-N)传输，之后经过PMA和物理介质关联层接口(physical media dependent，PMD)等向外传输。在一些实施例中，图3中，第二芯片可以是网络设备，比如路由器、交换机中的物理层(PHY)芯片，第一芯片可以是光模块中的芯片，或者时钟数据恢复(clock data recovery，CDR)/重定时(retimer)芯片。所述PHY芯片可以是位于网络设备的单板上的芯片，该芯片可以是中央处理器(central processing unit，CPU)、网络处理器(network processor，NP)、神经网络处理单元(neural network processing unit，NPU)、现场可编程逻辑门阵列(field programmable gate array，FPGA)、可编程逻辑控制器(programmable logic controller，PLC)等中的一个或其任意组合。
在一种可能的实现方式中，无论是一个第一数据，还是多个第一数据，第一芯片按照第二FEC码型对第一数据进行编码，得到第二数据，包括：第一芯片分发第一数据得到多个第一子数据，第一芯片按照第二FEC码型分别对多个第一子数据进行编码，得到多个第二子数据。例如，该过程可如图4所示。
示例性地，第一芯片分发第一数据得到多个第一子数据的方式包括但不限于如下两种方式。
方式一、第一芯片通过逻辑通道分发第一数据得到多个第一子数据。
示例性地，第一芯片通过N条逻辑通道分发第一数据得到多个第一子数据，其中，每条逻辑通道用于传输一个第一子数据，该逻辑通道可以为PCS通道或FEC通道。第一芯片按照 第二FEC码型分别对多个第一子数据进行编码，得到多个第二子数据。例如，该过程可如图5所示，得到的多个第二子数据可分别经过PMA和PMD等向外传输。
方式二、第一芯片通过PMA分发第一数据得到多个第一子数据。
步骤204、第一芯片传输第二数据。
其中，第一芯片通过逻辑通道传输第二数据，该逻辑通道可以为PCS通道或FEC通道。在一种可能的实现方式中，针对数据传输的通道数量情况，第一芯片传输第二数据包括但不限于如下两种情况。
情况一、通道数量为1。
针对情况一，第一芯片通过该条通道传输第二数据，该第二数据可以为单个数据，或包括多个第二子数据。
情况二、通道数量为大于等于2的正整数。
针对情况二，第一芯片对第二数据进行分发，得到多个第三子数据，通过多条逻辑通道发送该多个第三子数据。示例性地，第一芯片通过轮询对该第二数据进行分发。示例性地，如图6所示，逻辑通道数量为N条，N为大于等于2的正整数，第一芯片通过轮询对该第二数据进行分发，得到N个第三子数据，通过N条逻辑通道发送该N个第三子数据。示例性地，N条逻辑通道分别对应发送一个第三子数据。该N个第三子数据包括但不限于经过PMA以及PMD发送至下一芯片。
示例性地，若第一数据为单个数据，第一芯片对该单个第一数据采用第二FEC码型编码得到第二数据之后，将该第二数据进行分发，得到多个第三子数据，通过多条逻辑通道发送该多个第三子数据；若第一数据分发为多个第一子数据，对于多个第一子数据中的任一第一子数据采用第二FEC码型编码得到第二子数据，第一芯片对多个第二子数据进行分发，得到多个第三子数据，通过多条逻辑通道发送该多个第三子数据。例如，第一芯片通过轮询对该多个第二子数据中的任一第二子数据进行分发。以如图7所示的系统为例，通过第二FEC码型编码得到多个第二子数据，对于每个第二子数据，第一芯片对该第二子数据进行分发得到N个第三子数据，N为大于等于2的正整数，通过N条逻辑通道分发该多个第三子数据。示例性地，N条逻辑通道分别对应发送一个第三子数据。
上述步骤201至步骤204均为第一芯片侧执行该数据传输的过程，接下来，以第三芯片侧为例，对数据传输的方法进行说明。
步骤205、第三芯片接收第二数据，第二数据为采用第二FEC码型对第一数据进行编码得到的数据，第一数据为采用第一FEC码型编码的数据。
在一种可能的实现方式中，第三芯片通过逻辑通道接收由第一芯片发送的第二数据。
步骤206、第三芯片按照第二FEC码型对第二数据进行解码，得到解码后的数据。
由于第二数据是对第一数据采用第二FEC码型编码得到的，而第一数据又是采用第一FEC码型编码得到的，因而第三芯片收到的第二数据的编码增益更高，纠错能力更高，通过对该第二数据进行解码，得到的解码后的数据的准确性更高。
在一种可能的实现方式中，第三芯片与发送第二数据的第一芯片进行自协商；响应于自协商结果指示需要进行解码，第三芯片按照第二FEC码型对第二数据进行解码，得到解码后的数据。
第三芯片按照第二FEC码型对第二数据进行解码，包括但不限于：第三芯片按照第二 FEC码型对第二数据进行软判决解码。示例性地，第三芯片按照第二FEC码型对第二数据进行软判决解码，得到解码后的数据，包括：第三芯片根据第二数据得到第二FEC码型的第一序列，第一序列包括多个码元；第三芯片分别为多个码元中的每个码元分配可靠性量度；基于可靠性量度，第三芯片确定至少一个最不可靠位置；基于至少一个最不可靠位置，第三芯片得到错误图样，根据该错误图样对第一序列进行修正；第三芯片通过对修正后的第一序列进行代数译码，得到第一码字集合，通过对第一码字集合中的码字进行映射，基于映射结果，第三芯片得到解码后的数据。
在一种可能的实现方式中，第三芯片按照第二FEC码型对第二数据进行解码，得到解码后的数据之后，该方法还包括：第三芯片按照第三FEC码型对解码后的数据进行再次编码，传输经过再次编码后的数据。通过按照第三FEC码型对解码后的数据进行再次编码，可以保护下一段链路的数据传输质量。本申请实施例不对第三FEC码型进行限定，例如，该第三FEC码型为第二FEC码型，其中，该第二FEC码型可以与上述编码第二数据的第二FEC码型相同，也可以为满足上述开销比例关系以及码字长度与被分发的逻辑通道数量成整数倍关系的其他第二FEC码型。
示例性地，如图8所示，第三芯片按照第二FEC码型对第二数据进行解码，得到解码后的数据之后，第三芯片需要将解码后的数据传输至第四芯片，第四芯片可以按照第一芯片的处理方式来处理接收到的数据，例如按照上述步骤202至步骤204的过程，对解码后的数据进行再次编码，传输经过再次编码的数据。可选地，第四芯片也可以按照第一FEC码型对接收到的数据进行解码，获得业务数据。
本申请实施例提供的方法，基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型，将获取的采用第一FEC码型编码的第一数据通过第二FEC码型进行再一次编码，得到级联编码的第二数据，使该第二数据具有更高的编码增益，在容易出现误码的通道中传输时，能够对出现误码的数据进行有效的纠错，从而提高数据传输的质量。
其次，由于第二数据为在第一数据的基础上直接编码获得的数据，该方法的实现过程较为简便，提高了数据传输的效率。
此外，由于该方法能够通过芯片之间进行自协商，根据自协商结果指示需要级联编码，执行基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码的过程，使芯片之间能够主动确定是否需要进行级联编码的过程，对于在不同通道中传输的数据的编码更为灵活。
本申请实施例还提供了一种数据传输的装置。图9是本申请实施例提供的一种数据传输的装置的结构示意图。基于图9所示的如下多个模块，该图9所示的数据传输的装置能够执行第一芯片所执行的全部或部分操作。应理解到，该装置可以包括比所示模块更多的附加模块或者省略其中所示的一部分模块，本申请实施例对此并不进行限制。如图9所示，该装置包括：
获取模块901，用于获取第一数据，第一数据为采用第一FEC码型编码的数据；
确定模块902，用于基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型；
编码模块903，用于按照第二FEC码型对第一数据进行编码，得到第二数据；
传输模块904，用于传输第二数据。
在一种可能的实现方式中，第一芯片的参考时钟频率、第一FEC码型对应的输出速率与第二数据的码字长度以及第二数据的码字内信息长度满足开销比例关系；确定模块902，用于基于第一芯片的参考时钟频率及第一FEC码型对应的输出速率，按照开销比例关系确定第二FEC码型。
在一种可能的实现方式中，该开销比例关系，包括：
Figure PCTCN2022073180-appb-000005
其中，n为第二数据的码字长度，k为第二数据的码字内信息长度，v 1为第一FEC码型对应的输出速率，p为调整参数，f为第一芯片的参考时钟频率，p为正整数。
在一种可能的实现方式中，第二数据的码字长度与第二数据被分发时的逻辑通道数量成整数倍关系。
在一种可能的实现方式中，编码模块903，用于分发第一数据得到多个第一子数据，按照第二FEC码型分别对多个第一子数据进行编码，得到多个第二子数据；传输模块904，用于对多个第二子数据进行传输。
在一种可能的实现方式中，编码模块903，用于通过PCS通道分发第一数据得到多个第一子数据；或者，通过PMA分发第一数据流得到多个第一子数据。
在一种可能的实现方式中，传输模块904，用于对第二数据进行分发，得到多个第三子数据，通过多条逻辑通道发送多个第三子数据。
在一种可能的实现方式中，该装置还包括：自协商模块，用于与接收第一芯片发送的数据的第三芯片进行自协商；响应于自协商结果指示需要级联编码，确定模块902执行基于第一芯片的参考时钟频率以及第一FEC码型对应的输出速率确定第二FEC码型。
在一种可能的实现方式中，第一数据为第一芯片内部的数据，或第一数据为第一芯片接收的由第二芯片发送的数据。
图10是本申请实施例提供的一种数据传输的装置的结构示意图。基于图10所示的如下多个模块，该图10所示的数据传输的装置能够执行第三芯片所执行的全部或部分操作。应理解到，该装置可以包括比所示模块更多的附加模块或者省略其中所示的一部分模块，本申请实施例对此并不进行限制。如图10所示，该装置包括：
接收模块1001，用于接收第二数据，第二数据为采用第二FEC码型对第一数据进行编码得到的数据，第一数据为采用第一FEC码型编码的数据；
解码模块1002，用于按照第二FEC码型对第二数据进行解码，得到解码后的数据。
在一种可能的实现方式中，解码模块1002，用于按照第二FEC码型对第二数据进行软判决解码，得到解码后的数据。
在一种可能的实现方式中，该装置还包括：编码模块，用于按照第三FEC码型对解码后的数据进行再次编码；传输模块，用于传输经过再次编码后的数据。
在一种可能的实现方式中，第三FEC码型为第一FEC码型或者第二FEC码型。
应理解的是，上述图9、图10提供的装置在实现其功能时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将 设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的装置与方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
本申请实施例提供了一种数据传输的设备，该设备包括：处理器，该处理器与存储器耦合，该存储器中存储有至少一条程序指令或代码，该至少一条程序指令或代码由该处理器加载并执行，以使该数据传输的设备实现如上述方法实施例中的方法。
参见图11，图11示出了本申请一个示例性实施例提供的数据传输的设备1100的结构示意图，该数据传输的设备1100为发送侧/接收侧设备。图11所示的数据传输的设备1100用于执行上述图2所示的数据传输的方法所涉及的操作。该数据传输的设备1100例如是交换机、路由器等网络设备以及其他包含这种芯片级联模式的设备(例如服务器、PC等)。该数据传输的设备1100的硬件结构包括通信接口1101和处理器1102。可选地，通信接口1101和处理器1102之间通过总线1104连接。其中，通信接口1101用于获取第一数据和传输第二数据，处理器可存储有指令或程序代码，通过调用该指令或程序代码来执行上述第一芯片所执行的功能，或者第三芯片所执行的功能。可选地，该网络设备还包括存储器1103，由存储器1103存放指令或程序代码，处理器1102用于调用存储器1103中的指令或程序代码使得网络设备执行上述方法实施例中第一芯片的相关处理步骤。在具体实施例中，本申请实施例的数据传输的设备1100可包括上述各个方法实施例中的第一芯片，数据传输的设备1100中的处理器1102读取存储器1103中的指令或程序代码，使图11所示的数据传输的设备1100能够执行第一芯片所执行的全部或部分操作。
在具体实施例中，本申请实施例的数据传输的设备1100包括上述各个方法实施例中的第三芯片，数据传输的设备1100中的处理器1102读取存储器1103中的指令或程序代码，使图11所示的数据传输的设备1100能够执行第三芯片所执行的全部或部分操作。
示例性地，处理器1102例如是通用中央处理器(central processing unit，CPU)、数字信号处理器(digital signal processor，DSP)、网络处理器(network processer，NP)、图形处理器(graphics processing unit，GPU)、神经网络处理器(neural-network processing units，NPU)、数据处理单元(data processing unit，DPU)、微处理器或者一个或多个用于实现本申请方案的集成电路。例如，处理器1102包括专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。PLD例如是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。其可以实现或执行结合本发明实施例公开内容所描述的各种逻辑方框、模块和电路。处理器也可以是实现计算功能的组合，例如包括一个或多个微处理器组合，DSP和微处理器的组合等等。
可选的，数据传输的设备1100还包括总线。总线用于在数据传输的设备1100的各组件之间传送信息。总线可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图11中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。图11中数据传输的设备1100的各组件之间除了采用总线连接，还可采用其他方式连接，本发明实施例不对各组件的连接方式进行限定。
存储器1103例如是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，又如是随机存取存储器(random access memory，RAM)或者可存储信息和指令的其它类型的动态存储设备，又如是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。存储器1103例如是独立存在，并通过总线与处理器1102相连接。存储器1103也可以和处理器1102集成在一起。
通信接口1101使用任何收发器一类的装置，用于与其它设备或通信网络通信，通信网络可以为以太网、无线接入网(RAN)或无线局域网(wireless local area networks，WLAN)等。通信接口1101可以包括有线通信接口，还可以包括无线通信接口。具体的，通信接口1101可以为以太(ethernet)接口、快速以太(fast ethernet，FE)接口、千兆以太(gigabit ethernet，GE)接口，异步传输模式(asynchronous transfer mode，ATM)接口，无线局域网(wireless local area networks，WLAN)接口，蜂窝网络通信接口或其组合。以太网接口可以是光接口，电接口或其组合。在本申请实施例中，通信接口1101可以用于数据传输的设备1100与其他设备进行通信。
在具体实现中，作为一种实施例，处理器1102可以包括一个或多个CPU。这些处理器中的每一个可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，数据传输的设备1100可以包括多个处理器。这些处理器中的每一个可以是一个单核处理器(single-CPU)，也可以是一个多核处理器(multi-CPU)。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，数据传输的设备1100还可以包括输出设备和输入设备。输出设备和处理器1102通信，可以以多种方式来显示信息。例如，输出设备可以是液晶显示器(liquid crystal display，LCD)、发光二级管(light emitting diode，LED)显示设备、阴极射线管(cathode ray tube，CRT)显示设备或投影仪(projector)等。输入设备和处理器1102通信，可以以多种方式接收用户的输入。例如，输入设备可以是鼠标、键盘、触摸屏设备或传感设备等。
在一些实施例中，存储器1103用于存储执行本申请方案的程序代码，处理器1102可以执行存储器1103中存储的程序代码。也即是，数据传输的设备1100可以通过处理器1102以及存储器1103中的程序代码，来实现方法实施例提供的数据传输的方法。程序代码中可以包括一个或多个软件模块。可选地，处理器1102自身也可以存储执行本申请方案的程序代码或指令。
在具体实施例中，本申请实施例的数据传输的设备1100可包括上述各个方法实施例中的第一芯片，数据传输的设备1100中的处理器1102读取存储器1103中的程序代码或处理器1102自身存储的程序代码或指令，使图11所示的数据传输的设备1100能够执行第一芯片所 执行的全部或部分操作。
在具体实施例中，本申请实施例的数据传输的设备1100可包括上述各个方法实施例中的第三芯片，数据传输的设备1100中的处理器1102读取存储器1103中的程序代码或处理器1102自身存储的程序代码或指令，使图11所示的数据传输的设备1100能够执行第三芯片所执行的全部或部分操作。
数据传输的设备1100还可以对应于上述图9、10所示的装置，图9、10所示的装置中的每个功能模块采用数据传输的设备1100的软件实现。换句话说，图9、10所示的装置包括的功能模块为数据传输的设备1100的处理器1102读取存储器1103中存储的程序代码后生成的。
其中，图2所示的数据传输的方法的各步骤通过数据传输的设备1100的处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤，为避免重复，这里不再详细描述。
本申请实施例还提供了一种数据传输的系统，该系统包括：第一数据传输的设备和第二数据传输的设备；第一数据传输的设备用于执行图2所示的第一芯片所执行的方法，第二数据传输的设备用于执行图2所示的第三芯片所执行的方法。
该系统的第一数据传输的设备和第二数据传输的设备各自的功能可参考上述图2所示的相关描述，此处不再一一赘述。
应理解的是，上述处理器可以是中央处理器(central processing unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。值得说明的是，处理器可以是支持进阶精简指令集机器(advanced RISC machines，ARM)架构的处理器。
进一步地，在一种可选的实施例中，上述存储器可以包括只读存储器和随机存取存储器，并向处理器提供指令和数据。存储器还可以包括非易失性随机存取存储器。例如，存储器还可以存储设备类型的信息。
该存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用。例如，静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic random access memory，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data date SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储 器(direct rambus RAM，DR RAM)。
还提供了一种计算机可读存储介质，存储介质中存储有至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行时以使计算机实现如上图2所示的数据传输的方法。
本申请提供了一种计算机程序，当计算机程序被计算机执行时，可以使得处理器或计算机执行上述方法实施例中对应的各个步骤和/或流程。
提供了一种芯片，包括处理器，用于从存储器中调用并运行所述存储器中存储的指令，使得安装有所述芯片的设备执行上述各方面中的方法。
提供另一种芯片，包括：输入接口、输出接口、处理器和存储器，所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连，所述处理器用于执行所述存储器中的代码，当所述代码被执行时，所述处理器用于执行上述各方面中的方法。
提供一种设备，包括上述方案中任一所述的芯片。
提供一种设备，包括上述方案中任一所述的第一芯片，和/或，上述方案中任一所述的第三芯片。
在一些实施例中，图1-8中，第二芯片可以是发送侧设备，比如路由器、交换机、服务器中的物理层(PHY)芯片，第一芯片可以是发送侧设备的接口，比如光模块中的芯片或者CDR/retimer芯片。第三芯片可以是接收侧设备的接口，比如光模块中的芯片或者CDR/retimer芯片，第四芯片可以是接收侧设备中的物理层(PHY)芯片。所述PHY芯片可以是位于计算设备的单板上的芯片，该芯片可以是CPU、网络处理器(network processor，NP)、神经网络处理单元(neural network processing unit,NPU)、现场可编程逻辑门阵列(field programmable gate array，FPGA)、可编程逻辑控制器(programmable logic controller，PLC)等中的一个或其任意组合。
在一些实施例中，所述第一芯片和所述第二芯片之间通过AUI通信；在一些实施例中，所述第三芯片和所述第四芯片之间通过AUI通信。
在以上实施例中，软解码时，先基于接收的量化软判决信息计算接收码字中的每个比特的置信度(也称可靠度，reliability)，获得置信度序列，从中选取M个最不可靠比特位置，在这M个最不可靠比特位置中，依次尝试对0，1，2，…，N(N≤M)个比特位置取反的所有组合，即得到多个测试码字，并对每个测试码字进行硬解码纠错，然后计算所有已纠正的测试码字与置信度序列的欧氏距离，选择最小距离对应的已纠正测试码字作为最终纠后码字输出。如果测试码字中没有可纠码字，则将原始接收码字对应的硬判决结果作为输出码字。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、 硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘，solid state disk)等。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。
本领域普通技术人员可以意识到，结合本文中所公开的实施例中描述的各方法步骤和模块，能够以软件、硬件、固件或者其任意组合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各实施例的步骤及组成。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域普通技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，该程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机程序指令。作为示例，本申请实施例的方法可以在机器可执行指令的上下文中被描述，机器可执行指令诸如包括在目标的真实或者虚拟处理器上的器件中执行的程序模块中。一般而言，程序模块包括例程、程序、库、对象、类、组件、数据结构等，其执行特定的任务或者实现特定的抽象数据结构。在各实施例中，程序模块的功能可以在所描述的程序模块之间合并或者分割。用于程序模块的机器可执行指令可以在本地或者分布式设备内执行。在分布式设备中，程序模块可以位于本地和远程存储介质二者中。
用于实现本申请实施例的方法的计算机程序代码可以用一种或多种编程语言编写。这些计算机程序代码可以提供给通用计算机、专用计算机或其他可编程的数据处理装置的处理器，使得程序代码在被计算机或其他可编程的数据处理装置执行的时候，引起在流程图和/或框图中规定的功能/操作被实施。程序代码可以完全在计算机上、部分在计算机上、作为独立的软件包、部分在计算机上且部分在远程计算机上或完全在远程计算机或服务器上执行。
在本申请实施例的上下文中，计算机程序代码或者相关数据可以由任意适当载体承载，以使得设备、装置或者处理器能够执行上文描述的各种处理和操作。载体的示例包括信号、计算机可读介质等等。
信号的示例可以包括电、光、无线电、声音或其它形式的传播信号，诸如载波、红外信号等。
机器可读介质可以是包含或存储用于或有关于指令执行系统、装置或设备的程序的任何有形介质。机器可读介质可以是机器可读信号介质或机器可读存储介质。机器可读介质可以包括但不限于电子的、磁的、光学的、电磁的、红外的或半导体系统、装置或设备，或其任意合适的组合。机器可读存储介质的更详细示例包括带有一根或多根导线的电气连接、便携式计算机磁盘、硬盘、随机存储存取器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或闪存)、光存储设备、磁存储设备，或其任意合适的组合。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、设备和模块的具体工作过程，可以参见前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，该模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、设备或模块的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
该作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以是两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
该集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例中方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请中术语“第一”“第二”等字样用于对作用和功能基本相同的相同项或相似项进行区分，应理解，“第一”、“第二”、“第n”之间不具有逻辑或时序上的依赖关系，也不对数量和执行顺序进行限定。还应理解，尽管以下描述使用术语第一、第二等来描述各种元素，但这些元素不应受术语的限制。这些术语只是用于将一元素与另一元素区别分开。例如，在不脱离各种所述示例的范围的情况下，第一网络设备可以被称为第二网络设备，并且类似地，第二网络设备可以被称为第一网络设备。第一网络和设备和第二网络设备都可以是网络设备，并且在某些情况下，可以是单独且不同的网络设备。
还应理解，在本申请的各个实施例中，各个过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本申请中术语“至少一个”的含义是指一个或多个，本申请中术语“多个”的含义是指两个或两个以上，例如，多个第二报文是指两个或两个以上的第二报文。本文中术语“系统”和“网络”经常可互换使用。
应理解，在本文中对各种所述示例的描述中所使用的术语只是为了描述特定示例，而并非旨在进行限制。如在对各种所述示例的描述和所附权利要求书中所使用的那样，单数形式“一个(“a”，“an”)”和“该”旨在也包括复数形式，除非上下文另外明确地指示。
还应理解，术语“包括”(也称“includes”、“including”、“comprises”和/或“comprising”)当在本说明书中使用时指定存在所陈述的特征、整数、步骤、操作、元素、和/或部件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元素、部件、和/或其分组。
还应理解，术语“若”和“如果”可被解释为意指“当...时”(“when”或“upon”)或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“若确定...”或“若检测到[所陈述的条件或事件]”可被解释为意指“在确定...时”或“响应于确定...”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
还应理解，说明书通篇中提到的“一个实施例”、“一实施例”、“一种可能的实现方式”意味着与实施例或实现方式有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”、“一种可能的实现方式”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。

Claims (34)

  1. 一种数据传输的方法，其特征在于，所述方法包括：
    第一芯片获取第一数据，所述第一数据为采用第一前向纠错码FEC码型编码的数据；
    基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型；
    所述第一芯片按照所述第二FEC码型对所述第一数据进行编码，得到第二数据；
    所述第一芯片传输所述第二数据。
  2. 根据权利要求1所述的方法，其特征在于，所述第一芯片的参考时钟频率、所述第一FEC码型对应的输出速率与所述第二数据的码字长度以及所述第二数据的码字内信息长度满足开销比例关系；
    所述基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型，包括：
    基于所述第一芯片的参考时钟频率及所述第一FEC码型对应的输出速率，按照所述开销比例关系确定所述第二FEC码型。
  3. 根据权利要求2所述的方法，其特征在于，所述开销比例关系，包括：
    Figure PCTCN2022073180-appb-100001
    其中，所述n为第二数据的码字长度，所述k为所述第二数据的码字内信息长度，所述v 1为所述第一FEC码型对应的输出速率，所述p为调整参数，所述f为所述第一芯片的参考时钟频率，所述p为正整数。
  4. 根据权利要求1-3任一所述的方法，其特征在于，所述第二数据的码字长度与所述第二数据被分发时的逻辑通道数量成整数倍关系。
  5. 根据权利要求1-4任一所述的方法，其特征在于，所述第一芯片按照所述第二FEC码型对所述第一数据进行编码，得到第二数据，包括：
    所述第一芯片分发所述第一数据得到多个第一子数据，所述第一芯片按照所述第二FEC码型分别对所述多个第一子数据进行编码，得到多个第二子数据；
    所述第一芯片传输所述第二数据，包括：
    所述第一芯片对所述多个第二子数据进行传输。
  6. 根据权利要求5所述的方法，其特征在于，所述第一芯片分发所述第一数据得到多个第一子数据，包括：
    所述第一芯片通过物理编码子层PCS通道分发所述第一数据得到多个第一子数据；
    或者，所述第一芯片通过物理介质接入子层PMA分发所述第一数据流得到多个第一子数据。
  7. 根据权利要求1-4任一所述的方法，其特征在于，所述第一芯片传输所述第二数据，包括：
    所述第一芯片对所述第二数据进行分发，得到多个第三子数据，通过多条逻辑通道发送所述多个第三子数据。
  8. 根据权利要求1-7任一所述的方法，其特征在于，所述基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型之前，所述方法还包括：
    所述第一芯片与接收所述第一芯片发送的数据的第三芯片进行自协商；
    响应于自协商结果指示需要级联编码，所述第一芯片执行所述基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型。
  9. 根据权利要求1-8任一所述的方法，其特征在于，所述第一数据为所述第一芯片内部的数据，或所述第一数据为所述第一芯片接收的由第二芯片发送的数据。
  10. 一种数据传输的方法，其特征在于，所述方法包括：
    第三芯片接收第二数据，所述第二数据为采用第二前向纠错码FEC码型对第一数据进行编码得到的数据，所述第一数据为采用第一FEC码型编码的数据；
    所述第三芯片按照所述第二FEC码型对所述第二数据进行解码，得到解码后的数据。
  11. 根据权利要求10所述的方法，其特征在于，所述第三芯片按照所述第二FEC码型对所述第二数据进行解码，包括：
    所述第三芯片按照所述第二FEC码型对所述第二数据进行软判决解码。
  12. 根据权利要求11所述的方法，其特征在于，所述第三芯片按照所述第二FEC码型对所述第二数据进行软判决解码，包括：基于接收的量化软判决信息计算接收码字中的每个比特的置信度，获得置信度序列，从中选取M个最不可靠比特位置，在这M个最不可靠比特位置中，依次尝试对0，1，2，…，N(N≤M)个比特位置取反的所有组合，得到多个测试码字，并对每个测试码字进行硬解码纠错，计算所有已纠正的测试码字与置信度序列的欧氏距离，选择最小距离对应的已纠正测试码字作为最终纠后码字输出。
  13. 根据权利要求12所述的方法，其特征在于，所述第三芯片按照所述第二FEC码型对所述第二数据进行软判决解码，还包括：如果测试码字中没有可纠码字，则将原始接收码字对应的硬判决结果作为输出码字。
  14. 根据权利要求10-13任一所述的方法，其特征在于，所述第三芯片按照所述第二FEC码型对所述第二数据进行解码，得到解码后的数据之后，所述方法还包括：
    所述第三芯片按照第三FEC码型对所述解码后的数据进行再次编码，传输经过再次编码后的数据。
  15. 根据权利要求14所述的方法，其特征在于，所述第三FEC码型为所述第二FEC码型。
  16. 一种数据传输的装置，其特征在于，所述装置包括：
    获取模块，用于获取第一数据，所述第一数据为采用第一前向纠错码FEC码型编码的数据；
    确定模块，用于基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型；
    编码模块，用于按照所述第二FEC码型对所述第一数据进行编码，得到第二数据；
    传输模块，用于传输所述第二数据。
  17. 根据权利要求16所述的装置，其特征在于，所述第一芯片的参考时钟频率、所述第一FEC码型对应的输出速率与所述第二数据的码字长度以及所述第二数据的码字内信息长度满足开销比例关系；
    所述确定模块，用于基于所述第一芯片的参考时钟频率及所述第一FEC码型对应的输出速率，按照所述开销比例关系确定所述第二FEC码型。
  18. 根据权利要求17所述的装置，其特征在于，所述开销比例关系，包括：
    Figure PCTCN2022073180-appb-100002
    其中，所述n为第二数据的码字长度，所述k为所述第二数据的码字内信息长度，所述v 1为所述第一FEC码型对应的输出速率，所述p为调整参数，所述f为所述第一芯片的参考时钟频率，所述p为正整数。
  19. 根据权利要求16-18任一所述的装置，其特征在于，所述第二数据的码字长度与所述第二数据被分发时的逻辑通道数量成整数倍关系。
  20. 根据权利要求16-19任一所述的装置，其特征在于，所述编码模块，用于分发所述第一数据得到多个第一子数据，按照所述第二FEC码型分别对所述多个第一子数据进行编码，得到多个第二子数据；
    所述传输模块，用于对所述多个第二子数据进行传输。
  21. 根据权利要求20所述的装置，其特征在于，所述编码模块，用于通过物理编码子层PCS通道分发所述第一数据得到多个第一子数据；或者，通过物理介质接入子层PMA分发所述第一数据流得到多个第一子数据。
  22. 根据权利要求16-19任一所述的装置，其特征在于，所述传输模块，用于对所述第二数据进行分发，得到多个第三子数据，通过多条逻辑通道发送所述多个第三子数据。
  23. 根据权利要求16-22任一所述的装置，其特征在于，还包括：
    自协商模块，用于与接收所述第一芯片发送的数据的第三芯片进行自协商；响应于自协商结果指示需要级联编码，所述确定模块执行所述基于所述第一芯片的参考时钟频率以及所述第一FEC码型对应的输出速率确定第二FEC码型。
  24. 根据权利要求16-23任一所述的装置，其特征在于，所述第一数据为所述第一芯片内部的数据，或所述第一数据为所述第一芯片接收的由第二芯片发送的数据。
  25. 一种数据传输的装置，其特征在于，所述装置包括：
    接收模块，用于接收第二数据，所述第二数据为采用第二前向纠错码FEC码型对第一数据进行编码得到的数据，所述第一数据为采用第一FEC码型编码的数据；
    解码模块，用于按照所述第二FEC码型对所述第二数据进行解码，得到解码后的数据。
  26. 根据权利要求25所述的装置，其特征在于，所述解码模块，用于按照所述第二FEC码型对所述第二数据进行软判决解码，得到解码后的数据。
  27. 根据权利要求26所述的装置，其特征在于，所述解码模块，用于基于接收的量化软判决信息计算接收码字中的每个比特的置信度，获得置信度序列，从中选取M个最不可靠比特位置，在这M个最不可靠比特位置中，依次尝试对0，1，2，…，N(N≤M)个比特位置取反的所有组合，得到多个测试码字，并对每个测试码字进行硬解码纠错，计算所有已纠正的测试码字与置信度序列的欧氏距离，选择最小距离对应的已纠正测试码字作为最终纠后码字输出。
  28. 根据权利要求27所述的装置，其特征在于，所述解码模块，还用于如果测试码字中没有可纠码字，则将原始接收码字对应的硬判决结果作为输出码字。
  29. 根据权利要求25-28任一所述的装置，其特征在于，所述装置还包括：
    编码模块，用于按照第三FEC码型对所述解码后的数据进行再次编码；
    传输模块，用于传输经过再次编码后的数据。
  30. 根据权利要求29所述的装置，其特征在于，所述第三FEC码型为所述第二FEC码型。
  31. 一种数据传输的设备，其特征在于，所述数据传输的设备包括：处理器，所述处理器与存储器耦合，所述存储器中存储有至少一条程序指令或代码，所述至少一条程序指令或代码由所述处理器加载并执行，以使所述数据传输的设备实现如权利要求1-15中任一所述的方法。
  32. 一种数据传输的系统，其特征在于，所述数据传输的系统包括第一数据传输的设备和 第二数据传输的设备，所述第一数据传输的设备用于执行如权利要求1-9任一所述的方法，和/或，所述第二数据传输的设备用于执行如权利要求10-15中任一所述的方法。
  33. 一种计算机可读存储介质，其特征在于，包括至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行，以使计算机实现如权利要求1-15中任一所述的方法。
  34. 一种计算机程序产品，其特征在于，包括至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行，以使计算机实现如权利要求1-15中任一所述的方法。
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