WO2023065717A1 - Ddr存储器数据读写调度方法和装置 - Google Patents

Ddr存储器数据读写调度方法和装置 Download PDF

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Publication number
WO2023065717A1
WO2023065717A1 PCT/CN2022/102774 CN2022102774W WO2023065717A1 WO 2023065717 A1 WO2023065717 A1 WO 2023065717A1 CN 2022102774 W CN2022102774 W CN 2022102774W WO 2023065717 A1 WO2023065717 A1 WO 2023065717A1
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read
write
ddr memory
data
priority
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PCT/CN2022/102774
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English (en)
French (fr)
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陈果
何林峰
潘建波
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瓴盛科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes

Definitions

  • the present invention mainly relates to the field of information technology, in particular to a DDR memory data reading and writing scheduling method and device.
  • Double Data Rate Synchronous Dynamic Random Access Memory is a memory with double data transfer rate, that is, the data transfer speed of DDR memory is twice the system clock frequency, because The speed is increased, and its transmission performance is better than that of traditional SDRAM. DDR memory can perform data transmission on both rising and falling edges of the system clock.
  • the purpose of the present invention is to provide a DDR memory data reading and writing scheduling method and device, so as to improve the data reading and writing efficiency of the DDR memory.
  • the DDR memory data read and write scheduling method includes the following steps: receiving the read and write request instructions of a plurality of main interfaces; The storage address distribution mode of the request data on the DDR memory; according to the storage address distribution mode of the request data on the DDR memory, arbitration obtains the first priority of the read and write request instructions of the multiple master interfaces Level response mode; performing a first data read and write operation based on the first priority response mode.
  • the DDR memory data reading and writing scheduling method further includes: judging the first data reading and writing operation based on the response scheduling rule of the reading and writing request instruction, and determining whether to re-arbitrate, Obtaining a second priority response mode to the read and write request instructions of the plurality of main interfaces; performing a second data read and write operation based on the second priority response mode.
  • the storage address distribution method of the request data on the DDR memory includes: the same row located on the same storage block on the DDR memory, the same row located on a different storage block on the DDR memory rows or different rows and different rows located on the same memory block on the DDR memory.
  • the first priority response mode obtained by arbitration for the read and write request instructions of the multiple master interfaces includes:
  • the same row on the same memory block on the DDR memory where the request data is arbitrated is the first level priority in the first priority response mode; the request data is located on the same memory block on the different memory blocks on the DDR memory A row or a different row is arbitrated as the second level priority in the first priority response mode; a different row whose request data is located on the same memory block on the DDR memory is arbitrated as the first priority response mode
  • judging the first data read/write operation based on the response scheduling rule of the read/write request instruction includes: Whether the number of consecutive arbitrations of the first level exceeds the first threshold.
  • judging the first data read and write operation based on the response scheduling rule of the read and write request command includes whether the time interval of one read and write request command of the main interface exceeds the second threshold.
  • judging the first data read and write operation based on the response scheduling rule of the read and write request command includes whether the response time of one read and write request command of the main interface exceeds the third threshold.
  • judging the first data read and write operation based on the response scheduling rule of the read and write request instruction includes whether there are other masters when one of the master interfaces performs the first data read and write operation The interface responds immediately to priority read and write requests.
  • judging the first data read/write operation based on the response scheduling rule of the read/write request instruction includes an instruction that does not return requested data among the read/write request instructions of the main interface Whether the number exceeds the fourth threshold.
  • judging the first data read/write operation based on the response scheduling rule of the read/write request instruction includes whether the size of the requested data corresponding to a read/write request instruction of the main interface is Cache space exceeded for said main interface.
  • each of the times takes Y clock cycles as a unit, and Y is a positive integer.
  • the present invention also provides a DDR memory data read and write scheduling device, comprising: an instruction receiving module, configured to receive read and write request instructions of a plurality of main interfaces; a priority arbitration module, configured to: acquire the The storage address distribution mode of the request data corresponding to the plurality of read and write request instructions on the DDR memory; determine the read access to the multiple main interfaces according to the storage address distribution mode of the request data on the DDR memory The first priority response mode of the write request instruction; the data read and write module, configured to perform the first data read and write operation based on the first priority response mode.
  • the DDR memory data read and write scheduling device further includes: the priority arbitration module is further configured to: perform the first data read and write operation based on the response scheduling rule of the read and write request instruction Judging to determine a second priority response mode to the read and write request instructions of the multiple main interfaces; the data read and write module also performs a second data read and write operation based on the second priority response mode.
  • the DDR memory data reading and writing scheduling method proposed by the present invention determines the response priority to the reading and writing requests of the main interface based on the different distribution modes of the request data corresponding to the reading and writing requests of the main interface, so as to reduce the pre-charging as much as possible
  • the time occupied by the operation in data read and write operations improves data processing efficiency.
  • FIG. 1 is a flow chart of a method for scheduling data reading and writing in a DDR memory according to an embodiment of the present application.
  • FIG. 2 is a flow chart of a method for scheduling data reading and writing of a DDR memory according to another embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a DDR memory according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a storage block read and write operation of a DDR memory according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a storage block read and write operation state machine of a DDR memory according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a device for scheduling read and write data of a DDR memory according to an embodiment of the present application.
  • spatially relative terms may be used here, such as “on !, “over !, “on the surface of !, “above”, etc., to describe the The spatial positional relationship between one device or feature shown and other devices or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the flow chart is used in this application to illustrate the operations performed by the system according to the embodiment of this application. It should be understood that the preceding or following operations are not necessarily performed in an exact order. Instead, various steps may be processed in reverse order or concurrently. At the same time, other operations are either added to these procedures, or a certain step or steps are removed from these procedures.
  • the embodiments of the present application describe a method and device for scheduling data reading and writing in a DDR memory.
  • FIG. 1 is a flow chart of a method for scheduling data reading and writing in a DDR memory according to an embodiment of the present application.
  • FIG. 2 is a flow chart of a method for scheduling data reading and writing of a DDR memory according to another embodiment of the present application.
  • the DDR memory data read and write scheduling method includes, step 101, receiving the read and write request instructions of a plurality of main interfaces; The storage address distribution mode of the request data on the DDR memory; step 103, according to the storage address distribution mode of the request data on the DDR memory, arbitrate to obtain the first read and write request instructions of the plurality of main interfaces A priority response mode; step 104, perform a first data read and write operation based on the first priority response mode.
  • FIG. 3 is a schematic structural diagram of a DDR memory according to an embodiment of the present application.
  • the DDR memory 301 includes a plurality of memory blocks (Bank). Shown in Fig. 3 also can be understood as one side (Rank) or one side (Side) of DDR memory 301, and one side is relative to the two sides that comprise front and reverse side, and one side is relative to both sides of DDR memory. Word. Figure 3 indicates Rank 1 or Side 1.
  • one side of the DDR memory 301 may include a plurality of memory chips (memory ICs).
  • the memory chips 311 , 312 , 318 etc. are marked in FIG. 3 .
  • Each memory chip can include a plurality of memory blocks (Bank).
  • the memory chip 311 (the corresponding enlarged structure is 321 ) includes 8 memory blocks such as Bank1 (block 1), Bank2 (block 2), . . . , Bank8 (block 8).
  • the enlarged structure of one memory block (referred to as block n) among the plurality of memory blocks included in the memory chip 311 is illustrated as 331 in FIG. 3 .
  • the storage block 331 includes a row decoder (Row Decoder) 341, a column decoder (Column Decoder) 342, a sense amplifier (Sense Amplifier) 345 and a memory matrix (Memory Matrix) 346.
  • the memory array is composed of rows and columns, and each row and column intersects the unit, which represents N bit, usually 8bit or 16 bits, each of which is composed of a transistor and a capacitor, such as in GDDR5 (DDR for fifth edition graphics) and In HBM (high-bandwidth memory) memory, it is usually 32Byte, representing a byte or a word (word).
  • N bit usually 8bit or 16 bits
  • HBM high-bandwidth memory
  • the memory chip 311 may also include a data input/output buffer (Data Input/Output Buffers) 351 .
  • the data input/output buffer 351 can input/output data, so as to perform read and write operations on data.
  • 352 for example, refers to data input from other memory blocks, and 353, for example, refers to output to the memory bus.
  • FIG. 4 is a schematic diagram of a storage block read and write operation of a DDR memory according to an embodiment of the present application.
  • each row in a storage block constitutes a page (page), and each row includes many columns (a column here refers to a single intersection unit).
  • N BITS N bit is also shown in FIG. 4, which refers to a plurality of row and column interleaving units.
  • ACTIVATE Putting a row into the sense amplifier is called "ACTIVATE” because this operation activates the bank.
  • Arrow 1 in FIG. 4 indicates an ACTIVATE operation
  • arrow 2 indicates a read operation or a write operation
  • Arrow 3 indicates precharge (PRECHARGE) operation.
  • FIG. 5 is a schematic diagram of a storage block read and write operation state machine of a DDR memory according to an embodiment of the present application.
  • the storage block for example, the reading and writing of the storage block of SDRAM type can be described with a state machine, and its state includes idle state (IDLE) 511, activates operating state (Activating) 512, block activation state ( Bank Active) 513, precharging operation state (Precharging) 518, refresh operation state (Refreshing) 519, reading state (Reading) 515, writing state (Writing) 514, reading and automatic charging operation state (Read with Auto-Precharge) 517 , write and automatic charging state (Write with Auto-Precharge) 516.
  • the state machine illustrated in Figure 5 requires some minimum waiting time for switching from one state to another and starting data operations in the new state. These delays will affect the performance of reading and writing data in SDRAM memory blocks, thereby affecting performance of the entire computing system.
  • SDARM Bank SDRAM-type storage block memory unit row and column intersection (usually called cell) point, used to store data, it is usually composed of some capacitors and amplifiers,
  • the refresh rate usually depends on the process of the memory die and the design of the cell itself.
  • the reading and writing of memory cells has the same effect as memory refreshing, but not all memory cells have read and write operations before the capacitor power decays enough to refresh, so regular refreshing is still required.
  • the refresh operation is performed by row or by page. After the refresh, the capacitor of the cell in the row will be charged.
  • the usual refresh operation cycle is hundreds of clocks (clocks) to thousands of clocks.
  • each Bank Before refreshing the command, each Bank must be precharged and then in the IDLE state, which requires a tRP delay.
  • Precharge or denoted as PRECHARGE
  • RAS Row Access Strobe
  • the bank Before SDRAM responds to read and write commands, the bank must be in an active state, and the memory controller specifies the accessed rank, bank, and page (or row) by sending the activate command.
  • the time consumed to read a byte of data from an active page including sending read and write commands on the read and write interface, program control logic, and transferring the content of the sensor amplifier to the input and output buffers , and the total time spent putting the first word of data on the memory bus.
  • a Bank can only open one page at a time (opening here refers to putting the content of the page into the sensor amplifier). For the page in the open state, it can be read and written. If there is no need to perform operations on the page For read and write operations, the page can be closed, and the content of the page can be written from the sense amplifier into the page corresponding to the row and column unit of the Bank, so as to perform read and write operations on other pages.
  • This closing operation is realized by a PRECHARGE command.
  • the PRECHARGE command can close a certain Bank, or close all opened Banks in the Rank.
  • the PRECHARGE command writes the data in the sense amplifier into the corresponding page in the bank, and then prepares for the next data access.
  • 501 represents an initialization sequence (Initialization Sequence).
  • Figure 5 also includes a legend, where the legend 1 represents the command sequence (Command Sequence), and the legend 2 represents the automatic sequence (Automatic Sequence).
  • Arrow 3 in FIG. 5 indicates continuous write operations, and arrow 4 indicates continuous read operations.
  • steps 101 to 104 the steps of the DDR memory data read and write scheduling method of the present application are illustrated in steps 101 to 104 above.
  • step 101 multiple read and write request instructions of master interfaces (Masters) are received.
  • the type of the master interface can vary according to the bus type and protocol type of the system, for example, including the AMBA type bus in the ARM system, and the master interface (AXI Master) using the AXI protocol type.
  • the multiple master interfaces include, for example, Master0, Master1, Master2, ..., Master N-1, where N is a positive integer.
  • Each of the multiple main interfaces can send multiple read and write request commands.
  • step 102 the storage address distribution mode of the request data corresponding to the plurality of read and write request instructions of each master interface on the DDR memory is obtained.
  • the storage address distribution method of the requested data on the DDR memory includes the same row located on the same storage block on the DDR memory, the same row located on different storage blocks on the DDR memory, or different row and a different row located on the same memory block on the DDR memory.
  • the distribution of the same row (Row) on the same storage block (Bank), the same row or different rows on different storage blocks, and the distribution of different rows on the same storage block can be understood with reference to FIG. 3 and FIG. 4 .
  • the request data is located in the same row (Row) on the same storage block (Bank) on the DDR memory, which may be referred to as a page hit (PageHit).
  • step 103 according to the storage address distribution mode of the request data on the DDR memory, arbitrate to obtain a first priority response mode to the read and write request commands of the multiple master interfaces.
  • the first priority response mode obtained by arbitration for the read and write request instructions of the multiple master interfaces includes: the request data The same row on the same memory block on the DDR memory is arbitrated as the first level priority in the first priority response mode; the request data is located on the same row or different rows on different memory blocks on the DDR memory Arbitrated as the second level priority in the first priority response mode; the request data is located in a different row on the same memory block on the DDR memory is arbitrated as the third level in the first priority response mode class priority.
  • step 104 a first data read and write operation is performed based on the first priority response manner.
  • a first data read and write operation is performed on the master interface determined to respond based on the first priority response manner.
  • the DDR memory data read and write scheduling method of the present application determines the response priority to the read and write requests of the main interface, thereby realizing reducing PRECHARGE as much as possible. charging) operation in data read and write operations to improve data processing efficiency.
  • step 205 based on the response dispatching rule of the read and write request instruction to the first Judging the data read and write operations, determining whether the arbitration needs to be re-arbitrated, and obtaining the second priority response mode for the read and write request instructions of the multiple main interfaces; step 206, performing the second priority response mode based on the second priority response mode Two data read and write operations.
  • judging the first data read/write operation based on the response scheduling rule of the read/write request instruction includes that one of the master interfaces in the first priority response mode is continuously arbitrated as Whether the number of times of the first level of priority exceeds the first threshold.
  • the request data located in the same row (Row) on the same memory block (Bank) on the DDR memory may be referred to as a page hit (PageHit).
  • PageHit the read and write request command of the corresponding master interface is arbitrated as the first level priority in the first priority response mode, and enters the page hit lock (PageHitLock) state.
  • the corresponding main interface is transferred to the lock release (PageHitLock Release) state, and re-arbitration is carried out to obtain the second priority response mode to the read and write request instructions of the multiple main interfaces.
  • the arbitration is performed again to obtain a second-priority response manner to the read and write request commands of the multiple master interfaces, which may be performed with reference to the manner of step 103 .
  • each of the times takes Y clock cycles (cycle) as a unit, and Y is a positive integer.
  • judging the first data read/write operation based on the response scheduling rule of the read/write request command includes whether a time interval of one read/write request command of the main interface exceeds a second threshold. If it is judged that the time interval of a read and write request instruction of the main interface exceeds the second threshold, it can also be called that the read and write requests of the main interface are discontinuous, then the corresponding main interface is transferred from the response state to the response release (Release) state . Particularly, if the main interface is in the page hit lock (PageHitLock) state, then the corresponding main interface is transferred to the lock release (PageHitLock Release) state. Then, a re-arbitration is performed to obtain a second priority response mode to the read and write request commands of the multiple master interfaces.
  • judging the first data read and write operation based on the response scheduling rule of the read and write request command includes whether the response time of a read and write request command of the main interface exceeds a third threshold, and also Timeout occurs for read and write requests that can be called the main interface. If it is judged that the response time of a read/write request command of the main interface exceeds the third threshold, the corresponding main interface is changed from a response state to a response release (Release) state. Particularly, if the main interface is in the page hit lock (PageHitLock) state, then the corresponding main interface is transferred to the lock release (PageHitLock Release) state.
  • PageHitLock page hit lock
  • PageHitLock Release lock release
  • a re-arbitration is performed to obtain a second priority response mode to the read and write request commands of the multiple master interfaces. Then perform a second data read and write operation based on the second priority response mode.
  • judging the first data read/write operation based on the response scheduling rule of the read/write request instruction includes whether there is an immediate Responds to priority read and write requests.
  • Immediate response priority read and write requests include, for example, read and write requests to meet the delay rules of the system, which need to be responded with super high priority to maintain the normal operation of the system and realize the effective execution of read and write operations.
  • the main interface of the current response is changed from the response state to the response release (Release) state, and re-arbitrated to obtain the read and write requests to the multiple main interfaces
  • the second priority response mode of the command is specifically to respond to the main interface that sends the immediate response priority read and write request at this time. Then perform a second data read and write operation based on the second priority response mode.
  • judging the first data read/write operation based on the response scheduling rule of the read/write request instruction includes whether the number of instructions that do not return requested data in one read/write request instruction of the main interface is Exceeding the fourth threshold, in some types of SoC systems, the outstanding parameter, which may also be referred to as the main interface, reaches the set threshold.
  • the main interface of the current response is changed from the response state to the response release (Release) state, and re-arbitrated to obtain A second priority response mode to the read and write request commands of the multiple master interfaces.
  • the arbitration is performed again to obtain the second priority response mode to the read and write request commands of the multiple master interfaces, which can be performed with reference to the manner in step 103 .
  • judging the first data read/write operation based on the response scheduling rule of the read/write request instruction includes whether the size of the requested data corresponding to one read/write request instruction of the main interface exceeds the Cache space of the main interface. If it is judged that the size of the request data corresponding to the read and write request instruction of a described main interface exceeds the buffer space of the described main interface, in order to ensure that the read and write operations of the main interface are carried out normally and effectively, the main interface of the current response is read from The response state changes to a response release (Release) state, and re-arbitration is performed to obtain a second-priority response mode to the read and write request commands of the multiple master interfaces.
  • the response state changes to a response release (Release) state, and re-arbitration is performed to obtain a second-priority response mode to the read and write request commands of the multiple master interfaces.
  • re-arbitration is performed to obtain the second priority response
  • the priority of the corresponding main interface previously in the first priority response mode is adjusted to the lowest. After a set time interval, it is allowed to participate in the arbitration again.
  • the DDR memory data read and write scheduling method of the present application on the basis of reducing the time occupied by the PRECHARGE operation in the data read and write operation as much as possible, can also realize the efficient scheduling of the read and write requests of multiple main interfaces, and improve the data quality. Efficiency of read and write operations.
  • the present application also provides a DDR memory data reading and writing scheduling device.
  • FIG. 6 is a schematic diagram of a device for scheduling read and write data of a DDR memory according to an embodiment of the present application.
  • the DDR memory data read/write scheduling device 600 includes an instruction receiving module 602 , a priority arbitration module 604 and a data read/write module 606 .
  • the command receiving module 602 is configured to receive read and write request commands of multiple master interfaces.
  • the priority arbitration module 604 is configured to first obtain the storage address distribution mode of the request data corresponding to the plurality of read and write request instructions of each main interface on the DDR memory; The storage address distribution mode on the DDR memory determines the first priority response mode to the read and write request commands of the multiple master interfaces.
  • the data read-write module 606 is configured to perform a first data read-write operation based on the first priority response manner.
  • the priority arbitration module 604 is further configured to judge the first data read and write operation based on the response scheduling rule of the read and write request instruction, and determine the read and write of the multiple main interfaces The second priority response mode of the request command.
  • the data read-write module 606 also performs a second data read-write operation based on the second priority response mode.
  • the DDR memory data reading and writing scheduling device of the present application can reduce the time occupied by the PRECHARGE operation in data reading and writing operations as much as possible, and can also realize efficient scheduling of reading and writing requests for multiple main interfaces, improving data reading and writing operations. s efficiency.
  • the processor can be one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DAPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors , a controller, a microcontroller, a microprocessor, or a combination thereof.
  • ASICs Application Specific Integrated Circuits
  • DSPs Digital Signal Processors
  • DAPDs Digital Signal Processing Devices
  • PLDs Programmable Logic Devices
  • FPGAs Field Programmable Gate Arrays
  • aspects of the present application may be embodied as a computer product comprising computer readable program code on one or more computer readable media.
  • computer-readable media may include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, magnetic tape%), optical disks (e.g., compact disk CD, digital versatile disk DVD%), smart cards, and flash memory devices ( For example, cards, sticks, key drives).
  • a computer readable medium may contain a propagated data signal embodying a computer program code, for example, in baseband or as part of a carrier wave.
  • the propagated signal may take many forms, including electromagnetic, optical, etc., or a suitable combination.
  • the computer-readable medium can be any computer-readable medium, except computer-readable storage media, that can communicate, propagate, or transfer the program for use by being coupled to an instruction execution system, apparatus, or device.
  • Program code residing on a computer readable medium may be transmitted over any suitable medium, including radio, electrical cables, fiber optic cables, radio frequency signals, or the like, or combinations of any of the foregoing.
  • numbers describing the quantity of components and attributes are used, and it should be understood that such numbers used in the description of the embodiments, in some examples, use the modifiers "about”, “approximately” or “substantially” to express grooming. Unless otherwise stated, “about”, “approximately” or “substantially” indicates that the stated figure allows for a variation of ⁇ 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that can vary depending upon the desired characteristics of individual embodiments. In some embodiments, numerical parameters should take into account the specified significant digits and adopt the general digit reservation method. Although the numerical ranges and parameters used to confirm the breadth of the scope in some embodiments of the application are approximate values, in specific embodiments, such numerical values are set as precisely as practicable.

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Abstract

本发明提供一种DDR存储器数据读写调度方法和装置，所述方法包括以下步骤：接收多个主接口的读写请求指令；获取每个所述主接口的多条所述读写请求指令对应的请求数据在所述DDR存储器上的存储地址分布方式；根据所述请求数据在所述DDR存储器上的存储地址分布方式，仲裁得到对所述多个主接口的读写请求指令的第一优先级响应方式；基于所述第一优先级响应方式进行第一数据读写操作。本发明能够提高DDR存储器的数据处理效率。

Description

DDR存储器数据读写调度方法和装置 技术领域
本发明主要涉及信息技术领域，尤其涉及一种DDR存储器数据读写调度方法和装置。
背景技术
双倍数据率同步动态随机存取存储器(Double Data Rate Synchronous Dynamic Random Access Memory，简称DDR SDRAM)为具有双倍数据传输率的存储器，即DDR存储器的数据传输速度为系统时钟频率的两倍，由于速度增加，其传输性能优于传统的SDRAM。DDR存储器在系统时钟的上升沿和下降沿都可以进行数据传输。
在应用DDR存储器时，为提高DDR存储器的数据读写效率，需要对DDR存储器的读写操作进行调度，以提高信息系统(例如SoC系统)的运行效率，此为需要应对的课题。
发明内容
本发明的目的是提供一种DDR存储器数据读写调度方法和装置，实现提高DDR存储器的数据读写效率。
为了实现上述目的，本发明所提供的DDR存储器数据读写调度方法，包括以下步骤：接收多个主接口的读写请求指令；获取每个所述主接口的多条所述读写请求指令对应的请求数据在所述DDR存储器上的存储地址分布方式；根据所述请求数据在所述DDR存储器上的存储地址分布方式，仲裁得到对所述多个主接口的读写请求指令的第一优先级响应方式；基于所述第一优先级响应方式进行第一数据读写操作。
在本发明的一实施例中，DDR存储器数据读写调度方法还包括：基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断，确定是否需重新所述仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式；基于所述第二优先级响应方式进行第二数据读写操作。
在本发明的一实施例中，所述请求数据在所述DDR存储器上的存储地址分布方式包括，位于DDR存储器上的同一存储块上的同一行、位于DDR存储器上的不同存储块上的同一行或不同行和位于DDR存储器上的同一存储块上的不同行。
在本发明的一实施例中，根据所述请求数据在所述DDR存储器上的存储地址分布方式，仲裁得到对所述多个主接口的读写请求指令的第一优先级响应方式包括：
所述请求数据位于DDR存储器上的同一存储块上的同一行被仲裁为所述第一优先级响应方式中的第一等级优先级；所述请求数据位于DDR存储器上的不同存储块上的同一行或不同行被仲裁为所述第一优先级响应方式中的第二等级优先级；所述请求数据位于DDR存储器上的同一存储块上的不同行被仲裁为所述第一优先级响应方式中的第三等级优先级。
在本发明的一实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口在所述第一优先级响应方式中的被连续仲裁为第一等级的次数是否超过第一阈值。
在本发明的一实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令的时间间隔是否超过第二阈值。
在本发明的一实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令的响应时长是否超过第三阈值。
在本发明的一实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口进行第一数据读写操作时是否存在其他主接口的即时响应优先级读写请求。
在本发明的一实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令中未返回请求数据的指令的数量是否超过第四阈值。
在本发明的一实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令对应的请求数据的大小是否超过所述主接口的缓存空间。
在本发明的一实施例中，所述次数中的每一次以Y个时钟周期为单位，Y为正 整数。
本发明还提供一种DDR存储器数据读写调度装置，包括：指令接收模块，用于接收多个主接口的读写请求指令；优先级仲裁模块，被配置为：获取每个所述主接口的多条所述读写请求指令对应的请求数据在所述DDR存储器上的存储地址分布方式；根据所述请求数据在所述DDR存储器上的存储地址分布方式确定对所述多个主接口的读写请求指令的第一优先级响应方式；数据读写模块，用于基于所述第一优先级响应方式进行第一数据读写操作。
在本发明的一实施例中，DDR存储器数据读写调度装置还包括：所述优先级仲裁模块还被配置为：基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断，确定对所述多个主接口的读写请求指令的第二优先级响应方式；所述数据读写模块还基于所述第二优先级响应方式进行第二数据读写操作。
本发明提出的DDR存储器数据读写调度方法，基于主接口的读写请求对应的请求数据的分布方式的不同，确定对主接口的读写请求的响应优先级，从而实现尽可能减小预充电操作在数据读写操作中占用的时间，提高数据处理效率。
附图概述
包括附图是为提供对本申请进一步的理解，它们被收录并构成本申请的一部分，附图示出了本申请的实施例，并与本说明书一起起到解释本申请原理的作用。附图中：
图1是本申请一实施例的DDR存储器数据读写调度方法的流程图。
图2是本申请另一实施例的DDR存储器数据读写调度方法的流程图。
图3是本申请一实施例的DDR存储器的结构示意图。
图4是本申请一实施例的DDR存储器的存储块读写操作示意图。
图5是本申请一实施例的DDR存储器的存储块读写操作状态机示意图。
图6是本申请一实施例的DDR存储器数据读写调度装置的示意图。
本发明的较佳实施方式
为了更清楚地说明本申请的实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单的介绍。显而易见地，下面描述中的附图仅仅是本申请 的一些示例或实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图将本申请应用于其他类似情景。除非从语言环境中显而易见或另做说明，图中相同标号代表相同结构或操作。
如本申请和权利要求书中所示，除非上下文明确提示例外情形，“一”、“一个”、“一种”和/或“该”等词并非特指单数，也可包括复数。一般说来，术语“包括”与“包含”仅提示包括已明确标识的步骤和元素，而这些步骤和元素不构成一个排它性的罗列，方法或者设备也可能包含其他的步骤或元素。
除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本申请的范围。同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
为了便于描述，在这里可以使用空间相对术语，如“在……之上”、“在……上方”、“在……上表面”、“上面的”等，用来描述如在图中所示的一个器件或特征与其他器件或特征的空间位置关系。应当理解的是，空间相对术语旨在包含除了器件在图中所描述的方位之外的在使用或操作中的不同方位。
此外，需要说明的是，使用“第一”、“第二”等词语来限定零部件或术语，仅仅是为了便于对相应零部件或术语进行区别，如没有另行声明，上述词语并没有特殊含义，因此不能理解为对本申请保护范围的限制。此外，尽管本申请中所使用的术语是从公知公用的术语中选择的，但是本申请说明书中所提及的一些术语可能是申请人按他或她的判断来选择的，其详细含义在本文的描述的相关部分中说明。此外，要求不仅仅通过所使用的实际术语，而是还要通过每个术语所蕴含的意义来理解本申请。
应当理解，当一个部件被称为“在另一个部件上”、“连接到另一个部件”、 “耦合于另一个部件”或“接触另一个部件”时，它可以直接在该另一个部件之上、连接于或耦合于、或接触该另一个部件，或者可以存在插入部件。相比之下，当一个部件被称为“直接在另一个部件上”、“直接连接于”、“直接耦合于”或“直接接触”另一个部件时，不存在插入部件。同样的，当第一个部件被称为“电接触”或“电耦合于”第二个部件，在该第一部件和该第二部件之间存在允许电流流动的电路径。该电路径可以包括电容器、耦合的电感器和/或允许电流流动的其它部件，甚至在导电部件之间没有直接接触。
本申请中使用了流程图用来说明根据本申请的实施例的系统所执行的操作。应当理解的是，前面或下面操作不一定按照顺序来精确地执行。相反，可以按照倒序或同时处理各种步骤。同时，或将其他操作添加到这些过程中，或从这些过程移除某一步或数步操作。
本申请的实施例描述一种DDR存储器数据读写调度方法和装置。
图1是本申请一实施例的DDR存储器数据读写调度方法的流程图。图2是本申请另一实施例的DDR存储器数据读写调度方法的流程图。
如图1所例示，DDR存储器数据读写调度方法包括，步骤101，接收多个主接口的读写请求指令；步骤102，获取每个所述主接口的多条所述读写请求指令对应的请求数据在所述DDR存储器上的存储地址分布方式；步骤103，根据所述请求数据在所述DDR存储器上的存储地址分布方式，仲裁得到对所述多个主接口的读写请求指令的第一优先级响应方式；步骤104，基于所述第一优先级响应方式进行第一数据读写操作。
图3是本申请一实施例的DDR存储器的结构示意图。
如图3所例示，DDR存储器301包括多个存储块(Bank)组成。图3中示出的也可理解为DDR存储器301的一面(Rank)或一侧(Side)，一面是相对于包括正面和反面的两面而言，一侧则是相对于DDR存储器的两侧而言。图3标示了第1面(Rank 1)或第1侧(Side 1)。
图3的例示中，DDR存储器301的一侧可包括多个存储芯片(存储IC)。图3中标示出存储芯片311、312、318等。每一存储芯片可包括多个存储块(Bank)。例如存储芯片311(对应的放大图示结构为321)包括Bank1(块1)、Bank2(块2)、……、Bank8(块8)等8个存储块。
在一实施例中，存储芯片311包含的多个存储块中的一个存储块(用块n指代)的放大结构如图3中的331所例示。继续参考图3，存储块331包括行解码器(Row Decoder)341、列解码器(Column Decoder)342、传感放大器(Sense Amplifier)345和内存矩阵(Memory Matrix)346。
内存阵列由行列组成，每个行列交叉的单元，表示N bit，通常是8bit或者16位，其中每一位都是由一个晶体管和一个电容组成，例如在GDDR5(第五版图形用DDR)和HBM(高带宽显存)内存中，通常为32Byte，表示一个字节或者一个word(字)。
存储芯片311(对应的放大图示结构为321)还可包括数据输入/输出缓存(Data Input/Output Buffers)351。数据输入/输出缓存351可对数据进行输入/输出，以便对数据进行读写操作。352例如指来自其他存储块的数据输入，353例如指输出至存储器总线。
图4是本申请一实施例的DDR存储器的存储块读写操作示意图。
参考图3和图4，存储块(Bank)中的每一行组成一个page(页)，每一行又包括很多列(这里列是指单个交叉单元)。
DDR内存读写的最小单位就是这些交叉单元，通常只有这些单元被放入传感放大器的时候，才能够被读写，如图4所示，传感放大器与数据管脚(DATA PINS)408之间进行数据交互，所以通常要不断在行和传感放大器之间移动数据。图4中还示出了N BITS(N位)，指多个行列交叉单元。
把一行放入传感放大器称作“ACTIVATE”(激活)，因为这个操作会激活Bank。把传感放大器(图4中标示为SENSE AMPS)406的内容放入行，称作“PRECHARGE”(预充电)。有时。READ(读操作)或者WRITE(写操作)的时候会隐含着PRECHARGE的操作，称作AP-READ或者AP-WRITE，AP指auto precharge。
图4中的箭头①表示激活(ACTIVATE)操作，箭头②表示读操作或写操作。箭头③表示预充电(PRECHARGE)操作。
图5是本申请一实施例的DDR存储器的存储块读写操作状态机示意图。
如果图5所例示，存储块，例如SDRAM型的存储块的读写可以用一个的状态机来描述，它的状态包括空闲状态(IDLE)511，激活操作状态(Activating) 512，块激活状态(Bank Active)513，预充电操作状态(Precharging)518，刷新操作状态(Refreshing)519，读状态(Reading)515，写状态(Writing)514，读及自动充电操作状态(Read with Auto-Precharge)517，写及自动充电状态(Write with Auto-Precharge)516。图5所例示的状态机，从一个状态转换到另一个状态，并在新的状态开始数据操作，都需要一些最小等待时间，这些时延会影响SDRAM型存储块读写数据的性能，从而影响整个计算系统的性能。
SDARM Bank(SDRAM型的存储块)中的内存单元行列交叉(通常称作cel l)点，用来存储数据，它通常都是一些电容和放大器组成，
由于电容的特性，它的电量会随着时间衰减，比如温度等因素都会影响它的衰减速度，所以需要周期性进行加电刷新操作，维持其中的数据。
刷新频率通常依赖于内存die的工艺以及cell本身的设计。对内存cell的读写和内存刷新有相同的效果，但是在电容电量衰减到必须刷新之前，并不是所有的内存cell都有读写操作，所以定时刷新仍是需要的。
通常刷新操作是按行(row)或者说按page进行的，刷新之后，该行cell的电容就会被充电。通常的刷新操作周期是几百个clocks(时钟)到几千个clocks。在刷新命令之前，每个Bank必须要先precharged，然后处于IDLE状态，这需要消耗一个tRP时延。
Precharge(或记作PRECHARGE)一个打开的bank所消耗的时间称作the Row Access Strobe(RAS)Precharge Delay，通过写作tRP。
在一个刷新命令完成后，所有的bank处于precharge(IDLE)状态，在刷新命令和下一个activate命令(ACT)之间cycles(时钟周期)数目必须大于等于tRFC(the Row Refresh Cycle Time)。
SDRAM在响应读写命令之前，bank必须处于激活状态，内存控制器通过发送activate命令，指定被访问的rank，bank以及page(或row)。
Bank激活之后，传感放大器中有完整page内容，这个时候，可以发送读写命令，指定从某列开始读写数据。
从某个激活的page(放在传感放大器中)中读取一个byte数据消耗的时间，包括在读写接口发送读写命令，program控制逻辑，把传感放大器的内容传输 入到输入输出缓冲，并把数据的第一个word放在内存总线上总共消耗的时间。
一个Bank每次只能打开一个page(这里的打开即是指把page内容放入到传感放大器)，对于处于打开状态的page，可对其进行读写操作，如果不需要再对该page进行读写操作，可以关闭该page,把该page内容从传感放大器中写入Bank的行列单元对应的page中，以便对其它page进行读写操作。这个关闭操作通过一个PRECHARGE命令实现，PRECHARGE命令可以关闭某一个Bank，也可以关闭Rank中所有打开的Bank。PRECHARGE命令把传感放大器中的数据写入bank中对应的page中，然后可准备下一个数据访问。图5中，501表示初始化时序(Initialization Sequence)。图5中还包括图例，其中图例①表示指令时序(Command Sequence)，图例②表示自动时序(Automatic Sequence)。
图5中的箭头③表示连续的写操作，箭头④表示连续的读操作。
为尽可能减小PRECHARGE操作在数据读写操作中占用的时间，提高数据处理效率，本申请的DDR存储器数据读写调度方法的步骤前述的步骤101至步骤104所例示。
具体地，在步骤101，接收多个主接口(Master)的读写请求指令。主接口的类型可根据系统的总线类型和协议类型的不同而有所差异，例如包括ARM系统中的AMBA类型总线，采用AXI协议类型的主接口(AXI Master)。多个主接口例如包括Master0、Master1、Master2、…、Master N-1，N为正整数。多个主接口中的每一主接口可发送多条读写请求指令。
在步骤102，获取每个所述主接口的多条所述读写请求指令对应的请求数据在所述DDR存储器上的存储地址分布方式。
在一些实施例中，所述请求数据在所述DDR存储器上的存储地址分布方式包括，位于DDR存储器上的同一存储块上的同一行、位于DDR存储器上的不同存储块上的同一行或不同行和位于DDR存储器上的同一存储块上的不同行。同一存储块(Bank)上的同一行(Row)、不同存储块上的同一行或不同行以及同一存储块上的不同行的分布方式可参考图3和图4进行理解。
其中，所述请求数据位于DDR存储器上的同一存储块(Bank)上的同一行(Row)可称为页命中(PageHit)。
在步骤103，根据所述请求数据在所述DDR存储器上的存储地址分布方式，仲裁得到对所述多个主接口的读写请求指令的第一优先级响应方式。
在一些实施例中，根据所述请求数据在所述DDR存储器上的存储地址分布方式，仲裁得到对所述多个主接口的读写请求指令的第一优先级响应方式包括：所述请求数据位于DDR存储器上的同一存储块上的同一行被仲裁为所述第一优先级响应方式中的第一等级优先级；所述请求数据位于DDR存储器上的不同存储块上的同一行或不同行被仲裁为所述第一优先级响应方式中的第二等级优先级；所述请求数据位于DDR存储器上的同一存储块上的不同行被仲裁为所述第一优先级响应方式中的第三等级优先级。
在步骤104，基于所述第一优先级响应方式进行第一数据读写操作。对基于第一优先级响应方式确定进行响应的主接口，进行第一数据读写操作。
本申请的DDR存储器数据读写调度方法，基于主接口的读写请求对应的请求数据的分布方式的不同，确定对主接口的读写请求的响应优先级，从而实现尽可能减小PRECHARGE(预充电)操作在数据读写操作中占用的时间，提高数据处理效率。
参考图2，在本申请一些实施例中，除了与步骤101至步骤104相似的步骤201至步骤204以外，还包括，步骤205，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断，确定是否需重新所述仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式；步骤206，基于所述第二优先级响应方式进行第二数据读写操作。
在一些实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口在所述第一优先级响应方式中的被连续仲裁为第一等级优先级的次数是否超过第一阈值。
如前述，所述请求数据位于DDR存储器上的同一存储块(Bank)上的同一行(Row)可称为页命中(PageHit)。此时，对应的主接口的读写请求指令被仲裁为所述第一优先级响应方式中的第一等级优先级，进入页命中锁定(PageHitLock)状态。
但如果判断一个所述主接口在所述第一优先级响应方式中的被连续仲裁为第一等级优先级的次数超过第一阈值，为避免一个主接口长时间占用DDR存 储器的数据读写通道，影响系统的调度操作，则将对应的主接口转为锁定释放(PageHitLock Release)状态，并进行重新仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式。
在一些实施例中，重新进行所述仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式，可参考步骤103的方式进行。
在一些实施例中，所述次数中的每一次以Y个时钟周期(cycle)为单位，Y为正整数。
在一些实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令的时间间隔是否超过第二阈值。如果判断一个所述主接口的读写请求指令的时间间隔超过第二阈值，也可称为主接口的读写请求不连续，则将对应的主接口从响应状态转为响应释放(Release)状态。特别地，如果所述主接口处于页命中锁定(PageHitLock)状态，则将对应的主接口转为锁定释放(PageHitLock Release)状态。而后，进行重新仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式。
在一些实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令的响应时长是否超过第三阈值，也可称为主接口的读写请求出现Timeout。如果判断一个所述主接口的读写请求指令的响应时长超过第三阈值，则将对应的主接口从响应状态转为响应释放(Release)状态。特别地，如果所述主接口处于页命中锁定(PageHitLock)状态，则将对应的主接口转为锁定释放(PageHitLock Release)状态。
而后，进行重新仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式。再基于所述第二优先级响应方式进行第二数据读写操作。
在一些实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口进行第一数据读写操作时是否存在其他主接口的即时响应优先级读写请求。即时响应优先级读写请求例如包括为满足系统的延时规则的读写请求，需要被以超高优先级响应，以保持系统的正常运行，并实现读写操作的有效进行。如果判断存在其他主接口的即时响应优先级读写请求，则将当前响应的主接口从响应状态转为响应释放(Release)状 态，进行重新仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式，此时具体为对发出即时响应优先级读写请求的主接口进行相应。再基于所述第二优先级响应方式进行第二数据读写操作。
在一些实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令中未返回请求数据的指令的数量是否超过第四阈值，在一些类型的SoC系统中，也可称为主接口的outstanding参数达到设定的门限值。
如果判断一个所述主接口的读写请求指令中未返回请求数据的指令的数量超过第四阈值，则将当前响应的主接口从响应状态转为响应释放(Release)状态，进行重新仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式。重新进行所述仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式，可参考步骤103的方式进行。
在一些实施例中，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令对应的请求数据的大小是否超过所述主接口的缓存空间。如果判断一个所述主接口的读写请求指令对应的请求数据的大小超过所述主接口的缓存空间，为保证该主接口的读写操作的正常和有效进行，则将当前响应的主接口从响应状态转为响应释放(Release)状态，进行重新仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式。
在一些实施例中，对于在第一优先级响应方式中被判定为较高优先级，例如第一等优先级或第二等优先级的主接口，在进行重新仲裁，得到第二优先级相应方式时，将先前在第一优先级响应方式被相应的主接口的优先级调为最低。经过设定的时间间隔后，再让其重新参与仲裁。
本申请的DDR存储器数据读写调度方法，在实现尽可能减小PRECHARGE操作在数据读写操作中占用的时间的基础上，还能够实现对多个主接口的读写请求的高效调度，提高数据读写操作的效率。
本申请还提供一种DDR存储器数据读写调度装置。
图6是本申请一实施例的DDR存储器数据读写调度装置的示意图。
如图6所示，DDR存储器数据读写调度装置600包括指令接收模块602、 优先级仲裁模块604和数据读写模块606。
在一些实施例中，指令接收模块602被用于接收多个主接口的读写请求指令。优先级仲裁模块604被配置为，先获取每个所述主接口的多条所述读写请求指令对应的请求数据在所述DDR存储器上的存储地址分布方式；再根据所述请求数据在所述DDR存储器上的存储地址分布方式确定对所述多个主接口的读写请求指令的第一优先级响应方式。
数据读写模块606则用于基于所述第一优先级响应方式进行第一数据读写操作。
在一些实施例中，优先级仲裁模块604还被配置为，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断，确定对所述多个主接口的读写请求指令的第二优先级响应方式。数据读写模块606还基于所述第二优先级响应方式进行第二数据读写操作。
本申请的DDR存储器数据读写调度装置，能够实现尽可能减小PRECHARGE操作在数据读写操作中占用的时间，还能够实现对多个主接口的读写请求的高效调度，提高数据读写操作的效率。
上文已对基本概念做了描述，显然，对于本领域技术人员来说，上述发明披露仅仅作为示例，而并不构成对本申请的限定。虽然此处并没有明确说明，本领域技术人员可能会对本申请进行各种修改、改进和修正。该类修改、改进和修正在本申请中被建议，所以该类修改、改进、修正仍属于本申请示范实施例的精神和范围。
同时，本申请使用了特定词语来描述本申请的实施例。如“一个实施例”、“一实施例”、和/或“一些实施例”意指与本申请至少一个实施例相关的某一特征、结构或特点。因此，应强调并注意的是，本说明书中在不同位置两次或多次提及的“一实施例”或“一个实施例”或“一替代性实施例”并不一定是指同一实施例。此外，本申请的一个或多个实施例中的某些特征、结构或特点可以进行适当的组合。
本申请的一些方面可以完全由硬件执行、可以完全由软件(包括固件、常驻软件、微码等)执行、也可以由硬件和软件组合执行。以上硬件或软件均可被称为“数据块”、“模块”、“引擎”、“单元”、“组件”或“系统”。 处理器可以是一个或多个专用集成电路(ASIC)、数字信号处理器(DSP)、数字信号处理器件(DAPD)、可编程逻辑器件(PLD)、现场可编程门阵列(FPGA)、处理器、控制器、微控制器、微处理器或者其组合。此外，本申请的各方面可能表现为位于一个或多个计算机可读介质中的计算机产品，该产品包括计算机可读程序编码。例如，计算机可读介质可包括，但不限于，磁性存储设备(例如，硬盘、软盘、磁带……)、光盘(例如，压缩盘CD、数字多功能盘DVD……)、智能卡以及闪存设备(例如，卡、棒、键驱动器……)。
计算机可读介质可能包含一个内含有计算机程序编码的传播数据信号，例如在基带上或作为载波的一部分。该传播信号可能有多种表现形式，包括电磁形式、光形式等等、或合适的组合形式。计算机可读介质可以是除计算机可读存储介质之外的任何计算机可读介质，该介质可以通过连接至一个指令执行系统、装置或设备以实现通讯、传播或传输供使用的程序。位于计算机可读介质上的程序编码可以通过任何合适的介质进行传播，包括无线电、电缆、光纤电缆、射频信号、或类似介质、或任何上述介质的组合。
同理，应当注意的是，为了简化本申请披露的表述，从而帮助对一个或多个发明实施例的理解，前文对本申请实施例的描述中，有时会将多种特征归并至一个实施例、附图或对其的描述中。但是，这种披露方法并不意味着本申请对象所需要的特征比权利要求中提及的特征多。实际上，实施例的特征要少于上述披露的单个实施例的全部特征。
一些实施例中使用了描述成分、属性数量的数字，应当理解的是，此类用于实施例描述的数字，在一些示例中使用了修饰词“大约”、“近似”或“大体上”来修饰。除非另外说明，“大约”、“近似”或“大体上”表明所述数字允许有±20％的变化。相应地，在一些实施例中，说明书和权利要求中使用的数值参数均为近似值，该近似值根据个别实施例所需特点可以发生改变。在一些实施例中，数值参数应考虑规定的有效数位并采用一般位数保留的方法。尽管本申请一些实施例中用于确认其范围广度的数值域和参数为近似值，在具体实施例中，此类数值的设定在可行范围内尽可能精确。
虽然本申请已参照当前的具体实施例来描述，但是本技术领域中的普通技术人员应当认识到，以上的实施例仅是用来说明本申请，在没有脱离本申请精 神的情况下还可作出各种等效的变化或替换，因此，只要在本申请的实质精神范围内对上述实施例的变化、变型都将落在本申请的权利要求书的范围内。

Claims (13)

  1. 一种DDR存储器数据读写调度方法，包括以下步骤：
    接收多个主接口的读写请求指令；
    获取每个所述主接口的多条所述读写请求指令对应的请求数据在所述DDR存储器上的存储地址分布方式；
    根据所述请求数据在所述DDR存储器上的存储地址分布方式，仲裁得到对所述多个主接口的读写请求指令的第一优先级响应方式；
    基于所述第一优先级响应方式进行第一数据读写操作。
  2. 根据权利要求1所述的DDR存储器数据读写调度方法，其特征在于，还包括：
    基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断，确定是否需重新所述仲裁，得到对所述多个主接口的读写请求指令的第二优先级响应方式；
    基于所述第二优先级响应方式进行第二数据读写操作。
  3. 根据权利要求1所述的DDR存储器数据读写调度方法，其特征在于，所述请求数据在所述DDR存储器上的存储地址分布方式包括，位于DDR存储器上的同一存储块上的同一行、位于DDR存储器上的不同存储块上的同一行或不同行和位于DDR存储器上的同一存储块上的不同行。
  4. 根据权利要求3所述的DDR存储器数据读写调度方法，其特征在于，根据所述请求数据在所述DDR存储器上的存储地址分布方式，仲裁得到对所述多个主接口的读写请求指令的第一优先级响应方式包括：
    所述请求数据位于DDR存储器上的同一存储块上的同一行被仲裁为所述第一优先级响应方式中的第一等级优先级；所述请求数据位于DDR存储器上的不同存储块上的同一行或不同行被仲裁为所述第一优先级响应方式中的第二等级优先级；所述请求数据位于DDR存储器上的同一存储块上的不同行被仲裁为所述第一优先级响应方式中的第三等级优先级。
  5. 根据权利要求2所述的DDR存储器数据读写调度方法，其特征在于，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口在所述第一优先级响应方式中的被连续仲裁为第一等级的次数是否超过第一阈值。
  6. 根据权利要求2所述的DDR存储器数据读写调度方法，其特征在于，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令的时间间隔是否超过第二阈值。
  7. 根据权利要求2所述的DDR存储器数据读写调度方法，其特征在于，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令的响应时长是否超过第三阈值。
  8. 根据权利要求2所述的DDR存储器数据读写调度方法，其特征在于，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口进行第一数据读写操作时是否存在其他主接口的即时响应优先级读写请求。
  9. 根据权利要求2所述的DDR存储器数据读写调度方法，其特征在于，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令中未返回请求数据的指令的数量是否超过第四阈值。
  10. 根据权利要求2所述的DDR存储器数据读写调度方法，其特征在于，基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断包括，一个所述主接口的读写请求指令对应的请求数据的大小是否超过所述主接口的缓存空间。
  11. 根据权利要求5所述的DDR存储器数据读写调度方法，其特征在于，所述次数中的每一次以Y个时钟周期为单位，Y为正整数。
  12. 一种DDR存储器数据读写调度装置，包括：
    指令接收模块，用于接收多个主接口的读写请求指令；
    优先级仲裁模块，被配置为：
    获取每个所述主接口的多条所述读写请求指令对应的请求数据在所述DDR存储器上的存储地址分布方式；
    根据所述请求数据在所述DDR存储器上的存储地址分布方式确定对所述多个主接口的读写请求指令的第一优先级响应方式；
    数据读写模块，用于基于所述第一优先级响应方式进行第一数据读写操作。
  13. 根据权利要求12所述的DDR存储器数据读写调度装置，其特征在于，还包括：
    所述优先级仲裁模块还被配置为：
    基于所述读写请求指令的响应调度规则对所述第一数据读写操作进行判断，确定对所述多个主接口的读写请求指令的第二优先级响应方式；
    所述数据读写模块还基于所述第二优先级响应方式进行第二数据读写操作。
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