WO2023060997A1 - 实现控制电流变化功能的电路结构 - Google Patents

实现控制电流变化功能的电路结构 Download PDF

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WO2023060997A1
WO2023060997A1 PCT/CN2022/108951 CN2022108951W WO2023060997A1 WO 2023060997 A1 WO2023060997 A1 WO 2023060997A1 CN 2022108951 W CN2022108951 W CN 2022108951W WO 2023060997 A1 WO2023060997 A1 WO 2023060997A1
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field effect
effect transistor
type field
power
module
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PCT/CN2022/108951
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English (en)
French (fr)
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刘卫中
蒋亚平
张明丰
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华润微集成电路(无锡)有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to the field of drive control circuits, in particular to the field of power application circuits, and specifically refers to a circuit structure for realizing the function of controlling current change.
  • power devices such as IGBT (Insulated Gate Bipolar Translator, Insulated Gate Bipolar Transistor) (or MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, Metal-Oxide-Semiconductor Field Effect Transistor)) are usually used to Drive inductors and motors, etc.
  • IGBT Insulated Gate Bipolar Translator
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor, Metal-Oxide-Semiconductor Field Effect Transistor
  • FIG. 1 it is a half-bridge drive circuit structure commonly used in the prior art.
  • the circuit contains two sets of high-side and low-side power devices.
  • the low-side power tube When the low-side power tube is turned on, the high-side power tube is turned off; when the high-side power tube is turned on, the low-side power tube is turned off.
  • the two groups of power devices on the high side and the low side cannot be turned on at the same time, so as to prevent direct connection between the power supply and the ground to generate a large current and burn out.
  • the load is inductive
  • the power device on one side (such as the low side) is turned off, because of the continuity of the current in the inductive load, the power device on the other side (high side) is required to continue to flow (mainly parallel diodes) .
  • the low-side power tube is turned on again, if the high-side power tube is in the freewheeling state, then as the current of the low-side power tube increases, the state of the high-side power tube changes from the freewheeling state to the cut-off state, and the power device also The forward conduction of the PN junction is transformed into a depletion cut-off. Since this process is completed in a short time, the di/dt is very large, and the instantaneous power is very large. After the device’s bearing capacity is exceeded, the power device will be burned. Therefore, the limit peak current is necessary.
  • Power devices can be equivalent to a combination of PNP transistors and NMOS transistors.
  • the source-drain current Ids of the MOS tube controls the conduction current Ice of the power device.
  • the value of Ids is related to the gate-source voltage Vgs, so limiting the value of Vgs can control the conduction current Ice of the power device, thereby limiting the instantaneous power and achieving the protection effect.
  • Vgs value reduce the Vgs voltage or slow down the rising speed of Vgs
  • the circuit structure uses the clamp diode D21 to limit the highest gate voltage of the IGBT to control the peak current of the IGBT.
  • R21 with a smaller resistance can be used to keep the IGBT current at a faster rise rate during the turn-on phase and reduce the conduction
  • the conduction capability is also reduced, and the driving capability of the IGBT cannot be fully utilized. Therefore, the saturation voltage drop after the IGBT is turned on is also high, resulting in an increase in power loss.
  • the object of the present invention is to overcome the above-mentioned shortcomings of the prior art, and provide a circuit structure for realizing the function of controlling current change, which satisfies high utilization rate, simple operation and wide application range.
  • circuit structure of the present invention to realize the function of controlling current change is as follows:
  • circuit structure includes:
  • a drive circuit module the input terminal of which receives an input signal
  • a delay clamping circuit module connected to the driving circuit module, and receiving the input signal
  • a power module the input end of the power module is connected to the output end of the driving circuit module to receive the output signal Vo of the driving circuit module, and the input end of the power module is also connected to the delay clamp
  • the output terminals of the bit circuit modules are connected;
  • the delay clamping circuit module includes:
  • a delay circuit unit is connected to the drive circuit module and receives an input signal
  • the clamping circuit unit is connected with the delay circuit unit and also connected with the driving circuit module;
  • the time delay clamping circuit module limits the gate voltage value of the power tube during the turn-on phase of the power tube of the drive circuit module, and limits the peak current and reverse recovery current of the power tube after the turn-on phase and the rate of change; the delay clamping circuit module controls the release of the clamping phase, and increases the grid voltage of the power transistor of the driving circuit module to a normal value.
  • the delay circuit unit includes a second P-type field effect transistor, a third resistor and a capacitor, the gate of the second P-type field effect transistor is connected to the input signal, and the drain is connected to the input signal through the capacitor. Grounded, source and substrate connected to power, one end of the third resistor receives the input signal, and the other end is connected to the capacitor.
  • the clamping circuit unit includes a clamping device and a second N-type field effect transistor, the gate of the second N-type field effect transistor is connected to the drain of the second P-type field effect transistor Connected, the source of the second N-type field effect transistor is connected to the substrate and then grounded, one end of the clamping device is connected to the drain of the second N-type field effect transistor, and the other end is connected to the drive circuit
  • the modules are connected.
  • the drive circuit module includes a first P-type field effect transistor, a first N-type field effect transistor, a first resistor, a second resistor and an inverter, and the first P-type field effect transistor
  • the grid is connected to the output terminal of the inverter, the source and substrate of the first P-type field effect transistor are connected to the power supply, and the source and substrate of the first N-type field effect transistor are connected to each other.
  • the bottom is connected to the ground, the gate of the first N-type field effect transistor is connected to the output terminal of the inverter, and the drain of the first P-type field effect transistor is connected to the first N-type field effect transistor.
  • the drain of the field effect transistor is connected in series with the second resistor through the first resistor, the input terminal of the inverter is connected to the input signal, and the output terminal is connected to one end of the third resistor of the delay circuit unit.
  • the power module includes a power tube
  • the gate of the power tube is connected to the output terminal of the clamping circuit unit, and is also connected to the drive circuit module, and the gate of the power tube
  • the drain is connected to the load, and the source of the power tube is grounded.
  • the clamping device is composed of at least one set of zener tubes and/or at least one set of PN junctions, and the clamping device includes at least one set of zener tubes and/or at least one set of PN junctions connected in series PN junction.
  • the clamping device further includes a resistor connected in parallel with the at least one set of Zener transistors and at least one set of PN junctions connected in series.
  • the delay circuit unit includes a second P-type field effect transistor, a third resistor, a capacitor and a third N-type field effect transistor, and the gate of the second P-type field effect transistor is connected to the Input signal, the drain is also grounded through the capacitor, the source and the substrate are connected to the power supply, one end of the third resistor is connected to the drain of the second P-type field effect transistor, and the other end is connected to the third resistor.
  • the drain of the N-type field effect transistor is connected, and the source and the substrate of the third N-type field effect transistor are grounded.
  • the clamping circuit unit includes an amplifier, a second N-type field effect transistor and a third P-type field effect transistor, the inverting input terminal of the amplifier is connected to the input terminal of the power module, and the output The terminal is connected to the gate of the third P-type field effect transistor, the positive phase input terminal is connected to the reference voltage, the source and the substrate of the third P-type field effect transistor are connected to the input terminal of the power module, The drain of the second N-type field effect transistor is connected to the drain of the third P-type field effect transistor, and the source and gate of the second N-type field effect transistor are grounded.
  • FIG. 1 is a schematic structural diagram of a half-bridge driving circuit in the prior art.
  • FIG. 2 is a schematic diagram of a circuit structure for realizing the function of controlling current change according to the present invention.
  • FIG. 3 is a schematic diagram of a clamping circuit structure of a circuit structure for realizing the function of controlling current variation in the present invention.
  • FIG. 4 is a schematic diagram of a clamping device with a circuit structure for realizing the function of controlling current variation according to the present invention.
  • FIG. 5 is a schematic diagram of another embodiment of the circuit structure for realizing the function of controlling current change according to the present invention.
  • the present invention designs a drive control circuit in combination with practical applications, which can effectively control the size of di/dt when the power tube is turned on, reduce the impact of reverse recovery current, and reduce EMI , and at the same time after the end of the turn-on, the normal gate drive voltage is restored without affecting the output capability of the device.
  • the circuit structure of the present invention to realize the function of controlling current change includes:
  • the input terminal receives an input signal
  • a delay clamping circuit module is connected to the driving circuit module and receives an input signal
  • a power module the input end of the power module is connected to the output end of the driving circuit module, and receives the output signal Vo of the driving circuit module, and the input end of the power module is also connected to the delay clamping circuit module The output is connected;
  • the delay clamping circuit module includes:
  • a delay circuit unit is connected to the drive circuit module and receives an input signal
  • the clamping circuit unit is connected with the delay circuit unit and also connected with the driving circuit module;
  • the time delay clamping circuit module limits the gate voltage value of the power tube during the turn-on phase of the power tube of the drive circuit module, and limits the peak current and reverse recovery current of the power tube after the turn-on phase and the rate of change; the delay clamping circuit module controls the release of the clamping phase, and increases the grid voltage of the power transistor of the driving circuit module to a normal value.
  • the delay circuit unit includes a second P-type field effect transistor MP32, a third resistor R33 and a capacitor C31, and the second P-type field effect transistor MP32
  • the gate of the third resistor R33 is connected to the input signal, the drain is grounded through the capacitor C31, the source and the substrate are connected to the power supply, one end of the third resistor R33 receives the input signal, and the other end is connected to the capacitor C31.
  • the clamping circuit unit includes a clamping device T01 and a second N-type field effect transistor MN32, and the gate of the second N-type field effect transistor MN32 It is connected to the drain of the second P-type field effect transistor MP32, the source of the second N-type field effect transistor MN32 is connected to the substrate and then grounded, and one end of the clamping device T01 is connected to the second N-type field effect transistor MN32.
  • the drain of the type field effect transistor MN32 is connected, and the other end is connected with the driving circuit module.
  • the drive circuit module includes a first P-type field effect transistor MP31, a first N-type field effect transistor MN31, a first resistor R31, a second resistor R32 and an inverter Inverter INV1, the gate of the first P-type field effect transistor MP31 is connected to the output terminal of the inverter INV1, and the source and substrate of the first P-type field effect transistor MP31 are connected to each other.
  • the power supply is connected, the source and the substrate of the first N-type field effect transistor MN31 are connected to the ground, and the gate of the first N-type field effect transistor MN31 is connected to the output terminal of the inverter INV1 , the drain of the first P-type field effect transistor MP31 is connected in series with the drain of the first N-type field effect transistor MN31 through the first resistor R31 and the second resistor R32, and the reverse phase
  • the input terminal of the device INV1 is connected to the input signal, and the output terminal is connected to one end of the third resistor R33 of the delay circuit unit.
  • the power module includes a power tube
  • the gate of the power tube is connected to the output terminal of the clamping circuit unit, and is also connected to the driving circuit module.
  • the drain of the power tube is connected to the load, and the source of the power tube is grounded.
  • the clamping device is composed of at least one set of Zener tubes and/or at least one set of PN junctions, and the clamping device includes at least one series connection A set of Zener tubes and/or at least a set of PN junctions.
  • the clamping device further includes a resistor connected in parallel with the at least one set of zener transistors and at least one set of PN junctions connected in series.
  • the delay circuit unit includes a second P-type field effect transistor MP32, a third resistor R33, a capacitor C31 and a third N-type field effect transistor MN33, the The gate of the second P-type field effect transistor MP32 is connected to the input signal, the drain is also connected to the ground through the capacitor C31, the source and the substrate are connected to the power supply, and one end of the third resistor R33 is connected to the second resistor R33.
  • the drain of the P-type field effect transistor MP32 is connected, and the other end is connected with the drain of the third N-type field effect transistor MN33, and the source and substrate of the third N-type field effect transistor MN33 are grounded.
  • the clamping circuit unit includes an amplifier OPA1, a second N-type field effect transistor MN32 and a third P-type field effect transistor MP33, the reverse of the amplifier OPA1
  • the phase input terminal is connected to the input terminal of the power module
  • the output terminal is connected to the gate of the third P-type field effect transistor MP33
  • the positive phase input terminal is connected to the reference voltage
  • the third P-type field effect transistor MP33 The source and substrate of the power module are connected to the input terminal of the power module
  • the drain of the second N-type field effect transistor MN32 is connected to the drain of the third P-type field effect transistor MP33
  • the second The source and gate of the NFET MN32 are grounded.
  • Figure 2 is a schematic structure of the present invention: different from the conventional drive circuit structure, the present invention consists of a delay clamp circuit module, a drive circuit module and a power module.
  • Figure 3 shows the internal structure for realizing this function, which is also the technical solution of the present invention.
  • the invention patent consists of a drive circuit, a delay clamp circuit, and a power module.
  • the drive circuit includes an inverter INV1, the first P-type field effect transistor MP31 and the first N-type field effect transistor MN31, the first resistor R31 and the second resistor R32;
  • the power module is composed of power MOSFET or IGBT and other devices, and the input is the drive The output signal Vo of the circuit;
  • the delay clamp circuit is composed of a delay circuit and a clamp circuit: the delay circuit is composed of a second P-type field effect transistor MP32, a third resistor R33 and a capacitor C31;
  • the clamp circuit is composed of a second N Type FET MN32 and clamp devices.
  • the output Wv1 of the inverter INV1 of the drive circuit changes from high level to low level, the first N-type field effect transistor MN31 is turned off, the first P-type field effect transistor MP31 is turned on, and the power is passed through the first P-type field effect transistor MP31 , the first resistor R31 charges the gate of the IGBT device, and the voltage of Vo rises;
  • the second P-type field effect transistor MP32 in the delay circuit is also turned off synchronously, and the charge on the capacitor C31 is discharged to the Wv1 node through the third resistor R33, that is, it flows to the output terminal of the inverter INV1 in the drive circuit; at this time, The voltage of Wv2 is still at a high level, but with the discharge of the charge on the capacitor C31, the voltage will slowly drop;
  • the second N-type field effect transistor MN32 is in the conduction state. At this time, it can be considered that the clamping structure is connected to the ground through the second N-type field effect transistor MN32. Assuming that the clamping voltage of the voltage clamping structure is Vz1, that is, in this turn-on phase, the voltage of the Vo node is limited near Vz1, that is, the output voltage generated by the driving circuit is clamped, thereby limiting the gate voltage of the power device.
  • the setting of Vz1 can be determined with reference to the relationship between the gate voltage and current of the power device.
  • the conduction time of the second N-type field effect transistor MN32 can be passed by the third resistor R33, The value of the capacitor C31 is adjusted, and the value of the third resistor R33 and the capacitor C31 is set appropriately, so that the second N-type field effect transistor MN32 remains on during the turn-on phase, thereby limiting the gate voltage of the power device and controlling the peak current of the power device. the goal of.
  • the clamping function is turned off, and the gate voltage of the IGBT device can continue to rise to VCC, so that the IGBT device can obtain sufficient conduction capability, reduce the saturation voltage drop Vcesat during the conduction period, and reduce Small power loss.
  • the inverter INV1 in the drive circuit outputs a high level, that is, Wv1 becomes high, the first P-type field effect transistor MP31 is turned off, the first N-type field effect transistor MN31 is turned on, the voltage of the Vo point drops, and the power device decreases due to the gate voltage And off.
  • the second P-type field effect transistor MP32 in the delay circuit is turned on to charge the capacitor C31, so that the voltage on Wv2 point rises rapidly, so that the second N-type field effect transistor MN32 is turned on, and the clamping structure is connected to Vo and ground Between, the condition is established for the clamping function of the next cycle; because the Vo potential at this time is low, it does not affect the working state of the circuit.
  • the point Wv1 is a high voltage, and the capacitor C31 can also be charged through the third resistor R33, thereby speeding up the voltage rise of the point Wv2.
  • the voltage clamp can be composed of multiple Zener tubes, PN junctions and resistors connected in series and parallel, as shown in Figure 4.
  • the amplifier OPA1 and the third P-type field effect transistor MP33 combined with a follower to form an active voltage limiting structure can also achieve the same effect.
  • the delay circuit unit in the circuit will clamp the power tube to turn on, and the output voltage generated by the drive circuit will be clamped to limit the grid voltage of the power device, thereby limiting the power tube conduction It also limits the size and rate of change of the reverse recovery current, which protects the power device; the clamping circuit unit in the circuit controls the release of the clamping function, and the grid voltage of the power tube of the power module increases to the normal value , so that it maintains sufficient conduction capability, reduces Vcesat, and reduces power loss.

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Abstract

一种实现控制电流变化功能的电路结构，包括驱动电路模块，输入端接收输入信号；时延箝位电路模块，与所述的驱动电路模块相连接，并接收所述输入信号；功率模块，所述功率模块的输入端与所述的驱动电路模块的输出端相连接，接收所述驱动电路模块的输出信号，且所述功率模块的输入端还与所述的时延箝位电路模块的输出端相连接。该实现控制电流变化功能的电路结构，利用时延结构将箝位作用在功率管开启阶段，从而限制功率管导通的峰值电流，也限制反向恢复电流的大小及变化速率，起到对功率器件的保护作用；在箝位阶段解除后，功率管栅压提高到正常值，使其维持足够的导通能力。

Description

实现控制电流变化功能的电路结构 技术领域
本发明涉及驱动控制电路领域，尤其涉及功率应用电路领域，具体是指一种实现控制电流变化功能的电路结构。
背景技术
在现有技术的功率应用中，通常采用IGBT(Insulated Gate Bipolar Translator，绝缘栅双极晶体管)(或MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管))等功率器件来驱动电感和电机等。在该功率电路结构中一般采用高、低侧两个功率器件半桥结构，或多组功率管的全桥结构，如图1所示即为现有技术中常用的半桥驱动电路结构。
如图1所示，电路中包含高侧和低侧两组功率器件，在低侧功率管导通时，高侧功率管关闭；高侧功率管导通时，低侧功率管关闭。所述的高、低侧两组功率器件在驱动电路的控制下不能同时导通，以防止电源地之间出现直通产生大电流而烧毁。
如果负载是感性的，在一侧(如低侧)的功率管关断时，因为感性负载中电流的连续性，需要另一侧(高侧)的功率器件续流(主要是并联的二极管)。当低侧功率管再次开启时，如果高侧功率管处于续流状态，那么随着低侧的功率管电流的增大，高侧功率管的状态由续流状态转换为截止状态，功率器件也表现为PN结的正向导通转变为耗尽截止，由于这个过程在较短的时间完成，导致di/dt很大，瞬时功率很大，超过器件的承受能力后将导致功率器件烧毁，因此限制峰值电流很有必要。
功率器件可等效为PNP管和NMOS管的组合。MOS管的源漏电流Ids大小控制了功率器件的导通电流Ice。Ids值的大小与栅源电压Vgs相关，因此限制Vgs的值就可以控制功率器件的导通电流Ice，从而限制瞬时功率，达到保护作用。
通常限制Vgs值的实现方式有以下两种：降低Vgs电压或减缓Vgs的上升速度；
(1)减缓Vgs的上升速度：
现有技术该电路结构带来的问题是开启期间IGBT的功耗增加，能源利用率降低；电流变化越缓慢，时间越长，消耗在IGBT上能量越多，造成发热。
(2)降低Vgs电压：
通常电路结构利用箝位二极管D21限制IGBT的最高栅压，以此控制IGBT的峰值电流， 同时可以采用较小阻值的R21，在开启阶段使IGBT电流保持较快的上升速度，减小导通损耗，但是因为栅压限制，导通能力也变小，不能充分发挥IGBT的驱动能力，因此在IGBT导通后其饱和压降也较高，导致功耗损失增加。
发明内容
本发明的目的是克服了上述现有技术的缺点，提供了一种满足利用率高、操作简便、适用范围较为广泛的实现控制电流变化功能的电路结构。
为了实现上述目的，本发明的实现控制电流变化功能的电路结构如下：
该实现控制电流变化功能的电路结构，其主要特点是，所述的电路结构包括：
驱动电路模块，其输入端接收输入信号；
时延箝位电路模块，与所述的驱动电路模块相连接，并接收所述输入信号；
功率模块，所述功率模块的输入端与所述的驱动电路模块的输出端相连接，接收所述驱动电路模块的输出信号Vo，且所述功率模块的输入端还与所述的时延箝位电路模块的输出端相连接；
其中，所述的时延箝位电路模块包括：
延时电路单元，与所述的驱动电路模块相连接，并接收输入信号；
箝位电路单元，与所述的延时电路单元相连接，还与所述的驱动电路模块相连接；
所述的时延箝位电路模块在所述驱动电路模块的功率管的开启阶段限制所述功率管的栅压值，并限制所述功率管开启阶段后的峰值电流以及反向恢复电流的大小及变化速率；所述的时延箝位电路模块控制箝位阶段解除，且提高所述驱动电路模块的功率管的栅压至正常值。
较佳地，所述的延时电路单元包括第二P型场效应管、第三电阻和电容，所述的第二P型场效应管的栅极接所述输入信号，漏极还通过电容接地，源极和衬底接电源，所述的第三电阻的一端接收所述输入信号，另一端与所述电容相连接。
较佳地，所述的箝位电路单元包括箝位器件和第二N型场效应管，所述的第二N型场效应管的栅极与所述第二P型场效应管的漏极相连，所述第二N型场效应管的源极和衬底相连后接地，所述箝位器件的一端与所述第二N型场效应管的漏极相连，另一端与所述驱动电路模块相连。
较佳地，所述的驱动电路模块包括第一P型场效应管、第一N型场效应管、第一电阻、第二电阻和反相器，所述的第一P型场效应管的栅极与所述的反相器的输出端相连，所述的第一P型场效应管的源极与衬底均与电源相连，所述的第一N型场效应管的源极和衬底与地相连，所述的第一N型场效应管的栅极与所述的反相器的输出端相连，所述的第一P型场效 应管的漏极与所述第一N型场效应管的漏极通过所述第一电阻和所述第二电阻串联，所述的反相器的输入端接输入信号，输出端与所述延时电路单元的第三电阻的一端相连。
较佳地，所述的功率模块包括功率管，所述的功率管的栅极与所述箝位电路单元的输出端相连，还与所述驱动电路模块均相接，所述的功率管的漏极与负载相连，所述的功率管的源极接地。
较佳地，所述的箝位器件由至少一组齐纳管和/或至少一组PN结组合而成，所述箝位器件包括串联连接的至少一组齐纳管和/或至少一组PN结。
较佳地，所述钳位器件还包括电阻，所述电阻与所述串联连接的至少一组齐纳管及至少一组PN结并联。
较佳地，所述的延时电路单元包括第二P型场效应管、第三电阻、电容和第三N型场效应管，所述的第二P型场效应管的栅极接所述输入信号，漏极还通过所述电容接地，源极及衬底接电源，所述的第三电阻的一端与所述第二P型场效应管的漏极相连，另一端与所述第三N型场效应管的漏极相连，所述的第三N型场效应管的与源极及衬底接地。
较佳地，所述的箝位电路单元包括放大器、第二N型场效应管和第三P型场效应管，所述的放大器的反相输入端与所述功率模块的输入端相连，输出端与所述第三P型场效应管的栅极相连，正相输入端接参考电压，所述的第三P型场效应管的源极及衬底与所述功率模块的输入端相连，所述的第二N型场效应管的漏极与所述第三P型场效应管的漏极相连，所述第二N型场效应管的源极与栅极接地。
采用了本发明的实现控制电流变化功能的电路结构，利用时延结构将箝位作用在功率管开启阶段，从而限制功率管导通的峰值电流，也限制反向恢复电流的大小及变化速率，起到对功率器件的保护作用；在箝位阶段解除后，功率管栅压提高到正常值，使其维持足够的导通能力，降低饱和压降Vcesat，减小功率损耗。
附图说明
图1为现有技术的半桥驱动电路结构示意图。
图2为本发明的实现控制电流变化功能的电路结构的示意图。
图3为本发明的实现控制电流变化功能的电路结构的箝位电路结构的示意图。
图4为本发明的实现控制电流变化功能的电路结构的箝位器件示意图。
图5为本发明的实现控制电流变化功能的电路结构的另一种实施例示意图。
具体实施方式
为了能够更清楚地描述本发明的技术内容，下面结合具体实的电路结构的结构图。施例来进行进一步的描述。
本发明基于功率器件(IGBT或MOSFET)的特性，结合实际应用，设计了一种驱动控制电路，可以有效控制功率管导通时的di/dt的大小，减小反向恢复电流冲击，降低EMI，同时在开启结束后，恢复正常的栅驱动电压，不影响器件的输出能力。
如图2所示，本发明的该实现控制电流变化功能的电路结构，其中包括：
驱动电路模块，输入端接收输入信号；
时延箝位电路模块，与所述的驱动电路模块相连接，并接收输入信号；
功率模块，该功率模块的输入端与所述的驱动电路模块的输出端相连接，接收驱动电路模块的输出信号Vo，且该功率模块的输入端还与所述的时延箝位电路模块的输出端相连接；
其中，所述的时延箝位电路模块包括：
延时电路单元，与所述的驱动电路模块相连接，并接收输入信号；
箝位电路单元，与所述的延时电路单元相连接，还与所述的驱动电路模块相连接；
所述的时延箝位电路模块在所述驱动电路模块的功率管的开启阶段限制所述功率管的栅压值，并限制所述功率管开启阶段后的峰值电流以及反向恢复电流的大小及变化速率；所述的时延箝位电路模块控制箝位阶段解除，且提高所述驱动电路模块的功率管的栅压至正常值。
如图3所示，作为本发明的优选实施方式，所述的延时电路单元包括第二P型场效应管MP32、第三电阻R33和电容C31，所述的第二P型场效应管MP32的栅极接所述输入信号，漏极还通过电容C31接地，源极和衬底接电源，所述的第三电阻R33的一端接收所述输入信号，另一端与所述电容C31相连接。
如图3所示，作为本发明的优选实施方式，所述的箝位电路单元包括箝位器件T01和第二N型场效应管MN32，所述的第二N型场效应管MN32的栅极与所述第二P型场效应管MP32的漏极相连，所述第二N型场效应管MN32的源极和衬底相连后接地，所述箝位器件T01的一端与所述第二N型场效应管MN32的漏极相连，另一端与所述驱动电路模块相连。
如图2所示，作为本发明的优选实施方式，所述的驱动电路模块包括第一P型场效应管MP31、第一N型场效应管MN31、第一电阻R31、第二电阻R32和反相器INV1，所述的第一P型场效应管MP31的栅极与所述的反相器INV1的输出端相连，所述的第一P型场效应管MP31的源极和衬底均与电源相连，所述的第一N型场效应管MN31的源极和衬底与地相连，所述的第一N型场效应管MN31的栅极与所述的反相器INV1的输出端相连，所述的第一P型场效应管MP31的漏极与所述第一N型场效应管MN31的漏极通过所述第一电阻R31 和所述第二电阻R32串联，所述的反相器INV1的输入端接输入信号，输出端与所述延时电路单元的第三电阻R33的一端相连。
作为本发明的优选实施方式，所述的功率模块包括功率管，所述的功率管的栅极与所述箝位电路单元的输出端相连，还与所述驱动电路模块均相接，所述的功率管的漏极与负载相连，所述的功率管的源极接地。
如图4所示，作为本发明的优选实施方式，所述的箝位器件由至少一组齐纳管和/或至少一组PN结组合而成，所述箝位器件包括串联连接的至少一组齐纳管和/或至少一组PN结。
所述钳位器件还包括电阻，所述电阻与所述串联连接的至少一组齐纳管及至少一组PN结并联。
如图5所示，作为本发明的优选实施方式，所述的延时电路单元包括第二P型场效应管MP32、第三电阻R33、电容C31和第三N型场效应管MN33，所述的第二P型场效应管MP32的栅极接所述输入信号，漏极还通过所述电容C31接地，源极及衬底接电源，所述的第三电阻R33的一端与所述第二P型场效应管MP32的漏极相连，另一端与所述第三N型场效应管MN33的漏极相连，所述的第三N型场效应管MN33的源极及衬底接地。
如图5所示，作为本发明的优选实施方式，所述的箝位电路单元包括放大器OPA1、第二N型场效应管MN32和第三P型场效应管MP33，所述的放大器OPA1的反相输入端与所述功率模块的输入端相连，输出端与所述第三P型场效应管MP33的栅极相连，正相输入端接参考电压，所述的第三P型场效应管MP33的源极及衬底与所述功率模块的输入端相连，所述的第二N型场效应管MN32的漏极与所述第三P型场效应管MP33的漏极相连，所述第二N型场效应管MN32的源极与栅极接地。
如图2是本发明的示意图结构：不同于常规驱动电路结构，本发明由时延箝位电路模块、驱动电路模块和功率模块组成。图3中展示了实现该功能的内部结构，也是本发明的技术方案。
本发明专利由驱动电路、时延箝位电路、功率模块组成。驱动电路包括反相器INV1、第一P型场效应管MP31和第一N型场效应管MN31、第一电阻R31和第二电阻R32；功率模块由功率MOSFET或IGBT等器件组成，输入为驱动电路的输出信号Vo；时延箝位电路由延时电路和箝位电路构成：延时电路由第二P型场效应管MP32、第三电阻R33和电容C31组成；箝位电路由第二N型场效应管MN32和箝位器件组成。
如图2和图3所示，本发明电路结构的工作过程如下：
1)输入信号IN由低电平变为高电平时：
驱动电路的反相器INV1输出Wv1由高电平变为低电平，第一N型场效应管MN31关闭，第一P型场效应管MP31导通，电源通过第一P型场效应管MP31、第一电阻R31对IGBT器件的栅极充电，Vo电压上升；
延时电路中的第二P型场效应管MP32也同步关闭，电容C31上的电荷通过第三电阻R33向Wv1节点泄放，即流向驱动电路中的反相器INV1的输出端；此时，Wv2的电压仍是高电平，但随着电容C31上电荷的泄放，电压会慢慢下降；
因为Wv2的电压仍是高电平，因此第二N型场效应管MN32处于导通状态，此时可认为箝位结构通过第二N型场效应管MN32与地连接。假设电压箝位结构的箝位电压为Vz1，即在这一开启阶段，Vo节点的电压被限制在Vz1附近，即驱动电路产生的输出电压被箝位了，从而限制了功率器件的栅压。Vz1的设置可参考功率器件栅压与电流的关系确定。
随着电容C31上电荷的泄放，Wv2点电压的下降，第二N型场效应管MN32因为栅压降低而关闭；第二N型场效应管MN32的导通时间可以通过第三电阻R33、电容C31的值来调整，设置合适的第三电阻R33、电容C31的值，使第二N型场效应管MN32在开启阶段维持导通，从而限制功率器件的栅压，达到控制功率器件电流峰值的目的。
当第二N型场效应管MN32关闭后，箝位功能关闭，IGBT器件的栅压可以继续上升到VCC，使的IGBT器件获得足够的导通能力，降低导通期间的饱和压降Vcesat，减小功率损耗。
2)当IN信号由高电平变为低电平时：
驱动电路中的反相器INV1输出高电平，即Wv1变为高，第一P型场效应管MP31关闭，第一N型场效应管MN31开启，Vo点电压下降，功率器件因栅压降低而关闭。
延时电路中的第二P型场效应管MP32导通，对电容C31充电，使Wv2点上的电压快速上升，使第二N型场效应管MN32导通，箝位结构连接于Vo和地之间，为下一个周期的箝位功能建立条件；因为此时的Vo电位为低电平，因此不影响电路的工作状态。
Wv1点为高电压，也可以通过第三电阻R33对电容C31充电，从而加快Wv2点电压的上升。
电压箝位可以用多个齐纳管、PN结及电阻等串并联组成，如图4所示。
如图5所示，其为本发明的另一种实施例，采用放大器OPA1、第三P型场效应管MP33组合跟随器形成有源限压结构，也可以实现同样的效果。
在本发明的上述技术方案中，电路中的延时电路单元将箝位作用在功率管开启阶段，驱动电路产生的输出电压被箝位，限制了功率器件的栅压，从而限制的功率管导通的峰值电 流，也限制反向恢复电流的大小及变化速率，起到对功率器件的保护作用；电路中的箝位电路单元控制箝位作用解除，功率模块的功率管栅压提高到正常值，使其维持足够的导通能力，降低Vcesat，减小功率损耗。
应当理解，本发明的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行装置执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列PGA，现场可编程门阵列FPGA等。
在此说明书中，本发明已参照其特定的实施例作了描述。但是，很显然仍可以作出各种修改和变换而不背离本发明的精神和范围。因此，说明书和附图应被认为是说明性的而非限制性的。

Claims (14)

  1. 一种实现控制电流变化功能的电路结构，其特征在于，所述的电路结构包括：
    驱动电路模块，所述驱动电路模块的输入端接收输入信号；
    时延箝位电路模块，所述时延箝位电路模块与所述的驱动电路模块相连接，并接收所述输入信号；
    功率模块，所述功率模块的输入端与所述的驱动电路模块的输出端相连接，接收所述驱动电路模块的输出信号，且所述功率模块的输入端还与所述的时延箝位电路模块的输出端相连接；
    其中，所述的时延箝位电路模块包括：
    延时电路单元，与所述的驱动电路模块相连接，并接收输入信号；
    箝位电路单元，与所述的延时电路单元相连接，还与所述的驱动电路模块相连接；
    所述的时延箝位电路模块在所述驱动电路模块的功率管的开启阶段限制所述功率管的栅压值，并限制所述功率管开启阶段后的峰值电流以及反向恢复电流的大小及变化速率；所述的时延箝位电路模块控制箝位阶段解除，且提高所述驱动电路模块的功率管的栅压至正常值。
  2. 根据权利要求1所述的实现控制电流变化功能的电路结构，其特征在于，所述的延时电路单元包括第二P型场效应管(MP32)、第三电阻(R33)和电容(C31)。
  3. 根据权利要求2所述的实现控制电流变化功能的电路结构，其特征在于，所述的第二P型场效应管(MP32)的栅极接所述输入信号，漏极还通过电容(C31)接地，源极和衬底接电源，所述的第三电阻(R33)的一端接收所述输入信号，另一端与所述电容(C31)相连接。
  4. 根据权利要求2所述的实现控制电流变化功能的电路结构，其特征在于，所述的箝位电路单元包括箝位器件(T01)和第二N型场效应管(MN32)，。
  5. 根据权利要求4所述的实现控制电流变化功能的电路结构，其特征在于，所述的第二N型场效应管(MN32)的栅极与所述第二P型场效应管(MP32)的漏极相连，所述第二N型场效应管(MN32)的源极和衬底相连后接地，所述箝位器件(T01)的一端与所述第二N型场效应管(MN32)的漏极相连，另一端与所述驱动电路模块相连。
  6. 根据权利要求2所述的实现控制电流变化功能的电路结构，其特征在于，所述的驱动电路模块包括第一P型场效应管(MP31)、第一N型场效应管(MN31)、第一电阻(R31)、第二电阻(R32)和反相器(INV1)。
  7. 根据权利要求6所述的实现控制电流变化功能的电路结构，其特征在于，所述的第一P 型场效应管(MP31)的栅极与所述的反相器(INV1)的输出端相连，所述的第一P型场效应管(MP31)的源极和衬底均与电源相连，所述的第一N型场效应管(MN31)的源极和衬底与地相连，所述的第一N型场效应管(MN31)的栅极与所述的反相器(INV1)的输出端相连，所述的第一P型场效应管(MP31)的漏极与所述第一N型场效应管(MN31)的漏极通过所述第一电阻(R31)和所述第二电阻(R32)串联，所述的反相器(INV1)的输入端接输入信号，输出端与所述延时电路单元的第三电阻(R33)的一端相连。
  8. 根据权利要求1所述的实现控制电流变化功能的电路结构，其特征在于，所述的功率模块包括功率管，所述的功率管的栅极与所述箝位电路单元的输出端相连，还与所述驱动电路模块均相接，所述的功率管的漏极与负载相连，所述的功率管的源极接地。
  9. 根据权利要求1所述的实现控制电流变化功能的电路结构，其特征在于，所述的箝位器件由至少一组齐纳管和/或至少一组PN结组合而成，所述箝位器件包括串联连接的至少一组齐纳管和/或至少一组PN结。
  10. 权利要求9所述的实现控制电流变化功能的电路结构，其特征在于，所述钳位器件还包括电阻，所述电阻与所述串联连接的至少一组齐纳管及至少一组PN结并联。
  11. 根据权利要求1所述的实现控制电流变化功能的电路结构，其特征在于，所述的延时电路单元包括第二P型场效应管(MP32)、第三电阻(R33)、电容(C31)和第三N型场效应管(MN33)。
  12. 根据权利要求11所述的实现控制电流变化功能的电路结构，其特征在于，所述的第二P型场效应管(MP32)的栅极接所述输入信号，漏极还通过所述电容(C31)接地，源极及衬底接电源，所述的第三电阻(R33)的一端与所述第二P型场效应管(MP32)的漏极相连，另一端与所述第三N型场效应管(MN33)的漏极相连，所述的第三N型场效应管(MN33)的源极及衬底接地。
  13. 根据权利要求11所述的实现控制电流变化功能的电路结构，其特征在于，所述的箝位电路单元包括放大器(OPA1)、第二N型场效应管(MN32)和第三P型场效应管(MP33)。
  14. 根据权利要求13所述的实现控制电流变化功能的电路结构，其特征在于，所述的放大器(OPA1)的反相输入端与所述功率模块的输入端相连，输出端与所述第三P型场效应管(MP33)的栅极相连，正相输入端接参考电压，所述的第三P型场效应管(MP33)的源极及衬底与所述功率模块的输入端相连，所述的第二N型场效应管(MN32)的漏极与所述第三P型场效应管(MP33)的漏极相连，所述第二N型场效应管(MN32)的源极与栅极接地。
PCT/CN2022/108951 2021-10-13 2022-07-29 实现控制电流变化功能的电路结构 WO2023060997A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060103428A1 (en) * 2004-11-17 2006-05-18 Nec Electronics Corporation Semiconductor integrated circuit
CN103312133A (zh) * 2012-03-07 2013-09-18 盛群半导体股份有限公司 具电压箝位功能的栅极驱动电路
CN106452404A (zh) * 2016-07-25 2017-02-22 天津理工大学 一种有源门极控制电路及其igbt电磁干扰抑制方法
CN107465334A (zh) * 2016-06-06 2017-12-12 华润矽威科技（上海）有限公司 驱动源电路及带箝位的功率开关管栅极驱动电路
JP2017224999A (ja) * 2016-06-15 2017-12-21 富士電機株式会社 半導体スイッチング素子の保護回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060103428A1 (en) * 2004-11-17 2006-05-18 Nec Electronics Corporation Semiconductor integrated circuit
CN103312133A (zh) * 2012-03-07 2013-09-18 盛群半导体股份有限公司 具电压箝位功能的栅极驱动电路
CN107465334A (zh) * 2016-06-06 2017-12-12 华润矽威科技（上海）有限公司 驱动源电路及带箝位的功率开关管栅极驱动电路
JP2017224999A (ja) * 2016-06-15 2017-12-21 富士電機株式会社 半導体スイッチング素子の保護回路
CN106452404A (zh) * 2016-07-25 2017-02-22 天津理工大学 一种有源门极控制电路及其igbt电磁干扰抑制方法

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