WO2023060741A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2023060741A1
WO2023060741A1 PCT/CN2021/137432 CN2021137432W WO2023060741A1 WO 2023060741 A1 WO2023060741 A1 WO 2023060741A1 CN 2021137432 W CN2021137432 W CN 2021137432W WO 2023060741 A1 WO2023060741 A1 WO 2023060741A1
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Prior art keywords
metal layer
conductivity type
transistor
metal
substrate
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English (en)
French (fr)
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刘志拯
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/805,850 priority Critical patent/US20230114418A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof.
  • TSV Through Silicon Via
  • the conductive vias tend to protrude out of the substrate after thermal expansion, affecting the flatness of the substrate and further affecting the performance of the semiconductor structure.
  • the embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof to solve at least one problem existing in the background art.
  • an embodiment of the present disclosure provides a semiconductor structure, including:
  • the second conductivity type transistor is disposed on the other two sides of the conductive via along a second direction; the first direction is perpendicular to the second direction;
  • the first metal layer is located on the substrate, the first metal layer includes at least one first metal line extending along a first direction, the first metal line is connected to the gate electrode of the transistor of the first conductivity type connect;
  • the second metal layer is located on the first metal layer, the second metal layer includes at least one second metal line extending along the second direction, the second metal line is connected to the gate of the second conductivity type transistor pole electrical connection;
  • first metal line and the second metal line cross each other to form a grid structure covering the conductive via hole.
  • the number of the first metal wires is multiple, and the multiple first metal wires are evenly arranged along the second direction; and/or, the number of the second metal wires is multiple, the multiple The second metal lines are uniformly arranged along the first direction.
  • the spacing between the plurality of first metal lines is between 0.5 micron and 2 microns; and/or, the spacing between the plurality of second metal lines is between 0.5 micron and 2 microns between.
  • the transistor of the first conductivity type is an n-type transistor
  • the transistor of the second conductivity type is a p-type transistor
  • the channel direction of the first conductivity type transistor is parallel to the first direction; the channel direction of the second conductivity type transistor is perpendicular to the second direction.
  • the channel direction of the first conductivity type transistor is perpendicular to the first direction; the channel direction of the second conductivity type transistor is parallel to the second direction.
  • the semiconductor structure further includes an intermediate metal layer and a conductive plug; the intermediate metal layer is located between the first metal layer and the substrate, and the conductive plug includes a At least one first sub-plug between the metal layer and the first metal layer, and at least one second sub-plug between the first metal layer and the second metal layer.
  • the first metal line is electrically connected to the gate of the transistor of the first conductivity type, including: the first metal line passes through the first sub-plug, the intermediate metal layer and the The gate of the transistor of the first conductivity type is electrically connected.
  • the first metal layer further includes a first wiring structure; the second metal line is electrically connected to the gate of the transistor of the second conductivity type, including: the second metal line passes through the The second sub-plug, the first wiring structure, the first sub-plug, and the intermediate metal layer are electrically connected to the gate of the transistor of the second conductivity type.
  • At least one of the first metal lines and at least one of the second metal lines are electrically connected through the second sub-plugs at intersections.
  • the intermediate metal layer includes a metal pad, and the metal pad is located on the upper surface of the conductive via;
  • At least one first metal line is electrically connected to the metal pad through the first sub-plug.
  • the substrate includes a corner region sandwiched between the transistor of the first conductivity type and the transistor of the second conductivity type, and the distance between the corner region and the conductive via is within 1 micrometer. to 20 microns.
  • the semiconductor structure further includes passive devices disposed within the corner regions of the substrate.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, including:
  • the substrate comprising a predetermined area for forming a conductive via
  • a transistor of a first conductivity type and a transistor of a second conductivity type are formed in the substrate; wherein the transistor of the first conductivity type is disposed on both sides of the predetermined region along a first direction, and the transistor of the second conductivity type disposed on the other two sides of the preset area along a second direction, the first direction is perpendicular to the second direction;
  • a first metal layer is formed on the substrate, the first metal layer includes at least one first metal line extending along a first direction, and the first metal line is connected to the gate electrode of the transistor of the first conductivity type. connect;
  • a second metal layer is formed on the first metal layer, the second metal layer includes at least one second metal line extending along a second direction, the second metal line is connected to the gate of the second conductivity type transistor pole electrical connection;
  • first metal line and the second metal line cross each other to form a grid structure covering the conductive via hole.
  • the semiconductor structure further includes an intermediate metal layer and a first sub-plug; before forming the first metal layer on the substrate, including:
  • the intermediate metal layer is electrically connected to the gates of the transistors of the first conductivity type and the transistors of the second conductivity type;
  • a first sub-plug is formed on the middle metal layer, and the first sub-plug is used for electrically connecting the first metal layer and the middle metal layer.
  • the semiconductor structure further includes a second sub-plug; before forming the second metal layer on the first metal layer, including:
  • the second sub-plug is formed on the first metal layer, and the second sub-plug is used to electrically connect the first metal layer and the second metal layer.
  • the semiconductor structure includes: a substrate, conductive vias located in the substrate, transistors of the first conductivity type, and transistors of the second conductivity type; wherein, the The transistors of the first conductivity type are arranged on both sides of the conductive via hole along the first direction; the transistors of the second conductivity type are arranged on the other two sides of the conductive via hole along the second direction;
  • the second direction is vertical;
  • a first metal layer is located on the substrate, the first metal layer includes at least one first metal line extending along the first direction, and the first metal line is connected to the first metal line.
  • the gate of the conductivity type transistor is electrically connected; the second metal layer is located on the first metal layer, and the second metal layer includes at least one second metal line extending along the second direction, and the second metal line is connected to the second metal line
  • the gates of the transistors of the second conductivity type are electrically connected; wherein, the first metal lines and the second metal lines cross each other to form a grid structure covering the conductive vias. In this way, the situation that the conductive via hole protrudes outward after thermal expansion can be improved; in addition, the first metal line and the second metal line are connected to the first conductivity type transistor and the second conductivity type transistor respectively.
  • the gate connection of the transistor acts as an electrical connection.
  • FIG. 1 is a schematic diagram of an exemplary semiconductor structure
  • Fig. 2a is a schematic top view of the semiconductor structure provided by the embodiment of the present disclosure
  • Fig. 2b is a schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiment of the present disclosure taken along the line AA' of Fig. 2a
  • Fig. 2c is a schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure A schematic cross-sectional structure diagram of the semiconductor structure taken along the line BB' of FIG. 2a;
  • FIG. 3 is a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 4a-4h are schematic cross-sectional structure diagrams taken along the line AA' of FIG. 2a in various steps in the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of an exemplary semiconductor structure.
  • the semiconductor structure includes a substrate 10 and an insulating layer 12 on the substrate 10; a conductive via 11 is located in the substrate 10, and The upper surface of the conductive via 11 is flush with the upper surface of the insulating layer 12; the dielectric layer 13 is located on the insulating layer 12; the metal pad 14 is located in the dielectric layer 13 and connected to the conductive
  • the through holes 11 are electrically connected.
  • the conductive vias 11 can provide vertical interconnection between the semiconductor structure and the other structures.
  • the semiconductor structure when the semiconductor structure is bonded with other structures, the semiconductor structure will be heated. During this process, the conductive via 11 protrudes out of the substrate 10 after being heated and expands, lowering the substrate. The flatness of the bottom 10 affects the performance of the semiconductor structure.
  • An embodiment of the present disclosure provides a semiconductor structure, including: a substrate, a conductive via located in the substrate, a transistor of a first conductivity type, and a transistor of a second conductivity type; wherein, the transistor of the first conductivity type along the second One direction is disposed on both sides of the conductive via; the second conductivity type transistor is disposed on the other two sides of the conductive via along a second direction; the first direction is perpendicular to the second direction; A metal layer located on the substrate, the first metal layer includes at least one first metal line extending along a first direction, the first metal line is electrically connected to the gate of the first conductivity type transistor a second metal layer, located on the first metal layer, the second metal layer includes at least one second metal line extending along the second direction, the second metal line and the transistor of the second conductivity type The gate is electrically connected; wherein, the first metal line and the second metal line cross each other to form a grid structure covering the conductive via hole.
  • the semiconductor structure provided by the embodiments of the present disclosure by forming the grid structure on the conductive via hole, the situation that the conductive via hole protrudes outward after thermal expansion can be improved; in addition, the first metal line and The second metal wires are respectively connected to the gates of the transistors of the first conductivity type and the transistors of the second conductivity type, which serve as electrical connections.
  • the semiconductor structure provided by the embodiments of the present disclosure may be a dynamic random access memory (DRAM). But not limited thereto, the semiconductor structure may also be any semiconductor structure with conductive vias.
  • DRAM dynamic random access memory
  • Fig. 2a is a schematic top view of the semiconductor structure provided by the embodiment of the present disclosure
  • Fig. 2b is a schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiment of the present disclosure taken along the line AA' of Fig. 2a
  • Fig. 2c is a schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure
  • the semiconductor structure includes: a substrate 20 and a conductive via 21 located in the substrate 20, a first conductivity type transistor 23 and a second conductivity type transistor 24; wherein the first conductivity type The transistor 23 is arranged on both sides of the conductive via 21 along the first direction; the second conductivity type transistor 24 is arranged on the other two sides of the conductive via 21 along the second direction; The second direction is vertical; the first metal layer M1 is located on the substrate 20, the first metal layer M1 includes at least one first metal line 30 extending along the first direction, and the first metal line 30 and The gate 233 of the first conductivity type transistor 23 is electrically connected; the second metal layer M2 is located on the first metal layer M1, and the second metal layer M2 includes at least one second metal layer extending along the second direction. line 31, the second metal line 31 is electrically connected to the gate 241 of the second conductivity type transistor 24; wherein, the first metal line 30 and the second metal line 31 intersect each other to form covering the conductive A grid structure 32 of through holes 21 .
  • the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI A compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
  • the substrate is a silicon (Si) substrate.
  • the thickness of the substrate may be between 40-70 ⁇ m, for example, between 50-60 ⁇ m.
  • the conductive via 21 includes a through hole (not marked) penetrating the substrate 20 and a conductive material located in the through hole (not marked), and the conductive via 21 is used in the Signals are conducted in the semiconductor structure.
  • the through hole (not marked) is formed by etching downward from the upper surface of the substrate 20 .
  • the through hole (not marked) can also be formed by etching from the back surface of the substrate 20 to the upper surface of the substrate 20 .
  • the characteristic size of the conductive via 21 is between 2-10 ⁇ m, and the depth is between 5-100 ⁇ m.
  • the conductive via hole will undergo a cooling process from high temperature to low temperature.
  • the conductive via hole and the substrate shrink to different extents, and a The stress will affect the mobility of carriers in the substrate near the conductive via. Therefore, when designing a semiconductor structure, technicians generally set forbidden areas around the conductive vias, and no active devices such as transistors are arranged in the forbidden areas. Taking the center of the conductive via hole as the center, the radius of the forbidden zone is usually between 5-15 ⁇ m. Understandably, the presence of exclusion zones reduces substrate utilization.
  • an n-type transistor is disposed on both sides of the conductive via along a first direction, and the channel direction of the n-type transistor is parallel to the first direction;
  • a p-type transistor is disposed on the other two sides of the conductive via hole along a second direction, and the channel direction of the p-type transistor is perpendicular to the second direction.
  • the mobility of the n-type transistor and the p-type transistor can be improved at the same time, thereby increasing the turn-on speed of the n-type transistor and the p-type transistor.
  • the n-type transistor and the p-type transistor are connected to each other through the first metal layer and the second metal layer to form an inverter, and the input end of the inverter is electrically connected to the conductive via hole. connection, that is, the signal is conducted to the input terminal of the inverter through the conductive via. Since the mobility of the n-type transistor and the p-type transistor constituting the inverter is relatively high, the inverter has a faster turn-on speed, which accelerates the signal transmission speed.
  • an n-type transistor is disposed on both sides of the conductive via along a first direction, and the channel direction of the n-type transistor is perpendicular to the first direction; the p The p-type transistor is disposed on the other two sides of the conductive via along the second direction, and the channel direction of the p-type transistor is parallel to the second direction.
  • the n-type transistor and the p-type transistor are connected to each other through the first metal layer and the second metal layer to form an inverter, and the input end of the inverter is electrically connected to the conductive via hole. connection, that is, the signal is conducted to the input terminal of the inverter through the conductive via. Since the mobility of the n-type transistor and the p-type transistor constituting the inverter is low, the inverter has a small leakage current, which reduces the power consumption of the semiconductor structure.
  • the selection of the first direction is related to the crystal orientation of the substrate surface.
  • the first direction may be parallel to the crystal direction of the substrate surface.
  • the first conductivity type transistor 23 includes a gate 233, a gate dielectric layer 234, a first source/drain doped region 231 and a second source/drain doped region 232;
  • Type transistor 24 includes a gate 241 , a gate dielectric layer 242 , a first source/drain doped region (not shown) and a second source/drain doped region (not shown).
  • the semiconductor structure further includes an insulating layer 25 on the substrate 20 and an isolation structure 22 in the substrate 20 .
  • the insulating layer is located between the gates of the first conductivity type transistor and the second conductivity type transistor, and the upper surface of the insulating layer is flush with the upper surface of the gate for electrical isolating the gates of the transistors of the first conductivity type and the transistors of the second conductivity type, and the insulating layer is also used to protect the substrate from being oxidized, nitrided, damaged or polluted;
  • the isolation structure is used for electrically isolating device structures located in the substrate and adjacent to each other, the isolation structure may be, for example, a shallow trench isolation structure, and the device structure may be a transistor formed in the substrate, for example, in an embodiment of the present disclosure transistors of the first conductivity type and transistors of the second conductivity type.
  • the substrate 20 includes a corner region 33 interposed between the transistor of the first conductivity type 23 and the transistor of the second conductivity type 24, the corner region 33 and the conductive via
  • the distance of 21 is between 1 micron and 20 microns.
  • the semiconductor structure further includes passive devices (not shown), and the passive devices (not shown) are disposed in the corner region 33 of the substrate 20 .
  • the passive components include but not limited to resistors and capacitors. Arranging passive devices (not shown) that are not sensitive to stress in the corner area 33 can improve the utilization rate of the forbidden area.
  • the number of the first metal wires 30 is multiple, and the multiple first metal wires 30 are uniformly arranged along the second direction; and/or, the number of the second metal wires 31 is multiple, the multiple of the The second metal lines 31 are uniformly arranged along the first direction.
  • the spacing between the plurality of first metal lines 30 is between 0.5 micron and 2 microns; and/or, the spacing between the plurality of second metal lines 31 is between 0.5 micron and 2 microns. between 2 microns.
  • the semiconductor structure further includes an intermediate metal layer M0 and conductive plugs V1, V2; the intermediate metal layer M0 is located between the first metal layer M1 and the substrate 20, the conductive The plugs V1 and V2 include at least one first sub-plug V1 located between the middle metal layer M0 and the first metal layer M1, and at least one sub-plug V1 located between the first metal layer M1 and the second metal layer M2. at least one second sub-plug V2 between them.
  • the intermediate metal layer M0 includes a metal pad 28, the metal pad 28 is located on the upper surface of the conductive via 21, and at least one of the first metal lines 30 passes through the first The sub-plug V1 is electrically connected to the metal pad 28 , so that the signal can be transmitted to the first metal line 30 through the conductive via 21 .
  • the first metal line 30 is electrically connected to the gate 233 of the first conductivity type transistor 23, including: the first metal line 30 passes through the first sub-plug V1 , the intermediate metal layer M0 is electrically connected to the gate 233 of the transistor of the first conductivity type 23 , so that a signal can be conducted to the gate 233 of the transistor of the first conductivity type 23 through the conductive via 21 .
  • the first metal layer M1 further includes a first wiring structure 29; the second metal line 31 is electrically connected to the gate 241 of the second conductivity type transistor 24, including: the second metal line 31 passes through The second sub-plug V2, the first wiring structure 29, the first sub-plug V1, and the intermediate metal layer M0 are electrically connected to the gate 241 of the second conductivity type transistor 24, as shown in FIG. 2c shown.
  • At least one of the first metal wires 30 and at least one of the second metal wires 31 may be electrically connected through the second sub-plug V2 at the intersection, so that the signal is conducted to the The gate 241 of the second conductivity type transistor 24 is described above.
  • the semiconductor structure further includes a ring-shaped shielding layer 27, and the ring-shaped shielding layer 27 is disposed around the conductive via 21, as shown in FIG. 2a.
  • the function of the ring-shaped shielding layer 27 is to reduce the crosstalk effect generated by the conductive via 21 and its nearby metal conductive structures when transmitting signals.
  • the number of layers of the annular shielding layer 27 is a single layer, as shown in Figure 2b and Figure 2c; optionally, the annular shielding layer 27 and the intermediate metal layer M0 formed simultaneously in the same process step. But not limited thereto, the number of layers of the annular shielding layer 27 may be multiple layers.
  • the semiconductor structure further includes a dielectric layer 26, and the dielectric layer 26 covers the middle metal layer M0, the first metal layer M1, the second metal layer M2, the annular The shielding layer 27 and the first sub-plug V1 and the second sub-plug V2.
  • the dielectric layer 26 is not a single-layer structure, but is formed by multiple layers of insulating materials in multiple process steps.
  • the first metal wire and the second metal wire cross each other to form a grid structure on the conductive via, which can improve the outward protrusion of the conductive via after thermal expansion.
  • the transistors of the first conductivity type and the transistors of the second conductivity type are rationally arranged around the forbidden zone of the conductive via, and the transistors of the first conductivity type and the transistors of the second conductivity type are connected via the second conductivity type.
  • a metal wire and the second metal wire are electrically connected to form a device, such as an inverter, which can increase substrate utilization and improve certain performances of the device, such as conduction speed, power consumption, and the like.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, as shown in FIG. 3 , the method includes the following steps:
  • Step 301 providing a substrate, the substrate includes a predetermined area, and the predetermined area is used to form conductive vias;
  • Step 302 forming a transistor of a first conductivity type and a transistor of a second conductivity type in the substrate; wherein, the transistor of the first conductivity type is arranged on both sides of the predetermined region along a first direction, and the transistor of the second conductivity type Conductive type transistors are arranged on the other two sides of the preset region along a second direction, the first direction is perpendicular to the second direction;
  • Step 303 forming a conductive via hole in the predetermined area of the substrate
  • Step 304 forming a first metal layer on the substrate, the first metal layer including at least one first metal line extending along a first direction, the first metal line and the transistor of the first conductivity type Grid electrical connection;
  • Step 305 forming a second metal layer on the first metal layer, the second metal layer includes at least one second metal line extending along a second direction, the second metal line is compatible with the second conductivity type
  • the gates of the transistors are electrically connected; wherein, the first metal line and the second metal line cross each other to form a grid structure covering the conductive via.
  • step 301 is performed to provide a substrate 20, the substrate 20 includes a predetermined region 21a for forming a conductive via 21 (see FIG. 4d ), as shown in FIG. 4a.
  • the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI A compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
  • the substrate is a silicon (Si) substrate.
  • the thickness of the substrate may be between 40-70 ⁇ m, for example, between 50-60 ⁇ m.
  • the predetermined area 21a is a cylindrical area, and the diameter of the cylindrical area is between 2-10 ⁇ m.
  • step 302 is performed to form a transistor of the first conductivity type 23 and a transistor of the second conductivity type 24 in the substrate 20; wherein, the transistor of the first conductivity type 23 is arranged in the preset region along the first direction 21a, the second conductivity type transistor 24 is disposed on the other two sides of the preset region 21a along a second direction, and the first direction is perpendicular to the second direction, as shown in FIG. 4b.
  • the transistor of the first conductivity type 23 may be, for example, an n-type transistor, and the transistor of the second conductivity type 24 may be, for example, a p-type transistor.
  • a conductive via hole will be formed in the preset area.
  • the conductive via hole will undergo a cooling process from high temperature to low temperature.
  • the conductive via hole and the substrate shrink to different extents, and a The stress will affect the mobility of carriers in the substrate near the conductive via. Therefore, when designing a semiconductor structure, technicians generally set forbidden areas around the conductive vias, and no active devices such as transistors are arranged in the forbidden areas. Taking the center of the conductive via hole as the center, the radius of the forbidden zone is usually between 5-15 ⁇ m. Understandably, the presence of exclusion zones reduces substrate utilization.
  • an n-type transistor is disposed on both sides of the conductive via along a first direction, and the channel direction of the n-type transistor is parallel to the first direction;
  • a p-type transistor is disposed on the other two sides of the conductive via hole along a second direction, and the channel direction of the p-type transistor is perpendicular to the second direction.
  • an n-type transistor is disposed on both sides of the conductive via along a first direction, and the channel direction of the n-type transistor is perpendicular to the first direction; the p The p-type transistor is disposed on the other two sides of the conductive via along the second direction, and the channel direction of the p-type transistor is parallel to the second direction.
  • the selection of the first direction is related to the crystal orientation of the substrate surface.
  • the first direction may be parallel to the crystal direction of the substrate surface.
  • the first conductivity type transistor 23 includes a gate 233, a gate dielectric layer 234, a first source/drain doped region 231 and a second source/drain doped region 232, as shown in FIG. 4b;
  • the first The two-conductivity type transistor 24 includes a gate 241 , a gate dielectric layer 242 , a first source/drain doped region (not shown) and a second source/drain doped region (not shown), as shown in FIG. 2 c .
  • the method further includes: forming an isolation structure 22 in the substrate 20 .
  • the isolation structure 22 is formed before the transistors of the first conductivity type 23 and the transistors of the second conductivity type 24 are formed.
  • the isolation structure 22 is used to electrically isolate device structures located in the substrate 20 and adjacent to each other.
  • the isolation structure 22 can be, for example, a shallow trench isolation structure, and the device structure can be formed in the substrate 20. transistors, such as the first conductivity type transistor 23 and the second conductivity type transistor 24 in the embodiment of the present disclosure.
  • the substrate 20 after forming the first conductivity type transistor 23 and the second conductivity type transistor 24 in the substrate 20, it further includes: forming an insulating layer 25 on the substrate 20.
  • the insulating layer is formed between the gates of the transistor of the first conductivity type and the transistor of the second conductivity type, and the upper surface of the insulating layer is flush with the upper surface of the gate, for
  • the gates of the transistors of the first conductivity type and the transistors of the second conductivity type are electrically isolated, and the insulating layer is also used to protect the substrate from being oxidized, nitrided, damaged or polluted.
  • the substrate 20 further includes a corner region 33 interposed between the transistor of the first conductivity type 23 and the transistor of the second conductivity type 24, the corner region 33 communicates with the conductive
  • the distance of the holes 21 is between 1 micron and 20 microns, as shown in FIG. 2 .
  • the semiconductor structure further includes a passive device (not shown), and the passive device (not shown) is disposed in the corner region 33 of the substrate 20 , and the passive device (not shown) Components (not shown) include, but are not limited to, resistors, capacitors. Arranging passive devices (not shown) that are not sensitive to stress in the corner area 33 can improve the utilization rate of the forbidden zone.
  • step 303 is performed to form conductive vias 21 in the predetermined region 21 a of the substrate 20 , as shown in FIG. 4 d .
  • the forming method of the conductive via 21 includes: forming a via hole in the substrate 20, the via hole passing through the substrate 20 and the insulating layer 25; forming a conductive via in the via hole. materials to form the conductive vias 21 for conducting signals in the semiconductor structure.
  • the conductive material may be copper.
  • the characteristic size of the conductive via 21 is between 2-10 ⁇ m, and the depth is between 5-100 ⁇ m.
  • the conductive via hole further includes an insulating film formed on an inner wall of the via hole, and a barrier layer formed between the insulating film and the conductive material.
  • the material of the insulating film can be an oxide, such as silicon oxide, and the thickness of the insulating film is between between.
  • the barrier layer can be metal, such as tantalum, and the thickness of the barrier layer is between between.
  • step 304 is performed to form a first metal layer M1 on the substrate 20, the first metal layer M1 includes at least one first metal line 30 extending along a first direction, and the first metal line 30 It is electrically connected to the gate 233 of the transistor 23 of the first conductivity type, as shown in FIG. 4g.
  • forming a first metal layer M1 on the substrate 20 includes:
  • a dielectric layer 26 is formed on the substrate, the dielectric layer 26 is patterned, and a first metal layer M1 is formed in the patterned dielectric layer.
  • the number of the first metal wires 30 is multiple, and the multiple first metal wires 30 are uniformly arranged along the second direction.
  • the distance between the plurality of first metal lines 30 is between 0.5 microns and 2 microns.
  • the semiconductor structure further includes an intermediate metal layer M0 and a first sub-plug V1; before forming the first metal layer M1 on the substrate 20, it includes:
  • An intermediate metal layer M0 is formed on the substrate 20, and the intermediate metal layer M0 is electrically connected to the gates 233, 241 of the first conductivity type transistor 23 and the second conductivity type transistor 24, as shown in FIG. 4e Show;
  • a first sub-plug V1 is formed on the middle metal layer M0, and the first sub-plug V1 is used to electrically connect the first metal layer M1 and the middle metal layer M0, as shown in FIG. 4f.
  • forming the intermediate metal layer M0 and the first sub-plug V1 includes:
  • a dielectric layer covering the intermediate metal layer M0 is formed, a through hole is formed in the dielectric layer, and the first sub-plug V1 is formed in the through hole.
  • the middle metal layer M0 includes a metal pad 28, the metal pad 28 is located on the upper surface of the conductive via 21, and at least one of the first metal lines 30 passes through the first sub-hole.
  • the plug V1 is electrically connected to the metal pad 28 , so that the signal can be transmitted to the first metal line 30 through the conductive via 21 .
  • the first metal line 30 is electrically connected to the gate 233 of the first conductivity type transistor 23, including: the first metal line 30 passes through the first sub-plug V1,
  • the middle metal layer M0 is electrically connected to the gate 233 of the transistor of the first conductivity type 23 , so that a signal can be transmitted to the gate 233 of the transistor of the first conductivity type 23 through the conductive via 21 .
  • the first metal layer M1 further includes a first wiring structure 29, and the first wiring structure 29 is electrically connected to the middle metal layer M0 through the first sub-plug V1, as shown in FIG. 2c shown.
  • the method further includes: forming a ring-shaped shielding layer 27 on the substrate 20 , and the ring-shaped shielding layer 27 is disposed around the conductive via 21 .
  • the function of the ring-shaped shielding layer 27 is to reduce the crosstalk effect generated by the conductive via 21 and its nearby metal conductive structures when transmitting signals.
  • the number of layers of the ring-shaped shielding layer 27 is a single layer, and the ring-shaped shielding layer 27 and the middle metal layer M0 are simultaneously formed in the same process step. But not limited thereto, the number of layers of the annular shielding layer 27 may be multiple layers.
  • step 305 is executed to form a second metal layer M2 on the first metal layer M1, the second metal layer M2 includes at least one second metal line 31 extending along the second direction, and the second metal line 31 is electrically connected to the gate 241 of the second conductivity type transistor 24; wherein, the first metal line 30 and the second metal line 31 cross each other to form a grid structure 32 covering the conductive via 21, As shown in Figure 2a-2c.
  • forming a second metal layer M2 on the first metal layer M1 includes:
  • a dielectric layer covering the first metal layer is formed, the dielectric layer is patterned, and a second metal layer M2 is formed in the patterned dielectric layer.
  • the number of the second metal wires 31 is multiple, and the multiple second metal wires 31 are uniformly arranged along the first direction.
  • the distance between the plurality of second metal lines 31 is between 0.5 ⁇ m and 2 ⁇ m.
  • the semiconductor structure further includes a second sub-plug V2; before forming the second metal layer M2 on the first metal layer M1, it includes: forming the second metal layer M1 on the first metal layer M1.
  • a second sub-plug V2, the second sub-plug V2 is used to electrically connect the first metal layer M1 and the second metal layer M2, as shown in FIG. 4h.
  • forming the second sub-plug V2 on the first metal layer M1 includes:
  • a dielectric layer is formed on the first metal layer M1, a through hole is formed in the dielectric layer, and the second sub-plug V2 is formed in the through hole.
  • the second metal line 31 is electrically connected to the gate 241 of the second conductivity type transistor 24, including: the second metal line 31 passes through the second sub-plug V2, the The first wiring structure 29 , the first sub-plug V1 , the intermediate metal layer M0 are electrically connected to the gate 241 of the second conductivity type transistor 24 .
  • At least one of the first metal wires 30 and at least one of the second metal wires 31 are electrically connected through the second sub-plug V2 at the intersection, so that the signal is passed through the conductive
  • the hole 21 conducts to the gate 241 of the second conductivity type transistor 24 .
  • the semiconductor structure includes: a substrate, conductive vias located in the substrate, transistors of the first conductivity type, and transistors of the second conductivity type; wherein, the The transistors of the first conductivity type are arranged on both sides of the conductive via hole along the first direction; the transistors of the second conductivity type are arranged on the other two sides of the conductive via hole along the second direction;
  • the second direction is vertical;
  • a first metal layer is located on the substrate, the first metal layer includes at least one first metal line extending along the first direction, and the first metal line is connected to the first metal line.
  • the gate of the conductivity type transistor is electrically connected; the second metal layer is located on the first metal layer, and the second metal layer includes at least one second metal line extending along the second direction, and the second metal line is connected to the second metal line
  • the gates of the transistors of the second conductivity type are electrically connected; wherein, the first metal lines and the second metal lines cross each other to form a grid structure covering the conductive vias. In this way, the situation that the conductive via hole protrudes outward after thermal expansion can be improved; in addition, the first metal line and the second metal line are connected to the first conductivity type transistor and the second conductivity type transistor respectively.
  • the gate connection of the transistor acts as an electrical connection.

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Abstract

本公开实施例公开了一种半导体结构及其制造方法，所述半导体结构包括：衬底以及位于衬底内的导电通孔、第一导电类型晶体管及第二导电类型晶体管；其中，第一导电类型晶体管沿第一方向设置于导电通孔的两侧；第二导电类型晶体管沿第二方向设置于导电通孔的另外两侧；第一方向与第二方向垂直；第一金属层，位于衬底上，第一金属层包括至少一条沿第一方向延伸的第一金属线，第一金属线与第一导电类型晶体管的栅极电连接；第二金属层，位于第一金属层上，第二金属层包括至少一条沿第二方向延伸的第二金属线，第二金属线与第二导电类型晶体管的栅极电连接；其中，第一金属线和第二金属线相互交叉构成覆盖导电通孔的网格结构。

Description

一种半导体结构及其制造方法
相关申请的交叉引用
本公开基于申请号为202111190824.6、申请日为2021年10月13日、发明名称为“一种半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及一种半导体结构及其制造方法。
背景技术
基于导电通孔(Through Silicon Via，TSV)互连技术的垂直互连叠层封装方式，以其短距离互连和高密度集成的优势，逐渐引领了封装技术发展的趋势。
然而，导电通孔在受热膨胀后容易向衬底外突出，影响衬底的平整度，进而影响半导体结构的性能。
发明内容
有鉴于此，本公开实施例为解决背景技术中存在的至少一个问题而提供一种半导体结构及其制造方法。
本公开的技术方案是这样实现的：本公开实施例提供了一种半导体结构，包括：
衬底以及位于所述衬底内的导电通孔、第一导电类型晶体管及第二导电类型晶体管；其中，所述第一导电类型晶体管沿第一方向设置于所述导电通孔的两侧；所述第二导电类型晶体管沿第二方向设置于所述导电通孔 的另外两侧；所述第一方向与所述第二方向垂直；
第一金属层，位于所述衬底上，所述第一金属层包括至少一条沿第一方向延伸的第一金属线，所述第一金属线与所述第一导电类型晶体管的栅极电连接；
第二金属层，位于所述第一金属层上，所述第二金属层包括至少一条沿第二方向延伸的第二金属线，所述第二金属线与所述第二导电类型晶体管的栅极电连接；
其中，所述第一金属线和所述第二金属线相互交叉构成覆盖所述导电通孔的网格结构。
在一些实施例中，所述第一金属线的数量为多条，多条所述第一金属线沿第二方向均匀排列；和/或，所述第二金属线的数量为多条，多条所述第二金属线沿第一方向均匀排列。
在一些实施例中，多条所述第一金属线之间的间距在0.5微米至2微米之间；和/或，多条所述第二金属线之间的间距在0.5微米至2微米之间。
在一些实施例中，所述第一导电类型晶体管为n型晶体管，所述第二导电类型晶体管为p型晶体管。
在一些实施例中，所述第一导电类型晶体管的沟道方向与所述第一方向平行；所述第二导电类型晶体管的沟道方向与所述第二方向垂直。
在一些实施例中，所述第一导电类型晶体管的沟道方向与所述第一方向垂直；所述第二导电类型晶体管的沟道方向与所述第二方向平行。
在一些实施例中，所述半导体结构还包括中间金属层和导电插塞；所述中间金属层位于所述第一金属层和所述衬底之间，所述导电插塞包括位于所述中间金属层和所述第一金属层之间的至少一个第一子插塞、以及位于所述第一金属层与所述第二金属层之间的至少一个第二子插塞。
在一些实施例中，所述第一金属线与所述第一导电类型晶体管的栅极电连接，包括：所述第一金属线通过所述第一子插塞、所述中间金属层与 所述第一导电类型晶体管的栅极电连接。
在一些实施例中，所述第一金属层还包括第一布线结构；所述第二金属线与所述第二导电类型晶体管的栅极电连接，包括：所述第二金属线通过所述第二子插塞、所述第一布线结构、所述第一子插塞、所述中间金属层与所述第二导电类型晶体管的栅极电连接。
在一些实施例中，至少一条所述第一金属线和至少一条所述第二金属线在交叉处通过所述第二子插塞电连接。
在一些实施例中，所述中间金属层包括金属焊盘，所述金属焊盘位于所述导电通孔的上表面；
至少一条所述第一金属线通过所述第一子插塞与所述金属焊盘电连接。
在一些实施例中，所述衬底包括夹设于所述第一导电类型晶体管和所述第二导电类型晶体管之间的角区域，所述角区域与所述导电通孔的距离在1微米至20微米之间。
在一些实施例中，所述半导体结构还包括无源器件，所述无源器件设置于所述衬底的所述角区域内。
本公开实施例还提供了一种半导体结构的制造方法，包括：
提供衬底，所述衬底包括预设区域，所述预设区域用于形成导电通孔；
在所述衬底内形成第一导电类型晶体管及第二导电类型晶体管；其中，所述第一导电类型晶体管沿第一方向设置于所述预设区域的两侧，所述第二导电类型晶体管沿第二方向设置于所述预设区域的另外两侧，所述第一方向与所述第二方向垂直；
在所述衬底的所述预设区域形成导电通孔；
在所述衬底上形成第一金属层，所述第一金属层包括至少一条沿第一方向延伸的第一金属线，所述第一金属线与所述第一导电类型晶体管的栅极电连接；
在所述第一金属层上形成第二金属层，所述第二金属层包括至少一条 沿第二方向延伸的第二金属线，所述第二金属线与所述第二导电类型晶体管的栅极电连接；
其中，所述第一金属线和所述第二金属线相互交叉构成覆盖所述导电通孔的网格结构。
在一些实施例中，所述半导体结构还包括中间金属层和第一子插塞；在所述衬底上形成第一金属层之前，包括：
在所述衬底上形成中间金属层，所述中间金属层与所述第一导电类型晶体管和所述第二导电类型晶体管的栅极电连接；
在所述中间金属层上形成第一子插塞，所述第一子插塞用于电连接所述第一金属层与所述中间金属层。
在一些实施例中，所述半导体结构还包括第二子插塞；在所述第一金属层上形成第二金属层之前，包括：
在所述第一金属层上形成所述第二子插塞，所述第二子插塞用于电连接所述第一金属层和所述第二金属层。
本公开实施例提供的半导体结构及其制造方法，其中，所述半导体结构包括：衬底以及位于所述衬底内的导电通孔、第一导电类型晶体管及第二导电类型晶体管；其中，所述第一导电类型晶体管沿第一方向设置于所述导电通孔的两侧；所述第二导电类型晶体管沿第二方向设置于所述导电通孔的另外两侧；所述第一方向与所述第二方向垂直；第一金属层，位于所述衬底上，所述第一金属层包括至少一条沿第一方向延伸的第一金属线，所述第一金属线与所述第一导电类型晶体管的栅极电连接；第二金属层，位于所述第一金属层上，所述第二金属层包括至少一条沿第二方向延伸的第二金属线，所述第二金属线与所述第二导电类型晶体管的栅极电连接；其中，所述第一金属线和所述第二金属线相互交叉构成覆盖所述导电通孔的网格结构。如此，可以改善所述导电通孔受热膨胀后向外凸出的情况；此外，所述第一金属线和所述第二金属线分别与所述第一导电类型晶体管 和所述第二导电类型晶体管的栅极连接，起到了电连接的作用。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征和优点将从说明书附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为示例性半导体结构的示意图；
图2a为本公开实施例提供的半导体结构的俯视示意图，图2b为本公开实施例提供的半导体结构沿图2a的线A-A'截取的剖面结构示意图，图2c为本公开实施例提供的半导体结构沿图2a的线B-B'截取的剖面结构示意图；
图3为本公开实施例提供的半导体结构的制造方法的流程框图；
图4a-4h为本公开实施例提供的半导体结构的制造方法中各步骤沿图2a的线A-A'截取的剖面结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需 一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
图1为示例性半导体结构的示意图，如图所示，所述半导体结构包括衬底10以及位于所述衬底10上的绝缘层12；导电通孔11，位于所述衬底10内，所述导电通孔11的上表面与所述绝缘层12的上表面齐平；介质层13，位于所述绝缘层12上；金属焊盘14，位于所述介质层13内，并与所述导电通孔11电连接。所述半导体结构在与其他结构键合时，所述导电通孔11可以在所述半导体结构和所述其他结构之间提供垂直互连。
然而，在所述半导体结构与其他结构键合时，会对所述半导体结构进行加热，在此过程中，所述导电通孔11受热膨胀后向所述衬底10外突出，降低所述衬底10的平整度，影响所述半导体结构的性能。
基于此，提出了本公开实施例的以下技术方案：
本公开实施例提供了一种半导体结构，包括：衬底以及位于所述衬底内的导电通孔、第一导电类型晶体管及第二导电类型晶体管；其中，所述第一导电类型晶体管沿第一方向设置于所述导电通孔的两侧；所述第二导电类型晶体管沿第二方向设置于所述导电通孔的另外两侧；所述第一方向与所述第二方向垂直；第一金属层，位于所述衬底上，所述第一金属层包括至少一条沿第一方向延伸的第一金属线，所述第一金属线与所述第一导电类型晶体管的栅极电连接；第二金属层，位于所述第一金属层上，所述第二金属层包括至少一条沿第二方向延伸的第二金属线，所述第二金属线与所述第二导电类型晶体管的栅极电连接；其中，所述第一金属线和所述 第二金属线相互交叉构成覆盖所述导电通孔的网格结构。
本公开实施例提供的半导体结构，通过在所述导电通孔上形成所述网格结构，可以改善所述导电通孔受热膨胀后向外凸出的情况；此外，所述第一金属线和所述第二金属线分别与所述第一导电类型晶体管和所述第二导电类型晶体管的栅极连接，起到了电连接的作用。
本公开实施例提供的半导体结构，可以是动态随机存储器(DRAM)。但不限于此，所述半导体结构还可以是任何具有导电通孔的半导体结构。
下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例做局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图2a为本公开实施例提供的半导体结构的俯视示意图，图2b为本公开实施例提供的半导体结构沿图2a的线A-A'截取的剖面结构示意图，图2c为本公开实施例提供的半导体结构沿图2a的线B-B'截取的剖面结构示意图。以下结合图2a-2c对本公开实施例提供的半导体结构的制造方法再作进一步详细的说明。
如图所示，所述半导体结构包括：衬底20以及位于所述衬底20内的导电通孔21、第一导电类型晶体管23及第二导电类型晶体管24；其中，所述第一导电类型晶体管23沿第一方向设置于所述导电通孔21的两侧；所述第二导电类型晶体管24沿第二方向设置于所述导电通孔21的另外两侧；所述第一方向与所述第二方向垂直；第一金属层M1，位于所述衬底20上，所述第一金属层M1包括至少一条沿第一方向延伸的第一金属线30，所述第一金属线30与所述第一导电类型晶体管23的栅极233电连接；第二金属层M2，位于所述第一金属层M1上，所述第二金属层M2包括至少一条沿第二方向延伸的第二金属线31，所述第二金属线31与所述第二导电类型晶体管24的栅极241电连接；其中，所述第一金属线30和所述第二金属线31相互交叉构成覆盖所述导电通孔21的网格结构32。
所述衬底可以为半导体衬底，并且可以包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底)、至少一个III-V化合物半导体材料、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料。在一具体实施例中，所述衬底为硅(Si)衬底。
在实际的工艺中，所述衬底的厚度可选在40-70μm之间，例如，50-60μm之间。
在实际工艺中，所述导电通孔21包括贯穿所述衬底20的通孔(未标识)以及位于所述通孔(未标识)内的导电材料，所述导电通孔21用于在所述半导体结构中传导信号。在一实施例中，所述通孔(未标识)是从所述衬底20的上表面向下刻蚀形成的。但不限于此，所述通孔(未标识)也可以从所述衬底20的背面向所述衬底20的上表面刻蚀形成。在一些实施例中，所述导电通孔21的特征尺寸在2-10μm之间，深度在5-100μm之间。
所述导电通孔在制备的过程中，会经历高温至低温的冷却过程，在所述冷却过程中，所述导电通孔及所述衬底收缩的程度不同，会在所述衬底中产生应力，该应力会影响所述导电通孔附近的衬底内的载流子的迁移速度。因此，技术人员在设计半导体结构时，通常会在所述导电通孔周围设置禁区，所述禁区内不设置诸如晶体管之类的有源器件。以所述导电通孔的中心为圆心，所述禁区的半径通常在5-15μm之间。可以理解的是，禁区的存在降低了衬底的利用率。
本申请人经研究发现，在所述禁区内合理的布置不同导电类型的晶体管，不仅可以提高禁区的利用率，还可以提高半导体结构的某些性能。例如，在本公开的一个实施例中，将n型晶体管沿第一方向设置在所述导电通孔的两侧，且使所述n型晶体管的沟道方向与所述第一方向平行；将p型晶体管沿第二方向设置在所述导电通孔的另外两侧，且使所述p型晶体管的沟道方向与所述第二方向垂直。如此，可以同时提高所述n型晶体管 和所述p型晶体管的迁移率，进而提高所述n型晶体管和所述p型晶体管的导通速度。可选的，所述n型晶体管和所述p型晶体管通过所述第一金属层和所述第二金属层相互连接构成反相器，该反相器的输入端与所述导电通孔电连接，即信号经所述导电通孔传导至所述反相器的输入端。由于构成该反相器的n型晶体管和p型晶体管的迁移率较高，使得该反相器具有较快的导通速度，加快了信号的传输速度。
在本公开的另一个实施例中，将n型晶体管沿第一方向设置在所述导电通孔的两侧，且使所述n型晶体管的沟道方向与所述第一方向垂直；将p型晶体管沿第二方向设置在所述导电通孔的另外两侧，且使所述p型晶体管的沟道方向与所述第二方向平行。如此，可以同时降低所述n型晶体管和所述p型晶体管的迁移率，降低流经所述n型晶体管和所述p型晶体管的漏电流，降低半导体结构的功耗。可选的，所述n型晶体管和所述p型晶体管通过所述第一金属层和所述第二金属层相互连接构成反相器，该反相器的输入端与所述导电通孔电连接，即信号经所述导电通孔传导至所述反相器的输入端。由于构成该反相器的n型晶体管和p型晶体管的迁移率较低，使得该反相器具有较小的漏电流，降低了所述半导体结构的功耗。
需要说明的是，所述第一方向的选取与衬底表面的晶向有关。在本公开的一个实施例中，所述第一方向可以与所述衬底表面的晶向平行。
参见图2b及图2c，所述第一导电类型晶体管23包括栅极233、栅介质层234、第一源/漏掺杂区231和第二源/漏掺杂区232；所述第二导电类型晶体管24包括栅极241、栅介质层242、第一源/漏掺杂区(未图示)和第二源/漏掺杂区(未图示)。
在一实施例中，所述半导体结构还包括位于所述衬底20上的绝缘层25以及位于所述衬底20内的隔离结构22。
具体地，所述绝缘层位于所述第一导电类型晶体管和所述第二导电类型晶体管的栅极之间，所述绝缘层的上表面与所述栅极的上表面齐平，用 于电隔离所述第一导电类型晶体管和所述第二导电类型晶体管的栅极，所述绝缘层还用于保护所述衬底不被氧化、氮化、损伤或者污染等；所述隔离结构用于电隔离位于衬底内且彼此相邻的器件结构，所述隔离结构例如可以为浅沟槽隔离结构，所述器件结构可以为形成在所述衬底内的晶体管，如，本公开实施例中的第一导电类型晶体管和第二导电类型晶体管。
如图2a所示，所述衬底20包括夹设于所述第一导电类型晶体管23和所述第二导电类型晶体管24之间的角区域33，所述角区域33与所述导电通孔21的距离在1微米至20微米之间。在一实例中，所述半导体结构还包括无源器件(未图示)，所述无源器件(未图示)设置于所述衬底20的所述角区域33内。所述无源器件(未图示)包括但不限于电阻器、电容器。在所述角区域33内设置对应力不敏感的无源器件(未图示)，能够提高禁区的利用率。
所述第一金属线30的数量为多条，多条所述第一金属线30沿第二方向均匀排列；和/或，所述第二金属线31的数量为多条，多条所述第二金属线31沿第一方向均匀排列。在一具体实施例中，多条所述第一金属线30之间的间距在0.5微米至2微米之间；和/或，多条所述第二金属线31之间的间距在0.5微米至2微米之间。
参见图2b及2c，所述半导体结构还包括中间金属层M0和导电插塞V1、V2；所述中间金属层M0位于所述第一金属层M1和所述衬底20之间，所述导电插塞V1、V2包括位于所述中间金属层M0和所述第一金属层M1之间的至少一个第一子插塞V1、以及位于所述第一金属层M1与所述第二金属层M2之间的至少一个第二子插塞V2。
在一具体实施例中，所述中间金属层M0包括金属焊盘28，所述金属焊盘28位于所述导电通孔21的上表面，至少一条所述第一金属线30通过所述第一子插塞V1与所述金属焊盘28电连接，如此，信号通过所述导电通孔21可传导至所述第一金属线30。
在一更具体的实施例中，所述第一金属线30与所述第一导电类型晶体管23的栅极233电连接，包括：所述第一金属线30通过所述第一子插塞V1、所述中间金属层M0与所述第一导电类型晶体管23的栅极233电连接，如此，信号通过所述导电通孔21可传导至所述第一导电类型晶体管23的栅极233。
另外，所述第一金属层M1还包括第一布线结构29；所述第二金属线31与所述第二导电类型晶体管24的栅极241电连接，包括：所述第二金属线31通过所述第二子插塞V2、所述第一布线结构29、所述第一子插塞V1、所述中间金属层M0与所述第二导电类型晶体管24的栅极241电连接，如图2c所示。
这里，至少一条所述第一金属线30和至少一条所述第二金属线31可以在交叉处通过所述第二子插塞V2电连接，如此，信号通过所述导电通孔21传导至所述第二导电类型晶体管24的栅极241。
在一实施例中，所述半导体结构还包括环状屏蔽层27，所述环状屏蔽层27围绕所述导电通孔21设置，如图2a所示。所述环状屏蔽层27的作用是降低所述导电通孔21与其附近的金属导电结构在传输信号时产生的串扰效应。
在一具体的实施例中，所述环状屏蔽层27的层数是单层，如图2b及图2c所示；可选的，所述环状屏蔽层27和所述中间金属层M0在相同的工艺步骤中同时形成。但不限于此，所述环状屏蔽层27的层数可以是多层。
在一实施例中，所述半导体结构还包括介质层26，所述介质层26包覆所述中间金属层M0、所述第一金属层M1、所述第二金属层M2、所述环状屏蔽层27以及所述第一子插塞V1、第二子插塞V2。
需要说明的是，所述介质层26并非单层结构，其由多层绝缘材料在多次工艺步骤中形成。
在本公开的实施例中，第一金属线和所述第二金属线相互交叉在导电 通孔上形成了网格结构，可以改善所述导电通孔受热膨胀后向外凸出的情况。此外，在本公开的实施例中，在导电通孔的禁区周围合理设置第一导电类型晶体管和第二导电类型晶体管，所述第一导电类型晶体管和所述第二导电类型晶体管经所述第一金属线和所述第二金属线电连接形成器件，如反相器，可以提高衬底利用率，并且能够改善所述器件的某些性能，如导通速度，功耗等。
本公开实施例还提供了一种半导体结构的制造方法，如图3所示，所述方法包括以下步骤：
步骤301、提供衬底，所述衬底包括预设区域，所述预设区域用于形成导电通孔；
步骤302、在所述衬底内形成第一导电类型晶体管及第二导电类型晶体管；其中，所述第一导电类型晶体管沿第一方向设置于所述预设区域的两侧，所述第二导电类型晶体管沿第二方向设置于所述预设区域的另外两侧，所述第一方向与所述第二方向垂直；
步骤303、在所述衬底的所述预设区域形成导电通孔；
步骤304、在所述衬底上形成第一金属层，所述第一金属层包括至少一条沿第一方向延伸的第一金属线，所述第一金属线与所述第一导电类型晶体管的栅极电连接；
步骤305、在所述第一金属层上形成第二金属层，所述第二金属层包括至少一条沿第二方向延伸的第二金属线，所述第二金属线与所述第二导电类型晶体管的栅极电连接；其中，所述第一金属线和所述第二金属线相互交叉构成覆盖所述导电通孔的网格结构。
下面，结合图4a-4h对本公开实施例的半导体结构的制造方法再做进一步详细的说明。
首先，执行步骤301，提供衬底20，所述衬底20包括预设区域21a，所述预设区域21a用于形成导电通孔21(参见图4d)，如图4a所示。
所述衬底可以为半导体衬底，并且可以包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底)、至少一个III-V化合物半导体材料、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料。在一些实施例中，在一具体实施例中，所述衬底为硅(Si)衬底。
在实际的工艺中，所述衬底的厚度可选在40-70μm之间，例如，50-60μm之间。
在一实施例中，所述预设区域21a为一圆柱形区域，所述圆柱形区域的直径在2-10μm之间。
接下来，执行步骤302，在所述衬底20内形成第一导电类型晶体管23及第二导电类型晶体管24；其中，所述第一导电类型晶体管23沿第一方向设置于所述预设区域21a的两侧，所述第二导电类型晶体管24沿第二方向设置于所述预设区域21a的另外两侧，所述第一方向与所述第二方向垂直，如图4b所示。
所述第一导电类型晶体管23例如可以为n型晶体管，所述第二导电类型晶体管24例如可以为p型晶体管。
在后续的工艺中，会在所述预设区域形成导电通孔。所述导电通孔在制备的过程中，会经历高温至低温的冷却过程，在所述冷却过程中，所述导电通孔及所述衬底收缩的程度不同，会在所述衬底中产生应力，该应力会影响所述导电通孔附近的衬底内的载流子的迁移速度。因此，技术人员在设计半导体结构时，通常会在所述导电通孔周围设置禁区，所述禁区内不设置诸如晶体管之类的有源器件。以所述导电通孔的中心为圆心，所述禁区的半径通常在5-15μm之间。可以理解的是，禁区的存在降低了衬底的利用率。
本申请人经研究发现，在所述禁区内合理的布置不同导电类型的晶体管，不仅可以提高禁区的利用率，还可以提高半导体结构的某些性能。例 如，在本公开的一个实施例中，将n型晶体管沿第一方向设置在所述导电通孔的两侧，且使所述n型晶体管的沟道方向与所述第一方向平行；将p型晶体管沿第二方向设置在所述导电通孔的另外两侧，且使所述p型晶体管的沟道方向与所述第二方向垂直。如此，可以同时提高所述n型晶体管和所述p型晶体管的迁移率，进而提高所述n型晶体管和所述p型晶体管的导通速度。
在本公开的另一个实施例中，将n型晶体管沿第一方向设置在所述导电通孔的两侧，且使所述n型晶体管的沟道方向与所述第一方向垂直；将p型晶体管沿第二方向设置在所述导电通孔的另外两侧，且使所述p型晶体管的沟道方向与所述第二方向平行。如此，可以同时降低所述n型晶体管和所述p型晶体管的迁移率，降低流经所述n型晶体管和所述p型晶体管的漏电流，降低半导体结构的功耗。
需要说明的是，所述第一方向的选取与衬底表面的晶向有关。在本公开的一个实施例中，所述第一方向可以与所述衬底表面的晶向平行。
具体的，所述第一导电类型晶体管23包括栅极233、栅介质层234、第一源/漏掺杂区231和第二源/漏掺杂区232，如图4b所示；所述第二导电类型晶体管24包括栅极241、栅介质层242、第一源/漏掺杂区(未图示)和第二源/漏掺杂区(未图示)，如图2c所示。
再次参见图4b，在一实施例中，所述方法还包括：在所述衬底20内形成隔离结构22。在一具体的实施例中，在形成所述第一导电类型晶体管23和所述第二导电类型晶体管24之前，形成所述隔离结构22。所述隔离结构22用于电隔离位于衬底20内且彼此相邻的器件结构，所述隔离结构22例如可以为浅沟槽隔离结构，所述器件结构可以为形成在所述衬底20内的晶体管，如，本公开实施例中的第一导电类型晶体管23和第二导电类型晶体管24。
如图4c所示，在所述衬底20内形成第一导电类型晶体管23及第二导 电类型晶体管24之后，还包括：在所述衬底20上形成绝缘层25。
具体地，所述绝缘层形成于所述第一导电类型晶体管和所述第二导电类型晶体管的栅极之间，所述绝缘层的上表面与所述栅极的上表面齐平，用于电隔离所述第一导电类型晶体管和所述第二导电类型晶体管的栅极，所述绝缘层还用于保护所述衬底不被氧化、氮化、损伤或者污染等。
在一实施例中，所述衬底20还包括夹设于所述第一导电类型晶体管23和所述第二导电类型晶体管24之间的角区域33，所述角区域33与所述导电通孔21(参见图4d)的距离在1微米至20微米之间，如图2所示。在一具体实例中，所述半导体结构还包括无源器件(未图示)，所述无源器件(未图示)设置于所述衬底20的所述角区域33内，所述无源器件(未图示)包括但不限于电阻器、电容器。在所述角区域33内设置对应力不敏感的无源器件(未图示)，能够提高禁区的利用率。
接下来，执行步骤303，在所述衬底20的所述预设区域21a形成导电通孔21，如图4d所示。
具体地，所述导电通孔21的形成方法包括：在所述衬底20内形成一通孔，所述通孔贯穿所述衬底20和所述绝缘层25；在所述通孔内形成导电材料以形成所述导电通孔21，所述导电通孔21用于在所述半导体结构中传导信号。所述导电材料可以为铜。在一些实施例中，所述导电通孔21的特征尺寸在2-10μm之间，深度在5-100μm之间。
更具体地，所述导电通孔还包括形成于所述通孔内壁上的绝缘膜，以及形成于所述绝缘膜与所述导电材料之间的阻挡层。所述绝缘膜的材料可以是氧化物，如，氧化硅，所述绝缘膜的厚度在
Figure PCTCN2021137432-appb-000001
之间。所述阻挡层可以为金属，如，钽，所述阻挡层的厚度在
Figure PCTCN2021137432-appb-000002
之间。
接下来，执行步骤304，在所述衬底20上形成第一金属层M1，所述第一金属层M1包括至少一条沿第一方向延伸的第一金属线30，所述第一金属线30与所述第一导电类型晶体管23的栅极233电连接，如图4g所示。
具体地，在所述衬底20上形成第一金属层M1，包括：
在所述衬底上形成介质层26，将所述介质层26图案化，在所述图案化的介质层内形成第一金属层M1。
在一实施例中，所述第一金属线30的数量为多条，多条所述第一金属线30沿第二方向均匀排列。在一具体实施例中，多条所述第一金属线30之间的间距在0.5微米至2微米之间。
在一实施例中，所述半导体结构还包括中间金属层M0和第一子插塞V1；在所述衬底20上形成第一金属层M1之前，包括：
在所述衬底20上形成中间金属层M0，所述中间金属层M0与所述第一导电类型晶体管23和所述第二导电类型晶体管24的栅极233、241电连接，如图4e所示；
在所述中间金属层M0上形成第一子插塞V1，所述第一子插塞V1用于电连接所述第一金属层M1与所述中间金属层M0，如图4f。
在一具体实施例中，形成所述中间金属层M0、所述第一子插塞V1，包括：
在所述衬底上形成介质层，将所述介质层图案化，在所述图案化的介质层内形成中间金属层M0；
形成覆盖所述中间金属层M0的介质层，在所述介质层内形成通孔，在所述通孔内形成所述第一子插塞V1。
在一实施例中，所述中间金属层M0包括金属焊盘28，所述金属焊盘28位于所述导电通孔21的上表面，至少一条所述第一金属线30通过所述第一子插塞V1与所述金属焊盘28电连接，如此，信号通过所述导电通孔21可传导至所述第一金属线30。
在一具体的实施例中，所述第一金属线30与所述第一导电类型晶体管23的栅极233电连接，包括：所述第一金属线30通过所述第一子插塞V1、所述中间金属层M0与所述第一导电类型晶体管23的栅极233电连接，如 此，信号可通过所述导电通孔21传导至所述第一导电类型晶体管23的栅极233。
在一实施例中，所述第一金属层M1还包括第一布线结构29，所述第一布线结构29通过所述第一子插塞V1与所述中间金属层M0电连接，如图2c所示。
再次参见图4e，在一实施例中，所述方法还包括：在所述衬底20上形成环状屏蔽层27，所述环状屏蔽层27围绕所述导电通孔21设置。所述环状屏蔽层27的作用是降低所述导电通孔21与其附近的金属导电结构在传输信号时产生的串扰效应。在一具体实施例中，所述环状屏蔽层27的层数是单层，所述环状屏蔽层27和所述中间金属层M0在相同的工艺步骤中同时形成。但不限于此，所述环状屏蔽层27的层数可以是多层。
最后，执行步骤305，在所述第一金属层M1上形成第二金属层M2，所述第二金属层M2包括至少一条沿第二方向延伸的第二金属线31，所述第二金属线31与所述第二导电类型晶体管24的栅极241电连接；其中，所述第一金属线30和所述第二金属线31相互交叉构成覆盖所述导电通孔21的网格结构32，如图2a-2c所示。
具体地，在所述第一金属层M1上形成第二金属层M2，包括：
形成覆盖所述第一金属层的介质层，将所述介质层图案化，在所述图案化的介质层内形成第二金属层M2。
在一实施例中，所述第二金属线31的数量为多条，多条所述第二金属线31沿第一方向均匀排列。在一具体实施例中，多条所述第二金属线31之间的间距在0.5微米至2微米之间。
在一实施例中，所述半导体结构还包括第二子插塞V2；在所述第一金属层M1上形成第二金属层M2之前，包括：在所述第一金属层M1上形成所述第二子插塞V2，所述第二子插塞V2用于电连接所述第一金属层M1和所述第二金属层M2，如图4h所示。
具体地，在所述第一金属层M1上形成所述第二子插塞V2，包括：
在所述第一金属层M1上形成介质层，在所述介质层内形成通孔，在所述通孔内形成所述第二子插塞V2。
在一实施例中，所述第二金属线31与所述第二导电类型晶体管24的栅极241电连接，包括：所述第二金属线31通过所述第二子插塞V2、所述第一布线结构29、所述第一子插塞V1、所述中间金属层M0与所述第二导电类型晶体管24的栅极241电连接。
在一具体的实施例中，至少一条所述第一金属线30和至少一条所述第二金属线31在交叉处通过所述第二子插塞V2电连接，如此，信号通过所述导电通孔21传导至所述第二导电类型晶体管24的栅极241。
应当说明的是，本领域技术人员能够对上述步骤顺序进行变换而并不离开本公开的保护范围以上所述，仅为本公开的可选实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例提供的半导体结构及其制造方法，其中，所述半导体结构包括：衬底以及位于所述衬底内的导电通孔、第一导电类型晶体管及第二导电类型晶体管；其中，所述第一导电类型晶体管沿第一方向设置于所述导电通孔的两侧；所述第二导电类型晶体管沿第二方向设置于所述导电通孔的另外两侧；所述第一方向与所述第二方向垂直；第一金属层，位于所述衬底上，所述第一金属层包括至少一条沿第一方向延伸的第一金属线，所述第一金属线与所述第一导电类型晶体管的栅极电连接；第二金属层，位于所述第一金属层上，所述第二金属层包括至少一条沿第二方向延伸的第二金属线，所述第二金属线与所述第二导电类型晶体管的栅极电连接；其中，所述第一金属线和所述第二金属线相互交叉构成覆盖所述导电通孔 的网格结构。如此，可以改善所述导电通孔受热膨胀后向外凸出的情况；此外，所述第一金属线和所述第二金属线分别与所述第一导电类型晶体管和所述第二导电类型晶体管的栅极连接，起到了电连接的作用。

Claims (16)

  1. 一种半导体结构，包括：
    衬底以及位于所述衬底内的导电通孔、第一导电类型晶体管及第二导电类型晶体管；其中，所述第一导电类型晶体管沿第一方向设置于所述导电通孔的两侧；所述第二导电类型晶体管沿第二方向设置于所述导电通孔的另外两侧；所述第一方向与所述第二方向垂直；
    第一金属层，位于所述衬底上，所述第一金属层包括至少一条沿第一方向延伸的第一金属线，所述第一金属线与所述第一导电类型晶体管的栅极电连接；
    第二金属层，位于所述第一金属层上，所述第二金属层包括至少一条沿第二方向延伸的第二金属线，所述第二金属线与所述第二导电类型晶体管的栅极电连接；
    其中，所述第一金属线和所述第二金属线相互交叉构成覆盖所述导电通孔的网格结构。
  2. 根据权利要求1所述的半导体结构，其中，所述第一金属线的数量为多条，多条所述第一金属线沿第二方向均匀排列；和/或，所述第二金属线的数量为多条，多条所述第二金属线沿第一方向均匀排列。
  3. 根据权利要求2所述的半导体结构，其中，多条所述第一金属线之间的间距在0.5微米至2微米之间；和/或，多条所述第二金属线之间的间距在0.5微米至2微米之间。
  4. 根据权利要求1所述的半导体结构，其中，所述第一导电类型晶体管为n型晶体管，所述第二导电类型晶体管为p型晶体管。
  5. 根据权利要求4所述的半导体结构，其中，所述第一导电类型晶体管的沟道方向与所述第一方向平行；所述第二导电类型晶体管的沟道方向与所述第二方向垂直。
  6. 根据权利要求4所述的半导体结构，其中，所述第一导电类型晶体管的沟道方向与所述第一方向垂直；所述第二导电类型晶体管的沟道方向与所述第二方向平行。
  7. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括中间金属层和导电插塞；所述中间金属层位于所述第一金属层和所述衬底之间，所述导电插塞包括位于所述中间金属层和所述第一金属层之间的至少一个第一子插塞、以及位于所述第一金属层与所述第二金属层之间的至少一个第二子插塞。
  8. 根据权利要求7所述的半导体结构，其中，所述第一金属线与所述第一导电类型晶体管的栅极电连接，包括：所述第一金属线通过所述第一子插塞、所述中间金属层与所述第一导电类型晶体管的栅极电连接。
  9. 根据权利要求7所述的半导体结构，其中，所述第一金属层还包括第一布线结构；所述第二金属线与所述第二导电类型晶体管的栅极电连接，包括：所述第二金属线通过所述第二子插塞、所述第一布线结构、所述第一子插塞、所述中间金属层与所述第二导电类型晶体管的栅极电连接。
  10. 根据权利要求7所述的半导体结构，其中，至少一条所述第一金属线和至少一条所述第二金属线在交叉处通过所述第二子插塞电连接。
  11. 根据权利要求7所述的半导体结构，其中，所述中间金属层包括金属焊盘，所述金属焊盘位于所述导电通孔的上表面；
    至少一条所述第一金属线通过所述第一子插塞与所述金属焊盘电连接。
  12. 根据权利要求1所述的半导体结构，其中，所述衬底包括夹设于所述第一导电类型晶体管和所述第二导电类型晶体管之间的角区域，所述角区域与所述导电通孔的距离在1微米至20微米之间。
  13. 根据权利要求12所述的半导体结构，其中，所述半导体结构还 包括无源器件，所述无源器件设置于所述衬底的所述角区域内。
  14. 一种半导体结构的制备方法，包括：
    提供衬底，所述衬底包括预设区域，所述预设区域用于形成导电通孔；
    在所述衬底内形成第一导电类型晶体管及第二导电类型晶体管；其中，所述第一导电类型晶体管沿第一方向设置于所述预设区域的两侧，所述第二导电类型晶体管沿第二方向设置于所述预设区域的另外两侧，所述第一方向与所述第二方向垂直；
    在所述衬底的所述预设区域形成导电通孔；
    在所述衬底上形成第一金属层，所述第一金属层包括至少一条沿第一方向延伸的第一金属线，所述第一金属线与所述第一导电类型晶体管的栅极电连接；
    在所述第一金属层上形成第二金属层，所述第二金属层包括至少一条沿第二方向延伸的第二金属线，所述第二金属线与所述第二导电类型晶体管的栅极电连接；
    其中，所述第一金属线和所述第二金属线相互交叉构成覆盖所述导电通孔的网格结构。
  15. 根据权利要求14所述的制备方法，其中，所述半导体结构还包括中间金属层和第一子插塞；在所述衬底上形成第一金属层之前，包括：
    在所述衬底上形成中间金属层，所述中间金属层与所述第一导电类型晶体管和所述第二导电类型晶体管的栅极电连接；
    在所述中间金属层上形成第一子插塞，所述第一子插塞用于电连接所述第一金属层与所述中间金属层。
  16. 根据权利要求14所述的制备方法，其中，所述半导体结构还包括第二子插塞；在所述第一金属层上形成第二金属层之前，包括：
    在所述第一金属层上形成所述第二子插塞，所述第二子插塞用于电 连接所述第一金属层和所述第二金属层。
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