TW202247309A - 半導體結構 - Google Patents

半導體結構 Download PDF

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TW202247309A
TW202247309A TW110134710A TW110134710A TW202247309A TW 202247309 A TW202247309 A TW 202247309A TW 110134710 A TW110134710 A TW 110134710A TW 110134710 A TW110134710 A TW 110134710A TW 202247309 A TW202247309 A TW 202247309A
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gate
conductive pad
buried conductive
electrically coupled
via hole
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TW110134710A
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吳國暉
王柏鈞
陳志良
田麗鈞
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台灣積體電路製造股份有限公司
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Abstract

一種半導體結構，包括形成於基板上的隔離結構、形成於隔離結構上的環繞式閘極電晶體結構、電性耦接至環繞式閘極電晶體結構閘極的通孔，以及在隔離結構內並電性耦接至通孔的埋入式導電墊，上述埋入式導電墊可以在兩個維度上(例如在垂直維度與水平維度上) 延伸通過隔離結構，上述半導體結構具有其他可能的優勢，其中之一是可以在佈線靈活性的方面提供優勢。

Description

與環繞式閘極裝置一起使用的埋入式銲墊
無。
本揭示內容係有關半導體裝置和用於製造半導體裝置的方法，尤其是關於包括半導體裝置之電路的設計佈局。隨著半導體裝置的特徵尺寸不斷減小，對電路佈局中空間使用的限制經常會出現，半導體裝置用於各種電子產品，且通常需要同時改進半導體裝置的製造和性能。
無。
以下揭示內容提供了用於實現提供之標的的不同特徵的許多不同的實施例或實例。以下描述組件、材料、值、步驟、操作、材料、佈置等的特定實例用以簡化本案的一實施例。當然，該些僅為實例，並不旨在進行限制。可以預期其他組件、值、操作、材料、佈置等。例如，在下面的描述中在第二特徵上方或之上形成第一特徵可包括其中第一及第二特徵直接接觸形成的實施例，並且亦可包括其中在第一與第二特徵之間形成附加特徵的實施例，以使得第一及第二特徵可以不直接接觸。此外，本案的一實施例可以在各個實例中重複元件符號及/或字母。此重複係出於簡單及清楚的目的，其本身並不指定所討論之各種實施例或組態之間的關係。
此外，為了便於描述，本文中可以使用諸如「在...下方」、「在...下」、「下方」、「在...上方」、「上方」之類的空間相對術語，來描述如圖中所示的一個元件或特徵與另一元件或特徵的關係。除了在附圖中示出的方位之外，空間相對術語意在涵蓋裝置在使用或操作中的不同方位。裝置可以其他方式定向(旋轉90度或以其他方位)，並且在此使用的空間相對描述語亦可被相應地解釋。
本揭示內容提供了一種能在積體電路中實現的半導體結構，該半導體結構包括環繞式閘極電晶體結構，該電晶體結構電性耦接至埋入式導電墊，上述埋入式導電墊使用通孔形成於隔離結構內。在隔離結構(例如形成在基板上的淺溝槽隔離結構)內埋入式導電墊的形成，可在設計電路佈局時於佈線靈活性方面提供優勢。
參照第1A圖示出根據一些實施例的實例半導體結構100的俯視圖。半導體結構100通常包括複數個環繞式閘極電晶體結構，例如環繞式閘極場效電晶體(gate-all-around field-effect transistor；GAAFET)結構，這些結構有時被稱為環繞閘極電晶體 (surrounding-gate transistor；SGT)結構，與諸如鰭式場效電晶體(FinFET)結構的一些替代方案相比，環繞式閘極電晶體結構通常可以允許形成更小的電晶體結構，進而能形成更小和更緊湊的積體電路。環繞式閘極電晶體結構形成在隔離結構上，且上述隔離結構形成在基板上。
半導體結構100示出了包括複數個磊晶區110。如第1A圖所示，磊晶區110沿半導體結構100於水平方向 (從第1A圖中所示的頂部) 上以均勻或大約均勻間隔的距離形成，磊晶區110各自用以作為一個或多個環繞式閘極的源極或汲極端。磊晶區110通常是可以使用磊晶成長製程所形成的晶體結構，磊晶成長製程例如是化學氣相沉積(chemical vapor deposition；CVD)、氣相磊晶(vapor-phase epitaxy；VPE)、分子束磊晶(molecular-beam epitaxy；MBE)、液相磊晶(liquid-phase epitaxy；LPE)及其他合適的製程與其組合，磊晶區110可以使用合適的摻雜物摻雜，包括n型和p型摻雜物。
半導體結構100也示出包括複數個通道結構120。通道結構120可以使用奈米線或奈米片來實現，例如：每個通道結構120可以使用三個(或更多，或更少)奈米片來實現，上述奈米片使用諸如砷化鎵銦(InGaAs)之類的半導體材料形成，其他合適的半導體材料也可用於形成奈米片。同樣地，每個通道結構120可以使用三個(或更多，或更少)奈米線來實現，上述奈米線使用半導體材料形成，諸如砷化銦鎵以及其他合適的半導體材料。奈米片通常具有更平坦的幾何輪廓，而奈米線通常具有更圓的幾何輪廓。應當理解的是，除了奈米片和奈米線之外，還可以使用其他合適的結構來實現通道結構120，如第1A圖之俯視圖所示，磊晶區110形成在通道結構120上，通道結構120通常形成在半導體結構100的隔離結構170上，更詳細的討論如下文。
半導體結構100也示出包括複數個閘極結構140。舉例而言，閘極結構140可以實現為多晶矽或金屬閘極結構。每個閘極結構140係環繞每個通道結構120的相應部分形成，以便與相應的磊晶區110一起形成單獨的環繞式閘極電晶體結構。閘極結構140可使用各種合適的製程形成，包括化學氣相沉積(CVD)和其他合適的製程及其組合。雖然在第1A圖中沒有明確例示，應當理解的是附加層可以在半導體結構 100的製造過程中形成，其中附加層包括例如用於電性隔離閘極結構140的間隔物以及其他合適的絕緣層，如第1A圖所示，閘極結構140通常設置與通道結構120垂直。
半導體結構100也示出包括複數個埋入式(或背面)導電墊130(如下文進一步討論)及兩個剖面（剖面150和剖面160）。剖面150是沿閘極結構140之一者於垂直方向(從第1A圖所示的俯視圖)切割，而剖面160是沿埋入式導電墊130之一者於水平方向(從第1A圖所示的俯視圖)切割。埋入式導電墊130通常由導電材料例如銅、鋁、鎢、鈷或其他合適的導電材料及其組合形成，埋入式導電墊130通常可以在半導體結構100內提供電子訊號的佈線，例如：在半導體結構100的背面上
參照第1B圖示出根據一些實施例的半導體結構100的剖面，上述剖面是切割自第1A圖例示的剖面150。在第1B圖中的剖面中，可以看到隔離結構170，其可以形成在半導體結構100(未示出)之基板的背面上，上述基板可以原矽基板、矽隔離體上的矽基板、藍寶石上的矽基板和其他類型的基板來實現。隔離結構170可以淺溝槽隔離(shallow trench isolation；STI)結構或層間介電(interlayer dielectric；ILD)結構來實現，且可以藉由在基板內創建溝槽，再用隔離材料(例如介電材料諸如二氧化矽)填充溝槽來形成，並使用化學機械拋光(chemical-mechanical polishing；CMP)等製程去除多餘的隔離材料。
第1B圖中也示出通孔180，通孔180用於將圖示的閘極結構140和埋入式導電墊130電性耦接，通孔180可以使用多種不同的材料和結構來實現，例如銅、鋁、鎢、鈷和其他合適的金屬材料或其組合。通孔180可以參照第1A圖的俯視圖所示。如第1B圖例示，通孔180和埋入式導電墊130都形成在隔離結構170內。第1B圖也例示通道結構120的剖面，其中在第1B圖的實施例中，通道結構120是使用奈米片實現的。在第1B圖中可以看出，圖中例示的閘極結構140環繞奈米片，以形成環繞式閘極晶體結構。如第1B圖例示，奈米片是被薄氧化物層包圍的矽薄片，然而應當理解的是通道結構120可以多種不同的方式實現。
參照第1C圖，第1C圖示出根據一些實施例的半導體結構100之另一剖面，上述剖面是切割自第1A圖例示的剖面160。在第1C圖的剖面中，可以看到形成在半導體結構100內的複數個不同之通孔180，上述多個通孔180包括第一通孔、第二通孔以及第三通孔，其中第一通孔電性耦接至第一環繞式閘極電晶體結構的閘極端，第二通孔電性耦接至第二環繞式閘極電晶體結構的閘極端，第三通孔電性耦接至第三環繞式閘極電晶體結構的磊晶區(源極端或汲極端)。每個圖示的通孔180也電性耦接至圖示的埋入式導電墊130。在各種實施例中，閘極結構140各自形成以環繞通道結構120的每一者(如圖1B所示)，且磊晶區110各自形成在每個閘極結構140的一側(如第1A圖和1C所示)。
參照第2圖，第2圖示出根據一些實施例的另一例示半導體結構200之俯視圖。半導體結構200與半導體100的相似之處在於它包括複數個磊晶區210、複數個通道結構220、複數個埋入式導電墊230、複數個閘極結構240以及複數個通孔280，這些結構分別類似於半導體結構100的磊晶區110、通道結構120、埋入式導電墊130、閘極結構140以及通孔180，因此不再重複討論。然而，如第2圖例示，埋入式導電墊230可以沿著半導體結構200的隔離結構(類似於上述的隔離結構170)內的兩個維度延伸。例如：兩個埋入式導電墊230沿通道結構220延伸，其中一個埋入式導電墊230沿著與水平通道結構220及垂直閘極結構240傾斜的方向延伸。特別的是，這種傾斜的埋入式導電墊230可以延伸橫跨一個或多個通道結構220的各自投影。
由於通道結構220形成於半導體結構200的隔離結構上而不是在上述隔離結構內，因此可以達到埋入式導電墊230的額外佈線靈活性。由於在隔離結構內不存在鰭片(例如鰭式場效電晶體裝置的鰭片)，因此可以在隔離結構內的多個方向上形成埋入式導電墊230，而無需擔心碰到鰭片。形成於半導體結構200內延伸於兩個維度上的埋入式導電墊230有各種可能性，思及其中一些關於例示的電路佈局300、400、500如下所述。此外，因為這種佈線靈活性，使埋入式導電墊230不會碰到隔離結構內的鰭片或其他障礙物，因此可以實現對於埋入式導電墊230具有減少面積需求的電路佈局。
參照第3A圖，第3A圖示出根據一些實施例的實例電路佈局300的俯視圖。電路佈局300可以對應於掃瞄式D型正反器(D-flip flop)，或具有掃描輸入的D型正反器，為了清楚起見，在圖中未示出。電路佈局300類似於半導體結構100和半導體結構200，因為電路佈局300包括形成於隔離結構上的複數個環繞式閘極電晶體結構，以及形成於隔離結構內的複數個埋入式導電墊。上述埋入式導電墊可以延伸於兩個維度上，從而提供增強的佈線靈活性和減少電路佈局 300之總面積需求的能力。
在第3A圖中，繪示複數個通道結構320和複數個閘極結構340，這些結構類似於上文討論的通道結構120和通道結構220，及閘極結構140和閘極結構240。電路佈局300也被示出為包括環繞通道結構320所形成的複數個磊晶區350，類似於上文討論的磊晶區110和磊晶區210。第3A圖中也示出了複數個埋入式導電墊330，上述的多個埋入式導電墊330電性耦接至電路佈局300的各種環繞式閘極電晶體結構。埋入式導電墊330類似於上文討論的埋入式導電墊130和埋入式導電墊230，即形成在基板的背面上，以實現電路佈局300。電路佈局300提供如本揭示內容所述的二維埋入式導電墊之例示實現方式，透過此種埋入式導電墊的使用，可以減少電路佈局300的中心多晶矽間距(與實現鰭式場效電晶體結構的現存佈局相比)，而這是因為所揭示的埋入式導電墊可以更靈活地形成於橫跨採用GAAFET結構的多個通道結構，或形成於採用GAAFET結構的多個通道結構之間，致使需要的面積更少(例如：減少至少9%)。第3A圖中也示出第一電源軌301、第二電源軌303和接地軌302。在一些實施例中，此類電源軌形成在基板的背面上。
參照第3B圖，第3B圖示出根據一些實施例的電路佈局300的仰視圖。在第3B圖中，可以看到通道結構320以及閘極結構340。此外，也可以看到電源軌301、電源軌303和接地軌302沿著埋入式導電墊330。第3B圖提供了埋入式導電墊330的另一個視圖，以說明埋入式導電墊330的二維特性，如在第3B圖所見，埋入式導電墊330不僅延伸於x維度上，也延伸於y維度上。
參照第4A圖，第4A圖示出根據一些實施例的另一例示電路佈局400的俯視圖。電路佈局400可以對應於與或非閘(AND-OR-INVERTER)且在第4C圖中所示並非限制的實例。如第4C圖所示，與或非閘包括多個電晶體，每個電晶體都由輸入訊號A1、A2、A3和B閘控，並且電晶體共同提供輸出訊號ZN。在一些實施例中，第4C圖所示的反相器可以提供以下布林函數：
Figure 02_image001
，這種輸入/輸出訊號可以透過多個導電結構提供，其在第4A圖的俯視圖中可更好地理解。電路佈局400也類似於半導體結構100和半導體結構200，因為它包括形成於隔離結構上的複數個環繞式閘極電晶體結構，以及形成於隔離結構內的複數個埋入式導電墊。上述多個埋入式導電墊形成於電路佈局400的隔離結構內，從而提供增強的佈線靈活性和減少電路佈局400之總面積需求的能力。
在第4A圖中，其繪示複數個通道結構420和複數個閘極結構440，這些結構類似於上文討論的通道結構120和通道結構220，以及閘極結構140和閘極結構240。電路佈局400也被示出為包括環繞通道結構420形成的複數個磊晶區450，類似於上文討論的磊晶區110和磊晶區210。第4A圖中也示出了複數個埋入式導電墊430，上述多個埋入式導電墊430電性耦接至電路佈局400的各種環繞式閘極電晶體結構。埋入式導電墊430類似於上文討論的埋入式導電墊130和埋入式導電墊230，即形成在基板的背面上，以實現電路佈局400。電路佈局400提供如本揭示內容所述的埋入式導電墊形成於隔離結構內之例示實現方式。透過此種埋入式導電墊的使用，可以減少電路佈局400的中心多晶矽間距(與實現鰭式場效電晶體結構的現存佈局相比)，這是因為所揭示的埋入式導電墊可以更靈活地形成於橫跨採用GAAFET結構的多個通道結構或形成於採用GAAFET結構的多個通道結構之間，致使需要的面積更少(例如：減少至少10%)。第4A圖中也示出電源軌401和接地軌402，在一些實施例中，此類電源軌形成於基板的背面上。
參照第4B圖，第4B圖示出根據一些實施例的電路佈局400的仰視圖。在第4B圖中，可以看到通道結構420以及閘極結構440。此外，也可以看到電源軌401和接地軌402沿著埋入式導電墊430。第4B圖提供埋入式導電墊430的另一視圖，以說明埋入式導電墊430的特性。
參照第5A圖，第5A圖示出根據一些實施例的另一例示電路佈局500的俯視圖。電路佈局500可以對應於另一與或非閘且在第5C圖中所示並非限制性的實例。如第5C圖所示，與或非閘包括多個電晶體，每個電晶體由輸入訊號A1、A2、B1和B2閘控，並且電晶體共同提供輸出訊號ZN。在一些實施例中，第5C圖所示的反相器可以提供以下布林函數：
Figure 02_image003
，這種輸入/輸出訊號可以透過多個導電結構提供，其在第5A圖的俯視圖中可好地理解。電路佈局500類似於半導體結構100和半導體結構200，因為它包括形成於隔離結構上的複數個環繞式閘極電晶體結構，以及形成於隔離結構內的埋入式導電墊。上述埋入式導電墊可以延伸於兩個維度上，從而提供增強的佈線靈活性和減少電路佈局500之總面積要求的能力。
在第5A圖中，其繪示複數個通道結構520和複數個閘極結構540，這些結構類似於上文討論的通道結構120和通道結構220，以及閘極結構140和閘極結構240。電路佈局500也被示出為包括環繞通道結構520形成的複數個磊晶區550，類似於上文討論的磊晶區110和磊晶區210。第5A圖中也示出了埋入式導電墊530，上述埋入式導電墊530電性耦接至電路佈局500的各種環繞式閘極電晶體結構。埋入式導電墊530類似於上文討論的埋入式導電墊130和埋入式導電墊230，即形成在基板的背面上，以實現電路佈局500。電路佈局500提供如本揭示內容所述的二維埋入式導電墊之例示實現方式，透過此種埋入式導電墊的使用，可以減少電路佈局500的中心多晶矽間距(與實現鰭式場效電晶體結構的現存佈局相比)。這是因為所揭示的埋入式導電墊可以更靈活地形成於橫跨採用GAAFET結構的多個通道結構或形成於採用GAAFET結構的多個通道結構之間，致使所需的面積更少。第5A圖中也示出電源軌501和接地軌502。在一些實施例中，此類電源軌形成於基板的背面上。
參照第5B圖示出根據一些實施例的電路佈局500的仰視圖。在第5B圖中，可以看到通道結構520以及閘極結構540，此外，也可以看到電源軌501和接地軌502沿著埋入式導電墊530。第5B圖提供了埋入式導電墊530的另一視圖，以說明埋入式導電墊530的二維特性，如第5B圖中所見，埋入式導電墊530不僅延伸於x維度上，也延伸於y維度上。
如上文的詳細描述，本揭示內容提供一半導體結構以於積體電路中實現，此半導體結構包括環繞式閘極電晶體結構，上述電晶體結構電性耦接至埋入式導電墊，而上述埋入式導電墊使用通孔形成於隔離結構內。埋入式導電墊於隔離結構(例如形成於基板上的淺溝槽隔離結構)內的形成，可以在設計電路佈局時於佈線靈活性的方面提供優勢。
本揭示內容的一實現方式是半導體結構。此半導體結構包括形成於基板上的隔離結構、形成於隔離結構上的環繞式閘極電晶體結構、通孔及埋入式導電墊。上述通孔電性耦接至環繞式閘極電晶體結構的閘極端，而上述埋入式導電墊形成於隔離結構內並電性耦接至上述通孔。
本揭示內容的另一實現方式是電路。此電路包括形成於基板上的淺溝槽隔離結構、形成於淺溝槽隔離結構上且環繞複數條奈米線的閘極結構、電性耦接至閘極結構的通孔、以及埋入式導電墊，上述埋入式導電墊形成於淺溝槽隔離結構內並電性耦接至上述通孔，且在淺溝槽隔離結構內延伸於兩個維度上。
本揭示內容的又一實現方式是另一半導體結構。此半導體結構包括形成於基板上的隔離結構、形成於隔離結構上且環繞複數個奈米片的閘極結構、電性耦接至閘極結構的通孔、以及埋入式導電墊，上述埋入式導電墊形成於淺溝槽隔離結構內並電性耦接至上述通孔，且在隔離結構內延伸於水平維度和垂直維度上。
上文概述了幾個實施例的特徵，以便本領域技術人員可更好地理解本揭示內容的各層面，本領域技術人員應當理解的是，他們可以容易地使用本揭示內容作為設計或修改其他製程和結構的基礎，以實現與本文介紹的實施例相同之目的及/或達到相同之優點。本領域技術人員也應該意識到，這樣的等效構造並不脫離本揭示內容的精神和範圍，在不脫離本揭示內容的精神和範圍的情況下，可以對本文進行各種變化、替換和變更。
100:半導體結構 110:磊晶區 120:通道結構 130:埋入式導電墊 140:閘極結構 150:剖面 160:剖面 170:隔離結構 180:通孔 200:半導體結構 210:磊晶區 220:通道結構 230:埋入式導電墊 240:閘極結構 280:通孔 300:電路佈局 301:電源軌 302:接地軌 303:電源軌 320:通道結構 330:埋入式導電墊 340:閘極結構 350:磊晶區 400:電路佈局 401:電源軌 402:接地軌 420:通道結構 430:埋入式導電墊 440:閘極結構 450:磊晶區 500:電路佈局 501:電源軌 502:接地軌 520:通道結構 530:埋入式導電墊 540:閘極結構 550:磊晶區 A1-A3:輸入信號 B1-B2:輸入信號 ZN:輸出信號
以下詳細描述結合附圖閱讀時，可以最好地理解本揭示內容的各方面。注意，根據行業中的標準實踐，各種特徵並未按比例繪製。事實上，為了討論的清楚起見，各種特徵的尺寸可以任意擴大或縮小。 第1A圖示出根據一些實施例的實例半導體結構之俯視圖。 第1B圖示出根據一些實施例的第1A圖的半導體結構之剖面圖。 第1C圖示出根據一些實施例的第1A圖的半導體結構之另一剖面圖。 第2圖示出根據一些實施例的另一例示半導體結構之俯視圖。 第3A圖示出根據一些實施例的實例電路佈局之俯視圖。 第3B圖示出根據一些實施例的第3A圖的實例電路佈局之仰視圖。 第4A圖示出根據一些實施例的實例電路佈局之俯視圖。 第4B圖示出根據一些實施例的第4A圖的實例電路佈局之仰視圖。 第4C圖示出根據一些實施例且對應於第4A圖至第4B圖的佈局之實例電路圖。 第5A圖示出根據一些實施例的實例電路佈局之俯視圖。 第5B圖示出根據一些實施例的第5A圖的實例電路佈局之仰視圖。 第5C圖示出根據一些實施例且對應於第5A圖至第5B圖的佈局之實例電路圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
100:半導體結構
110:磊晶區
120:通道結構
130:埋入式導電墊
140:閘極結構
150:剖面
160:剖面
180:通孔

Claims (20)

  1. 一種半導體結構，包括： 一隔離結構，形成於一基板上； 一環繞式閘極電晶體結構，形成於該隔離結構上； 一通孔，電性耦接至環繞式閘極電晶體結構的一閘極端；以及 一埋入式導電墊，形成於該隔離結構內，且該埋入式導電墊電性耦接至該通孔。
  2. 如請求項1所述之半導體結構，其中該埋入式導電墊在該隔離結構內延伸於一水平維度和一垂直維度上。
  3. 如請求項1所述之半導體結構，其中該埋入式導電墊在該隔離結構內沿兩個維度延伸。
  4. 如請求項1所述之半導體結構，其中該通孔包括一第一通孔，且該環繞式閘極電晶體結構包括一第一環繞式閘極電晶體結構，該半導體結構更包括一第二環繞式閘極電晶體結構和一第二通孔，其中該第二通孔電性耦接至該埋入式導電墊與該第二環繞式閘極電晶體結構的一閘極端。
  5. 如請求項1所述之半導體結構，其中該通孔包括一第一通孔，該半導體結構更包括一第二通孔，該第二通孔電性耦接至該環繞式閘極電晶體結構的一源極端或一汲極端並電性耦接至該埋入式導電墊。
  6. 如請求項1所述之半導體結構，其中該環繞式閘極電晶體結構的該閘極端環繞複數個奈米線形成。
  7. 如請求項1所述之半導體結構，其中該環繞式閘極電晶體結構的該閘極端環繞複數個奈米片形成。
  8. 一種電路，包括： 一淺溝槽隔離結構，形成於基板上； 一閘極結構，形成於淺溝槽隔離結構上且環繞複數條奈米線； 一通孔，電性耦接至閘極結構；以及 一埋入式導電墊，該埋入式導電墊形成於淺溝槽隔離結構內並電性耦接至上述通孔，且在淺溝槽隔離結構內延伸於兩個維度上。
  9. 如請求項8所述之電路，其中該閘極結構使用多晶矽材料形成，且該閘極結構是一環繞式閘極電晶體結構的一閘極端。
  10. 如請求項8所述之電路，其中該通孔包括一第一通孔並且該閘極結構包括一第一閘極結構，該電路更包括一第二通孔，該第二通孔電性耦接至該埋入式導電墊與一第二閘極結構。
  11. 如請求項8所述之電路，其中該通孔包括一第一通孔，該電路更包括一第二通孔，該第二通孔電性耦接至一磊晶區與該埋入式導電墊。
  12. 如請求項8所述之電路，其中該埋入式導電墊在該隔離結構內延伸於一水平維度和一垂直維度上。
  13. 如請求項8所述之電路，其中該埋入式導電墊包括一第一部分和一第二部分，該第一部分在該淺溝槽隔離結構內延伸於一個維度上，而該第二部分在該淺溝槽隔離結構內延伸於兩個維度上。
  14. 如請求項8所述之電路，進一步包括一第三通孔，該第三通孔電性耦接至一磊晶區與該埋入式導電墊。
  15. 一種半導體結構，包括： 一隔離結構，形成於基板上； 一閘極結構，形成於隔離結構上且環繞複數個奈米片； 一通孔，電性耦接至閘極結構；以及 一埋入式導電墊，該埋入式導電墊形成於淺溝槽隔離結構內並電性耦接至上述通孔，且在隔離結構內延伸於水平維度和垂直維度上。
  16. 如請求項15所述之半導體結構，其中該閘極結構使用多晶矽材料形成，且該閘極結構是一環繞式閘極電晶體結構的一閘極端。
  17. 如請求項15所述之半導體結構，其中該通孔包括一第一通孔且該閘極結構包括一第一閘極結構，該電路更包括一第二通孔，該第二通孔電性耦接至該埋入式導電墊與一第二閘極結構。
  18. 如請求項17所述之半導體結構，進一步包括一第三通孔，該第三通孔電性耦接至一磊晶區與該埋入式導電墊。
  19. 如請求項15所述之半導體結構，其中該通孔包括一第一通孔，半導體結構更包括一第二通孔，該第二通孔電性耦接至一磊晶區與該埋入式導電墊。
  20. 如請求項16所述之半導體結構，其中該通孔包括一第一通孔，半導體結構更包括一第二通孔，該第二通孔電性耦接至該環繞式閘極電晶體結構的的一源極端或一汲極端並電性耦接至該埋入式導電墊。
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