CN115116951A - 半导体结构及集成电路 - Google Patents

半导体结构及集成电路 Download PDF

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CN115116951A
CN115116951A CN202210569872.4A CN202210569872A CN115116951A CN 115116951 A CN115116951 A CN 115116951A CN 202210569872 A CN202210569872 A CN 202210569872A CN 115116951 A CN115116951 A CN 115116951A
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gate
conductive pad
buried conductive
electrically coupled
semiconductor structure
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吴国晖
王柏钧
陈志良
田丽钧
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体结构及集成电路，半导体结构包括形成于基板上的隔离结构、形成于隔离结构上的环绕式栅极晶体管结构、电性耦接至环绕式栅极晶体管结构栅极的通孔，以及在隔离结构内并电性耦接至通孔的埋入式导电垫，上述埋入式导电垫可以在两个维度上(例如在垂直维度与水平维度上)延伸通过隔离结构，上述半导体结构具有其他可能的优势，其中之一是可以在布线灵活性的方面提供优势。

Description

半导体结构及集成电路
技术领域
本揭示内容有关半导体装置，尤其是关于包括半导体装置的电路的设计布局。
背景技术
本揭示内容是有关半导体装置和用于制造半导体装置的方法，尤其是关于包括半导体装置的电路的设计布局。随着半导体装置的特征尺寸不断减小，对电路布局中空间使用的限制经常会出现，半导体装置用于各种电子产品，且通常需要同时改进半导体装置的制造和性能。
发明内容
本揭示内容的一实现方式是半导体结构。此半导体结构包括形成于基板上的隔离结构、形成于隔离结构上的环绕式栅极晶体管结构、通孔及埋入式导电垫。上述通孔电性耦接至环绕式栅极晶体管结构的栅极端，而上述埋入式导电垫形成于隔离结构内并电性耦接至上述通孔。
本揭示内容的另一实现方式是集成电路。此集成电路包括形成于基板上的浅沟槽隔离结构、形成于浅沟槽隔离结构上且环绕多条纳米线的栅极结构、电性耦接至栅极结构的通孔、以及埋入式导电垫，上述埋入式导电垫形成于浅沟槽隔离结构内并电性耦接至上述通孔，且在浅沟槽隔离结构内延伸于两个维度上。
本揭示内容的又一实现方式是另一半导体结构。此半导体结构包括形成于基板上的隔离结构、形成于隔离结构上且环绕多个纳米片的栅极结构、电性耦接至栅极结构的通孔、以及埋入式导电垫，上述埋入式导电垫形成于浅沟槽隔离结构内并电性耦接至上述通孔，且在隔离结构内延伸于水平维度和垂直维度上。
附图说明
以下详细描述结合附图阅读时，可以最好地理解本揭示内容的各方面。注意，根据行业中的标准实践，各种特征并未按比例绘制。事实上，为了讨论的清楚起见，各种特征的尺寸可以任意扩大或缩小。
图1A示出根据一些实施例的实例半导体结构的俯视图；
图1B示出根据一些实施例的图1A的半导体结构的剖面图；
图1C示出根据一些实施例的图1A的半导体结构的另一剖面图；
图2示出根据一些实施例的另一例示半导体结构的俯视图；
图3A示出根据一些实施例的实例电路布局的俯视图；
图3B示出根据一些实施例的图3A的实例电路布局的仰视图；
图4A示出根据一些实施例的实例电路布局的俯视图；
图4B示出根据一些实施例的图4A的实例电路布局的仰视图；
图4C示出根据一些实施例且对应于图4A至图4B的布局的实例电路图；
图5A示出根据一些实施例的实例电路布局的俯视图；
图5B示出根据一些实施例的图5A的实例电路布局的仰视图；
图5C示出根据一些实施例且对应于图5A至图5B的布局的实例电路图。
【符号说明】
100：半导体结构
110：磊晶区
120：通道结构
130：埋入式导电垫
140：栅极结构
150：剖面
160：剖面
170：隔离结构
180：通孔
200：半导体结构
210：磊晶区
220：通道结构
230：埋入式导电垫
240：栅极结构
280：通孔
300：电路布局
301：电源轨
302：接地轨
303：电源轨
320：通道结构
330：埋入式导电垫
340：栅极结构
350：磊晶区
400：电路布局
401：电源轨
402：接地轨
420：通道结构
430：埋入式导电垫
440：栅极结构
450：磊晶区
500：电路布局
501：电源轨
502：接地轨
520：通道结构
530：埋入式导电垫
540：栅极结构
550：磊晶区
A1-A3：输入信号
B1-B2：输入信号
ZN：输出信号
具体实施方式
以下揭示内容提供了用于实现提供的标的的不同特征的许多不同的实施例或实例。以下描述组件、材料、值、步骤、操作、材料、布置等的特定实例用以简化本案的一实施例。当然，该些仅为实例，并不旨在进行限制。可以预期其他组件、值、操作、材料、布置等。例如，在下面的描述中在第二特征上方或之上形成第一特征可包括其中第一及第二特征直接接触形成的实施例，并且亦可包括其中在第一与第二特征之间形成附加特征的实施例，以使得第一及第二特征可以不直接接触。此外，本案的一实施例可以在各个实例中重复元件符号及/或字母。此重复是出于简单及清楚的目的，其本身并不指定所讨论的各种实施例或组态之间的关系。
此外，为了便于描述，本文中可以使用诸如“在...下方”、“在...下”、“下方”、“在...上方”、“上方”之类的空间相对术语，来描述如图中所示的一个元件或特征与另一元件或特征的关系。除了在附图中示出的方位之外，空间相对术语意在涵盖装置在使用或操作中的不同方位。装置可以其他方式定向(旋转90度或以其他方位)，并且在此使用的空间相对描述语亦可被相应地解释。
本揭示内容提供了一种能在集成电路中实现的半导体结构，该半导体结构包括环绕式栅极晶体管结构，该晶体管结构电性耦接至埋入式导电垫，上述埋入式导电垫使用通孔形成于隔离结构内。在隔离结构(例如形成在基板上的浅沟槽隔离结构)内埋入式导电垫的形成，可在设计电路布局时于布线灵活性方面提供优势。
参照图1A示出根据一些实施例的实例半导体结构100的俯视图。半导体结构100通常包括多个环绕式栅极晶体管结构，例如环绕式栅极场效晶体管(gate-all-aroundfield-effect transistor；GAAFET)结构，这些结构有时被称为环绕栅极晶体管(surrounding-gate transistor；SGT)结构，与诸如鳍式场效晶体管(FinFET)结构的一些替代方案相比，环绕式栅极晶体管结构通常可以允许形成更小的晶体管结构，进而能形成更小和更紧凑的集成电路。环绕式栅极晶体管结构形成在隔离结构上，且上述隔离结构形成在基板上。
半导体结构100示出了包括多个磊晶区110。如图1A所示，磊晶区110沿半导体结构100于水平方向(从图1A中所示的顶部)上以均匀或大约均匀间隔的距离形成，磊晶区110各自用以作为一个或多个环绕式栅极的源极或漏极端。磊晶区110通常是可以使用磊晶成长制程所形成的晶体结构，磊晶成长制程例如是化学气相沉积(chemical vapordeposition；CVD)、气相磊晶(vapor-phase epitaxy；VPE)、分子束磊晶(molecular-beamepitaxy；MBE)、液相磊晶(liquid-phase epitaxy；LPE)及其他合适的制程与其组合，磊晶区110可以使用合适的掺杂物掺杂，包括n型和p型掺杂物。
半导体结构100也示出包括多个通道结构120。通道结构120可以使用纳米线或纳米片来实现，例如：每个通道结构120可以使用三个(或更多，或更少)纳米片来实现，上述纳米片使用诸如砷化镓铟(InGaAs)之类的半导体材料形成，其他合适的半导体材料也可用于形成纳米片。同样地，每个通道结构120可以使用三个(或更多，或更少)纳米线来实现，上述纳米线使用半导体材料形成，诸如砷化铟镓以及其他合适的半导体材料。纳米片通常具有更平坦的几何轮廓，而纳米线通常具有更圆的几何轮廓。应当理解的是，除了纳米片和纳米线之外，还可以使用其他合适的结构来实现通道结构120，如图1A的俯视图所示，磊晶区110形成在通道结构120上，通道结构120通常形成在半导体结构100的隔离结构170上，更详细的讨论如下文。
半导体结构100也示出包括多个栅极结构140。举例而言，栅极结构140可以实现为多晶硅或金属栅极结构。每个栅极结构140是环绕每个通道结构120的相应部分形成，以便与相应的磊晶区110一起形成单独的环绕式栅极晶体管结构。栅极结构140可使用各种合适的制程形成，包括化学气相沉积(CVD)和其他合适的制程及其组合。虽然在图1A中没有明确例示，应当理解的是附加层可以在半导体结构100的制造过程中形成，其中附加层包括例如用于电性隔离栅极结构140的间隔物以及其他合适的绝缘层，如图1A所示，栅极结构140通常设置与通道结构120垂直。
半导体结构100也示出包括多个埋入式(或背面)导电垫130(如下文进一步讨论)及两个剖面(剖面150和剖面160)。剖面150是沿栅极结构140的一者于垂直方向(从图1A所示的俯视图)切割，而剖面160是沿埋入式导电垫130的一者于水平方向(从图1A所示的俯视图)切割。埋入式导电垫130通常由导电材料例如铜、铝、钨、钴或其他合适的导电材料及其组合形成，埋入式导电垫130通常可以在半导体结构100内提供电子信号的布线，例如：在半导体结构100的背面上。
参照图1B示出根据一些实施例的半导体结构100的剖面，上述剖面是切割自图1A例示的剖面150。在图1B中的剖面中，可以看到隔离结构170，其可以形成在半导体结构100(未示出)的基板的背面上，上述基板可以原硅基板、硅隔离体上的硅基板、蓝宝石上的硅基板和其他类型的基板来实现。隔离结构170可以浅沟槽隔离(shallow trench isolation；STI)结构或层间介电(interlayer dielectric；ILD)结构来实现，且可以通过在基板内创建沟槽，再用隔离材料(例如介电材料诸如二氧化硅)填充沟槽来形成，并使用化学机械抛光(chemical-mechanical polishing；CMP)等制程去除多余的隔离材料。
图1B中也示出通孔180，通孔180用于将图示的栅极结构140和埋入式导电垫130电性耦接，通孔180可以使用多种不同的材料和结构来实现，例如铜、铝、钨、钴和其他合适的金属材料或其组合。通孔180可以参照图1A的俯视图所示。如图1B例示，通孔180和埋入式导电垫130都形成在隔离结构170内。图1B也例示通道结构120的剖面，其中在图1B的实施例中，通道结构120是使用纳米片实现的。在图1B中可以看出，图中例示的栅极结构140环绕纳米片，以形成环绕式栅极晶体结构。如图1B例示，纳米片是被薄氧化物层包围的硅薄片，然而应当理解的是通道结构120可以多种不同的方式实现。
参照图1C，图1C示出根据一些实施例的半导体结构100的另一剖面，上述剖面是切割自图1A例示的剖面160。在图1C的剖面中，可以看到形成在半导体结构100内的多个不同的通孔180，上述多个通孔180包括第一通孔、第二通孔以及第三通孔，其中第一通孔电性耦接至第一环绕式栅极晶体管结构的栅极端，第二通孔电性耦接至第二环绕式栅极晶体管结构的栅极端，第三通孔电性耦接至第三环绕式栅极晶体管结构的磊晶区(源极端或漏极端)。每个图示的通孔180也电性耦接至图示的埋入式导电垫130。在各种实施例中，栅极结构140各自形成以环绕通道结构120的每一者(如图1B所示)，且磊晶区110各自形成在每个栅极结构140的一侧(如图1A和1C所示)。
参照图2，图2示出根据一些实施例的另一例示半导体结构200的俯视图。半导体结构200与半导体100的相似之处在于它包括多个磊晶区210、多个通道结构220、多个埋入式导电垫230、多个栅极结构240以及多个通孔280，这些结构分别类似于半导体结构100的磊晶区110、通道结构120、埋入式导电垫130、栅极结构140以及通孔180，因此不再重复讨论。然而，如图2例示，埋入式导电垫230可以沿着半导体结构200的隔离结构(类似于上述的隔离结构170)内的两个维度延伸。例如：两个埋入式导电垫230沿通道结构220延伸，其中一个埋入式导电垫230沿着与水平通道结构220及垂直栅极结构240倾斜的方向延伸。特别的是，这种倾斜的埋入式导电垫230可以延伸横跨一个或多个通道结构220的各自投影。
由于通道结构220形成于半导体结构200的隔离结构上而不是在上述隔离结构内，因此可以达到埋入式导电垫230的额外布线灵活性。由于在隔离结构内不存在鳍片(例如鳍式场效晶体管装置的鳍片)，因此可以在隔离结构内的多个方向上形成埋入式导电垫230，而无需担心碰到鳍片。形成于半导体结构200内延伸于两个维度上的埋入式导电垫230有各种可能性，思及其中一些关于例示的电路布局300、400、500如下所述。此外，因为这种布线灵活性，使埋入式导电垫230不会碰到隔离结构内的鳍片或其他障碍物，因此可以实现对于埋入式导电垫230具有减少面积需求的电路布局。
参照图3A，图3A示出根据一些实施例的实例电路布局300的俯视图。电路布局300可以对应于扫瞄式D型正反器(D-flip flop)，或具有扫描输入的D型正反器，为了清楚起见，在图中未示出。电路布局300类似于半导体结构100和半导体结构200，因为电路布局300包括形成于隔离结构上的多个环绕式栅极晶体管结构，以及形成于隔离结构内的多个埋入式导电垫。上述埋入式导电垫可以延伸于两个维度上，从而提供增强的布线灵活性和减少电路布局300的总面积需求的能力。
在图3A中，绘示多个通道结构320和多个栅极结构340，这些结构类似于上文讨论的通道结构120和通道结构220，及栅极结构140和栅极结构240。电路布局300也被示出为包括环绕通道结构320所形成的多个磊晶区350，类似于上文讨论的磊晶区110和磊晶区210。图3A中也示出了多个埋入式导电垫330，上述的多个埋入式导电垫330电性耦接至电路布局300的各种环绕式栅极晶体管结构。埋入式导电垫330类似于上文讨论的埋入式导电垫130和埋入式导电垫230，即形成在基板的背面上，以实现电路布局300。电路布局300提供如本揭示内容所述的二维埋入式导电垫的例示实现方式，透过此种埋入式导电垫的使用，可以减少电路布局300的中心多晶硅间距(与实现鳍式场效晶体管结构的现存布局相比)，而这是因为所揭示的埋入式导电垫可以更灵活地形成于横跨采用GAAFET结构的多个通道结构，或形成于采用GAAFET结构的多个通道结构之间，致使需要的面积更少(例如：减少至少9％)。图3A中也示出第一电源轨301、第二电源轨303和接地轨302。在一些实施例中，此类电源轨形成在基板的背面上。
参照图3B，图3B示出根据一些实施例的电路布局300的仰视图。在图3B中，可以看到通道结构320以及栅极结构340。此外，也可以看到电源轨301、电源轨303和接地轨302沿着埋入式导电垫330。图3B提供了埋入式导电垫330的另一个视图，以说明埋入式导电垫330的二维特性，如在图3B所见，埋入式导电垫330不仅延伸于x维度上，也延伸于y维度上。
参照图4A，图4A示出根据一些实施例的另一例示电路布局400的俯视图。电路布局400可以对应于与或非门(AND-OR-INVERTER)且在图4C中所示并非限制的实例。如图4C所示，与或非门包括多个晶体管，每个晶体管都由输入信号A1、A2、A3和B闸控，并且晶体管共同提供输出信号ZN。在一些实施例中，图4C所示的反相器可以提供以下布林函数：NOT[(A1AND A2)OR(B1 AND B2)]，这种输入/输出信号可以透过多个导电结构提供，其在图4A的俯视图中可更好地理解。电路布局400也类似于半导体结构100和半导体结构200，因为它包括形成于隔离结构上的多个环绕式栅极晶体管结构，以及形成于隔离结构内的多个埋入式导电垫。上述多个埋入式导电垫形成于电路布局400的隔离结构内，从而提供增强的布线灵活性和减少电路布局400的总面积需求的能力。
在图4A中，其绘示多个通道结构420和多个栅极结构440，这些结构类似于上文讨论的通道结构120和通道结构220，以及栅极结构140和栅极结构240。电路布局400也被示出为包括环绕通道结构420形成的多个磊晶区450，类似于上文讨论的磊晶区110和磊晶区210。图4A中也示出了多个埋入式导电垫430，上述多个埋入式导电垫430电性耦接至电路布局400的各种环绕式栅极晶体管结构。埋入式导电垫430类似于上文讨论的埋入式导电垫130和埋入式导电垫230，即形成在基板的背面上，以实现电路布局400。电路布局400提供如本揭示内容所述的埋入式导电垫形成于隔离结构内的例示实现方式。透过此种埋入式导电垫的使用，可以减少电路布局400的中心多晶硅间距(与实现鳍式场效晶体管结构的现存布局相比)，这是因为所揭示的埋入式导电垫可以更灵活地形成于横跨采用GAAFET结构的多个通道结构或形成于采用GAAFET结构的多个通道结构之间，致使需要的面积更少(例如：减少至少10％)。图4A中也示出电源轨401和接地轨402，在一些实施例中，此类电源轨形成于基板的背面上。
参照图4B，图4B示出根据一些实施例的电路布局400的仰视图。在图4B中，可以看到通道结构420以及栅极结构440。此外，也可以看到电源轨401和接地轨402沿着埋入式导电垫430。图4B提供埋入式导电垫430的另一视图，以说明埋入式导电垫430的特性。
参照图5A，图5A示出根据一些实施例的另一例示电路布局500的俯视图。电路布局500可以对应于另一与或非门且在图5C中所示并非限制性的实例。如图5C所示，与或非门包括多个晶体管，每个晶体管由输入信号A1、A2、B1和B2闸控，并且晶体管共同提供输出信号ZN。在一些实施例中，图5C所示的反相器可以提供以下布林函数：NOT[(A1 AND A2 AND A3)OR(B)]，这种输入/输出信号可以透过多个导电结构提供，其在图5A的俯视图中可好地理解。电路布局500类似于半导体结构100和半导体结构200，因为它包括形成于隔离结构上的多个环绕式栅极晶体管结构，以及形成于隔离结构内的埋入式导电垫。上述埋入式导电垫可以延伸于两个维度上，从而提供增强的布线灵活性和减少电路布局500的总面积要求的能力。
在图5A中，其绘示多个通道结构520和多个栅极结构540，这些结构类似于上文讨论的通道结构120和通道结构220，以及栅极结构140和栅极结构240。电路布局500也被示出为包括环绕通道结构520形成的多个磊晶区550，类似于上文讨论的磊晶区110和磊晶区210。图5A中也示出了埋入式导电垫530，上述埋入式导电垫530电性耦接至电路布局500的各种环绕式栅极晶体管结构。埋入式导电垫530类似于上文讨论的埋入式导电垫130和埋入式导电垫230，即形成在基板的背面上，以实现电路布局500。电路布局500提供如本揭示内容所述的二维埋入式导电垫的例示实现方式，透过此种埋入式导电垫的使用，可以减少电路布局500的中心多晶硅间距(与实现鳍式场效晶体管结构的现存布局相比)。这是因为所揭示的埋入式导电垫可以更灵活地形成于横跨采用GAAFET结构的多个通道结构或形成于采用GAAFET结构的多个通道结构之间，致使所需的面积更少。图5A中也示出电源轨501和接地轨502。在一些实施例中，此类电源轨形成于基板的背面上。
参照图5B示出根据一些实施例的电路布局500的仰视图。在图5B中，可以看到通道结构520以及栅极结构540，此外，也可以看到电源轨501和接地轨502沿着埋入式导电垫530。图5B提供了埋入式导电垫530的另一视图，以说明埋入式导电垫530的二维特性，如图5B中所见，埋入式导电垫530不仅延伸于x维度上，也延伸于y维度上。
如上文的详细描述，本揭示内容提供一半导体结构以于集成电路中实现，此半导体结构包括环绕式栅极晶体管结构，上述晶体管结构电性耦接至埋入式导电垫，而上述埋入式导电垫使用通孔形成于隔离结构内。埋入式导电垫于隔离结构(例如形成于基板上的浅沟槽隔离结构)内的形成，可以在设计电路布局时于布线灵活性的方面提供优势。
本揭示内容的一实现方式是半导体结构。此半导体结构包括形成于基板上的隔离结构、形成于隔离结构上的环绕式栅极晶体管结构、通孔及埋入式导电垫。上述通孔电性耦接至环绕式栅极晶体管结构的栅极端，而上述埋入式导电垫形成于隔离结构内并电性耦接至上述通孔。
在一些实施例中，半导体结构中该埋入式导电垫在该隔离结构内延伸于一水平维度和一垂直维度上。
在一些实施例中，半导体结构中该埋入式导电垫在该隔离结构内沿两个维度延伸。
在一些实施例中，半导体结构中该通孔包括一第一通孔，且该环绕式栅极晶体管结构包括一第一环绕式栅极晶体管结构，该半导体结构还包括一第二环绕式栅极晶体管结构和一第二通孔，其中该第二通孔电性耦接至该埋入式导电垫与该第二环绕式栅极晶体管结构的一栅极端。
在一些实施例中，半导体结构中该通孔包括一第一通孔，该半导体结构还包括一第二通孔，该第二通孔电性耦接至该环绕式栅极晶体管结构的一源极端或一漏极端并电性耦接至该埋入式导电垫。
在一些实施例中，半导体结构中该环绕式栅极晶体管结构的该栅极端环绕多个纳米线形成。
在一些实施例中，半导体结构中该环绕式栅极晶体管结构的该栅极端环绕多个纳米片形成。
本揭示内容的另一实现方式是电路。此电路包括形成于基板上的浅沟槽隔离结构、形成于浅沟槽隔离结构上且环绕多条纳米线的栅极结构、电性耦接至栅极结构的通孔、以及埋入式导电垫，上述埋入式导电垫形成于浅沟槽隔离结构内并电性耦接至上述通孔，且在浅沟槽隔离结构内延伸于两个维度上。
在一些实施例中，电路中该栅极结构使用多晶硅材料形成，且该栅极结构是一环绕式栅极晶体管结构的一栅极端。
在一些实施例中，电路中该通孔包括一第一通孔并且该栅极结构包括一第一栅极结构，该电路还包括一第二通孔，该第二通孔电性耦接至该埋入式导电垫与一第二栅极结构。
在一些实施例中，电路中该通孔包括一第一通孔，该电路还包括一第二通孔，该第二通孔电性耦接至一磊晶区与该埋入式导电垫。
在一些实施例中，电路中该埋入式导电垫在该隔离结构内延伸于一水平维度和一垂直维度上。
在一些实施例中，电路中该埋入式导电垫包括一第一部分和一第二部分，该第一部分在该浅沟槽隔离结构内延伸于一个维度上，而该第二部分在该浅沟槽隔离结构内延伸于两个维度上。
在一些实施例中，电路进一步包括一第三通孔，该第三通孔电性耦接至一磊晶区与该埋入式导电垫。
本揭示内容的又一实现方式是另一半导体结构。此半导体结构包括形成于基板上的隔离结构、形成于隔离结构上且环绕多个纳米片的栅极结构、电性耦接至栅极结构的通孔、以及埋入式导电垫，上述埋入式导电垫形成于浅沟槽隔离结构内并电性耦接至上述通孔，且在隔离结构内延伸于水平维度和垂直维度上。
在一些实施例中，半导体结构中该栅极结构使用多晶硅材料形成，且该栅极结构是一环绕式栅极晶体管结构的一栅极端。
在一些实施例中，半导体结构中该通孔包括一第一通孔且该栅极结构包括一第一栅极结构，该电路还包括一第二通孔，该第二通孔电性耦接至该埋入式导电垫与一第二栅极结构。
在一些实施例中，半导体结构进一步包括一第三通孔，该第三通孔电性耦接至一磊晶区与该埋入式导电垫。
在一些实施例中，半导体结构中该通孔包括一第一通孔，半导体结构还包括一第二通孔，该第二通孔电性耦接至一磊晶区与该埋入式导电垫。
在一些实施例中，半导体结构中该通孔包括一第一通孔，半导体结构还包括一第二通孔，该第二通孔电性耦接至该环绕式栅极晶体管结构的的一源极端或一漏极端并电性耦接至该埋入式导电垫。
上文概述了几个实施例的特征，以便本领域技术人员可更好地理解本揭示内容的各层面，本领域技术人员应当理解的是，他们可以容易地使用本揭示内容作为设计或修改其他制程和结构的基础，以实现与本文介绍的实施例相同的目的及/或达到相同的优点。本领域技术人员也应该意识到，这样的等效构造并不脱离本揭示内容的精神和范围，在不脱离本揭示内容的精神和范围的情况下，可以对本文进行各种变化、替换和变更。

Claims (10)

1.一种半导体结构，其特征在于，包括：
一隔离结构，形成于一基板上；
一环绕式栅极晶体管结构，形成于该隔离结构上；
一通孔，电性耦接至环绕式栅极晶体管结构的一栅极端；以及
一埋入式导电垫，形成于该隔离结构内，且该埋入式导电垫电性耦接至该通孔。
2.如权利要求1所述的半导体结构，其特征在于，该埋入式导电垫在该隔离结构内延伸于一水平维度和一垂直维度上。
3.如权利要求1所述的半导体结构，其特征在于，该埋入式导电垫在该隔离结构内沿两个维度延伸。
4.如权利要求1所述的半导体结构，其特征在于，该通孔包括一第一通孔，且该环绕式栅极晶体管结构包括一第一环绕式栅极晶体管结构，该半导体结构还包括一第二环绕式栅极晶体管结构和一第二通孔，其中该第二通孔电性耦接至该埋入式导电垫与该第二环绕式栅极晶体管结构的一栅极端。
5.如权利要求1所述的半导体结构，其特征在于，该通孔包括一第一通孔，该半导体结构还包括一第二通孔，该第二通孔电性耦接至该环绕式栅极晶体管结构的一源极端或一漏极端并电性耦接至该埋入式导电垫。
6.如权利要求1所述的半导体结构，其特征在于，该环绕式栅极晶体管结构的该栅极端环绕多个纳米线形成。
7.如权利要求1所述的半导体结构，其特征在于，该环绕式栅极晶体管结构的该栅极端环绕多个纳米片形成。
8.一种集成电路，其特征在于，包括：
一浅沟槽隔离结构，形成于一基板上；
一栅极结构，形成于该浅沟槽隔离结构上并环绕多个纳米线；
一通孔，电性耦接至该栅极结构；以及
一埋入式导电垫，形成于该浅沟槽隔离结构内并电性耦接至该通孔，该埋入式导电垫在该浅沟槽隔离结构内延伸于两个维度上。
9.如权利要求8所述的集成电路，其特征在于，该栅极结构使用多晶硅材料形成，且该栅极结构是一环绕式栅极晶体管结构的一栅极端。
10.一种半导体结构，其特征在于，包括：
一隔离结构，形成于一基板上；
一栅极结构，形成于该隔离结构上并环绕多个纳米片；
一通孔，电性耦接至该栅极结构；以及
一埋入式导电垫，形成于浅沟槽的该隔离结构内并电性耦接至该通孔，该埋入式导电垫在该隔离结构内延伸于一水平维度和一垂直维度上。
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