WO2023048281A1 - Procédé de traitement au plasma et système de traitement au plasma - Google Patents

Procédé de traitement au plasma et système de traitement au plasma Download PDF

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Publication number
WO2023048281A1
WO2023048281A1 PCT/JP2022/035685 JP2022035685W WO2023048281A1 WO 2023048281 A1 WO2023048281 A1 WO 2023048281A1 JP 2022035685 W JP2022035685 W JP 2022035685W WO 2023048281 A1 WO2023048281 A1 WO 2023048281A1
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signal
power level
plasma processing
bias
chamber
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PCT/JP2022/035685
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English (en)
Japanese (ja)
Inventor
宰永 朴
優一 藤澤
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東京エレクトロン株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00—Generating plasma; Handling plasma
    • H05H1/24—Generating plasma
    • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy

Definitions

  • Exemplary embodiments of the present disclosure relate to plasma processing methods and plasma processing systems.
  • Patent Document 1 discloses a method of etching a silicon-containing film.
  • the present disclosure provides a technique for controlling the shape of recesses formed by etching.
  • the RF signal includes alternating first time periods having a first power level and second time periods having a second power level lower than the first power level.
  • a plasma processing method is provided in which the second power level is reduced with respect to the first power level as the etching progresses in step (c).
  • the shape of recesses formed by etching can be controlled.
  • FIG. 1 schematically shows a plasma processing system 1;
  • FIG. It is a flow chart which shows an example of this processing method. It is a figure which shows typically an example of the cross-sectional structure of the board
  • FIG. 4 is a diagram schematically showing an example of a cross-sectional structure of a substrate W after being processed in steps ST3A to ST3F; 4 is a timing chart showing an example of a source RF signal in steps ST3A to ST3F; 4 is a timing chart showing an example of bias RF signals in steps ST3A to ST3F; 4 is a timing chart showing an example of bias DC signals in steps ST3A to ST3F;
  • the bias signal is a pulse wave containing alternating two periods of different power or voltage levels.
  • the bias signal is a continuous wave.
  • a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber and (b) processing within the chamber.
  • the signal is a pulse wave comprising alternating third periods having a third power or voltage level and fourth periods having a fourth power or voltage level lower than the third power or voltage level.
  • a plasma processing method is provided in which the fourth power or voltage level with respect to the third power or voltage level is increased as the etching progresses.
  • the RF signal is a pulsed wave containing alternating periods of two different power levels.
  • the RF signal is continuous wave.
  • an RF signal is used as the bias signal.
  • a DC signal is used as the bias signal.
  • a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber and (b) processing within the chamber.
  • processing within the chamber supplying a source RF signal to generate a plasma of the process gas in the chamber and supplying a bias RF signal to the substrate support to etch the substrate.
  • the source RF signal is a pulsed wave comprising alternating first durations having a first power level and second durations having a second power level lower than the first power level;
  • the signal is a pulse wave comprising alternating third periods having a third power level and fourth periods having a fourth power level lower than the third power level; (c1) decreasing the second power level relative to the first power level as the etch progresses; and (c2) increasing the fourth power level relative to the third power level as the etch progresses.
  • step (c1) holds the fourth power level constant relative to the third power level
  • step (c2) holds the second power level constant relative to the first power level
  • step (c2) is performed after step (c1) is performed.
  • step (c2) is performed after the etching time or etching depth exceeds a given time or depth in step (c).
  • step (c) the pressure in the chamber is lowered as the etching progresses.
  • the process gas comprises CxFy gas (x, y are positive integers ) or CsHtFu gas ( s , t, u are positive integers).
  • the recesses formed by the step (c) have an aspect ratio of 100 or more.
  • the duty ratio of the pulse wave of the source RF signal and/or the duty ratio of the pulse wave of the bias RF signal is 20% or more and 80% or less.
  • the silicon-containing film is a laminated film of a silicon oxide film and a silicon nitride film.
  • the film stack is included in a 3D-NAND structure.
  • the mask film is an amorphous carbon film.
  • a chamber a substrate support disposed within the chamber and configured to support a substrate having a silicon-containing film and a mask film formed on the silicon-containing film; and a power supply that produces a source RF signal and a bias RF signal, the source RF signal having a first power level for a first period of time and a first a pulse wave comprising alternating second periods having a second power level less than one power level, wherein the bias RF signal has third periods having a third power level and a third power level; a power supply, which is a pulsed wave comprising alternating fourth periods having a fourth power level lower than the power level; a controller configured to provide a bias RF signal from to the substrate support to control etching of the substrate, the controller controlling the first power level as the etching progresses.
  • a plasma processing system is provided that performs controlled decrease of the second power level and controlled increase of the fourth power level with respect to the third power level as etching progresses.
  • a capacitively coupled plasma processing apparatus is included.
  • the source RF signal is provided to the substrate support.
  • FIG. 1 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.
  • the plasma processing system includes a capacitively coupled plasma processing apparatus 1 and a controller 2.
  • a capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10 , a gas supply section 20 , a power supply 30 and an exhaust system 40 . Further, the plasma processing apparatus 1 includes a substrate support section 11 and a gas introduction section.
  • the gas introduction is configured to introduce at least one process gas into the plasma processing chamber 10 .
  • the gas introduction section includes a showerhead 13 .
  • a substrate support 11 is positioned within the plasma processing chamber 10 .
  • the showerhead 13 is arranged above the substrate support 11 . In one embodiment, showerhead 13 forms at least a portion of the ceiling of plasma processing chamber 10 .
  • the plasma processing chamber 10 has a plasma processing space 10 s defined by a showerhead 13 , side walls 10 a of the plasma processing chamber 10 and a substrate support 11 .
  • the plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space 10s and at least one gas exhaust port for exhausting gas from the plasma processing space.
  • Plasma processing chamber 10 is grounded.
  • the showerhead 13 and substrate support 11 are electrically insulated from the plasma processing chamber 10 housing.
  • the substrate support section 11 includes a body section 111 and a ring assembly 112 .
  • the body portion 111 has a central region 111 a for supporting the substrate W and an annular region 111 b for supporting the ring assembly 112 .
  • a wafer is an example of a substrate W;
  • the annular region 111b of the body portion 111 surrounds the central region 111a of the body portion 111 in plan view.
  • the substrate W is arranged on the central region 111 a of the main body 111
  • the ring assembly 112 is arranged on the annular region 111 b of the main body 111 so as to surround the substrate W on the central region 111 a of the main body 111 .
  • the central region 111a is also referred to as a substrate support surface for supporting the substrate W
  • the annular region 111b is also referred to as a ring support surface for supporting the edge ring assembly 112.
  • the body portion 111 includes a base 1110 and an electrostatic chuck 1111 .
  • Base 1110 includes a conductive member.
  • a conductive member of the base 1110 can function as a bottom electrode.
  • An electrostatic chuck 1111 is arranged on the base 1110 .
  • the electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a.
  • Ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have the annular region 111b.
  • the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or may be placed on both the electrostatic chuck 1111 and the annular insulating member.
  • An RF or DC electrode may also be placed within the ceramic member 1111a, in which case the RF or DC electrode serves as the bottom electrode.
  • An RF or DC electrode is also referred to as a bias electrode when a bias RF signal or DC signal, described below, is connected to the RF or DC electrode. Note that both the conductive member of the base 1110 and the RF or DC electrode may function as the two bottom electrodes.
  • Ring assembly 112 includes one or more annular members.
  • the one or more annular members include one or more edge rings and at least one cover ring.
  • the edge ring is made of a conductive material or an insulating material
  • the cover ring is made of an insulating material.
  • the substrate supporter 11 may include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature.
  • the temperature control module may include heaters, heat transfer media, channels 1110a, or combinations thereof.
  • channels 1110a are formed in base 1110 and one or more heaters are located in ceramic member 1111a of electrostatic chuck 1111.
  • the substrate supporter 11 may include a heat transfer gas supply unit configured to supply a heat transfer gas between the back surface of the substrate W and the central region 111a.
  • the showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s.
  • the showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas introduction ports 13c.
  • the processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s through a plurality of gas introduction ports 13c.
  • showerhead 13 also includes an upper electrode.
  • the gas introduction part may include one or more side gas injectors (SGI: Side Gas Injector) attached to one or more openings formed in the side wall 10a.
  • SGI Side Gas Injector
  • the gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22 .
  • gas supply 20 is configured to supply at least one process gas from respective gas sources 21 through respective flow controllers 22 to showerhead 13 .
  • Each flow controller 22 may include, for example, a mass flow controller or a pressure controlled flow controller.
  • gas supply 20 may include one or more flow modulation devices that modulate or pulse the flow of at least one process gas.
  • Power supply 30 includes an RF power supply 31 coupled to plasma processing chamber 10 via at least one impedance matching circuit.
  • RF power supply 31 is configured to supply at least one RF signal (RF power), such as a source RF signal and a bias RF signal, to at least one bottom electrode and/or at least one top electrode.
  • RF power source 31 may function as at least part of a plasma generator configured to generate a plasma from one or more process gases in plasma processing chamber 10 .
  • a bias RF signal to at least one lower electrode, a bias potential is generated in the substrate W, and ion components in the formed plasma can be drawn into the substrate W.
  • the RF power supply 31 includes a first RF generator 31a and a second RF generator 31b.
  • the first RF generator 31a is coupled to at least one lower electrode and/or at least one upper electrode via at least one impedance matching circuit to generate a source RF signal (source RF power) for plasma generation.
  • the source RF signal has a frequency within the range of 10 MHz to 150 MHz.
  • the first RF generator 31a may be configured to generate multiple source RF signals having different frequencies.
  • One or more source RF signals generated are provided to at least one bottom electrode and/or at least one top electrode.
  • the second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and configured to generate a bias RF signal (bias RF power).
  • the frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal.
  • the bias RF signal has a frequency lower than the frequency of the source RF signal.
  • the bias RF signal has a frequency within the range of 100 kHz to 60 MHz.
  • the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies.
  • One or more bias RF signals generated are provided to at least one bottom electrode. Also, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.
  • Power supply 30 may also include a DC power supply 32 coupled to plasma processing chamber 10 .
  • the DC power supply 32 includes a first DC generator 32a and a second DC generator 32b.
  • the first DC generator 32a is connected to the at least one bottom electrode and configured to generate a first DC signal.
  • a generated first bias DC signal is applied to at least one bottom electrode.
  • the second DC generator 32b is connected to the at least one top electrode and configured to generate a second DC signal. The generated second DC signal is applied to at least one top electrode.
  • At least one of the first and second DC signals may be pulsed.
  • a sequence of DC-based voltage pulses is applied to at least one bottom electrode and/or at least one top electrode.
  • the voltage pulses may have rectangular, trapezoidal, triangular, or combinations thereof pulse waveforms.
  • a waveform generator for generating a sequence of voltage pulses from a DC signal is connected between the first DC generator 32a and the at least one bottom electrode. Therefore, the first DC generator 32a and the waveform generator constitute a voltage pulse generator.
  • the voltage pulse generator is connected to at least one upper electrode.
  • the voltage pulse may have a positive polarity or a negative polarity.
  • the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses in one cycle.
  • the first and second DC generators 32a and 32b may be provided in addition to the RF power supply 31, and the first DC generator 32a may be provided instead of the second RF generator 31b. good.
  • the exhaust system 40 may be connected to a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10, for example.
  • Exhaust system 40 may include a pressure regulating valve and a vacuum pump.
  • the pressure regulating valve regulates the pressure in the plasma processing space 10s.
  • Vacuum pumps may include turbomolecular pumps, dry pumps, or combinations thereof.
  • the controller 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various steps described in this disclosure. Controller 2 may be configured to control elements of plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the controller 2 may be included in the plasma processing apparatus 1 .
  • the control unit 2 may include, for example, a computer 2a.
  • the computer 2a may include, for example, a processing unit (CPU: Central Processing Unit) 2a1, a storage unit 2a2, and a communication interface 2a3.
  • Processing unit 2a1 can be configured to perform various control operations by reading a program from storage unit 2a2 and executing the read program. This program may be stored in the storage unit 2a2 in advance, or may be acquired via a medium when necessary.
  • the acquired program is stored in the storage unit 2a2, read from the storage unit 2a2 and executed by the processing unit 2a1.
  • the medium may be various storage media readable by the computer 2a, or may be a communication line connected to the communication interface 2a3.
  • the storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof.
  • the communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).
  • FIG. 2 is a flow chart showing a plasma processing method (hereinafter also referred to as "this processing method") according to one exemplary embodiment.
  • this processing method includes a step ST1 of providing a substrate, a step ST2 of supplying a processing gas, and a step ST3 of etching the substrate.
  • the step ST3 of etching the substrate includes a step ST3A of etching the first region, a step ST3B of etching the second region, a step ST3C of etching the third region, a step ST3D of etching the fourth region, and a step ST3D of etching the fifth region.
  • ST3E including step ST6F of etching the sixth region.
  • the processing in each step may be performed by the plasma processing system shown in FIG.
  • An example in which the control unit 2 controls each unit of the plasma processing apparatus 1 to perform the present processing method on the substrate W will be described below.
  • step ST ⁇ b>1 the substrate W is provided within the plasma processing space 10 s of the plasma processing apparatus 1 .
  • the substrate W is placed on the upper surface of the substrate support portion 11 .
  • FIG. 3 is a diagram showing an example of the cross-sectional structure of the substrate W provided in step ST1.
  • a silicon-containing film SF and a mask film MF are formed in this order on a base film UF.
  • the substrate W may be used, for example, in the manufacture of semiconductor devices including semiconductor memory devices such as DRAMs, 3D-NAND flash memories and the like.
  • the base film UF may be, for example, a silicon wafer or an organic film, dielectric film, metal film, semiconductor film, or the like formed on a silicon wafer.
  • the base film UF may be configured by laminating a plurality of films.
  • the silicon-containing film SF is a film to be etched in this processing method.
  • the silicon-containing film SF may be, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.
  • the silicon-containing film SF may be configured by laminating a plurality of films.
  • the silicon-containing film SF may be configured by alternately stacking a silicon oxide film and a polycrystalline silicon film.
  • the silicon-containing film SF may be configured by alternately stacking a silicon oxide film and a silicon nitride film.
  • the mask film MF may be, for example, a carbon-containing film such as an amorphous carbon film, a spin-on carbon film, or a photoresist film.
  • the mask film MF may be a single layer mask consisting of one layer or a multilayer mask consisting of two or more layers.
  • Mask film MF has at least one opening OP.
  • the opening OP may have any shape when the substrate W is viewed from above, that is, when the substrate W is viewed from the top to the bottom in FIG.
  • the shape may be, for example, a circle, an ellipse, a rectangle, a line, or a combination of one or more of these.
  • the mask film MF may have multiple openings OP.
  • a processing gas is supplied into the plasma processing space 10s.
  • the processing gas is a gas used for etching the silicon-containing film SF formed on the substrate W.
  • the type of processing gas may be appropriately selected based on the material of the silicon-containing film SF, the material of the mask film MF, the material of the base film UF, the pattern of the mask film MF, the depth of etching, and the like.
  • the processing gas may include, for example , one or both of CxFy gas and CsHtFu gas .
  • the CxFy gas may be at least one selected from the group consisting of C4F6 gas, C4F8 gas, C3F6 gas and C7F8 gas .
  • the CsHtFu gas may be CH2F2 gas or CH3F gas .
  • the process gas may include a hydrogen-containing gas such as H2 gas or CH4 gas.
  • Step ST3 Etching
  • a source RF signal (RF power) is supplied from the first RF generator 31a to the lower electrode and/or the upper electrode.
  • a bias RF signal is supplied to the lower electrode from the second RF generator 31b.
  • plasma is generated from the processing gas supplied to the plasma processing space 10s, and a bias potential is generated on the substrate W as well.
  • Active species such as ions and radicals in the generated plasma are attracted to the substrate W, and the silicon-containing film SF is etched.
  • the timing to start supplying the source RF signal and the timing to start supplying the bias RF signal may be the same or different.
  • steps ST3A to ST3F of step ST3 the power levels of the source RF signal and the bias RF signal are changed as the etching of the silicon-containing film SF progresses. This point will be described with reference to FIGS. 4A to 4F, 5A to 5F, and 6A to 6F.
  • the progress of etching may be determined based on the elongation of the etching depth or the lapse of etching time.
  • 4A to 4F are diagrams showing examples of cross-sectional structures of the substrate W after being processed in steps ST3A to ST3F, respectively.
  • 5A to 5F are timing charts showing examples of source RF signals in steps ST3A to ST3F, respectively.
  • the horizontal axis indicates time.
  • the vertical axis indicates the effective value of the power level of the source RF signal.
  • “L 11 ”, “L 12 ”, “L 13 ”, and “L 14 ” indicate power levels lower than those indicated by “H 1 ”.
  • L 11 >L 12 >L 13 > L 14 holds between L 11 , L 12 , L 13 and L 14 (that is, L 11 has the highest power level and L 14 has the lowest power level).
  • “L 14 ” includes when the power level is 0 W, ie no signal is applied. As shown in FIGS.
  • the source RF signal has a H1 period (first period) with a power level of H 1 (first power) and L 11 , L 12 , L lower than H 1 .
  • 6A to 6F are timing charts showing examples of bias RF signals in steps ST3A to ST3F, respectively.
  • the horizontal axis indicates time.
  • the vertical axis indicates the effective value of the power level of the bias RF signal.
  • “L 21 ”, “L 22 ”, and “L 23 ” indicate lower power levels than indicated by “H 2 ”.
  • L 21 , L 22 and L 23 have the relationship of L 21 ⁇ L 22 ⁇ L 23 (that is, among L 21 , L 22 and L 23 , L 21 has the lowest power level and L 23 highest power level).
  • “L 21 ” includes when the power level is 0 W, ie no signal is being supplied.
  • the bias RF signal has an H2 period (third period) having a power level of H2 (third power) and a power level of L21 , L22 or L23 lower than H2 (fourth power). It is a pulse wave that alternately includes an L2 period (fourth period).
  • Step ST3A Etching of First Region
  • the step ST3A is performed in the first region from the start of etching until the etching depth of the recess RC formed by etching reaches d1 (see FIG. 4A).
  • the recess RC is a portion of the silicon-containing film SF corresponding to the opening OP of the mask film MF.
  • a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L11 lower than H1 is used as the source RF signal (see FIG. 5A).
  • the bias RF signal a pulse wave that alternately includes H2 periods having a power level of H2 and L2 periods having a power level L21 lower than H2 is used (see FIG. 6A).
  • Step ST3B Etching of Second Region
  • the step ST3B is performed in the second region until the etching depth of the recess RC reaches d2 (see FIG. 4B).
  • the etching depth d2 is deeper than the etching depth d1, and the relationship of d2>d1 holds.
  • a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L12 lower than H1 is used as the source RF signal (see FIG. 5B).
  • the power level L12 of the source RF signal of step ST3B is lower than the power level L11 of the source RF signal of step ST3A.
  • the same pulse wave as in step ST3A is used (see FIG. 6B).
  • Step ST3C etching of the third region
  • the step ST3C is performed in the third region until the etching depth of the recess RC reaches d3 (see FIG. 4C).
  • the etching depth d3 is deeper than the etching depth d2, and the relationship of d3>d2 holds.
  • the etching depth d3 may be, for example, half the depth to be etched in step ST3.
  • the etching depth d3 may be half the thickness of the silicon-containing film SF.
  • a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L13 lower than H1 is used as the source RF signal (see FIG. 5C).
  • the power level L13 of the source RF signal of step ST3C is lower than the power level L12 of the source RF signal of step ST3B.
  • the bias RF signal the same pulse wave as in steps ST3A and ST3B is used (see FIG. 6C).
  • Step ST3D Etching of fourth region
  • the step ST3D is performed in the fourth region until the etching depth of the recess RC reaches d4 (see FIG. 4D).
  • the etching depth d4 is deeper than the etching depth d3, and the relationship of d4>d3 holds.
  • a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L14 lower than H1 is used as the source RF signal (see FIG. 5D).
  • the power level L14 of the source RF signal of step ST3D is lower than the power level L13 of the source RF signal of step ST3C.
  • the bias RF signal the same pulse wave as in steps ST3A to ST3C is used (see FIG. 6D).
  • Step ST3E Etching of fifth region
  • the step ST3E is performed in the fifth region until the etching depth of the recess RC reaches d5 (see FIG. 4E).
  • the etching depth d5 is deeper than the etching depth d4, and the relationship of d2>d1 holds.
  • the same pulse wave as in step ST3D is used as the source RF signal (see FIG. 5E).
  • the bias RF signal a pulse wave containing alternating H2 periods with a power level of H2 and L2 periods with a power level L22 lower than H2 is used (see FIG. 6E).
  • the power level L22 of the bias RF signal in step ST3E is higher than the power level L21 of the bias RF signal in steps ST3A to ST3D.
  • Step ST3F Etching of sixth region
  • the step ST3F is performed in the sixth region until the etching depth of the recess RC reaches d6 (see FIG. 4F).
  • the etching depth d6 is deeper than the etching depth d5, and the relationship of d6>d5 holds.
  • the etching depth d6 is, for example, the film thickness of the silicon-containing film SF.
  • the step ST3F is performed until the bottom of the recess RC reaches the underlying film UF.
  • the aspect ratio of the recess RC in this state may be, for example, 20 or more, 30 or more, 40 or more, 50 or more, or 100 or more.
  • step ST3F the same pulse wave as in steps ST3D and ST3E is used as the source RF signal (see FIG. 5F).
  • the bias RF signal a pulse wave containing alternating H2 periods with a power level of H2 and L2 periods with a power level L23 lower than H2 is used (see FIG. 6E).
  • the power level L23 of the bias RF signal in step ST3F is higher than the power level L22 of the bias RF signal in step ST3E.
  • the duty ratio of the pulse wave of the source RF signal that is, the ratio of the H1 period to the H1 period and the L1 period may be 20% or more and 80% or less.
  • the duty ratio of the pulse wave of the bias RF signal that is, the ratio of the H2 period to the H2 period and the L2 period may be 20% or more and 80% or less.
  • the H1 period of the source RF signal may or may not be synchronous with the H2 period of the bias RF signal.
  • the time length of the H1 period of the source RF signal may be the same as or different from the time length of the H2 period of the bias RF signal. Part or all of the H1 period of the source RF signal may overlap with the H2 period of the bias RF signal.
  • step ST3 the power level of the source RF signal during the L1 period with respect to the power level H1 during the H1 period may decrease stepwise from step ST3A to step ST3D and become lowest in step ST3D to step 3F (FIG. 5A). (see FIG. 5F).
  • step ST3D to 3F high-density plasma is generated in this order in steps ST3A to ST3C, ie, in the etching of the shallower region of the recess RC.
  • steps ST3D to 3F that is, in the etching of the region where the recess RC is deeper, plasma with a lower density than in steps ST3A to ST3C is generated.
  • step ST3 the power level of the bias RF signal during the L2 period with respect to the power level H2 during the H2 period may be the lowest in steps ST3A to ST3D and increase stepwise from step ST3D to step ST3F (FIG. 6A). (see FIG. 6F).
  • a lower bias potential is applied to the substrate W in steps ST3A to ST3D, ie, the etching of the region where the recess RC is shallower than in the steps ST3E to ST3F, ie, the etching of the region where the recess RC is deeper. occur.
  • a higher bias potential is generated on the substrate W in step ST3F than in step ST3E.
  • step ST3 while the power level of the source RF signal during the L1 period is gradually decreased, that is, in steps ST3A to ST3D, the power level of the bias RF signal during the L2 period may be kept constant. Further, while the power level of the bias RF signal during the L2 period is increased stepwise, that is, in steps ST3D to ST3F, the power level of the source RF signal during the L1 period may be kept constant.
  • the shallower portion of the recess RC can be etched with a higher density plasma and a lower bias potential.
  • High - density plasma accelerates the dissociation of CxFy gas and/or CsHtFu gas in the process gas, making it easier to generate molecules with higher adsorption coefficients. Therefore, the amount of reaction products adhering to the mask film MF and the sidewalls of the recess RC may increase.
  • the high-density plasma reduces the flow of ions toward the substrate W, and the low bias potential reduces sputtering on the mask film MF and sidewalls of the recess RC.
  • This protective film can protect the side walls of the recess RC in etching after step ST3 (including etching in a region where the depth of the recess RC is deeper). Therefore, bowing in which the width of the opening of the recess RC is partially widened can be suppressed.
  • the deep region of the recess RC can be etched with a lower density plasma and a higher bias potential.
  • dissociation of CxFy gas and/or CsHtFu gas in the processing gas is difficult to promote, and molecules with high adsorption coefficients are difficult to generate . Therefore, the amount of reaction products adhering to the mask film MF and the sidewalls of the recesses RC can be reduced. As a result, narrowing of the openings of the mask film MF and the recesses RC can be suppressed, and changes in the incident angle of the ions entering the recesses RC can be suppressed.
  • the high density plasma may increase the flow of ions toward the bottom of the recess RC. Furthermore, since etching is performed at a high bias potential, the incident angle of ions entering the recess RC can be closer to the vertical. As described above, it is possible to prevent the bottom width (bottom CD) of the recess RC from being narrowed at a portion where the depth of the recess RC is deep.
  • step ST3 the power level of the source RF signal during the L1 period may be decreased in stages, and then the power level of the bias RF signal during the L2 period may be increased in stages.
  • the power level of the source RF signal during the L1 period may be kept constant, and only the power level of the bias RF signal during the L2 period may be increased stepwise.
  • only the power level of the source RF signal during the L1 period may be stepwise decreased while the power level of the bias RF signal during the L2 period may be kept constant.
  • the pulse wave of the source RF signal and the pulse wave of the bias RF signal may be used.
  • either the source RF signal or the bias RF signal may be continuous waves with no H1, L1, etc. periods.
  • a continuous wave source RF signal and a pulsed bias RF signal may be used.
  • the power level of the continuous wave of the source RF signal may be stepwise decreased
  • steps ST3D to ST3F the power level of the L2 period of the bias RF signal may be stepwise increased.
  • a pulsed source RF signal and a continuous biased RF signal may be used.
  • steps ST3A to ST3D the power level of the L1 period of the source RF signal may be stepwise decreased, and in steps ST3E to ST3F, the power level of the continuous wave of the bias RF signal may be stepwise increased. .
  • a bias RF signal may be used as the bias signal (power) supplied to the lower electrode.
  • a negative DC voltage may be supplied to the lower electrode as a bias DC signal from the first DC generator 32a.
  • the voltage level of the bias DC signal is the effective value of the absolute value of the negative DC voltage.
  • the bias DC signal may be pulsed or continuous wave.
  • the bias DC signal has a sequence of negative voltage pulses during H3.
  • the sequence of negative voltage pulses has, for example, a pulse frequency in the range of 100 kHz to 500 kHz.
  • the negative voltage pulse has a voltage level of V 1 (FIGS. 7A-7D), a voltage level of V 2 (FIG. 7E) or a voltage level of V 3 (FIG. 7F).
  • the waveform of the negative voltage pulse may have a rectangular, trapezoidal, triangular, or combination waveform.
  • V 1 , V 2 , and V 3 show negative values smaller than 0, and the relationship
  • the bias DC signal is a pulse wave containing alternating H3 periods with power levels of V 1 , V 2 or V 3 and L3 periods in which no bias DC signal is provided (voltage level is 0).
  • the bias DC signal may have a sequence of negative voltage pulses during the L3 period. In this case, the voltage level of the voltage of the negative voltage pulse is lower than the voltage level of the negative voltage pulse during the H3 period.
  • bias DC signal shown in FIGS. 7A to 7F is used, as in the case of using the bias RF signal shown in FIGS.
  • a lower bias potential is developed on the substrate W.
  • a higher bias potential is generated on the substrate W in step ST3F than in step ST3E.
  • step ST3 six regions may be provided in which etching is performed by changing the power levels of the source RF signal and the bias RF signal, depending on the depth of the recess RC.
  • the thickness of the silicon-containing film SF is divided into an upper region where the upper half of the thickness is etched and a lower region where the lower half is etched, and the power levels of the source RF signal and the bias RF signal are changed in the upper region and the lower region.
  • the area may be set according to the etching time instead of the etching depth (the depth of the recess RC).
  • step ST3 the pressure inside the plasma processing chamber 10 may be decreased as the etching progresses.
  • a higher density plasma can be generated at a portion where the recess RC is shallower, and a lower density plasma can be generated at a portion where the recess RC is deeper.
  • Etching progress may be determined based on the elongation of the etching depth or the elapse of the etching time.
  • this processing method was applied to the substrate W shown in FIG. 3, and the silicon-containing film SF was etched with a processing gas containing C 4 F 8 gas.
  • the silicon-containing film SF of the substrate W is a laminated film of a silicon oxide film and a silicon nitride film
  • the mask film MF is an amorphous carbon film.
  • the opening pattern of the mask film MF is a hole pattern.
  • the silicon-containing film SF is divided into six regions (referred to as "first region”, "second region”, etc. in order from the top), and in each region, the pulse wave of the source RF signal and the bias RF signal Etching was performed by changing the power level of the pulse wave.
  • the etching time for each region was 300 seconds.
  • Example 1 the power level of the source RF signal was stepped down during the L1 period, and then the power level of the bias RF signal was stepped up during the L2 period.
  • the power level H1 of the source RF signal during the H1 period was 7500 [W] in the first to sixth regions.
  • the power level of the source RF signal during the L1 period was 400 [W] in the first region, 200 [W] in the second region, and 0 [W] in the third to sixth regions.
  • the power level of the bias RF signal during the H2 period was 12000 [W] in all of the first to sixth regions.
  • the power level of the bias RF signal during the L2 period was 0 [W] in the first to fourth regions, 200 [W] in the fifth region, and 700 [W] in the sixth region.
  • Example 2 only the power level of the source RF signal during the L1 period was stepped down, while the power level of the bias RF signal during the L2 period was kept constant.
  • the power level H1 of the source RF signal during the H1 period was 7500 [W] in the first to sixth regions.
  • the power level of the source RF signal during the L1 period is 500 [W] in the first region, 300 [W] in the second region, 100 [W] in the third region, and 0 [W] in the fourth to sixth regions.
  • Met The power level of the bias RF signal during the H2 period was 12000 [W] in all of the first to sixth regions.
  • the power level of the bias RF signal during the L2 period was 0 [W] in all of the first to sixth regions.
  • Example 3 the power level of the source RF signal during the L1 period was kept constant, and only the power level of the bias RF signal during the L2 period was increased stepwise. Specifically, the power level H1 of the H1 period of the source RF signal was 7500 [W] in all of the first to sixth regions. The power level of the source RF signal during the L1 period was 0 [W] in the first to sixth regions. The power level of the bias RF signal during the H2 period was 12000 [W] in all of the first to sixth regions. The power level of the bias RF signal during the L2 period was 0 [W] in the first to fourth regions, 200 [W] in the fifth region, and 700 [W] in the sixth region.
  • the silicon-containing film SF of the substrate W having the same configuration and hole pattern as those of the substrate W in the example was etched with a processing gas containing a C 4 F 8 gas.
  • etching was continuously performed for 1800 seconds without changing the power level of the pulse wave of the source RF signal and the pulse wave of the bias RF signal.
  • the power level of the source RF signal during the H1 period was 7500 [W].
  • the power level of the source RF signal during the L1 period was 0 [W].
  • the power level of the bias RF signal during the H2 period was 12000 [W].
  • the power level of the bias RF signal during the L2 period was 0 [W].
  • Table 1 shows various measurement results for each example and reference example.
  • D is the etching depth of the silicon-containing film SF after processing.
  • B W is the maximum opening width (Boeing CD) of the recess RC.
  • B t is the width (bottom CD) of the bottom of the recess RC.
  • B W ⁇ B t is the difference between Boeing CD and Bottom CD.
  • the difference between the Boeing CD and the bottom CD in the example was improved compared to the reference example. That is, in the example, it was possible to expand the bottom width of the recess RC while suppressing bowing due to etching.
  • this processing method may be performed using a plasma processing apparatus using an arbitrary plasma source, such as inductively coupled plasma or microwave plasma, other than the capacitively coupled plasma processing apparatus 1 .
  • Plasma processing apparatus Control unit 10 Plasma processing chamber 10s Plasma processing space 11 Substrate support 13 shower head 20 Gas supply unit 31a First RF generator 31b Second RF generator 32a First DC generator MF Mask film OP Opening SF Silicon-containing film RC Recess UF Bottom base film, W... substrate

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Abstract

L'invention concerne une technologie qui régule la forme d'une section évidée formée par gravure. Le procédé de traitement au plasma selon l'invention comprend : (a) une étape dans laquelle un substrat comportant un film comprenant du silicium et un film de masquage formé sur le film comprenant du silicium est disposé sur une partie support de substrat dans une chambre ; (b) une étape dans laquelle un gaz de traitement est introduit dans la chambre ; et (c) une étape dans laquelle un signal RF est fourni et le plasma du gaz de traitement est généré dans la chambre, tandis qu'un signal de polarisation est fourni à la partie support de substrat, et le substrat est gravé. Le signal RF est une onde pulsée qui comprend, de manière alternée, des premières périodes présentant un premier niveau de puissance et des secondes périodes présentant un second niveau de puissance inférieur au premier niveau de puissance. Pendant l'étape (c), le second niveau de puissance est réduit par rapport au premier niveau de puissance pendant le déroulement de la gravure.
PCT/JP2022/035685 2021-09-27 2022-09-26 Procédé de traitement au plasma et système de traitement au plasma WO2023048281A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014204050A (ja) * 2013-04-09 2014-10-27 株式会社日立ハイテクノロジーズ プラズマ処理方法およびプラズマ処理装置
US20140363975A1 (en) * 2011-12-19 2014-12-11 Beijing Nmc Co., Ltd. Substrate etching method and substrate processing device
US20180053661A1 (en) * 2016-08-17 2018-02-22 Samsung Electronics Co. Ltd. Plasma etching apparatus and method of manufacturing a semiconductor device using the same
WO2020163100A1 (fr) * 2019-02-08 2020-08-13 Applied Materials, Inc. Procédés et appareil de gravure de structures semi-conductrices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140363975A1 (en) * 2011-12-19 2014-12-11 Beijing Nmc Co., Ltd. Substrate etching method and substrate processing device
JP2014204050A (ja) * 2013-04-09 2014-10-27 株式会社日立ハイテクノロジーズ プラズマ処理方法およびプラズマ処理装置
US20180053661A1 (en) * 2016-08-17 2018-02-22 Samsung Electronics Co. Ltd. Plasma etching apparatus and method of manufacturing a semiconductor device using the same
WO2020163100A1 (fr) * 2019-02-08 2020-08-13 Applied Materials, Inc. Procédés et appareil de gravure de structures semi-conductrices

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