WO2023048281A1 - Plasma processing method and plasma processing system - Google Patents

Plasma processing method and plasma processing system Download PDF

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Publication number
WO2023048281A1
WO2023048281A1 PCT/JP2022/035685 JP2022035685W WO2023048281A1 WO 2023048281 A1 WO2023048281 A1 WO 2023048281A1 JP 2022035685 W JP2022035685 W JP 2022035685W WO 2023048281 A1 WO2023048281 A1 WO 2023048281A1
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Prior art keywords
signal
power level
plasma processing
bias
chamber
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PCT/JP2022/035685
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French (fr)
Japanese (ja)
Inventor
宰永 朴
優一 藤澤
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東京エレクトロン株式会社
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Publication of WO2023048281A1 publication Critical patent/WO2023048281A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00—Generating plasma; Handling plasma
    • H05H1/24—Generating plasma
    • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy

Definitions

  • Exemplary embodiments of the present disclosure relate to plasma processing methods and plasma processing systems.
  • Patent Document 1 discloses a method of etching a silicon-containing film.
  • the present disclosure provides a technique for controlling the shape of recesses formed by etching.
  • the RF signal includes alternating first time periods having a first power level and second time periods having a second power level lower than the first power level.
  • a plasma processing method is provided in which the second power level is reduced with respect to the first power level as the etching progresses in step (c).
  • the shape of recesses formed by etching can be controlled.
  • FIG. 1 schematically shows a plasma processing system 1;
  • FIG. It is a flow chart which shows an example of this processing method. It is a figure which shows typically an example of the cross-sectional structure of the board
  • FIG. 4 is a diagram schematically showing an example of a cross-sectional structure of a substrate W after being processed in steps ST3A to ST3F; 4 is a timing chart showing an example of a source RF signal in steps ST3A to ST3F; 4 is a timing chart showing an example of bias RF signals in steps ST3A to ST3F; 4 is a timing chart showing an example of bias DC signals in steps ST3A to ST3F;
  • the bias signal is a pulse wave containing alternating two periods of different power or voltage levels.
  • the bias signal is a continuous wave.
  • a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber and (b) processing within the chamber.
  • the signal is a pulse wave comprising alternating third periods having a third power or voltage level and fourth periods having a fourth power or voltage level lower than the third power or voltage level.
  • a plasma processing method is provided in which the fourth power or voltage level with respect to the third power or voltage level is increased as the etching progresses.
  • the RF signal is a pulsed wave containing alternating periods of two different power levels.
  • the RF signal is continuous wave.
  • an RF signal is used as the bias signal.
  • a DC signal is used as the bias signal.
  • a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber and (b) processing within the chamber.
  • processing within the chamber supplying a source RF signal to generate a plasma of the process gas in the chamber and supplying a bias RF signal to the substrate support to etch the substrate.
  • the source RF signal is a pulsed wave comprising alternating first durations having a first power level and second durations having a second power level lower than the first power level;
  • the signal is a pulse wave comprising alternating third periods having a third power level and fourth periods having a fourth power level lower than the third power level; (c1) decreasing the second power level relative to the first power level as the etch progresses; and (c2) increasing the fourth power level relative to the third power level as the etch progresses.
  • step (c1) holds the fourth power level constant relative to the third power level
  • step (c2) holds the second power level constant relative to the first power level
  • step (c2) is performed after step (c1) is performed.
  • step (c2) is performed after the etching time or etching depth exceeds a given time or depth in step (c).
  • step (c) the pressure in the chamber is lowered as the etching progresses.
  • the process gas comprises CxFy gas (x, y are positive integers ) or CsHtFu gas ( s , t, u are positive integers).
  • the recesses formed by the step (c) have an aspect ratio of 100 or more.
  • the duty ratio of the pulse wave of the source RF signal and/or the duty ratio of the pulse wave of the bias RF signal is 20% or more and 80% or less.
  • the silicon-containing film is a laminated film of a silicon oxide film and a silicon nitride film.
  • the film stack is included in a 3D-NAND structure.
  • the mask film is an amorphous carbon film.
  • a chamber a substrate support disposed within the chamber and configured to support a substrate having a silicon-containing film and a mask film formed on the silicon-containing film; and a power supply that produces a source RF signal and a bias RF signal, the source RF signal having a first power level for a first period of time and a first a pulse wave comprising alternating second periods having a second power level less than one power level, wherein the bias RF signal has third periods having a third power level and a third power level; a power supply, which is a pulsed wave comprising alternating fourth periods having a fourth power level lower than the power level; a controller configured to provide a bias RF signal from to the substrate support to control etching of the substrate, the controller controlling the first power level as the etching progresses.
  • a plasma processing system is provided that performs controlled decrease of the second power level and controlled increase of the fourth power level with respect to the third power level as etching progresses.
  • a capacitively coupled plasma processing apparatus is included.
  • the source RF signal is provided to the substrate support.
  • FIG. 1 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.
  • the plasma processing system includes a capacitively coupled plasma processing apparatus 1 and a controller 2.
  • a capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10 , a gas supply section 20 , a power supply 30 and an exhaust system 40 . Further, the plasma processing apparatus 1 includes a substrate support section 11 and a gas introduction section.
  • the gas introduction is configured to introduce at least one process gas into the plasma processing chamber 10 .
  • the gas introduction section includes a showerhead 13 .
  • a substrate support 11 is positioned within the plasma processing chamber 10 .
  • the showerhead 13 is arranged above the substrate support 11 . In one embodiment, showerhead 13 forms at least a portion of the ceiling of plasma processing chamber 10 .
  • the plasma processing chamber 10 has a plasma processing space 10 s defined by a showerhead 13 , side walls 10 a of the plasma processing chamber 10 and a substrate support 11 .
  • the plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space 10s and at least one gas exhaust port for exhausting gas from the plasma processing space.
  • Plasma processing chamber 10 is grounded.
  • the showerhead 13 and substrate support 11 are electrically insulated from the plasma processing chamber 10 housing.
  • the substrate support section 11 includes a body section 111 and a ring assembly 112 .
  • the body portion 111 has a central region 111 a for supporting the substrate W and an annular region 111 b for supporting the ring assembly 112 .
  • a wafer is an example of a substrate W;
  • the annular region 111b of the body portion 111 surrounds the central region 111a of the body portion 111 in plan view.
  • the substrate W is arranged on the central region 111 a of the main body 111
  • the ring assembly 112 is arranged on the annular region 111 b of the main body 111 so as to surround the substrate W on the central region 111 a of the main body 111 .
  • the central region 111a is also referred to as a substrate support surface for supporting the substrate W
  • the annular region 111b is also referred to as a ring support surface for supporting the edge ring assembly 112.
  • the body portion 111 includes a base 1110 and an electrostatic chuck 1111 .
  • Base 1110 includes a conductive member.
  • a conductive member of the base 1110 can function as a bottom electrode.
  • An electrostatic chuck 1111 is arranged on the base 1110 .
  • the electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a.
  • Ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have the annular region 111b.
  • the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or may be placed on both the electrostatic chuck 1111 and the annular insulating member.
  • An RF or DC electrode may also be placed within the ceramic member 1111a, in which case the RF or DC electrode serves as the bottom electrode.
  • An RF or DC electrode is also referred to as a bias electrode when a bias RF signal or DC signal, described below, is connected to the RF or DC electrode. Note that both the conductive member of the base 1110 and the RF or DC electrode may function as the two bottom electrodes.
  • Ring assembly 112 includes one or more annular members.
  • the one or more annular members include one or more edge rings and at least one cover ring.
  • the edge ring is made of a conductive material or an insulating material
  • the cover ring is made of an insulating material.
  • the substrate supporter 11 may include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature.
  • the temperature control module may include heaters, heat transfer media, channels 1110a, or combinations thereof.
  • channels 1110a are formed in base 1110 and one or more heaters are located in ceramic member 1111a of electrostatic chuck 1111.
  • the substrate supporter 11 may include a heat transfer gas supply unit configured to supply a heat transfer gas between the back surface of the substrate W and the central region 111a.
  • the showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s.
  • the showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas introduction ports 13c.
  • the processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s through a plurality of gas introduction ports 13c.
  • showerhead 13 also includes an upper electrode.
  • the gas introduction part may include one or more side gas injectors (SGI: Side Gas Injector) attached to one or more openings formed in the side wall 10a.
  • SGI Side Gas Injector
  • the gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22 .
  • gas supply 20 is configured to supply at least one process gas from respective gas sources 21 through respective flow controllers 22 to showerhead 13 .
  • Each flow controller 22 may include, for example, a mass flow controller or a pressure controlled flow controller.
  • gas supply 20 may include one or more flow modulation devices that modulate or pulse the flow of at least one process gas.
  • Power supply 30 includes an RF power supply 31 coupled to plasma processing chamber 10 via at least one impedance matching circuit.
  • RF power supply 31 is configured to supply at least one RF signal (RF power), such as a source RF signal and a bias RF signal, to at least one bottom electrode and/or at least one top electrode.
  • RF power source 31 may function as at least part of a plasma generator configured to generate a plasma from one or more process gases in plasma processing chamber 10 .
  • a bias RF signal to at least one lower electrode, a bias potential is generated in the substrate W, and ion components in the formed plasma can be drawn into the substrate W.
  • the RF power supply 31 includes a first RF generator 31a and a second RF generator 31b.
  • the first RF generator 31a is coupled to at least one lower electrode and/or at least one upper electrode via at least one impedance matching circuit to generate a source RF signal (source RF power) for plasma generation.
  • the source RF signal has a frequency within the range of 10 MHz to 150 MHz.
  • the first RF generator 31a may be configured to generate multiple source RF signals having different frequencies.
  • One or more source RF signals generated are provided to at least one bottom electrode and/or at least one top electrode.
  • the second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and configured to generate a bias RF signal (bias RF power).
  • the frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal.
  • the bias RF signal has a frequency lower than the frequency of the source RF signal.
  • the bias RF signal has a frequency within the range of 100 kHz to 60 MHz.
  • the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies.
  • One or more bias RF signals generated are provided to at least one bottom electrode. Also, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.
  • Power supply 30 may also include a DC power supply 32 coupled to plasma processing chamber 10 .
  • the DC power supply 32 includes a first DC generator 32a and a second DC generator 32b.
  • the first DC generator 32a is connected to the at least one bottom electrode and configured to generate a first DC signal.
  • a generated first bias DC signal is applied to at least one bottom electrode.
  • the second DC generator 32b is connected to the at least one top electrode and configured to generate a second DC signal. The generated second DC signal is applied to at least one top electrode.
  • At least one of the first and second DC signals may be pulsed.
  • a sequence of DC-based voltage pulses is applied to at least one bottom electrode and/or at least one top electrode.
  • the voltage pulses may have rectangular, trapezoidal, triangular, or combinations thereof pulse waveforms.
  • a waveform generator for generating a sequence of voltage pulses from a DC signal is connected between the first DC generator 32a and the at least one bottom electrode. Therefore, the first DC generator 32a and the waveform generator constitute a voltage pulse generator.
  • the voltage pulse generator is connected to at least one upper electrode.
  • the voltage pulse may have a positive polarity or a negative polarity.
  • the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses in one cycle.
  • the first and second DC generators 32a and 32b may be provided in addition to the RF power supply 31, and the first DC generator 32a may be provided instead of the second RF generator 31b. good.
  • the exhaust system 40 may be connected to a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10, for example.
  • Exhaust system 40 may include a pressure regulating valve and a vacuum pump.
  • the pressure regulating valve regulates the pressure in the plasma processing space 10s.
  • Vacuum pumps may include turbomolecular pumps, dry pumps, or combinations thereof.
  • the controller 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various steps described in this disclosure. Controller 2 may be configured to control elements of plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the controller 2 may be included in the plasma processing apparatus 1 .
  • the control unit 2 may include, for example, a computer 2a.
  • the computer 2a may include, for example, a processing unit (CPU: Central Processing Unit) 2a1, a storage unit 2a2, and a communication interface 2a3.
  • Processing unit 2a1 can be configured to perform various control operations by reading a program from storage unit 2a2 and executing the read program. This program may be stored in the storage unit 2a2 in advance, or may be acquired via a medium when necessary.
  • the acquired program is stored in the storage unit 2a2, read from the storage unit 2a2 and executed by the processing unit 2a1.
  • the medium may be various storage media readable by the computer 2a, or may be a communication line connected to the communication interface 2a3.
  • the storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof.
  • the communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).
  • FIG. 2 is a flow chart showing a plasma processing method (hereinafter also referred to as "this processing method") according to one exemplary embodiment.
  • this processing method includes a step ST1 of providing a substrate, a step ST2 of supplying a processing gas, and a step ST3 of etching the substrate.
  • the step ST3 of etching the substrate includes a step ST3A of etching the first region, a step ST3B of etching the second region, a step ST3C of etching the third region, a step ST3D of etching the fourth region, and a step ST3D of etching the fifth region.
  • ST3E including step ST6F of etching the sixth region.
  • the processing in each step may be performed by the plasma processing system shown in FIG.
  • An example in which the control unit 2 controls each unit of the plasma processing apparatus 1 to perform the present processing method on the substrate W will be described below.
  • step ST ⁇ b>1 the substrate W is provided within the plasma processing space 10 s of the plasma processing apparatus 1 .
  • the substrate W is placed on the upper surface of the substrate support portion 11 .
  • FIG. 3 is a diagram showing an example of the cross-sectional structure of the substrate W provided in step ST1.
  • a silicon-containing film SF and a mask film MF are formed in this order on a base film UF.
  • the substrate W may be used, for example, in the manufacture of semiconductor devices including semiconductor memory devices such as DRAMs, 3D-NAND flash memories and the like.
  • the base film UF may be, for example, a silicon wafer or an organic film, dielectric film, metal film, semiconductor film, or the like formed on a silicon wafer.
  • the base film UF may be configured by laminating a plurality of films.
  • the silicon-containing film SF is a film to be etched in this processing method.
  • the silicon-containing film SF may be, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.
  • the silicon-containing film SF may be configured by laminating a plurality of films.
  • the silicon-containing film SF may be configured by alternately stacking a silicon oxide film and a polycrystalline silicon film.
  • the silicon-containing film SF may be configured by alternately stacking a silicon oxide film and a silicon nitride film.
  • the mask film MF may be, for example, a carbon-containing film such as an amorphous carbon film, a spin-on carbon film, or a photoresist film.
  • the mask film MF may be a single layer mask consisting of one layer or a multilayer mask consisting of two or more layers.
  • Mask film MF has at least one opening OP.
  • the opening OP may have any shape when the substrate W is viewed from above, that is, when the substrate W is viewed from the top to the bottom in FIG.
  • the shape may be, for example, a circle, an ellipse, a rectangle, a line, or a combination of one or more of these.
  • the mask film MF may have multiple openings OP.
  • a processing gas is supplied into the plasma processing space 10s.
  • the processing gas is a gas used for etching the silicon-containing film SF formed on the substrate W.
  • the type of processing gas may be appropriately selected based on the material of the silicon-containing film SF, the material of the mask film MF, the material of the base film UF, the pattern of the mask film MF, the depth of etching, and the like.
  • the processing gas may include, for example , one or both of CxFy gas and CsHtFu gas .
  • the CxFy gas may be at least one selected from the group consisting of C4F6 gas, C4F8 gas, C3F6 gas and C7F8 gas .
  • the CsHtFu gas may be CH2F2 gas or CH3F gas .
  • the process gas may include a hydrogen-containing gas such as H2 gas or CH4 gas.
  • Step ST3 Etching
  • a source RF signal (RF power) is supplied from the first RF generator 31a to the lower electrode and/or the upper electrode.
  • a bias RF signal is supplied to the lower electrode from the second RF generator 31b.
  • plasma is generated from the processing gas supplied to the plasma processing space 10s, and a bias potential is generated on the substrate W as well.
  • Active species such as ions and radicals in the generated plasma are attracted to the substrate W, and the silicon-containing film SF is etched.
  • the timing to start supplying the source RF signal and the timing to start supplying the bias RF signal may be the same or different.
  • steps ST3A to ST3F of step ST3 the power levels of the source RF signal and the bias RF signal are changed as the etching of the silicon-containing film SF progresses. This point will be described with reference to FIGS. 4A to 4F, 5A to 5F, and 6A to 6F.
  • the progress of etching may be determined based on the elongation of the etching depth or the lapse of etching time.
  • 4A to 4F are diagrams showing examples of cross-sectional structures of the substrate W after being processed in steps ST3A to ST3F, respectively.
  • 5A to 5F are timing charts showing examples of source RF signals in steps ST3A to ST3F, respectively.
  • the horizontal axis indicates time.
  • the vertical axis indicates the effective value of the power level of the source RF signal.
  • “L 11 ”, “L 12 ”, “L 13 ”, and “L 14 ” indicate power levels lower than those indicated by “H 1 ”.
  • L 11 >L 12 >L 13 > L 14 holds between L 11 , L 12 , L 13 and L 14 (that is, L 11 has the highest power level and L 14 has the lowest power level).
  • “L 14 ” includes when the power level is 0 W, ie no signal is applied. As shown in FIGS.
  • the source RF signal has a H1 period (first period) with a power level of H 1 (first power) and L 11 , L 12 , L lower than H 1 .
  • 6A to 6F are timing charts showing examples of bias RF signals in steps ST3A to ST3F, respectively.
  • the horizontal axis indicates time.
  • the vertical axis indicates the effective value of the power level of the bias RF signal.
  • “L 21 ”, “L 22 ”, and “L 23 ” indicate lower power levels than indicated by “H 2 ”.
  • L 21 , L 22 and L 23 have the relationship of L 21 ⁇ L 22 ⁇ L 23 (that is, among L 21 , L 22 and L 23 , L 21 has the lowest power level and L 23 highest power level).
  • “L 21 ” includes when the power level is 0 W, ie no signal is being supplied.
  • the bias RF signal has an H2 period (third period) having a power level of H2 (third power) and a power level of L21 , L22 or L23 lower than H2 (fourth power). It is a pulse wave that alternately includes an L2 period (fourth period).
  • Step ST3A Etching of First Region
  • the step ST3A is performed in the first region from the start of etching until the etching depth of the recess RC formed by etching reaches d1 (see FIG. 4A).
  • the recess RC is a portion of the silicon-containing film SF corresponding to the opening OP of the mask film MF.
  • a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L11 lower than H1 is used as the source RF signal (see FIG. 5A).
  • the bias RF signal a pulse wave that alternately includes H2 periods having a power level of H2 and L2 periods having a power level L21 lower than H2 is used (see FIG. 6A).
  • Step ST3B Etching of Second Region
  • the step ST3B is performed in the second region until the etching depth of the recess RC reaches d2 (see FIG. 4B).
  • the etching depth d2 is deeper than the etching depth d1, and the relationship of d2>d1 holds.
  • a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L12 lower than H1 is used as the source RF signal (see FIG. 5B).
  • the power level L12 of the source RF signal of step ST3B is lower than the power level L11 of the source RF signal of step ST3A.
  • the same pulse wave as in step ST3A is used (see FIG. 6B).
  • Step ST3C etching of the third region
  • the step ST3C is performed in the third region until the etching depth of the recess RC reaches d3 (see FIG. 4C).
  • the etching depth d3 is deeper than the etching depth d2, and the relationship of d3>d2 holds.
  • the etching depth d3 may be, for example, half the depth to be etched in step ST3.
  • the etching depth d3 may be half the thickness of the silicon-containing film SF.
  • a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L13 lower than H1 is used as the source RF signal (see FIG. 5C).
  • the power level L13 of the source RF signal of step ST3C is lower than the power level L12 of the source RF signal of step ST3B.
  • the bias RF signal the same pulse wave as in steps ST3A and ST3B is used (see FIG. 6C).
  • Step ST3D Etching of fourth region
  • the step ST3D is performed in the fourth region until the etching depth of the recess RC reaches d4 (see FIG. 4D).
  • the etching depth d4 is deeper than the etching depth d3, and the relationship of d4>d3 holds.
  • a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L14 lower than H1 is used as the source RF signal (see FIG. 5D).
  • the power level L14 of the source RF signal of step ST3D is lower than the power level L13 of the source RF signal of step ST3C.
  • the bias RF signal the same pulse wave as in steps ST3A to ST3C is used (see FIG. 6D).
  • Step ST3E Etching of fifth region
  • the step ST3E is performed in the fifth region until the etching depth of the recess RC reaches d5 (see FIG. 4E).
  • the etching depth d5 is deeper than the etching depth d4, and the relationship of d2>d1 holds.
  • the same pulse wave as in step ST3D is used as the source RF signal (see FIG. 5E).
  • the bias RF signal a pulse wave containing alternating H2 periods with a power level of H2 and L2 periods with a power level L22 lower than H2 is used (see FIG. 6E).
  • the power level L22 of the bias RF signal in step ST3E is higher than the power level L21 of the bias RF signal in steps ST3A to ST3D.
  • Step ST3F Etching of sixth region
  • the step ST3F is performed in the sixth region until the etching depth of the recess RC reaches d6 (see FIG. 4F).
  • the etching depth d6 is deeper than the etching depth d5, and the relationship of d6>d5 holds.
  • the etching depth d6 is, for example, the film thickness of the silicon-containing film SF.
  • the step ST3F is performed until the bottom of the recess RC reaches the underlying film UF.
  • the aspect ratio of the recess RC in this state may be, for example, 20 or more, 30 or more, 40 or more, 50 or more, or 100 or more.
  • step ST3F the same pulse wave as in steps ST3D and ST3E is used as the source RF signal (see FIG. 5F).
  • the bias RF signal a pulse wave containing alternating H2 periods with a power level of H2 and L2 periods with a power level L23 lower than H2 is used (see FIG. 6E).
  • the power level L23 of the bias RF signal in step ST3F is higher than the power level L22 of the bias RF signal in step ST3E.
  • the duty ratio of the pulse wave of the source RF signal that is, the ratio of the H1 period to the H1 period and the L1 period may be 20% or more and 80% or less.
  • the duty ratio of the pulse wave of the bias RF signal that is, the ratio of the H2 period to the H2 period and the L2 period may be 20% or more and 80% or less.
  • the H1 period of the source RF signal may or may not be synchronous with the H2 period of the bias RF signal.
  • the time length of the H1 period of the source RF signal may be the same as or different from the time length of the H2 period of the bias RF signal. Part or all of the H1 period of the source RF signal may overlap with the H2 period of the bias RF signal.
  • step ST3 the power level of the source RF signal during the L1 period with respect to the power level H1 during the H1 period may decrease stepwise from step ST3A to step ST3D and become lowest in step ST3D to step 3F (FIG. 5A). (see FIG. 5F).
  • step ST3D to 3F high-density plasma is generated in this order in steps ST3A to ST3C, ie, in the etching of the shallower region of the recess RC.
  • steps ST3D to 3F that is, in the etching of the region where the recess RC is deeper, plasma with a lower density than in steps ST3A to ST3C is generated.
  • step ST3 the power level of the bias RF signal during the L2 period with respect to the power level H2 during the H2 period may be the lowest in steps ST3A to ST3D and increase stepwise from step ST3D to step ST3F (FIG. 6A). (see FIG. 6F).
  • a lower bias potential is applied to the substrate W in steps ST3A to ST3D, ie, the etching of the region where the recess RC is shallower than in the steps ST3E to ST3F, ie, the etching of the region where the recess RC is deeper. occur.
  • a higher bias potential is generated on the substrate W in step ST3F than in step ST3E.
  • step ST3 while the power level of the source RF signal during the L1 period is gradually decreased, that is, in steps ST3A to ST3D, the power level of the bias RF signal during the L2 period may be kept constant. Further, while the power level of the bias RF signal during the L2 period is increased stepwise, that is, in steps ST3D to ST3F, the power level of the source RF signal during the L1 period may be kept constant.
  • the shallower portion of the recess RC can be etched with a higher density plasma and a lower bias potential.
  • High - density plasma accelerates the dissociation of CxFy gas and/or CsHtFu gas in the process gas, making it easier to generate molecules with higher adsorption coefficients. Therefore, the amount of reaction products adhering to the mask film MF and the sidewalls of the recess RC may increase.
  • the high-density plasma reduces the flow of ions toward the substrate W, and the low bias potential reduces sputtering on the mask film MF and sidewalls of the recess RC.
  • This protective film can protect the side walls of the recess RC in etching after step ST3 (including etching in a region where the depth of the recess RC is deeper). Therefore, bowing in which the width of the opening of the recess RC is partially widened can be suppressed.
  • the deep region of the recess RC can be etched with a lower density plasma and a higher bias potential.
  • dissociation of CxFy gas and/or CsHtFu gas in the processing gas is difficult to promote, and molecules with high adsorption coefficients are difficult to generate . Therefore, the amount of reaction products adhering to the mask film MF and the sidewalls of the recesses RC can be reduced. As a result, narrowing of the openings of the mask film MF and the recesses RC can be suppressed, and changes in the incident angle of the ions entering the recesses RC can be suppressed.
  • the high density plasma may increase the flow of ions toward the bottom of the recess RC. Furthermore, since etching is performed at a high bias potential, the incident angle of ions entering the recess RC can be closer to the vertical. As described above, it is possible to prevent the bottom width (bottom CD) of the recess RC from being narrowed at a portion where the depth of the recess RC is deep.
  • step ST3 the power level of the source RF signal during the L1 period may be decreased in stages, and then the power level of the bias RF signal during the L2 period may be increased in stages.
  • the power level of the source RF signal during the L1 period may be kept constant, and only the power level of the bias RF signal during the L2 period may be increased stepwise.
  • only the power level of the source RF signal during the L1 period may be stepwise decreased while the power level of the bias RF signal during the L2 period may be kept constant.
  • the pulse wave of the source RF signal and the pulse wave of the bias RF signal may be used.
  • either the source RF signal or the bias RF signal may be continuous waves with no H1, L1, etc. periods.
  • a continuous wave source RF signal and a pulsed bias RF signal may be used.
  • the power level of the continuous wave of the source RF signal may be stepwise decreased
  • steps ST3D to ST3F the power level of the L2 period of the bias RF signal may be stepwise increased.
  • a pulsed source RF signal and a continuous biased RF signal may be used.
  • steps ST3A to ST3D the power level of the L1 period of the source RF signal may be stepwise decreased, and in steps ST3E to ST3F, the power level of the continuous wave of the bias RF signal may be stepwise increased. .
  • a bias RF signal may be used as the bias signal (power) supplied to the lower electrode.
  • a negative DC voltage may be supplied to the lower electrode as a bias DC signal from the first DC generator 32a.
  • the voltage level of the bias DC signal is the effective value of the absolute value of the negative DC voltage.
  • the bias DC signal may be pulsed or continuous wave.
  • the bias DC signal has a sequence of negative voltage pulses during H3.
  • the sequence of negative voltage pulses has, for example, a pulse frequency in the range of 100 kHz to 500 kHz.
  • the negative voltage pulse has a voltage level of V 1 (FIGS. 7A-7D), a voltage level of V 2 (FIG. 7E) or a voltage level of V 3 (FIG. 7F).
  • the waveform of the negative voltage pulse may have a rectangular, trapezoidal, triangular, or combination waveform.
  • V 1 , V 2 , and V 3 show negative values smaller than 0, and the relationship
  • the bias DC signal is a pulse wave containing alternating H3 periods with power levels of V 1 , V 2 or V 3 and L3 periods in which no bias DC signal is provided (voltage level is 0).
  • the bias DC signal may have a sequence of negative voltage pulses during the L3 period. In this case, the voltage level of the voltage of the negative voltage pulse is lower than the voltage level of the negative voltage pulse during the H3 period.
  • bias DC signal shown in FIGS. 7A to 7F is used, as in the case of using the bias RF signal shown in FIGS.
  • a lower bias potential is developed on the substrate W.
  • a higher bias potential is generated on the substrate W in step ST3F than in step ST3E.
  • step ST3 six regions may be provided in which etching is performed by changing the power levels of the source RF signal and the bias RF signal, depending on the depth of the recess RC.
  • the thickness of the silicon-containing film SF is divided into an upper region where the upper half of the thickness is etched and a lower region where the lower half is etched, and the power levels of the source RF signal and the bias RF signal are changed in the upper region and the lower region.
  • the area may be set according to the etching time instead of the etching depth (the depth of the recess RC).
  • step ST3 the pressure inside the plasma processing chamber 10 may be decreased as the etching progresses.
  • a higher density plasma can be generated at a portion where the recess RC is shallower, and a lower density plasma can be generated at a portion where the recess RC is deeper.
  • Etching progress may be determined based on the elongation of the etching depth or the elapse of the etching time.
  • this processing method was applied to the substrate W shown in FIG. 3, and the silicon-containing film SF was etched with a processing gas containing C 4 F 8 gas.
  • the silicon-containing film SF of the substrate W is a laminated film of a silicon oxide film and a silicon nitride film
  • the mask film MF is an amorphous carbon film.
  • the opening pattern of the mask film MF is a hole pattern.
  • the silicon-containing film SF is divided into six regions (referred to as "first region”, "second region”, etc. in order from the top), and in each region, the pulse wave of the source RF signal and the bias RF signal Etching was performed by changing the power level of the pulse wave.
  • the etching time for each region was 300 seconds.
  • Example 1 the power level of the source RF signal was stepped down during the L1 period, and then the power level of the bias RF signal was stepped up during the L2 period.
  • the power level H1 of the source RF signal during the H1 period was 7500 [W] in the first to sixth regions.
  • the power level of the source RF signal during the L1 period was 400 [W] in the first region, 200 [W] in the second region, and 0 [W] in the third to sixth regions.
  • the power level of the bias RF signal during the H2 period was 12000 [W] in all of the first to sixth regions.
  • the power level of the bias RF signal during the L2 period was 0 [W] in the first to fourth regions, 200 [W] in the fifth region, and 700 [W] in the sixth region.
  • Example 2 only the power level of the source RF signal during the L1 period was stepped down, while the power level of the bias RF signal during the L2 period was kept constant.
  • the power level H1 of the source RF signal during the H1 period was 7500 [W] in the first to sixth regions.
  • the power level of the source RF signal during the L1 period is 500 [W] in the first region, 300 [W] in the second region, 100 [W] in the third region, and 0 [W] in the fourth to sixth regions.
  • Met The power level of the bias RF signal during the H2 period was 12000 [W] in all of the first to sixth regions.
  • the power level of the bias RF signal during the L2 period was 0 [W] in all of the first to sixth regions.
  • Example 3 the power level of the source RF signal during the L1 period was kept constant, and only the power level of the bias RF signal during the L2 period was increased stepwise. Specifically, the power level H1 of the H1 period of the source RF signal was 7500 [W] in all of the first to sixth regions. The power level of the source RF signal during the L1 period was 0 [W] in the first to sixth regions. The power level of the bias RF signal during the H2 period was 12000 [W] in all of the first to sixth regions. The power level of the bias RF signal during the L2 period was 0 [W] in the first to fourth regions, 200 [W] in the fifth region, and 700 [W] in the sixth region.
  • the silicon-containing film SF of the substrate W having the same configuration and hole pattern as those of the substrate W in the example was etched with a processing gas containing a C 4 F 8 gas.
  • etching was continuously performed for 1800 seconds without changing the power level of the pulse wave of the source RF signal and the pulse wave of the bias RF signal.
  • the power level of the source RF signal during the H1 period was 7500 [W].
  • the power level of the source RF signal during the L1 period was 0 [W].
  • the power level of the bias RF signal during the H2 period was 12000 [W].
  • the power level of the bias RF signal during the L2 period was 0 [W].
  • Table 1 shows various measurement results for each example and reference example.
  • D is the etching depth of the silicon-containing film SF after processing.
  • B W is the maximum opening width (Boeing CD) of the recess RC.
  • B t is the width (bottom CD) of the bottom of the recess RC.
  • B W ⁇ B t is the difference between Boeing CD and Bottom CD.
  • the difference between the Boeing CD and the bottom CD in the example was improved compared to the reference example. That is, in the example, it was possible to expand the bottom width of the recess RC while suppressing bowing due to etching.
  • this processing method may be performed using a plasma processing apparatus using an arbitrary plasma source, such as inductively coupled plasma or microwave plasma, other than the capacitively coupled plasma processing apparatus 1 .
  • Plasma processing apparatus Control unit 10 Plasma processing chamber 10s Plasma processing space 11 Substrate support 13 shower head 20 Gas supply unit 31a First RF generator 31b Second RF generator 32a First DC generator MF Mask film OP Opening SF Silicon-containing film RC Recess UF Bottom base film, W... substrate

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Abstract

Provided is a technology that controls the shape of a recessed section formed by etching. This plasma processing method includes: (a) a step in which a substrate having a silicon-including film and a masking film that is formed on the silicon-including film is provided on a substrate support part in a chamber; (b) a step in which a processing gas is supplied into the chamber; and (c) a step in which an RF signal is supplied and plasma of the processing gas is generated in the chamber, while a biasing signal is supplied to the substrate support part, and the substrate is etched. The RF signal is a pulsed wave that includes, in an alternating manner, first periods having a first power level and second periods having a second power level that is lower than the first power level. During step (c), the second power level is reduced relative to the first power level as the etching proceeds.

Description

プラズマ処理方法及びプラズマ処理システムPlasma processing method and plasma processing system
　本開示の例示的実施形態は、プラズマ処理方法及びプラズマ処理システムに関する。 Exemplary embodiments of the present disclosure relate to plasma processing methods and plasma processing systems.
　特許文献１には、シリコン含有膜をエッチングする方法が開示されている。 Patent Document 1 discloses a method of etching a silicon-containing film.
　　　特開２０１６－３９３０９号公報 Japanese Patent Application Laid-Open No. 2016-39309
　本開示は、エッチングで形成される凹部の形状を制御する技術を提供する。 The present disclosure provides a technique for controlling the shape of recesses formed by etching.
　本開示の一つの例示的実施形態において、（ａ）シリコン含有膜と前記シリコン含有膜上に形成されたマスク膜とを有する基板をチャンバ内の基板支持部上に提供する工程と、（ｂ）前記チャンバ内に処理ガスを供給する工程と、（ｃ）ＲＦ信号を供給して前記チャンバ内に前記処理ガスのプラズマを生成するとともに前記基板支持部にバイアス信号を供給して、前記基板をエッチングする工程と、を含み、前記ＲＦ信号は、第１の電力レベルを有する第１の期間と、前記第１の電力レベルよりも低い第２の電力レベルを有する第２の期間とを交互に含むパルス波であり、前記（ｃ）の工程において、エッチングの進行に伴って前記第１の電力レベルに対する前記第２の電力レベルを減少させる、プラズマ処理方法が提供される。 In one exemplary embodiment of the present disclosure, the steps of (a) providing a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber; providing a process gas into the chamber; and (c) providing an RF signal to generate a plasma of the process gas within the chamber and a bias signal to the substrate support to etch the substrate. wherein the RF signal includes alternating first time periods having a first power level and second time periods having a second power level lower than the first power level. A plasma processing method is provided in which the second power level is reduced with respect to the first power level as the etching progresses in step (c).
　本開示の一つの例示的実施形態によれば、エッチングで形成される凹部の形状を制御することができる。 According to one exemplary embodiment of the present disclosure, the shape of recesses formed by etching can be controlled.
プラズマ処理システム１を概略的に示す図である。1 schematically shows a plasma processing system 1; FIG. 本処理方法の一例を示すフローチャートである。It is a flow chart which shows an example of this processing method. 工程ＳＴ１で提供される基板Ｗの断面構造の一例を模式的に示す図である。It is a figure which shows typically an example of the cross-sectional structure of the board|substrate W provided by process ST1. 工程ＳＴ３Ａ乃至ＳＴ３Ｆにおける処理後の基板Ｗの断面構造の一例を模式的に示す図である。FIG. 4 is a diagram schematically showing an example of a cross-sectional structure of a substrate W after being processed in steps ST3A to ST3F; 工程ＳＴ３Ａ乃至ＳＴ３ＦにおけるソースＲＦ信号の一例を示すタイミングチャートである。4 is a timing chart showing an example of a source RF signal in steps ST3A to ST3F; 工程ＳＴ３Ａ乃至ＳＴ３ＦにおけるバイアスＲＦ信号の一例を示すタイミングチャートである。4 is a timing chart showing an example of bias RF signals in steps ST3A to ST3F; 工程ＳＴ３Ａ乃至ＳＴ３ＦにおけるバイアスＤＣ信号の一例を示すタイミングチャートである。4 is a timing chart showing an example of bias DC signals in steps ST3A to ST3F;
　以下、本開示の各実施形態について説明する。 Each embodiment of the present disclosure will be described below.
　一つの例示的実施形態において、（ａ）シリコン含有膜とシリコン含有膜上に形成されたマスク膜とを有する基板をチャンバ内の基板支持部上に提供する工程と、（ｂ）チャンバ内に処理ガスを供給する工程と、（ｃ）ＲＦ信号を供給してチャンバ内に処理ガスのプラズマを生成するとともに基板支持部にバイアス信号を供給して、基板をエッチングする工程と、を含み、ＲＦ信号は、第１の電力レベルを有する第１の期間と、第１の電力レベルよりも低い第２の電力レベルを有する第２の期間とを交互に含むパルス波であり、（ｃ）の工程において、エッチングの進行に伴って第１の電力レベルに対する第２の電力レベルを減少させるプラズマ処理方法が提供される。 In one exemplary embodiment, (a) providing a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber; and (b) processing within the chamber. and (c) providing an RF signal to create a plasma of the process gas in the chamber and a bias signal to the substrate support to etch the substrate, the RF signal comprising: is a pulse wave that alternately includes a first period having a first power level and a second period having a second power level lower than the first power level, and in step (c) A plasma processing method is provided that decreases a second power level relative to the first power level as the etch progresses.
　一つの例示的実施形態において、バイアス信号は、電力又は電圧レベルが異なる２つの期間を交互に含むパルス波である。 In one exemplary embodiment, the bias signal is a pulse wave containing alternating two periods of different power or voltage levels.
　一つの例示的実施形態において、バイアス信号は、連続波である。 In one exemplary embodiment, the bias signal is a continuous wave.
　一つの例示的実施形態において、（ａ）シリコン含有膜とシリコン含有膜上に形成されたマスク膜とを有する基板をチャンバ内の基板支持部上に提供する工程と、（ｂ）チャンバ内に処理ガスを供給する工程と、（ｃ）ＲＦ信号を供給してチャンバ内に処理ガスのプラズマを生成するとともに、基板支持部にバイアス信号を供給して、基板をエッチングする工程と、を含み、バイアス信号は、第３の電力又は電圧レベルを有する第３の期間と、第３の電力又は電圧レベルよりも低い第４の電力又は電圧レベルを有する第４の期間とを交互に含むパルス波であり、（ｃ）の工程において、第３の電力又は電圧レベルに対する第４の電力又は電圧レベルをエッチングの進行に伴って増加させるプラズマ処理方法が提供される。 In one exemplary embodiment, (a) providing a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber; and (b) processing within the chamber. (c) providing an RF signal to generate a plasma of the process gas in the chamber and a bias signal to the substrate support to etch the substrate; The signal is a pulse wave comprising alternating third periods having a third power or voltage level and fourth periods having a fourth power or voltage level lower than the third power or voltage level. , (c), a plasma processing method is provided in which the fourth power or voltage level with respect to the third power or voltage level is increased as the etching progresses.
　一つの例示的実施形態において、ＲＦ信号は、電力レベルが異なる２つの期間を交互に含むパルス波である。 In one exemplary embodiment, the RF signal is a pulsed wave containing alternating periods of two different power levels.
　一つの例示的実施形態において、ＲＦ信号は、連続波である。 In one exemplary embodiment, the RF signal is continuous wave.
　一つの例示的実施形態において、バイアス信号として、ＲＦ信号を用いる。 In one exemplary embodiment, an RF signal is used as the bias signal.
　一つの例示的実施形態において、バイアス信号として、ＤＣ信号を用いる。 In one exemplary embodiment, a DC signal is used as the bias signal.
　一つの例示的実施形態において、（ａ）シリコン含有膜とシリコン含有膜上に形成されたマスク膜とを有する基板をチャンバ内の基板支持部上に提供する工程と、（ｂ）チャンバ内に処理ガスを供給する工程と、（ｃ）ソースＲＦ信号を供給してチャンバ内に処理ガスのプラズマを生成するとともに、基板支持部にバイアスＲＦ信号を供給して、基板をエッチングする工程と、を含み、ソースＲＦ信号は、第１の電力レベルを有する第１の期間と、第１の電力レベルよりも低い第２の電力レベルを有する第２の期間とを交互に含むパルス波であり、バイアスＲＦ信号は、第３の電力レベルを有する第３の期間と、第３の電力レベルよりも低い第４の電力レベルを有する第４の期間とを交互に含むパルス波であり、（ｃ）の工程は、（ｃ１）エッチングの進行に伴って第１の電力レベルに対する第２の電力レベルを減少させる工程と、（ｃ２）エッチングの進行に伴って第３の電力レベルに対する第４の電力レベルを増加させる工程と、を含むプラズマ処理方法が提供される。 In one exemplary embodiment, (a) providing a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber; and (b) processing within the chamber. (c) supplying a source RF signal to generate a plasma of the process gas in the chamber and supplying a bias RF signal to the substrate support to etch the substrate. , the source RF signal is a pulsed wave comprising alternating first durations having a first power level and second durations having a second power level lower than the first power level; the signal is a pulse wave comprising alternating third periods having a third power level and fourth periods having a fourth power level lower than the third power level; (c1) decreasing the second power level relative to the first power level as the etch progresses; and (c2) increasing the fourth power level relative to the third power level as the etch progresses. A plasma processing method is provided, comprising the step of:
　一つの例示的実施形態において、（ｃ１）の工程において、第３の電力レベルに対する第４の電力レベルを一定にし、（ｃ２）の工程において、第１の電力レベルに対する第２の電力レベルを一定にする。 In one exemplary embodiment, step (c1) holds the fourth power level constant relative to the third power level, and step (c2) holds the second power level constant relative to the first power level. to
　一つの例示的実施形態において、（ｃ）の工程において、（ｃ１）の工程を行った後、（ｃ２）の工程を行う。 In one exemplary embodiment, in step (c), step (c2) is performed after step (c1) is performed.
　一つの例示的実施形態において、（ｃ）の工程において、エッチング時間又はエッチングの深さが所与の時間又は深さを超えた後に、（ｃ２）の工程を行う。 In one exemplary embodiment, step (c2) is performed after the etching time or etching depth exceeds a given time or depth in step (c).
　一つの例示的実施形態において、（ｃ）の工程において、エッチングの進行に伴って、チャンバ内の圧力を低下させる。 In one exemplary embodiment, in step (c), the pressure in the chamber is lowered as the etching progresses.
　一つの例示的実施形態において、処理ガスは、ＣｘＦｙガス（ｘ、ｙは正の整数）又はＣｓＨｔＦｕガス（ｓ、ｔ，ｕは正の整数）を含む。 In one exemplary embodiment, the process gas comprises CxFy gas (x, y are positive integers ) or CsHtFu gas ( s , t, u are positive integers).
　一つの例示的実施形態において、（ｃ）の工程により形成される凹部のアスペクト比が１００以上である。 In one exemplary embodiment, the recesses formed by the step (c) have an aspect ratio of 100 or more.
　一つの例示的実施形態において、ソースＲＦ信号のパルス波のデューティ比、および／または、バイアスＲＦ信号のパルス波のデューティ比は、２０％以上８０％以下である。 In one exemplary embodiment, the duty ratio of the pulse wave of the source RF signal and/or the duty ratio of the pulse wave of the bias RF signal is 20% or more and 80% or less.
　一つの例示的実施形態において、シリコン含有膜は、シリコン酸化膜とシリコン窒化膜との積層膜である。 In one exemplary embodiment, the silicon-containing film is a laminated film of a silicon oxide film and a silicon nitride film.
　一つの例示的実施形態において、積層膜は、３Ｄ－ＮＡＮＤ構造に含まれる。 In one exemplary embodiment, the film stack is included in a 3D-NAND structure.
　一つの例示的実施形態において、マスク膜は、アモルファスカーボン膜である。 In one exemplary embodiment, the mask film is an amorphous carbon film.
　一つの例示的実施形態において、チャンバと、チャンバ内に設けられ、シリコン含有膜とシリコン含有膜上に形成されたマスク膜とを有する基板を支持するように構成された基板支持部と、チャンバ内に処理ガスを供給するように構成されたガス供給部と、ソースＲＦ信号及びバイアスＲＦ信号を生成する電源であって、ソースＲＦ信号は、第１の電力レベルを有する第１の期間と、第１の電力レベルよりも低い第２の電力レベルを有する第２の期間とを交互に含むパルス波であり、バイアスＲＦ信号は、第３の電力レベルを有する第３の期間と、第３の電力レベルよりも低い第４の電力レベルを有する第４の期間とを交互に含むパルス波である、電源と、電源からソースＲＦ信号を供給してチャンバ内に処理ガスのプラズマを生成するとともに、電源からバイアスＲＦ信号を基板支持部に供給して、基板をエッチングする制御を実行するように構成された制御部と、を有し、制御部は、エッチングの進行に伴って第１の電力レベルに対する第２の電力レベルを減少させる制御と、エッチングの進行に伴って第３の電力レベルに対する第４の電力レベルを増加させる制御と、を実行するプラズマ処理システムを提供する。 In one exemplary embodiment, a chamber; a substrate support disposed within the chamber and configured to support a substrate having a silicon-containing film and a mask film formed on the silicon-containing film; and a power supply that produces a source RF signal and a bias RF signal, the source RF signal having a first power level for a first period of time and a first a pulse wave comprising alternating second periods having a second power level less than one power level, wherein the bias RF signal has third periods having a third power level and a third power level; a power supply, which is a pulsed wave comprising alternating fourth periods having a fourth power level lower than the power level; a controller configured to provide a bias RF signal from to the substrate support to control etching of the substrate, the controller controlling the first power level as the etching progresses. A plasma processing system is provided that performs controlled decrease of the second power level and controlled increase of the fourth power level with respect to the third power level as etching progresses.
　一つの例示的実施形態において、容量結合型のプラズマ処理装置を含む。 In one exemplary embodiment, a capacitively coupled plasma processing apparatus is included.
　一つの例示的実施形態において、ソースＲＦ信号は、基板支持部に供給される。 In one exemplary embodiment, the source RF signal is provided to the substrate support.
　以下、図面を参照して、本開示の各実施形態について詳細に説明する。なお、各図面において同一または同様の要素には同一の符号を付し、重複する説明を省略する。特に断らない限り、図面に示す位置関係に基づいて上下左右等の位置関係を説明する。図面の寸法比率は実際の比率を示すものではなく、また、実際の比率は図示の比率に限られるものではない。 Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or similar elements are denoted by the same reference numerals, and overlapping descriptions are omitted. Unless otherwise specified, positional relationships such as top, bottom, left, and right will be described based on the positional relationships shown in the drawings. The dimensional ratios in the drawings do not indicate the actual ratios, and the actual ratios are not limited to the illustrated ratios.
＜プラズマ処理システムの構成例＞
　以下に、プラズマ処理システムの構成例について説明する。図１は、容量結合型のプラズマ処理装置の構成例を説明するための図である。 <Configuration example of plasma processing system>
A configuration example of the plasma processing system will be described below. FIG. 1 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.
　プラズマ処理システムは、容量結合型のプラズマ処理装置１及び制御部２を含む。容量結合型のプラズマ処理装置１は、プラズマ処理チャンバ１０、ガス供給部２０、電源３０及び排気システム４０を含む。また、プラズマ処理装置１は、基板支持部１１及びガス導入部を含む。ガス導入部は、少なくとも１つの処理ガスをプラズマ処理チャンバ１０内に導入するように構成される。ガス導入部は、シャワーヘッド１３を含む。基板支持部１１は、プラズマ処理チャンバ１０内に配置される。シャワーヘッド１３は、基板支持部１１の上方に配置される。一実施形態において、シャワーヘッド１３は、プラズマ処理チャンバ１０の天部（ｃｅｉｌｉｎｇ）の少なくとも一部を構成する。プラズマ処理チャンバ１０は、シャワーヘッド１３、プラズマ処理チャンバ１０の側壁１０ａ及び基板支持部１１により規定されたプラズマ処理空間１０ｓを有する。プラズマ処理チャンバ１０は、少なくとも１つの処理ガスをプラズマ処理空間１０ｓに供給するための少なくとも１つのガス供給口と、プラズマ処理空間からガスを排出するための少なくとも１つのガス排出口とを有する。プラズマ処理チャンバ１０は接地される。シャワーヘッド１３及び基板支持部１１は、プラズマ処理チャンバ１０筐体とは電気的に絶縁される。 The plasma processing system includes a capacitively coupled plasma processing apparatus 1 and a controller 2. A capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10 , a gas supply section 20 , a power supply 30 and an exhaust system 40 . Further, the plasma processing apparatus 1 includes a substrate support section 11 and a gas introduction section. The gas introduction is configured to introduce at least one process gas into the plasma processing chamber 10 . The gas introduction section includes a showerhead 13 . A substrate support 11 is positioned within the plasma processing chamber 10 . The showerhead 13 is arranged above the substrate support 11 . In one embodiment, showerhead 13 forms at least a portion of the ceiling of plasma processing chamber 10 . The plasma processing chamber 10 has a plasma processing space 10 s defined by a showerhead 13 , side walls 10 a of the plasma processing chamber 10 and a substrate support 11 . The plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space 10s and at least one gas exhaust port for exhausting gas from the plasma processing space. Plasma processing chamber 10 is grounded. The showerhead 13 and substrate support 11 are electrically insulated from the plasma processing chamber 10 housing.
　基板支持部１１は、本体部１１１及びリングアセンブリ１１２を含む。本体部１１１は、基板Ｗを支持するための中央領域１１１ａと、リングアセンブリ１１２を支持するための環状領域１１１ｂとを有する。ウェハは基板Ｗの一例である。本体部１１１の環状領域１１１ｂは、平面視で本体部１１１の中央領域１１１ａを囲んでいる。基板Ｗは、本体部１１１の中央領域１１１ａ上に配置され、リングアセンブリ１１２は、本体部１１１の中央領域１１１ａ上の基板Ｗを囲むように本体部１１１の環状領域１１１ｂ上に配置される。従って、中央領域１１１ａは、基板Ｗを支持するための基板支持面とも呼ばれ、環状領域１１１ｂは、エッジリングアセンブリ１１２を支持するためのリング支持面とも呼ばれる。 The substrate support section 11 includes a body section 111 and a ring assembly 112 . The body portion 111 has a central region 111 a for supporting the substrate W and an annular region 111 b for supporting the ring assembly 112 . A wafer is an example of a substrate W; The annular region 111b of the body portion 111 surrounds the central region 111a of the body portion 111 in plan view. The substrate W is arranged on the central region 111 a of the main body 111 , and the ring assembly 112 is arranged on the annular region 111 b of the main body 111 so as to surround the substrate W on the central region 111 a of the main body 111 . Accordingly, the central region 111a is also referred to as a substrate support surface for supporting the substrate W, and the annular region 111b is also referred to as a ring support surface for supporting the edge ring assembly 112. FIG.
　一実施形態において、本体部１１１は、基台１１１０及び静電チャック１１１１を含む。基台１１１０は、導電性部材を含む。基台１１１０の導電性部材は下部電極として機能し得る。静電チャック１１１１は、基台１１１０の上に配置される。静電チャック１１１１は、セラミック部材１１１１ａとセラミック部材１１１１ａ内に配置される静電電極１１１１ｂとを含む。セラミック部材１１１１ａは、中央領域１１１ａを有する。一実施形態において、セラミック部材１１１１ａは、環状領域１１１ｂも有する。なお、環状静電チャックや環状絶縁部材のような、静電チャック１１１１を囲む他の部材が環状領域１１１ｂを有してもよい。この場合、リングアセンブリ１１２は、環状静電チャック又は環状絶縁部材の上に配置されてもよく、静電チャック１１１１と環状絶縁部材の両方の上に配置されてもよい。また、ＲＦ又はＤＣ電極がセラミック部材１１１１ａ内に配置されてもよく、この場合、ＲＦ又はＤＣ電極が下部電極として機能する。後述するバイアスＲＦ信号又はＤＣ信号がＲＦ又はＤＣ電極に接続される場合、ＲＦ又はＤＣ電極はバイアス電極とも呼ばれる。なお、基台１１１０の導電性部材とＲＦ又はＤＣ電極との両方が２つの下部電極として機能してもよい。 In one embodiment, the body portion 111 includes a base 1110 and an electrostatic chuck 1111 . Base 1110 includes a conductive member. A conductive member of the base 1110 can function as a bottom electrode. An electrostatic chuck 1111 is arranged on the base 1110 . The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. Ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have the annular region 111b. In this case, the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or may be placed on both the electrostatic chuck 1111 and the annular insulating member. An RF or DC electrode may also be placed within the ceramic member 1111a, in which case the RF or DC electrode serves as the bottom electrode. An RF or DC electrode is also referred to as a bias electrode when a bias RF signal or DC signal, described below, is connected to the RF or DC electrode. Note that both the conductive member of the base 1110 and the RF or DC electrode may function as the two bottom electrodes.
　リングアセンブリ１１２は、１又は複数の環状部材を含む。一実施形態において、１又は複数の環状部材は、１又は複数のエッジリングと少なくとも１つのカバーリングとを含む。エッジリングは、導電性材料又は絶縁材料で形成され、カバーリングは、絶縁材料で形成される。 Ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge ring is made of a conductive material or an insulating material, and the cover ring is made of an insulating material.
　また、基板支持部１１は、静電チャック１１１１、リングアセンブリ１１２及び基板のうち少なくとも１つをターゲット温度に調節するように構成される温調モジュールを含んでもよい。温調モジュールは、ヒータ、伝熱媒体、流路１１１０ａ、又はこれらの組み合わせを含んでもよい。流路１１１０ａには、ブラインやガスのような伝熱流体が流れる。一実施形態において、流路１１１０ａが基台１１１０ 内に形成され、１又は複数のヒータが静電チャック１１１１のセラミック部材１１１１ａ内に配置される。また、基板支持部１１は、基板Ｗの裏面と中央領域１１１ａとの間に伝熱ガスを供給するように構成された伝熱ガス供給部を含んでもよい。 Also, the substrate supporter 11 may include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature control module may include heaters, heat transfer media, channels 1110a, or combinations thereof. A heat transfer fluid, such as brine or gas, flows through flow path 1110a. In one embodiment, channels 1110a are formed in base 1110 and one or more heaters are located in ceramic member 1111a of electrostatic chuck 1111. As shown in FIG. Further, the substrate supporter 11 may include a heat transfer gas supply unit configured to supply a heat transfer gas between the back surface of the substrate W and the central region 111a.
　シャワーヘッド１３は、ガス供給部２０からの少なくとも１つの処理ガスをプラズマ処理空間１０ｓ内に導入するように構成される。シャワーヘッド１３は、少なくとも１つのガス供給口１３ａ、少なくとも１つのガス拡散室１３ｂ、及び複数のガス導入口１３ｃを有する。ガス供給口１３ａに供給された処理ガスは、ガス拡散室１３ｂを通過して複数のガス導入口１３ｃからプラズマ処理空間１０ｓ内に導入される。また、シャワーヘッド１３は、上部電極を含む。なお、ガス導入部は、シャワーヘッド１３に加えて、側壁１０ａに形成された１又は複数の開口部に取り付けられる１又は複数のサイドガス注入部（ＳＧＩ：Ｓｉｄｅ　Ｇａｓ　Ｉｎｊｅｃｔｏｒ）を含んでもよい。 The showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas introduction ports 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s through a plurality of gas introduction ports 13c. Showerhead 13 also includes an upper electrode. In addition to the showerhead 13, the gas introduction part may include one or more side gas injectors (SGI: Side Gas Injector) attached to one or more openings formed in the side wall 10a.
　ガス供給部２０は、少なくとも１つのガスソース２１及び少なくとも１つの流量制御器２２を含んでもよい。一実施形態において、ガス供給部２０は、少なくとも１つの処理ガスを、それぞれに対応のガスソース２１からそれぞれに対応の流量制御器２２を介してシャワーヘッド１３に供給するように構成される。各流量制御器２２は、例えばマスフローコントローラ又は圧力制御式の流量制御器を含んでもよい。さらに、ガス供給部２０は、少なくとも１つの処理ガスの流量を変調又はパルス化する１又はそれ以上の流量変調デバイスを含んでもよい。 The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22 . In one embodiment, gas supply 20 is configured to supply at least one process gas from respective gas sources 21 through respective flow controllers 22 to showerhead 13 . Each flow controller 22 may include, for example, a mass flow controller or a pressure controlled flow controller. Additionally, gas supply 20 may include one or more flow modulation devices that modulate or pulse the flow of at least one process gas.
　電源３０は、少なくとも１つのインピーダンス整合回路を介してプラズマ処理チャンバ１０に結合されるＲＦ電源３１を含む。ＲＦ電源３１は、ソースＲＦ信号及びバイアスＲＦ信号のような少なくとも１つのＲＦ信号（ＲＦ電力）を、少なくとも１つの下部電極及び／又は少なくとも１つの上部電極に供給するように構成される。これにより、プラズマ処理空間１０ｓに供給された少なくとも１つの処理ガスからプラズマが形成される。従って、ＲＦ電源３１は、プラズマ処理チャンバ１０において１又はそれ以上の処理ガスからプラズマを生成するように構成されるプラズマ生成部の少なくとも一部として機能し得る。また、バイアスＲＦ信号を少なくとも１つの下部電極に供給することにより、基板Ｗにバイアス電位が発生し、形成されたプラズマ中のイオン成分を基板Ｗに引き込むことができる。 Power supply 30 includes an RF power supply 31 coupled to plasma processing chamber 10 via at least one impedance matching circuit. RF power supply 31 is configured to supply at least one RF signal (RF power), such as a source RF signal and a bias RF signal, to at least one bottom electrode and/or at least one top electrode. Thereby, plasma is formed from at least one processing gas supplied to the plasma processing space 10s. Accordingly, RF power source 31 may function as at least part of a plasma generator configured to generate a plasma from one or more process gases in plasma processing chamber 10 . Also, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated in the substrate W, and ion components in the formed plasma can be drawn into the substrate W. FIG.
　一実施形態において、ＲＦ電源３１は、第１のＲＦ生成部３１ａ及び第２のＲＦ生成部３１ｂを含む。第１のＲＦ生成部３１ａは、少なくとも１つのインピーダンス整合回路を介して少なくとも１つの下部電極及び／又は少なくとも１つの上部電極に結合され、プラズマ生成用のソースＲＦ信号（ソースＲＦ電力）を生成するように構成される。一実施形態において、ソースＲＦ信号は、１０ＭＨｚ～１５０ＭＨｚの範囲内の周波数を有する。一実施形態において、第１のＲＦ生成部３１ａは、異なる周波数を有する複数のソースＲＦ信号を生成するように構成されてもよい。生成された１又は複数のソースＲＦ信号は、少なくとも１つの下部電極及び／又は少なくとも１つの上部電極に供給される。 In one embodiment, the RF power supply 31 includes a first RF generator 31a and a second RF generator 31b. The first RF generator 31a is coupled to at least one lower electrode and/or at least one upper electrode via at least one impedance matching circuit to generate a source RF signal (source RF power) for plasma generation. configured as In one embodiment, the source RF signal has a frequency within the range of 10 MHz to 150 MHz. In one embodiment, the first RF generator 31a may be configured to generate multiple source RF signals having different frequencies. One or more source RF signals generated are provided to at least one bottom electrode and/or at least one top electrode.
　第２のＲＦ生成部３１ｂは、少なくとも１つのインピーダンス整合回路を介して少なくとも１つの下部電極に結合され、バイアスＲＦ信号（バイアスＲＦ電力）を生成するように構成される。バイアスＲＦ信号の周波数は、ソースＲＦ信号の周波数と同じであっても異なっていてもよい。一実施形態において、バイアスＲＦ信号は、ソースＲＦ信号の周波数よりも低い周波数を有する。一実施形態において、バイアスＲＦ信号は、１００ｋＨｚ～６０ＭＨｚの範囲内の周波数を有する。一実施形態において、第２のＲＦ生成部３１ｂは、異なる周波数を有する複数のバイアスＲＦ信号を生成するように構成されてもよい。生成された１又は複数のバイアスＲＦ信号は、少なくとも１つの下部電極に供給される。また、種々の実施形態において、ソースＲＦ信号及びバイアスＲＦ信号のうち少なくとも１つがパルス化されてもよい。 The second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency within the range of 100 kHz to 60 MHz. In one embodiment, the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies. One or more bias RF signals generated are provided to at least one bottom electrode. Also, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.
　また、電源３０は、プラズマ処理チャンバ１０に結合されるＤＣ電源３２を含んでもよい。ＤＣ電源３２は、第１のＤＣ生成部３２ａ及び第２のＤＣ生成部３２ｂを含む。一実施形態において、第１のＤＣ生成部３２ａは、少なくとも１つの下部電極に接続され、第１のＤＣ信号を生成するように構成される。生成された第１のバイアスＤＣ信号は、少なくとも１つの下部電極に印加される。一実施形態において、第２のＤＣ生成部３２ｂは、少なくとも１つの上部電極に接続され、第２のＤＣ信号を生成するように構成される。生成された第２のＤＣ信号は、少なくとも１つの上部電極に印加される。 Power supply 30 may also include a DC power supply 32 coupled to plasma processing chamber 10 . The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to the at least one bottom electrode and configured to generate a first DC signal. A generated first bias DC signal is applied to at least one bottom electrode. In one embodiment, the second DC generator 32b is connected to the at least one top electrode and configured to generate a second DC signal. The generated second DC signal is applied to at least one top electrode.
　種々の実施形態において、第１及び第２のＤＣ信号のうち少なくとも１つがパルス化されてもよい。この場合、ＤＣに基づく電圧パルスのシーケンスが少なくとも１つの下部電極及び／又は少なくとも１つの上部電極に印加される。電圧パルスは、矩形、台形、三角形又はこれらの組み合わせのパルス波形を有してもよい。一実施形態において、ＤＣ信号から電圧パルスのシーケンスを生成するための波形生成部が第１のＤＣ生成部３２ａと少なくとも１つの下部電極との間に接続される。従って、第１のＤＣ生成部３２ａ及び波形生成部は、電圧パルス生成部を構成する。第２のＤＣ生成部３２ｂ及び波形生成部が電圧パルス生成部を構成する場合、電圧パルス生成部は、少なくとも１つの上部電極に接続される。電圧パルスは、正の極性を有してもよく、負の極性を有してもよい。また、電圧パルスのシーケンスは、１周期内に１又は複数の正極性電圧パルスと１又は複数の負極性電圧パルスとを含んでもよい。なお、第１及び第２のＤＣ生成部３２ａ，３２ｂは、ＲＦ電源３１に加えて設けられてもよく、第１のＤＣ生成部３２ａが第２のＲＦ生成部３１ｂに代えて設けられてもよい。 In various embodiments, at least one of the first and second DC signals may be pulsed. In this case, a sequence of DC-based voltage pulses is applied to at least one bottom electrode and/or at least one top electrode. The voltage pulses may have rectangular, trapezoidal, triangular, or combinations thereof pulse waveforms. In one embodiment, a waveform generator for generating a sequence of voltage pulses from a DC signal is connected between the first DC generator 32a and the at least one bottom electrode. Therefore, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulse may have a positive polarity or a negative polarity. Also, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses in one cycle. Note that the first and second DC generators 32a and 32b may be provided in addition to the RF power supply 31, and the first DC generator 32a may be provided instead of the second RF generator 31b. good.
　排気システム４０は、例えばプラズマ処理チャンバ１０の底部に設けられたガス排出口１０ｅに接続され得る。排気システム４０は、圧力調整弁及び真空ポンプを含んでもよい。圧力調整弁によって、プラズマ処理空間１０ｓ内の圧力が調整される。真空ポンプは、ターボ分子ポンプ、ドライポンプ又はこれらの組み合わせを含んでもよい。 The exhaust system 40 may be connected to a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10, for example. Exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. Vacuum pumps may include turbomolecular pumps, dry pumps, or combinations thereof.
　制御部２は、本開示において述べられる種々の工程をプラズマ処理装置１に実行させるコンピュータ実行可能な命令を処理する。制御部２は、ここで述べられる種々の工程を実行するようにプラズマ処理装置１の各要素を制御するように構成され得る。一実施形態において、制御部２の一部又は全てがプラズマ処理装置１に含まれてもよい。制御部２は、例えばコンピュータ２ａを含んでもよい。コンピュータ２ａは、例えば、処理部（ＣＰＵ：Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）２ａ１、記憶部２ａ２、及び通信インターフェース２ａ３を含んでもよい。処理部２ａ１は、記憶部２ａ２からプログラムを読み出し、読み出されたプログラムを実行することにより種々の制御動作を行うように構成され得る。このプログラムは、予め記憶部２ａ２に格納されていてもよく、必要なときに、媒体を介して取得されてもよい。取得されたプログラムは、記憶部２ａ２に格納され、処理部２ａ１によって記憶部２ａ２から読み出されて実行される。媒体は、コンピュータ２ａに読み取り可能な種々の記憶媒体であってもよく、通信インターフェース２ａ３に接続されている通信回線であってもよい。記憶部２ａ２は、ＲＡＭ（Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、ＲＯＭ（Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）、ＨＤＤ（Ｈａｒｄ　Ｄｉｓｋ　Ｄｒｉｖｅ）、ＳＳＤ（Ｓｏｌｉｄ　Ｓｔａｔｅ　Ｄｒｉｖｅ）、又はこれらの組み合わせを含んでもよい。通信インターフェース２ａ３は、ＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）等の通信回線を介してプラズマ処理装置１との間で通信してもよい。 The controller 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various steps described in this disclosure. Controller 2 may be configured to control elements of plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the controller 2 may be included in the plasma processing apparatus 1 . The control unit 2 may include, for example, a computer 2a. The computer 2a may include, for example, a processing unit (CPU: Central Processing Unit) 2a1, a storage unit 2a2, and a communication interface 2a3. Processing unit 2a1 can be configured to perform various control operations by reading a program from storage unit 2a2 and executing the read program. This program may be stored in the storage unit 2a2 in advance, or may be acquired via a medium when necessary. The acquired program is stored in the storage unit 2a2, read from the storage unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or may be a communication line connected to the communication interface 2a3. The storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).
＜プラズマ処理方法の一例＞
　図２は、一つの例示的実施形態に係るプラズマ処理方法（以下「本処理方法」ともいう。）を示すフローチャートである。図２に示すように、本処理方法は、基板を提供する工程ＳＴ１と、処理ガスを供給する工程ＳＴ２と、基板をエッチングする工程ＳＴ３とを含む。基板をエッチングする工程ＳＴ３は、第１領域をエッチングする工程ＳＴ３Ａ第２領域をエッチングする工程ＳＴ３Ｂ、第３領域をエッチングする工程ＳＴ３Ｃ、第４領域をエッチングする工程ＳＴ３Ｄ、第５流域をエッチングする工程ＳＴ３Ｅ、第６領域をエッチングする工程ＳＴ６Ｆを含む。 <Example of plasma treatment method>
FIG. 2 is a flow chart showing a plasma processing method (hereinafter also referred to as "this processing method") according to one exemplary embodiment. As shown in FIG. 2, this processing method includes a step ST1 of providing a substrate, a step ST2 of supplying a processing gas, and a step ST3 of etching the substrate. The step ST3 of etching the substrate includes a step ST3A of etching the first region, a step ST3B of etching the second region, a step ST3C of etching the third region, a step ST3D of etching the fourth region, and a step ST3D of etching the fifth region. ST3E, including step ST6F of etching the sixth region.
　各工程における処理は、図１に示すプラズマ処理システムで実行されてよい。以下では、制御部２がプラズマ処理装置１の各部を制御して、基板Ｗに対して本処理方法を実行する場合を例に説明する。 The processing in each step may be performed by the plasma processing system shown in FIG. An example in which the control unit 2 controls each unit of the plasma processing apparatus 1 to perform the present processing method on the substrate W will be described below.
（工程ＳＴ１：基板の提供）
　工程ＳＴ１において、基板Ｗは、プラズマ処理装置１のプラズマ処理空間１０ｓ内に提供される。基板Ｗは、基板支持部１１の上面に配置される。 (Process ST1: Provision of substrate)
In step ST<b>1 , the substrate W is provided within the plasma processing space 10 s of the plasma processing apparatus 1 . The substrate W is placed on the upper surface of the substrate support portion 11 .
　図３は、工程ＳＴ１で提供される基板Ｗの断面構造の一例を示す図である。基板Ｗは、下地膜ＵＦ上に、シリコン含有膜ＳＦ及びマスク膜ＭＦがこの順で形成されている。基板Ｗは、例えば、ＤＲＡＭ、３Ｄ－ＮＡＮＤフラッシュメモリ等の半導体メモリデバイスを含む半導体デバイスの製造に用いられてよい。 FIG. 3 is a diagram showing an example of the cross-sectional structure of the substrate W provided in step ST1. In the substrate W, a silicon-containing film SF and a mask film MF are formed in this order on a base film UF. The substrate W may be used, for example, in the manufacture of semiconductor devices including semiconductor memory devices such as DRAMs, 3D-NAND flash memories and the like.
　下地膜ＵＦは、例えば、シリコンウェハやシリコンウェハ上に形成された有機膜、誘電体膜、金属膜、半導体膜等でよい。下地膜ＵＦは、複数の膜が積層されて構成されてよい。 The base film UF may be, for example, a silicon wafer or an organic film, dielectric film, metal film, semiconductor film, or the like formed on a silicon wafer. The base film UF may be configured by laminating a plurality of films.
　シリコン含有膜ＳＦは、本処理方法におけるエッチング対象膜である。シリコン含有膜ＳＦは、一例では、シリコン酸化膜、シリコン窒化膜、シリコン酸窒化膜でよい。シリコン含有膜ＳＦは、複数の膜が積層されて構成されてよい。例えば、シリコン含有膜ＳＦは、シリコン酸化膜と多結晶シリコン膜とが交互に積層されて構成されてよい。また例えば、シリコン含有膜ＳＦは、シリコン酸化膜とシリコン窒化膜とが交互に積層されて構成されてよい。 The silicon-containing film SF is a film to be etched in this processing method. The silicon-containing film SF may be, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The silicon-containing film SF may be configured by laminating a plurality of films. For example, the silicon-containing film SF may be configured by alternately stacking a silicon oxide film and a polycrystalline silicon film. Further, for example, the silicon-containing film SF may be configured by alternately stacking a silicon oxide film and a silicon nitride film.
　マスク膜ＭＦは、例えば、アモルファスカーボン膜、スピンオンカーボン膜、フォトレジスト膜等の炭素含有膜でよい。マスク膜ＭＦは、１つの層からなる単層マスクでも、２つ以上の層からなる多層マスクであってもよい。マスク膜ＭＦは、少なくとも一つの開口ＯＰを有する。開口ＯＰは、基板Ｗの平面視、すなわち、基板Ｗを図３の上から下に向かう方向に見た場合において、任意の形状を有してよい。当該形状は、例えば、円、楕円、矩形、線やこれらの１種類以上を組み合わせた形状であってよい。マスク膜ＭＦは、複数の開口ＯＰを有してよい。 The mask film MF may be, for example, a carbon-containing film such as an amorphous carbon film, a spin-on carbon film, or a photoresist film. The mask film MF may be a single layer mask consisting of one layer or a multilayer mask consisting of two or more layers. Mask film MF has at least one opening OP. The opening OP may have any shape when the substrate W is viewed from above, that is, when the substrate W is viewed from the top to the bottom in FIG. The shape may be, for example, a circle, an ellipse, a rectangle, a line, or a combination of one or more of these. The mask film MF may have multiple openings OP.
（工程ＳＴ２：処理ガスの供給）
　工程ＳＴ２において、処理ガスがプラズマ処理空間１０ｓ内に供給される。処理ガスは、基板Ｗに形成されたシリコン含有膜ＳＦをエッチングするために用いられるガスである。処理ガスの種類は、シリコン含有膜ＳＦの材料、マスク膜ＭＦの材料、下地膜ＵＦの材料、マスク膜ＭＦが有するパターン、エッチングの深さ等に基づいて適宜選択されてよい。 (Process ST2: Supply of processing gas)
In step ST2, a processing gas is supplied into the plasma processing space 10s. The processing gas is a gas used for etching the silicon-containing film SF formed on the substrate W. As shown in FIG. The type of processing gas may be appropriately selected based on the material of the silicon-containing film SF, the material of the mask film MF, the material of the base film UF, the pattern of the mask film MF, the depth of etching, and the like.
　処理ガスは、例えば、ＣｘＦｙガス及びＣｓＨｔＦｕガスのいずれか一方又は双方を含んでよい。ここで、ｘ、ｙ、ｓ、ｔ，ｕは正の整数である。ＣｘＦｙガスは、Ｃ４Ｆ６ガス、Ｃ４Ｆ８ガス、Ｃ３Ｆ６ガス及びＣ７Ｆ８ガスからなる群から選択される少なくとも１種でよい。ＣｓＨｔＦｕガスは、ＣＨ２Ｆ２ガス又はＣＨ３Ｆガスでよい。処理ガスは、Ｈ２ガスやＣＨ４ガス等の水素含有ガスを含んでよい。 The processing gas may include, for example , one or both of CxFy gas and CsHtFu gas . where x, y, s, t and u are positive integers. The CxFy gas may be at least one selected from the group consisting of C4F6 gas, C4F8 gas, C3F6 gas and C7F8 gas . The CsHtFu gas may be CH2F2 gas or CH3F gas . The process gas may include a hydrogen-containing gas such as H2 gas or CH4 gas.
（工程ＳＴ３：エッチング）
　工程ＳＴ３において、第１のＲＦ生成部３１ａからソースＲＦ信号（ＲＦ電力）が下部電極及び／又は上部電極に供給される。また第２のＲＦ生成部３１ｂから、バイアスＲＦ信号が下部電極に供給される。これにより、プラズマ処理空間１０ｓに供給された処理ガスからプラズマが生成されるとともに基板Ｗにバイアス電位が発生する。生成されたプラズマ中のイオン、ラジカルといった活性種が基板Ｗに引きよせられ、シリコン含有膜ＳＦがエッチングされる。なお、ソースＲＦ信号の供給を開始するタイミングとバイアスＲＦ信号の供給を開始するタイミングとは、同時でよく、また異なってもよい。 (Step ST3: Etching)
In step ST3, a source RF signal (RF power) is supplied from the first RF generator 31a to the lower electrode and/or the upper electrode. A bias RF signal is supplied to the lower electrode from the second RF generator 31b. As a result, plasma is generated from the processing gas supplied to the plasma processing space 10s, and a bias potential is generated on the substrate W as well. Active species such as ions and radicals in the generated plasma are attracted to the substrate W, and the silicon-containing film SF is etched. The timing to start supplying the source RF signal and the timing to start supplying the bias RF signal may be the same or different.
　工程ＳＴ３の工程ＳＴ３Ａ～工程ＳＴ３Ｆにおいては、シリコン含有膜ＳＦのエッチングの進行に伴って、ソースＲＦ信号及びバイアスＲＦ信号の電力レベルを変化させる。この点を図４Ａ～図４Ｆ、図５Ａ～図５Ｆ、及び、図６Ａ～図６Ｆを用いて説明する。なお、エッチングの進行は、エッチング深さの伸長やエッチング時間の経過に基づいて判断してよい。 In steps ST3A to ST3F of step ST3, the power levels of the source RF signal and the bias RF signal are changed as the etching of the silicon-containing film SF progresses. This point will be described with reference to FIGS. 4A to 4F, 5A to 5F, and 6A to 6F. The progress of etching may be determined based on the elongation of the etching depth or the lapse of etching time.
　図４Ａ～図４Ｆは、それぞれ工程ＳＴ３Ａ～工程ＳＴ３Ｆにおける処理後の基板Ｗの断面構造の一例を示す図である。 4A to 4F are diagrams showing examples of cross-sectional structures of the substrate W after being processed in steps ST3A to ST3F, respectively.
　図５Ａ～図５Ｆは、それぞれ、工程ＳＴ３Ａ～工程ＳＴ３ＦにおけるソースＲＦ信号の一例を示すタイミングチャートである。図５Ａ～図５Ｆにおいて、横軸は時間を示す。また縦軸は、ソースＲＦ信号の電力レベルの実効値を示す。「Ｌ１１」「Ｌ１２」「Ｌ１３」「Ｌ１４」は、「Ｈ１」で示す電力レベルよりも低いことを示す。またＬ１１、Ｌ１２、Ｌ１３、Ｌ１４には、Ｌ１１＞Ｌ１２＞Ｌ１３＞Ｌ１４の関係が成り立つ（すなわち、Ｌ１１、Ｌ１２、Ｌ１３、Ｌ１４の中では、Ｌ１１の電力レベルが最も高く、Ｌ１４の電力レベルが最も低い）。「Ｌ１４」は、電力レベルが０Ｗである場合、すなわち信号が供給されていない場合を含む。図５Ａ～図５Ｆに示すとおり、すなわち、ソースＲＦ信号は、Ｈ１の電力レベル（第１の電力）を有するＨ１期間（第１の期間）とＨ１よりも低いＬ１１、Ｌ１２、Ｌ１３又はＬ１４の電力レベル（第２の電力）を有するＬ１期間（第２の期間）とを交互に繰り返すパルス波である。 5A to 5F are timing charts showing examples of source RF signals in steps ST3A to ST3F, respectively. 5A to 5F, the horizontal axis indicates time. Also, the vertical axis indicates the effective value of the power level of the source RF signal. “L 11 ”, “L 12 ”, “L 13 ”, and “L 14 ” indicate power levels lower than those indicated by “H 1 ”. In addition, L 11 >L 12 >L 13 > L 14 holds between L 11 , L 12 , L 13 and L 14 ( that is, L 11 has the highest power level and L 14 has the lowest power level). “L 14 ” includes when the power level is 0 W, ie no signal is applied. As shown in FIGS. 5A-5F, ie, the source RF signal has a H1 period (first period) with a power level of H 1 (first power) and L 11 , L 12 , L lower than H 1 . A pulse wave that alternates with an L1 period (second period) having a power level of 13 or L 14 (second power).
　図６Ａ～図６Ｆは、それぞれ工程ＳＴ３Ａ～工程ＳＴ３ＦにおけるバイアスＲＦ信号の一例を示すタイミングチャートである。図６Ａ～図６Ｆにおいて、横軸は時間を示す。また縦軸は、バイアスＲＦ信号の電力レベルの実効値を示す。「Ｌ２１」「Ｌ２２」「Ｌ２３」は、「Ｈ２」で示す電力レベルよりも低いことを示す。またＬ２１、Ｌ２２、Ｌ２３には、Ｌ２１＜Ｌ２２＜Ｌ２３の関係が成り立つ（すなわち、Ｌ２１、Ｌ２２、Ｌ２３の中では、Ｌ２１の電力レベルが最も低く、Ｌ２３の電力レベルが最も高い）。「Ｌ２１」は、電力レベルが０Ｗである場合、すなわち信号が供給されていない場合を含む。バイアスＲＦ信号は、Ｈ２の電力レベル（第３の電力）を有するＨ２期間（第３の期間）とＨ２よりも低いＬ２１、Ｌ２２又はＬ２３の電力レベル（第４の電力）を有するＬ２期間（第４の期間）とを交互に含むパルス波である。 6A to 6F are timing charts showing examples of bias RF signals in steps ST3A to ST3F, respectively. 6A to 6F, the horizontal axis indicates time. The vertical axis indicates the effective value of the power level of the bias RF signal. “L 21 ”, “L 22 ”, and “L 23 ” indicate lower power levels than indicated by “H 2 ”. In addition, L 21 , L 22 and L 23 have the relationship of L 21 <L 22 <L 23 (that is, among L 21 , L 22 and L 23 , L 21 has the lowest power level and L 23 highest power level). “L 21 ” includes when the power level is 0 W, ie no signal is being supplied. The bias RF signal has an H2 period (third period) having a power level of H2 (third power) and a power level of L21 , L22 or L23 lower than H2 (fourth power). It is a pulse wave that alternately includes an L2 period (fourth period).
　（工程ＳＴ３Ａ：第１領域のエッチング）
　工程ＳＴ３Ａは、エッチングの開始から、エッチングにより形成される凹部ＲＣのエッチング深さがｄ１になるまでの第１領域で実行される（図４Ａ参照）。凹部ＲＣは、シリコン含有膜ＳＦのうちマスク膜ＭＦの開口ＯＰに対応する部分である。工程ＳＴ３Ａでは、ソースＲＦ信号として、Ｈ１の電力レベルを有するＨ１期間とＨ１よりも低い電力レベルＬ１１を有するＬ１期間とを交互に含むパルス波を用いる（図５Ａ参照）。またバイアスＲＦ信号として、Ｈ２の電力レベルを有するＨ２期間とＨ２よりも低い電力レベルＬ２１を有するＬ２期間とを交互に含むパルス波を用いる（図６Ａ参照）。 (Step ST3A: Etching of First Region)
The step ST3A is performed in the first region from the start of etching until the etching depth of the recess RC formed by etching reaches d1 (see FIG. 4A). The recess RC is a portion of the silicon-containing film SF corresponding to the opening OP of the mask film MF. In step ST3A, a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L11 lower than H1 is used as the source RF signal (see FIG. 5A). Also, as the bias RF signal, a pulse wave that alternately includes H2 periods having a power level of H2 and L2 periods having a power level L21 lower than H2 is used (see FIG. 6A).
　（工程ＳＴ３Ｂ：第２領域のエッチング）
　工程ＳＴ３Ｂは、凹部ＲＣのエッチング深さがｄ２になるまでの第２領域で実行される（図４Ｂ参照）。エッチング深さｄ２は、エッチング深さｄ１より深く、ｄ２＞ｄ１の関係が成り立つ。工程ＳＴ３Ｂでは、ソースＲＦ信号として、Ｈ１の電力レベルを有するＨ１期間とＨ１よりも低い電力レベルＬ１２を有するＬ１期間とを交互に含むパルス波を用いる（図５Ｂ参照）。工程ＳＴ３ＢのソースＲＦ信号の電力レベルＬ１２は、工程ＳＴ３ＡソースＲＦ信号の電力レベルＬ１１よりも低い。バイアスＲＦ信号としては、工程ＳＴ３Ａと同一のパルス波を用いる（図６Ｂ参照）。 (Step ST3B: Etching of Second Region)
The step ST3B is performed in the second region until the etching depth of the recess RC reaches d2 (see FIG. 4B). The etching depth d2 is deeper than the etching depth d1, and the relationship of d2>d1 holds. In step ST3B, a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L12 lower than H1 is used as the source RF signal (see FIG. 5B). The power level L12 of the source RF signal of step ST3B is lower than the power level L11 of the source RF signal of step ST3A. As the bias RF signal, the same pulse wave as in step ST3A is used (see FIG. 6B).
　（工程ＳＴ３Ｃ：第３領域のエッチング）
　工程ＳＴ３Ｃは、凹部ＲＣのエッチング深さがｄ３になるまでの第３領域で実行される（図４Ｃ参照）。エッチング深さｄ３は、エッチングｄ２より深く、ｄ３＞ｄ２の関係が成り立つ。エッチング深さｄ３は、例えば、工程ＳＴ３でエッチングするべき深さの半分でよい。エッチング深さｄ３は、一例ではシリコン含有膜ＳＦの膜厚の半分の大きさでよい。工程ＳＴ３Ｃでは、ソースＲＦ信号として、Ｈ１の電力レベルを有するＨ１期間とＨ１よりも低い電力レベルＬ１３を有するＬ１期間とを交互に含むパルス波を用いる（図５Ｃ参照）。工程ＳＴ３ＣのソースＲＦ信号の電力レベルＬ１３は、工程ＳＴ３ＢのソースＲＦ信号の電力レベルＬ１２よりも低い。バイアスＲＦ信号としては、工程ＳＴ３Ａや工程ＳＴ３Ｂと同一のパルス波を用いる（図６Ｃ参照）。 (Step ST3C: etching of the third region)
The step ST3C is performed in the third region until the etching depth of the recess RC reaches d3 (see FIG. 4C). The etching depth d3 is deeper than the etching depth d2, and the relationship of d3>d2 holds. The etching depth d3 may be, for example, half the depth to be etched in step ST3. For example, the etching depth d3 may be half the thickness of the silicon-containing film SF. In step ST3C, a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L13 lower than H1 is used as the source RF signal (see FIG. 5C). The power level L13 of the source RF signal of step ST3C is lower than the power level L12 of the source RF signal of step ST3B. As the bias RF signal, the same pulse wave as in steps ST3A and ST3B is used (see FIG. 6C).
　（工程ＳＴ３Ｄ：第４領域のエッチング）
　工程ＳＴ３Ｄは、凹部ＲＣのエッチング深さがｄ４になるまでの第４領域で実行される（図４Ｄ参照）。エッチング深さｄ４は、エッチング深さｄ３より深く、ｄ４＞ｄ３の関係が成り立つ。工程ＳＴ３Ｄでは、ソースＲＦ信号として、Ｈ１の電力レベルを有するＨ１期間とＨ１よりも低い電力レベルＬ１４を有するＬ１期間とを交互に含むパルス波を用いる（図５Ｄ参照）。工程ＳＴ３ＤのソースＲＦ信号の電力レベルＬ１４は、工程ＳＴ３ＣのソースＲＦ信号の電力レベルＬ１３よりも低い。バイアスＲＦ信号としては、工程ＳＴ３Ａ～工程ＳＴ３Ｃと同一のパルス波を用いる（図６Ｄ参照）。 (Step ST3D: Etching of fourth region)
The step ST3D is performed in the fourth region until the etching depth of the recess RC reaches d4 (see FIG. 4D). The etching depth d4 is deeper than the etching depth d3, and the relationship of d4>d3 holds. In step ST3D, a pulse wave that alternately includes H1 periods having a power level of H1 and L1 periods having a power level L14 lower than H1 is used as the source RF signal (see FIG. 5D). The power level L14 of the source RF signal of step ST3D is lower than the power level L13 of the source RF signal of step ST3C. As the bias RF signal, the same pulse wave as in steps ST3A to ST3C is used (see FIG. 6D).
　（工程ＳＴ３Ｅ：第５領域のエッチング）
　工程ＳＴ３Ｅは、凹部ＲＣのエッチング深さがｄ５になるまでの第５領域で実行される（図４Ｅ参照）。エッチング深さｄ５は、エッチング深さｄ４より深く、ｄ２＞ｄ１の関係が成り立つ。工程ＳＴ３Ｅでは、ソースＲＦ信号として、工程ＳＴ３Ｄと同一のパルス波を用いる（図５Ｅ参照）。バイアスＲＦ信号としては、Ｈ２の電力レベルを有するＨ２期間とＨ２よりも低い電力レベルＬ２２を有するＬ２期間とを交互に含むパルス波を用いる（図６Ｅ参照）。工程ＳＴ３ＥのバイアスＲＦ信号の電力レベルＬ２２は、工程ＳＴ３Ａ～工程ＳＴ３ＤのバイアスＲＦ信号の電力レベルＬ２１よりも高い。 (Step ST3E: Etching of fifth region)
The step ST3E is performed in the fifth region until the etching depth of the recess RC reaches d5 (see FIG. 4E). The etching depth d5 is deeper than the etching depth d4, and the relationship of d2>d1 holds. In step ST3E, the same pulse wave as in step ST3D is used as the source RF signal (see FIG. 5E). As the bias RF signal, a pulse wave containing alternating H2 periods with a power level of H2 and L2 periods with a power level L22 lower than H2 is used (see FIG. 6E). The power level L22 of the bias RF signal in step ST3E is higher than the power level L21 of the bias RF signal in steps ST3A to ST3D.
　（工程ＳＴ３Ｆ：第６領域のエッチング）
　工程ＳＴ３Ｆは、凹部ＲＣのエッチング深さがｄ６になるまでの第６領域で実行される（図４Ｆ参照）。エッチング深さｄ６は、エッチング深さｄ５より深く、ｄ６＞ｄ５の関係が成り立つ。エッチング深さｄ６は、一例では、シリコン含有膜ＳＦの膜厚であり、この場合、工程ＳＴ３Ｆは、凹部ＲＣの底部が下地膜ＵＦに到達するまで実行される。この状態における凹部ＲＣのアスペクト比は、例えば、２０以上であってよく、３０以上、４０以上、５０以上、又は１００以上であってもよい。工程ＳＴ３Ｆでは、ソースＲＦ信号として、工程ＳＴ３Ｄや工程ＳＴ３Ｅと同一のパルス波を用いる（図５Ｆ参照）。バイアスＲＦ信号としては、Ｈ２の電力レベルを有するＨ２期間とＨ２よりも低い電力レベルＬ２３を有するＬ２期間とを交互に含むパルス波を用いる（図６Ｅ参照）。工程ＳＴ３ＦのバイアスＲＦ信号の電力レベルＬ２３は、工程ＳＴ３ＥのバイアスＲＦ信号の電力レベルＬ２２よりも高い。 (Step ST3F: Etching of sixth region)
The step ST3F is performed in the sixth region until the etching depth of the recess RC reaches d6 (see FIG. 4F). The etching depth d6 is deeper than the etching depth d5, and the relationship of d6>d5 holds. The etching depth d6 is, for example, the film thickness of the silicon-containing film SF. In this case, the step ST3F is performed until the bottom of the recess RC reaches the underlying film UF. The aspect ratio of the recess RC in this state may be, for example, 20 or more, 30 or more, 40 or more, 50 or more, or 100 or more. In step ST3F, the same pulse wave as in steps ST3D and ST3E is used as the source RF signal (see FIG. 5F). As the bias RF signal, a pulse wave containing alternating H2 periods with a power level of H2 and L2 periods with a power level L23 lower than H2 is used (see FIG. 6E). The power level L23 of the bias RF signal in step ST3F is higher than the power level L22 of the bias RF signal in step ST3E.
　工程ＳＴ３において、ソースＲＦ信号のパルス波のデューティ比、すなわち、Ｈ１期間及びＬ１期間に占めるＨ１期間の割合は、２０％以上８０％以下でよい。またバイアスＲＦ信号のパルス波のデューティ比、すなわちＨ２期間及びＬ２期間に占めるＨ２期間の割合は、２０％以上８０％以下でよい。ソースＲＦ信号のＨ１期間は、バイアスＲＦ信号のＨ２期間と同期してよく、また同期しなくてもよい。ソースＲＦ信号のＨ１期間の時間長は、バイアスＲＦ信号のＨ２期間の時間長と同一でよく、また異なってもよい。ソースＲＦ信号のＨ１期間の一部又は全部は、バイアスＲＦ信号のＨ２期間と重複してよい。 In step ST3, the duty ratio of the pulse wave of the source RF signal, that is, the ratio of the H1 period to the H1 period and the L1 period may be 20% or more and 80% or less. Also, the duty ratio of the pulse wave of the bias RF signal, that is, the ratio of the H2 period to the H2 period and the L2 period may be 20% or more and 80% or less. The H1 period of the source RF signal may or may not be synchronous with the H2 period of the bias RF signal. The time length of the H1 period of the source RF signal may be the same as or different from the time length of the H2 period of the bias RF signal. Part or all of the H1 period of the source RF signal may overlap with the H2 period of the bias RF signal.
　工程ＳＴ３においては、ソースＲＦ信号のＨ１期間の電力レベルＨ１に対するＬ１期間の電力レベルは、工程ＳＴ３Ａ～工程ＳＴ３Ｄにかけて段階的に減少し、工程ＳＴ３Ｄ～工程３Ｆにおいて最も低くなってよい（図５Ａ～図５Ｆ参照）。これにより、工程ＳＴ３Ａ～工程ＳＴ３Ｃ、すなわち凹部ＲＣの深さがより浅い領域のエッチングでは、この順で高密度のプラズマが生成される。また工程ＳＴ３Ｄ～工程３Ｆ、すなわち、凹部ＲＣの深さがより深い領域のエッチングでは、工程ＳＴ３Ａ～工程ＳＴ３Ｃに比べて低密度のプラズマが生成される。 In step ST3, the power level of the source RF signal during the L1 period with respect to the power level H1 during the H1 period may decrease stepwise from step ST3A to step ST3D and become lowest in step ST3D to step 3F (FIG. 5A). (see FIG. 5F). As a result, high-density plasma is generated in this order in steps ST3A to ST3C, ie, in the etching of the shallower region of the recess RC. In steps ST3D to 3F, that is, in the etching of the region where the recess RC is deeper, plasma with a lower density than in steps ST3A to ST3C is generated.
　工程ＳＴ３においては、バイアスＲＦ信号のＨ２期間の電力レベルＨ２に対するＬ２期間の電力レベルは、工程ＳＴ３Ａ～工程ＳＴ３Ｄにおいて最も低くなり、工程ＳＴ３Ｄ～工程ＳＴ３Ｆにかけて段階的に増加してよい（図６Ａ～図６Ｆ参照）。これにより、工程ＳＴ３Ａ～工程ＳＴ３Ｄ、すなわち凹部ＲＣの深さがより浅い領域のエッチングでは工程ＳＴ３Ｅ～工程ＳＴ３Ｆ、すなわち凹部ＲＣの深さがより深い領域のエッチングに比べて低いバイアス電位が基板Ｗに生じる。また工程ＳＴ３Ｆは、工程ＳＴ３Ｅに比べてより高いバイアス電位が基板Ｗに生じる。 In step ST3, the power level of the bias RF signal during the L2 period with respect to the power level H2 during the H2 period may be the lowest in steps ST3A to ST3D and increase stepwise from step ST3D to step ST3F (FIG. 6A). (see FIG. 6F). As a result, a lower bias potential is applied to the substrate W in steps ST3A to ST3D, ie, the etching of the region where the recess RC is shallower than in the steps ST3E to ST3F, ie, the etching of the region where the recess RC is deeper. occur. Further, a higher bias potential is generated on the substrate W in step ST3F than in step ST3E.
　なお、工程ＳＴ３において、ソースＲＦ信号のＬ１期間の電力レベルを段階的に減少させている間、すなわち、工程ＳＴ３Ａ～工程ＳＴ３Ｄでは、バイアスＲＦ信号のＬ２期間の電力レベルは一定にしてよい。また、バイアスＲＦ信号のＬ２期間の電力レベルを段階的に増加させている間、すなわち工程ＳＴ３Ｄ～工程ＳＴ３Ｆでは、ソースＲＦ信号のＬ１期間の電力レベルは一定にしてよい。 In step ST3, while the power level of the source RF signal during the L1 period is gradually decreased, that is, in steps ST3A to ST3D, the power level of the bias RF signal during the L2 period may be kept constant. Further, while the power level of the bias RF signal during the L2 period is increased stepwise, that is, in steps ST3D to ST3F, the power level of the source RF signal during the L1 period may be kept constant.
　以上によれば、工程ＳＴ３においては、凹部ＲＣの深さがより浅い箇所では、より高密度のプラズマかつより低いバイアス電位でのエッチングがされ得る。高密度のプラズマでは処理ガス中のＣｘＦｙガス及び／又はＣｓＨｔＦｕガス解離が促進され、より吸着係数の高い分子が生成されやすくなる。そのためマスク膜ＭＦや凹部ＲＣの側壁に付着する反応生成物の量が増加し得る。他方、高密度のプラズマでは基板Ｗに向かうイオンの流れが減少し、また低いバイアス電位により、マスク膜ＭＦや凹部ＲＣの側壁に対するスパッタリングが低減される。以上により、凹部ＲＣの深さが浅い領域では、マスク膜ＭＦや凹部ＲＣの側壁に保護膜を形成することが容易になる。この保護膜は、工程ＳＴ３の以降のエッチング（凹部ＲＣの深さがより深い領域でのエッチングも含む）において、凹部ＲＣの側壁を保護し得る。よって、凹部ＲＣの開口幅が一部で広くなるボーイングが抑制され得る。 According to the above, in the step ST3, the shallower portion of the recess RC can be etched with a higher density plasma and a lower bias potential. High - density plasma accelerates the dissociation of CxFy gas and/or CsHtFu gas in the process gas, making it easier to generate molecules with higher adsorption coefficients. Therefore, the amount of reaction products adhering to the mask film MF and the sidewalls of the recess RC may increase. On the other hand, the high-density plasma reduces the flow of ions toward the substrate W, and the low bias potential reduces sputtering on the mask film MF and sidewalls of the recess RC. As described above, it becomes easy to form the protective film on the mask film MF and the side walls of the recess RC in the shallow region of the recess RC. This protective film can protect the side walls of the recess RC in etching after step ST3 (including etching in a region where the depth of the recess RC is deeper). Therefore, bowing in which the width of the opening of the recess RC is partially widened can be suppressed.
　また工程ＳＴ３においては、凹部ＲＣの深さが深い領域では、より低密度のプラズマかつより高いバイアス電位でのエッチングがされ得る。低密度のプラズマでは処理ガス中のＣｘＦｙガス及び／又はＣｓＨｔＦｕガス解離が促進されにくく、吸着係数の高い分子が生成されにくい。そのためマスク膜ＭＦや凹部ＲＣの側壁に付着する反応生成物の量が減少し得る。これにより、マスク膜ＭＦや凹部ＲＣの開口が狭まることが抑制され、凹部ＲＣに入射したイオンの入射角が変化することが抑制され得る。また、高密度のプラズマにより凹部ＲＣの底部に向かうイオンの流れが増加し得る。さらに、高いバイアス電位でエッチングを行うため、凹部ＲＣに入射するイオンの入射角がより垂直に近くなり得る。以上より、凹部ＲＣの深さが深い箇所において、凹部ＲＣの底部幅（ボトムＣＤ）が狭くなることが抑制され得る。 Further, in the step ST3, the deep region of the recess RC can be etched with a lower density plasma and a higher bias potential. In the low-density plasma, dissociation of CxFy gas and/or CsHtFu gas in the processing gas is difficult to promote, and molecules with high adsorption coefficients are difficult to generate . Therefore, the amount of reaction products adhering to the mask film MF and the sidewalls of the recesses RC can be reduced. As a result, narrowing of the openings of the mask film MF and the recesses RC can be suppressed, and changes in the incident angle of the ions entering the recesses RC can be suppressed. Also, the high density plasma may increase the flow of ions toward the bottom of the recess RC. Furthermore, since etching is performed at a high bias potential, the incident angle of ions entering the recess RC can be closer to the vertical. As described above, it is possible to prevent the bottom width (bottom CD) of the recess RC from being narrowed at a portion where the depth of the recess RC is deep.
　上述のとおり、工程ＳＴ３においては、ソースＲＦ信号のＬ１期間の電力レベルを段階的に減少させ、その後、バイアスＲＦ信号のＬ２期間の電力レベルを段階的に増加させてよい。一例では、工程ＳＴ３において、ソースＲＦ信号のＬ１期間の電力レベルを一定に保ち、バイアスＲＦ信号のＬ２期間の電力レベルのみを段階的に増加させてよい。また、ソースＲＦ信号のＬ１期間の電力レベルのみを段階的に減少させ、バイアスＲＦ信号のＬ２期間の電力レベルを一定に保ってもよい。 As described above, in step ST3, the power level of the source RF signal during the L1 period may be decreased in stages, and then the power level of the bias RF signal during the L2 period may be increased in stages. In one example, in step ST3, the power level of the source RF signal during the L1 period may be kept constant, and only the power level of the bias RF signal during the L2 period may be increased stepwise. Alternatively, only the power level of the source RF signal during the L1 period may be stepwise decreased while the power level of the bias RF signal during the L2 period may be kept constant.
　上述のとおり、工程ＳＴ３においては、ソースＲＦ信号のパルス波及びバイアスＲＦ信号のパルス波を用いてよい。一例では、ソースＲＦ信号及びバイアスＲＦ信号のいずれかは、Ｈ１期間やＬ１期間等を有しない連続波としてよい。例えば、ソースＲＦ信号の連続波とバイアスＲＦ信号のパルス波を用いてよい。この場合、工程ＳＴ３Ａ～工程ＳＴ３Ｄにおいて、ソースＲＦ信号の連続波の電力レベルを段階的に減少させ、工程ＳＴ３Ｄ～工程ＳＴ３Ｆにおいて、バイアスＲＦ信号のＬ２期間の電力レベルを段階的に増加させてよい。また例えば、ソースＲＦ信号のパルス波とバイアスＲＦ信号の連続波を用いてよい。この場合、工程ＳＴ３Ａ～工程ＳＴ３Ｄにおいて、ソースＲＦ信号のＬ１期間の電力レベルを段階的に減少させ、工程ＳＴ３Ｅ～工程ＳＴ３Ｆにおいて、バイアスＲＦ信号の連続波の電力レベルを段階的に増加させてよい。 As described above, in step ST3, the pulse wave of the source RF signal and the pulse wave of the bias RF signal may be used. In one example, either the source RF signal or the bias RF signal may be continuous waves with no H1, L1, etc. periods. For example, a continuous wave source RF signal and a pulsed bias RF signal may be used. In this case, in steps ST3A to ST3D, the power level of the continuous wave of the source RF signal may be stepwise decreased, and in steps ST3D to ST3F, the power level of the L2 period of the bias RF signal may be stepwise increased. . Alternatively, for example, a pulsed source RF signal and a continuous biased RF signal may be used. In this case, in steps ST3A to ST3D, the power level of the L1 period of the source RF signal may be stepwise decreased, and in steps ST3E to ST3F, the power level of the continuous wave of the bias RF signal may be stepwise increased. .
　上述のとおり、工程ＳＴ３においては、下部電極に供給するバイアス信号（電力）として、バイアスＲＦ信号を用いてよい。一例では、第１のＤＣ生成部３２ａからバイアスＤＣ信号として負極性の直流電圧を下部電極に供給してよい。この場合、バイアスＤＣ信号の電圧レベルは、負極性の直流電圧の絶対値の実効値である。バイアスＤＣ信号は、パルス波でよく、また連続波でもよい。 As described above, in step ST3, a bias RF signal may be used as the bias signal (power) supplied to the lower electrode. In one example, a negative DC voltage may be supplied to the lower electrode as a bias DC signal from the first DC generator 32a. In this case, the voltage level of the bias DC signal is the effective value of the absolute value of the negative DC voltage. The bias DC signal may be pulsed or continuous wave.
　図７Ａ～図７Ｆは、それぞれ工程ＳＴ３Ａ～工程ＳＴ３ＦにおけるバイアスＤＣ信号の一例を示すタイミングチャートである。図７Ａ～図７Ｆにおいて、横軸は時間を示す。また縦軸は、バイアスＤＣ信号の電圧レベルを示す。図７Ａ～図７Ｆに示す例において、バイアスＤＣ信号は、Ｈ３期間において、負電圧パルスのシーケンスを有する。負電圧パルスのシーケンスは、例えば、１００ｋＨｚから５００ｋＨｚまでの範囲内にあるパルス周波数を有する。負電圧パルスは、Ｖ１の電圧レベル（図７Ａ～７Ｄ）、Ｖ２の電圧レベル（図７Ｅ）又はＶ３の電圧レベル（図７Ｆ）を有する。負電圧パルスの波形は、矩形、台形、三角形又はこれらの組み合わせの波形を有してよい。 7A to 7F are timing charts showing examples of bias DC signals in steps ST3A to ST3F, respectively. 7A to 7F, the horizontal axis indicates time. The vertical axis indicates the voltage level of the bias DC signal. In the example shown in FIGS. 7A-7F, the bias DC signal has a sequence of negative voltage pulses during H3. The sequence of negative voltage pulses has, for example, a pulse frequency in the range of 100 kHz to 500 kHz. The negative voltage pulse has a voltage level of V 1 (FIGS. 7A-7D), a voltage level of V 2 (FIG. 7E) or a voltage level of V 3 (FIG. 7F). The waveform of the negative voltage pulse may have a rectangular, trapezoidal, triangular, or combination waveform.
　図７Ａ～図７Ｆにおいて、Ｖ１、Ｖ２、Ｖ３は、０より小さい負の値を示し、｜Ｖ１｜＜｜Ｖ２｜＜｜Ｖ３｜の関係が成り立つ。すなわち、Ｖ１、Ｖ２、Ｖ３の中では、Ｖ１の電圧レベルが最も低く、Ｖ３の電圧レベルが最も高い。バイアスＤＣ信号は、Ｖ１、Ｖ２、又は、Ｖ３の電力レベルを有するＨ３期間と、バイアスＤＣ信号が供給されない（電圧レベルが０である）Ｌ３期間とを交互に含むパルス波である。なお、一実施形態において、バイアスＤＣ信号は、Ｌ３期間において、負電圧パルスのシーケンスを有してよい。この場合、当該負電圧パルスの電圧の電圧レベルは、Ｈ３期間における負電圧パルスの電圧レベルよりも小さい。 In FIGS. 7A to 7F, V 1 , V 2 , and V 3 show negative values smaller than 0, and the relationship |V 1 |<|V 2 |<|V 3 | holds true. That is, among V 1 , V 2 and V 3 , V 1 has the lowest voltage level and V 3 has the highest voltage level. The bias DC signal is a pulse wave containing alternating H3 periods with power levels of V 1 , V 2 or V 3 and L3 periods in which no bias DC signal is provided (voltage level is 0). Note that in one embodiment, the bias DC signal may have a sequence of negative voltage pulses during the L3 period. In this case, the voltage level of the voltage of the negative voltage pulse is lower than the voltage level of the negative voltage pulse during the H3 period.
　図７Ａ～図７Ｆに示すバイアスＤＣ信号を用いた場合、図６Ａ～図６Ｆに示したバイアスＲＦ信号を用いた場合と同様、工程ＳＴ３Ａ～工程ＳＴ３Ｄのエッチングでは工程ＳＴ３Ｅ～工程ＳＴ３Ｆのエッチングに比べて低いバイアス電位が基板Ｗに生じる。また工程ＳＴ３Ｆは、工程ＳＴ３Ｅに比べてより高いバイアス電位が基板Ｗに生じる。 When the bias DC signal shown in FIGS. 7A to 7F is used, as in the case of using the bias RF signal shown in FIGS. A lower bias potential is developed on the substrate W. Further, a higher bias potential is generated on the substrate W in step ST3F than in step ST3E.
　上述のとおり、工程ＳＴ３においては、ソースＲＦ信号やバイアスＲＦ信号の電力レベルを変化させてエッチングを行う領域は、凹部ＲＣの深さに応じて６つ設けてよい。一例では、当該領域は２以上でよい。例えば、シリコン含有膜ＳＦの厚みの上半分をエッチングする上部領域と、下半分をエッチングする下部領域の２つに分けて、上部領域と下部領域においてソースＲＦ信号やバイアスＲＦ信号の電力レベルを変化させてよい。また当該領域は、エッチングの深さ（凹部ＲＣの深さ）ではなく、エッチング時間に応じて設定してよい。 As described above, in step ST3, six regions may be provided in which etching is performed by changing the power levels of the source RF signal and the bias RF signal, depending on the depth of the recess RC. In one example, there may be two or more such regions. For example, the thickness of the silicon-containing film SF is divided into an upper region where the upper half of the thickness is etched and a lower region where the lower half is etched, and the power levels of the source RF signal and the bias RF signal are changed in the upper region and the lower region. let me Also, the area may be set according to the etching time instead of the etching depth (the depth of the recess RC).
　一例では、工程ＳＴ３において、エッチングの進行に伴って、プラズマ処理チャンバ１０内の圧力を減少させてよい。これにより、凹部ＲＣの深さがより浅い箇所でより高密度のプラズマが生成され、凹部ＲＣの深さがより深い箇所でより低密度のプラズマが生成され得る。エッチングの進行は、エッチング深さの伸長又はエッチング時間の経過に基づいて判断してよい。 For example, in step ST3, the pressure inside the plasma processing chamber 10 may be decreased as the etching progresses. As a result, a higher density plasma can be generated at a portion where the recess RC is shallower, and a lower density plasma can be generated at a portion where the recess RC is deeper. Etching progress may be determined based on the elongation of the etching depth or the elapse of the etching time.
＜実施例＞
　次に、本処理方法の実施例について説明する。本開示は、以下の実施例によって何ら限定されるものではない。 <Example>
Next, an embodiment of this processing method will be described. The present disclosure is in no way limited by the following examples.
　実施例１～実施例３において、図３に示す基板Ｗに対して、本処理方法を適用し、Ｃ４Ｆ８ガスを含む処理ガスでシリコン含有膜ＳＦをエッチングした。各実施例において、基板Ｗのシリコン含有膜ＳＦは、シリコン酸化膜とシリコン窒化膜との積層膜であり、マスク膜ＭＦは、アモルファスカーボン膜である。マスク膜ＭＦの開口パターンは、ホールパターンである。各実施例において、シリコン含有膜ＳＦを６つの領域（上から順に「第１領域」、「第２領域」等という）に分けて、それぞれの領域で、ソースＲＦ信号のパルス波やバイアスＲＦ信号のパルス波の電力レベルを変化させてエッチングを行った。各領域のエッチング時間は、いずれも３００秒であった。 In Examples 1 to 3, this processing method was applied to the substrate W shown in FIG. 3, and the silicon-containing film SF was etched with a processing gas containing C 4 F 8 gas. In each embodiment, the silicon-containing film SF of the substrate W is a laminated film of a silicon oxide film and a silicon nitride film, and the mask film MF is an amorphous carbon film. The opening pattern of the mask film MF is a hole pattern. In each embodiment, the silicon-containing film SF is divided into six regions (referred to as "first region", "second region", etc. in order from the top), and in each region, the pulse wave of the source RF signal and the bias RF signal Etching was performed by changing the power level of the pulse wave. The etching time for each region was 300 seconds.
　実施例１では、ソースＲＦ信号のＬ１期間の電力レベルを段階的に減少させ、その後、バイアスＲＦ信号のＬ２期間の電力レベルを段階的に増加させた。ソースＲＦ信号のＨ１期間の電力レベルＨ１は、第１領域～第６領域においていずれも７５００［Ｗ］であった。ソースＲＦ信号のＬ１期間の電力レベルは、第１領域で４００［Ｗ］、第２領域で２００［Ｗ］、第３領域～第６領域で０［Ｗ］であった。バイアスＲＦ信号のＨ２期間の電力レベルは、第１領域～第６領域でいずれも１２０００［Ｗ］であった。バイアスＲＦ信号のＬ２期間の電力レベルは、第１領域～第４領域で０［Ｗ］、第５領域で２００［Ｗ］、第６領域で７００［Ｗ］であった。 In Example 1, the power level of the source RF signal was stepped down during the L1 period, and then the power level of the bias RF signal was stepped up during the L2 period. The power level H1 of the source RF signal during the H1 period was 7500 [W] in the first to sixth regions. The power level of the source RF signal during the L1 period was 400 [W] in the first region, 200 [W] in the second region, and 0 [W] in the third to sixth regions. The power level of the bias RF signal during the H2 period was 12000 [W] in all of the first to sixth regions. The power level of the bias RF signal during the L2 period was 0 [W] in the first to fourth regions, 200 [W] in the fifth region, and 700 [W] in the sixth region.
　実施例２では、ソースＲＦ信号のＬ１期間の電力レベルのみを段階的に減少させ、バイアスＲＦ信号のＬ２期間の電力レベルを一定に保った。ソースＲＦ信号のＨ１期間の電力レベルＨ１は、第１領域～第６領域においていずれも７５００［Ｗ］であった。ソースＲＦ信号のＬ１期間の電力レベルは、第１領域で５００［Ｗ］、第２領域で３００［Ｗ］、第３領域で１００［Ｗ］、第４領域～第６領域において０［Ｗ］であった。バイアスＲＦ信号のＨ２期間の電力レベルは、第１領域～第６領域においていずれも１２０００［Ｗ］であった。バイアスＲＦ信号のＬ２期間の電力レベルは、第１領域～第６領域においていずれも０［Ｗ］であった。 In Example 2, only the power level of the source RF signal during the L1 period was stepped down, while the power level of the bias RF signal during the L2 period was kept constant. The power level H1 of the source RF signal during the H1 period was 7500 [W] in the first to sixth regions. The power level of the source RF signal during the L1 period is 500 [W] in the first region, 300 [W] in the second region, 100 [W] in the third region, and 0 [W] in the fourth to sixth regions. Met. The power level of the bias RF signal during the H2 period was 12000 [W] in all of the first to sixth regions. The power level of the bias RF signal during the L2 period was 0 [W] in all of the first to sixth regions.
　実施例３では、ソースＲＦ信号のＬ１期間の電力レベルを一定に保ち、バイアスＲＦ信号のＬ２期間の電力レベルのみを段階的に増加させた。具体的には、ソースＲＦ信号のＨ１期間の電力レベルＨ１は、第１領域～第６領域においていずれも７５００［Ｗ］であった。ソースＲＦ信号のＬ１期間の電力レベルは、第１領域～第６領域においていずれも０［Ｗ］であった。バイアスＲＦ信号のＨ２期間の電力レベルは、第１領域～第６領域でいずれも１２０００［Ｗ］であった。バイアスＲＦ信号のＬ２期間の電力レベルは、第１領域～第４領域で０［Ｗ］、第５領域で２００［Ｗ］、第６領域で７００［Ｗ］であった。 In Example 3, the power level of the source RF signal during the L1 period was kept constant, and only the power level of the bias RF signal during the L2 period was increased stepwise. Specifically, the power level H1 of the H1 period of the source RF signal was 7500 [W] in all of the first to sixth regions. The power level of the source RF signal during the L1 period was 0 [W] in the first to sixth regions. The power level of the bias RF signal during the H2 period was 12000 [W] in all of the first to sixth regions. The power level of the bias RF signal during the L2 period was 0 [W] in the first to fourth regions, 200 [W] in the fifth region, and 700 [W] in the sixth region.
　参考例では、実施例における基板Ｗと同一の構成及びホールパターンを有する基板Ｗについて、Ｃ４Ｆ８ガスを含む処理ガスで、シリコン含有膜ＳＦをエッチングした。参考例では、ソースＲＦ信号のパルス波やバイアスＲＦ信号のパルス波の電力レベルを変化させず、連続して１８００秒のエッチングを行った。ソースＲＦ信号のＨ１期間の電力レベルは、７５００［Ｗ］であった。ソースＲＦ信号のＬ１期間の電力レベルは、０［Ｗ］であった。バイアスＲＦ信号のＨ２期間の電力レベルは、１２０００［Ｗ］であった。バイアスＲＦ信号のＬ２期間の電力レベルは、０［Ｗ］であった。 In the reference example, the silicon-containing film SF of the substrate W having the same configuration and hole pattern as those of the substrate W in the example was etched with a processing gas containing a C 4 F 8 gas. In the reference example, etching was continuously performed for 1800 seconds without changing the power level of the pulse wave of the source RF signal and the pulse wave of the bias RF signal. The power level of the source RF signal during the H1 period was 7500 [W]. The power level of the source RF signal during the L1 period was 0 [W]. The power level of the bias RF signal during the H2 period was 12000 [W]. The power level of the bias RF signal during the L2 period was 0 [W].
　表１は、各実施例及び参考例にかかる各種測定結果を示す。表１において、「Ｄ」は、処理後のシリコン含有膜ＳＦのエッチング深さである。「ＢＷ」は、凹部ＲＣの最大開口幅（ボーイングＣＤ）である。「Ｂｔ」は、凹部ＲＣの底部の幅（ボトムＣＤ）である。「ＢＷ－Ｂｔ」は、ボーイングＣＤとボトムＣＤとの差である。 Table 1 shows various measurement results for each example and reference example. In Table 1, "D" is the etching depth of the silicon-containing film SF after processing. “B W ” is the maximum opening width (Boeing CD) of the recess RC. “B t ” is the width (bottom CD) of the bottom of the recess RC. “B W −B t ” is the difference between Boeing CD and Bottom CD.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　表１に示すとおり、実施例におけるボーイングＣＤとボトムＣＤとの差は、いずれも参考例に比べて改善した。すなわち、実施例では、エッチングによるボーイングを抑制しつつ、凹部ＲＣの底部幅を拡大することができた。 As shown in Table 1, the difference between the Boeing CD and the bottom CD in the example was improved compared to the reference example. That is, in the example, it was possible to expand the bottom width of the recess RC while suppressing bowing due to etching.
　本処理方法は、本開示の範囲及び趣旨から逸脱することなく種々の変形をなし得る。例えば、本処理方法は、容量結合型のプラズマ処理装置１以外にも、誘導結合型プラズマやマイクロ波プラズマ等、任意のプラズマ源を用いたプラズマ処理装置を用いて実行してよい。 Various modifications can be made to this processing method without departing from the scope and spirit of the present disclosure. For example, this processing method may be performed using a plasma processing apparatus using an arbitrary plasma source, such as inductively coupled plasma or microwave plasma, other than the capacitively coupled plasma processing apparatus 1 .
１……プラズマ処理装置、２……制御部、１０……プラズマ処理チャンバ、１０ｓ……プラズマ処理空間、１１……基板支持部、１３……シャワーヘッド、２０……ガス供給部、３１ａ……第１のＲＦ生成部、３１ｂ……第２のＲＦ生成部、３２ａ……第１のＤＣ生成部、ＭＦ…マスク膜、ＯＰ…開口、ＳＦ…シリコン含有膜、ＲＣ……凹部、ＵＦ…下地膜、Ｗ…基板 Reference Signs List 1 Plasma processing apparatus 2 Control unit 10 Plasma processing chamber 10s Plasma processing space 11 Substrate support 13 Shower head 20 Gas supply unit 31a First RF generator 31b Second RF generator 32a First DC generator MF Mask film OP Opening SF Silicon-containing film RC Recess UF Bottom base film, W... substrate

Claims (22)

  1. （ａ）シリコン含有膜と前記シリコン含有膜上に形成されたマスク膜とを有する基板をチャンバ内の基板支持部上に提供する工程と、
    （ｂ）前記チャンバ内に処理ガスを供給する工程と、
    （ｃ）ＲＦ信号を供給して前記チャンバ内に前記処理ガスのプラズマを生成するとともに前記基板支持部にバイアス信号を供給して、前記基板をエッチングする工程と、を含み、
    　前記ＲＦ信号は、第１の電力レベルを有する第１の期間と、前記第１の電力レベルよりも低い第２の電力レベルを有する第２の期間とを交互に含むパルス波であり、
    　前記（ｃ）の工程において、エッチングの進行に伴って前記第１の電力レベルに対する前記第２の電力レベルを減少させる、
    プラズマ処理方法。     (a) providing a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber;
    (b) supplying a process gas into the chamber;
    (c) providing an RF signal to generate a plasma of the process gas within the chamber and a bias signal to the substrate support to etch the substrate;
    wherein said RF signal is a pulse wave comprising alternating first periods having a first power level and second periods having a second power level lower than said first power level;
    In step (c), decreasing the second power level with respect to the first power level as the etching progresses;
    Plasma treatment method.
  2. 　前記バイアス信号は、電力レベルが異なる２つの期間又は電圧レベルが異なる２つの期間を交互に含むパルス波である、請求項１に記載のプラズマ処理方法。 The plasma processing method according to claim 1, wherein the bias signal is a pulse wave that alternately includes two periods with different power levels or two periods with different voltage levels.
  3. 　前記バイアス信号は、連続波である、請求項１に記載のプラズマ処理方法。 The plasma processing method according to claim 1, wherein said bias signal is a continuous wave.
  4. （ａ）シリコン含有膜と前記シリコン含有膜上に形成されたマスク膜とを有する基板をチャンバ内の基板支持部上に提供する工程と、
    （ｂ）前記チャンバ内に処理ガスを供給する工程と、
    （ｃ）ＲＦ信号を供給して前記チャンバ内に前記処理ガスのプラズマを生成するとともに、前記基板支持部にバイアス信号を供給して、前記基板をエッチングする工程と、を含み、
    　前記バイアス信号は、第３の電力又は電圧レベルを有する第３の期間と、前記第３の電力又は電圧レベルよりも低い第４の電力又は電圧レベルを有する第４の期間とを交互に含むパルス波であり、
    　前記（ｃ）の工程において、前記第３の電力又は電圧レベルに対する前記第４の電力又は電圧レベルをエッチングの進行に伴って増加させる、
    プラズマ処理方法。     (a) providing a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber;
    (b) supplying a process gas into the chamber;
    (c) providing an RF signal to generate a plasma of the process gas within the chamber and providing a bias signal to the substrate support to etch the substrate;
    The bias signal is pulsed with alternating third durations having a third power or voltage level and fourth durations having a fourth power or voltage level lower than the third power or voltage level. is a wave,
    In the step (c), increasing the fourth power or voltage level with respect to the third power or voltage level as the etching progresses;
    Plasma treatment method.
  5. 　前記ＲＦ信号は、電力レベルが異なる２つの期間を交互に含むパルス波である、請求項４に記載のプラズマ処理方法。 The plasma processing method according to claim 4, wherein the RF signal is a pulse wave that alternately includes two periods with different power levels.
  6. 　前記ＲＦ信号は、連続波である、請求項４に記載のプラズマ処理方法。 The plasma processing method according to claim 4, wherein said RF signal is a continuous wave.
  7. 　前記バイアス信号として、ＲＦ信号を用いる、請求項１乃至請求項６のいずれか１項に記載のプラズマ処理方法。 The plasma processing method according to any one of claims 1 to 6, wherein an RF signal is used as said bias signal.
  8. 　前記バイアス信号として、ＤＣ信号を用いる、請求項１乃至請求項６のいずれか１項に記載のプラズマ処理方法。 The plasma processing method according to any one of claims 1 to 6, wherein a DC signal is used as the bias signal.
  9. （ａ）シリコン含有膜と前記シリコン含有膜上に形成されたマスク膜とを有する基板をチャンバ内の基板支持部上に提供する工程と、
    （ｂ）前記チャンバ内に処理ガスを供給する工程と、
    （ｃ）ソースＲＦ信号を供給して前記チャンバ内に前記処理ガスのプラズマを生成するとともに、前記基板支持部にバイアスＲＦ信号を供給して、前記基板をエッチングする工程と、を含み、
    　前記ソースＲＦ信号は、第１の電力レベルを有する第１の期間と、前記第１の電力レベルよりも低い第２の電力レベルを有する第２の期間とを交互に含むパルス波であり、
    　前記バイアスＲＦ信号は、第３の電力レベルを有する第３の期間と、前記第３の電力レベルよりも低い第４の電力レベルを有する第４の期間とを交互に含むパルス波であり、
    　前記（ｃ）の工程は、（ｃ１）エッチングの進行に伴って前記第１の電力レベルに対する前記第２の電力レベルを減少させる工程と、（ｃ２）エッチングの進行に伴って前記第３の電力レベルに対する前記第４の電力レベルを増加させる工程と、を含む、
    プラズマ処理方法。     (a) providing a substrate having a silicon-containing film and a mask film formed over the silicon-containing film on a substrate support within a chamber;
    (b) supplying a process gas into the chamber;
    (c) providing a source RF signal to generate a plasma of the process gas in the chamber and providing a bias RF signal to the substrate support to etch the substrate;
    the source RF signal is a pulsed wave comprising alternating first periods having a first power level and second periods having a second power level lower than the first power level;
    said bias RF signal is a pulse wave comprising alternating third periods having a third power level and fourth periods having a fourth power level lower than said third power level;
    The step (c) includes (c1) decreasing the second power level with respect to the first power level as etching progresses, and (c2) decreasing the third power level as etching progresses. increasing the fourth power level to level;
    Plasma treatment method.
  10. 　前記（ｃ１）の工程において、前記第３の電力レベルに対する前記第４の電力レベルを一定にし、前記（ｃ２）の工程において、前記第１の電力レベルに対する前記第２の電力レベルを一定にする、請求項９に記載のプラズマ処理方法。 In step (c1), the fourth power level is kept constant with respect to the third power level, and in step (c2), the second power level is kept constant with respect to the first power level. 10. The plasma processing method according to claim 9.
  11. 　前記（ｃ）の工程において、前記（ｃ１）の工程を行った後、前記（ｃ２）の工程を行う、請求項９又は請求項１０のいずれかに記載のプラズマ処理方法。 11. The plasma processing method according to claim 9 or 10, wherein in the step (c), the step (c2) is performed after the step (c1) is performed.
  12. 　前記（ｃ）の工程において、エッチング時間又はエッチングの深さが所与の時間又は深さを超えた後に、前記（ｃ２）の工程を行う、請求項９乃至請求項１１のいずれか１項に記載のプラズマ処理方法。 12. The method according to any one of claims 9 to 11, wherein in the step (c), the step (c2) is performed after the etching time or etching depth exceeds a given time or depth. The plasma treatment method described.
  13. 　前記（ｃ）の工程において、エッチングの進行に伴って、前記チャンバ内の圧力を低下させる、請求項１乃至請求項１２のいずれか１項に記載のプラズマ処理方法。 13. The plasma processing method according to any one of claims 1 to 12, wherein in the step (c), the pressure in the chamber is lowered as the etching progresses.
  14. 　前記処理ガスは、ＣｘＦｙガス（ｘ、ｙは正の整数）又はＣｓＨｔＦｕガス（ｓ、ｔ，ｕは正の整数）を含む、請求項１乃至請求項１３のいずれか１項に記載のプラズマ処理方法。 14. Any of claims 1 to 13, wherein the process gas comprises CxFy gas (x, y are positive integers ) or CsHtFu gas (s, t , u are positive integers). 1. The plasma processing method according to claim 1.
  15. 　前記（ｃ）の工程により形成される凹部のアスペクト比が１００以上である、請求項１乃至請求項１４のいずれか１項に記載のプラズマ処理方法。 15. The plasma processing method according to any one of claims 1 to 14, wherein the recesses formed by the step (c) have an aspect ratio of 100 or more.
  16. 　前記ソースＲＦ信号のパルス波のデューティ比、および／または、前記バイアスＲＦ信号のパルス波のデューティ比は、２０％以上８０％以下である、請求項９乃至請求項１２のいずれか１項に記載のプラズマ処理方法。 13. The duty ratio of the pulse wave of the source RF signal and/or the duty ratio of the pulse wave of the bias RF signal is 20% or more and 80% or less, according to any one of claims 9 to 12. plasma treatment method.
  17. 　前記シリコン含有膜は、シリコン酸化膜とシリコン窒化膜との積層膜である、請求項１乃至請求項１６のいずれか１項に記載のプラズマ処理方法。 The plasma processing method according to any one of claims 1 to 16, wherein said silicon-containing film is a laminated film of a silicon oxide film and a silicon nitride film.
  18. 　前記積層膜は、３Ｄ－ＮＡＮＤ構造に含まれる、請求項１７に記載のプラズマ処理方法。 The plasma processing method according to claim 17, wherein the laminated film is included in a 3D-NAND structure.
  19. 　前記マスク膜は、アモルファスカーボン膜である、請求項１乃至請求項１８のいずれか１項に記載のプラズマ処理方法。 The plasma processing method according to any one of claims 1 to 18, wherein said mask film is an amorphous carbon film.
  20. 　チャンバと、
    　前記チャンバ内に設けられ、シリコン含有膜と前記シリコン含有膜上に形成されたマスク膜とを有する基板を支持するように構成された基板支持部と、
    　前記チャンバ内に処理ガスを供給するように構成されたガス供給部と、
    　ソースＲＦ信号及びバイアスＲＦ信号を生成する電源であって、前記ソースＲＦ信号は、第１の電力レベルを有する第１の期間と、前記第１の電力レベルよりも低い第２の電力レベルを有する第２の期間とを交互に含むパルス波であり、前記バイアスＲＦ信号は、第３の電力レベルを有する第３の期間と、前記第３の電力レベルよりも低い第４の電力レベルを有する第４の期間とを交互に含むパルス波である、電源と、
    　前記電源から前記ソースＲＦ信号を供給して前記チャンバ内に前記処理ガスのプラズマを生成するとともに、前記電源から前記バイアスＲＦ信号を前記基板支持部に供給して、前記基板をエッチングする制御を実行するように構成された制御部と、を有し、
    　前記制御部は、エッチングの進行に伴って前記第１の電力レベルに対する前記第２の電力レベルを減少させる制御と、エッチングの進行に伴って前記第３の電力レベルに対する前記第４の電力レベルを増加させる制御と、を実行する、
    プラズマ処理システム。     a chamber;
    a substrate support provided in the chamber and configured to support a substrate having a silicon-containing film and a mask film formed on the silicon-containing film;
    a gas supply configured to supply a process gas into the chamber;
    A power supply for generating a source RF signal and a bias RF signal, the source RF signal having a first duration having a first power level and a second power level lower than the first power level. wherein the bias RF signal has a third period having a third power level and a fourth power level lower than the third power level. a power source, which is a pulse wave comprising alternating 4 periods;
    providing the source RF signal from the power supply to generate a plasma of the process gas in the chamber and providing the bias RF signal from the power supply to the substrate support to control etching of the substrate; a controller configured to
    The control unit controls to decrease the second power level with respect to the first power level as etching progresses, and decreases the fourth power level with respect to the third power level as etching progresses. increasing control and performing
    Plasma processing system.
  21. 　容量結合型のプラズマ処理装置を含む、請求項２０に記載のプラズマ処理システム。 The plasma processing system according to claim 20, comprising a capacitively coupled plasma processing device.
  22. 　前記ソースＲＦ信号は、前記基板支持部に供給される、請求項２０又は請求項２１のいずれかに記載のプラズマ処理システム。 22. The plasma processing system of any of claims 20 or 21, wherein the source RF signal is provided to the substrate support.
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