WO2023041032A1 - 输出匹配模块、多尔蒂功率放大器 - Google Patents

输出匹配模块、多尔蒂功率放大器 Download PDF

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Publication number
WO2023041032A1
WO2023041032A1 PCT/CN2022/119294 CN2022119294W WO2023041032A1 WO 2023041032 A1 WO2023041032 A1 WO 2023041032A1 CN 2022119294 W CN2022119294 W CN 2022119294W WO 2023041032 A1 WO2023041032 A1 WO 2023041032A1
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electronic component
passive electronic
inductor
radio frequency
frequency signal
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PCT/CN2022/119294
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English (en)
French (fr)
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吕肖林
张煜
崔凯
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中兴通讯股份有限公司
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Publication of WO2023041032A1 publication Critical patent/WO2023041032A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/04—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers
    • H03F1/06—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers to raise the efficiency of amplifying modulated radio frequency waves; to raise the efficiency of amplifiers acting also as modulators
    • H03F1/07—Doherty-type amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/22—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with tubes only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks

Definitions

  • the embodiments of the present application relate to the field of microwave power amplifiers, in particular to output matching modules and Doherty power amplifiers.
  • the Doherty power amplifier generally uses the lumped C-L-C ⁇ network equivalent of the 1/4 wavelength impedance transformation line (that is, the 1/4 ⁇ line in Figure 1) in the output matching network (will be described below In this paper, it is described in detail with reference to Fig.
  • An embodiment of the present application provides an output matching module and a Doherty power amplifier.
  • the embodiment of the present application provides an output matching module, including: a first inductor, a second inductor, a first passive electronic component, a second passive electronic component, a third passive electronic component, a first A DC blocking capacitor and a second DC blocking capacitor; wherein, one end of the first inductor is connected to the drain of the main circuit die, and the other end of the first inductor is connected to one end of the second passive electronic component connected; the other end of the second passive electronic component is grounded through the first DC blocking capacitor; one end of the second inductor is connected to the drain of the auxiliary circuit die, and the other end of the second inductor is connected to the One end of the third passive electronic component is connected; the other end of the third passive electronic component is grounded through the second DC blocking capacitor; the other end of the second passive electronic component or the third passive electronic component The other end of the source electronic component is connected to a bias power supply; one end of the first passive electronic component is connected to the other end of the first inductor, and the other end of the first DC blocking capacitor and
  • the embodiment of the present application provides a Doherty power amplifier, including: an input module, a main circuit die, an auxiliary circuit die, and any one of the above-mentioned output matching modules; wherein, the input module is configured to input
  • the radio frequency signal is divided into the first main channel radio frequency signal and the first auxiliary channel radio frequency signal, the first impedance matching is performed on the first main channel radio frequency signal to obtain the second main channel radio frequency signal, and the phase of the first auxiliary channel radio frequency signal is Compensation and second impedance matching to obtain a second auxiliary channel radio frequency signal;
  • the main channel die is configured to amplify the amplitude of the second main channel radio frequency signal to obtain a third main channel radio frequency signal;
  • the auxiliary channel die It is configured to amplify the amplitude of the radio frequency signal of the second auxiliary channel to obtain a radio frequency signal of the third auxiliary channel;
  • the output RF signal is obtained by impedance matching.
  • Fig. 1 is the schematic diagram of the circuit structure of the Doherty power amplifier of related art
  • FIG. 2 is a schematic diagram of the circuit structure of an output matching module provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a realizable circuit structure of the output matching module provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of another realizable circuit structure of the output matching module provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of another realizable circuit structure of the output matching module provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of another realizable circuit structure of the output matching module provided by the embodiment of the present application.
  • FIG. 7 is a block diagram of a Doherty amplifier provided by another embodiment of the present application.
  • FIG. 8 is a block diagram of the input module provided by the embodiment of the present application.
  • FIG. 9 is a schematic diagram of a realizable circuit structure of the Doherty power amplifier provided in the embodiment of the present application.
  • FIG. 10 is a schematic diagram of another realizable circuit structure of the Doherty power amplifier provided in the embodiment of the present application.
  • FIG. 11 is a schematic diagram of an integrated structure of a Doherty power amplifier provided in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of another integrated structure of the Doherty power amplifier provided by the embodiment of the present application.
  • Figure 1 shows a schematic diagram of the circuit structure of the Doherty power amplifier.
  • the 1/4 wavelength impedance transformation line is equivalent to a network composed of an inductor L T and two capacitors CT (the lower left of Figure 1 As shown in the dotted line box), the main circuit die (master core) and the auxiliary circuit die (auxiliary die) do not contain the parasitic drain-source capacitance Cds; but in practice, the main circuit die and the auxiliary circuit chip both include the parasitic drain-source capacitance Cds.
  • the mainstream practice in the industry is to use the parasitic drain-source capacitance Cds1 of the main circuit die and the parasitic drain-source capacitance Cds2 of the auxiliary circuit die as The parallel capacitance C T at both ends of the lumped CL-C ⁇ network, but because different sizes of die have different parasitic drain-source capacitance Cds, the parasitic drain-source capacitance Cds1 of the main road die and the parasitic drain-source capacitance Cds2 of the auxiliary road die It does not necessarily match the capacitance C T , therefore, it is necessary to coordinate the parasitic drain-source capacitance Cds1 of the main circuit die and the parasitic drain-source capacitance Cds2 of the auxiliary circuit die, as shown in the dotted line box in the lower right corner of Figure 1, the inductance L 1 It plays the role of coordinating the parasitic drain-source capacitance Cds1 of the main circuit
  • inductance L 1 , inductance L 2 , and inductance L T are all unique and cannot be selected, and inductance L 1 , inductance L 2 , and inductance L T are usually realized by bonding wires, limited by the limited integration available Utilizing space, the direct application of lumped CL-C ⁇ -type networks brings constraints on the physical realizability of circuit elements.
  • FIG. 2 is a circuit structure diagram of an output matching module provided by an embodiment of the present application.
  • the output matching module includes: a first inductor Ls1, a second inductor Ls2, a first passive electronic component, a second passive electronic component, a third passive electronic component, and a first DC blocking capacitor C1 and the second DC blocking capacitor C 2 .
  • first inductor Ls1 One end of the first inductor Ls1 is connected to the drain of the main circuit die, and the other end of the first inductor Ls1 is connected to one end of the second passive electronic component; the other end of the second passive electronic component passes through the first DC Capacitor C1 is grounded; one end of the second inductor Ls2 is connected to the drain of the auxiliary circuit die, and the other end of the second inductor Ls2 is connected to one end of the third passive electronic component; the other end of the third passive electronic component is passed through The second DC blocking capacitor C 2 is grounded; the other end of the second passive electronic component or the other end of the third passive electronic component is also connected to the bias power supply Vd (not shown in Figure 2); the first passive electronic component One end is connected to the other end of the first inductor Ls1, and the other end of the first passive electronic component is connected to the other end of the second inductor Ls2.
  • the first inductor Ls1 is implemented using bonding wires
  • the second inductor Ls2 is implemented using bonding wires.
  • the first passive electronic component, the second passive electronic component, and the third passive electronic component may all be inductors or transmission lines.
  • Fig. 3 to Fig. 6 show several realizable exemplary embodiments of the output matching module. It should be noted that the exemplary embodiments shown in FIG. 3 to FIG. 6 are not all possible implementations of the first passive electronic component, the second passive electronic component, and the third passive electronic component, and are not intended to limit the first passive electronic component. Combination range of primary electronic components, second passive electronic components, and third passive electronic components.
  • the first passive electronic component is the third inductor L3
  • the second passive electronic component is the first transmission line TL1
  • the third passive electronic component is the second transmission line TL2 .
  • the first transmission line TL1 is any one of a microstrip line and a coplanar waveguide
  • the second transmission line TL2 is any one of a microstrip line and a coplanar waveguide.
  • the first transmission line TL1 is implemented using a bonding wire
  • the second transmission line TL2 is implemented using a bonding wire
  • the third inductor L3 is implemented using a bonding wire.
  • the first passive electronic component is the third transmission line TL3
  • the second passive electronic component is the fourth transmission line TL4
  • the third passive electronic component is the fifth transmission line TL5 .
  • the third transmission line TL3 is any one of a microstrip line and a coplanar waveguide
  • the fourth transmission line TL4 is any one of a microstrip line and a coplanar waveguide
  • the fifth transmission line TL5 is a microstrip line. Any one of stripline and coplanar waveguide.
  • the third transmission line TL3 is implemented using a bonding wire
  • the fourth transmission line TL4 is implemented using a bonding wire
  • the fifth transmission line TL5 is implemented using a bonding wire.
  • the first passive electronic component is a fourth inductor L4
  • the second passive electronic component is a fifth inductor
  • the third passive electronic component is a sixth inductor. L6.
  • the fourth inductor L4 is implemented using bonding wires
  • the fifth inductor is implemented using bonding wires
  • the sixth inductor L6 is implemented using bonding wires.
  • the first passive electronic component is the sixth transmission line TL6
  • the second passive electronic component is the seventh inductor L7
  • the third passive electronic component is the eighth inductor L8.
  • the sixth transmission line TL6 is any one of a microstrip line and a coplanar waveguide.
  • the sixth transmission line TL6 is implemented using bonding wires
  • the seventh inductor L7 is implemented using bonding wires
  • the eighth inductor L8 is implemented using bonding wires.
  • the third inductance L3 and the fourth inductance L4 have the same or different values.
  • the third transmission line TL3 and the sixth transmission line TL6 have the same or different values.
  • the output matching modules in Fig. 3 to Fig. 6 all include the first inductor Ls1 and the second inductor Ls2, however, different connection modes correspond to the first inductor Ls1 and the second inductor
  • the value of Ls2 can be the same or different.
  • the first inductor Ls1 in FIG. 3 has the same value as the first inductor Ls1 in FIG. 5, and the second inductor Ls2 in FIG.
  • the values of the two inductors Ls2 are the same; the values of the first inductor Ls1 in Figure 3 and the first inductor Ls1 in Figure 4 are different, and the second inductor Ls2 in Figure 3 and the second inductor Ls2 in Figure 4 value is different.
  • the inductance value of the first inductor Ls1, the inductance value of the second inductor Ls2, the property value of the first passive electronic component, the property value of the second passive electronic component, and the third passive electronic component are all variable; the attribute values include: inductance value; or, length and characteristic impedance.
  • the output matching module further includes: a parasitic drain-source capacitance Cds1 of the main circuit die and a parasitic drain-source capacitance Cds2 of the auxiliary circuit die; wherein, the first inductor One end of the inductor Ls1 is grounded through the parasitic drain-source capacitance Cds1 of the main circuit die, and one end of the second inductor Ls2 is grounded through the parasitic drain-source capacitance Cds2 of the auxiliary circuit die.
  • the output matching module provided by the embodiment of the present application introduces the degree of freedom of circuit design by moderately increasing the complexity of the circuit, and the combination space of each component parameter is effectively expanded, so that the optimal component that meets the circuit size can be selected, that is, The circuit size of the output matching module is effectively reduced, the integration space required by the output matching module is effectively reduced, and the miniaturization of the output matching module is greatly enhanced.
  • the inductance value of the first inductor Ls1 is Ls1
  • the inductance value of the second inductor Ls2 is Ls2
  • the inductance value of the third inductor L3 is L3
  • the first The length of the transmission line TL1 is length (TL1)
  • the characteristic impedance of the first transmission line TL1 is Z 0(TL1)
  • the length of the second transmission line TL2 is length (TL2)
  • the characteristic impedance of the second transmission line TL2 is Z 0(TL2)
  • w 0 is the working frequency
  • Z 0 is the characteristic impedance of the 1/4 wavelength impedance conversion line
  • Cds1 is the parasitic drain-source capacitance of the main circuit die
  • Cds2 is the parasitic capacitance of the auxiliary circuit die. Drain-source capacitance.
  • Cds1, Cds2, w 0 and Z 0 are given by the actual application environment of the power amplifier.
  • the value of L3 is obtained according to formula (3)
  • the value of length (TL1) is obtained according to formula (4)
  • the value of length (TL2) is obtained according to formula (5)
  • Z 0(TL1) and Z 0(TL2) depends on the size of the bias current required by the actual environment. Therefore, selecting different Ls1 and Ls2 will correspond to different values of length (TL1) , length (TL2) and L3. Therefore Ls1 and Ls2 are introduced as two degrees of freedom.
  • Z 0( TL1 ) is the characteristic impedance of the first transmission line TL1
  • Z 0( TL2 ) is the characteristic impedance of the first transmission line TL2 .
  • the length of the bonding wire to realize the inductance L T is 7.18 millimeters (mm)
  • the length of the bonding wire to realize the inductance L 1 is 11.1 mm
  • the length of the bonding wire to realize the inductance L 2 is 11.1mm
  • the longest bonding wire length is 11.1mm
  • the length of the bonding wire to realize the first inductor Ls1 is 2.3mm
  • the bonding of the second inductor Ls2 is realized
  • the length of the wire is 2.3mm
  • the length of the bonding wire realizing the third inductor L3 is 0.84mm
  • the length of the first transmission line TL1 is
  • the length is 2.27mm
  • the third transmission line TL3 has a length of 3.25mm and a width of 0.25mm
  • the fourth transmission line TL4 has a length of 5mm and a width of 0.035mm
  • the fifth transmission line TL5 has a length of 5mm and a width of 0.035mm, the longest The bond wire length is 2.27mm.
  • the longest bonding wire length using the output matching module of the embodiment of the present application is smaller than the longest bonding wire length using the lumped CL-C ⁇ type network to realize the output matching module, which is due to the introduction of The degree of freedom leads to the effect of increased selectivity, and since the maximum length of a single bond wire is the key to limit the miniaturization of the output matching module, the maximum length of a single bond wire can be reduced to benefit Dole miniaturization of power amplifiers.
  • FIG. 7 is a block diagram of a Doherty power amplifier provided by another embodiment of the present application.
  • the Doherty power amplifier includes: an input module 701 , a main circuit die 702 , an auxiliary circuit die 703 and any one of the above output matching modules 704 .
  • the input module 701 is configured to divide the input radio frequency signal into a first main channel radio frequency signal and a first auxiliary channel radio frequency signal, perform first impedance matching on the first main channel radio frequency signal to obtain a second main channel radio frequency signal, and Perform phase compensation and second impedance matching on an auxiliary channel radio frequency signal to obtain a second auxiliary channel radio frequency signal;
  • the main channel die 702 is configured to amplify the amplitude of the second main channel radio frequency signal to obtain a third main channel radio frequency signal;
  • the auxiliary channel die 703, configured to amplify the amplitude of the radio frequency signal of the second auxiliary channel to obtain the radio frequency signal of the third auxiliary channel;
  • the output matching module 704 is configured to perform third impedance matching on the radio frequency signal of the third main channel and the radio frequency signal of the third
  • the input module 701 includes: a power divider 801 configured to divide the input radio frequency signal into a first main channel radio frequency signal and a first auxiliary channel radio frequency signal; the first input matching The submodule 802 is configured to perform first impedance matching on the first main channel radio frequency signal to obtain the second main channel radio frequency signal; the phase compensation submodule 803 is configured to perform phase compensation on the first auxiliary channel radio frequency signal; the second input matching submodule 804, configured to perform second impedance matching on the phase-compensated first auxiliary channel radio frequency signal to obtain a second auxiliary channel radio frequency signal.
  • the power ratio between the first main channel radio frequency signal and the first auxiliary channel radio frequency signal may be determined according to actual needs.
  • the power divider 801 simultaneously provides an isolation function for two channels of radio frequency signals.
  • the first input matching sub-module 802 matches the output impedance of the power divider 801 to the source impedance of the main circuit die 702, and the phase compensation sub-module 803 introduces an additional phase shift in the auxiliary circuit to ensure that the main circuit radio frequency
  • the signal is synchronized with the phase of the RF signal of the auxiliary circuit, and the second input matching sub-module 804 will match the output impedance of the power splitter 801 to the source impedance of the auxiliary circuit die 703 .
  • the output matching module 704 matches the load impedance of the main circuit die 702 and the auxiliary circuit die 703 to the load impedance of the junction point.
  • the power amplifier further includes: a post-matching module 705 configured to perform a fourth Impedance matching, to match the output load impedance to a preset impedance value; if the load impedance of the junction point is a preset impedance value, the power amplifier does not include a post-matching module 705 .
  • a post-matching module 705 configured to perform a fourth Impedance matching, to match the output load impedance to a preset impedance value; if the load impedance of the junction point is a preset impedance value, the power amplifier does not include a post-matching module 705 .
  • Fig. 9 and Fig. 10 show two examples of the Doherty power amplifier. It should be noted that the given examples are not intended to limit the protection scope of the embodiments of the present application.
  • FIG. 11 and FIG. 12 show two possible integration methods, and the given examples are not intended to limit the integration method of the Doherty power amplifier in the embodiment of the present application.
  • the input module 701 is integrated in the sub-chip 1
  • the main circuit die 702 is integrated in the sub-chip 5
  • the auxiliary circuit die 703 is integrated in the sub-chip In 4
  • the second transmission line TL2, the second DC blocking capacitor C2 in the output matching module 704, and the post-matching module 705 are integrated in the sub-chip 2
  • the first transmission line TL1 and the first DC blocking capacitor in the output matching module 704 C1 is integrated in the sub-chip 3
  • the second inductor Ls2 is connected between the sub-chip 4 and the sub-chip 2
  • the first inductor Ls1 is connected between the sub-chip 5 and the sub-chip 3
  • the third inductor Ls1 is connected between the sub-chip 2 and the sub-chip 3 Inductor L3.
  • the input module 701 is integrated in the sub-chip 1
  • the main circuit die 702 is integrated in the sub-chip 4
  • the auxiliary circuit die 703 is integrated in the sub-chip 3
  • the second transmission line TL2, the second DC blocking capacitor C 2 , the third transmission line TL3, the first transmission line TL1 and the first DC blocking capacitor C 1 in the output matching module 704, and the post-matching module 705 are integrated in the sub-chip 2
  • the first inductor Ls1 is connected between the sub-chip 4 and the sub-chip 2
  • the second inductor Ls2 is connected between the sub-chip 2 and the sub-chip 3 .
  • Sub-chip 1 , sub-chip 2 , sub-chip 3 , sub-chip 4 , first inductor Ls1 , and second inductor Ls2 are packaged into one large chip.
  • the power amplifier provided by the embodiment of the present application introduces the degree of freedom of circuit design by moderately increasing the complexity of the circuit of the output matching module, and the combination space of each component parameter is effectively expanded, so that the optimal component that meets the circuit size can be selected , that is, the circuit size of the output matching module is effectively reduced, and the integration space required by the output matching module is effectively reduced. Since the space ratio of the output matching module is relatively large among all components of the Doherty power amplifier, the output matching module is reduced. Matching the size of the module means reducing the size of the Doherty power amplifier, which greatly enhances the miniaturization of the Doherty power amplifier.

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Abstract

本申请提供了一种输出匹配模块、多尔蒂功率放大器，输出匹配模块包括：第一电感器、第二电感器、第一无源电子元件、第二无源电子元件、第三无源电子元件、第一隔直电容和第二隔直电容；其中，第一电感器的一端与主路管芯的漏极连接，第一电感器的另一端与第二无源电子元件的一端连接；第二无源电子元件的另一端通过第一隔直电容接地；第二电感器的一端与辅路管芯的漏极连接，第二电感器的另一端与第三无源电子元件的一端连接；第三无源电子元件的另一端通过第二隔直电容接地；第二无源电子元件或第三无源电子元件的另一端连接偏置电源；第一无源电子元件的一端与第一电感器的另一端连接，第一无源电子元件的另一端与第二电感器的另一端连接。

Description

输出匹配模块、多尔蒂功率放大器
相关申请的交叉引用
本申请要求于2021年9月16日提交的中国专利申请NO.202111087195.4的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本申请实施例微波功率放大器领域，特别涉及输出匹配模块、多尔蒂功率放大器。
背景技术
为了满足无线通信领域日益增长的高数据传输速率以及频谱效率需求，更宽的频带、更复杂的调制方式、更多的通道被引入。复杂的调制方式需要功率放大器放大高峰均比信号，为了满足高峰均比信号下线性度的要求需要使功率放大器大多数时间工作在回退状态，如此会带来回退效率大幅降低的问题，通道数量的增多也需要回退效率提升来降低功耗和减小散热，目前可以提升回退效率的技术包括包络跟踪(Envelope tracking)、异相(Outphasing)以及多尔蒂(Doherty)。其中Doherty功率放大器以结构简洁等优点被广泛使用。
随着无线收发机的射频前端通道数增多，需要Doherty功率放大器的集成度提高以小型化。在相关技术中，为了减小尺寸，Doherty功率放大器一般将输出匹配网络中的1/4波长阻抗变换线(即图1中1/4λ线)用集总C-L-Cπ型网络等效(将在下文中参考图1详述)，由于集总C-L-Cπ型网络中的所有电路元件参数值是唯一的，在将电路元件集成到芯片中时，如果芯片的可利用空间有限，则有可能无法实现集成，也就是说，直接应用集总C-L-Cπ型网络会导致芯片无法小型化和/或带来电路元件物理可实现性上的限制。
发明内容
本申请实施例提供一种输出匹配模块、多尔蒂功率放大器。
第一方面，本申请实施例提供一种输出匹配模块，包括：第一电感器、第二电感器、第一无源电子元件、第二无源电子元件、第三无源电子元件、第一隔直电容和第二隔直电容；其中，所述第一电感器的一端与主路管芯的漏极连接，所述第一电感器的另一端与所述第二无源电子元件的一端连接；所述第二无源电子元件的另一端通过所述第一隔直电容接地；所述第二电感器的一端与辅路管芯的漏极连接，所述第二电感器的另一端与所述第三无源电子元件的一端连接；所述第三无源电子元件的另一端通过所述第二隔直电容接地；所述第二无源电子元件的另一端或所述第三无源电子元件的另一端连接偏置电源；所述第一无源电子元件的一端与所述第一电感器的另一端连接，所述第一无源电子元件的另一端与所述第二电感器的另一端连接。
第二方面，本申请实施例提供一种多尔蒂功率放大器，包括：输入模块、主路管芯、辅路管芯和上述任意一种输出匹配模块；其中，所述输入模块，配置为将输入的射频信号分为第一主路射频信号和第一辅路射频信号，对所述第一主路射频信号进行第一阻抗匹配得到第 二主路射频信号，对所述第一辅路射频信号进行相位补偿和第二阻抗匹配得到第二辅路射频信号；所述主路管芯，配置为对所述第二主路射频信号的幅度进行放大处理得到第三主路射频信号；所述辅路管芯，配置为对所述第二辅路射频信号的幅度进行放大处理得到第三辅路射频信号；所述输出匹配模块，配置为对所述第三主路射频信号和所述第三辅路射频信号进行第三阻抗匹配得到输出的射频信号。
附图说明
图1为相关技术的多尔蒂功率放大器的电路结构示意图；
图2为本申请一个实施例提供的输出匹配模块的电路结构示意图；
图3为本申请实施例提供的输出匹配模块的一种可实现的电路结构示意图；
图4为本申请实施例提供的输出匹配模块的另一种可实现的电路结构示意图；
图5为本申请实施例提供的输出匹配模块的再一种可实现的电路结构示意图；
图6为本申请实施例提供的输出匹配模块的又一种可实现的电路结构示意图；
图7为本申请另一个实施例提供的多尔蒂放大器的组成框图；
图8为本申请实施例提供的输入模块的组成框图；
图9为本申请实施例提供的多尔蒂功率放大器的一种可实现的电路结构示意图；
图10为本申请实施例提供的多尔蒂功率放大器的另一种可实现的电路结构示意图；
图11为本申请实施例提供的多尔蒂功率放大器的一种集成结构示意图；
图12为本申请实施例提供的多尔蒂功率放大器的另一种集成结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本申请的技术方案，下面结合附图对本申请提供的输出匹配模块、功率放大器进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本申请透彻和完整，并将使本领域技术人员充分理解本申请的范围。
在不冲突的情况下，本申请各实施例及实施例中的各特征可相互组合。
如本文所使用的，术语“和/或”包括至少一个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本申请。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加至少一个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本申请的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
图1给出了多尔蒂功率放大器的电路结构示意图，在理想化状态下，1/4波长阻抗变换线等价于由电感L T和两个电容C T组成的网络(如图1的左下角虚线框所示)，主路管芯(主管 芯)和辅路管芯(辅管芯)均不包含寄生漏源电容Cds；但是实际中主路管芯和辅路管芯均包括寄生漏源电容Cds。为了简化图1中的输出匹配网络(即图1中1/4λ线)，业内主流的做法是将主路管芯的寄生漏源电容Cds1和辅路管芯的寄生漏源电容Cds2利用起来，作为集总C-L-Cπ型网络两端的并联电容C T，但是由于不同尺寸的管芯具有不同的寄生漏源电容Cds，主路管芯的寄生漏源电容Cds1和辅路管芯的寄生漏源电容Cds2并不一定与电容C T匹配，因此，需要协调主路管芯的寄生漏源电容Cds1和辅路管芯的寄生漏源电容Cds2的值，如图1的右下角虚线框所示，电感L 1起到协调主路管芯的寄生漏源电容Cds1的作用，电感L 2起到协调主路管芯的寄生漏源电容Cds2的作用。由于电感L 1、电感L 2、电感L T的值都是唯一的，不可选择，且电感L 1、电感L 2、电感L T通常采用键合线实现，从而，受限于有限的集成可利用空间，直接应用集总C-L-Cπ型网络会带来电路元件物理可实现性上的限制。
图2为本申请一个实施例提供的输出匹配模块的电路结构图。
参照图2，该输出匹配模块包括：第一电感器Ls1、第二电感器Ls2、第一无源电子元件、第二无源电子元件、第三无源电子元件、第一隔直电容C 1和第二隔直电容C 2。
第一电感器Ls1的一端与主路管芯的漏极连接，第一电感器Ls1的另一端与第二无源电子元件的一端连接；第二无源电子元件的另一端通过第一隔直电容C 1接地；第二电感器Ls2的一端与辅路管芯的漏极连接，第二电感器Ls2的另一端与第三无源电子元件的一端连接；第三无源电子元件的另一端通过第二隔直电容C 2接地；第二无源电子元件的另一端或第三无源电子元件的另一端还连接偏置电源Vd(图2中未示出)；第一无源电子元件的一端与第一电感器Ls1的另一端连接，第一无源电子元件的另一端与第二电感器Ls2的另一端连接。
在一些示例性实施例中，第一电感器Ls1采用键合线实现，第二电感器Ls2采用键合线实现。
在本申请实施例中，第一无源电子元件、第二无源电子元件、第三无源电子元件均可以是电感器或传输线。图3至图6给出了输出匹配模块的几种可实现的示例性实施例。需要说明的是，图3至图6给出的示例性实施例不是第一无源电子元件、第二无源电子元件、第三无源电子元件所有可实现方式，不旨在限定第一无源电子元件、第二无源电子元件、第三无源电子元件的组合范围。
在一些示例性实施例中，如图3所示，第一无源电子元件为第三电感器L3，第二无源电子元件为第一传输线TL1，第三无源电子元件为第二传输线TL2。
在一些示例性实施例中，第一传输线TL1为微带线、共面波导线中的任意一个，第二传输线TL2为微带线、共面波导线中的任意一个。
在一些示例性实施例中，第一传输线TL1采用键合线实现，第二传输线TL2采用键合线实现，第三电感器L3采用键合线实现。
在一些示例性实施例中，如图4所示，第一无源电子元件为第三传输线TL3，第二无源电子元件为第四传输线TL4，第三无源电子元件为第五传输线TL5。
在一些示例性实施例中，第三传输线TL3为微带线、共面波导线中的任意一个，第四传输线TL4为微带线、共面波导线中的任意一个，第五传输线TL5为微带线、共面波导线中的任意一个。
在一些示例性实施例中，第三传输线TL3采用键合线实现，第四传输线TL4采用键合线实现，第五传输线TL5采用键合线实现。
在一些示例性实施例中，如图5所示，第一无源电子元件为第四电感器L4，第二无源电子元件为第五电感器，第三无源电子元件为第六电感器L6。
在一些示例性实施例中，第四电感器L4采用键合线实现，第五电感器采用键合线实现，第六电感器L6采用键合线实现。
在一些示例性实施例中，如图6所示，第一无源电子元件为第六传输线TL6，第二无源电子元件为第七电感器L7，第三无源电子元件为第八电感器L8。
在一些示例性实施例中，第六传输线TL6为微带线、共面波导线中的任意一个。
在一些示例性实施例中，第六传输线TL6采用键合线实现，第七电感器L7采用键合线实现，第八电感器L8采用键合线实现。
在一些示例性实施例中，第三电感L3与第四电感L4的值相同或不同。
在一些示例性实施例中，第三传输线TL3与第六传输线TL6的值相同或不同。
在本申请实施例中，图3至图6中的输出匹配模块均包含有第一电感器Ls1和第二电感器Ls2，但是，不同的连接方式对应的第一电感器Ls1和第二电感器Ls2的值可以相同，也可以不同，例如，图3中的第一电感器Ls1与图5中的第一电感器Ls1的值相同，图3中的第二电感器Ls2与图5中的第二电感器Ls2的值相同；图3中的第一电感器Ls1与图4中的第一电感器Ls1的值不同，图3中的第二电感器Ls2与图4中的第二电感器Ls2的值不同。
在一些示例性实施例中，第一电感器Ls1的电感值、第二电感器Ls2的电感值、第一无源电子元件的属性值、第二无源电子元件的属性值和第三无源电子元件的属性值均为可变量；所述属性值包括：电感值；或者，长度和特性阻抗。
在一些示例性实施例中，如图2至图6所示，输出匹配模块，还包括：主路管芯的寄生漏源电容Cds1和辅路管芯的寄生漏源电容Cds2；其中，第一电感器Ls1的一端通过主路管芯的寄生漏源电容Cds1接地，第二电感器Ls2的一端通过辅路管芯的寄生漏源电容Cds2接地。
本申请实施例提供的输出匹配模块，通过适度提升电路的复杂度来引入电路设计的自由度，各元件参数的组合空间得到有效的扩展，从而可以选择出满足电路尺寸的最优元件，也就是有效缩减了输出匹配模块的电路尺寸，有效缩减了输出匹配模块所需要的集成空间，大大增强了输出匹配模块的小型化。
下面以图3的连接方式为例简单说明本申请实施例的输出匹配模块引入自由度的原因。
根据基于多尔蒂功率放大器的输出匹配问题约束条件，假设第一电感器Ls1的电感值为Ls1，第二电感器Ls2的电感值为Ls2，第三电感器L3的电感值为L3，第一传输线TL1的长度为length (TL1)，第一传输线TL1的特性阻抗为Z 0(TL1)，第二传输线TL2的长度为length (TL2)，第二传输线TL2的特性阻抗为Z 0(TL2)，那么，在满足公式(1)和公式(2)的前提下，上述的取值可以随意选择。
Figure PCTCN2022119294-appb-000001
Figure PCTCN2022119294-appb-000002
公式(1)和公式(2)中，w 0为工作频率，Z 0为1/4波长阻抗变换线的特性阻抗，Cds1为主路管芯的寄生漏源电容，Cds2为辅路管芯的寄生漏源电容。
其中，Cds1、Cds2、w 0，Z 0由功率放大器实际应用环境给出。在Ls1和Ls2选定之后，L3的值按公式(3)得到，length (TL1)的值按公式(4)得到，length (TL2)的值按公式(5)得到，Z 0(TL1)和Z 0(TL2)视实际环境所需的偏置电流大小来确定。因此，选定不同的Ls1和Ls2，就会对应不同值的length (TL1)、length (TL2)以及L3。因此Ls1和Ls2是作为两个自由度被引入。
L3＝F L3(Ls1,Ls2)             (3)
length (TL1)＝F TL1(Ls1,Ls2,Z 0(TL1))        (4)
length (TL2)＝F TL2(Ls1,Ls2,Z 0(TL2))        (5)
其中，Z 0(TL1)为第一传输线TL1的特性阻抗，Z 0(TL2)为第一传输线TL2的特性阻抗。
假设功率放大器的工作频率为2.6吉赫兹(GHz)，功率回退6分贝(dB)，管芯最佳负载阻抗100Ω，Cds1＝Cds2＝1.08皮法(pF)，那么，采用集总C-L-Cπ型网络来实现输出匹配模块时，实现电感L T的键合线的长度为7.18毫米(mm)，实现电感L 1的键合线的长度为11.1mm，实现电感L 2的键合线的长度为11.1mm，最长的键合线长度为11.1mm；而采用图3的输出匹配模块时，实现第一电感器Ls1的键合线的长度为2.3mm，实现第二电感器Ls2的键合线的长度为2.3mm，实现第三电感器L3的键合线的长度为0.84mm，第一传输线TL1的长度为7.5mm，宽度为0.043mm，第二传输线TL2的长度为7.5mm，宽度为0.043mm，最长的键合线长度为2.3mm；采用图4的输出匹配模块时，实现第一电感器Ls1的键合线的长度为2.27mm，实现第二电感器Ls2的键合线的长度为2.27mm，第三传输线TL3的长度为3.25mm，宽度为0.25mm，第四传输线TL4的长度为5mm，宽度为0.035mm，第五传输线TL5的长度为5mm，宽度为0.035mm，最长的键合线长度为2.27mm。由此可见，采用本申请实施例的输出匹配模块的最长的键合线长度要小于采用集总C-L-Cπ型网络来实现输出匹配模块的最长的键合线长度，这是由于引入了自由度导致可选择性的增加而产生的效果，并且，由于单根键合线的最大长度是限制输出匹配模块小型化的关键所在，单根键合线的最大长度得以缩减从而有利于多尔蒂功率放大器的小型化。
图7为本申请另一个实施例提供的多尔蒂功率放大器的组成框图。
参照图7，该多尔蒂功率放大器包括：输入模块701、主路管芯702、辅路管芯703和上述任意一种输出匹配模块704。其中，输入模块701，配置为将输入的射频信号分为第一主路射频信号和第一辅路射频信号，对第一主路射频信号进行第一阻抗匹配得到第二主路射频信号，对第一辅路射频信号进行相位补偿和第二阻抗匹配得到第二辅路射频信号；主路管芯702，配置为对第二主路射频信号的幅度进行放大处理得到第三主路射频信号；辅路管芯703，配置为对第二辅路射频信号的幅度进行放大处理得到第三辅路射频信号；输出匹配模块704，配置为对第三主路射频信号和第三辅路射频信号进行第三阻抗匹配得到输出的射频信号。
在一些示例性实施例中，如图8所示，输入模块701包括：功分器801，配置为将输入的射频信号分为第一主路射频信号和第一辅路射频信号；第一输入匹配子模块802，配置为对第一主路射频信号进行第一阻抗匹配得到第二主路射频信号；相位补偿子模块803，配置为对第一辅路射频信号进行相位补偿；第二输入匹配子模块804，配置为对相位补偿后的第 一辅路射频信号进行第二阻抗匹配得到第二辅路射频信号。
在本申请实施例中，第一主路射频信号和第一辅路射频信号之间的功率比例可以按照实际需要确定。
在本申请实施例中，功分器801同时为两路射频信号提供隔离功能。
在本申请实施例中，第一输入匹配子模块802将功分器801的输出阻抗匹配到主路管芯702的源阻抗，相位补偿子模块803在辅路引入额外的相移以保证主路射频信号和辅路射频信号的相位同步，第二输入匹配子模块804将将功分器801的输出阻抗匹配到辅路管芯703的源阻抗。
在本申请实施例中，输出匹配模块704将主路管芯702和辅路管芯703的负载阻抗匹配到合路点的负载阻抗。
在一些示例性实施例中，如果合路点的负载阻抗不是预设阻抗值(如50欧姆(Ω))，则功率放大器还包括：后匹配模块705，配置为对输出的射频信号进行第四阻抗匹配，以将输出负载阻抗匹配到预设阻抗值；如果合路点的负载阻抗为预设阻抗值，则功率放大器不包括后匹配模块705。
为了更直观体现多尔蒂功率放大器的整体电路结构图，图9和图10给出了多尔蒂功率放大器的两个例子。需要说明的是，所给出的例子不旨在限定本申请实施例的保护范围。
本申请实施例对多尔蒂功率放大器的集成方式不作限定。图11和图12给出了两种可实现的集成方式，所给出的例子不旨在限定本申请实施例的多尔蒂功率放大器的集成方式。
如图11所示，针对图9所给出的多尔蒂功率放大器，将输入模块701集成在子芯片1中，主路管芯702集成在子芯片5中，辅路管芯703集成在子芯片4中，输出匹配模块704中的第二传输线TL2、第二隔直电容C 2，以及后匹配模块705集成在子芯片2中，输出匹配模块704中的第一传输线TL1和第一隔直电容C 1集成在子芯片3中，子芯片4和子芯片2之间连接第二电感器Ls2，子芯片5和子芯片3之间连接第一电感器Ls1，子芯片2和子芯片3之间连接第三电感器L3。子芯片1、子芯片2、子芯片3、子芯片4、子芯片5、第一电感器Ls1、第二电感器Ls2、第三电感器L3封装成一个大芯片。
如图12所示，针对图10所给出的多尔蒂功率放大器，将输入模块701集成在子芯片1中，主路管芯702集成在子芯片4中，辅路管芯703集成在子芯片3中，输出匹配模块704中的第二传输线TL2、第二隔直电容C 2、第三传输线TL3、第一传输线TL1和第一隔直电容C 1，以及后匹配模块705集成在子芯片2中，子芯片4和子芯片2之间连接第一电感器Ls1，子芯片2和子芯片3之间连接第二电感器Ls2。子芯片1、子芯片2、子芯片3、子芯片4、第一电感器Ls1、第二电感器Ls2封装成一个大芯片。
本申请实施例提供的功率放大器，通过适度提升输出匹配模块的电路的复杂度来引入电路设计的自由度，各元件参数的组合空间得到有效的扩展，从而可以选择出满足电路尺寸的最优元件，也就是有效缩减了输出匹配模块的电路尺寸，有效缩减了输出匹配模块所需要的集成空间，由于多尔蒂功率放大器的所有组成部分中，输出匹配模块的空间占比比较大，缩减了输出匹配模块的尺寸就意味着缩减了多尔蒂功率放大器的尺寸，大大增强了多尔蒂功率放大器的小型化。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的 是，除非另外明确指出，否则可单独使用与特定实施例相结合描述的特征、特性和/或元素，或可与其它实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本申请的范围的情况下，可进行各种形式和细节上的改变。

Claims (10)

  1. 一种输出匹配模块，包括：
    第一电感器、第二电感器、第一无源电子元件、第二无源电子元件、第三无源电子元件、第一隔直电容和第二隔直电容；
    其中，所述第一电感器的一端与主路管芯的漏极连接，所述第一电感器的另一端与所述第二无源电子元件的一端连接；所述第二无源电子元件的另一端通过所述第一隔直电容接地；
    所述第二电感器的一端与辅路管芯的漏极连接，所述第二电感器的另一端与所述第三无源电子元件的一端连接；所述第三无源电子元件的另一端通过所述第二隔直电容接地；
    所述第二无源电子元件的另一端或所述第三无源电子元件的另一端连接偏置电源；并且
    所述第一无源电子元件的一端与所述第一电感器的另一端连接，所述第一无源电子元件的另一端与所述第二电感器的另一端连接。
  2. 根据权利要求1所述的输出匹配模块，其中，所述第一无源电子元件、所述第二无源电子元件、所述第三无源电子元件为电感器或传输线。
  3. 根据权利要求1所述的输出匹配模块，其中，所述第一无源电子元件为第三电感器，所述第二无源电子元件为第一传输线，所述第三无源电子元件为第二传输线。
  4. 根据权利要求1所述的输出匹配模块，其中，所述第一无源电子元件为第三传输线，所述第二无源电子元件为第四传输线，所述第三无源电子元件为第五传输线。
  5. 根据权利要求1所述的输出匹配模块，其中，所述第一无源电子元件为第四电感器，所述第二无源电子元件为第五电感器，所述第三无源电子元件为第六电感器。
  6. 根据权利要求1所述的输出匹配模块，其中，所述第一无源电子元件为第六传输线，所述第二无源电子元件为第七电感器，所述第三无源电子元件为第八电感器。
  7. 根据权利要求1-6任意一项所述的输出匹配模块，还包括：所述主路管芯的寄生漏源电容和所述辅路管芯的寄生漏源电容；
    其中，所述第一电感器的一端通过所述主路管芯的寄生漏源电容接地，所述第二电感器的一端通过所述辅路管芯的寄生漏源电容接地。
  8. 根据权利要求1-7任意一项所述的输出匹配模块，其中，所述第一电感器的电感值、所述第二电感器的电感值、所述第一无源电子元件的属性值、所述第二无源电子元件的属性值和所述第三无源电子元件的属性值为可变量；并且所述属性值包括：电感值；或者，长度和特性阻抗。
  9. 一种多尔蒂功率放大器，包括：输入模块、主路管芯、辅路管芯和如权利要求1-8任意一项所述的输出匹配模块，其中，
    所述输入模块，配置为将输入的射频信号分为第一主路射频信号和第一辅路射频信号，对所述第一主路射频信号进行第一阻抗匹配得到第二主路射频信号，对所述第一辅路射频信号进行相位补偿和第二阻抗匹配得到第二辅路射频信号；
    所述主路管芯，配置为对所述第二主路射频信号的幅度进行放大处理得到第三主路射频信号；
    所述辅路管芯，配置为对所述第二辅路射频信号的幅度进行放大处理得到第三辅路射频信号；并且
    所述输出匹配模块，配置为对所述第三主路射频信号和所述第三辅路射频信号进行第三阻抗匹配得到输出的射频信号。
  10. 根据权利要求9所述的多尔蒂功率放大器，还包括：
    后匹配模块，配置为对所述输出的射频信号进行第四阻抗匹配。
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