WO2024092499A1 - 多赫蒂放大器及其输出网络、多赫蒂放大器的设计方法 - Google Patents

多赫蒂放大器及其输出网络、多赫蒂放大器的设计方法 Download PDF

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WO2024092499A1
WO2024092499A1 PCT/CN2022/128960 CN2022128960W WO2024092499A1 WO 2024092499 A1 WO2024092499 A1 WO 2024092499A1 CN 2022128960 W CN2022128960 W CN 2022128960W WO 2024092499 A1 WO2024092499 A1 WO 2024092499A1
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network
amplifier
output
capacitor
inductor
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PCT/CN2022/128960
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English (en)
French (fr)
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刘昊宇
郑爽爽
林良
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苏州华太电子技术股份有限公司
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Priority to CN202280003932.4A priority Critical patent/CN117546412A/zh
Priority to PCT/CN2022/128960 priority patent/WO2024092499A1/zh
Publication of WO2024092499A1 publication Critical patent/WO2024092499A1/zh

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56Modifications of input or output impedances, not otherwise provided for
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only

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  • the present application relates to the field of wireless communications, and in particular, to an output network for a Doherty amplifier, a Doherty amplifier including the output network, and a method for designing a Doherty amplifier.
  • Doherty amplifiers can be used in the RF front end of wireless communication systems (including base stations, broadcasts, and mobile terminals, etc.) to improve the efficiency of wireless communication systems.
  • RF link units including power amplifiers and antennas, etc.
  • the load modulation of the Doherty amplifier is achieved by a quarter-wavelength transmission line, this structure results in a narrow operating bandwidth of the Doherty amplifier and a small high-efficiency back-off power range.
  • the present application provides an output network for a Doherty amplifier, a Doherty amplifier including the output network, and a method for designing a Doherty amplifier, so as to alleviate, mitigate, or even eliminate the above-mentioned problems.
  • An embodiment of the present application provides an output network for a Doherty amplifier, the Doherty amplifier comprising a main amplifier and an auxiliary amplifier, the output network comprising: a combining node, a main output network connected between the output end of the main amplifier and the combining node, an auxiliary output network connected between the output end of the auxiliary amplifier and the combining node, and a combining matching network connected between the combining node and the RF output end of the Doherty amplifier, wherein the auxiliary output network comprises a first sub-network and a second sub-network connected in series, the first sub-network and the main output network have the same circuit topology and both comprise at least an inductor and a capacitor, and the second sub-network comprises at least an inductor, wherein the combining matching network is configured such that the node impedance at the combining node is a complex impedance, and the main output network and the auxiliary output network are configured such that the node impedance is matched to the target load im
  • the main output network is equivalent to a first transmission line in the working frequency band
  • the auxiliary output network is equivalent to a second transmission line in the working frequency band
  • the electrical angle ⁇ M of the first transmission line and the electrical angle ⁇ A of the second transmission line satisfy: 70° ⁇ M ⁇ 90°, and 135° ⁇ A ⁇ 180°.
  • the output network is configured so that the output current IM of the main amplifier and the output current IA of the auxiliary amplifier satisfy: the amplitude of IM is not greater than the amplitude of IA , and the phase difference between IM and IA is less than 90°.
  • the first sub-network and the main output network both include a first capacitor, a second capacitor and a first inductor, one end of the first capacitor and one end of the first inductor are both connected to the output end of the main amplifier or the auxiliary amplifier, the other end of the first capacitor is grounded, the other end of the first inductor is connected to one end of the second capacitor, and the other end of the second capacitor is grounded.
  • the first sub-network and the main output network each further include a third capacitor, one end of the third capacitor is connected to the output end of the main amplifier or the auxiliary amplifier, and the other end of the third capacitor is grounded.
  • the first sub-network and the main output network each further include a second inductor, one end of the second inductor is connected to the output end of the main amplifier or the auxiliary amplifier, and the other end of the second inductor is grounded.
  • the second sub-network includes a third inductor and a fourth capacitor, one end of the third inductor is connected to the output end of the first sub-network, the other end of the third inductor is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded.
  • the combined matching network includes a fourth inductor, a fifth inductor, a sixth inductor, a fifth capacitor and a sixth capacitor, one end of the fourth inductor is connected to the combined node, the other end of the fourth inductor is connected to one end of the fifth capacitor and one end of the fifth inductor, the other end of the fifth capacitor is grounded, the other end of the fifth inductor is connected to one end of the sixth capacitor and one end of the sixth inductor, the other end of the sixth capacitor is grounded, and the other end of the sixth inductor is connected to a DC voltage terminal, and the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the sixth inductor, the fifth inductor, the fourth inductor, the main output network and the auxiliary output network.
  • the combining matching network includes a third transmission line, a fourth transmission line, a fifth transmission line, a sixth transmission line and a seventh capacitor, one end of the third transmission line is connected to the combination node, the other end of the third transmission line is connected to one end of the fourth transmission line and one end of the fifth transmission line, the other end of the fourth transmission line is connected to a DC voltage terminal and one end of the seventh capacitor, the other end of the seventh capacitor is grounded, the other end of the fifth transmission line is connected to one end of the sixth transmission line, the other end of the sixth transmission line is floating, and the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the fourth transmission line, the third transmission line, the main output network and the auxiliary output network.
  • the combining matching network includes a seventh inductor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a seventh transmission line and an eighth transmission line, one end of the seventh inductor is connected to the combined node, the other end of the seventh inductor is connected to one end of the eighth capacitor and one end of the seventh transmission line, the other end of the eighth capacitor is grounded, the other end of the seventh transmission line is connected to one end of the ninth capacitor and one end of the eighth transmission line, the other end of the ninth capacitor is grounded, the other end of the eighth transmission line is connected to a DC voltage terminal, one end of the tenth capacitor is connected to the DC voltage terminal, the other end of the tenth capacitor is grounded, and the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the eighth transmission line, the seventh transmission line, the seventh inductor, the main output network and the auxiliary output network.
  • At least one of the first to tenth capacitors may be implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device.
  • At least one of the first to seventh inductors may be implemented in at least one of the following forms: PCB surface mount components, integrated circuit devices, bonding wires, microstrip lines, metal windings, and transmission lines.
  • At least one transmission line among the third to eighth transmission lines may be implemented in at least one of the following forms: a microstrip line, a stripline, a coplanar waveguide, and a substrate integrated waveguide.
  • a Doherty amplifier comprising: a main amplifier; an auxiliary amplifier; and an output network according to any of the aforementioned embodiments, wherein the output network is configured to receive a first amplified signal output by the main amplifier and a second amplified signal output by the auxiliary amplifier, so that the first amplified signal and the second amplified signal are combined at the combination node to be provided to the RF output end of the Doherty amplifier.
  • Another embodiment of the present application provides a method for designing a Doherty amplifier, the Doherty amplifier comprising a main amplifier, an auxiliary amplifier, and an output network as claimed in claim 1, wherein the method comprises: setting a target performance indicator of the Doherty amplifier, the target performance indicator comprising at least an operating frequency, a saturation power, and a dynamic range of the Doherty amplifier; selecting transistors for the main amplifier and the auxiliary amplifier according to the target performance indicator; determining first, second, and third target impedances based on a load-pull test or a simulation analysis, wherein the first target impedance is a load impedance that makes the main amplifier most efficient when the Doherty amplifier is in a back-off power state, the second target impedance is a load impedance that makes the main amplifier most efficient when the output power of the main amplifier reaches a saturation power, and the third target impedance is a load impedance that makes the auxiliary amplifier most efficient when the output power of the auxiliary amplifier reaches a
  • a main output network, an auxiliary output network, and a combining matching network are provided, wherein the auxiliary output network includes a first sub-network and a second sub-network connected in series, wherein the combining matching network is configured so that the node impedance at the combined node is a complex impedance, and the main output network and the auxiliary output network are configured so that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier, so that the Doherty amplifier can operate efficiently from low power to high power.
  • the first sub-network and the main output network have the same circuit topology and both include at least an inductor and a capacitor, and the second sub-network includes at least an inductor, which helps to simplify the structure of the output network of the Doherty amplifier and the corresponding design process.
  • FIG1 schematically shows an exemplary principle diagram of a Doherty amplifier in the related art
  • FIG2 schematically shows an exemplary schematic diagram of an output network for a Doherty amplifier according to some embodiments of the present application
  • FIG3 schematically shows an exemplary principle diagram of the output network in FIG2 implementing load modulation at low power according to some embodiments of the present application
  • FIG4 schematically shows an exemplary principle diagram of the output network in FIG2 implementing load modulation at high power according to some embodiments of the present application
  • FIG5 schematically shows an exemplary circuit topology diagram of a first sub-network and a main output network according to some embodiments of the present application
  • FIG6 schematically shows an exemplary circuit topology diagram of a second sub-network according to some embodiments of the present application
  • FIG7 schematically shows an exemplary circuit topology diagram of a combiner matching network according to some embodiments of the present application
  • FIG8 schematically shows an exemplary principle diagram of a Doherty amplifier according to some embodiments of the present application.
  • FIG9 schematically shows a schematic diagram of a packaging structure included in a Doherty amplifier according to some embodiments of the present application.
  • FIG10 schematically shows a schematic diagram of a packaging structure included in a Doherty amplifier according to some other embodiments of the present application.
  • FIG11 schematically shows a schematic diagram of a packaging structure included in a Doherty amplifier according to still other embodiments of the present application.
  • FIG12 schematically shows a schematic diagram of various implementations of an inductor according to some embodiments of the present application.
  • FIG13 schematically shows a structural diagram of a Doherty amplifier according to some embodiments of the present application.
  • FIG14 schematically shows a flow chart of a method for designing a Doherty amplifier according to some embodiments of the present application
  • FIG15 schematically shows an example performance diagram of a Doherty amplifier according to some embodiments of the present application.
  • FIG. 16 schematically shows an example diagram of the performance of a Doherty amplifier according to some embodiments of the present application.
  • FIG1 schematically shows an exemplary schematic diagram of a Doherty amplifier in the related art.
  • the Doherty amplifier includes two amplifiers (a main amplifier and an auxiliary amplifier), the main amplifier and the auxiliary amplifier are respectively connected to two output ports of a power divider (not shown), and the RF output ports of the main amplifier and the auxiliary amplifier are connected to a power synthesis network composed of capacitors and inductors, wherein C dsM and C dsA are the parasitic capacitances of the transistors corresponding to the main amplifier and the auxiliary amplifier, respectively, C addM and C M -C dsA are lumped capacitor elements, and L M is a lumped inductor element.
  • the two-port network composed of these capacitors and inductors can be equivalent to a transmission line (i.e., a quarter-wavelength transmission line) with a characteristic impedance of Z M and an electrical length of 90° in the working frequency band.
  • the main amplifier works in class B or class AB
  • the auxiliary amplifier works in class C.
  • the current output after the auxiliary amplifier is turned on will modulate the load RL , and then dynamically modulate the respective loads of the two amplifiers (this process is also called "dynamic load modulation").
  • the two amplifiers do not work in turns, but the main amplifier works all the time, and the auxiliary amplifier starts working when the input power reaches the set peak value.
  • the quarter-wavelength transmission line in the output path of the main amplifier can play a role in phase compensation, so that the output signal in the output path of the main amplifier and the output signal in the output path of the auxiliary amplifier have the same phase at the combining point.
  • MIMO Multiple-Input Multiple-Output
  • the RF front-end system of the MIMO system contains multiple (for example, dozens or even hundreds) RF link units, which puts forward higher and higher requirements on the miniaturization design of the power amplifier in the RF link unit.
  • the traditional solutions are highly complex, use many components, and have large circuit size, which makes it difficult to meet the design requirements of miniaturized amplifiers.
  • the communication bandwidth is increasing exponentially.
  • the communication bandwidth has reached 500MHz or even higher, which poses a high challenge to the working bandwidth of the power amplifier.
  • the load modulation of the Doherty amplifier is implemented by a quarter-wavelength transmission line, and this structure has only a narrow working bandwidth (often less than 200MHz), so this architecture is far from meeting the requirements of today's system broadband operation.
  • Fig. 2 schematically shows an exemplary schematic diagram of an output network 200 for a Doherty amplifier according to some embodiments of the present application.
  • the output network 200 includes: a combining node 230, a main output network 210 connected between the output end of the main amplifier of the Doherty amplifier and the combining node 230, an auxiliary output network 220 connected between the output end of the auxiliary amplifier of the Doherty amplifier and the combining node 230, and a combining matching network 240 connected between the combining node 230 and the RF output end of the Doherty amplifier.
  • the auxiliary output network 220 includes a first sub-network 221 and a second sub-network 222 connected in series, the first sub-network 221 and the main output network 210 have the same circuit topology and both include at least an inductor and a capacitor, and the second sub-network 222 includes at least an inductor, wherein the combiner matching network 240 is configured so that the node impedance at the combined node 230 is a complex impedance Z combine , and the main output network 210 and the auxiliary output network 220 are configured so that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier.
  • the second sub-network 222 may include only one inductor, one end of which is connected to the output end of the first sub-network 221, and the other end of which is connected to the combined node 230.
  • the second sub-network 222 may include an inductor and a capacitor (e.g., an LC circuit).
  • Z combine is an equivalent impedance viewed from the combining node 230 toward the combining matching network 240, which in some cases can be regarded as the ratio of the voltage U TC at the combining node 230 to the current I TC flowing into the combining matching network 240.
  • the combining matching network 240 may include circuit devices of appropriate types and numbers, as long as these circuit devices make the node impedance at the combining node 230 a complex impedance Z combine .
  • the combining matching network 240 may include an LC circuit that transforms the load (e.g., RL in FIG1 ) at the RF output end of the Doherty amplifier into a complex impedance Z combine , i.e., makes the node impedance at the combining node 230 a complex impedance Z combine .
  • the expression "A and B have the same circuit topology” indicates that A and B include the same type and the same number of circuit elements (devices, components), and the connection relationship between these circuit elements in A and B is also the same.
  • the first sub-network 221 and the main output network 210 having the same circuit topology may both include an LC circuit or an LLC circuit.
  • the first sub-network 221 and the main output network 210 have the same circuit topology, this does not mean that the component parameters of the first sub-network 221 and the main output network 210 are also the same.
  • they may both include an LC circuit, but the corresponding inductance value and capacitance value in the LC circuit may be different.
  • the first sub-network 221 and the second sub-network 222 form an auxiliary output network 220, but this does not exclude the situation that the auxiliary output network 220 includes other components (this is also true for the main output network 210).
  • the main output network 210 may also include other circuit components, such as a capacitor for isolating direct current; similarly, the auxiliary output network 220 may also include other circuit components, such as a capacitor for isolating direct current.
  • the auxiliary output network 220 may also include other sub-networks, such as one or more third sub-networks (whose circuit topology may be the same as that of the second sub-network 222).
  • the combined node 230 indicates the common connection point of the main output network 210, the auxiliary output network 220 and the combining matching network 240.
  • the combined node 230 can be the electrical common connection point of the main output network 210, the auxiliary output network 220 and the combining matching network 240.
  • the combined node 230 can also be the electrical node at the output end of the main output network 210.
  • the combined node 230 can also be the electrical node at the output end of the auxiliary output network 220. Even the combined node 230 can be the electrical node at the input end of the combining matching network 240.
  • the auxiliary amplifier is not turned on, so it can be equivalent to an open circuit state.
  • the branch where the auxiliary output network 320 is located (hereinafter referred to as the auxiliary path) provides an auxiliary path impedance Z off at the combination node 330, which is connected in parallel with the node impedance Z combine to one end of the branch where the main output network 310 is located (hereinafter referred to as the main path).
  • the main output network 310 can convert the parallel impedance Z off // Z combine of the auxiliary path impedance Z off and the node impedance Z combine into the target load impedance (Z goal, BO in FIG3 ) of the main amplifier under the back-off power.
  • the main amplifier or the auxiliary amplifier (usually implemented as a transistor), its target load impedance indicates the best power matching impedance of the amplifier under a specific power level, that is, the load impedance that can make the amplifier reach the highest efficiency under a specific power level.
  • the target load impedance depends on the parameters of the amplifier itself and the actual power level, which can be obtained by theoretical calculation or simulation analysis, or by experimental determination methods (such as load pull test).
  • the main output network 310 converts the parallel impedance Z off //Z combine into the target load impedance Z goal,BO of the main amplifier at the back-off power, so that the main amplifier can still operate with high efficiency at the back-off power.
  • the auxiliary amplifier is turned on at high power, the current flowing through the auxiliary path is I T2 , and the current flowing through the main path is I T1 .
  • the combined equivalent impedance of the main path is (1+I T2 /I T1 )*Z combine
  • the combined equivalent impedance of the auxiliary path is (1+I T1 /I T2 )*Z combine
  • the current I T2 can dynamically modulate the combined equivalent impedance of the main path and the combined equivalent impedance of the auxiliary path.
  • the main output network 410 can convert the combined equivalent impedance of the main path (1+I T2 /I T1 )*Z combine into the target load impedance of the main amplifier under saturated power (Z goal, M in FIG4 ).
  • the auxiliary output network 420 (including the first sub-network 421 and the second sub-network 422) can convert the combined equivalent impedance (1+I T1 /I T2 )*Z combine of the auxiliary circuit into the target load impedance (Z goal, A in FIG4 ) of the auxiliary amplifier at saturated power.
  • the main output network 410 and the auxiliary output network 420 respectively convert the combined equivalent impedance of the main circuit and the combined equivalent impedance of the auxiliary circuit into the corresponding target load impedance of the main amplifier and the auxiliary amplifier at saturated power, so that both the main amplifier and the auxiliary amplifier can work efficiently at saturated power.
  • the “combined equivalent impedance” mentioned here indicates the equivalent impedance seen from a combining node (i.e., the combining node 430) on a certain path.
  • the combined equivalent impedance of the main path is the ratio of the main path output terminal voltage U T1 to the main path output current I T1
  • the combined equivalent impedance of the auxiliary path is the ratio of the auxiliary path output terminal voltage U T2 to the auxiliary path output current I T2 .
  • the main amplifier and the auxiliary amplifier may include and are not limited to, for example, power transistors based on VDMOS, LDMOS or GaN, and different transistor technologies provide different performance advantages in terms of output power, gain and performance.
  • the type of transistor can be selected according to requirements such as frequency, bandwidth, cost, etc.
  • the main amplifier and the auxiliary amplifier may be power transistors of the same type (such as GaN-based power transistors), and the parameters and sizes of the transistors used as the main amplifier and the transistors used as the auxiliary amplifier may be exactly the same.
  • the transistors used as the main amplifier and the transistors used as the auxiliary amplifier differ in at least one of the aspects of transistor type, parameters and size.
  • the main amplifier or the auxiliary amplifier may include a plurality of transistors. The specific implementation of the main amplifier and the auxiliary amplifier is not specifically limited herein.
  • the node impedance Z combine at the combination node 230 can be matched to the target load impedance of the main amplifier and the auxiliary amplifier of the Doherty amplifier at different power levels, so that the main amplifier can still work efficiently at the back-off power, and the main amplifier and the auxiliary amplifier can work efficiently at the saturation power, that is, the Doherty amplifier can work efficiently at different power levels.
  • the first sub-network 221 and the main output network 210 have the same circuit topology and both include at least an inductor and a capacitor, and the second sub-network 222 includes at least an inductor, which helps to simplify the structure of the output network of the Doherty amplifier and the corresponding design process.
  • the Doherty amplifier can have a larger working bandwidth and a deeper back-off power (i.e., a larger back-off power range) while working efficiently.
  • the main output network can be equivalent to the first transmission line TL 1 in the working frequency band
  • the auxiliary output network can be equivalent to the second transmission line TL 2 in the working frequency band
  • the electrical angle ⁇ M of the first transmission line TL 1 and the electrical angle ⁇ A of the second transmission line TL 2 satisfy: 70° ⁇ M ⁇ 90°, and 135° ⁇ A ⁇ 180°.
  • the above range can be achieved by appropriately selecting the circuit topology and component parameters of the main output network and the auxiliary output network.
  • the circuit topology and component parameters of the main output network 210, the first sub-network 221 and the second sub-network 222 can be selected so that the transmission lines (the first transmission line TL 1 and the second transmission line TL 2 ) equivalent to the main output network 210 and the auxiliary output network 220 in the working frequency band have corresponding characteristic impedances and electrical lengths, and the electrical angle ⁇ M of the first transmission line TL 1 and the electrical angle ⁇ A of the second transmission line TL 2 satisfy the above range.
  • the above range helps the Doherty amplifier to have a larger operating bandwidth and a deeper back-off power while operating at high efficiency.
  • the output network may be configured such that the output current IM of the main amplifier and the output current IA of the auxiliary amplifier satisfy: the amplitude of IM is not greater than the amplitude of IA , and the phase difference between IM and IA is less than 90°, that is, the phase of IA minus the phase of IM is less than 90°.
  • the above constraints on IM and IA can be achieved by appropriately selecting the circuit topology and component parameters of the main output network and the auxiliary output network, which also helps to make the Doherty amplifier have a larger operating bandwidth and deeper back-off power while working at high efficiency.
  • FIG. 5 schematically shows an exemplary circuit topology diagram of a first sub-network and a main output network according to some embodiments of the present application.
  • the first sub-network and the main output network may have a circuit topology 510, that is, they both include a first capacitor C 1 , a second capacitor C 2 and a first inductor L 1 , one end of the first capacitor C 1 and one end of the first inductor L 1 are both connected to the output of the main amplifier or the auxiliary amplifier (that is, one end of the first capacitor C 1 and one end of the first inductor L 1 in the main output network are both connected to the output of the main amplifier, and one end of the first capacitor C 1 and one end of the first inductor L 1 in the first sub-network are both connected to the output of the auxiliary amplifier), the other end of the first capacitor C 1 is grounded, the other end of the first inductor L 1 is connected to one end of the second capacitor C 2 , and the other end of the second capacitor C 2 is grounded.
  • the first sub-network and the main output network may have a circuit topology 520, that is, compared with the circuit topology 510, they both further include a third capacitor C 3 , one end of the third capacitor C 3 is connected to the output of the main amplifier or the auxiliary amplifier (that is, one end of the third capacitor C 3 in the main output network is connected to the output of the main amplifier, and one end of the third capacitor C 3 in the first sub-network is connected to the output of the auxiliary amplifier), and the other end of the third capacitor C 3 is grounded.
  • the first sub-network and the main output network may have a circuit topology 530, that is, compared with the circuit topology 510, they both further include a second inductor L2 , one end of the second inductor L2 is connected to the output of the main amplifier or the auxiliary amplifier (that is, one end of the second inductor L2 in the main output network is connected to the output of the main amplifier, and one end of the second inductor L2 in the first sub-network is connected to the output of the auxiliary amplifier), and the other end of the second inductor L2 is grounded.
  • FIG6 schematically shows an exemplary circuit topology diagram of the second sub-network according to some embodiments of the present application.
  • the second sub-network may have a circuit topology 610, that is, the second sub-network includes a third inductor L3 , one end of the third inductor L3 is connected to the output end of the first sub-network, and the other end of the third inductor L3 is connected to the combination node.
  • the second sub-network may have a circuit topology 620, that is, compared with the circuit topology 610, the second sub-network also includes a fourth capacitor C4 , as shown in the circuit topology 620, one end of the third inductor L3 is connected to the output end of the first sub-network, the other end of the third inductor L3 is connected to one end of the fourth capacitor C4 (the other end of the third inductor L3 is also connected to the combination node), and the other end of the fourth capacitor C4 is grounded.
  • circuit topology 620 of the second sub-network shown in FIG6 includes an LC circuit composed of a third inductor L3 and a fourth capacitor C4
  • the second sub-network may also include other circuit devices, such as a capacitor for isolating direct current.
  • circuit topologies 510, 520, and 530 shown in FIG5 may include other circuit devices, such as a capacitor for isolating direct current.
  • FIG. 7 schematically shows an exemplary circuit topology diagram of a combiner matching network according to some embodiments of the present application.
  • the combiner matching network may have a circuit topology 710, that is, the combiner matching network includes a fourth inductor L 4 , a fifth inductor L 5 , a sixth inductor L 6 , a fifth capacitor C 5 and a sixth capacitor C 6 , one end of the fourth inductor L 4 is connected to the combination node, the other end of the fourth inductor L 4 is connected to one end of the fifth capacitor C 5 and one end of the fifth inductor L 5 , the other end of the fifth capacitor C 5 is grounded, the other end of the fifth inductor L 5 is connected to one end of the sixth capacitor C 6 and one end of the sixth inductor L 6 , the other end of the sixth capacitor C 6 is grounded, and the other end of the sixth inductor L 6 is connected to a DC voltage terminal, and the DC voltage terminal is configured to provide a DC bias voltage V DD to the main amplifier and the auxiliary amplifier via the sixth inductor L 6 , the fifth inductor L 4 , the fifth inductor L 4
  • the combiner matching network may have a circuit topology 720, that is, the combiner matching network includes a third transmission line TL 3 , a fourth transmission line TL 4 , a fifth transmission line TL 5 , a sixth transmission line TL 6 and a seventh capacitor C 7 , one end of the third transmission line TL 3 is connected to the combination node, the other end of the third transmission line TL 3 is connected to one end of the fourth transmission line TL 4 and one end of the fifth transmission line TL 5 , the other end of the fourth transmission line TL 4 is connected to a DC voltage terminal and one end of the seventh capacitor C 7 , the other end of the seventh capacitor C 7 is grounded, the other end of the fifth transmission line TL 5 is connected to one end of the sixth transmission line TL 6 , the other end of the sixth transmission line TL 6 is floating, and the DC voltage terminal is configured to provide a DC bias voltage V DD to the main amplifier and the auxiliary amplifier via the fourth transmission line TL 4 , the third transmission line TL
  • the combiner matching network may have a circuit topology 730, that is, the combiner matching network includes a seventh inductor L7 , an eighth capacitor C8 , a ninth capacitor C9 , a tenth capacitor C10 , a seventh transmission line TL7 and an eighth transmission line TL8 , one end of the seventh inductor L7 is connected to the combination node, the other end of the seventh inductor L7 is connected to one end of the eighth capacitor C8 and one end of the seventh transmission line TL7 , the other end of the eighth capacitor C8 is grounded, the other end of the seventh transmission line TL7 is connected to one end of the ninth capacitor C9 and one end of the eighth transmission line TL8 , the other end of the ninth capacitor C9 is grounded, the other end of the eighth transmission line TL8 is connected to a DC voltage terminal, one end of the tenth capacitor C10 is connected to the DC voltage terminal, the other end of the tenth capacitor C10 is grounded, and the DC voltage terminal is configured to provide
  • circuit topologies 710, 720 and 730 shown in Figure 7 may include other circuit devices, such as a capacitor for isolating DC.
  • a capacitor for isolating DC By using this capacitor for isolating DC, the DC signal from the DC voltage end will not be transmitted to the RF output end of the Doherty amplifier, thereby protecting sensitive RF components (loads) from the influence of DC power.
  • the relevant bias circuit for providing the DC bias voltage V DD to the main amplifier and the auxiliary amplifier is not disclosed, this is only for illustration, and those skilled in the art should understand that the relevant bias circuit can be set in these embodiments according to the actual application.
  • the number of relevant bias circuits and their positions in the Doherty amplifier circuit can be flexibly adjusted.
  • corresponding DC bias circuits can be set for the main amplifier and the auxiliary amplifier, respectively.
  • a corresponding DC bias circuit can be set in the main output network to provide a DC bias for the main amplifier, and a corresponding DC bias circuit can be set in the first sub-network or the second sub-network to provide a DC bias for the auxiliary amplifier.
  • a corresponding DC bias circuit can be set in the combiner matching network to provide a DC bias for the main amplifier and the auxiliary amplifier (for example, see the circuit topologies 710, 720 and 730 described above).
  • At least one of the first to tenth capacitors may be implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device.
  • At least one of the first to seventh inductors may be implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device, a bonding wire, a microstrip line, a metal winding, and a transmission line.
  • At least one of the third to eighth transmission lines may be implemented in at least one of the following forms: a microstrip line, a stripline, a coplanar waveguide, or a substrate integrated waveguide.
  • Microstrip line is a planar transmission line that is currently used most in hybrid microwave integrated circuits and monolithic microwave integrated circuits. It is a strip conductor (signal line) that is isolated from the ground by a dielectric. Microstrip line can be implemented in a variety of forms such as PCB microstrip line and integrated circuit microstrip line. Factors affecting the characteristic impedance of the microstrip line include the thickness, width, distance from the ground, and dielectric constant of the dielectric of the microstrip line. The length of the microstrip line can correspond to the electrical angle of the microstrip line. Exemplarily, at least one of the third to eighth transmission lines can be implemented by a microstrip line.
  • the length, width and other dimensional parameters of the microstrip line can be configured based on the characteristic impedance and electrical angle of the corresponding transmission line in the third to eighth transmission lines.
  • a transmission line that meets the characteristic parameter requirements can be obtained, so that the Doherty amplifier can have a smaller circuit size, higher working efficiency, larger working bandwidth and deeper back-off power (i.e., a larger back-off power range).
  • the microstrip line can be implemented by adopting a substrate with a high dielectric constant to further reduce the size of the related circuit.
  • Stripline is a high-frequency transmission conductor between dielectrics placed between two parallel ground planes (or power planes). Stripline has the advantages of small size, light weight, wide bandwidth, high quality factor, simple process, low cost, etc., and is suitable for making high-performance (wideband, high quality factor, high isolation) passive components.
  • Coplanar waveguide is formed by making a central conductor strip on one surface of a dielectric substrate and making conductor planes on both sides adjacent to the central conductor strip. In the millimeter wave frequency band, the coplanar waveguide has less loss than microstrip and stripline circuits.
  • Substrate integrated waveguide uses metal through holes to realize the field propagation mode of waveguide on a dielectric substrate, and has the advantages of low differential loss, low radiation, high quality factor, etc.
  • at least one of the third to eighth transmission lines can be composed of only one of stripline, coplanar waveguide or substrate integrated waveguide.
  • a Doherty amplifier comprising: a main amplifier; an auxiliary amplifier; and an output network according to any of the foregoing embodiments, wherein the output network is configured to receive a first amplified signal output by the main amplifier and a second amplified signal output by the auxiliary amplifier, so that the first amplified signal and the second amplified signal are combined at the combination node to be provided to the RF output end of the Doherty amplifier. Since the Doherty amplifier includes the output network according to the foregoing embodiment of the present application, the Doherty amplifier has the advantages brought by the corresponding output network. This Doherty amplifier is further described below in conjunction with FIG. 8.
  • the RF input signal is connected to the main amplifier and the auxiliary amplifier respectively after passing through the power divider (these amplifiers can be single-stage transistors or multi-stage transistors cascaded), wherein the input side of the main amplifier and the auxiliary amplifier also includes an input matching network (i.e., input matching network 1 and input matching network 2 shown in FIG8 ) and a phase shifter network (i.e., phase shifter 1 and phase shifter 2 shown in FIG8 ), wherein the phase shifter network can be set only in the auxiliary path or only in the main path (for example, only in the auxiliary path).
  • an input matching network i.e., input matching network 1 and input matching network 2 shown in FIG8
  • a phase shifter network i.e., phase shifter 1 and phase shifter 2 shown in FIG8
  • the output side of the main amplifier and the auxiliary amplifier is an output network according to any of the aforementioned embodiments of the present application, wherein the output network includes a main output network 810 and an auxiliary output network 820, and the auxiliary output network 820 includes a first sub-network 821 and a second sub-network 822 connected in series.
  • the combining matching network 840 is configured so that the node impedance at the combined node 830 is a complex impedance, and the main output network 810 and the auxiliary output network 820 are configured so that the node impedance matches the target load impedance of the main amplifier and the auxiliary amplifier.
  • the (drain) DC bias voltage may be fed through the DC bias circuit in the main output network 810 and the first sub-network 821 (or the combiner matching network 840 ).
  • the main output network 810 and the first sub-network 821 may have any of the circuit topologies described above with respect to FIG. 5, the second sub-network 822 may have the circuit topology described above with respect to FIG. 6, and the combiner matching network 840 may have any of the circuit topologies described above with respect to FIG. 7.
  • the transmission lines equivalent to the main output network 810 and the auxiliary output network 820 in the working frequency band may have corresponding characteristic impedances, electrical lengths, and electrical angles, so that the Doherty amplifier has a larger working bandwidth and a deeper back-off power while working at a high efficiency.
  • the Doherty amplifier shown in Figure 8 includes only one auxiliary amplifier, those skilled in the art should understand that the Doherty amplifier disclosed in the present application may include more auxiliary amplifiers (for example, two auxiliary amplifiers), and based on the aforementioned embodiments of the present application, the multiple auxiliary output networks on the multiple auxiliary circuits corresponding to these auxiliary amplifiers can all adopt the circuit structure disclosed in the aforementioned embodiments of the present application.
  • FIG9 schematically shows a schematic diagram of a package structure included in a Doherty amplifier according to some embodiments of the present application.
  • the Doherty amplifier includes a package carrier 900 (which may adopt an LGA structure or a QFN structure), and the package carrier 900 includes: a metal pad 901 (the main purpose is to carry circuit elements and provide heat dissipation and a grounding loop); a main amplifier circuit chip 902, whose output end is connected to a pad 907 through a group of bonding wires 906 (the parasitic equivalent inductance can be controlled by adjusting the number, spacing, height, and length of the bonding wires); an auxiliary amplifier circuit chip 903, similar to the main amplifier circuit chip 902, whose output end is also connected to the pad through a group of bonding wires 908; and an output matching unit chip 904.
  • a metal pad 901 the main purpose is to carry circuit elements and provide heat dissipation and a grounding loop
  • a main amplifier circuit chip 902 whose output end is
  • the circuit topology of the main output network and the first sub-network is similar to the circuit topology 510 described above with respect to FIG5 (but does not include the first capacitor C1 ), and the second sub-network adopts the circuit topology 600 described above with respect to FIG6.
  • the bonding wire 906 is used to realize the first inductor L1 in the main output network.
  • the parasitic capacitances CdsM and CdsA i.e., the first capacitor C1
  • the output ends of the main amplifier circuit chip 902 and the auxiliary amplifier circuit chip 903 can be directly connected to the bonding wires 906 and 908.
  • the bonding wires 908 and 910 are respectively used to realize the first inductor L1 in the first sub-network and the third inductor L3 in the second sub-network ( L1 can be equal to L3 ).
  • the capacitor 909 is used to realize the second capacitor C2 in the first sub-network.
  • the capacitor 911 is used to realize the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network. That is, the capacitor 911 can be regarded as the parallel capacitance ( C2 + C4) of the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network.
  • the output matching unit chip 904 is connected to the package output pin through the bonding wire 912; in addition, the input ends of the main amplifier circuit chip 902 and the auxiliary amplifier circuit chip 903 are electrically connected to the pads 916 and 917 on the input circuit chip 915 through bonding wires or the like, which are connected to the input matching circuit.
  • the present application does not limit the specific implementation form of the input matching circuit.
  • FIG10 schematically shows a schematic diagram of a package structure included in a Doherty amplifier according to some other embodiments of the present application.
  • the Doherty amplifier includes a package carrier 1000 (which may adopt an LGA structure or a QFN structure), and the package carrier 1000 includes: a metal pad 1001 (the main purpose is to carry circuit elements and provide heat dissipation and a grounding loop); a main amplifier circuit chip 1002, whose output end is connected to a pad 1006 through a set of bonding wires 1005, where the height and length of the bonding wires 1005 are controlled to be as small as possible, so that its parasitic inductance characteristics can be ignored; an auxiliary amplifier circuit chip 1003, similar to the main amplifier circuit chip 1002, whose output end is also connected to the pad through a set of bonding wires; an output matching unit chip 1004, wherein the main output network and the first sub-network adopt the circuit topology 520 described above with respect to FIG5, and the second sub-network adopts the circuit topology
  • the first capacitor C1 in the main output network and the first sub-network can be the parasitic capacitances CdsM and CdsA of the transistors in the main amplifier circuit chip 1002 and the auxiliary amplifier circuit chip 1003, respectively;
  • the capacitor 1007 is used to realize the third capacitor C3 in the main output network;
  • the bonding wire 1008 (whose parasitic equivalent inductance can be controlled by adjusting the number, spacing, height and length of the bonding wires) is used to realize the first inductor L1 in the main output network;
  • the capacitors 1011 and 1012 are respectively used to realize the third capacitor C3 and the second capacitor C2 in the first sub-network;
  • the bonding wires 1009 and 1010 are respectively used to realize the first inductor L1 in the first sub-network and the third inductor L3 in the second sub-network;
  • the capacitor 1013 is used to realize the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network, that is, the capacitor 10
  • the output matching unit chip 1004 is connected to the package output pin through the bonding wire 1014; in addition, the input ends of the main amplifier circuit chip 1002 and the auxiliary amplifier circuit chip 1003 are electrically connected to the pads 1017 and 1018 on the input circuit chip 1016 through bonding wires or the like, which are connected to the input matching circuit.
  • the present application does not limit the specific implementation form of the input matching circuit.
  • FIG11 schematically shows a schematic diagram of a package structure included in a Doherty amplifier according to some other embodiments of the present application.
  • the Doherty amplifier includes a package carrier 1100 (which may adopt an LGA structure or a QFN structure), and the package carrier 1100 includes: a metal pad 1101 (the main purpose is to carry circuit elements and provide heat dissipation and a grounding loop); a main amplifier circuit chip 1102, whose output end is connected to a pad 1107 through a group of bonding wires 1106 (the parasitic equivalent inductance can be controlled by adjusting the number, spacing, height, and length of the bonding wires); an auxiliary amplifier circuit chip 1103, similar to the main amplifier circuit chip 1102, whose output end is also connected to the pad through a group of bonding wires 1108; and an output matching unit chip 1104.
  • a metal pad 1101 the main purpose is to carry circuit elements and provide heat dissipation and a grounding loop
  • a main amplifier circuit chip 1102 whose output end
  • the circuit topology of the main output network and the first sub-network is similar to the circuit topology 530 described above with respect to FIG5 (but does not include the first capacitor C1 ), and the second sub-network adopts the circuit topology 600 described above with respect to FIG6.
  • the bonding wire 1106 is used to realize the first inductor L1 in the main output network.
  • the parasitic capacitances CdsM and CdsA i.e., the first capacitor C1
  • the output ends of the main amplifier circuit chip 1102 and the auxiliary amplifier circuit chip 1103 can be directly connected to the bonding wires 1106 and 1108.
  • the bonding wires 1108 and 1110 are respectively used to realize the first inductor L1 in the first sub-network and the third inductor L3 in the second sub-network ( L1 can be equal to L3 ).
  • the capacitor 1109 is used to realize the second capacitor C2 in the first sub-network.
  • the capacitor 1111 is used to realize the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network. That is, the capacitor 1111 can be regarded as the parallel capacitance ( C2 + C4) of the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network.
  • the output matching unit chip 1104 is connected to the package output pin through the bonding wire 1112; in addition, the input ends of the main amplifier circuit chip 1102 and the auxiliary amplifier circuit chip 1103 are electrically connected to the pads 1116 and 1117 on the input circuit chip 1115 through bonding wires or the like, which are connected to the input matching circuit.
  • the present application does not limit the specific implementation form of the input matching circuit.
  • the output end of the main amplifier circuit chip 1102 is also connected to the package pin 1119 through the bonding wire 1118, and the output end of the auxiliary amplifier circuit chip 1103 is connected to the package pin 1121 through the bonding wire 1120.
  • the bonding wires 1118 and 1120 By adjusting the number, spacing, height, length, etc. of the bonding wires 1118 and 1120, their parasitic equivalent inductance can be controlled to realize the second inductor L2 in the main output network and the second inductor L2 in the first sub-network.
  • the package pins 1119 and 1121 can be directly or indirectly connected to the ground through an external circuit.
  • FIG12 schematically shows a schematic diagram of various implementations of inductance according to some embodiments of the present application.
  • output matching unit chips 1200 and 1210 which can be used to implement any output matching unit chip described above with respect to FIGS. 9-11
  • inductance in addition to being implemented by parasitic inductance of bonding wires, inductance can also be implemented in the form of metal wires or transmission lines.
  • the left side of FIG12 shows an example in which the first inductor L1 in the main output network is implemented by metal winding 1204 (the first inductor L1 in the first sub-network and the third inductor L3 in the second sub-network are still implemented by bonding wires 1205 and 1207), and its equivalent inductance can be adjusted by adjusting the length, line width and winding form (such as spacing and length) of the metal winding.
  • the right side of FIG. 12 shows an example in which all inductors (the first inductor L 1 in the main output network, the first inductor L 1 in the first sub-network, and the third inductor L 3 in the second sub-network) are implemented by metal windings ( 1214 , 1215 , and 1217 ).
  • FIG13 schematically shows a structural diagram of a Doherty amplifier according to some embodiments of the present application.
  • the Doherty amplifier includes a circuit carrier 1300, and the circuit carrier 1300 includes: a package structure 1301 (which can be any package structure shown in FIGS.
  • the input end 1320 is connected to a corresponding connector (which provides an RF input port of the Doherty amplifier) through a transmission line 1319, and multiple DC ports marked by 1318 can provide the required DC bias voltage (such as gate voltage and DC voltage of the driving circuit) for the package structure 1301.
  • a corresponding connector which provides an RF input port of the Doherty amplifier
  • multiple DC ports marked by 1318 can provide the required DC bias voltage (such as gate voltage and DC voltage of the driving circuit) for the package structure 1301.
  • FIG. 14 schematically shows a flow chart 1400 of a method for designing a Doherty amplifier according to some embodiments of the present application. As shown in FIG. 14 , the method comprises the following steps:
  • a target performance index of the Doherty amplifier is set, and the target performance index includes at least an operating frequency, a saturated power, and a dynamic range of the Doherty amplifier; in step 1420, transistors for the main amplifier and the auxiliary amplifier are selected according to the target performance index.
  • step 1430 based on a load-pull test or simulation analysis, a first, a second, and a third target impedance are determined, wherein the first target impedance is a load impedance that makes the main amplifier most efficient when the Doherty amplifier is in a back-off power state, the second target impedance is a load impedance that makes the main amplifier most efficient when the output power of the main amplifier reaches the saturated power, and the third target impedance is a load impedance that makes the auxiliary amplifier most efficient when the output power of the auxiliary amplifier reaches the saturated power; in step 1440, based on the first, second, and third target impedances, circuit topologies and component parameters of each sub-network in the auxiliary output network and the main output network are determined, and circuit topologies and component parameters of the
  • a Doherty amplifier with a more compact structure and a simplified circuit structure and design process can be obtained.
  • the Doherty amplifier can also achieve efficient operation in the range from low power to high power, with a deeper back-off power and a wider operating bandwidth.
  • the following is a parameter design example of the output circuit 1302 shown in FIG. 13 obtained by using the above design method (in the output network corresponding to the output circuit 1302, the first sub-network of the main output network and the auxiliary output network adopts the circuit topology 510 described above with respect to FIG. 5, and the second sub-network of the auxiliary output network adopts the circuit topology 600 described above with respect to FIG. 6):
  • the Doherty amplifier corresponding to the output network can be applied to 5G mobile communication systems (3.5GHz frequency band, 32T transmitter array, base station amplifier), the main amplifier is a transistor based on gallium nitride (GaN) semiconductor process with a total gate width of 4.8mm, its saturation power is 50W, and the parasitic capacitance C dsM is 2pF (here C dsM is the first capacitor in the main output network); the auxiliary amplifier is a transistor based on gallium nitride (GaN) semiconductor process with a total gate width of 8.4mm, its saturation power is 85W, and the parasitic capacitance C dsA is 3pF (here C dsA is the first capacitor in the first sub-network); other component parameters of each sub-network in the output network 1100 are as follows:
  • L 1 0.926nH (here L 1 is the first inductor in the main output network);
  • CM 2.03pF ( CM is the second capacitor in the main output network);
  • LA 0.358nH (where LA is the first inductor in the first sub-network and the third inductor in the second sub-network);
  • C 1 5.74pF (here C 1 is the second capacitor in the first sub-network);
  • C 2 2.87 pF (here C 2 is the fourth capacitor in the second sub-network);
  • the RF characteristics of the main output network in the 3.5 GHz frequency band are equivalent to a transmission line with an electrical length of 86°, and the RF characteristics of the auxiliary output network in the 3.5 GHz frequency band are equivalent to a transmission line with an electrical length of 161°.
  • FIG15 and FIG16 schematically show performance example graphs of the Doherty amplifier according to some embodiments of the present application.
  • the DC-RF conversion efficiency of the Doherty amplifier according to some embodiments of the present application and the traditional Doherty amplifier varies with the output power as shown in curves 1510 and 1520, respectively. It can be seen that, under low output power conditions, the efficiency of the Doherty amplifier according to some embodiments of the present application is much higher than that of the traditional solution.
  • the amplifier small signal gain of the Doherty amplifier according to some embodiments of the present application and the traditional Doherty amplifier are shown in curves 1610 and 1620, respectively. It can be seen that the bandwidth of the Doherty amplifier according to some embodiments of the present application is much greater than that of the traditional Doherty amplifier (more than twice the bandwidth of the traditional Doherty amplifier).

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Abstract

本申请实施例提供了一种用于多赫蒂放大器的输出网络,该输出网络包括:组合节点、连接在多赫蒂放大器的主放大器的输出端和组合节点之间的主输出网络、连接在多赫蒂放大器的辅放大器的输出端和组合节点之间的辅输出网络、以及连接在组合节点和多赫蒂放大器的射频输出端之间的合路匹配网络,其中辅输出网络包括串联连接的第一子网络和第二子网络,第一子网络和主输出网络具有相同的电路拓扑并且均至少包括电感和电容,并且第二子网络至少包括电感,其中合路匹配网络被配置成使得组合节点处的节点阻抗为复数阻抗,主输出网络和辅输出网络被配置成使得节点阻抗匹配至主放大器和辅放大器的目标负载阻抗。

Description

多赫蒂放大器及其输出网络、多赫蒂放大器的设计方法 技术领域
本申请涉及无线通信领域,具体地,涉及一种用于多赫蒂放大器的输出网络、包括该输出网络的多赫蒂放大器和一种设计多赫蒂放大器的方法。
背景技术
随着无线通信技术的发展,无线通信系统所需的通信带宽不断增长,无线通信系统采用的调制信号也越来越复杂。为了满足对无线通信系统的带宽、效率、体积等方面的要求,在无线通信网络的射频前端系统中,对功率放大器(PA)的效率、回退功率范围、工作带宽、尺寸等方面提出了越来越高的要求。
在相关技术中,可以在无线通信系统(包括基站、广播和移动终端等)的射频前端中使用多赫蒂放大器来提高无线通信系统的效率,但是由于射频前端系统包含的射频链路单元(包括功率放大器和天线等)的数量不断增长,而多赫蒂放大器使用的元器件较多、电路尺寸较大,因此难以满足小型化放大器的设计需求。另外,由于多赫蒂放大器的负载调制是由四分之一波长传输线来实现的,这种结构导致多赫蒂放大器的工作带宽较窄并且高效率的回退功率范围较小。因此,无线通信系统难以通过传统的多赫蒂放大器来满足在带宽、效率、体积等方面越来越高的要求。目前,存在一些通过改进多赫蒂放大器的负载调制网络来增加带宽的方法,但是往往使得多赫蒂放大器的尺寸增加,从而导致难以在放大器的效率、带宽、回退功率范围和电路尺寸之间达到较好的平衡。
发明内容
有鉴于此,本申请提供了一种用于多赫蒂放大器的输出网络、包括该输出网络的多赫蒂放大器和设计多赫蒂放大器的方法,以缓解、减轻、甚至消除上述问题。
本申请的实施例提供了一种用于多赫蒂放大器的输出网络,所述多赫蒂放大器包括主放大器和辅放大器,所述输出网络包括:组合节 点、连接在所述主放大器的输出端和所述组合节点之间的主输出网络、连接在所述辅放大器的输出端和所述组合节点之间的辅输出网络、以及连接在所述组合节点和所述多赫蒂放大器的射频输出端之间的合路匹配网络,其中所述辅输出网络包括串联连接的第一子网络和第二子网络,所述第一子网络和所述主输出网络具有相同的电路拓扑并且均至少包括电感和电容,并且所述第二子网络至少包括电感,其中所述合路匹配网络被配置成使得所述组合节点处的节点阻抗为复数阻抗,所述主输出网络和所述辅输出网络被配置成使得所述节点阻抗匹配至所述主放大器和所述辅放大器的目标负载阻抗。
根据本申请的一些实施例,所述主输出网络在工作频段等效为第一传输线,所述辅输出网络在工作频段等效为第二传输线,所述第一传输线的电角度θ M和所述第二传输线的电角度θ A满足:70°<θ M<90°,并且135°<θ A<180°。
根据本申请的一些实施例,所述输出网络被配置成使得所述主放大器的输出电流I M和所述辅放大器的输出电流I A满足:I M的幅值不大于I A的幅值,并且I M和I A的相位差小于90°。
根据本申请的一些实施例,所述第一子网络和所述主输出网络均包括第一电容器、第二电容器和第一电感器,所述第一电容器的一端和所述第一电感器的一端均连接至所述主放大器或所述辅放大器的输出端,所述第一电容器的另一端接地,所述第一电感器的另一端连接至所述第二电容器的一端,所述第二电容器的另一端接地。
根据本申请的一些实施例,所述第一子网络和所述主输出网络均还包括第三电容器,所述第三电容器的一端连接至所述主放大器或所述辅放大器的输出端,所述第三电容器的另一端接地。
根据本申请的一些实施例,所述第一子网络和所述主输出网络均还包括第二电感器,所述第二电感器的一端连接至所述主放大器或所述辅放大器的输出端,所述第二电感器的另一端接地。
根据本申请的一些实施例,所述第二子网络包括第三电感器和第四电容器,所述第三电感器的一端连接至所述第一子网络的输出端,所述第三电感器的另一端连接至所述第四电容器的一端,所述第四电容器的另一端接地。
根据本申请的一些实施例,所述合路匹配网络包括第四电感器、 第五电感器、第六电感器、第五电容器和第六电容器,所述第四电感器的一端连接至所述组合节点,所述第四电感器的另一端与所述第五电容器的一端和所述第五电感器的一端均连接,所述第五电容器的另一端接地,所述第五电感器的另一端与所述第六电容器的一端和所述第六电感器的一端均连接,所述第六电容器的另一端接地,所述第六电感器的另一端连接至直流电压端,所述直流电压端被配置成经由所述第六电感器、所述第五电感器、所述第四电感器、所述主输出网络和所述辅输出网络向所述主放大器和所述辅放大器提供直流偏置电压。
根据本申请的一些实施例,所述合路匹配网络包括第三传输线、第四传输线、第五传输线、第六传输线和第七电容器,所述第三传输线的一端连接至所述组合节点,所述第三传输线的另一端与所述第四传输线的一端和所述第五传输线的一端均连接,所述第四传输线的另一端连接至直流电压端和所述第七电容器的一端,所述第七电容器的另一端接地,所述第五传输线的另一端连接至所述第六传输线的一端,所述第六传输线的另一端浮接,所述直流电压端被配置成经由所述第四传输线、所述第三传输线、所述主输出网络和所述辅输出网络向所述主放大器和所述辅放大器提供直流偏置电压。
根据本申请的一些实施例,所述合路匹配网络包括第七电感器、第八电容器、第九电容器、第十电容器、第七传输线和第八传输线,所述第七电感器的一端连接至所述组合节点,所述第七电感器的另一端与所述第八电容器的一端和所述第七传输线的一端均连接,所述第八电容器的另一端接地,所述第七传输线的另一端与所述第九电容器的一端和所述第八传输线的一端均连接,所述第九电容器的另一端接地,所述第八传输线的另一端连接至直流电压端,所述第十电容器的一端连接至所述直流电压端,所述第十电容器的另一端接地,所述直流电压端被配置成经由所述第八传输线、所述第七传输线、所述第七电感器、所述主输出网络和所述辅输出网络向所述主放大器和所述辅放大器提供直流偏置电压。
根据本申请的一些实施例,所述第一至第十电容器中的至少一个电容器可以通过以下中的至少一种形式来实现:PCB表贴元件、集成电路器件。
根据本申请的一些实施例,所述第一至第七电感器中的至少一个 电感器可以通过以下中的至少一种形式来实现:PCB表贴元件、集成电路器件、键合线、微带线、金属绕线、传输线。
根据本申请的一些实施例,所述第三至第八传输线中的至少一条传输线可以通过以下中的至少一种形式来实现:微带线、带状线、共面波导、基片集成波导。
本申请的另一实施例提供了一种多赫蒂放大器,包括:主放大器;辅放大器;以及根据前述实施例中任一实施例所述的输出网络,其中所述输出网络被配置成接收所述主放大器的输出的第一放大信号和所述辅放大器输出的第二放大信号,使得所述第一放大信号和所述第二放大信号在所述组合节点处组合以提供给所述多赫蒂放大器的射频输出端。
本申请的又一实施例提供了一种设计多赫蒂放大器的方法,所述多赫蒂放大器包括主放大器、辅放大器、以及如权利要求1所述的输出网络,其中所述方法包括:设置所述多赫蒂放大器的目标性能指标,所述目标性能指标至少包括所述多赫蒂放大器的工作频率、饱和功率、以及动态范围;根据所述目标性能指标,选取用于所述主放大器和所述辅放大器的晶体管;基于负载牵引测试或仿真分析,确定第一、第二和第三目标阻抗,其中所述第一目标阻抗为所述多赫蒂放大器处于回退功率状态时使得所述主放大器效率最高的负载阻抗,所述第二目标阻抗为所述主放大器输出功率达到饱和功率时使得所述主放大器效率最高的负载阻抗,所述第三目标阻抗为所述辅放大器输出功率达到饱和功率时使得所述辅放大器效率最高的负载阻抗;基于所述第一、第二和第三目标阻抗,确定所述辅输出网络中的各个子网络和所述主输出网络的电路拓扑和元件参数,并且确定所述合路匹配网络的电路拓扑和元件参数。
在根据本申请的一些实施例的用于多赫蒂放大器的输出网络中,设置了主输出网络、辅输出网络、以及合路匹配网络,其中所述辅输出网络包括串联连接的第一子网络和第二子网络,其中所述合路匹配网络被配置成使得所述组合节点处的节点阻抗为复数阻抗,所述主输出网络和所述辅输出网络被配置成使得所述节点阻抗匹配至所述主放大器和所述辅放大器的目标负载阻抗,从而使得多赫蒂放大器从低功率到高功率均能高效工作。另一方面,所述第一子网络和所述主输出 网络具有相同的电路拓扑并且均至少包括电感和电容,并且所述第二子网络至少包括电感,从而有助于简化多赫蒂放大器的输出网络的结构以及相应的设计流程。
根据在下文中所描述的实施例,本申请的这些和其他方面将是清楚明白的,并且将参考在下文中所描述的实施例而被阐明。
附图说明
在下面结合附图对于示例性实施例的描述中,本申请的技术方案更多细节、特征和优点被公开,在附图中:
图1示意性示出了相关技术中的多赫蒂放大器的示例性原理图;
图2示意性示出了根据本申请的一些实施例的用于多赫蒂放大器的输出网络的示例性原理图;
图3示意性示出了根据本申请的一些实施例的图2中的输出网络在低功率下实现负载调制的示例性原理图;
图4示意性示出了根据本申请的一些实施例的图2中的输出网络在高功率下实现负载调制的示例性原理图;
图5示意性示出了根据本申请的一些实施例的第一子网络和主输出网络的示例性电路拓扑图;
图6示意性示出了根据本申请的一些实施例的第二子网络的示例性电路拓扑图;
图7示意性示出了根据本申请的一些实施例的合路匹配网络的示例性电路拓扑图;
图8示意性示出了根据本申请的一些实施例的多赫蒂放大器的示例性原理图;
图9示意性示出了根据本申请的一些实施例的多赫蒂放大器包括的封装结构的示意图;
图10示意性示出了根据本申请的另一些实施例的多赫蒂放大器包括的封装结构的示意图;
图11示意性示出了根据本申请的又一些实施例的多赫蒂放大器包括的封装结构的示意图;
图12示意性示出了根据本申请的一些实施例的电感的多种实现方式的示意图;
图13示意性示出了根据本申请的一些实施例的多赫蒂放大器的结构示意图;
图14示意性示出了根据本申请的一些实施例的设计多赫蒂放大器的方法的流程图;
图15示意性示出了根据本申请的一些实施例的多赫蒂放大器的性能示例图;
图16示意性示出了根据本申请的一些实施例的多赫蒂放大器的性能示例图。
具体实施方式
下面将参照附图更详细地描述本申请的若干个实施例以便使得本领域技术人员能够实现本申请的技术方案。本申请的技术方案可以体现为许多不同的形式和目的,并且不应局限于本文所阐述的实施例。提供这些实施例是为了使得本申请的技术方案清楚完整,但所述实施例并不限定本申请的保护范围。
除非另有定义,本文中使用的所有术语(包括技术术语和科学术语)具有与本申请所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是,诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义,并且将不在理想化或过于正式的意义上进行解释,除非本文中明确地如此定义。
图1示意性示出了相关技术中的多赫蒂放大器的示例性原理图。如图1所示,多赫蒂放大器包括两个放大器(主放大器和辅放大器),主放大器和辅放大器分别接入功率分配器(未示出)的两个输出端口,主放大器和辅放大器的射频输出端口连接至由电容电感构成的功率合成网络,其中,C dsM和C dsA分别是主放大器和辅放大器对应的晶体管自身的寄生电容,C addM和C M-C dsA是集总电容元件,L M是集总电感元件,这些电容电感元件所构成的两端口网络在工作频段可以等效于一个特征阻抗为Z M、电长度为90°的传输线(即四分之一波长传输线)。在相关技术中,主放大器工作在B类或者AB类,辅放大器工作在C类,随着输入功率的提升,辅放大器开启后输出的电流将对负载R L产生调制作用,继而动态地调制两个放大器的各自负载(这一过程也被 称为“动态负载调制”)。两个放大器不是轮流工作,而是主放大器一直工作,当输入功率达到设定的峰值时辅放大器开始工作。主放大器输出路径中的四分之一波长传输线可以起到相位补偿的作用,使得主放大器输出路径中的输出信号和辅放大器输出路径中的输出信号在合路点处相位相同。
随着通信技术的不断发展,多输入多输出(MIMO)系统得到越来越广泛的应用,MIMO系统的射频前端系统包含多个(例如,几十甚至上百个)射频链路单元,这对射频链路单元中的功率放大器的小型化设计提出了越来越高的要求,而传统方案复杂度高、使用元器件多、电路尺寸大,难以满足小型化放大器的设计需求。
另一方面,电路元器件的增多给功率放大器集成化设计带来更多问题,不仅设计难度加大,整体电路尺寸增大,芯片成本提高,而且电路的损耗也变得更大,功放的效率也会降低,这导致高效、节能、低成本的系统设计变得更加困难。
另外,随着通信系统的不断迭代,通信带宽在成倍的增长,例如,在5G场景下通信带宽已经达到500MHz甚至更高,这对功率放大器的工作带宽提出了很高的挑战。在图1中,多赫蒂放大器的负载调制是由四分之一波长传输线实现的,而该结构只有较窄的工作带宽(往往小于200MHz),因此这种架构远不能满足如今系统宽带工作的要求。
图2示意性示出了根据本申请的一些实施例的用于多赫蒂放大器的输出网络200的示例性原理图。如图2所示,输出网络200包括:组合节点230、连接在多赫蒂放大器的主放大器的输出端和组合节点230之间的主输出网络210、连接在多赫蒂放大器的辅放大器的输出端和组合节点230之间的辅输出网络220、以及连接在组合节点230和多赫蒂放大器的射频输出端之间的合路匹配网络240。
示例性地,辅输出网络220包括串联连接的第一子网络221和第二子网络222,第一子网络221和主输出网络210具有相同的电路拓扑并且均至少包括电感和电容,并且第二子网络222至少包括电感,其中合路匹配网络240被配置成使得组合节点230处的节点阻抗为复数阻抗Z combine,主输出网络210和辅输出网络220被配置成使得节点阻抗匹配至主放大器和辅放大器的目标负载阻抗。示例性地,第二子网 络222可以仅包括一个电感,该电感的一端连接至第一子网络221的输出端,该电感的另一端连接至组合节点230。替代地,第二子网络222可以包括电感和电容(例如,LC电路)。
如图2所示,Z combine为从组合节点230向合路匹配网络240看去的等效阻抗,其在一些情形下可被视为组合节点230处的电压U TC与流入合路匹配网络240的电流I TC之比。合路匹配网络240可以包括适当类型和数量的电路器件,只要这些电路器件使得组合节点230处的节点阻抗为复数阻抗Z combine。示例性地,合路匹配网络240可以包括LC电路,该电路使得多赫蒂放大器的射频输出端的负载(例如图1中的R L)被变换为复数阻抗Z combine,即使得组合节点230处的节点阻抗为复数阻抗Z combine
需要说明的是,在本申请中,表述“A和B具有相同的电路拓扑”指示A和B包括相同类型和相同数量的电路元件(器件,元器件),并且A和B中的这些电路元件之间的连接关系也相同。示例性地,具有相同的电路拓扑的第一子网络221和主输出网络210可以均包括LC电路或LLC电路。另外,尽管第一子网络221和主输出网络210具有相同的电路拓扑,但这并不意味着第一子网络221和主输出网络210的元件参数也是相同的,例如,它们可以都包括LC电路,但LC电路中相应的电感值和电容值可以是不相同的。
在图2所示的实施例中,第一子网络221和第二子网络222形成了辅输出网络220,但这并不排除辅输出网络220包括其他元件的情形(对于主输出网络210而言也是这样)。例如,在其他实施例中,主输出网络210还可以包括其他电路器件,例如用于隔离直流的电容器;同样地,辅输出网络220还可以包括其他电路器件,例如用于隔离直流的电容器。附加地或替代地,辅输出网络220还可以包括其他子网络,例如一个或多个第三子网络(其电路拓扑可以与第二子网络222的电路拓扑相同)。
另外,组合节点230指示主输出网络210、辅输出网络220和合路匹配网络240的公共连接点,示例性地,组合节点230可以是主输出网络210、辅输出网络220和合路匹配网络240在电气上的公共接点,组合节点230也可以是主输出网络210输出端的电气节点,组合节点230还可以是辅输出网络220的输出端的电气节点,甚至组合节点230 可以是合路匹配网络240的输入端的电气节点。
具体地,下面结合图3和图4来阐明输出网络200的阻抗匹配过程。
如图3所示,在低功率下,辅放大器未开启,因此可以将其等效为开路状态,此时辅输出网络320所在支路(以下简称为辅路)在组合节点330处提供辅路阻抗Z off,其与节点阻抗Z combine并联接在主输出网络310所在支路(以下简称为主路)的一端。在回退功率下,主输出网络310可以将辅路阻抗Z off和节点阻抗Z combine的并联阻抗Z off//Z combine转换为主放大器在回退功率下的目标负载阻抗(图3中的Z goal,BO)。对于主放大器或辅放大器(通常被实施为晶体管)而言,其目标负载阻抗指示特定功率水平下放大器的最佳功率匹配阻抗,即能够使得放大器在特定功率水平下效率达到最高值的负载阻抗。目标负载阻抗取决于放大器本身的参数和实际的功率水平,其可以通过理论计算或仿真分析的方式得到,也可以通过实验测定的方法(例如负载牵引测试)得到。主输出网络310通过将并联阻抗Z off//Z combine转换为主放大器在回退功率下的目标负载阻抗Z goal,BO,可以使得主放大器在回退功率下仍然能够高效率地工作。
如图4所示,在高功率下辅放大器开启,流过辅路的电流为I T2,流过主路的电流为I T1,根据基尔霍夫电压定律和基尔霍夫电流定律,可以得到此时主路的合路等效阻抗为(1+I T2/I T1)*Z combine,辅路的合路等效阻抗为(1+I T1/I T2)*Z combine,因此电流I T2可以动态地调制主路的合路等效阻抗和辅路的合路等效阻抗。在饱和功率下,主输出网络410可以将主路的合路等效阻抗(1+I T2/I T1)*Z combine转换为主放大器在饱和功率下的目标负载阻抗(图4中的Z goal,M)。辅输出网络420(包括第一子网络421和第二子网络422)可以将辅路的合路等效阻抗(1+I T1/I T2)*Z combine转换为辅放大器在饱和功率下的目标负载阻抗(图4中的Z goal,A)。主输出网络410和辅输出网络420分别通过将主路的合路等效阻抗和辅路的合路等效阻抗转换为主放大器和辅放大器在饱和功率下的对应目标负载阻抗,可以使得主放大器和辅放大器在饱和功率下均能够高效率地工作。
这里所提到的“合路等效阻抗”指示在某一路径上向合路节点(即组合节点430)看去的等效阻抗。示例性地,如图4所示,主路的合路 等效阻抗即为主路输出端电压U T1与主路输出电流I T1之比,辅路的合路等效阻抗即为辅路输出端电压U T2与辅路输出电流I T2之比。
在本申请中,主放大器和辅放大器可以包括且不限于例如基于VDMOS、LDMOS或GaN的功率晶体管,不同的晶体管技术在输出功率、增益和性能方面提供不同的性能优势。例如,可以根据频率、带宽、成本等要求来选取晶体管的类型。根据本申请的一些实施例,主放大器和辅放大器可以是相同类型的功率晶体管(如基于GaN的功率晶体管),且用作主放大器的晶体管和用作辅放大器的晶体管的参数和尺寸可以完全相同。在其他实施例中,用作主放大器的晶体管和用作辅放大器的晶体管至少在晶体管类型、参数和尺寸等方面中的一个方面存在差异。根据本申请的另外的实施例,主放大器或辅放大器可包括多个晶体管。本文对主放大器和辅放大器的具体实施方式不作具体限制。
通过在多赫蒂放大器中使用图2所示的输出网络200,可以在不同功率水平下均将组合节点230处的节点阻抗Z combine匹配至多赫蒂放大器的主放大器和辅放大器的目标负载阻抗,使得主放大器在回退功率下仍然能够高效率地工作,并且使得主放大器和辅放大器在饱和功率下均能够高效率地工作,即,使得多赫蒂放大器在不同功率水平下均能够高效率地工作。另一方面,第一子网络221和主输出网络210具有相同的电路拓扑并且均至少包括电感和电容,并且第二子网络222至少包括电感,从而有助于简化多赫蒂放大器的输出网络的结构以及相应的设计流程。此外,如将在下文中进一步描述的,通过合理设置主输出网络210、以及辅输出网络220中的各个子网络的电路拓扑与元件参数,可以使得多赫蒂放大器在高效率工作的同时,具备较大的工作带宽和更深的回退功率(即更大的回退功率范围)。
在一些实施例中,所述主输出网络在工作频段可以等效为第一传输线TL 1,所述辅输出网络在工作频段可以等效为第二传输线TL 2,并且第一传输线TL 1的电角度θ M和第二传输线TL 2的电角度θ A满足:70°<θ M<90°,并且135°<θ A<180°。可以通过适当地选取所述主输出网络、所述辅输出网络的电路拓扑和元件参数来实现上述范围,以图2所示的输出网络200为例,具体地,可以通过选取主输出网络210、第一子网络221和第二子网络222的电路拓扑和元件参数,使得 主输出网络210和辅输出网络220在工作频段所等效的传输线(第一传输线TL 1和第二传输线TL 2)具有相应的特征阻抗和电长度,并且使得第一传输线TL 1的电角度θ M和第二传输线TL 2的电角度θ A满足上述范围。上述范围有助于使得多赫蒂放大器在高效率工作的同时,具备较大的工作带宽和更深的回退功率。
在一些实施例中,所述输出网络可以被配置成使得主放大器的输出电流I M和辅放大器的输出电流I A满足:I M的幅值不大于I A的幅值,并且I M和I A的相位差小于90°,即I A的相位减去I M的相位所得结果小于90°。与上文所述类似,可以通过适当地选取所述主输出网络、所述辅输出网络的电路拓扑和元件参数来实现对I M和I A的以上约束,这同样有助于使得多赫蒂放大器在高效率工作的同时,具备较大的工作带宽和更深的回退功率。
图5示意性示出了根据本申请的一些实施例的第一子网络和主输出网络的示例性电路拓扑图。
如图5所示,在一些实施例中,所述第一子网络和所述主输出网络可以具有电路拓扑510,即它们均包括第一电容器C 1、第二电容器C 2和第一电感器L 1,第一电容器C 1的一端和第一电感器L 1的一端均连接至所述主放大器或所述辅放大器的输出端(即所述主输出网络中的第一电容器C 1的一端和第一电感器L 1的一端均连接至所述主放大器的输出端,而所述第一子网络中的第一电容器C 1的一端和第一电感器L 1的一端均连接至所述辅放大器的输出端),第一电容器C 1的另一端接地,第一电感器L 1的另一端连接至第二电容器C 2的一端,第二电容器C 2的另一端接地。
在一些实施例中,所述第一子网络和所述主输出网络可以具有电路拓扑520,即相较于电路拓扑510,它们均还包括第三电容器C 3,第三电容器C 3的一端连接至所述主放大器或所述辅放大器的输出端(即所述主输出网络中的第三电容器C 3的一端连接至所述主放大器的输出端,而所述第一子网络中的第三电容器C 3的一端连接至所述辅放大器的输出端),第三电容器C 3的另一端接地。
在一些实施例中,所述第一子网络和所述主输出网络可以具有电路拓扑530,即相较于电路拓扑510,它们均还包括第二电感器L 2,第二电感器L 2的一端连接至所述主放大器或所述辅放大器的输出端(即 所述主输出网络中的第二电感器L 2的一端连接至所述主放大器的输出端,而所述第一子网络中的第二电感器L 2的一端连接至所述辅放大器的输出端),第二电感器L 2的另一端接地。
图6示意性示出了根据本申请的一些实施例的第二子网络的示例性电路拓扑图。如图6所示,在一些实施例中,所述第二子网络可以具有电路拓扑610,即所述第二子网络包括第三电感器L 3,第三电感器L 3的一端连接至所述第一子网络的输出端,第三电感器L 3的另一端连接至所述组合节点。在另一些实施例中,所述第二子网络可以具有电路拓扑620,即相较于电路拓扑610,所述第二子网络还包括第四电容器C 4,如电路拓扑620所示,第三电感器L 3的一端连接至所述第一子网络的输出端,第三电感器L 3的另一端连接至第四电容器C 4的一端(第三电感器L 3的所述另一端也连接至所述组合节点),第四电容器C 4的另一端接地。
需要说明的是,尽管图6中所示的所述第二子网络的电路拓扑620包括由第三电感器L 3和第四电容器C 4组成的LC电路,但本领域技术人员应理解,所述第二子网络还可以包括其他电路器件,例如用于隔离直流的电容器。类似地,尽管未在图5的各个电路拓扑中示出,本领域技术人员应理解,图5所示的电路拓扑510、520和530中的至少一种可以包括其他电路器件,例如用于隔离直流的电容器。
图7示意性示出了根据本申请的一些实施例的合路匹配网络的示例性电路拓扑图。
如图7所示,在一些实施例中,所述合路匹配网络可以具有电路拓扑710,即所述合路匹配网络包括第四电感器L 4、第五电感器L 5、第六电感器L 6、第五电容器C 5和第六电容器C 6,第四电感器L 4的一端连接至所述组合节点,第四电感器L 4的另一端与第五电容器C 5的一端和第五电感器L 5的一端均连接,第五电容器C 5的另一端接地,第五电感器L 5的另一端与第六电容器C 6的一端和第六电感器L 6的一端均连接,第六电容器C 6的另一端接地,第六电感器L 6的另一端连接至直流电压端,所述直流电压端被配置成经由第六电感器L 6、第五电感器L 5、第四电感器L 4、所述主输出网络和所述辅输出网络向所述主放大器和所述辅放大器提供直流偏置电压V DD
在一些实施例中,所述合路匹配网络可以具有电路拓扑720,即所 述合路匹配网络包括第三传输线TL 3、第四传输线TL 4、第五传输线TL 5、第六传输线TL 6和第七电容器C 7,第三传输线TL 3的一端连接至所述组合节点,第三传输线TL 3的另一端与第四传输线TL 4的一端和第五传输线TL 5的一端均连接,第四传输线TL 4的另一端连接至直流电压端和第七电容器C 7的一端,第七电容器C 7的另一端接地,第五传输线TL 5的另一端连接至第六传输线TL 6的一端,第六传输线TL 6的另一端浮接,所述直流电压端被配置成经由第四传输线TL 4、第三传输线TL 3、所述主输出网络和所述辅输出网络向所述主放大器和所述辅放大器提供直流偏置电压V DD
在一些实施例中,所述合路匹配网络可以具有电路拓扑730,即所述合路匹配网络包括第七电感器L 7、第八电容器C 8、第九电容器C 9、第十电容器C 10、第七传输线TL 7和第八传输线TL 8,第七电感器L 7的一端连接至所述组合节点,第七电感器L 7的另一端与第八电容器C 8的一端和第七传输线TL 7的一端均连接,第八电容器C 8的另一端接地,第七传输线TL 7的另一端与第九电容器C 9的一端和第八传输线TL 8的一端均连接,第九电容器C 9的另一端接地,第八传输线TL 8的另一端连接至直流电压端,第十电容器C 10的一端连接至所述直流电压端,第十电容器C 10的另一端接地,所述直流电压端被配置成经由第八传输线TL 8、第七传输线TL 7、第七电感器L 7、所述主输出网络和所述辅输出网络向所述主放大器和所述辅放大器提供直流偏置电压V DD
需要说明的是,尽管未在图7的各个电路拓扑中示出,本领域技术人员应理解,图7所示的电路拓扑710、720和730中的至少一种可以包括其他电路器件,例如用于隔离直流的电容器,利用这种用于隔离直流的电容器,来自所述直流电压端的直流信号不会被传输到所述多赫蒂放大器的射频输出端,从而可以保护敏感的射频元件(负载)免受直流电的影响。
此外,在上文关于图5和图6描述的实施例中,尽管没有公开向所述主放大器和所述辅放大器提供直流偏置电压V DD的相关偏置电路,但这仅仅是示意性的,本领域技术人员应理解,可以根据实际应用在这些实施例中设置相关偏置电路。可以灵活调整相关偏置电路的数量和其在多赫蒂放大器电路中的位置。示例性地,当多赫蒂放大器的主放大器和辅放大器的配置参数不相同时(例如,当它们不是一种类型 的晶体管时),可以为主放大器和辅放大器分别设置对应的直流偏置电路。示例性地,可以在所述主输出网络中设置相应的直流偏置电路来为主放大器提供直流偏置,在所述第一子网络或所述第二子网络中设置相应的直流偏置电路来为辅放大器提供直流偏置。替代地,可以在所述合路匹配网络中设置相应的直流偏置电路来为主放大器和辅放大器提供直流偏置(例如参见上文所述电路拓扑710、720和730)。
在一些实施例中,所述第一至第十电容器中的至少一个电容器可以通过以下中的至少一种形式来实现:PCB表贴元件、集成电路器件。
在一些实施例中,所述第一至第七电感器中的至少一个电感器可以通过以下中的至少一种形式来实现:PCB表贴元件、集成电路器件、键合线、微带线、金属绕线、传输线。
在一些实施例中,所述第三至第八传输线中的至少一条传输线可以通过以下中的至少一种形式来实现:微带线、带状线、共面波导、基片集成波导。
微带线是目前混合微波集成电路和单片微波集成电路使用最多的一种平面型传输线,它是一根带状导线(信号线),与地层之间用一种电介质隔离开。微带线可以通过PCB微带线和集成电路微带线等多种实现形式来实现。影响微带线的特性阻抗的因素包括微带线的厚度、宽度、与地层的距离以及电介质的介电常数等,微带线的长度可以对应于微带线的电角度。示例性地,可以用微带线来实现所述第三至第八传输线中的至少一条传输线。相应地,可以基于所述第三至第八传输线中的相应传输线的特性阻抗和电角度来配置微带线的长度、宽度等尺寸参数。通过使用微带线来实现所述第三至第八传输线中的相应传输线,可以获取满足特征参数要求的传输线,从而可以使得多赫蒂放大器具有较小的电路尺寸、较高的工作效率、较大的工作带宽和更深的回退功率(即更大的回退功率范围)。特别地,可以通过采用选取高介电常数的基材来实现微带线,以进一步减少相关电路的尺寸。
带状线是置于两个平行的接地平面(或电源平面)之间的电介质之间的高频传输导线。带状线具有体积小、重量轻、频带宽、品质因数高、工艺简单、成本低廉等优点,适于制作高性能(宽频带、高品质因数、高隔离度)无源元件。共面波导(CPW)通过在介质基片的一个面上制作出中心导体带、并在紧邻中心导体带的两侧制作出导体 平面而构成,在毫米波频段,共面波导比微带线和带状线电路的损耗更小。基片集成波导(SIW)利用金属通孔在介质基片上实现波导的场传播模式,具有低差损、低辐射、高品质因数等优点。在一些实施例中,所述第三至第八传输线中的至少一条传输线可以仅由带状线、共面波导或基片集成波导中的一个构成。
本申请的另一实施例提供了一种多赫蒂放大器,包括:主放大器;辅放大器;以及根据前述实施例中任一实施例所述的输出网络,其中所述输出网络被配置成接收所述主放大器的输出的第一放大信号和所述辅放大器输出的第二放大信号,使得所述第一放大信号和所述第二放大信号在所述组合节点处组合以提供给所述多赫蒂放大器的射频输出端。由于所述多赫蒂放大器包括根据本申请前述实施例的输出网络,因此所述多赫蒂放大器具有相应的输出网络带来的优点。下面结合图8来进一步描述这种多赫蒂放大器。
如图8所示,射频输入信号经过功分器后分别连接至主放大器和辅放大器(这些放大器可以为单级晶体管也可以是多级晶体管级联实现),其中主放大器和辅放大器的输入侧还包含输入匹配网络(即图8所示的输入匹配网络1和输入匹配网络2)和移相器网络(即图8所示的移相器1和移相器2),其中移相器网络可以只设置在辅路或者只设置在主路(例如,仅设置在辅路)。主放大器和辅放大器的输出侧为根据本申请前述实施例中任一实施例所述的输出网络,所述输出网络包括主输出网络810和辅输出网络820,辅输出网络820包括串联连接的第一子网络821和第二子网络822。合路匹配网络840被配置成使得组合节点830处的节点阻抗为复数阻抗,主输出网络810和辅输出网络820被配置成使得节点阻抗匹配至主放大器和辅放大器的目标负载阻抗。示例性地,(漏极)直流偏置电压可以通过主输出网络810和第一子网络821(或者合路匹配网络840)中的直流偏置电路馈电。
主输出网络810和第一子网络821可以具有上文关于图5描述的电路拓扑中的任一种,第二子网络822可以具有上文关于图6描述的电路拓扑,合路匹配网络840可以具有上文关于图7描述的电路拓扑中的任一种。可以通过选取主输出网络810、第一子网络821和第二子网络822的电路拓扑和元件参数,使得主输出网络810和辅输出网络820在工作频段所等效的传输线具有相应的特征阻抗、电长度和电角度, 从而使得多赫蒂放大器在高效率工作的同时,具备较大的工作带宽和较深的回退功率。
需要说明的是,尽管图8中示出的多赫蒂放大器仅包括一个辅放大器,但本领域技术人员应理解,本申请所公开的多赫蒂放大器可以包括更多个辅放大器(例如,两个辅放大器),在本申请前述实施例的基础上,这些辅放大器对应的多个辅路上的多个辅输出网络均可以采用本申请前述实施例中公开的电路结构。
图9示意性示出了根据本申请的一些实施例的多赫蒂放大器包括的封装结构的示意图。如图9所示,多赫蒂放大器包括封装载体900(其可以采用LGA结构或者QFN结构),封装载体900包括:金属焊盘901(主要目的为了承载电路元件,并提供散热和接地回路);主放大器电路芯片902,其输出端通过一组键合线906(通过调整键合线数量、间距、高度、长度可以控制其寄生等效电感)连接至焊盘907;辅放大器电路芯片903,类似于主放大器电路芯片902,其输出端同样通过一组键合线908连接至焊盘;输出匹配单元芯片904。其中主输出网络和第一子网络的电路拓扑类似于上文关于图5描述的电路拓扑510(但不包括第一电容器C 1),第二子网络采用上文关于图6描述的电路拓扑600。其中,键合线906用于实现主输出网络中的第一电感器L 1,从图9中可以看出,由于不需要寄生电容C dsM和C dsA(即第一电容器C 1),主放大器电路芯片902和辅放大器电路芯片903的输出端可以和键合线906、908直接相连,键合线908和910分别用于实现第一子网络中的第一电感器L 1和第二子网络中的第三电感器L 3(L 1可以等于L 3),电容909用于实现第一子网络中的第二电容器C 2,电容911用于实现主输出网络中的第二电容器C 2和第二子网络中的第四电容器C 4,即电容911可以被视为主输出网络中的第二电容器C 2和第二子网络中的第四电容器C 4的并联电容(C 2+C 4),输出匹配单元芯片904通过键合线912连接至封装输出引脚;另外主放大器电路芯片902和辅放大器电路芯片903的输入端通过键合线等方式电气连接至输入电路芯片915上的焊盘916和917,其连接至输入匹配电路,本申请对输入匹配电路的具体实现形式不作限定。
图10示意性示出了根据本申请的另一些实施例的多赫蒂放大器包括的封装结构的示意图。如图10所示,多赫蒂放大器包括封装载体1000 (其可以采用LGA结构或者QFN结构),封装载体1000包括:金属焊盘1001(主要目的为了承载电路元件,并提供散热和接地回路);主放大器电路芯片1002,其输出端通过一组键合线1005连接至焊盘1006,这里键合线1005的高度、长度被控制的尽可能小,从而其寄生电感特性可以忽略不计;辅放大器电路芯片1003,类似于主放大器电路芯片1002,其输出端同样通过一组键合线连接至焊盘;输出匹配单元芯片1004,其中主输出网络和第一子网络采用上文关于图5描述的电路拓扑520,第二子网络采用上文关于图6描述的电路拓扑600。其中,主输出网络和第一子网络中的第一电容器C 1可以分别是主放大器电路芯片1002和辅放大器电路芯片1003中的晶体管的寄生电容C dsM和C dsA,电容1007用于实现主输出网络中的第三电容器C 3,键合线1008(通过调整键合线数量、间距、高度、长度可以控制其寄生等效电感)用于实现主输出网络中的第一电感器L 1,电容1011、1012分别用于实现第一子网络中的第三电容器C 3和第二电容器C 2,键合线1009和1010分别用于实现第一子网络中的第一电感器L 1和第二子网络中的第三电感器L 3,电容1013用于实现主输出网络中的第二电容器C 2和第二子网络中的第四电容器C 4,即电容1013可以被视为主输出网络中的第二电容器C 2和第二子网络中的第四电容器C 4的并联电容(C 2+C 4),输出匹配单元芯片1004通过键合线1014连接至封装输出引脚;另外主放大器电路芯片1002和辅放大器电路芯片1003的输入端通过键合线等方式电气连接至输入电路芯片1016上的焊盘1017和1018,其连接至输入匹配电路,本申请对输入匹配电路的具体实现形式不作限定。
图11示意性示出了根据本申请的又一些实施例的多赫蒂放大器包括的封装结构的示意图。如图11所示,多赫蒂放大器包括封装载体1100(其可以采用LGA结构或者QFN结构),封装载体1100包括:金属焊盘1101(主要目的为了承载电路元件,并提供散热和接地回路);主放大器电路芯片1102,其输出端通过一组键合线1106(通过调整键合线数量、间距、高度、长度可以控制其寄生等效电感)连接至焊盘1107;辅放大器电路芯片1103,类似于主放大器电路芯片1102,其输出端同样通过一组键合线1108连接至焊盘;输出匹配单元芯片1104。其中主输出网络和第一子网络的电路拓扑类似于上文关于图5描述的电路拓扑530(但不包括第一电容器C 1),第二子网络采用上文关于 图6描述的电路拓扑600。其中,键合线1106用于实现主输出网络中的第一电感器L 1,从图11中可以看出,由于不需要寄生电容C dsM和C dsA(即第一电容器C 1),主放大器电路芯片1102和辅放大器电路芯片1103的输出端可以和键合线1106、1108直接相连,键合线1108和1110分别用于实现第一子网络中的第一电感器L 1和第二子网络中的第三电感器L 3(L 1可以等于L 3),电容1109用于实现第一子网络中的第二电容器C 2,电容1111用于实现主输出网络中的第二电容器C 2和第二子网络中的第四电容器C 4,即电容1111可以被视为主输出网络中的第二电容器C 2和第二子网络中的第四电容器C 4的并联电容(C 2+C 4),输出匹配单元芯片1104通过键合线1112连接至封装输出引脚;另外主放大器电路芯片1102和辅放大器电路芯片1103的输入端通过键合线等方式电气连接至输入电路芯片1115上的焊盘1116和1117,其连接至输入匹配电路,本申请对输入匹配电路的具体实现形式不作限定。
此外,如图11所示,主放大器电路芯片1102的输出端还通过键合线1118连接至封装引脚1119,辅放大器电路芯片1103的输出端通过键合线1120连接至封装引脚1121,通过调整键合线1118、1120的数量、间距、高度、长度等,可以控制其寄生等效电感以实现主输出网络中的第二电感器L 2和第一子网络中的第二电感器L 2,封装引脚1119和1121可以通过外部电路直接或间接连接到地。
图12示意性示出了根据本申请的一些实施例的电感的多种实现方式的示意图。如图12所示,在输出匹配单元芯片1200和1210(它们可以用于实现上文关于图9-11中描述的任一输出匹配单元芯片)中,电感除了由键合线的寄生电感实现,还可以用金属线或者传输线的形式来实现。图12左侧示出了主输出网络中的第一电感器L 1由金属绕线1204实现的一个示例(第一子网络中的第一电感器L 1和第二子网络中的第三电感器L 3则依然由键合线1205和1207实现),通过调整金属绕线的长度、线宽和绕线形式(比如间距和长度)可以调整其等效电感。图12右侧则示出了全部电感(主输出网络中的第一电感器L 1、第一子网络中的第一电感器L 1和第二子网络中的第三电感器L 3)均由金属绕线(1214、1215和1217)实现的一个示例。
图13示意性示出了根据本申请的一些实施例的多赫蒂放大器的结构示意图。如图13所示,多赫蒂放大器包括电路载体1300,电路载体 1300包括:封装结构1301(其可以是图9-11所示的任一种封装结构),其主要由输入电路1303a、晶体管放大器1303,1304和输出电路1302构成,输出电路1302通过键合线1305连接至引脚1306并连接至外围PCB电路以实现上文关于图7所描述的电路拓扑730,其中1305为第七电感器L 7,1308为第八电容器C 8,1307为第七传输线TL 7,1309为第九电容器C 9,第九电容器C 9的另一端连接在焊盘上并通过通孔1310连接到地,1311为第八传输线TL 8,1312为第十电容器C 10,1313为滤波电容,1316为隔直电容,1315为外部直流电压端口,其可以通过1311(第八传输线TL 8)、1307(第七传输线TL 7)为晶体管提供漏极电压,1317为SMA接头(其提供多赫蒂放大器的射频输出端口)。输入端1320通过传输线1319连接至相应的接头(其提供多赫蒂放大器的射频输入端口),另外1318所标记的多个直流端口可以为封装结构1301提供所需的直流偏置电压(如栅极电压以及驱动电路的直流电压)。
本申请的另外的实施例提供了一种设计多赫蒂放大器的方法,所述多赫蒂放大器包括主放大器、辅放大器、以及上文关于图2描述的输出网络200,图14示意性示出了根据本申请的一些实施例的设计多赫蒂放大器的方法的流程图1400。如图14所示,所述方法包括以下步骤:
在步骤1410,设置所述多赫蒂放大器的目标性能指标,所述目标性能指标至少包括所述多赫蒂放大器的工作频率、饱和功率、以及动态范围;在步骤1420,根据所述目标性能指标,选取用于所述主放大器和所述辅放大器的晶体管,晶体管的选取可以考虑多方面的设计需求,例如功率、成本、尺寸等,可以参考上文对不同类型晶体管的描述,本申请对此不作限定;在步骤1430,基于负载牵引测试或仿真分析,确定第一、第二和第三目标阻抗,其中所述第一目标阻抗为所述多赫蒂放大器处于回退功率状态时使得所述主放大器效率最高的负载阻抗,所述第二目标阻抗为所述主放大器输出功率达到饱和功率时使得所述主放大器效率最高的负载阻抗,所述第三目标阻抗为所述辅放大器输出功率达到饱和功率时使得所述辅放大器效率最高的负载阻抗;在步骤1440,基于所述第一、第二和第三目标阻抗,确定所述辅输出网络中的各个子网络和所述主输出网络的电路拓扑和元件参数,并且 确定所述合路匹配网络的电路拓扑和元件参数。
利用本申请的实施例提出的设计多赫蒂放大器的方法,可以获得结构更加紧凑、电路结构和设计流程得以简化的多赫蒂放大器。另外,该多赫蒂放大器还能够实现从低功率到高功率范围内的高效工作,具有更深的回退功率和更宽的工作带宽。
以下给出使用上述设计方法,所获得的图13所示的输出电路1302的参数设计实例(在输出电路1302对应的输出网络中,主输出网络和辅输出网络的第一子网络采用上文关于图5描述的电路拓扑510,辅输出网络的第二子网络采用上文关于图6描述的电路拓扑600):
所述输出网络对应的多赫蒂放大器可以应用于5G移动通信系统中(3.5GHz频段、32T发射机阵列、基站放大器),主放大器为总栅宽4.8mm的基于氮化镓(GaN)半导体工艺的晶体管,其饱和功率为50W,寄生电容C dsM为2pF(这里C dsM为主输出网络中的第一电容器);辅放大器为总栅宽8.4mm的基于氮化镓(GaN)半导体工艺的晶体管,其饱和功率为85W,寄生电容C dsA为3pF(这里C dsA为第一子网络中的第一电容器);所述输出网络1100中各个子网络的其他元件参数如下:
L 1=0.926nH(这里L 1为主输出网络中的第一电感器);
C M=2.03pF(这里C M为主输出网络中的第二电容器);
L A=0.358nH(这里L A为第一子网络中的第一电感器、以及第二子网络中的第三电感器);
C 1=5.74pF(这里C 1为第一子网络中的第二电容器);
C 2=2.87pF(这里C 2为第二子网络中的第四电容器);
Z combine=2.31-j2.49。
其中主输出网络在3.5GHz频段其射频特征可等效为电长度为86°的传输线,辅输出网络在3.5GHz频段其射频特征可等效为电长度为161°的传输线。
图15和图16示意性示出了根据本申请的一些实施例的多赫蒂放大器的性能示例图。如图15所示,根据本申请的一些实施例的多赫蒂放大器和传统的多赫蒂放大器的放大器直流-射频转换效率随着输出功率变化的情况分别如曲线1510、1520所示,可以看出,在低输出功率状态下,根据本申请的一些实施例的多赫蒂放大器的效率远高于传统 方案。如图16所示,根据本申请的一些实施例的多赫蒂放大器和传统的多赫蒂放大器的放大器小信号增益分别如曲线1610、1620所示,可以看出,根据本申请的一些实施例的多赫蒂放大器的带宽远大于传统的多赫蒂放大器(是传统的多赫蒂放大器的带宽的两倍以上)。
将理解的是,尽管第一、第二、第三等术语在本文中可以用来描述各种设备、元件、部件或部分,但是这些设备、元件、部件或部分不应当由这些术语限制。这些术语仅用来将一个设备、元件、部件或部分与另一个设备、元件、部件或部分相区分。本文提到的“连接”包括“直接连接”或“间接连接”。
尽管已经结合一些实施例描述了本申请,但是其不旨在被限于在本文中所阐述的特定形式。相反,本申请的范围仅由所附权利要求来限制。附加地,尽管单独的特征可以被包括在不同的权利要求中,但是这些可以可能地被有利地组合,并且包括在不同权利要求中不暗示特征的组合不是可行的和/或有利的。特征在权利要求中的次序不暗示特征必须以其工作的任何特定次序。此外,在权利要求中,词“包括”不排除其他元件,并且术语“一”或“一个”不排除多个。权利要求中的附图标记仅作为明确的例子被提供,不应该被解释为以任何方式限制权利要求的范围。

Claims (15)

  1. 一种用于多赫蒂放大器的输出网络,所述多赫蒂放大器包括主放大器和辅放大器,所述输出网络包括:组合节点、连接在所述主放大器的输出端和所述组合节点之间的主输出网络、连接在所述辅放大器的输出端和所述组合节点之间的辅输出网络、以及连接在所述组合节点和所述多赫蒂放大器的射频输出端之间的合路匹配网络,
    其中所述辅输出网络包括串联连接的第一子网络和第二子网络,所述第一子网络和所述主输出网络具有相同的电路拓扑并且均至少包括电感和电容,并且所述第二子网络至少包括电感,
    其中所述合路匹配网络被配置成使得所述组合节点处的节点阻抗为复数阻抗,所述主输出网络和所述辅输出网络被配置成使得所述节点阻抗匹配至所述主放大器和所述辅放大器的目标负载阻抗。
  2. 根据权利要求1所述的输出网络,其中所述主输出网络在工作频段等效为第一传输线,所述辅输出网络在工作频段等效为第二传输线,所述第一传输线的电角度θ M和所述第二传输线的电角度θ A满足:70°<θ M<90°,并且135°<θ A<180°。
  3. 根据权利要求1所述的输出网络,其中所述输出网络被配置成使得所述主放大器的输出电流I M和所述辅放大器的输出电流I A满足:I M的幅值不大于I A的幅值,并且I M和I A的相位差小于90°。
  4. 根据权利要求1所述的输出网络,其中所述第一子网络和所述主输出网络均包括第一电容器、第二电容器和第一电感器,所述第一电容器的一端和所述第一电感器的一端均连接至所述主放大器或所述辅放大器的输出端,所述第一电容器的另一端接地,所述第一电感器的另一端连接至所述第二电容器的一端,所述第二电容器的另一端接地。
  5. 根据权利要求4所述的输出网络,其中所述第一子网络和所述主输出网络均还包括第三电容器,所述第三电容器的一端连接至所述主放大器或所述辅放大器的输出端,所述第三电容器的另一端接地。
  6. 根据权利要求4所述的输出网络,其中所述第一子网络和所述主输出网络均还包括第二电感器,所述第二电感器的一端连接至所述主放大器或所述辅放大器的输出端,所述第二电感器的另一端接地。
  7. 根据权利要求1所述的输出网络,其中所述第二子网络包括第三电感器和第四电容器,所述第三电感器的一端连接至所述第一子网络的输出端,所述第三电感器的另一端连接至所述第四电容器的一端,所述第四电容器的另一端接地。
  8. 根据权利要求1所述的输出网络,其中所述合路匹配网络包括第四电感器、第五电感器、第六电感器、第五电容器和第六电容器,所述第四电感器的一端连接至所述组合节点,所述第四电感器的另一端与所述第五电容器的一端和所述第五电感器的一端均连接,所述第五电容器的另一端接地,所述第五电感器的另一端与所述第六电容器的一端和所述第六电感器的一端均连接,所述第六电容器的另一端接地,所述第六电感器的另一端连接至直流电压端,所述直流电压端被配置成经由所述第六电感器、所述第五电感器、所述第四电感器、所述主输出网络和所述辅输出网络向所述主放大器和所述辅放大器提供直流偏置电压。
  9. 根据权利要求1所述的输出网络,其中所述合路匹配网络包括第三传输线、第四传输线、第五传输线、第六传输线和第七电容器,所述第三传输线的一端连接至所述组合节点,所述第三传输线的另一端与所述第四传输线的一端和所述第五传输线的一端均连接,所述第四传输线的另一端连接至直流电压端和所述第七电容器的一端,所述第七电容器的另一端接地,所述第五传输线的另一端连接至所述第六传输线的一端,所述第六传输线的另一端浮接,所述直流电压端被配置成经由所述第四传输线、所述第三传输线、所述主输出网络和所述辅输出网络向所述主放大器和所述辅放大器提供直流偏置电压。
  10. 根据权利要求1所述的输出网络,其中所述合路匹配网络包括第七电感器、第八电容器、第九电容器、第十电容器、第七传输线和第八传输线,所述第七电感器的一端连接至所述组合节点,所述第七电感器的另一端与所述第八电容器的一端和所述第七传输线的一端均连接,所述第八电容器的另一端接地,所述第七传输线的另一端与所述第九电容器的一端和所述第八传输线的一端均连接,所述第九电容器的另一端接地,所述第八传输线的另一端连接至直流电压端,所述第十电容器的一端连接至所述直流电压端,所述第十电容器的另一端接地,所述直流电压端被配置成经由所述第八传输线、所述第七传输 线、所述第七电感器、所述主输出网络和所述辅输出网络向所述主放大器和所述辅放大器提供直流偏置电压。
  11. 根据权利要求4-10中任一项所述的输出网络,其中所述第一至第十电容器中的至少一个电容器可以通过以下中的至少一种形式来实现:PCB表贴元件、集成电路器件。
  12. 根据权利要求4、6、7、8以及10中任一项所述的输出网络,其中所述第一至第七电感器中的至少一个电感器可以通过以下中的至少一种形式来实现:PCB表贴元件、集成电路器件、键合线、微带线、金属绕线、传输线。
  13. 根据权利要求9和10中任一项所述的输出网络,其中所述第三至第八传输线中的至少一条传输线可以通过以下中的至少一种形式来实现:微带线、带状线、共面波导、基片集成波导。
  14. 一种多赫蒂放大器,包括:
    主放大器;
    辅放大器;以及
    根据权利要求1-13中任一项所述的输出网络,
    其中所述输出网络被配置成接收所述主放大器的输出的第一放大信号和所述辅放大器输出的第二放大信号,使得所述第一放大信号和所述第二放大信号在所述组合节点处组合以提供给所述多赫蒂放大器的射频输出端。
  15. 一种设计多赫蒂放大器的方法,所述多赫蒂放大器包括主放大器、辅放大器、以及如权利要求1所述的输出网络,其中所述方法包括:
    设置所述多赫蒂放大器的目标性能指标,所述目标性能指标至少包括所述多赫蒂放大器的工作频率、饱和功率、以及动态范围;
    根据所述目标性能指标,选取用于所述主放大器和所述辅放大器的晶体管;
    基于负载牵引测试或仿真分析,确定第一、第二和第三目标阻抗,其中所述第一目标阻抗为所述多赫蒂放大器处于回退功率状态时使得所述主放大器效率最高的负载阻抗,所述第二目标阻抗为所述主放大器输出功率达到饱和功率时使得所述主放大器效率最高的负载阻抗,所述第三目标阻抗为所述辅放大器输出功率达到饱和功率时使得所述 辅放大器效率最高的负载阻抗;
    基于所述第一、第二和第三目标阻抗,确定所述辅输出网络中的各个子网络和所述主输出网络的电路拓扑和元件参数,并且确定所述合路匹配网络的电路拓扑和元件参数。
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