WO2023040117A1 - Substrat matriciel, panneau d'affichage et dispositif électronique - Google Patents

Substrat matriciel, panneau d'affichage et dispositif électronique Download PDF

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Publication number
WO2023040117A1
WO2023040117A1 PCT/CN2021/142289 CN2021142289W WO2023040117A1 WO 2023040117 A1 WO2023040117 A1 WO 2023040117A1 CN 2021142289 W CN2021142289 W CN 2021142289W WO 2023040117 A1 WO2023040117 A1 WO 2023040117A1
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WO
WIPO (PCT)
Prior art keywords
aperture area
array substrate
imaging aperture
line
imaging
Prior art date
Application number
PCT/CN2021/142289
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English (en)
Chinese (zh)
Inventor
毛晗
郑浩旋
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惠科股份有限公司
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Publication of WO2023040117A1 publication Critical patent/WO2023040117A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present application relates to the technical field of display devices, in particular to an array substrate, a display panel and electronic devices.
  • the metal traces at the camera hole are all of the same line width, and the metal traces around the camera hole are longer than the non-camera hole positions, which leads to uneven loads on capacitors and resistors. , prone to uneven display problems.
  • the main purpose of this application is to propose an array substrate.
  • the metal wiring at the imaging hole and the cutout of the array substrate the metal wiring at the imaging hole and the rest of the metal wiring have the same load value, thereby Solve the problem of uneven display caused by different loads.
  • the array substrate proposed in this application includes a substrate and a plurality of parallel scanning lines and a plurality of parallel data lines arranged on the substrate, each of the scanning lines and each of the data lines Vertically staggered, the base is provided with a camera hole area;
  • At least two parts of the data lines are arranged around the area of the imaging aperture, at least two parts of the scanning lines are arranged around the area of the imaging aperture, and the setting part is arranged around the area of the imaging aperture
  • the scanning line is the first scanning line
  • the scanning line not surrounding the imaging aperture area is the second scanning line
  • the data line surrounding the imaging aperture area is set as the first data line
  • the scanning line not surrounding the imaging aperture area is set as the first scanning line.
  • the scanning line is the second data line;
  • the width of the portion of the first data line and/or the first scanning line surrounding the imaging aperture area increases gradually.
  • the number of pixel units formed by two adjacent data lines and scanning lines is gradually decreased with tolerances such as the first tolerance
  • the number of pixel units formed by two adjacent scan lines and data lines decreases gradually with a tolerance such as a second tolerance.
  • the width of the part of the first scanning line surrounding the imaging aperture area increases with tolerances such as the third tolerance, wherein, The third tolerance is equal to the first tolerance.
  • the width of the first data line increases with tolerances such as the fourth tolerance, wherein the fourth tolerance is equal to the second tolerance.
  • the shape of the imaging hole area is a drop shape or a bang shape
  • the number of pixel units formed by two adjacent first scanning lines and data lines is in a first non-arithmetic sequence decrease
  • the number of pixel units formed by adjacent two first data lines and scanning lines decreases in a second asymmetric sequence.
  • the width of the part of the first scanning line surrounding the imaging aperture area increases in a first unequal sequence .
  • the width of the part of the first data line surrounding the imaging aperture area increases in a second non-alertometric sequence.
  • each of the first scanning lines includes two first straight line segments and a first arc line segment, and the two ends of the first arc line segment are respectively connected to the two first straight line segments , the first arc segment closest to the camera hole area is spaced from the edge of the camera hole area;
  • each of the first data lines includes two second straight line segments and a second arc segment, the two ends of the second arc segment are respectively connected to the two second straight line segments, and the closest The second arc segment of the camera hole area is spaced apart from the edge of the camera hole area.
  • the present application also proposes a display panel, including a color filter substrate, an array substrate, and a liquid crystal layer, the color filter substrate and the array substrate are arranged in a box, and the array substrate is the array substrate as described above.
  • the present application also proposes an electronic device, which includes a housing and a display panel disposed on the housing, where the display panel is the above-mentioned display panel.
  • the array substrate includes a substrate and data lines and scanning lines arranged on the substrate, and an imaging hole area is also arranged on the substrate, and the data lines and scanning lines are arranged in sequence and staggered.
  • the first A part of a data line surrounds the imaging hole area, and the number of segments that normally form pixels becomes less.
  • the second data line is not affected by the imaging hole area and has a normal length.
  • a part of the first scanning line surrounds the imaging hole. area, the number of segments that normally form pixels is reduced, and the length of the second scanning line is normal. The smaller the number, the corresponding resistance load increases and the capacitive load decreases.
  • the width of the part of the first data line and/or the first scanning line surrounding the imaging aperture area increases gradually, and also That is, reduce the resistive load of the first data line and/or the first scan line, increase the capacitive load of the first data line and/or the first scan line, thereby compensating for the lost pixel load, effectively reducing the Load difference to improve display quality.
  • FIG. 1 is a schematic top view of an array substrate in Embodiment 1 of the present application.
  • FIG. 2 is an arrangement diagram of pixel units in the array substrate shown in FIG. 1;
  • FIG. 3 is a partially enlarged structural schematic diagram of scanning lines in the array substrate shown in FIG. 1;
  • FIG. 4 is a partially enlarged structural schematic diagram of data lines in the array substrate shown in FIG. 1;
  • FIG. 5 is a schematic top view of the array substrate in Embodiment 2 of the present application.
  • FIG. 6 is an arrangement diagram of pixel units of the array substrate shown in FIG. 5;
  • FIG. 7 is a partially enlarged structural schematic diagram of the scanning lines corresponding to the array substrate shown in FIG. 5;
  • FIG. 8 is a partially enlarged structural schematic diagram of data lines corresponding to the array substrate shown in FIG. 5;
  • FIG. 9 is a schematic top view of the array substrate in Embodiment 3 of the present application.
  • FIG. 10 is an arrangement diagram of pixel units of the array substrate shown in FIG. 9;
  • FIG. 11 is a schematic structural diagram of scanning lines corresponding to the array substrate shown in FIG. 9;
  • FIG. 12 is a cross-sectional view of a display panel in Embodiment 4 of the present application.
  • FIG. 13 is a partial structural schematic diagram of the first electronic device in Embodiment 5 of the present application.
  • FIG. 14 is a partial structural schematic diagram of the second electronic device in Embodiment 5 of the present application.
  • FIG. 15 is a partial structural diagram of the third electronic device in Embodiment 5 of the present application.
  • the directional indications are only used to explain the position in a certain posture (as shown in the attached figure). If the specific posture changes, the directional indication will also change accordingly.
  • the present application provides an array substrate 100 .
  • the array substrate 100 includes a substrate 10 and a plurality of parallel scanning lines 50 and a plurality of parallel data lines 30 arranged on the substrate 10, each of the scanning lines 50 and each of the data
  • the lines 30 are vertically staggered, and the substrate 10 is provided with an imaging hole area 10a;
  • At least two parts of the data line 30 are arranged around the imaging aperture area 10a, at least two parts of the scanning line 50 are arranged around the imaging aperture area 10a, and the setting part is arranged around the imaging aperture area 10a.
  • the scanning line 50 of the imaging aperture area 10a is the first scanning line 51
  • the scanning line 50 not surrounding the imaging aperture area 10a is the second scanning line 53
  • the data line 30 surrounding the imaging aperture area 10a is set as The first data line 31, the scanning line 50 not surrounding the imaging aperture area 10a is the second data line 33;
  • the width of the portion of the first data line 31 and/or the first scanning line 51 surrounding the imaging aperture area 10a increases gradually.
  • the array substrate 100 is a multi-layer structure, and each layer structure is formed layer by layer through coating, exposure, development and etching processes.
  • the array substrate 100 includes a base 10 , which provides a basic carrier.
  • the base 10 is transparent, and its material may be a transparent glass plate or a quartz plate, which is not limited here, as long as it does not affect the passage of the backlight. Since the substrate 10 is non-conductive, the movement and arrangement of the medium used for display, such as liquid crystal, need electrons to drive, so the array substrate 100 also includes conductive data lines 30 (Data Line, DL) and scanning lines 50 (SL, Scanning line), thin film transistor (TFT switch) and pixel electrode (Pixel Electrode, PE), etc.
  • Data Line, DL Data Line
  • scanning lines 50 SL, Scanning line
  • TFT switch thin film transistor
  • PE Pixel Electrode
  • a plurality of data lines 30 and a plurality of scan lines 50 are intersected to divide the array substrate 100 to form a plurality of pixel regions, and each region corresponds to a pixel electrode and a thin film transistor, because the data lines 30 and the scanning line 50 are opaque, so the part where they are located forms the non-display area of the pixel area, the thin film transistor is also arranged in the non-display area, and the pixel electrode forms the display area of the pixel area.
  • a camera hole area 10a is also provided on the base 10 to correspond to the camera, so that the camera can realize the function of taking pictures or taking photos through the camera.
  • some sections of the scanning line 50 and the data line 30 arranged in a straight line are arc-shaped, so as to fit the edge of the imaging aperture area 10a.
  • the scanning line 50 partially surrounding the imaging aperture area 10a is set as the first scanning line 51
  • the data line 30 partially surrounding the imaging aperture area 10a is set as the first data line 31
  • the normally arranged scanning lines 50 is the second scanning line 53
  • the normally arranged data lines 30 are the second data lines 33 .
  • each of the first scanning lines 51 includes two first straight line segments 511 and a first arc line segment 513, and the two ends of the first arc line segment 513 are connected to the two first straight line segments 511 respectively.
  • the first arc segment 513 is arranged around the imaging aperture area 10a
  • each of the first data lines 31 includes two second straight line segments 311 and a second arc segment 313, and the two ends of the second arc segment 313
  • the two second straight line segments 311 are respectively connected
  • the second arc segment 313 is arranged around the imaging hole area 10a.
  • the length of the first scanning line 51 is greater than the length of the second scanning line 53, and the closer to the imaging aperture area 10a, the longer the length of the first arc segment 513 is, and the shorter the length of the first straight line segment 511 is;
  • the length of the data line 31 is greater than the length of the second data line 33, and the closer to the imaging aperture area 10a, the longer the length of the second arc segment 313, and the shorter the length of the second straight line segment 311, and the pixel unit of the array substrate 100 10b is formed by interlacing at least two of the second data line 33, the second scanning line 53, the first straight line segment 511, and the second straight line segment 311.
  • the imaging The pixel units 10b formed in the aperture area 10a are less than the pixel units 10b in the non-photographic aperture area, so in order to compensate for the capacitance and resistance load here, the width of the first arc segment 513 and the second arc segment 313 here increase, thereby reducing load differences in different regions.
  • the width of each first arc segment 513 and/or each second arc segment 313 may increase uniformly along its extending direction, or may increase in some sections, which is not limited herein.
  • the imaging hole is generally circular, so the imaging hole area 10a is generally set in the shape of a round hole, a drop shape or a bangs shape. Of course, in other embodiments, it can also be set in a square or polygonal shape, which is not limited here. .
  • the array substrate 100 includes a base 10 and data lines 30 and scan lines 50 provided on the base 10, and an imaging hole area 10a is also arranged on the base 10, and the data lines 30 and scan lines 50 are arranged in a staggered order , when passing through the imaging aperture area 10a, a part of the first data line 31 surrounds the imaging aperture area 10a, and the number of segments normally forming pixels becomes less, and the second data line 33 is not affected by the imaging aperture area 10a, as Normal length, part of the first scanning line 51 surrounds the imaging aperture area 10a, and the number of segments that normally form pixels becomes less, the length of the second scanning line 53 is normal, the closer to the first scanning line of the imaging aperture area 10a 51 and the length of the first data line 31 around the longer, then the number of correspondingly formed pixel units 10b is less, the corresponding resistance load increases, and the capacitive load decreases.
  • the width of the part of the first data line 31 and/or the first scanning line 51 surrounding the imaging aperture area 10a is gradually increased, that is, the resistance load of the first data line 31 and/or the first scanning line 51 is reduced, and the first data line is increased.
  • 31 and/or the capacitive load of the first scan line 51 so as to compensate the lost pixel load, effectively reduce the load difference in different regions of the array substrate 100, and improve the display quality.
  • a metal layer is first deposited on the substrate 10, and the metal layer is patterned through a photomask to form the data line 30 on the substrate 10, so that the thin film transistor can be provided with an on-off voltage, simultaneously with the data line 30 A grid is also formed.
  • the process of patterning through a photomask is to deposit a photoresist on the metal layer, expose and develop after being covered by a photomask, and then perform etching.
  • the material of the metal layer is an opaque conductive metal material, such as a combination of one or more of molybdenum, titanium, chromium and aluminum, which is not limited herein.
  • a gate insulating layer is formed on the gate and data lines 30, and an active layer, a source electrode and a drain electrode which are in contact with both ends of the active layer and arranged at intervals are sequentially formed on the gate insulating layer, thereby completing the thin film transistor.
  • a passivation layer is deposited on the source, drain, and gate insulating layers, and the passivation layer is patterned through a photomask process to form a via hole through the passivation layer, which can be exposed part of the drain; finally, a transparent conductive layer is formed on the passivation layer, and the transparent conductive layer is patterned through a photomask process to form a pixel electrode of a specific shape, and the pixel electrode is in electrical contact with the drain through a via hole, thereby corresponding to the pixel unit 10b
  • the display area of the display area is provided with the voltage for liquid crystal movement, and the fabrication of the array substrate 100 is completed.
  • the number of pixel units 10b formed by two adjacent data lines 30 and scanning lines 50 decreases gradually with a first tolerance of d1;
  • the number of pixel units 10b formed by two adjacent scanning lines 50 and data lines 30 has a second tolerance of d2 and other tolerances decrease.
  • the extending direction of the scanning line 50 is the horizontal direction
  • the extending direction of the second data line 33 is the vertical direction.
  • the first arc segment 513 of the first scan line 51 is also arranged axisymmetrically with the diameter in the horizontal direction of the imaging aperture area 10a
  • the second arc segment 313 of the first data line 31 is The vertical diameter of the imaging aperture area 10a is arranged axially symmetrically, and the first straight line segment 511 and the second straight line segment 311 are also arranged axially symmetrically with the diameter of the imaging aperture area 10a as the axis.
  • the first straight line segment 511, the second straight line segment 311, the second scanning line 53, and the second data line 33 are composed of
  • the tolerances such as the number of pixel units 10b decrease, and the first tolerance is set to d1, for example, the number of pixel units 10b normally formed on a second scan line 53 is N1, then the first scan line next to the second scan line 53
  • the number of pixel units 10b formed on 51 is N1-d1, and toward the center of the imaging aperture area 10a, the number of pixel units 10b formed by the first scanning line 51 is N1-2d1, N1-3d1..., located at The row where the first scanning line 51 is located on the diameter of the imaging aperture area 10 a forms the least number of pixel units 10 b.
  • the number of pixel units 10b formed by two adjacent scanning lines 50 and data lines 30 is set to a second tolerance of d2 and other tolerances Decrease, for example, the second data line 33 forms N2 pixel units 10b, then the number of pixel units 10b formed by the first data line 31 is N2-d2, N2-2d2, N2-3d2..., so that the data line 30 And the processing of the scanning line 50 makes the distribution of pixels at the edge of the imaging aperture area 10a uniform, without affecting the display effect.
  • the values of N1 and N2 can be the same, for example, the formed pixel unit 10b is a square; of course, the two can also be different, for example, the formed pixel unit 10b is rectangular, similarly, the first tolerance d1 and the second The tolerance d2 can be the same or different, and can be set according to the actual situation.
  • the width of the part of the first scanning line 51 surrounding the imaging aperture area 10a is equal to the second
  • the three tolerances are increments of d3 and other tolerances, wherein said d3 is equal to d1.
  • the width of the first arc segment 513 of the first scanning line 51 is set as D1, which is represented by the first arc segment 513.
  • the three tolerances are that d3 increases with equal tolerance, that is, in the vertical direction, in the direction from one end of the data line 30 to the other end, the width of the first arc segment 513 of the first scan line 51 is increased with equal tolerance first. , and then wait for the tolerance to decrease.
  • setting d3 and d1 to be the same can compensate the load value of missing pixels, thereby minimizing the difference in capacitive and resistive loads between the non-photographic aperture area and the imaging aperture area 10a, so that the display screen at each position is uniform.
  • the width of the first arc segment 513 can be set uniformly, or the width of a certain segment can be increased.
  • the width of the first data line 31 increases with a fourth tolerance of d4 and other tolerances, wherein , d4 is equal to d2.
  • the width of the second arc segment 313 of the first data line 31 is set to be D2, and the fourth Incremental tolerances such as tolerance d4. That is, in the horizontal direction, from one end to the other end of the scan line 50 , the width of the second arc segment 313 of the first data line 31 first waits for the tolerance to increase, and then waits for the tolerance to decrease.
  • setting d4 and d2 to be the same can compensate the load value of missing pixels, thereby minimizing the difference in capacitive and resistive loads between the non-photographic aperture area and the imaging aperture area 10a, so that the display screen at each position is uniform.
  • the width of the second arc segment 313 is set uniformly along its extending direction, which improves the convenience of processing.
  • part of the sections may also be widened, so that the widths are inconsistent in the extending direction.
  • the number of pixel units 10b formed by two adjacent first scanning lines 51 and data lines 30 is equal to or greater than Decrease of the first unequal progression
  • the number of pixel units 10b formed by two adjacent first data lines 31 and scanning lines 50 is the second unequal difference. Decremented sequence.
  • the imaging aperture area 10a is in the shape of a water droplet, which is an inverted shape of a normally falling water droplet, that is, in the vertical direction, the upper dimension of the imaging aperture area 10a is larger and the lower dimension is smaller. Therefore, in the vertical direction, the scanning lines 50 and the data lines 30 at the peripheral edge of the imaging aperture area 10 a are not arranged symmetrically about the axis, nor are they arranged symmetrically about the center. In the horizontal direction, the scan lines 50 and the data lines 30 around the imaging hole area 10a can be arranged axisymmetrically with the center line of the imaging hole area 10a as the axis.
  • the number of pixel units 10b formed on the periphery of the imaging aperture area 10a of the substrate 10 decreases with the first non-alertically differential sequence, for example, normally formed
  • the number of pixel units 10b on each horizontal line is N3, then the number of pixel units 10b formed on the horizontal line where the first scanning line 51 of the second scanning line 53 is located is N3-a1, toward the direction of the imaging aperture area 10a
  • the number of pixel units 10b to be formed is N3-b1, N3-c1, . . . in sequence.
  • the number of pixel units 10b formed by adjacent two first data lines 31 and the scanning line 50 decreases in a second unequal sequence, for example , the number of pixel units 10b on each vertical line that is normally formed is N4, then the number of pixel units 10b formed on the horizontal line where the first scan line 51 adjacent to the second scan line 53 is located is N4-a2.
  • the number of pixel units 10b formed is N4-b2, N4-c2, . . .
  • the number of pixel units 10b formed by the first data line 31 decreases firstly, and then increases, and the first data line 31 is arranged symmetrically with the central axis of the imaging aperture area 10a, Therefore, the processing of the array substrate 100 is more convenient and the processing efficiency is improved.
  • the first scanning line 51 surrounds the imaging aperture area 10a
  • the width increases by the first arithmetic progression.
  • the width of the first arc segment 513 of the first scanning line 51 is in the first unequal progression Incremental, that is, in the vertical direction, in the direction from one end of the data line 30 to the other end, the width D3 of the first arc segment 513 of the first scan line 51 is incrementally increased by the first unequal sequence, That is, D3-a1, D3-b1, D3-c1.
  • the width of the first arc segment 513 can compensate for the load value of the missing pixels, thereby minimizing the capacitive resistance of the non-photographic aperture area and the imaging aperture area 10a The difference of the load, so that the display picture of each position is uniform.
  • the width of the first arc segment 513 may also be set to be different from the reduced number of pixel units 10b at the corresponding position, or within a fluctuation range of the reduced number of pixel units 10b at the corresponding position.
  • the width of the first arc segment 513 can be set uniformly, or a plurality of segments can be increased at intervals.
  • the first data line 31 surrounds the portion of the imaging aperture area 10a The width of increases by the second arithmetic progression.
  • the width of the second arc segment 313 of the first data line 31 increases with a second unequal sequence. That is, in the horizontal direction, in the direction from one end of the scan line 50 to the other end, the width D4 of the second arc segment 313 of the first data line 31 is firstly increased by the second unequal sequence, and then by the inverse Decrease to the second unequal arithmetic sequence, that is, D4-a2, D4-b2, D4-c2....
  • the width of the second arc segment 313 can compensate for the load value of the missing pixel unit 10b, thereby reducing the non-photographic aperture area and the imaging aperture area 10a to the greatest extent.
  • the difference in capacitive and resistive loads, so that the display screen at each position is uniform.
  • the width of the second arc segment 313 may also be set differently from the reduced number of pixel units 10b at the corresponding position, or within a fluctuation range of the reduced number of pixel units 10b at the corresponding position.
  • the width of the second arc segment 313 is set uniformly along its extending direction, which improves the convenience of processing.
  • part of the sections may also be widened, so that the widths are inconsistent in the extending direction.
  • FIG. 9 and FIG. 10 Please refer to FIG. 9 and FIG. 10 in combination.
  • the imaging aperture area 10a is bangs-shaped, in the extending direction of the data line 30 from the end far away from the imaging aperture area 10a to the imaging aperture area 10a, the The number of pixel units 10b formed adjacent to the first scanning line 51 and the data line 30 is decreased by the first non-arithmetic sequence;
  • the number of pixel units 10b formed by two adjacent first data lines 31 and scanning lines 50 is the second unequal difference. Decremented sequence.
  • the notch-shaped shape is roughly trapezoidal, with a slightly wider upper end and a slightly narrower lower end.
  • 30 is neither axisymmetrically arranged nor centrosymmetrically arranged.
  • the scanning lines 50 and the data lines 30 around the imaging aperture area 10a are axisymmetrically arranged with the central line of the imaging aperture area 10a as the axis.
  • the number of pixel units 10b formed on the periphery of the imaging aperture area 10a of the substrate 10 decreases with the first non-alertically differential sequence, for example, normally formed
  • the number of pixel units 10b on each horizontal line is N5, then the number of pixel units 10b formed on the horizontal line where the first scanning line 51 of the second scanning line 53 is located is N5-a1, toward the direction of the imaging aperture area 10a
  • the number of formed pixel units 10b is N5-b1, N5-c1... in sequence.
  • the number of bangs-shaped pixel units 10b can optionally be arranged with a value different from that of the first unequal sequence, for example, the second unequal sequence.
  • the notch-shaped imaging aperture area is the same as the drop-shaped imaging aperture area.
  • two adjacent first data lines 31 and the scanning line 50 form a
  • the number of pixel units 10b decreases in the second unequal progression.
  • the number of pixel units 10b on each vertical line normally formed is N6, then the number of pixel units 10b formed on the horizontal line where the first scan line 51 next to the second scan line 53 is located is N6-a2, to When the direction of the imaging aperture region 10a extends, the number of pixel units 10b formed is N6-b2, N6-c2, . . .
  • the width of the first arc segment 513 of the first scanning line 51 is in the first unequal progression Incremental, that is, in the vertical direction, in the direction from one end of the data line 30 to the other end, the width D5 of the first arc segment 513 of the first scanning line 51 is increasing in the first unequal sequence, That is, D5-a1, D5-b1, D5-c1....
  • the width of the first arc segment 513 can compensate for the load value of the missing pixels, thereby minimizing the capacitive resistance of the non-photographic aperture area and the imaging aperture area 10a The difference of the load, so that the display picture of each position is uniform.
  • the width of the first arc segment 513 may also be set to be different from the reduced number of pixel units 10b at the corresponding position, or within a fluctuation range of the reduced number of pixel units 10b at the corresponding position.
  • the first arc segment 513 closest to the imaging aperture area 10a is spaced apart from the edge of the imaging aperture area 10a;
  • the second arc segment 313 closest to the imaging aperture area 10a is spaced apart from the edge of the imaging aperture area 10a.
  • the first arc segment 513 closest to the imaging hole area 10a is spaced from the edge of the imaging hole area 10a, which can prevent metal wiring from being affected when cutting the imaging hole area 10a, and can also The stability of the metal wiring is ensured, and the performance stability of the array substrate 100 is improved.
  • the second arc segment 313 closest to the imaging aperture area 10a and the imaging aperture are arranged at intervals, so as to further improve the manufacturing efficiency of the array substrate 100 and ensure the stability of its structure.
  • the present application also proposes a display panel 300, the display panel 300 includes a color filter substrate 400, an array substrate 100, and a liquid crystal layer 500, the color filter substrate 400 and the array substrate 100 are arranged in pairs, so
  • the array substrate 100 is the array substrate 100 described in any one of the above embodiments. Since the array substrate 100 of the display panel 300 includes all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.
  • the color filter substrate 400 of the display panel 300 is also provided with a structure avoiding the imaging aperture area 10a, so as not to affect the installation and function of the camera.
  • the present application also proposes an electronic device 600, the electronic device 600 includes a housing 601 and a display panel 300 disposed on the housing 601, the display panel 300 is as described above Display panel 300 . Since the display panel 300 of the electronic device 600 includes all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.
  • the electronic device 600 can be a mobile terminal, such as a mobile phone, a notebook computer, a tablet computer, and a wrist-worn device, etc., and the electronic device 600 can also be a household electronic device 600 with a display screen such as a TV, an air conditioner, etc., or any other
  • the electronic device 600 with a camera is not limited here.

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

La présente invention concerne un substrat matriciel (100), un panneau d'affichage (300) et un dispositif électronique (600). Le substrat matriciel (100) comprend une base (10), des lignes de balayage (50) et des lignes de données (30), les lignes de balayage (50) et les lignes de données (30) étant disposées en quinconce verticalement, et la base (10) comportant une zone de trou de caméra (10a). Les lignes de balayage (50) qui entourent partiellement la zone de trou de caméra (10a) sont réglées en tant que premières lignes de balayage (51), et les lignes de balayage (50) qui n'entourent pas la zone de trou de caméra (10a) sont réglées en tant que secondes lignes de balayage (53) ; et les lignes de données (30) qui entourent la zone de trou de caméra (10a) sont définies en tant que premières lignes de données (31), et les lignes de données (30) qui n'entourent pas la zone de trou de caméra (10a) sont définies en tant que secondes lignes de données (33). Dans la direction à partir d'un bord de la zone de trou de caméra (10a) au centre de celle-ci, la largeur de la partie des premières lignes de données (31) et/ou les premières lignes de balayage (51) qui entourent la zone de trou de caméra (10a) augmente progressivement. Dans le substrat matriciel (100) dans la solution technique de la présente invention, au moyen de sections d'élargissement de lignes de balayage (50) et des lignes de données (30) dans une zone de trou de caméra (10a), la longueur de câblage accrue et le nombre réduit de pixels en raison de l'occupation de la zone de trou de caméra (10a) sont compensés, ce qui permet de garantir que la charge résistive et la charge capacitive à chaque position sont les mêmes, et de résoudre le problème d'affichage non uniforme.
PCT/CN2021/142289 2021-09-18 2021-12-29 Substrat matriciel, panneau d'affichage et dispositif électronique WO2023040117A1 (fr)

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