WO2023040117A1

WO2023040117A1 - Array substrate, display panel, and electronic device

Info

Publication number: WO2023040117A1
Application number: PCT/CN2021/142289
Authority: WO
Inventors: 毛晗; 郑浩旋
Original assignee: 惠科股份有限公司
Priority date: 2021-09-18
Filing date: 2021-12-29
Publication date: 2023-03-23
Also published as: CN113568231A; CN113568231B

Abstract

Disclosed in the present application are an array substrate (100), a display panel (300), and an electronic device (600). The array substrate (100) comprises a base (10), scanning lines (50) and data lines (30), wherein the scanning lines (50) and the data lines (30) are arranged in a vertically staggered manner, and the base (10) is provided with a camera hole area (10a). The scanning lines (50) that partially surround the camera hole area (10a) are set as first scanning lines (51), and the scanning lines (50) that do not surround the camera hole area (10a) are set as second scanning lines (53); and the data lines (30) that surround the camera hole area (10a) are set as first data lines (31), and the data lines (30) that do not surround the camera hole area (10a) are set as second data lines (33). In the direction from an edge of the camera hole area (10a) to the center thereof, the width of the portion of the first data lines (31) and/or the first scanning lines (51) that surround the camera hole area (10a) increases progressively. In the array substrate (100) in the technical solution of the present application, by means of widening sections of scanning lines (50) and data lines (30) in a camera hole area (10a), the increased wiring length and the reduced number of pixels due to the occupation of the camera hole area (10a) are compensated, thereby ensuring that the resistive load and capacitive load at each position are the same, and solving the problem of non-uniform display.

Description

Array substrate, display panel and electronic equipment

This application claims priority to a Chinese patent application with application number 202111096466.2 filed on September 18, 2021, the entire contents of which are incorporated herein by reference.

technical field

The present application relates to the technical field of display devices, in particular to an array substrate, a display panel and electronic devices.

Background technique

Today, mobile electronic devices have become an indispensable part of people's daily life, such as smart phones, tablet computers, and the like. Generally speaking, these electronic devices all have a camera function, including front and rear cameras. And with the popularity of ultra-narrow bezel design, some products put the front camera inside the display screen, that is, the design of the hole-punch screen or the water drop screen. For mobile electronic devices using liquid crystal displays (LCDs), in order to To ensure that the camera function is not affected, there must be no metal wiring around the glass camera hole (Camera hole) on the array substrate side of the LCD, that is, the metal wiring needs to avoid the camera hole.

At present, in mobile electronic devices using liquid crystal displays on the market, the metal traces at the camera hole are all of the same line width, and the metal traces around the camera hole are longer than the non-camera hole positions, which leads to uneven loads on capacitors and resistors. , prone to uneven display problems.

technical problem

The main purpose of this application is to propose an array substrate. By designing the metal wiring at the imaging hole and the cutout of the array substrate, the metal wiring at the imaging hole and the rest of the metal wiring have the same load value, thereby Solve the problem of uneven display caused by different loads.

technical solution

In order to achieve the above purpose, the array substrate proposed in this application includes a substrate and a plurality of parallel scanning lines and a plurality of parallel data lines arranged on the substrate, each of the scanning lines and each of the data lines Vertically staggered, the base is provided with a camera hole area;

At least two parts of the data lines are arranged around the area of the imaging aperture, at least two parts of the scanning lines are arranged around the area of the imaging aperture, and the setting part is arranged around the area of the imaging aperture The scanning line is the first scanning line, the scanning line not surrounding the imaging aperture area is the second scanning line, the data line surrounding the imaging aperture area is set as the first data line, and the scanning line not surrounding the imaging aperture area is set as the first scanning line. The scanning line is the second data line;

In the direction from the edge of the imaging aperture area to its center, the width of the portion of the first data line and/or the first scanning line surrounding the imaging aperture area increases gradually.

In an embodiment of the present application, when the shape of the imaging hole area is circular;

In the direction from the second scanning line to the center of the imaging aperture area, the number of pixel units formed by two adjacent data lines and scanning lines is gradually decreased with tolerances such as the first tolerance;

Moreover, in the direction from the second data line to the center of the imaging aperture area, the number of pixel units formed by two adjacent scan lines and data lines decreases gradually with a tolerance such as a second tolerance.

In an embodiment of the present application, in the direction from the edge of the imaging aperture area to its center, the width of the part of the first scanning line surrounding the imaging aperture area increases with tolerances such as the third tolerance, wherein, The third tolerance is equal to the first tolerance.

In an embodiment of the present application, in the direction from the edge of the imaging aperture area to its center, the width of the first data line increases with tolerances such as the fourth tolerance, wherein the fourth tolerance is equal to the second tolerance.

In an embodiment of the present application, when the shape of the imaging hole area is a drop shape or a bang shape;

In the extending direction of the data line from one end away from the imaging aperture area to the imaging aperture area, the number of pixel units formed by two adjacent first scanning lines and data lines is in a first non-arithmetic sequence decrease;

Moreover, in the direction from the second scanning line to the center of the imaging aperture area, the number of pixel units formed by adjacent two first data lines and scanning lines decreases in a second asymmetric sequence.

In an embodiment of the present application, in the direction from the second data line to the imaging aperture area, the width of the part of the first scanning line surrounding the imaging aperture area increases in a first unequal sequence .

In an embodiment of the present application, in the direction from the edge of the imaging aperture area to the center thereof, the width of the part of the first data line surrounding the imaging aperture area increases in a second non-alertometric sequence.

In an embodiment of the present application, each of the first scanning lines includes two first straight line segments and a first arc line segment, and the two ends of the first arc line segment are respectively connected to the two first straight line segments , the first arc segment closest to the camera hole area is spaced from the edge of the camera hole area;

And/or, each of the first data lines includes two second straight line segments and a second arc segment, the two ends of the second arc segment are respectively connected to the two second straight line segments, and the closest The second arc segment of the camera hole area is spaced apart from the edge of the camera hole area.

The present application also proposes a display panel, including a color filter substrate, an array substrate, and a liquid crystal layer, the color filter substrate and the array substrate are arranged in a box, and the array substrate is the array substrate as described above.

The present application also proposes an electronic device, which includes a housing and a display panel disposed on the housing, where the display panel is the above-mentioned display panel.

Beneficial effect

In the technical solution of the present application, the array substrate includes a substrate and data lines and scanning lines arranged on the substrate, and an imaging hole area is also arranged on the substrate, and the data lines and scanning lines are arranged in sequence and staggered. When passing through the imaging hole area, the first A part of a data line surrounds the imaging hole area, and the number of segments that normally form pixels becomes less. The second data line is not affected by the imaging hole area and has a normal length. A part of the first scanning line surrounds the imaging hole. area, the number of segments that normally form pixels is reduced, and the length of the second scanning line is normal. The smaller the number, the corresponding resistance load increases and the capacitive load decreases. In this way, in the direction from the edge to the center of the imaging aperture area, the width of the part of the first data line and/or the first scanning line surrounding the imaging aperture area increases gradually, and also That is, reduce the resistive load of the first data line and/or the first scan line, increase the capacitive load of the first data line and/or the first scan line, thereby compensating for the lost pixel load, effectively reducing the Load difference to improve display quality.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to the structures shown in these drawings without creative effort.

FIG. 1 is a schematic top view of an array substrate in Embodiment 1 of the present application;

FIG. 2 is an arrangement diagram of pixel units in the array substrate shown in FIG. 1;

FIG. 3 is a partially enlarged structural schematic diagram of scanning lines in the array substrate shown in FIG. 1;

FIG. 4 is a partially enlarged structural schematic diagram of data lines in the array substrate shown in FIG. 1;

FIG. 5 is a schematic top view of the array substrate in Embodiment 2 of the present application;

FIG. 6 is an arrangement diagram of pixel units of the array substrate shown in FIG. 5;

FIG. 7 is a partially enlarged structural schematic diagram of the scanning lines corresponding to the array substrate shown in FIG. 5;

FIG. 8 is a partially enlarged structural schematic diagram of data lines corresponding to the array substrate shown in FIG. 5;

FIG. 9 is a schematic top view of the array substrate in Embodiment 3 of the present application;

FIG. 10 is an arrangement diagram of pixel units of the array substrate shown in FIG. 9;

FIG. 11 is a schematic structural diagram of scanning lines corresponding to the array substrate shown in FIG. 9;

FIG. 12 is a cross-sectional view of a display panel in Embodiment 4 of the present application;

FIG. 13 is a partial structural schematic diagram of the first electronic device in Embodiment 5 of the present application;

FIG. 14 is a partial structural schematic diagram of the second electronic device in Embodiment 5 of the present application;

FIG. 15 is a partial structural diagram of the third electronic device in Embodiment 5 of the present application.

Explanation of reference numbers:

100: array substrate; 10: base; 10a: camera hole area; 10b: pixel unit; 30: data line; 31: first data line; 311: second straight line segment; 313: second arc segment; 33: first Two data lines; 50: scanning line; 51: first scanning line; 511: first straight line segment; 513: first arc segment; 53: second scanning line; 300: display panel; 400: color film substrate; 500 : liquid crystal layer; 600: electronic equipment; 601: housing.

The realization, functional features and advantages of the present application will be further described in conjunction with the embodiments and with reference to the accompanying drawings.

Embodiments of the present invention

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

It should be noted that if there are directional indications (such as up, down, left, right, front, back...) in the embodiment of the present application, the directional indications are only used to explain the position in a certain posture (as shown in the attached figure). If the specific posture changes, the directional indication will also change accordingly.

In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only for descriptive purposes, and cannot be interpreted as indications or hints Its relative importance or implicitly indicates the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the realization of those skilled in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist , nor within the scope of protection required by the present application.

Embodiment one

The present application provides an array substrate 100 .

1, the array substrate 100 includes a substrate 10 and a plurality of parallel scanning lines 50 and a plurality of parallel data lines 30 arranged on the substrate 10, each of the scanning lines 50 and each of the data The lines 30 are vertically staggered, and the substrate 10 is provided with an imaging hole area 10a;

At least two parts of the data line 30 are arranged around the imaging aperture area 10a, at least two parts of the scanning line 50 are arranged around the imaging aperture area 10a, and the setting part is arranged around the imaging aperture area 10a. The scanning line 50 of the imaging aperture area 10a is the first scanning line 51, the scanning line 50 not surrounding the imaging aperture area 10a is the second scanning line 53, and the data line 30 surrounding the imaging aperture area 10a is set as The first data line 31, the scanning line 50 not surrounding the imaging aperture area 10a is the second data line 33;

In the direction from the edge of the imaging aperture area 10a to its center, the width of the portion of the first data line 31 and/or the first scanning line 51 surrounding the imaging aperture area 10a increases gradually.

It can be understood that the array substrate 100 is a multi-layer structure, and each layer structure is formed layer by layer through coating, exposure, development and etching processes. Specifically, the array substrate 100 includes a base 10 , which provides a basic carrier. The base 10 is transparent, and its material may be a transparent glass plate or a quartz plate, which is not limited here, as long as it does not affect the passage of the backlight. Since the substrate 10 is non-conductive, the movement and arrangement of the medium used for display, such as liquid crystal, need electrons to drive, so the array substrate 100 also includes conductive data lines 30 (Data Line, DL) and scanning lines 50 (SL, Scanning line), thin film transistor (TFT switch) and pixel electrode (Pixel Electrode, PE), etc. Looking down at the array substrate 100, a plurality of data lines 30 and a plurality of scan lines 50 are intersected to divide the array substrate 100 to form a plurality of pixel regions, and each region corresponds to a pixel electrode and a thin film transistor, because the data lines 30 and the scanning line 50 are opaque, so the part where they are located forms the non-display area of the pixel area, the thin film transistor is also arranged in the non-display area, and the pixel electrode forms the display area of the pixel area.

It can be understood that a camera hole area 10a is also provided on the base 10 to correspond to the camera, so that the camera can realize the function of taking pictures or taking photos through the camera. Here, in order to avoid the imaging aperture area 10a, some sections of the scanning line 50 and the data line 30 arranged in a straight line are arc-shaped, so as to fit the edge of the imaging aperture area 10a. Here, the scanning line 50 partially surrounding the imaging aperture area 10a is set as the first scanning line 51, the data line 30 partially surrounding the imaging aperture area 10a is set as the first data line 31, and the normally arranged scanning lines 50 is the second scanning line 53 , and the normally arranged data lines 30 are the second data lines 33 . At the same time, it is set that each of the first scanning lines 51 includes two first straight line segments 511 and a first arc line segment 513, and the two ends of the first arc line segment 513 are connected to the two first straight line segments 511 respectively. , the first arc segment 513 is arranged around the imaging aperture area 10a, each of the first data lines 31 includes two second straight line segments 311 and a second arc segment 313, and the two ends of the second arc segment 313 The two second straight line segments 311 are respectively connected, and the second arc segment 313 is arranged around the imaging hole area 10a.

It can be seen that the length of the first scanning line 51 is greater than the length of the second scanning line 53, and the closer to the imaging aperture area 10a, the longer the length of the first arc segment 513 is, and the shorter the length of the first straight line segment 511 is; The length of the data line 31 is greater than the length of the second data line 33, and the closer to the imaging aperture area 10a, the longer the length of the second arc segment 313, and the shorter the length of the second straight line segment 311, and the pixel unit of the array substrate 100 10b is formed by interlacing at least two of the second data line 33, the second scanning line 53, the first straight line segment 511, and the second straight line segment 311. Therefore, along the extending direction of the first scanning line 51, the imaging The pixel units 10b formed in the aperture area 10a are less than the pixel units 10b in the non-photographic aperture area, so in order to compensate for the capacitance and resistance load here, the width of the first arc segment 513 and the second arc segment 313 here increase, thereby reducing load differences in different regions. Here, the width of each first arc segment 513 and/or each second arc segment 313 may increase uniformly along its extending direction, or may increase in some sections, which is not limited herein. And according to the shape of the imaging hole is generally circular, so the imaging hole area 10a is generally set in the shape of a round hole, a drop shape or a bangs shape. Of course, in other embodiments, it can also be set in a square or polygonal shape, which is not limited here. .

In the technical solution of the present application, the array substrate 100 includes a base 10 and data lines 30 and scan lines 50 provided on the base 10, and an imaging hole area 10a is also arranged on the base 10, and the data lines 30 and scan lines 50 are arranged in a staggered order , when passing through the imaging aperture area 10a, a part of the first data line 31 surrounds the imaging aperture area 10a, and the number of segments normally forming pixels becomes less, and the second data line 33 is not affected by the imaging aperture area 10a, as Normal length, part of the first scanning line 51 surrounds the imaging aperture area 10a, and the number of segments that normally form pixels becomes less, the length of the second scanning line 53 is normal, the closer to the first scanning line of the imaging aperture area 10a 51 and the length of the first data line 31 around the longer, then the number of correspondingly formed pixel units 10b is less, the corresponding resistance load increases, and the capacitive load decreases. In this way, in the direction from the edge to the center of the imaging aperture area 10a, The width of the part of the first data line 31 and/or the first scanning line 51 surrounding the imaging aperture area 10a is gradually increased, that is, the resistance load of the first data line 31 and/or the first scanning line 51 is reduced, and the first data line is increased. 31 and/or the capacitive load of the first scan line 51, so as to compensate the lost pixel load, effectively reduce the load difference in different regions of the array substrate 100, and improve the display quality.

In the processing procedure, a metal layer is first deposited on the substrate 10, and the metal layer is patterned through a photomask to form the data line 30 on the substrate 10, so that the thin film transistor can be provided with an on-off voltage, simultaneously with the data line 30 A grid is also formed. Here, the process of patterning through a photomask is to deposit a photoresist on the metal layer, expose and develop after being covered by a photomask, and then perform etching. The material of the metal layer is an opaque conductive metal material, such as a combination of one or more of molybdenum, titanium, chromium and aluminum, which is not limited herein.

Next, a gate insulating layer is formed on the gate and data lines 30, and an active layer, a source electrode and a drain electrode which are in contact with both ends of the active layer and arranged at intervals are sequentially formed on the gate insulating layer, thereby completing the thin film transistor. processing; moreover, a passivation layer is deposited on the source, drain, and gate insulating layers, and the passivation layer is patterned through a photomask process to form a via hole through the passivation layer, which can be exposed part of the drain; finally, a transparent conductive layer is formed on the passivation layer, and the transparent conductive layer is patterned through a photomask process to form a pixel electrode of a specific shape, and the pixel electrode is in electrical contact with the drain through a via hole, thereby corresponding to the pixel unit 10b The display area of the display area is provided with the voltage for liquid crystal movement, and the fabrication of the array substrate 100 is completed.

Referring to FIG. 2, in Embodiment 1 of the present application, when the shape of the imaging aperture area 10a is circular;

In the direction from the second scanning line 53 to the center of the imaging aperture area 10a, the number of pixel units 10b formed by two adjacent data lines 30 and scanning lines 50 decreases gradually with a first tolerance of d1;

In addition, in the direction from the second data line 33 to the center of the imaging aperture area 10a, the number of pixel units 10b formed by two adjacent scanning lines 50 and data lines 30 has a second tolerance of d2 and other tolerances decrease.

Here, it is assumed that the extending direction of the scanning line 50 is the horizontal direction, and the extending direction of the second data line 33 is the vertical direction. Symmetrical and axisymmetric figures, then the first arc segment 513 of the first scan line 51 is also arranged axisymmetrically with the diameter in the horizontal direction of the imaging aperture area 10a, and the second arc segment 313 of the first data line 31 is The vertical diameter of the imaging aperture area 10a is arranged axially symmetrically, and the first straight line segment 511 and the second straight line segment 311 are also arranged axially symmetrically with the diameter of the imaging aperture area 10a as the axis.

Therefore, in the direction from the second scanning line 53 to the center of the imaging aperture area 10a, at least two of the first straight line segment 511, the second straight line segment 311, the second scanning line 53, and the second data line 33 are composed of The tolerances such as the number of pixel units 10b decrease, and the first tolerance is set to d1, for example, the number of pixel units 10b normally formed on a second scan line 53 is N1, then the first scan line next to the second scan line 53 The number of pixel units 10b formed on 51 is N1-d1, and toward the center of the imaging aperture area 10a, the number of pixel units 10b formed by the first scanning line 51 is N1-2d1, N1-3d1..., located at The row where the first scanning line 51 is located on the diameter of the imaging aperture area 10 a forms the least number of pixel units 10 b. Similarly, in the direction from the second data line 33 to the center of the imaging aperture area 10a, the number of pixel units 10b formed by two adjacent scanning lines 50 and data lines 30 is set to a second tolerance of d2 and other tolerances Decrease, for example, the second data line 33 forms N2 pixel units 10b, then the number of pixel units 10b formed by the first data line 31 is N2-d2, N2-2d2, N2-3d2..., so that the data line 30 And the processing of the scanning line 50 makes the distribution of pixels at the edge of the imaging aperture area 10a uniform, without affecting the display effect.

Here, the values of N1 and N2 can be the same, for example, the formed pixel unit 10b is a square; of course, the two can also be different, for example, the formed pixel unit 10b is rectangular, similarly, the first tolerance d1 and the second The tolerance d2 can be the same or different, and can be set according to the actual situation.

Please refer to FIG. 3 , in an embodiment of the present application, in the direction from the edge of the imaging aperture area 10a to its center, the width of the part of the first scanning line 51 surrounding the imaging aperture area 10a is equal to the second The three tolerances are increments of d3 and other tolerances, wherein said d3 is equal to d1.

In order to make the loads of each area approximately the same, in the present embodiment, in the direction from the edge of the imaging aperture area 10a to its center, the width of the first arc segment 513 of the first scanning line 51 is set as D1, which is represented by the first arc segment 513. The three tolerances are that d3 increases with equal tolerance, that is, in the vertical direction, in the direction from one end of the data line 30 to the other end, the width of the first arc segment 513 of the first scan line 51 is increased with equal tolerance first. , and then wait for the tolerance to decrease. Here, setting d3 and d1 to be the same can compensate the load value of missing pixels, thereby minimizing the difference in capacitive and resistive loads between the non-photographic aperture area and the imaging aperture area 10a, so that the display screen at each position is uniform. Certainly, in other embodiments, it is also possible to set d3 to be different from d1, or to be within a fluctuation range of d1.

Here, the width of the first arc segment 513 can be set uniformly, or the width of a certain segment can be increased.

Please refer to FIG. 4 , in an embodiment of the present application, in the direction from the edge of the imaging aperture area 10a to its center, the width of the first data line 31 increases with a fourth tolerance of d4 and other tolerances, wherein , d4 is equal to d2.

In this embodiment, similarly, in the horizontal direction, and in the direction from the edge of the imaging aperture area 10a to its center, the width of the second arc segment 313 of the first data line 31 is set to be D2, and the fourth Incremental tolerances such as tolerance d4. That is, in the horizontal direction, from one end to the other end of the scan line 50 , the width of the second arc segment 313 of the first data line 31 first waits for the tolerance to increase, and then waits for the tolerance to decrease. Here, setting d4 and d2 to be the same can compensate the load value of missing pixels, thereby minimizing the difference in capacitive and resistive loads between the non-photographic aperture area and the imaging aperture area 10a, so that the display screen at each position is uniform. Certainly, in other embodiments, it is also possible to set d4 to be different from d2, or to be within a fluctuation range of d2.

Here, the width of the second arc segment 313 is set uniformly along its extending direction, which improves the convenience of processing. Of course, in other embodiments, part of the sections may also be widened, so that the widths are inconsistent in the extending direction.

Embodiment two

Please refer to FIG. 5 and FIG. 6 in conjunction, when the shape of the imaging hole area 10a is a drop shape;

In the extending direction of the data line 30 from one end away from the imaging aperture area 10a to the imaging aperture area 10a, the number of pixel units 10b formed by two adjacent first scanning lines 51 and data lines 30 is equal to or greater than Decrease of the first unequal progression;

Moreover, in the direction from the second scanning line 53 to the center of the imaging aperture area 10a, the number of pixel units 10b formed by two adjacent first data lines 31 and scanning lines 50 is the second unequal difference. Decremented sequence.

In this embodiment, the imaging aperture area 10a is in the shape of a water droplet, which is an inverted shape of a normally falling water droplet, that is, in the vertical direction, the upper dimension of the imaging aperture area 10a is larger and the lower dimension is smaller. Therefore, in the vertical direction, the scanning lines 50 and the data lines 30 at the peripheral edge of the imaging aperture area 10 a are not arranged symmetrically about the axis, nor are they arranged symmetrically about the center. In the horizontal direction, the scan lines 50 and the data lines 30 around the imaging hole area 10a can be arranged axisymmetrically with the center line of the imaging hole area 10a as the axis. When the data line 30 extends from the end far away from the imaging aperture area 10a to the imaging aperture area 10a, the number of pixel units 10b formed on the periphery of the imaging aperture area 10a of the substrate 10 decreases with the first non-alertically differential sequence, for example, normally formed The number of pixel units 10b on each horizontal line is N3, then the number of pixel units 10b formed on the horizontal line where the first scanning line 51 of the second scanning line 53 is located is N3-a1, toward the direction of the imaging aperture area 10a When extending, the number of pixel units 10b to be formed is N3-b1, N3-c1, . . . in sequence.

At this time, in the direction from the second scanning line 53 to the center of the imaging aperture area 10a, the number of pixel units 10b formed by adjacent two first data lines 31 and the scanning line 50 decreases in a second unequal sequence, for example , the number of pixel units 10b on each vertical line that is normally formed is N4, then the number of pixel units 10b formed on the horizontal line where the first scan line 51 adjacent to the second scan line 53 is located is N4-a2. When the direction of the hole region 10a extends, the number of pixel units 10b formed is N4-b2, N4-c2, . . . That is to say, in the horizontal direction, the number of pixel units 10b formed by the first data line 31 decreases firstly, and then increases, and the first data line 31 is arranged symmetrically with the central axis of the imaging aperture area 10a, Therefore, the processing of the array substrate 100 is more convenient and the processing efficiency is improved.

Please refer to FIG. 7, in an embodiment of the present application, in the direction from the second data line 33 to the imaging aperture area 10a, the first scanning line 51 surrounds the imaging aperture area 10a The width increases by the first arithmetic progression.

In this embodiment, in order to make the loads of each area approximately the same, in the direction from the second data line 33 to the imaging aperture area 10a, the width of the first arc segment 513 of the first scanning line 51 is in the first unequal progression Incremental, that is, in the vertical direction, in the direction from one end of the data line 30 to the other end, the width D3 of the first arc segment 513 of the first scan line 51 is incrementally increased by the first unequal sequence, That is, D3-a1, D3-b1, D3-c1.... Here, setting the width of the first arc segment 513 to be consistent with the reduced number of pixel units 10b can compensate for the load value of the missing pixels, thereby minimizing the capacitive resistance of the non-photographic aperture area and the imaging aperture area 10a The difference of the load, so that the display picture of each position is uniform. Of course, in other embodiments, the width of the first arc segment 513 may also be set to be different from the reduced number of pixel units 10b at the corresponding position, or within a fluctuation range of the reduced number of pixel units 10b at the corresponding position.

Here, the width of the first arc segment 513 can be set uniformly, or a plurality of segments can be increased at intervals.

Please refer to FIG. 8 , in an embodiment of the present application, in the direction from the edge of the imaging aperture area 10a in the horizontal direction to its center, the first data line 31 surrounds the portion of the imaging aperture area 10a The width of increases by the second arithmetic progression.

In this embodiment, in the horizontal direction, and in the direction from the edge of the imaging aperture area 10 a to its center, the width of the second arc segment 313 of the first data line 31 increases with a second unequal sequence. That is, in the horizontal direction, in the direction from one end of the scan line 50 to the other end, the width D4 of the second arc segment 313 of the first data line 31 is firstly increased by the second unequal sequence, and then by the inverse Decrease to the second unequal arithmetic sequence, that is, D4-a2, D4-b2, D4-c2.... Here, setting the width of the second arc segment 313 to be the same as the reduced number of pixel units 10b at the corresponding position can compensate for the load value of the missing pixel unit 10b, thereby reducing the non-photographic aperture area and the imaging aperture area 10a to the greatest extent. The difference in capacitive and resistive loads, so that the display screen at each position is uniform. Of course, in other embodiments, the width of the second arc segment 313 may also be set differently from the reduced number of pixel units 10b at the corresponding position, or within a fluctuation range of the reduced number of pixel units 10b at the corresponding position.

Embodiment Three

Please refer to FIG. 9 and FIG. 10 in combination. When the imaging aperture area 10a is bangs-shaped, in the extending direction of the data line 30 from the end far away from the imaging aperture area 10a to the imaging aperture area 10a, the The number of pixel units 10b formed adjacent to the first scanning line 51 and the data line 30 is decreased by the first non-arithmetic sequence;

In this embodiment, when the imaging hole area 10a is notch-shaped, the notch-shaped shape is roughly trapezoidal, with a slightly wider upper end and a slightly narrower lower end. 30 is neither axisymmetrically arranged nor centrosymmetrically arranged. In the horizontal direction, the scanning lines 50 and the data lines 30 around the imaging aperture area 10a are axisymmetrically arranged with the central line of the imaging aperture area 10a as the axis. When the data line 30 extends from the end far away from the imaging aperture area 10a to the imaging aperture area 10a, the number of pixel units 10b formed on the periphery of the imaging aperture area 10a of the substrate 10 decreases with the first non-alertically differential sequence, for example, normally formed The number of pixel units 10b on each horizontal line is N5, then the number of pixel units 10b formed on the horizontal line where the first scanning line 51 of the second scanning line 53 is located is N5-a1, toward the direction of the imaging aperture area 10a When extending, the number of formed pixel units 10b is N5-b1, N5-c1... in sequence. Of course, here, the number of bangs-shaped pixel units 10b can optionally be arranged with a value different from that of the first unequal sequence, for example, the second unequal sequence.

Similarly, the notch-shaped imaging aperture area is the same as the drop-shaped imaging aperture area. In the direction from the second scanning line 53 to the center of the imaging aperture area 10a, two adjacent first data lines 31 and the scanning line 50 form a The number of pixel units 10b decreases in the second unequal progression. For example, the number of pixel units 10b on each vertical line normally formed is N6, then the number of pixel units 10b formed on the horizontal line where the first scan line 51 next to the second scan line 53 is located is N6-a2, to When the direction of the imaging aperture region 10a extends, the number of pixel units 10b formed is N6-b2, N6-c2, . . .

Please refer to FIG. 11 , in order to make the loads of each area approximately the same, in the direction from the second data line 33 to the imaging aperture area 10a, the width of the first arc segment 513 of the first scanning line 51 is in the first unequal progression Incremental, that is, in the vertical direction, in the direction from one end of the data line 30 to the other end, the width D5 of the first arc segment 513 of the first scanning line 51 is increasing in the first unequal sequence, That is, D5-a1, D5-b1, D5-c1.... Here, setting the width of the first arc segment 513 to be consistent with the reduced number of pixel units 10b can compensate for the load value of the missing pixels, thereby minimizing the capacitive resistance of the non-photographic aperture area and the imaging aperture area 10a The difference of the load, so that the display picture of each position is uniform. Of course, in other embodiments, the width of the first arc segment 513 may also be set to be different from the reduced number of pixel units 10b at the corresponding position, or within a fluctuation range of the reduced number of pixel units 10b at the corresponding position.

Referring to FIG. 3 , in an embodiment of the present application, the first arc segment 513 closest to the imaging aperture area 10a is spaced apart from the edge of the imaging aperture area 10a;

And/or, the second arc segment 313 closest to the imaging aperture area 10a is spaced apart from the edge of the imaging aperture area 10a.

In this embodiment, in order to facilitate processing, the first arc segment 513 closest to the imaging hole area 10a is spaced from the edge of the imaging hole area 10a, which can prevent metal wiring from being affected when cutting the imaging hole area 10a, and can also The stability of the metal wiring is ensured, and the performance stability of the array substrate 100 is improved.

In the same way, on the basis of whether the first arc segment 513 closest to the imaging aperture area 10a is spaced from the edge of the imaging aperture area 10a, then the second arc segment 313 closest to the imaging aperture area 10a and the imaging aperture The edges of the regions 10a are arranged at intervals, so as to further improve the manufacturing efficiency of the array substrate 100 and ensure the stability of its structure.

Embodiment four

Please refer to FIG. 12 , the present application also proposes a display panel 300, the display panel 300 includes a color filter substrate 400, an array substrate 100, and a liquid crystal layer 500, the color filter substrate 400 and the array substrate 100 are arranged in pairs, so The array substrate 100 is the array substrate 100 described in any one of the above embodiments. Since the array substrate 100 of the display panel 300 includes all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

Wherein, the color filter substrate 400 of the display panel 300 is also provided with a structure avoiding the imaging aperture area 10a, so as not to affect the installation and function of the camera.

Embodiment five

Please refer to FIG. 13 to FIG. 15 , the present application also proposes an electronic device 600, the electronic device 600 includes a housing 601 and a display panel 300 disposed on the housing 601, the display panel 300 is as described above Display panel 300 . Since the display panel 300 of the electronic device 600 includes all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

Wherein, the electronic device 600 can be a mobile terminal, such as a mobile phone, a notebook computer, a tablet computer, and a wrist-worn device, etc., and the electronic device 600 can also be a household electronic device 600 with a display screen such as a TV, an air conditioner, etc., or any other The electronic device 600 with a camera is not limited here.

The above is only the preferred embodiment of the application, and does not limit the patent scope of the application. Under the conception of the application, the equivalent structural transformation made by using the specification and drawings of the application, or directly/indirectly used in Other relevant technical fields are included in the scope of patent protection of this application.

Claims

An array substrate (100), the array substrate (100) comprising a substrate (10), a plurality of parallel scan lines (50) and a plurality of parallel data lines ( 30), each of the scanning lines (50) and each of the data lines (30) are vertically interlaced, and the substrate (10) is provided with an imaging hole area (10a), wherein:

At least two parts of the data lines (30) are arranged around the periphery of the imaging aperture area (10a), and at least two parts of the scanning lines (50) are arranged around the periphery of the imaging aperture area (10a) Setting, setting the scanning line (50) partially surrounding the imaging aperture area (10a) as the first scanning line (51), and the scanning line (50) not surrounding the imaging aperture area (10a) as the second scanning line line (53), set the data line (30) surrounding the imaging aperture area (10a) as the first data line (31), and the scanning line (50) not surrounding the imaging aperture area (10a) as the second Two data lines (33);

In the direction from the edge of the imaging aperture area (10a) to its center, the first data line (31) and/or the first scanning line (51) surrounds a part of the imaging aperture area (10a) width increments.
The array substrate (100) according to claim 1, wherein when the shape of the imaging hole area (10a) is circular;

In the direction from the second scanning line (53) to the center of the imaging aperture area (10a), the number of pixel units (10b) formed by two adjacent data lines (30) and scanning lines (50) Decrease by first tolerance and other tolerances;

Moreover, in the direction from the second data line (33) to the center of the imaging aperture area (10a), two adjacent pixel units (10b) formed by the scanning line (50) and the data line (30) The quantity of is decremented by the second tolerance and other tolerances.
The array substrate (100) according to claim 2, wherein, in the direction from the edge of the imaging aperture area (10a) to its center, the first scanning line (51) surrounds the imaging aperture area (10a) ) in increments of a third tolerance equal to the first tolerance.
The array substrate (100) according to claim 2, wherein, in the direction from the edge of the imaging aperture area (10a) to its center, the width of the first data line (31) is equal to the fourth tolerance Incrementally, wherein the fourth tolerance is equal to the second tolerance.
The array substrate (100) according to claim 1, wherein when the shape of the imaging hole area (10a) is a drop shape or a notch shape;

In the extension direction of the data line (30) from the end far away from the imaging aperture area (10a) to the imaging aperture area (10a), two adjacent first scanning lines (51) and data lines ( 30) The number of pixel units (10b) to be formed is decremented by the first non-arithmetic sequence;

Moreover, in the direction from the second scanning line (53) to the center of the imaging aperture area (10a), the pixel units ( 10b) is decremented by the second unequal progression.
The array substrate (100) according to claim 5, wherein, in the direction from the second data line (33) to the imaging hole area (10a), the first scanning line (51) surrounds the The width of the portion of the camera aperture area (10a) increases in increments of the first non-arithmetic sequence.
The array substrate (100) according to claim 5, wherein, in the direction from the horizontal edge of the imaging aperture area (10a) to its center, the first data line (31) surrounds the imaging aperture The width of the portion of the region (10a) increases in the second arithmetic progression.
The array substrate (100) according to claim 1, wherein each of the first scanning lines (51) includes two first straight line segments (511) and a first arc segment (513), the first Both ends of the arc segment (513) are respectively connected to the two first straight line segments (511), and the first arc segment (513) closest to the camera hole area (10a) is connected to the camera hole area (10a) The edge interval setting of ;

And/or, each of the first data lines (31) includes two second straight line segments (311) and a second arc segment (313), and the two ends of the second arc segment (313) are respectively connected to The two second straight line segments (311), the second arc segment (313) closest to the imaging aperture area (10a) and the edge of the imaging aperture area (10a) are arranged at intervals.
The array substrate (100) according to claim 1, wherein the array substrate (100), a plurality of the data lines (30) and a plurality of the scanning lines (50) are intersected so that the array substrate (100) Segment to form a plurality of pixel regions.
The array substrate (100) according to claim 8, wherein the length of the first scanning line (51) is greater than the length of the second scanning line (53), and the closer to the imaging aperture area (10a) the The longer the length of the first arc segment (513), the shorter the length of the first straight line segment (511).
The array substrate (100) according to claim 8, wherein the length of the first data line (31) is greater than the length of the second data line (33), and the closer to the imaging hole area (10a) the The longer the length of the second arc segment (313), the shorter the length of the second straight line segment (311).
The array substrate (100) according to claim 8, wherein the pixel unit (10b) of the array substrate (100) is composed of the second data line (33), the second scan line (53 ), at least two of the first straight line segment (511) and the second straight line segment (311) are formed alternately.
A display panel (300), wherein the display panel (300) comprises a color filter substrate (400), an array substrate (100) and a liquid crystal layer (500), the color filter substrate (400) and the array substrate (100) arranged in a box, the array substrate (100) is the array substrate (100) according to claim 1.
The display panel according to claim 13, wherein the color filter substrate (400) of the display panel (300) is provided with a structure avoiding the imaging aperture area (10a).
An electronic device (600), wherein the electronic device (600) comprises a casing (601) and a display panel (300) arranged on the casing (601), the display panel (300) is as claimed in The display panel (300) of claim 13.