JP2003167271A - Liquid crystal display element - Google Patents
Liquid crystal display elementInfo
- Publication number
- JP2003167271A JP2003167271A JP2001366880A JP2001366880A JP2003167271A JP 2003167271 A JP2003167271 A JP 2003167271A JP 2001366880 A JP2001366880 A JP 2001366880A JP 2001366880 A JP2001366880 A JP 2001366880A JP 2003167271 A JP2003167271 A JP 2003167271A
- Authority
- JP
- Japan
- Prior art keywords
- electrode line
- arc
- hole
- gate electrode
- shaped wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、パネル面内に貫通
孔を有し機械式アナログ表示手段などとを組み合わせて
用いられるアクティブマトリクス方式の液晶表示素子に
関し、さらに詳しく言えば、貫通孔の周りの電極線の引
き回し技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device having a through hole in a panel surface and used in combination with a mechanical analog display means, and more specifically, a periphery of the through hole. The present invention relates to a technique for arranging electrode wires of
【０００２】[0002]
【従来の技術】ＴＦＴ−ＬＣＤ（薄膜トランジスタによ
る液晶表示素子）は、基本的にドットマトリクス表示型
である。まず、そのアレイ基板側に形成されている１画
素を図４に模式的に示し、これについて簡単に説明す
る。2. Description of the Related Art A TFT-LCD (liquid crystal display element using a thin film transistor) is basically a dot matrix display type. First, one pixel formed on the array substrate side is schematically shown in FIG. 4, and this will be briefly described.
【０００３】アレイ基板上にゲート電極線１とソース電
極線２とが互いに直交するように形成され、その交差部
にＴＦＴ３が配置されている。ゲート電極線１はＴＦＴ
３のゲート３Ｇに接続され、また、ソース電極線２はＴ
ＦＴ３のソース３Ｓに接続されている。ＴＦＴ３のドレ
イン３ＤにはＩＴＯよりなる画素電極４が接続されてい
る。A gate electrode line 1 and a source electrode line 2 are formed on an array substrate so as to be orthogonal to each other, and a TFT 3 is arranged at the intersection thereof. The gate electrode line 1 is a TFT
3 is connected to the gate 3G, and the source electrode line 2 is T
It is connected to the source 3S of FT3. A pixel electrode 4 made of ITO is connected to the drain 3D of the TFT 3.
【０００４】画素電極４の裏面側に蓄積容量５が配置さ
れ、この蓄積容量５にはキャパシタ用電極線６が接続さ
れている。蓄積容量５およびそのキャパシタ用電極線６
はゲート電極線１とともに、同じ材料によってアレイ基
板面上に形成され、キャパシタ用電極線６はゲート電極
線１と平行に配線されている。A storage capacitor 5 is arranged on the back surface side of the pixel electrode 4, and a capacitor electrode line 6 is connected to the storage capacitor 5. Storage capacitor 5 and electrode line 6 for the capacitor
Is formed on the array substrate surface together with the gate electrode line 1 by the same material, and the capacitor electrode line 6 is wired in parallel with the gate electrode line 1.
【０００５】なお、蓄積容量をゲート電極線に接続し、
ゲート電極線にキャパシタ用電極線の役割を兼ねさせる
場合もあるが、以下、キャパシタ用電極線が独立してい
る場合を中心に説明を進める。また、ソース電極線２と
画素電極４は、これらの電極線１，６および蓄積容量５
の上に絶縁膜を介して形成されている。In addition, the storage capacitor is connected to the gate electrode line,
The gate electrode line may also serve as the capacitor electrode line in some cases, but the following description will be focused on the case where the capacitor electrode line is independent. The source electrode line 2 and the pixel electrode 4 are connected to the electrode lines 1 and 6 and the storage capacitor 5 respectively.
Is formed on the above with an insulating film interposed.
【０００６】ＴＦＴ−ＬＣＤにおける駆動方法は線順次
走査による。すなわち、各ゲート電極線１に対して所定
のデューティ比で駆動電圧が交代的に印加され、各ソー
ス電極線２には信号電圧が印加される。蓄積容量５は、
ゲート電極線１に駆動電圧が印加されその後オフとされ
ても、信号電圧を保持するためのものである。The driving method in the TFT-LCD is line-sequential scanning. That is, the drive voltage is alternately applied to each gate electrode line 1 at a predetermined duty ratio, and the signal voltage is applied to each source electrode line 2. The storage capacity 5 is
This is for holding the signal voltage even when the drive voltage is applied to the gate electrode line 1 and then turned off.
【０００７】[0007]
【発明が解決しようとする課題】ところで、ＴＦＴ−Ｌ
ＣＤにおいて、そのパネル面内に貫通孔を設け、その貫
通孔内に例えば自動車のスピードメータやアナログ時計
などのようなアナログ指示計器の指針駆動軸を挿通し
て、ＴＦＴ−ＬＣＤをアナログ指針の目盛板として用い
る場合、次のような課題が生ずる。By the way, the TFT-L
In the CD, a through hole is provided in the panel surface, and the pointer drive shaft of an analog indicating instrument such as an automobile speedometer or an analog clock is inserted into the through hole, and the TFT-LCD is calibrated with the analog pointer. When used as a plate, the following problems occur.
【０００８】すなわち、パネル面の表示部内に貫通孔を
設けると、その部分には画素電極４を設けることができ
ないばかりでなく、ゲート電極線１，ソース電極線２お
よびキャパシタ用電極線６を必然的に貫通孔から避ける
ように配線しなければならない。That is, when the through hole is provided in the display portion of the panel surface, not only the pixel electrode 4 cannot be provided at that portion, but also the gate electrode line 1, the source electrode line 2 and the capacitor electrode line 6 are inevitable. The wiring must be made to avoid the through holes.
【０００９】その場合、貫通孔を避けて迂回した配線部
分と、そうでない他の配線部分との電気容量をできるだ
け同じ条件として、迂回した配線部分の先の画素で部分
的な表示むらが生じないようにすることが求められる。
これが、本発明が解決しようとする課題である。In this case, if the electric capacitances of the wiring portion that bypasses the through hole and the other wiring portions that do not pass through are set to the same condition as much as possible, partial display unevenness does not occur in the pixel ahead of the bypassed wiring portion. Is required.
This is the problem to be solved by the present invention.
【００１０】[0010]
【課題を解決するための手段】すなわち、本発明は、マ
トリクス状に配列された各画素電極ごとに能動素子と蓄
積容量とが設けられ、その各能動素子に対してゲート電
極線とソース電極線とが配線接続されているアレイ基板
と、共通電極を有する対向基板とを周辺シール材を介し
て圧着し、その各基板間に液晶を封入してなるアクティ
ブマトリクス方式の液晶表示素子において、表示部内の
所定部位に、上記両基板を同軸的に貫通し内面が環状シ
ール材により封止された貫通孔を設けるにあたって、上
記貫通孔の周辺に配線される上記ゲート電極線および上
記ソース電極線の各々に、上記貫通孔の軸線を中心とす
る円弧状配線部をそれぞれ形成するとともに、上記ソー
ス電極線の円弧状配線部を、上記ゲート電極線の円弧状
配線部の間に配置することを特徴としている。That is, according to the present invention, an active element and a storage capacitor are provided for each pixel electrode arranged in a matrix, and a gate electrode line and a source electrode line are provided for each active element. In an active matrix type liquid crystal display element in which an array substrate to which wirings and are connected by wiring and a counter substrate having a common electrode are pressure-bonded via a peripheral sealing material and liquid crystal is sealed between the substrates, In providing a through hole in which the both substrates are coaxially penetrated and the inner surface of which is sealed with an annular sealing material, in each of the predetermined portion of the gate electrode line and the source electrode line which are wired around the through hole, And forming arc-shaped wiring portions centering on the axis of the through-hole, and arranging the arc-shaped wiring portions of the source electrode lines between the arc-shaped wiring portions of the gate electrode lines. It is characterized in Rukoto.
【００１１】また、上記ゲート電極線に平行に配線され
た独立したキャパシタ用電極線がある場合には、上記ソ
ース電極線の円弧状配線部を上記ゲート電極線と上記キ
ャパシタ用電極線の各円弧状配線部の間に配置すること
が好ましい。When there is an independent capacitor electrode wire which is wired in parallel with the gate electrode wire, the arc-shaped wiring portion of the source electrode wire is formed in each circle of the gate electrode wire and the capacitor electrode wire. It is preferable to arrange between the arc-shaped wiring portions.
【００１２】これによれば、ソース電極線の円弧状配線
部が、ゲート電極線とキャパシタ用電極線の各円弧状配
線部とオーバーラップする部分が最小となるため、貫通
孔を避けて迂回した配線部分と、そうでない他の配線部
分との電気容量の差を最小にすることができる。According to this, since the arcuate wiring portion of the source electrode line overlaps with each arcuate wiring portion of the gate electrode line and the capacitor electrode line at the minimum, the bypass is avoided while avoiding the through hole. It is possible to minimize the difference in electric capacitance between the wiring portion and other wiring portions that are not.
【００１３】なお、ゲート電極線とキャパシタ用電極線
の各円弧状配線部の間の幅が、ソース電極線の円弧状配
線部の幅よりも狭く、ソース電極線の円弧状配線部に対
してオーバーラップ部分が生じてしまうような場合に
は、ソース電極線の円弧状配線部の中心線と、ゲート電
極線とキャパシタ用電極線の各円弧状配線部間の中心線
とを一致させて配線することが好ましい。The width between the arc-shaped wiring portions of the gate electrode line and the capacitor electrode line is narrower than the width of the arc-shaped wiring portion of the source electrode line, If there is an overlap, the center line of the arc-shaped wiring part of the source electrode line and the center line of each arc-shaped wiring part of the gate electrode line and the capacitor electrode line should be aligned. Preferably.
【００１４】また、別の方法として、ゲート電極線およ
びキャパシタ用電極線の各円弧状配線部を貫通孔の内周
側もしくは外周側のいずれか一方の側に配置し、いずれ
か他方の側にソース電極線の円弧状配線部を配置するこ
とによっても、上記課題を解決することができる。As another method, the arcuate wiring portions of the gate electrode line and the capacitor electrode line are arranged on either the inner peripheral side or the outer peripheral side of the through hole and the other side is arranged on the other side. The above problem can also be solved by disposing the arc-shaped wiring portion of the source electrode line.
【００１５】[0015]
【発明の実施の形態】次に、本発明の実施形態について
説明する。図１にこの実施形態に係る液晶表示素子が備
える貫通孔部分の概略的な断面図を示し、図２の平面図
にその貫通孔周辺の電極線の配線状態を示す。BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described. FIG. 1 shows a schematic cross-sectional view of a through hole portion provided in the liquid crystal display element according to this embodiment, and a plan view of FIG. 2 shows a wiring state of electrode lines around the through hole.
【００１６】この液晶表示素子は、アレイ基板１１と対
向基板１２とを定法にしたがって図示しない周辺シール
材を介して圧着してなり、そのパネル面（表示部）の所
定部位には、アレイ基板１１と対向基板１２とを同軸的
に貫通する貫通孔１３が設けられている。貫通孔１３の
内周は、液晶の漏洩を防止するためシール材１４にて封
止されている。貫通孔１３には、例えばスピードメータ
の指針駆動軸１５が挿通される。In this liquid crystal display element, the array substrate 11 and the counter substrate 12 are pressure-bonded to each other through a peripheral sealing material (not shown) according to a standard method, and the array substrate 11 is provided at a predetermined portion of the panel surface (display portion). A through hole 13 that coaxially penetrates the counter substrate 12 and the counter substrate 12 is provided. The inner periphery of the through hole 13 is sealed with a sealing material 14 to prevent liquid crystal from leaking. A pointer drive shaft 15 of a speedometer, for example, is inserted into the through hole 13.
【００１７】アレイ基板１１側には、先の図４で説明し
たゲート電極線１，ソース電極線２およびキャパシタ用
電極線６が縦横に無数に配線されているが、作図の都合
上、貫通孔１３の周辺に配線される各電極線の内、ゲー
ト電極線１とキャパシタ用電極線６については各２本、
ソース電極線２については４本のみを図２に示し、これ
について説明する。On the array substrate 11 side, the gate electrode lines 1, the source electrode lines 2 and the capacitor electrode lines 6 described in FIG. 4 are innumerably laid vertically and horizontally, but for the convenience of drawing, through holes are provided. Of the electrode lines wired around 13, two for the gate electrode line 1 and two for the capacitor electrode line 6,
Only four source electrode lines 2 are shown in FIG. 2 and will be described.
【００１８】ゲート電極線１とキャパシタ用電極線６は
１本置きの交互配置とされ、この例においてはともに横
軸（Ｘ軸）方向に沿って配線されている。これに対し
て、ソース電極線２は縦軸（Ｙ軸）方向に沿って配線さ
れている。The gate electrode lines 1 and the capacitor electrode lines 6 are arranged alternately every other line, and in this example, both are arranged along the horizontal axis (X axis) direction. On the other hand, the source electrode line 2 is wired along the vertical axis (Y axis) direction.
【００１９】貫通孔１３の周辺において、ゲート電極線
１，ソース電極線２およびキャパシタ用電極線６の各々
に、貫通孔１３の軸線を中心とする円弧状配線部が形成
されている。ゲート電極線１の円弧状配線部を１ａ，ソ
ース電極線２の円弧状配線部を２ａ，キャパシタ用電極
線６の円弧状配線部を６ａとする。Around the through hole 13, an arcuate wiring portion centered on the axis of the through hole 13 is formed in each of the gate electrode line 1, the source electrode line 2 and the capacitor electrode line 6. The arc-shaped wiring part of the gate electrode line 1 is 1a, the arc-shaped wiring part of the source electrode line 2 is 2a, and the arc-shaped wiring part of the capacitor electrode line 6 is 6a.
【００２０】この円弧状配線部の電気容量を、これ以外
の直線状配線部の電気容量と同程度とするには、ゲート
電極線１およびキャパシタ用電極線６に対するソース電
極線２のクロスオーバー部分の面積を可能な限り小さく
すればよい。In order to make the electric capacity of the arc-shaped wiring portion substantially the same as that of the other linear wiring portions, the crossover portion of the source electrode line 2 with respect to the gate electrode line 1 and the capacitor electrode line 6 is formed. The area should be as small as possible.
【００２１】そのため、この実施形態では、ソース電極
線２の円弧状配線部２ａを、ゲート電極線１の円弧状配
線部１ａとキャパシタ用電極線６の円弧状配線部６ａと
の間の線間内に配置するようにしている。Therefore, in this embodiment, the arc-shaped wiring portion 2a of the source electrode line 2 is arranged between the arc-shaped wiring portion 1a of the gate electrode line 1 and the arc-shaped wiring portion 6a of the capacitor electrode line 6. I try to place it inside.
【００２２】なお、電極線の抵抗を均一なものとするた
めには、電極線幅は円弧状配線部と直線状配線部とで等
幅であることが好ましいが、電極線の抵抗値にＴＦＴを
駆動するに十分な余力がある場合には、円弧状配線部の
線幅を狭めてもよい。In order to make the resistance of the electrode wire uniform, it is preferable that the electrode wire width is equal between the arc-shaped wiring portion and the straight wiring portion. If there is sufficient surplus power to drive the, the line width of the arc-shaped wiring portion may be narrowed.
【００２３】これとは反対に、設計の都合上、ゲート電
極線１の円弧状配線部１ａとキャパシタ用電極線６の円
弧状配線部６ａとの間の線間幅が、相対的にソース電極
線２の円弧状配線部２ａの線幅よりも狭くなってしまう
場合には、円弧状配線部２ａの線幅の中心と、円弧状配
線部１ａと円弧状配線部６ａ間の線間中心とを合わせる
ように配線することが好ましい。On the contrary, for the sake of design, the line width between the arcuate wiring portion 1a of the gate electrode line 1 and the arcuate wiring portion 6a of the capacitor electrode line 6 is relatively large. When the line width of the line 2 becomes narrower than the line width of the arc-shaped wiring part 2a, the center of the line width of the arc-shaped wiring part 2a and the center of the line between the arc-shaped wiring part 1a and the arc-shaped wiring part 6a. It is preferable to wire so that they are aligned with each other.
【００２４】次に、図３を参照して、本発明の別の実施
形態について説明する。この別の実施形態では、ゲート
電極線１およびキャパシタ用電極線６の円弧状配線部１
ａ，６ａを束とし、また、ソース電極線２の円弧状配線
部２ａも束として、貫通孔１３を回避して配線する。Next, another embodiment of the present invention will be described with reference to FIG. In this other embodiment, the arc-shaped wiring portion 1 of the gate electrode line 1 and the capacitor electrode line 6 is formed.
The a and 6a are bundled, and the arc-shaped wiring portion 2a of the source electrode wire 2 is also bundled to avoid the through hole 13 for wiring.
【００２５】図３の例では、円弧状配線部２ａの束を貫
通孔１３の内周側とし、円弧状配線部１ａ，６ａの束を
その外周側に配置しているが、逆に円弧状配線部１ａ，
６ａの束を内周側とし、円弧状配線部２ａの束を外周側
としてもよい。In the example of FIG. 3, the bundle of arcuate wiring portions 2a is arranged on the inner peripheral side of the through hole 13 and the bundle of arcuate wiring portions 1a and 6a is arranged on the outer peripheral side thereof. Wiring part 1a,
The bundle of 6a may be on the inner peripheral side and the bundle of arcuate wiring portions 2a may be on the outer peripheral side.
【００２６】なお、いずれの電極線においても、その円
弧状配線の曲率は内周側配線と外周側配線とで同一であ
ることを要しない。例えば、図３のように束として配線
される場合には、内周側の円弧状配線が小曲率で、外周
側の円弧状配線が大曲率とされてよい。In any of the electrode wires, the curvature of the arcuate wiring need not be the same for the inner peripheral side wiring and the outer peripheral side wiring. For example, when wiring as a bundle as shown in FIG. 3, the arcuate wiring on the inner peripheral side may have a small curvature and the arcuate wiring on the outer peripheral side may have a large curvature.
【００２７】[0027]
【発明の効果】以上説明したように、本発明によれば、
貫通孔を有するＴＦＴ−ＬＣＤにおいて、貫通孔の周辺
に配線されるゲート電極線，ソース電極線およびキャパ
シタ用電極線の各々に、貫通孔の軸線を中心とする円弧
状配線部をそれぞれ形成し、ソース電極線の円弧状配線
部を、ゲート電極線とキャパシタ用電極線の各円弧状配
線部の間に配置するか、もしくは、ゲート電極線および
キャパシタ用電極線の各円弧状配線部を束にして貫通孔
の内周側もしくは外周側のいずれか一方の側に配置し、
いずれか他方の側にソース電極線の円弧状配線部を束に
して配置するようにしたことにより、貫通孔を避けて迂
回した配線部分と、そうでない他の配線部分との電気容
量をできるだけ同じ条件として、迂回した配線部分の先
の画素で部分的な表示むらの発生を防止することができ
る。As described above, according to the present invention,
In a TFT-LCD having a through hole, arc-shaped wiring portions centering on the axis of the through hole are formed in each of the gate electrode line, the source electrode line and the capacitor electrode line that are wired around the through hole, Arrange the arc-shaped wiring part of the source electrode line between the arc-shaped wiring parts of the gate electrode line and the capacitor electrode line, or bundle the arc-shaped wiring parts of the gate electrode line and the capacitor electrode line. Placed on either the inner or outer peripheral side of the through hole,
By arranging the arc-shaped wiring part of the source electrode line in a bundle on the other side, the electric capacity of the detoured wiring part avoiding the through hole and the other wiring part which is not the same are as equal as possible. As a condition, it is possible to prevent the occurrence of partial display unevenness in the pixels ahead of the bypassed wiring portion.
【図１】本発明の実施形態に係る液晶表示素子が備える
貫通孔部分を概略的に示した断面図。FIG. 1 is a sectional view schematically showing a through hole portion included in a liquid crystal display element according to an embodiment of the present invention.
【図２】上記貫通孔周辺の電極線の配線状態を示した平
面図。FIG. 2 is a plan view showing a wiring state of electrode wires around the through hole.
【図３】本発明の別の実施形態の要部を図２とは異なる
縮尺で示した平面図。FIG. 3 is a plan view showing a main part of another embodiment of the present invention at a scale different from that of FIG.
【図４】ＴＦＴ−ＬＣＤの１画素の構成を示した模式
図。FIG. 4 is a schematic diagram showing the configuration of one pixel of a TFT-LCD.
１ ゲート電極線 ２ ソース電極線 ３ ＴＦＴ ４ 画素電極 ５ 蓄積容量 ６ キャパシタ用電極線 １１ アレイ基板 １２ 対向基板 １３ 貫通孔 １ａ，２ａ，６ａ 円弧状配線部 1 Gate electrode line 2 Source electrode wire 3 TFT 4 pixel electrodes 5 storage capacity 6 Capacitor electrode wire 11 Array substrate 12 Counter substrate 13 through holes 1a, 2a, 6a Circular wiring part
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/786 Ｈ０１Ｌ 29/78 ６１２Ｃ Ｆターム(参考） 2H092 GA13 GA20 GA26 GA37 GA41 JA24 MA35 NA25 NA27 PA01 PA05 PA06 5C094 AA03 BA03 BA43 CA19 CA20 EA04 EA07 5F110 AA30 BB01 EE37 HM19 NN72 NN73 Front page continuation (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 29/786 H01L 29/78 612C F term (reference) 2H092 GA13 GA20 GA26 GA37 GA41 JA24 MA35 NA25 NA27 PA01 PA05 PA06 5C094 AA03 BA03 BA43 CA19 CA20 EA04 EA07 5F110 AA30 BB01 EE37 HM19 NN72 NN73
Claims (5)
とに能動素子と蓄積容量とが設けられ、その各能動素子
に対してゲート電極線とソース電極線とが配線接続され
ているアレイ基板と、共通電極を有する対向基板とを周
辺シール材を介して圧着し、その各基板間に液晶を封入
してなるアクティブマトリクス方式の液晶表示素子にお
いて、 表示部内の所定部位に、上記両基板を同軸的に貫通し内
面が環状シール材により封止された貫通孔が設けられて
おり、上記貫通孔の周辺に配線される上記ゲート電極線
および上記ソース電極線の各々には、上記貫通孔の軸線
を中心とする円弧状配線部がそれぞれ形成されており、
上記ソース電極線の円弧状配線部が、上記ゲート電極線
の円弧状配線部の間に配置されていることを特徴とする
液晶表示素子。1. An array substrate in which an active element and a storage capacitor are provided for each pixel electrode arranged in a matrix, and a gate electrode line and a source electrode line are connected to each active element by wiring. , An active matrix type liquid crystal display element in which a counter substrate having a common electrode is pressure-bonded through a peripheral sealing material, and liquid crystal is sealed between the substrates, and the both substrates are coaxial with each other at a predetermined portion in the display section. Is provided with a through hole whose inner surface is sealed by an annular sealing material, and each of the gate electrode line and the source electrode line wired around the through hole has an axis line of the through hole. Arc-shaped wiring parts centered on are respectively formed,
A liquid crystal display element, wherein the arc-shaped wiring part of the source electrode line is arranged between the arc-shaped wiring parts of the gate electrode line.
に配線されたキャパシタ用電極線に接続されており、上
記貫通孔の周辺に配線される上記ゲート電極線，上記ソ
ース電極線および上記キャパシタ用電極線の各々には、
上記貫通孔の軸線を中心とする円弧状配線部がそれぞれ
形成されており、上記ソース電極線の円弧状配線部が、
上記ゲート電極線と上記キャパシタ用電極線の各円弧状
配線部の間に配置されている請求項１に記載の液晶表示
素子。2. The gate electrode line, the source electrode line, and the capacitor, wherein the storage capacitor is connected to a capacitor electrode line wired in parallel with the gate electrode line, and is wired around the through hole. For each of the electrode wires for
Arc-shaped wiring portions centered on the axis of the through hole are formed, respectively, the arc-shaped wiring portion of the source electrode line,
The liquid crystal display element according to claim 1, wherein the liquid crystal display element is arranged between each of the arc-shaped wiring portions of the gate electrode line and the capacitor electrode line.
線と、上記ゲート電極線と上記キャパシタ用電極線の各
円弧状配線部間の中心線とが一致している請求項２に記
載の液晶表示素子。3. The center line of the arc-shaped wiring portion of the source electrode line and the center line between the arc-shaped wiring portions of the gate electrode line and the capacitor electrode line are coincident with each other. Liquid crystal display element.
とに能動素子と蓄積容量とが設けられ、その各能動素子
に対してゲート電極線とソース電極線とが配線接続され
ているアレイ基板と、共通電極を有する対向基板とを周
辺シール材を介して圧着し、その各基板間に液晶を封入
してなるアクティブマトリクス方式の液晶表示素子にお
いて、 表示部内の所定部位に、上記両基板を同軸的に貫通し内
面が環状シール材により封止された貫通孔が設けられて
おり、上記貫通孔の周辺に配線される上記ゲート電極線
および上記ソース電極線の各々には、上記貫通孔の軸線
を中心とする円弧状配線部がそれぞれ形成されており、
上記ゲート電極線の円弧状配線部が上記貫通孔の内周側
もしくは外周側のいずれか一方の側に配置され、いずれ
か他方の側に上記ソース電極線の円弧状配線部が配置さ
れていることを特徴とする液晶表示素子。4. An array substrate in which an active element and a storage capacitor are provided for each pixel electrode arranged in a matrix, and a gate electrode line and a source electrode line are connected to each active element by wiring. , An active matrix type liquid crystal display element in which a counter substrate having a common electrode is pressure-bonded through a peripheral sealing material, and liquid crystal is sealed between the substrates, and the both substrates are coaxial with each other at a predetermined portion in the display section. Is provided with a through hole whose inner surface is sealed by an annular sealing material, and each of the gate electrode line and the source electrode line wired around the through hole has an axis line of the through hole. Arc-shaped wiring parts centered on are respectively formed,
The arc-shaped wiring portion of the gate electrode line is arranged on one of the inner peripheral side and the outer peripheral side of the through hole, and the arc-shaped wiring portion of the source electrode line is arranged on the other side. A liquid crystal display device characterized by the above.
に配線されたキャパシタ用電極線に接続されており、上
記貫通孔の周辺に配線される上記ゲート電極線，上記ソ
ース電極線および上記キャパシタ用電極線の各々には、
上記貫通孔の軸線を中心とする円弧状配線部がそれぞれ
形成されており、上記ゲート電極線および上記キャパシ
タ用電極線の各円弧状配線部が上記貫通孔の内周側もし
くは外周側のいずれか一方の側に配置され、いずれか他
方の側に上記ソース電極線の円弧状配線部が配置されて
いる請求項４に記載の液晶表示素子。5. The gate electrode line, the source electrode line, and the capacitor, wherein the storage capacitor is connected to a capacitor electrode line wired in parallel with the gate electrode line, and is wired around the through hole. For each of the electrode wires for
Arc-shaped wiring portions centering on the axis of the through-hole are formed, and each arc-shaped wiring portion of the gate electrode line and the capacitor electrode line is located either on the inner peripheral side or the outer peripheral side of the through-hole. The liquid crystal display element according to claim 4, wherein the liquid crystal display element is arranged on one side, and the arcuate wiring part of the source electrode line is arranged on the other side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001366880A JP2003167271A (en) | 2001-11-30 | 2001-11-30 | Liquid crystal display element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001366880A JP2003167271A (en) | 2001-11-30 | 2001-11-30 | Liquid crystal display element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003167271A true JP2003167271A (en) | 2003-06-13 |
Family
ID=19176717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001366880A Withdrawn JP2003167271A (en) | 2001-11-30 | 2001-11-30 | Liquid crystal display element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003167271A (en) |
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| US7420642B2 (en) | 2003-12-11 | 2008-09-02 | Lg Display Co., Lcd | Array substrate for in-plane switching mode liquid crystal display device |
| JP2008233606A (en) * | 2007-03-22 | 2008-10-02 | Seiko Epson Corp | Active-matrix circuit board and display |
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| US7420642B2 (en) | 2003-12-11 | 2008-09-02 | Lg Display Co., Lcd | Array substrate for in-plane switching mode liquid crystal display device |
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| JP2010008698A (en) * | 2008-06-26 | 2010-01-14 | Sharp Corp | Electronic paper |
| JP2010197740A (en) * | 2009-02-25 | 2010-09-09 | Kyocera Corp | Liquid crystal display panel and liquid crystal display device including the same |
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