WO2023035689A1 - 基于片上数字反馈自校准系统的真随机数发生器 - Google Patents

基于片上数字反馈自校准系统的真随机数发生器 Download PDF

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Publication number
WO2023035689A1
WO2023035689A1 PCT/CN2022/095919 CN2022095919W WO2023035689A1 WO 2023035689 A1 WO2023035689 A1 WO 2023035689A1 CN 2022095919 W CN2022095919 W CN 2022095919W WO 2023035689 A1 WO2023035689 A1 WO 2023035689A1
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random number
bias
output
signal
capacitor
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PCT/CN2022/095919
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English (en)
French (fr)
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赵晓锦
郝嘉诚
梁胜权
罗逸安
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深圳大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
    • G06M1/00—Design features of general application
    • G06M1/27—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum
    • G06M1/272—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum using photoelectric means

Definitions

  • the invention relates to the technical field of integrated circuits, in particular to a true random number generator based on an on-chip digital feedback self-calibration system.
  • the Internet of Things industry will usher in faster development, and penetrate into different fields such as smart office, smart medical care, wearable devices, and mobile payment. Provide convenience and quality assurance for our life.
  • the Internet of Things facilitates people's lives, it also has the risk of being hacked, leading to a series of privacy issues and security risks, such as physical tracking, personal characteristic profiling, and unauthorized access.
  • Some applications in medicine, such as blood pressure monitors, diabetes monitors, and cardiac pacemakers, can even be life-threatening if they are remotely hacked and tampered with.
  • NVM non-volatile memory
  • the complexity of the algorithm itself also causes the circuit to consume a large amount of hardware resources, which increases the manufacturing cost. Therefore, it is still a technology worthy of research to provide a secure, reliable, low-cost, and low-power encryption scheme for IoT devices.
  • Physically unclonable function Physically unclonable function
  • TRNG true random number generator
  • PUF Physically unclonable function
  • TRNG true random number generator
  • the output of PUF depends on random process deviation, which makes the output of PUF not easy to be erased and tampered with like NVM.
  • PUF is like the DNA of a chip. The output is determined after the chip is manufactured, and the physical parameters are hidden inside the chip to prevent information from being leaked.
  • TRNG is a hardware security primitive technology that exploits random physical processes in nanometer-scale circuits to obtain random numbers. These physical processes include thermal noise, clock drift, jitter, external electromagnetics, quantum phenomena, etc. Because such physical processes are difficult to capture and predict in nanoscale circuits, TRNGs are unpredictable.
  • TRNG is a key module for data encryption technologies such as symmetric encryption and asymmetric encryption to improve security.
  • TRNG can also be used to cut off the direct relationship between PUF excitation and response, and confuse the relationship between strong PUF excitation and response, so as to resist machine learning attacks.
  • the existing TRNG can usually only generate stable true random numbers under stable voltage and normal temperature. If the input voltage fluctuates or the temperature changes, the randomness of the true random number output by the existing TRNG will deviate. Based on TRNG The reliability of the output true random number for subsequent encryption processing is affected. Therefore, the true random number generator in the prior art method has the problem of insufficient reliability in use.
  • An embodiment of the present invention provides a true random number generator based on an on-chip digital feedback self-calibration system, aiming to solve the problem of poor reliability in use of the true random number generator in the prior art.
  • the embodiment of the present invention provides a true random number generator based on an on-chip digital feedback self-calibration system, which includes a noise digitization circuit, a bias judgment circuit, a self-calibration logic circuit and a post-processing circuit;
  • the noise digitization circuit includes a first inverting unit, a second inverting unit, an arbiter, a first capacitor array and a second capacitor array; the input terminal of the first inverting unit is connected to the second inverting unit The input terminal is connected and used as a signal input terminal to receive a clock signal; the output terminal of the first inverting unit is connected to the first input terminal of the arbiter and one end of the first capacitor array, and the first capacitor The other end of the array is grounded, the output end of the second inverting unit is connected to the second input end of the arbiter and one end of the second capacitor array, and the other end of the second capacitor array is grounded, so
  • the output terminal of the arbitrator is used to output an initial random number;
  • the noise digitization circuit is used to output the delay difference of jitter and noise generated by the two inverter chains under the input of the clock signal as an initial random number;
  • the first input end of the post-processing circuit is connected to the output end of the arbiter, the second input end is connected to the signal input end, and the output end is used to output an enhanced random number signal;
  • the post-processing circuit is used for The initial random number is processed by an algorithm to obtain an enhanced random number signal and output;
  • the first input terminal of the bias judging circuit is connected to the output terminal of the arbitrator, the second input terminal is connected to the initialization signal input terminal, the first bias output terminal is used to output the first bias signal, and the second input terminal is used to output the first bias signal.
  • the bias output terminal is used to output the second bias signal, and the second input terminal of the bias judgment circuit is used to input the initialization signal; the bias judgment circuit is used to detect and judge the bias direction of the original random number to output a first bias signal and a second bias signal;
  • the first input terminal and the second input terminal of the self-calibration logic circuit are both connected to the output terminal of the arbitrator, the third input terminal is connected to the signal input terminal, and the fourth signal input terminal is connected to the second bias input terminal.
  • Its fifth signal input terminal is connected to the first bias signal output terminal; its first control output terminal is connected to the control switch of the first capacitor array, and the first control signal is output to control access to the first bias signal.
  • the capacitance of an inverting unit is used to compensate the additional delay time of the first inverting unit, and its second control output terminal is connected to the control switch of the second capacitor array, and the second control signal is output to control access to the second
  • the capacitance of the inverting unit is used to compensate the extra delay time of the second inverting unit, so that the delay times of the first inverting unit and the second inverting unit due to process errors are compensated to be equal;
  • the calibration logic circuit is used to calibrate the first bias signal and the second bias signal according to the clock signal and the initial random number to obtain the first control signal and the second control signal.
  • the true random number generator based on the on-chip digital feedback self-calibration system, wherein, the first inverting unit and the second inverting unit are composed of a plurality of inverters connected in series.
  • the true random number generator based on the on-chip digital feedback self-calibration system, wherein, the first capacitor array and the second capacitor array are composed of a plurality of capacitor pairs equal in number, and the first capacitor array Or the delay time corresponding to the capacitance pairs included in the second capacitance array increases exponentially in turn.
  • the true random number generator based on the on-chip digital feedback self-calibration system, wherein the capacitor pair includes a capacitor whose one end is connected to the output end of the first inverting unit through the first control switch, and the other end is grounded. a first capacitor, and a second capacitor whose one end is connected to the output end of the second inverting unit through a second control switch, and whose other end is grounded;
  • the sizes of the first capacitors in each capacitor pair of the first capacitor array increase sequentially, and the sizes of the second capacitors in each capacitor pair are equal;
  • the sizes of the first capacitors in each capacitor pair of the second capacitor array are equal, and the sizes of the second capacitors in each capacitor pair increase sequentially.
  • the true random number generator based on the on-chip digital feedback self-calibration system, wherein the first control switch and the second control switch in each capacitor pair of the first capacitor array are connected to the first control output terminal connected to receive the first control signal input from the first control output terminal and to perform on-off control for each capacitor pair in the first capacitor array, thereby controlling the pair of the first capacitor array to the first Compensation duration of the extra delay time of the inverting unit and the second inverting unit;
  • the first control switch and the second control switch in each capacitor pair of the second capacitor array are connected to the second control output terminal to receive the second control signal input from the second control output terminal and On-off control is performed on each capacitor pair in the second capacitor array, so as to control the compensation period of the second capacitor array for the extra delay time of the first inverting unit and the second inverting unit.
  • the capacitors in the capacitor pair are gate capacitors of NMOS transistors.
  • the true random number generator based on the on-chip digital feedback self-calibration system, wherein the noise digitization circuit, the bias judgment circuit, the self-calibration logic circuit and the post-processing circuit all use complementary metal oxide It is produced by the material semiconductor process.
  • the true random number generator based on the on-chip digital feedback self-calibration system, wherein the bias judgment circuit includes a flip-flop, a first NOR gate and a second NOR gate;
  • the first input end of the flip-flop is connected to the output end of the arbiter, the second input end thereof is connected to the initialization signal input end, the first output end thereof is connected to the first input end of the first NOR gate, Its second output terminal is connected to the second input terminal of the second NOR gate;
  • the second input end of the first NOR gate is connected to the first input end of the second NOR gate for inputting a reset signal; the output end of the first NOR gate is used as the bias judgment
  • the first bias output terminal of the circuit outputs a first bias signal
  • the output terminal of the second NOR gate serves as a second bias output terminal of the bias judgment circuit to output a second bias signal.
  • the true random number generator based on the on-chip digital feedback self-calibration system, wherein the self-calibration logic circuit includes a first up-down counter, a second up-down counter, a reset logic, a third NOR gate and a fourth NOR gate;
  • the first input terminal of the first up-down counter is connected to the output terminal of the arbitrator, the second input terminal is connected to the signal input terminal, and the reset is set in series between the third input terminal and the first output terminal.
  • a logic device the fourth output terminal of which is connected to the second input terminal of the second up-down counter;
  • the first input terminal of the second up-down counter is connected to the output terminal of the arbitrator, the first output terminal thereof is connected to the second input terminal of the third NOR gate, and the second output terminal thereof is connected to the fourth NOR gate.
  • the first input terminal of the third NOR gate is connected to the second bias output terminal, and the output terminal is connected to the first capacitor array;
  • the second input end of the fourth NOR gate is connected to the first bias output end, and the output end is connected to the second capacitor array.
  • the first up-down counter is a four-bit up-down counter
  • the second up-down counter is a ten-bit up-down counter
  • An embodiment of the present invention provides a true random number generator based on an on-chip digital feedback self-calibration system, including a noise digitization circuit, a bias judgment circuit, a self-calibration logic circuit, and a post-processing circuit.
  • the noise digitization circuit includes a first inverting unit , the second inverting unit, the arbiter, the first capacitor array and the second capacitor array, and the noise digitization circuit is used to output the difference between the jitter and noise generated by the two inverter chains under the action of the input clock signal as an initial random number
  • the post-processing circuit is used to algorithmically process the initial random number to obtain an enhanced random number signal and output it
  • the bias judgment circuit is used to detect and judge the bias direction of the original random number so as to output the first bias signal and the second bias signal
  • the self-calibration logic circuit is used to calibrate the signal delays of the two inverter chains due to process errors according to the generated first bias signal and the second bias signal to obtain the first control signal and the second control signal
  • FIG. 1 is an overall circuit structure diagram of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention
  • FIG. 2 is a partial circuit structure diagram of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention
  • FIG. 3 is a partial circuit structure diagram of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention
  • FIG. 4 is a schematic diagram of the effect of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention
  • FIG. 5 is a schematic diagram of the effect of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention
  • FIG. 6 is a schematic diagram of the effect of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention
  • FIG. 7 is a structural layout of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention.
  • Fig. 8 is a self-calibration logic flow chart of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention
  • FIG. 9 is a schematic diagram of the effect of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of the effect of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention
  • FIG. 11 is a schematic diagram of the effect of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention.
  • Fig. 1 is the overall circuit structure diagram of the true random number generator based on the on-chip digital feedback self-calibration system provided by the embodiment of the present invention
  • FIG. 3 is a partial circuit structure diagram of the true random number generator based on the on-chip digital feedback self-calibration system provided by the embodiment of the present invention.
  • a true random number generator based on an on-chip digital feedback self-calibration system includes a noise digitization circuit 11, a bias judgment circuit 12, a self-calibration logic circuit 13 and a post-processing circuit H 0 .
  • the noise digitization circuit 11 includes a first inverting unit I, a second inverting unit I', an arbiter Z 0 , a first capacitor array CM 1 and a second capacitor array CM 2 ; the first inverting unit I
  • the input end is connected with the input end of the second inverting unit I' and receives the clock signal CLK as the signal input end, the clock signal is a square wave signal with a certain frequency, and its waveform is a wave signal as shown on the left side of Figure 2,
  • the output end of the first inverting unit I is connected to the first input end of the arbiter Z0 and one end of the first capacitor array CM1 , and the other end of the first capacitor array CM1 is grounded,
  • the output end of the second inverting unit I' is connected to the second input end of the arbiter Z0 and one end of the second capacitor array CM2 , and the other end of the second capacitor array CM2 is grounded , the output terminal of the arbiter Z 0 is used to
  • the basic structure of the noise digitization circuit 11 is shown in FIG. Afterwards, the ends of the first inverting unit I and the second inverting unit I' will obtain the two clock signals CLKA and CLKB accumulated with inverter oscillation noise, and the obtained two clock signals CLKA and CLKB respectively Input to the two input terminals of the arbiter Z 0 , the function of the arbiter Z 0 is to output a high level or a low level according to the sequence of each rising edge of CLKA and CLKB.
  • Figure 4 is a schematic diagram of the effect of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention, and Figure 4 is a simulation of 1000 groups of delays based on CLKA and CLKB in the noise digitization circuit 11 of Figure 2 under the influence of noise Difference statistical distribution diagram, where the unit of delay time is picosecond (ps), and the fitted curve conforms to Gaussian distribution, and this Gaussian distribution can be expressed by formula (1);
  • ⁇ 0.01ps (ideally it should be 0ps), and ⁇ is 7.74ps.
  • Delay noise when Delay noise is less than 0 in a certain CLK cycle, it means that under the action of noise, the rising edge of CLKA reaches the arbiter Z 0 before CLKB, and the initial random output of the arbiter Z 0
  • the number OUT' is a low level signal, otherwise the initial random number OUT' is a high level signal.
  • the probability P(0) of OUT' output being 0 will be close to 50%, and it meets the requirements of random numbers ( ⁇ 0.24 ⁇ ) within the NIST area (inside the dotted line box in Figure 4).
  • the first inverting unit I and the second inverting unit I' are composed of a plurality of inverters connected in series, as shown in FIG. 2 , the first inverting unit I is composed of The inverter I 1 , the inverter I 2 , ... and the inverter In are connected in series, the input terminal of the inverter I 1 is the input terminal of the first inverting unit I, and the output terminal of the inverter In That is, as the output terminal of the first inverting unit I, similarly, the second inverting unit I' is composed of an inverter I' 1 , an inverter I' 2 , ...
  • inverter I' n connected in series, and the first The number of inverters included in the inverting unit I and the second inverting unit I' is equal, such as the number of inverters included in the first inverting unit I and the second inverting unit I' in the specific embodiment of the case Both are n.
  • both the first capacitor array CM 1 and the second capacitor array CM 2 are composed of multiple capacitor pairs with an equal number, and the first capacitor array CM 1 or the second capacitor array CM 2 includes The delay time corresponding to the capacitor pair increases exponentially in turn.
  • the capacitor pair includes a first capacitor whose one end is connected to the output end of the first inverting unit I through a first control switch, and whose other end is grounded, and a first capacitor whose one end is connected to the first capacitor through a second control switch.
  • the output ends of the two inversion units I' are connected to each other and the other end is grounded to the second capacitor, as shown in FIG. 3, the first capacitor array CM 1 includes ten capacitor pairs, and each capacitor pair includes two capacitors, as shown in FIG.
  • a capacitor pair is composed of a first capacitor CA0 and a second capacitor CA'0 , one end of the first capacitor CA0 is connected to the output terminal (A terminal) of the first inverting unit I through the first control switch K, The other end is grounded, one end of the second capacitor CA'0 is connected to the output end (B end) of the second inverting unit I' through the first control switch K', and the other end is grounded.
  • the size of the first capacitor CA'0 in each capacitor pair of the first capacitor array CM1 increases sequentially, and the size of the second capacitor CA'0 in each capacitor pair is equal; each capacitor CA'0 in the second capacitor array CM2
  • the sizes of the first capacitors CA 0 in a capacitor pair are all equal, and the sizes of the second capacitors CA' 0 in each capacitor pair increase sequentially.
  • the first control switch K and the second control switch K' in each capacitor pair of the first capacitor array CM1 are connected to the first control output terminal to receive the The first control signal S_A[9:0] (which includes ten sub-signals) input from the first control output terminal and performs on-off control for each capacitor pair in the first capacitor array CM 1 , thereby controlling the The first capacitor array CM1 compensates for the additional delay time of the first inverting unit I and the second inverting unit I′, the first control switch and the first control switch of each capacitor pair in the first capacitor array CM1
  • the second control switch constitutes the control switch of the first capacitor array; the first control switch K and the second control switch K' in each capacitor pair of the second capacitor array CM 2 are connected with the second control output terminals are connected to receive the second control signal S_B[9:0] (including ten sub-signals) input from the second control output terminal and to pass through each capacitor pair in the second capacitor array CM2 respectively.
  • each capacitor in the second capacitor array CM 2 is Off control, thereby controlling the compensation duration of the second capacitor array CM 2 for the additional delay time of the first inverting unit I and the second inverting unit I', each capacitor in the second capacitor array CM 2
  • the pair of first control switch and second control switch constitutes the control switch of the first capacitor array.
  • the capacitors in the capacitor pair are gate capacitors of NMOS transistors.
  • the noise digitization circuit 11, the bias judgment circuit 12, the self-calibration logic circuit 13, and the post-processing circuit H0 are all produced by complementary metal oxide semiconductor technology, so as to achieve Compatible with the circuit components manufactured by the type metal oxide semiconductor process, in a more specific embodiment, the solution can be produced by using a 65nm, 1.2V low leakage process (low leakage) complementary metal oxide semiconductor process (CMOS process) Each circuit unit involved in.
  • CMOS process complementary metal oxide semiconductor process
  • each sub-signal in the first control signal S_A[9:0] can control a capacitance at the same time
  • the on-off of the pair that is, the two capacitors included in a capacitor pair are connected to the circuit at the same time or disconnected at the same time, then the final capacitance accuracy added by each capacitor pair is the difference between the two capacitors included in the capacitor pair value, the larger the capacitance value, the longer the additional delay time to be compensated, and the additional delay time compensated by each capacitor in the first capacitor array CM 1 at the output terminal of the first inverting unit I is the capacitance
  • the design size of the capacitor in the second capacitor array CM 2 is symmetrical to that of the first capacitor array CM 1 , that is, the first row of capacitors in the second capacitor array CM 2 is ten delay compensation transistors (all of the same size), and the second row The capacitors are ten main delay transistors (increasing in size).
  • Figure 5 is a schematic diagram of the effect of the true random number generator based on the on-chip digital feedback self-calibration system provided by the embodiment of the present invention, in S_A[9:0] (wherein 10 sub-signals can be expressed as 10-bit binary numbers in sequence)
  • S_A[9:0] wherein 10 sub-signals can be expressed as 10-bit binary numbers in sequence
  • the delay changes of CLKA and CLKB under its influence are shown in Figure 5.
  • the transistor capacitance of the first capacitor array CM 1 increases the delay time basically with the increase of S_A[9:0 ]
  • the growth of the value increases linearly, and the slope is about 0.9ps/bit, which is much better than the 82ps/bit in the traditional technical method.
  • the first input terminal of the post-processing circuit H0 is connected to the output terminal of the arbiter Z0 , its second input terminal is connected to the signal input terminal, and its output terminal is used to output the enhanced random number signal OUT; then the initial random number The number OUT' is input to the post-processing circuit H 0 through the first input terminal, and the clock signal CLK is input to the post-processing circuit H 0 through the second input terminal, and the post-processing circuit H 0 is used to process the initial random number OUT'
  • the algorithm processing gets the enhanced random number signal OUT and outputs it.
  • the post-processing circuit H0 may be an eight-level XOR chain composed of eight XOR gates connected in series.
  • the first input terminal of the bias judgment circuit 12 is connected to the output terminal of the arbiter Z0 , its second input terminal is connected to the initialization signal input terminal, and its first bias output terminal is used to output the first bias signal reset_S_A , its second bias output terminal is used to output the second bias signal reset_S_B, the second input terminal of the bias judgment circuit 12 is used to input the initialization signal CLK_I; the bias judgment circuit is used for the original random number OUT 'Detect and judge the bias direction so as to output the first bias signal reset_S_A and the second bias signal reset_S_B.
  • the bias judgment circuit 12 includes a flip-flop Cf, a first NOR gate NOR 1 and a second NOR gate NOR 2 ; the first input terminal Cf_D of the flip-flop Cf is connected to the The output terminal of the arbiter Z 0 , its second input terminal Cf_E is connected to the initialization signal input terminal, its first output terminal Cf_Q is connected to the first input terminal of the first NOR gate NOR 1 , its second output terminal Cf_Q_n Connect the second input end of the second NOR gate NOR 2 ; the second input end of the first NOR gate is connected with the first input end of the second NOR gate for inputting the reset signal R ;
  • the output terminal of the first NOR gate NOR 1 is used as the first bias output terminal of the bias judgment circuit 12 to output the first bias signal reset_S_A, and the output terminal of the second NOR gate NOR 2 is used as the first bias output terminal of the bias judgment circuit 12.
  • the second bias output terminal of the bias judgment circuit 12 outputs a second bias signal reset_S_B.
  • the second input terminal Cf_E of the flip-flop Cf is used to input the initialization signal CLK_I
  • the initialization signal CLK_I can be used as a switch signal of the flip-flop Cf
  • the initialization signal CLK_I is set at a high level when the flip-flop Cf starts to work and remains there.
  • the function of the bias judging circuit 12 is to judge the order of the rising edges of CLKA and CLKB under the condition that no capacitance is added to the end of the first inverting unit I and the second inverting unit I′, so as to determine the order of the rising edges of CLKA and CLKB through the first capacitor array CM 1 and The specific position where the capacitor is turned on in the second capacitor array CM2 (increase the capacitor at one end of the inverting unit where the rising edge comes faster, thereby increasing the delay time), so that the rising edges of CLKA and CLKB come closer.
  • the first input terminal and the second input terminal of the self-calibration logic circuit 13 are connected to the output terminal of the arbiter Z0 , the third input terminal thereof is connected to the signal input terminal, and the fourth signal input terminal thereof is connected to the The second bias output terminal, its fifth signal input terminal is connected to the first bias signal output terminal; its first control output terminal is connected to the first capacitor array CM1 to output the first control signal S_A[9:0 ] to control the delay time of the first capacitor array CM1 , and its second control output terminal is connected to the second capacitor array CM2 to output a second control signal S_B[9:0] to control the delay time of the second capacitor array CM2 ;
  • the self-calibration logic circuit 13 is used to calibrate the first bias signal reset_S_A and the second bias signal reset_S_B according to the clock signal CLK and the initial random number OUT' to obtain the first control signal S_A[9:0] and the second control signal S_B[9:0].
  • the first control signal S_A[9:0] and the second control signal S_B[9:0] are composed of ten sub-signals, and each sub-signal can be represented by "0" or "1", then the ten sub-signals Combining in order can be expressed as a 10-bit binary number, and the value range of the 10-bit binary number is [0, 1023].
  • the self-calibration logic circuit 13 includes a first up-down counter J 1 , a second up-down counter J 2 , a reset logic F, a third NOR gate NOR 3 and a fourth NOR gate NOR 4 ; the first input terminal J1_a /s of the first up-down counter J1 is connected to the output terminal of the arbiter Z0 , its second input terminal J1_E is connected to the signal input terminal, and its second input terminal J1_E is connected to the signal input terminal.
  • the reset logic F is set in series between the three input terminals J1_reset and the first output terminal J1_T , and its fourth output terminal J1_co is connected to the second input terminal J2_ of the second up-down counter J2 .
  • the first input terminal J2_a /s of the second up-down counter J2 is connected to the output terminal of the arbiter Z0 , and its first output terminal J2_Q is connected to the third NOR gate NOR3
  • the second input end of the second input end, its second output end J2_Q_n is connected to the first input end of the fourth NOR gate NOR 4 ;
  • the first input end of the third NOR gate NOR 3 is connected to the second bias Set the output terminal, the output terminal is connected to the first capacitor array CM 1 ;
  • the second input terminal of the fourth NOR gate NOR 4 is connected to the first bias output terminal, and the output terminal is connected to the second capacitor array CM 2 .
  • the first addition and subtraction counter J 1 is a four-
  • the initial random number OUT' is low level, it indicates that CLKA is faster than CLKB, and a capacitor should be added at the output terminal of the first inverting unit I, otherwise, a capacitor should be added at the output terminal of the second inverting unit I' Add capacitance to the output.
  • the initial random number OUT' will be stored in the flip-flop Cf.
  • the first bias signal reset_S_A and the second bias signal reset_S_B can be used to select to close all of the output terminals of the first capacitor array CM 1 or the output terminals of the second capacitor array CM 2 capacitance.
  • the self-calibration logic circuit 13 is composed of two up-subtract counters, the first up-subtract counter has four digits, and the second up-subtract counter has ten digits.
  • the function of the four-digit addition and subtraction counter output Cnt4[3:0] is to count the bias of the initial random number OUT' output 0 and 1, while the ten-digit addition and subtraction counter outputs Cnt10[9:0] and Cnt10_n[9:0 ], after performing NOR logic operations with reset_S_A and reset_S_B respectively, the first control signal S_A[9:0] and the second control signal S_B[9:0] for controlling the capacitor array can be obtained.
  • FIG. 8 is a self-calibration logic flow chart of a true random number generator based on an on-chip digital feedback self-calibration system provided by an embodiment of the present invention.
  • CLKA is faster than CLKB
  • reset_S_A and reset_S_B are 0 and 1 respectively, so that S_B[9:0] (capacitive switch at the B terminal) is always equal to 10'b0 (0 represented by a 10-bit binary number), and the B All capacitors on the terminal, and S_A[9:0] (capacitance switch on the A terminal) starts counting from 10'b0 (0 represented by a 10-bit binary number).
  • the initial value of the four-bit counter is 4'b0 (0 represented by a 4-bit binary number). Since it is judged that the initial random number OUT' is biased towards outputting 0 at the beginning, the counter is added.
  • the four-bit counter is reset to 4'b0 through the reset logic, and at the same time it outputs a carry pulse to ten through the fourth output terminal J 1_ co
  • the second input terminal J 2_ E of the bit counter, the first output terminal J 2_ Q of the tens counter will add Cnt10[9:0] according to the initial random number OUT' (0) at this time, and its second
  • the output terminal J 2_ Q_n will subtract Cnt10_n[9:0], after passing through the third NOR gate NOR 3 and the fourth NOR gate NOR 4 , it will add S_A[9:0], so that the first inversion
  • the capacitance value of the output terminal of the phase unit I increases.
  • the capacitor value will continue to increase, and the delay time will also continue to increase until the phase difference between CLKA and CLKB is close, and P(0) is close to 50%. , into the NIST region.
  • the initial random number OUT' outputs 0 and 1, which will be played in the four-digit counter, and the output values of the ten-digit counter Cnt10[9:0] and Cnt10_n[9:0] will only change between one and two digits , reaching a relatively stable state.
  • Figure 6 is a schematic diagram of the effect of the true random number generator based on the on-chip digital feedback self-calibration system provided by the embodiment of the present invention, as shown in Figure 6, which shows that when the bias judgment initial random number OUT' is 0, Cnt10[9 :0] and P(1) change with time during the calibration process, where the dark line is the decimal value of Cnt10[9:0], the light line is P(1), and the value of P(1) is for each Two hundred initial random numbers OUT' output bits for statistical probability results. It can be observed from the figure that Cnt10[9:0] increases after the circuit calibration starts, and remains stable after a period of time, when the inherent delay between CLKA and CLKB has basically been corrected.
  • Fig. 7 is the structural layout of the true random number generator based on the on-chip digital feedback self-calibration system provided by the embodiment of the present invention, as shown in Fig. 7, the TRNG (true random number generator) in this scheme uses the 65nm 1.2V standard Manufactured by CMOS technology, the length and width are 112um and 23um respectively, and the overall area is about 2576um 2 . By simulating transient noise and using Monte Carlo simulation to simulate process errors, the performance of the TRNG fabricated based on the above process can be further obtained.
  • the randomness of a true random number generator is a basic requirement in secure encryption applications and a prerequisite for measuring other performances.
  • the method of evaluating the TRNG output sequence is similar to the method of evaluating the randomness of the PUF response bit, mainly including the aforementioned NIST test, autocorrelation detection and minimum entropy value H(X).
  • the enhanced random number signal OUT is used as the output sequence input for the autocorrelation detection to obtain the result of Figure 9, in the 95% confidence interval (the area between the two horizontal straight lines in Figure 9), the value of ⁇ is 0.0016 , which proves that the TRNG output sequence has no obvious correlation.
  • the output sequence contains a total of n values, and the output sequence is taken as a sample X t , the sample contains ⁇ x 1 ,x 2 ,x 3 ,...,x n ⁇ , and another sample X is taken from the output sequence t+1 , the sample contains ⁇ x 2 ,x 3 ,x 4 ...,x n ⁇ .
  • the mean values of these two groups of samples can be calculated by formula (2):
  • the estimated value of the autocorrelation coefficient is r k , and r k can be calculated by formula (3):
  • r 0 is always equal to "1”
  • r k is called the sample autocorrelation function (ACF).
  • ACF sample autocorrelation function
  • Figure 10 shows the random number speckle pattern generated by TRNG under various voltage and temperature conditions, where the black dots are high level and the white dots are low level.
  • TRNG can compensate the process deviation of the two inverting units through the calibration logic, so that the two The noise and jitter during the operation of the inverting unit are digitized, and finally output an irregular 01 sequence (enhanced random number signal OUT), which shows that the TRNG designed in this paper can resist a certain range of power supply voltage and temperature changes, and the output 01 sequence (enhanced random number signal OUT) can still guarantee better randomness.
  • the throughput rate measures the speed at which TRNG outputs random sequences per unit time, while the energy efficiency refers to the energy consumed by TRNG per output unit bit, and its size is the ratio of the overall power of TRNG to the throughput rate.
  • TRNG should also have higher throughput and lower energy efficiency as much as possible, so as to meet the high-speed data transmission requirements in low-power IoT devices.
  • Figure 11 shows the relationship between the power, energy efficiency and throughput of TRNG at normal temperature and pressure (1.2V&27°C). Among them, when the throughput rate is 488Kbps, the energy efficiency of TRNG is 1.23pJ/bit. As the throughput rate increases, the energy efficiency gradually decreases. It is worth mentioning that the highest throughput rate of TRNG reaches 250Mbps. At this time, the power of the circuit is 60.5uW, and the energy efficiency is 0.24pJ/bit.
  • Table 2 shows the performance comparison between the TRNG designed in this scheme and the TRNG design in the prior art.
  • Contrast 1 Contrast 2 Contrast 3 Contrast 4 This program Process (nm) 45 40 65 40 65 noise source Metastable oscillator oscillator diverse oscillator Working temperature (°C) none -40 ⁇ 120 none none none -40 ⁇ 120 Working voltage (V) 0.28 ⁇ 1.35 0.6 ⁇ 0.9 1.08 ⁇ 1.44 none 0.8 ⁇ 1.4 Power Consumption (mW) 7 0.046/0.005 0.289/0.418 0.528 0.06 Area (um 2 ) 4004 836 920 270 2576 Energy efficiency (pJ/bit) 2.9 23/11 35.4/43.4 0.33 0.24 Throughput rate (Mbps) 2400 2/0.45 8.2/9.9 1600 250
  • the TRNG designed in this scheme can work normally in the range of power supply voltage and temperature of 0.8 to 1.4V and -40 to 120°C, with good speed and energy efficiency performance, and reliability better.
  • the highest throughput rate of TRNG in this solution is 250Mbps, and the overall energy efficiency is 0.24pJ/bit, which is the best among the designs listed in the table.
  • the true random number generator based on the on-chip digital feedback self-calibration system provided in the embodiment of the present invention includes a noise digitization circuit, a bias judgment circuit, a self-calibration logic circuit and a post-processing circuit
  • the noise digitization circuit includes a first inverting unit , the second inverting unit, the arbiter, the first capacitor array and the second capacitor array
  • the noise digitization circuit is used to output the difference between the jitter and noise generated by the two inverter chains under the action of the input clock signal as an initial random number
  • the post-processing circuit is used to algorithmically process the initial random number to obtain an enhanced random number signal and output it
  • the bias judgment circuit is used to detect and judge the bias direction of the original random number so as to output the first bias signal and the second bias signal
  • the self-calibration logic circuit is used to calibrate the signal delays of the two inverter chains due to process errors according to the generated first bias signal and the second bias signal to obtain the first control signal and the second control signal.

Abstract

本发明公开了基于片上数字反馈自校准系统的真随机数发生器，包括噪声数字化电路、偏置判断电路、自校准逻辑电路及后处理电路，噪声数字化电路用于将两路反相器链在输入时钟信号作用下产生的抖动和噪声的差异输出为初始随机数，后处理电路用于对初始随机数进行算法处理得到增强随机数信号并输出，偏置判断电路用于对原始随机数进行检测判断偏置方向从而输出第一偏置信号及第二偏置信号，自校准逻辑电路用于根据产生的第一偏置信号及第二偏置信号对两条反相器链因工艺误差而产生的信号延迟进行校准得到第一控制信号及第二控制信号。上述的真随机数发生器，可在输入电压大范围波动及温度大范围变化的情况下依然确保高随机性，大幅提高了可靠性。

Description

基于片上数字反馈自校准系统的真随机数发生器 技术领域
本发明涉及集成电路技术领域，尤其涉及一种基于片上数字反馈自校准系统的真随机数发生器。
背景技术
随着人工智能、5G、智能语音识别和自动驾驶等新兴领域的应用进一步拓展下，物联网产业将迎来更高速的发展，深入智能办公，智能医疗，可穿戴设备，移动支付等不同领域，为我们的生活提供便利和质量保障。然而，物联网在方便人们生活的同时，也存在着被黑客攻击的风险，导致一系列的隐私问题和安全隐患，比如物理跟踪、个人特征侧写和非授权访问。在医学上的部分应用，如血压监测仪、糖尿病监测器和心脏起搏器等，被远距离侵入和篡改的后果甚至会危害生命安全。
针对这一系列问题，传统的防侵入解决方案主要有两种：基于软件加密和基于硬件加密。软件加密常用的认证协议有AES、DES和RSA，具有易维护、易实施的优点，但其安全性较低。如现有技术方法中可使用硬币大小的蓝牙设备对基于软件加密的物联网设备发送并嵌入唯一标识符，成功侵入设备，证明了攻击此类加密方式的简易性。此外，软件加密往往需要建立在操作系统上，这对物联网设备来说无疑增加了额外的成本。硬件加密通过在芯片内建立复杂的电路，将软件层的算法移植到硬件层来实现，从而减少了对操作系统的依赖。然而，基于硬件电路生成的密钥最终也要存储在非易失型存储器(Non-volatile memory,NVM)中使用，容易遭受破解泄露密钥。而且，算法本身的复杂性也导致了电路需要消耗大量的硬件资源，增加了制造成本。因此，为物联网设备提供安全可靠、低成本、低功耗的加密方案仍然是非常值得研究的技术。
物理不可克隆函数(Physically unclonable function,PUF)和真随机数发生器(True random number generator,TRNG)是近年来受到学术界广泛关注的基于硬件的物联网安全解决方案。PUF是一项基于纳米尺寸器件工艺偏差的硬件安全原语技术，为物联网设备加密问题提供了良好的解决方案。在制造工艺中，由于局部的掺杂浓度、光刻尺寸、薄膜生长厚度等无法避免的纳米尺度工艺误差，相同版图制造的晶体管在阈值电压、宽长比、等效阻抗等物理参数上是有差异。在制造完成后，芯片内部的物理特性就已经确定，PUF利用这种硬件上的物理特性生成了随机的密钥。与直接存储在NVM的密钥不同，PUF的输出取决于随机的工艺偏差，这就使得PUF的输出不会像NVM一样容易被擦除和篡改。PUF如同芯片的DNA，在芯片制造完成后输出就已经确定，并且将物理参数隐藏在芯片内部，防止泄露信息。TRNG是一项利用纳米尺寸电路中的随机物理过程来获取随机数的硬件安全原语技术，这些物理过程包括热噪声、时钟漂移、抖动、外部电磁、量子现象等。由于在纳米尺寸电路中，这种物理过程难以捕捉和预测，所以TRNG具有不可预测性。在密码学上，TRNG是对称加密、非对称加密等数据加密技术提升安全性的关键模块。数据在传输和存储过程中，用真随机数对原始数据进行处理，从而将数据承载的信息被隐藏起来，即使攻击者 窃取了数据也获取不到有用的信息。此外，在PUF实施阶段，TRNG也可被用于切断PUF激励与响应的直接关系，混淆强PUF的激励与响应之间的关系，从而抵抗机器学习攻击。
然而现有的TRNG通常仅能在稳定电压及常温下生成稳定的真随机数，若输入电压出现波动或温度发生变化，现有的TRNG所输出的真随机数的随机性会出现偏差，基于TRNG输出的真随机数进行后续加密处理的可靠性受到影响。因此现有技术方法中的真随机数发生器存在使用可靠性不足的问题。
发明内容
本发明实施例提供了一种基于片上数字反馈自校准系统的真随机数发生器，旨在解决现有技术方法中的真随机数发生器所存在的使用可靠性较差的问题。
本发明实施例提供了基于片上数字反馈自校准系统的真随机数发生器，其中，包括噪声数字化电路、偏置判断电路、自校准逻辑电路及后处理电路；
所述噪声数字化电路包括第一反相单元、第二反相单元、仲裁器、第一电容阵列及第二电容阵列；所述第一反相单元的输入端与所述第二反相单元的输入端相连接并作为信号输入端接收时钟信号；所述第一反相单元的输出端与所述仲裁器的第一输入端及所述第一电容阵列的一端相连接，所述第一电容阵列的另一端接地，所述第二反相单元的输出端与所述仲裁器的第二输入端及所述第二电容阵列的一端相连接，所述第二电容阵列的另一端接地，所述仲裁器的输出端用于输出初始随机数；所述噪声数字化电路用于将两路反相器链在输入所述时钟信号作用下产生的抖动和噪声的延迟差异输出为初始随机数；
所述后处理电路的第一输入端连接所述仲裁器的输出端、其第二输入端连接所述信号输入端、其输出端用于输出增强随机数信号；所述后处理电路用于对所述初始随机数进行算法处理得到增强随机数信号并输出；
所述偏置判断电路的第一输入端连接所述仲裁器的输出端、其第二输入端连接初始化信号输入端、其第一偏置输出端用于输出第一偏置信号、其第二偏置输出端用于输出第二偏置信号，所述偏置判断电路的第二输入端用于输入初始化信号；所述偏置判断电路用于对原始随机数进行检测判断偏置方向从而输出第一偏置信号及第二偏置信号；
所述自校准逻辑电路的第一输入端及第二输入端均连接所述仲裁器的输出端、其第三输入端连接所述信号输入端、其第四信号输入端连接所述第二偏置输出端、其第五信号输入端连接所述第一偏置信号输出端；其第一控制输出端连接所述第一电容阵列的控制开关，通过输出第一控制信号控制接入所述第一反相单元的电容以补偿所述第一反相单元的额外延迟时间，其第二控制输出端连接所述第二电容阵列的控制开关，通过输出第二控制信号控制接入所述第二反相单元的电容以补偿所述第二反相单元的额外延迟时间，从而将所述第一反相单元及所述第二反相单元因工艺误差造成的延迟时间补偿至相等；所述自校准逻辑电路用于根据时钟信号及初始随机数对所述第一偏置信号及所述第二偏置信号进行校准得到第一控制信号及第二控制信号。
所述的基于片上数字反馈自校准系统的真随机数发生器，其中，所述第一 反相单元及所述第二反相单元均由多个反相器进行串联组成。
所述的基于片上数字反馈自校准系统的真随机数发生器，其中，所述第一电容阵列及所述第二电容阵列均由数量相等的多个电容对组成，且所述第一电容阵列或所述第二电容阵列包含的电容对所对应的延迟时间依次成倍数增长。
所述的基于片上数字反馈自校准系统的真随机数发生器，其中，所述电容对均包含一个一端通过第一控制开关与所述第一反相单元的输出端相连接、另一端接地的第一电容，以及一个一端通过第二控制开关与所述第二反相单元的输出端相连接、另一端接地的第二电容；
所述第一电容阵列的每一电容对中的第一电容尺寸依次增加，每一电容对中第二电容的尺寸均相等；
所述第二电容阵列的每一电容对中第一电容的尺寸均相等，每一电容对中第二电容的尺寸依次增加。
所述的基于片上数字反馈自校准系统的真随机数发生器，其中，所述第一电容阵列的每一电容对中的第一控制开关及第二控制开关均与所述第一控制输出端相连接，以接收所述第一控制输出端输入的第一控制信号并对所述第一电容阵列中每一电容对分别进行通断控制，从而控制所述第一电容阵列对所述第一反相单元及所述第二反相单元的额外延迟时间的补偿时长；
所述第二电容阵列的每一电容对中的第一控制开关及第二控制开关均与所述第二控制输出端相连接，以接收所述第二控制输出端输入的第二控制信号并对所述第二电容阵列中每一电容对分别进行通断控制，从而控制所述第二电容阵列对所述第一反相单元及所述第二反相单元的额外延迟时间的补偿时长。
所述的基于片上数字反馈自校准系统的真随机数发生器，其中，所述电容对中的电容均为NMOS晶体管的栅极电容。
所述的基于片上数字反馈自校准系统的真随机数发生器，其中，所述噪声数字化电路、所述偏置判断电路、所述自校准逻辑电路及所述后处理电路均采用互补型金属氧化物半导体工艺制作得到。
所述的基于片上数字反馈自校准系统的真随机数发生器，其中，所述偏置判断电路包括触发器、第一或非门及第二或非门；
所述触发器的第一输入端连接所述仲裁器的输出端、其第二输入端连接所述初始化信号输入端、其第一输出端连接所述第一或非门的第一输入端、其第二输出端连接所述第二或非门的第二输入端；
所述第一或非门的第二输入端与所述第二或非门的第一输入端相连接用于输入重置信号；所述第一或非门的输出端作为所述偏置判断电路的第一偏置输出端输出第一偏置信号，所述第二或非门的输出端作为所述偏置判断电路的第二偏置输出端输出第二偏置信号。
所述的基于片上数字反馈自校准系统的真随机数发生器，其中，所述自校准逻辑电路包括第一加减计数器、第二加减计数器、复位逻辑器、第三或非门及第四或非门；
所述第一加减计数器的第一输入端连接所述仲裁器的输出端、其第二输入 端连接所述信号输入端、其第三输入端与第一输出端之间串联设置所述复位逻辑器、其第四输出端连接所述第二加减计数器的第二输入端；
所述第二加减计数器的第一输入端连接所述仲裁器的输出端、其第一输出端连接所述第三或非门的第二输入端、其第二输出端连接所述第四或非门的第一输入端；
所述第三或非门的第一输入端连接所述第二偏置输出端、输出端连接所述第一电容阵列；
所述第四或非门的第二输入端连接所述第一偏置输出端、输出端连接所述第二电容阵列。
所述的基于片上数字反馈自校准系统的真随机数发生器，其中，所述第一加减计数器为四位加减计数器，所述第二加减计数器为十位加减计数器。
本发明实施例提供了一种基于片上数字反馈自校准系统的真随机数发生器，包括噪声数字化电路、偏置判断电路、自校准逻辑电路及后处理电路，噪声数字化电路包括第一反相单元、第二反相单元、仲裁器、第一电容阵列及第二电容阵列，噪声数字化电路用于将两路反相器链在输入时钟信号作用下产生的抖动和噪声的差异输出为初始随机数，后处理电路用于对初始随机数进行算法处理得到增强随机数信号并输出，偏置判断电路用于对原始随机数进行检测判断偏置方向从而输出第一偏置信号及第二偏置信号，自校准逻辑电路用于根据产生的第一偏置信号及第二偏置信号对两条反相器链因工艺误差而产生的信号延迟进行校准得到第一控制信号及第二控制信号。上述的真随机数发生器，可在输入电压大范围波动及温度大范围变化的情况下依然确保高随机性，大幅提高了使用可靠性。
附图说明
为了更清楚地说明本发明实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的整体电路结构图；
图2为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的局部电路结构图；
图3为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的局部电路结构图；
图4为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的效果示意图；
图5为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的效果示意图；
图6为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的效果示意图；
图7为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的结构版图；
图8为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的自校准逻辑流程图；
图9为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的效果示意图；
图10为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的效果示意图；
图11为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的效果示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
应当理解，当在本说明书和所附权利要求书中使用时，术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在本发明说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本发明。如在本发明说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
还应当进一步理解，在本发明说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
请参阅图1及图3，图1为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的整体电路结构图；图2为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的局部电路结构图；图3为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的局部电路结构图。如图所示，一种基于片上数字反馈自校准系统的真随机数发生器，包括噪声数字化电路11、偏置判断电路12、自校准逻辑电路13及后处理电路H 0。
所述噪声数字化电路11包括第一反相单元I、第二反相单元I’、仲裁器Z 0、第一电容阵列CM 1及第二电容阵列CM 2；所述第一反相单元I的输入端与所述第二反相单元I’的输入端相连接并作为信号输入端接收时钟信号CLK，时钟信号即为一定频率的方形波信号，其波形如图2左侧所示波信号，所述第一反相单元I的输出端与所述仲裁器Z 0的第一输入端及所述第一电容阵列CM 1的一端相连接，所述第一电容阵列CM 1的另一端接地，所述第二反相单元I’的输出端与所述仲裁器Z 0的第二输入端及所述第二电容阵列CM 2的一端相连接，所述第二电 容阵列CM 2的另一端接地，所述仲裁器Z 0的输出端用于输出初始随机数OUT’；所述噪声数字化电路用于将两路反相器链在输入所述时钟信号CLK作用下产生的抖动和噪声的延迟差异输出为初始随机数OUT’，第一反相单元I及第二反相单元I’即分别对应上述的两条反相器链。
具体的，噪声数字化电路11的基础结构如图2所示，第一反相单元I即可接收一路震荡噪声，第二反相单元I’可接收另一路震荡噪声，经过若干级反相器振荡后，第一反相单元I及第二反相单元I’的末端将会得到积累了反相器振荡噪声的两个时钟信号CLKA和CLKB，并且将所得到的两个时钟信号CLKA和CLKB分别输入至仲裁器Z 0的两个输入端，仲裁器Z 0的作用是根据CLKA和CLKB每一次上升沿来的先后顺序来输出高电平或低电平。
图4为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的效果示意图，图4是基于图2的噪声数字化电路11中CLKA和CLKB在噪声影响下仿真的1000组延迟差异统计分布图，其中延迟时间单位为皮秒(ps)，拟合的曲线符合高斯分布，此高斯分布可采用公式(1)进行表示；
Delay noise～N(μ,σ 2)           (1)；
其中，μ为0.01ps(理想情况下应为0ps)，σ为7.74ps。在不考虑工艺误差的理想情况下，某个CLK周期下当Delay noise小于0时，意味着在噪声作用下，CLKA的上升沿比CLKB先到达仲裁器Z 0，仲裁器Z 0输出的初始随机数OUT’为低电平信号，反之为初始随机数OUT’为高电平信号。此时，OUT’输出为0的概率P(0)将接近50％，并且在NIST区域内(图4中虚线框内)符合随机数的要求(±0.24σ)。
在更具体的实施例中，所述第一反相单元I及所述第二反相单元I’均由多个反相器进行串联组成，如图2所示，第一反相单元I由反相器I 1、反相器I 2、…及反相器I n串联组成，反相器I 1的输入端即作为第一反相单元I的输入端，反相器I n的输出端即作为第一反相单元I的输出端，同样地，第二反相单元I’由反相器I’ 1、反相器I’ 2、…及反相器I’ n串联组成，第一反相单元I及第二反相单元I’的所包含反相器的数量相等，如本案具体实施例中第一反相单元I及第二反相单元I’所包含的反相器的数量均为n。
具体的，所述第一电容阵列CM 1及所述第二电容阵列CM 2均由数量相等的多个电容对组成，且所述第一电容阵列CM 1或所述第二电容阵列CM 2包含的电容对所对应的延迟时间依次成倍数增长。其中，所述电容对均包含一个一端通过第一控制开关与所述第一反相单元I的输出端相连接、另一端接地的第一电容，以及一个一端通过第二控制开关与所述第二反相单元I’的输出端相连接、另一端接地的第二电容，如图3所示，第一电容阵列CM 1包含十个电容对，每一电容对均包含两个电容，如第一电容对由第一电容CA 0和第二电容CA’ 0组成，第一电容CA 0的一端通过第一控制开关K与所述第一反相单元I的输出端(A端)相连接、另一端接地，第二电容CA’ 0的一端通过第一控制开关K’与所述第二反相单元I’的输出端(B端)相连接、另一端接地。所述第一电容阵列CM 1的每一电容对中的第一电容CA 0尺寸依次增加，每一电容对中第二电容CA’ 0的尺寸 均相等；所述第二电容阵列CM 2的每一电容对中第一电容CA 0的尺寸均相等，每一电容对中第二电容CA’ 0的尺寸依次增加。
在更具体的实施例中，所述第一电容阵列CM 1的每一电容对中的第一控制开关K及第二控制开关K’均与所述第一控制输出端相连接，以接收所述第一控制输出端输入的第一控制信号S_A[9:0](其中包含十个子信号)并对所述第一电容阵列CM 1中每一电容对分别进行通断控制，从而控制所述第一电容阵列CM 1对所述第一反相单元I及所述第二反相单元I’的额外延迟时间的补偿时长，第一电容阵列CM 1中每一电容对的第一控制开关及第二控制开关即组成为第一电容阵列的控制开关；所述第二电容阵列CM 2的每一电容对中的第一控制开关K及第二控制开关K’均与所述第二控制输出端相连接，以接收所述第二控制输出端输入的第二控制信号S_B[9:0](其中包含十个子信号)并对所述第二电容阵列CM 2中每一电容对分别进行通断控制，从而控制所述第二电容阵列CM 2对所述第一反相单元I及所述第二反相单元I’的额外延迟时间的补偿时长，第二电容阵列CM 2中每一电容对的第一控制开关及第二控制开关即组成为第一电容阵列的控制开关。具体的，所述电容对中的电容均为NMOS晶体管的栅极电容。其中，所述噪声数字化电路11、所述偏置判断电路12、所述自校准逻辑电路13及所述后处理电路H 0均采用互补型金属氧化物半导体工艺制作得到，从而实现与其他采用互补型金属氧化物半导体工艺制作的电路元器件进行兼容，在更具体的实施例中，可采用65nm、1.2V低漏电工艺(low leakage)互补型金属氧化物半导体工艺(CMOS工艺)制作得到本方案中涉及的各电路单元。
对于65nm的互补型金属氧化物半导体工艺(UMC65工艺)，制作得到最小的栅极电容(晶体管)尺寸为W/L＝80nm/60nm(宽度为80nm，长度为60nm)，电容的尺寸即决定了延迟时间，电容尺寸越大则延迟时间越长。若使用电容直接作为最小的延迟单元，通过二进制数控制电容阵列的精度约为82ps/bit，这一精度较低，难以实现精确地将输出的电平信号控制在NIST区域内的目的。本方案中采用了一种补偿式的电容阵列设计，图4所示即为第一电容阵列CM 1(第二电容阵列CM 2与第一电容阵列CM 1对称设计)，在给第一反相单元I的输出端增加电容时，同时在第二反相单元I’的输出端补偿一个更小的电容，则第一控制信号S_A[9:0]中的每一个子信号可同时控制一个电容对的通断，也即是一个电容对中包含的两个电容同时接入电路或同时断开，则最终每一电容对所增加的电容精度为该电容对中所包含的两个电容的差值，电容值越大则所补偿的额外延迟时间也越长，则第一电容阵列CM 1中的每一电容对在第一反相单元I的输出端所补偿的额外延迟时间，即为电容对对第一反相单元及第二反相单元的额外延迟时间的补偿时长的差值，则第二电容阵列CM 2中的每一电容对在第二反相单元I的输出端所补偿的额外延迟时间，即为电容对对第一反相单元及第二反相单元的额外延迟时间的补偿时长的差值。
本设计为满足反相器延迟链的误差需求，设计了十位二进制电容阵列，也即是第一电容阵列CM 1及第二电容阵列CM 2均包含十个电容对，以为第一电容阵列CM 1例，其所包含的十个主延迟晶体管(图4中第一排电容)的栅极宽(W值) 依次为90nm、100nm、120nm、160nm、240nm、400nm、720nm、1360nm、2640和5200nm，长度均为60nm，其所包含的十个延迟补偿晶体管(图4中第二排电容)的栅极宽均为80(单位均为nm)，长度均为60nm，则图4中第一个电容对可补偿至第一反相单元I的输出端的额外延迟时间即与两个电容的栅极宽差90-80＝10nm相对应，第二电容对可补偿至第一反相单元I的输出端的额外延迟时间即与两个电容的栅极宽差100-80＝20nm相对应，第三电容对可补偿至第一反相单元I的输出端的额外延迟时间即与两个电容的栅极宽差120-80＝40nm相对应，以此类推。第二电容阵列CM 2中电容的设计尺寸与第一电容阵列CM 1相对称，也即是第二电容阵列CM 2中第一排电容为十个延迟补偿晶体管(尺寸均相同)，第二排电容为十个主延迟晶体管(尺寸依次增加)。
图5为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的效果示意图，在S_A[9:0](其中10个子信号按顺序组合即可表示成10位二进制数)从0计数到1023的过程中，其作用下的CLKA和CLKB延迟变化如图5所示，由图中可知第一电容阵列CM 1的晶体管电容带来延迟时间的增长基本随S_A[9:0]数值的增长线性增加，且斜率约为0.9ps/bit，这一精度大大优于传统技术方法中的82ps/bit。
所述后处理电路H 0的第一输入端连接所述仲裁器Z 0的输出端、其第二输入端连接所述信号输入端、其输出端用于输出增强随机数信号OUT；则初始随机数OUT’由第一输入端输入至后处理电路H 0，时钟信号CLK由第二输入端输入至后处理电路H 0，所述后处理电路H 0用于对所述初始随机数OUT’进行算法处理得到增强随机数信号OUT并输出。其中，后处理电路H 0可以是由八个异或门进行串联连接所组成的八级异或链。
所述偏置判断电路12的第一输入端连接所述仲裁器Z 0的输出端、其第二输入端连接初始化信号输入端、其第一偏置输出端用于输出第一偏置信号reset_S_A、其第二偏置输出端用于输出第二偏置信号reset_S_B，所述偏置判断电路12的第二输入端用于输入初始化信号CLK_I；所述偏置判断电路用于对原始随机数OUT’进行检测判断偏置方向从而输出第一偏置信号reset_S_A及第二偏置信号reset_S_B。
在更具体的实施例中，所述偏置判断电路12包括触发器Cf、第一或非门NOR 1及第二或非门NOR 2；所述触发器Cf的第一输入端Cf_D连接所述仲裁器Z 0的输出端、其第二输入端Cf_E连接所述初始化信号输入端、其第一输出端Cf_Q连接所述第一或非门NOR 1的第一输入端、其第二输出端Cf_Q_n连接所述第二或非门NOR 2的第二输入端；所述第一或非门的第二输入端与所述第二或非门的第一输入端相连接用于输入重置信号R；所述第一或非门NOR 1的输出端作为所述偏置判断电路12的第一偏置输出端输出第一偏置信号reset_S_A，所述第二或非门NOR 2的输出端作为所述偏置判断电路12的第二偏置输出端输出第二偏置信号reset_S_B。其中，触发器Cf的第二输入端Cf_E用于输入初始化信号CLK_I，初始化信号CLK_I可作为触发器Cf的开关信号，初始化信号CLK_I在触发器Cf开始工作时置于高电平并一直保持。
偏置判断电路12的作用是判断在第一反相单元I及第二反相单元I’末端未加电容情况下CLKA和CLKB上升沿先后顺序，以此来决定通过第一电容阵列CM 1及第二电容阵列CM 2中电容接通的具体位置(在上升沿来得更快的反相单元的一端增加电容，从而增加延迟时间)，从而让CLKA和CLKB上升沿到来的时间更接近。
所述自校准逻辑电路13的第一输入端及第二输入端均连接所述仲裁器Z 0的输出端、其第三输入端连接所述信号输入端、其第四信号输入端连接所述第二偏置输出端、其第五信号输入端连接所述第一偏置信号输出端；其第一控制输出端连接所述第一电容阵列CM 1以输出第一控制信号S_A[9:0]控制第一电容阵列CM 1的延迟时间，其第二控制输出端连接所述第二电容阵列CM 2以输出第二控制信号S_B[9:0]控制第二电容阵列CM 2的延迟时间；所述自校准逻辑电路13用于根据时钟信号CLK及初始随机数OUT’对所述第一偏置信号reset_S_A及所述第二偏置信号reset_S_B进行校准得到第一控制信号S_A[9:0]及第二控制信号S_B[9:0]。其中，第一控制信号S_A[9:0]及第二控制信号S_B[9:0]均由十个子信号组成，每一子信号可采用“0”或“1”进行表示，则10个子信号按顺序组合即可表示成10位二进制数，10位二进制数的数值范围为[0，1023]。
在更具体的实施例中，所述自校准逻辑电路13包括第一加减计数器J 1、第二加减计数器J 2、复位逻辑器F、第三或非门NOR 3及第四或非门NOR 4；所述第一加减计数器J 1的第一输入端J 1_a/s连接所述仲裁器Z 0的输出端、其第二输入端J 1_E连接所述信号输入端、其第三输入端J 1_reset与第一输出端J 1_T之间串联设置所述复位逻辑器F、其第四输出端J 1_co连接所述第二加减计数器J 2的第二输入端J 2_E；所述第二加减计数器J 2的第一输入端J 2_a/s连接所述仲裁器Z 0的输出端、其第一输出端J 2_Q连接所述第三或非门NOR 3的第二输入端、其第二输出端J 2_Q_n连接所述第四或非门NOR 4的第一输入端；所述第三或非门NOR 3的第一输入端连接所述第二偏置输出端、输出端连接所述第一电容阵列CM 1；所述第四或非门NOR 4的第二输入端连接所述第一偏置输出端、输出端连接所述第二电容阵列CM 2。其中，所述第一加减计数器J 1为四位加减计数器，所述第二加减计数器J 2为十位加减计数器。
具体的，将图1中的R信号置1，此时第一偏置信号reset_S_A和第二偏置信号reset_S_B均为1，再经过第一或非门NOR 1及第二或非门NOR 2后，第一控制信号S_A[9:0]及第二控制信号S_B[9:0]均被置为低电平(数值均为0)，进而断开了第一电容阵列CM 1及第二电容阵列CM 2中所包含的所有电容。然后，输入方波CLK，若初始随机数OUT’为低电平，则表明CLKA快于CLKB，应当在第一反相单元I的输出端增加电容，反之则在第二反相单元I’的输出端增加电容。通过触发器Cf的一个上升沿，初始随机数OUT’将会被保存在触发器Cf内。最后，使R信号置0，就能通过第一偏置信号reset_S_A和第二偏置信号reset_S_B选择关闭第一电容阵列CM 1的输出端或第二电容阵列CM 2的输出端中某一端的全部电容。
自校准逻辑电路13包含两个加减计数器组成，第一加减计数器的位数为四 位，第二加减计数器的位数为十位。四位加减计数器输出Cnt4[3:0]的作用是统计初始随机数OUT’输出0和1的偏置情况，而十位加减计数器输出的Cnt10[9:0]及Cnt10_n[9:0]，在分别与reset_S_A及reset_S_B进行或非逻辑运算后，可以得到控制电容阵列的第一控制信号S_A[9:0]和第二控制信号S_B[9:0]。图8为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的自校准逻辑流程图，如图8所示，在偏置判断电路12完成判断后，假设CLKA快于CLKB，则初始随机数OUT’为0，reset_S_A和reset_S_B分别为0、1，使S_B[9:0](B端电容开关)恒等于10’b0(10位二进制数表示的0)，关闭了B端所有的电容，而S_A[9:0](A端电容开关)从10’b0(10位二进制数表示的0)开始计数。四位计数器起始值为4’b0(4位二进制数表示的0)，由于开始时判断了初始随机数OUT’是偏向输出0，计数器做加法。当四位计数器的值为4’b1000(4位二进制数表示的1000)时，通过复位逻辑将四位计数器复位为4’b0，同时其通过第四输出端J 1_co输出一个进位脉冲给十位计数器的第二输入端J 2_E，十位计数器的第一输出端J 2_Q将根据此时的初始随机数OUT’(为0)对Cnt10[9:0]做加法，而其第二输出端J 2_Q_n将对Cnt10_n[9:0]做减法，经过第三或非门NOR 3及第四或非门NOR 4后，将对S_A[9:0]做加法，从而使第一反相单元I的输出端电容值增加。只要初始随机数OUT’的输出偏向于0，这个过程将一直持续，电容值将一直增加，延迟时间也将一直增加，直到CLKA和CLKB两者的相位相差接近，P(0)很接近50％，进入NIST区域。此时初始随机数OUT’输出0、1将在四位计数器里进行博弈，而十位计数器的输出值Cnt10[9:0]及Cnt10_n[9:0]也只在一两位之间进行变化，达到相对稳定状态。另外，若CLKB快于CLKA，则初始随机数OUT’为1，偏置判断阶段将使reset_S_A和reset_S_B分别为1、0，关闭第一反相单元I的输出端的所有电容，此时，由于Cnt10[9:0]初始化为10’b0，与reset_S_B或非后将得到S_B[9:0]为10’d1023，即第二反相单元I’的输出端的电容全部打开。原本CLKB快于CLKA的状态将在这些电容的作用下使得CLKA快于CLKB，初始随机数OUT’还是输出0，十位计数器的第一输出端J 2_Q对cnt10[9:0]做加法，经过或非门后得到的S_B[9:0]将做减法，使B端电容减小，直到P(0)趋近于50％。
图6为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的效果示意图，如图6所示，其中展示了偏置判断初始随机数OUT’为0时，Cnt10[9:0]和P(1)在校准过程中随时间变化情况，其中深色线为Cnt10[9:0]的十进制值，浅色线为P(1)，P(1)的值是对每两百个初始随机数OUT’输出比特进行统计的概率结果。从图中可以观察到，Cnt10[9:0]在电路校准开始后增加，经过一段时间后能保持稳定，此时CLKA和CLKB之间的固有延迟基本已经被校正。从图中可以看到，P(1)偶尔会偏移NIST区域(两条横向虚线的中间区域)，主要原因有两个：第一、每次统计的数据总量较少，仅200bits；第二、电路中一些非随机因素影响了初始随机数OUT’输出。因此，在初始随机数OUT’的基础上，使用后处理电路H 0(八级异或链)对其进行后处理，使输出的0、1值更加均匀，并减少非随机因素的影响，得到最终输出增强随机数信号OUT。
图7为本发明实施例提供的基于片上数字反馈自校准系统的真随机数发生器的结构版图，如图7所示，本方案中的TRNG(真随机数发生器)使用65nm 1.2V标准的CMOS工艺进行制作得到，长和宽分别为112um、23um，整体面积约为2576um 2。通过模拟瞬态噪声，并且使用蒙特卡洛仿真模拟工艺误差，可进一步获取基于上述工艺制作得到的TRNG的性能。
真随机数发生器(TRNG)的随机性是其在安全加密应用中的基本要求，是衡量其他性能的前提。评估TRNG输出序列与评估PUF响应位随机性的方法类似，主要包括前面提到的NIST测试、自相关检测和最小熵值H(X)。在VDD＝1.2V&T＝27℃下，通过蒙特卡洛仿真得到了500Kbits的连续序列，并使用NIST Pub 800套件来评估其随机性，结果如表1所示。从表中可以看出，所有项目的P值均大于0.01，并且全部项目通过了NIST测试，证明了该TRNG在常温常压下输出序列的随机性是符合要求的。
测试名称 单次序列长度 运行次数 置信度(P) 结果
Frequency 50kb 10 0.834308 通过
BlockFrequency 50kb 10 0.534146 通过
CumulativeSums 50kb 10 0.312541 通过
Runs 50kb 10 0.534146 通过
LongestRun 50kb 10 0.275709 通过
Rank 50kb 10 0.437274 通过
FFT 50kb 10 0.275709 通过
NonOverlappingTemplate 50kb 10 0.439032 通过
OverlappingTemplate 50kb 10 0.275709 通过
ApproximateEntropy 50kb 10 0.437274 通过
Serial 50kb 10 0.442315 通过
LinearComplexity 50kb 10 0.437274 通过
表1
此外，将该增强随机数信号OUT作为输出序列输入用于自相关检测中得到图9的结果，在95％的置信区间(图9中两条横向直线之间的区域)，σ的值为0.0016，证明TRNG输出序列并无明显相关性。具体的，输出序列中共包含n个数值，取输出序列作为样本X t，该样本包含{x 1,x 2,x 3,...,x n}，从该输出序列中取另一样本X t+1，该样本包含{x 2,x 3,x 4...,x n}。在平稳性条件下，这两组样本的均值均可采用公式(2)计算得到：
Figure PCTCN2022095919-appb-000001
则X t与X t+k的自相关系数即为＝自协方差/k＝0时的自协方差，分母也等于X t的方差。自相关系数的估计值为r k，r k可采用公式(3)计算得到：
Figure PCTCN2022095919-appb-000002
其中，r 0永远等于“1”，r k称为样本自相关函数(ACF)。对于样本x t与x t+k之间的自相关系数，可将k从0到n的自相关系数r k求出，所得到的计算值即 为图9中的纵坐标值，k值两组样本之间的间隔值，也即是图9中横坐标值lag。
同时，通过测试证明，上述技术方案中的TRNG能够在电源电压0.8至1.4V&温度范围-40至120℃的工作条件下正常工作。我们通过每0.2V取一个电源电压(即VDD＝0.8V、VDD＝1.0V、VDD＝1.2V和VDD＝1.4V)、每40℃取一个温度点(即T＝-40℃、T＝0℃、T＝40℃、T＝80℃和T＝120℃)组合成20种工作条件进行仿真，每个条件下获得10Kbits的01序列，分别用于NIST Pub 800套件进行随机性检测，最终均通过检测。图10展示了TRNG在各个电压和温度条件下生成随机数散斑图，其中黑色斑点为高电平，白色斑点为低电平。从图10中可以看到，在电源电压范围VDD为0.8-1.4V&温度范围为-40-120℃的条件下，TRNG能通过校准逻辑来补偿两个反相单元的工艺偏差，从而将两个反相单元运行过程中的噪声和抖动数字化，最终输出无规律的01序列(增强随机数信号OUT)，这说明了本文设计的TRNG能够抵抗一定范围的电源电压和温度变化，并且输出的01序列(增强随机数信号OUT)仍能保证较好的随机性。
吞吐率衡量了单位时间内TRNG输出随机序列的速度，而能效则是TRNG每输出单位bit消耗的能量,它的大小为TRNG的整体功率与吞吐率的比值。在随机性达到要求的情况下，TRNG还应尽可能地有更高的吞吐率和更低的能效，从而满足低功耗物联网设备中高速的数据传输要求。图11中给出了在常温常压下(1.2V&27℃)下，TRNG的功率、能效与吞吐率之间的变化关系。其中，在吞吐率为488Kbps时，TRNG的能效为1.23pJ/bit。随着吞吐率的升高，能效逐渐降低。值得一提的是，TRNG的最高吞吐率达到250Mbps，此时电路的功率为60.5uW，能效为0.24pJ/bit。
表2为本方案设计的TRNG与现有技术中的TRNG设计的性能对比。
  对比1 对比2 对比3 对比4 本方案
工艺(nm) 45 40 65 40 65
噪声源 亚稳态 振荡器 振荡器 多样 振荡器
工作温度(℃) 无 -40～120 无 无 -40～120
工作电压(V) 0.28～1.35 0.6～0.9 1.08～1.44 无 0.8～1.4
功耗(mW) 7 0.046/0.005 0.289/0.418 0.528 0.06
面积(um 2) 4004 836 920 270 2576
能效(pJ/bit) 2.9 23/11 35.4/43.4 0.33 0.24
吞吐速率(Mbps) 2400 2/0.45 8.2/9.9 1600 250
表2
从表2数据的中可以看到，本方案设计的TRNG可以在电源电压和温度分别为0.8至1.4V、-40至120℃的范围内正常工作，具有良好的速度和能效表现，且可靠性更佳。且本方案TRNG的最高吞吐率大小为250Mbps，总体能效为0.24pJ/bit,能效在表中列出的各个设计中表现最好。
在本发明实施例所提供的基于片上数字反馈自校准系统的真随机数发生器，包括噪声数字化电路、偏置判断电路、自校准逻辑电路及后处理电路，噪声数字化电路包括第一反相单元、第二反相单元、仲裁器、第一电容阵列及第二电 容阵列，噪声数字化电路用于将两路反相器链在输入时钟信号作用下产生的抖动和噪声的差异输出为初始随机数，后处理电路用于对初始随机数进行算法处理得到增强随机数信号并输出，偏置判断电路用于对原始随机数进行检测判断偏置方向从而输出第一偏置信号及第二偏置信号，自校准逻辑电路用于根据产生的第一偏置信号及第二偏置信号对两条反相器链因工艺误差而产生的信号延迟进行校准得到第一控制信号及第二控制信号。上述的真随机数发生器，可在输入电压大范围波动及温度大范围变化的情况下依然确保高随机性，大幅提高了使用可靠性。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

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  1. 一种基于片上数字反馈自校准系统的真随机数发生器，其特征在于，包括噪声数字化电路、偏置判断电路、自校准逻辑电路及后处理电路；
    所述噪声数字化电路包括第一反相单元、第二反相单元、仲裁器、第一电容阵列及第二电容阵列；所述第一反相单元的输入端与所述第二反相单元的输入端相连接并作为信号输入端接收时钟信号；所述第一反相单元的输出端与所述仲裁器的第一输入端及所述第一电容阵列的一端相连接，所述第一电容阵列的另一端接地，所述第二反相单元的输出端与所述仲裁器的第二输入端及所述第二电容阵列的一端相连接，所述第二电容阵列的另一端接地，所述仲裁器的输出端用于输出初始随机数；所述噪声数字化电路用于将两路反相器链在输入所述时钟信号作用下产生的抖动和噪声的延迟差异输出为初始随机数；
    所述后处理电路的第一输入端连接所述仲裁器的输出端、其第二输入端连接所述信号输入端、其输出端用于输出增强随机数信号；所述后处理电路用于对所述初始随机数进行算法处理得到增强随机数信号并输出；
    所述偏置判断电路的第一输入端连接所述仲裁器的输出端、其第二输入端连接初始化信号输入端、其第一偏置输出端用于输出第一偏置信号、其第二偏置输出端用于输出第二偏置信号，所述偏置判断电路的第二输入端用于输入初始化信号；所述偏置判断电路用于对原始随机数进行检测判断偏置方向从而输出第一偏置信号及第二偏置信号；
    所述自校准逻辑电路的第一输入端及第二输入端均连接所述仲裁器的输出端、其第三输入端连接所述信号输入端、其第四信号输入端连接所述第二偏置输出端、其第五信号输入端连接所述第一偏置信号输出端；其第一控制输出端连接所述第一电容阵列的控制开关，通过输出第一控制信号控制接入所述第一反相单元的电容以补偿所述第一反相单元的额外延迟时间，其第二控制输出端连接所述第二电容阵列的控制开关，通过输出第二控制信号控制接入所述第二反相单元的电容以补偿所述第二反相单元的额外延迟时间，从而将所述第一反相单元及所述第二反相单元因工艺误差造成的延迟时间补偿至相等；所述自校准逻辑电路用于根据时钟信号及初始随机数对所述第一偏置信号及所述第二偏置信号进行校准得到第一控制信号及第二控制信号。
  2. 根据权利要求1所述的基于片上数字反馈自校准系统的真随机数发生器，其特征在于，所述第一反相单元及所述第二反相单元均由多个反相器进行串联组成。
  3. 根据权利要求1所述的基于片上数字反馈自校准系统的真随机数发生器，其特征在于，所述第一电容阵列及所述第二电容阵列均由数量相等的多个电容对组成，且所述第一电容阵列或所述第二电容阵列包含的电容对所对应的延迟时间依次成倍数增长。
  4. 根据权利要求3所述的基于片上数字反馈自校准系统的真随机数发生器，其特征在于，所述电容对均包含一个一端通过第一控制开关与所述第一反相单元的输出端相连接、另一端接地的第一电容，以及一个一端通过第二控制开关与所述第二反相单元的输出端相连接、另一端接地的第二电容；
    所述第一电容阵列的每一电容对中的第一电容尺寸依次增加，每一电容对中第二电容的尺寸均相等；
    所述第二电容阵列的每一电容对中第一电容的尺寸均相等，每一电容对中第二电容的尺寸依次增加。
  5. 根据权利要求4所述的基于片上数字反馈自校准系统的真随机数发生器，其特征在于，所述第一电容阵列的每一电容对中的第一控制开关及第二控制开关均与所述第一控制输出端相连接，以接收所述第一控制输出端输入的第一控制信号并对所述第一电容阵列中每一电容对分别进行通断控制，从而控制所述第一电容阵列对所述第一反相单元及所述第二反相单元的额外延迟时间的补偿时长；
    所述第二电容阵列的每一电容对中的第一控制开关及第二控制开关均与所述第二控制输出端相连接，以接收所述第二控制输出端输入的第二控制信号并对所述第二电容阵列中每一电容对分别进行通断控制，从而控制所述第二电容阵列对所述第一反相单元及所述第二反相单元的额外延迟时间的补偿时长。
  6. 根据权利要求3或4所述的基于片上数字反馈自校准系统的真随机数发生器，其特征在于，所述电容对中的电容均为NMOS晶体管的栅极电容。
  7. 根据权利要求6所述的基于片上数字反馈自校准系统的真随机数发生器，其特征在于，所述噪声数字化电路、所述偏置判断电路、所述自校准逻辑电路及所述后处理电路均采用互补型金属氧化物半导体工艺制作得到。
  8. 根据权利要求1所述的基于片上数字反馈自校准系统的真随机数发生器，其特征在于，所述偏置判断电路包括触发器、第一或非门及第二或非门；
    所述触发器的第一输入端连接所述仲裁器的输出端、其第二输入端连接所述初始化信号输入端、其第一输出端连接所述第一或非门的第一输入端、其第二输出端连接所述第二或非门的第二输入端；
    所述第一或非门的第二输入端与所述第二或非门的第一输入端相连接用于输入重置信号；所述第一或非门的输出端作为所述偏置判断电路的第一偏置输出端输出第一偏置信号，所述第二或非门的输出端作为所述偏置判断电路的第二偏置输出端输出第二偏置信号。
  9. 根据权利要求1所述的基于片上数字反馈自校准系统的真随机数发生器，其特征在于，所述自校准逻辑电路包括第一加减计数器、第二加减计数器、复位逻辑器、第三或非门及第四或非门；
    所述第一加减计数器的第一输入端连接所述仲裁器的输出端、其第二输入端连接所述信号输入端、其第三输入端与第一输出端之间串联设置所述复位逻辑器、其第四输出端连接所述第二加减计数器的第二输入端；
    所述第二加减计数器的第一输入端连接所述仲裁器的输出端、其第一输出端连接所述第三或非门的第二输入端、其第二输出端连接所述第四或非门的第一输入端；
    所述第三或非门的第一输入端连接所述第二偏置输出端、输出端连接所述第一电容阵列；
    所述第四或非门的第二输入端连接所述第一偏置输出端、输出端连接所述第二电容阵列。
  10. 根据权利要求9所述的基于片上数字反馈自校准系统的真随机数发生器，其特征在于，所述第一加减计数器为四位加减计数器，所述第二加减计数器为十位加减计数器。
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