WO2023035370A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023035370A1
WO2023035370A1 PCT/CN2021/125733 CN2021125733W WO2023035370A1 WO 2023035370 A1 WO2023035370 A1 WO 2023035370A1 CN 2021125733 W CN2021125733 W CN 2021125733W WO 2023035370 A1 WO2023035370 A1 WO 2023035370A1
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WO
WIPO (PCT)
Prior art keywords
pixels
data line
column
columns
main data
Prior art date
Application number
PCT/CN2021/125733
Other languages
English (en)
French (fr)
Inventor
白一晨
严允晟
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/613,118 priority Critical patent/US20240038190A1/en
Publication of WO2023035370A1 publication Critical patent/WO2023035370A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel.
  • FIG. 1 shows a schematic diagram of a display panel 10 in the prior art.
  • the display panel 10 includes a plurality of data lines D1-D7, a plurality of gate lines G1-G16 and a plurality of pixels P, wherein the plurality of pixels includes a plurality of red pixels R, a plurality of green pixels G and a plurality of blue pixels B.
  • the display panel 10 adopts a DLS architecture, that is, pixels in different columns are connected to the same data line. The polarities of signals transmitted by two adjacent data lines are opposite. As shown in FIG.
  • the first to third columns of pixels display the first column of white lines
  • the fourth to sixth columns of pixels display the second column of white lines.
  • the seventh column of pixels displays the first column of red lines
  • the tenth column of pixels displays the second column of red lines
  • the switches of the remaining columns of pixels display black.
  • the ratio of positive polarity pixels to negative polarity pixels is 3:1.
  • the eleventh gate line G11 is turned on, the ratio of positive polarity pixels to negative polarity pixels is 1:3. That is, the number of positive pixels connected to the same gate line in the same row of pixels differs greatly from the number of negative pixels, which causes serious horizontal crosstalk problems in the existing DLS architecture and reduces the image quality of the panel.
  • the purpose of the present application is to provide a display panel to improve the horizontal crosstalk problem of the display panel and improve the image quality of the display panel.
  • the present application provides a display panel, comprising: a plurality of pixels arranged in an array along the row direction and the column direction; first main data lines extending along the column direction, wherein the first main data lines The line is electrically connected to the pixels arranged in at least two columns; the first data line extends along the column direction, wherein the first data line is separated from the first main data line by M columns of pixels, and the The first data line is electrically connected to the pixels arranged in at least two other columns; the first connection line is connected to the first main data line and the first data line; the second main data line is along the column The second data line extends along the column direction and is adjacent to the first data line, and the second data line is adjacent to the first data line.
  • the second main data lines are separated by M columns of pixels, and the second main data lines and the second secondary data lines are respectively electrically connected to pixels arranged in at least two columns;
  • the second connecting line is connected to the second The main data line and the second data line, wherein the first main data line and the first data line are configured to transmit signals of the first polarity, and the second main data line and the first The secondary data line is configured to transmit a signal of a second polarity opposite to the first polarity;
  • a plurality of gate lines extending along the row direction, wherein two adjacent rows of pixels are arranged between Gate lines, the plurality of gate lines include a first gate line and a second gate line, respectively arranged on both sides of the first row of pixels, the first gate line and the second gate line They are respectively connected to at least one pixel in the first row of pixels, and in the first row of pixels, the number of pixels with positive polarity and pixels with negative polarity is equal.
  • the first main data line alternately connects the pixels arranged in the first column and the pixels arranged in the second column, and the first data line alternately connects the pixels arranged in the Nth column and the pixels arranged in the N+1th column; and the second main data lines are alternately connected to the pixels arranged in the second column and the pixels arranged in the third column, and the second data lines are alternately connected The pixels arranged in the N+1th column and the pixels in the N+2th column are connected.
  • the first main data line connects the pixels in the first row and the second column and the pixels in the second row and the first column
  • the second main data line connects the pixels in the first row and the third column and Pixels in the second row and second column.
  • the first main data line is electrically connected to the pixels arranged in four columns, and the first data line is electrically connected to the pixels arranged in the other four columns; in odd-numbered rows of pixels, the The first main data line and the first data line are electrically connected to pixels in two columns of the corresponding four columns of pixels; and in an even row of pixels, the first main data line and the first data line The wires are electrically connected to the pixels of the other two columns of the respective corresponding four columns of pixels.
  • the first main data line is electrically connected to the pixels in the second and third columns of the corresponding four columns of pixels, and the first data line is connected to the corresponding The pixels in the first column and the fourth column of the four columns of pixels are electrically connected; Electrically connected, the first data line is electrically connected to the pixels in the second column and the third column of the corresponding four columns of pixels.
  • the second main data line is electrically connected to pixels arranged in four columns, and the second data line is electrically connected to pixels arranged in another four columns; in odd-numbered rows of pixels, the The second main data line and the second data line are electrically connected to pixels in two columns of the corresponding four columns of pixels; and in even-numbered rows of pixels, the second main data line and the second data line
  • the wires are electrically connected to the pixels of the other two columns of the respective corresponding four columns of pixels.
  • the first main data line is electrically connected to the pixels arranged in column X, column X+1, column X+2, and column X+3, and the second main data line is arranged in The pixels in the X+2 column, X+3 column, X+4 column, and X+5 column are electrically connected; in the odd-numbered row of pixels, the first main data line is arranged in the X+ Pixels in column 1 and column X+2 are electrically connected, and the second main data line is electrically connected to pixels arranged in column X+3 and column X+5; and in the even-numbered row of pixels, all The first main data line is electrically connected to the pixels arranged in the X column and the X+3 column, and the second main data line is electrically connected to the pixels arranged in the X+2 column and the X+4 column.
  • the display panel further includes: a source driver; and wiring, connecting the source driver and the first main data line, wherein the first connection line is provided at one end of the wiring and Between the pixels of the first row and the end is a connection end between the wiring and the first main data line.
  • the present application also provides a display panel, including: a plurality of pixels arranged in an array along a row direction and a column direction; a first main data line extending along the column direction, wherein the first main data line is arranged in an array with the Pixels in at least two columns are electrically connected; the first data line extends along the column direction, wherein the first data line is separated from the first main data line by M columns of pixels, and the first data line
  • the lines are electrically connected to the pixels arranged in at least two other columns; and the first connecting lines are used to connect the first main data lines and the first primary data lines.
  • the display panel further includes: a second main data line extending along the column direction and adjacent to the first main data line; a second sub data line extending along the column direction, and adjacent to the first data line, wherein the second data line is separated from the second main data line by M columns of pixels, and the second main data line and the second The data lines are respectively electrically connected to the pixels arranged in at least two columns; and the second connection line is connected to the second main data line and the second data line, wherein the first main data line is connected to the first The secondary data line is configured to transmit signals of a first polarity, and the second primary data line and the second secondary data line are configured to transmit signals of a second polarity opposite to the first polarity.
  • the first main data line alternately connects the pixels arranged in the first column and the pixels arranged in the second column, and the first data line alternately connects the pixels arranged in the Nth column and the pixels arranged in the N+1th column; and the second main data lines are alternately connected to the pixels arranged in the second column and the pixels arranged in the third column, and the second data lines are alternately connected The pixels arranged in the N+1th column and the pixels in the N+2th column are connected.
  • the first main data line connects the pixels in the first row and the second column and the pixels in the second row and the first column
  • the second main data line connects the pixels in the first row and the third column and Pixels in the second row and second column.
  • the first main data line is electrically connected to the pixels arranged in four columns, and the first data line is electrically connected to the pixels arranged in the other four columns;
  • the first main data line and the first-time data line are electrically connected to pixels in two columns of the corresponding four columns of pixels; and in even-numbered rows of pixels, the first main data line line and the first data line are electrically connected to the pixels in the other two columns of the corresponding four columns of pixels.
  • the first main data line is electrically connected to the pixels in the second and third columns of the corresponding four columns of pixels, and the first data line is connected to the corresponding The pixels in the first column and the fourth column of the four columns of pixels are electrically connected; Electrically connected, the first data line is electrically connected to the pixels in the second column and the third column of the corresponding four columns of pixels.
  • the second main data line is electrically connected to pixels arranged in four columns, and the second data line is electrically connected to pixels arranged in another four columns; in odd-numbered rows of pixels, the The second main data line and the second data line are electrically connected to pixels in two columns of the corresponding four columns of pixels; and in even-numbered rows of pixels, the second main data line and the second data line
  • the wires are electrically connected to the pixels of the other two columns of the respective corresponding four columns of pixels.
  • the first main data line is electrically connected to the pixels arranged in column X, column X+1, column X+2, and column X+3, and the second main data line is arranged in The pixels in the X+2 column, X+3 column, X+4 column, and X+5 column are electrically connected; in the odd-numbered row of pixels, the first main data line is arranged in the X+ Pixels in column 1 and column X+2 are electrically connected, and the second main data line is electrically connected to pixels arranged in column X+3 and column X+5; and in the even-numbered row of pixels, all The first main data line is electrically connected to the pixels arranged in the X column and the X+3 column, and the second main data line is electrically connected to the pixels arranged in the X+2 column and the X+4 column.
  • the display panel further includes: a source driver; and wiring, connecting the source driver and the first main data line, wherein the first connection line is provided at one end of the wiring and Between the pixels of the first row and the end is a connection end between the wiring and the first main data line.
  • the display panel further includes a plurality of gate lines extending along the row direction, and two gate lines are arranged between pixels in two adjacent rows; the plurality of gate lines include The first gate line and the second gate line are respectively arranged on both sides of the pixels in the first row, and the first gate line and the second gate line are respectively connected to at least one of the pixels in the first row.
  • One pixel is connected; and in the first row of pixels, the number of positive polarity pixels is equal to the number of negative polarity pixels.
  • the present application can realize the same row while using a smaller number of connectors for connecting the source driver and the display panel by setting the secondary data line connected to the main data line in the display panel.
  • the number of positive and negative pixels is similar, thereby improving the crosstalk problem of the display panel and enhancing the picture quality of the display panel.
  • FIG. 1 shows a schematic diagram of a display panel in the prior art.
  • FIG. 2 shows a schematic diagram of a pixel circuit of a display panel according to a first embodiment of the present application.
  • FIG. 3 shows a schematic diagram of a pixel circuit of a display panel according to a second embodiment of the present application.
  • FIG. 4 shows a schematic diagram of a display device according to an embodiment of the present application.
  • FIG. 2 it shows a schematic diagram of a pixel circuit of a display panel 200 according to an embodiment of the present application.
  • the display panel 200 includes a plurality of pixels and a plurality of data lines (including main data lines D1-1 to D8-1, secondary data lines D1 -2 to D8-2, multiple connection lines C1-C8), multiple gate lines G1-G6.
  • a plurality of pixels are arrayed along a row direction and a column direction, and include a red pixel R, a green pixel G, and a blue pixel B.
  • a plurality of data lines extends in a column direction, and a plurality of gate lines extends in a row direction.
  • each data line includes a main data line, a secondary data line and a connection line, such as the first data line includes the first main data line D1-1, the first data line D1-2 and the first connection line C1, the second data line includes a second main data line D2-1, a second secondary data line D2-2 and a second connection line C2.
  • the first main data line D1-1 is connected to the primary data line D1-2 through the first connection line C1
  • the second main data line D2-1 is connected to the second data line D2-2 through the second connection line C2.
  • the first main data line D1-1 is adjacent to the second main data line D2-1
  • the first data line D1-2 is adjacent to the second data line D2-2.
  • the first data line is not limited to the first data line arranged in the display panel 200, and can be any data line, that is, the first data line and the second data line should be understood as the first data line in the display panel 200. Any two adjacent data lines.
  • M there are M columns of pixels between the first main data line D1 - 1 and the first data line D1 - 2 .
  • the second main data line D2-1 and the second sub-data line D2-2 are also separated by M columns of pixels, wherein M is a positive integer greater than or equal to 1.
  • M is 4, that is, the distance between the connected main data line and the secondary data line is four columns of pixels.
  • M is preferably less than or equal to 2, which can effectively avoid electrostatic discharge (ESD) caused by excessive cross-line design in the connection line connecting the main data line and the secondary data line risk and reduce the charging speed of Pixel P.
  • ESD electrostatic discharge
  • the main data lines are electrically connected to the pixels arranged in at least two columns, and the sub data lines are electrically connected to the pixels arranged in at least the other two columns.
  • the connection of the data lines to the pixels arranged in a specific row means that they are connected to at least one pixel in the row, not to all the pixels in the row.
  • the same primary data line or secondary data line alternately connects pixels arranged in two columns.
  • the first main data line D1-1 is arranged between the pixels in the first column and the pixels in the second column, and the first main data line D1-1 alternately connects the pixels arranged in the first column and the pixels arranged in the second column.
  • the first data line D1-2 is arranged between the pixels in the Nth column and the N+1th column, and the first data line D1-2 alternately connects the pixels arranged in the Nth column and the pixels arranged in the Nth column. Pixels in the +1 column, where N is a positive integer greater than or equal to 1. In this embodiment, N is 5. That is, the first data line D1-2 is disposed between the pixels in the fifth column and the pixels in the sixth column, and alternately connects the pixels arranged in the fifth column and the pixels arranged in the sixth column.
  • the second main data line D2-1 is disposed between the pixels in the second column and the pixels in the third column, and the second main data line D2-1 alternately connects the pixels arranged in the second column and the pixels arranged in the third column.
  • the second data line D2-2 is arranged between the pixels in the sixth column and the pixels in the seventh column, and the second data line D2-2 alternately connects the pixels arranged in the sixth column and the pixels arranged in the seventh column. pixel.
  • the alternate connection of data lines means that the data lines are connected to pixels in odd rows or even rows of pixels in the same column. That is to say, the alternate connection includes the same data line connected to the odd-numbered row of pixels in one column of pixels and connected to the even-numbered row of pixels in another adjacent column of pixels, or the same data line is connected to two adjacent columns of pixels The odd-numbered rows of pixels, or the same data line is connected to the even-numbered rows of pixels in two adjacent columns of pixels.
  • the first main data line D1 - 1 connects the pixels in the first row and the second column to the pixels in the second row and the first column.
  • the alternate connection of data lines means that the first main data line D1-1 is connected to the even-numbered rows of pixels in the first column of pixels and to the odd-numbered rows of pixels in the second column pixel.
  • the second main data line D2-1 connects the pixels in the first row and the third column to the pixels in the second row and the second column.
  • the alternate connection of the data lines means that the second main data line D2-1 is connected to the pixels in the even rows of pixels in the second column and to the pixels in the odd rows of pixels in the third column.
  • pixels in the same row are controlled by two adjacent gate lines, and two gate lines are arranged between pixels in two adjacent rows.
  • the first row of pixels is disposed between the first gate line G1 and the second gate line G2
  • the second gate line G2 and the third gate line are disposed between the first row of pixels and the second row of pixels.
  • the pixels in the same row are correspondingly connected to two adjacent gate lines, for example, the first gate line G1 is connected to at least one pixel in the first row of pixels, and the second gate line G2 is connected to the second gate line G2. At least one other pixel in a row of pixels corresponds to a connection.
  • the third gate line G3 is correspondingly connected to at least one pixel in the second row of pixels
  • the fourth gate line G4 is correspondingly connected to at least one pixel in the second row of pixels.
  • the corresponding connections of the gate lines include ordered or disordered connections, that is to say, pixels in the same row can be correspondingly connected to two adjacent gate lines at intervals of the same or different number of pixels.
  • a group of four pixels is alternately connected to two adjacent gate lines.
  • the first gate line G1 is connected to the pixels in the first to fourth columns and the ninth to twelfth columns in the first row of pixels.
  • the second gate line G2 is connected to the pixels in the fifth to eighth columns and the thirteenth to sixteenth columns in the first row of pixels.
  • pixels in the same row may be connected to two adjacent gate lines at intervals of the same or different number of pixels.
  • the same data line is used to alternately connect pixels arranged in different columns and the same row of pixels is connected to two adjacent gate lines correspondingly, so that data line sharing (data line share, DLS) is realized. ) architecture. Therefore, in this embodiment, the number of connectors used to connect the source driver and the display panel can be reduced to half of that of the conventional structure, thereby reducing the risk of poor bonding caused by setting multiple connectors and reducing costs .
  • the display panel 200 includes liquid crystals.
  • the liquid crystal unit corresponding to each pixel has its own signal electrode.
  • the connected primary and secondary data lines are configured to transmit signals of the same polarity, and two adjacent data lines are configured to transmit signals of opposite polarities.
  • the first main data line D1-1 and the first data line D1-2 are configured to transmit signals of the first polarity
  • the second main data line D2-1 and the second data line D2-2 are configured To transmit a signal with a second polarity opposite to the first polarity, and so on.
  • the second main data line D2-1 and the second data line D2-2 configured to pass a signal of positive polarity.
  • pixels in the same column are of the same color.
  • the polarities of two adjacent pixels in the same row of pixels are opposite.
  • the pixels in the first row and first column are positive polarity
  • the pixels in the second row and first column Pixels are negative polarity
  • pixels in the third row and first column are positive polarity, and so on.
  • the cause of horizontal crosstalk in a special picture is strongly related to the polarity of pixels.
  • the polarity of the pixels presents "-+ - -+ - + +" or "+ - ++-+--” arrangement rule.
  • the overall perceived crosstalk can be reduced.
  • the display panel 200 displays a special picture with two columns of red lines and two columns of white lines alternately, a special picture with one column of red lines and two columns of white lines alternately, or a special picture with one column of white lines and one column of black lines alternately , the number of pixels of positive polarity and negative polarity connected to the same gate line in the same row of pixels is the same.
  • the same row of pixels is connected to The ratio of the pixels of the positive polarity to the pixels of the negative polarity of the same grid line is between 3/4 and 1. Also, when the display panel 200 displays a special picture with two columns of white lines and two columns of black lines alternately arranged , the ratio of positive polarity pixels connected to the same gate line to negative polarity pixels in the same row of pixels is between 2/3 and 3/4. It can be seen from this that when the display panel 200 displays the five special When the screen is displayed, the risk of horizontal crosstalk is low, thereby improving the picture quality of the display panel. In addition, in the same row of pixels, the polarity of the pixels is reversed at every interval of one or two pixels, that is, the (1 +2) Dot inversion (1+2 dot inversion) drive.
  • the coupling capacitance to the common electrode can be eliminated, thereby avoiding crosstalk.
  • a coupling capacitance is generated between the pixel and the data line, and the value of the coupling capacitance is inversely proportional to the distance between the pixel and the data line. In other words, the greater the distance between the pixel and the data line, the smaller the capacitance between the two.
  • FIG. 2 since opposite sides of each pixel are adjacent to the data line, and there is no other pixel disposed between the side of the pixel and the data line.
  • Two adjacent data lines are configured to transmit signals of opposite polarities, so the polarities of the coupling capacitors on both sides of each pixel are opposite, so that the coupling capacitance between each pixel and one of the data lines is similar to that of the other A coupling capacitance between data lines. Therefore, the present application can improve the problem of rough image quality and vertical crosstalk caused by a large difference in the distance between the pixel and two adjacent data lines on both sides, and asymmetrical coupling capacitors on both sides of the pixel.
  • FIG. 3 it shows a schematic diagram of a pixel circuit of a display panel 300 according to a second embodiment of the present application.
  • the display panel 300 includes a plurality of pixels, a plurality of data lines (including main data lines D1-1 to D4-1, secondary data lines lines D1-2 to D4-2, a plurality of connecting lines C1-C4), and a plurality of gate lines G1-G4.
  • a plurality of pixels are arrayed along a row direction and a column direction, and include a red pixel R, a green pixel G, and a blue pixel B.
  • a plurality of data lines extends in a column direction, and a plurality of gate lines extends in a row direction.
  • each data line includes a main data line, a secondary data line and a connection line, such as the first data line includes the first main data line D1-1, the first data line D1-2 and the first connection line C1, the second data line includes a second main data line D2-1, a second secondary data line D2-2 and a second connection line C2.
  • the first main data line D1-1 is connected to the primary data line D1-2 through the first connection line C1
  • the second main data line D2-1 is connected to the second data line D2-2 through the second connection line C2.
  • the first main data line D1-1 is adjacent to the second main data line D2-1
  • the first data line D1-2 is adjacent to the second data line D2-2.
  • the first data line is not limited to the first data line arranged in the display panel 300, and can be any data line, that is, the first data line and the second data line should be understood as the first data line in the display panel 300. Any two adjacent data lines.
  • M there are M columns of pixels between the first main data line D1 - 1 and the first data line D1 - 2 .
  • the second main data line D2-1 and the second sub-data line D2-2 are also separated by M columns of pixels.
  • M is 4, that is, the distance between the connected main data line and the secondary data line is four columns of pixels.
  • M is preferably less than or equal to 2, which can effectively avoid the risk of electrostatic discharge caused by the connection line connecting the main data line and the secondary data line including too many cross-line designs and reduce the pixel P charging speed.
  • the main data lines are electrically connected to the pixels arranged in four columns, and the sub data lines are electrically connected to the pixels arranged in the other four columns.
  • the first main data line D1-1 is electrically connected to the pixels arranged in the first column to the fourth column.
  • the first data line D1-2 is electrically connected to the pixels arranged in the Nth column to the N+3th column.
  • N is 5. That is, the primary data line D1-2 is electrically connected to the pixels arranged in the fifth column to the eighth column.
  • the connected primary data lines and secondary data lines are electrically connected to pixels in two columns of the corresponding four columns of pixels.
  • the connected main data lines and sub-data lines are electrically connected to pixels in the other two columns of the corresponding four columns of pixels.
  • the first main data line D1-1 is electrically connected to the pixels in the second and third columns of the corresponding four columns of pixels
  • the first data line D1-2 is electrically connected to the pixels in the corresponding four columns. Pixels of the first and fourth columns of columns of pixels are electrically connected.
  • the second main data line D2-1 is electrically connected to the pixels in the second and fourth columns of the corresponding four-column pixels
  • the second data line D2-2 is electrically connected to the corresponding four-column pixels.
  • the pixels of the first column and the third column are electrically connected.
  • the first main data line D1-1 is electrically connected to the pixels in the first and fourth columns of the corresponding four-column pixels
  • the first data line D1-2 is electrically connected to the corresponding four-column pixels.
  • the pixels of the second column and the third column are electrically connected.
  • the second main data line D2-1 is electrically connected to the pixels in the first column and the third column in the corresponding four columns of pixels
  • the second data line D2-2 is electrically connected to the pixels in the corresponding four columns. Pixels in the second and fourth columns of the columns of pixels are electrically connected.
  • pixels in the same column are correspondingly connected to different data lines.
  • One of the main or secondary data lines is electrically connected to the pixels arranged in the X column, the X+1 column, the X+2 column, and the X+3 column, and the other adjacent main or secondary data line is connected to the arrangement
  • the pixels in column X+2, column X+3, column X+4, and column X+5 are electrically connected, where X is a positive integer greater than or equal to 1.
  • the first main data line D1-1 is electrically connected to the pixels arranged in the first column to the fourth column
  • the second main data line D2-1 is electrically connected to the pixels arranged in the third column to the sixth column. .
  • the primary data line D1-2 is electrically connected to the pixels arranged in the fifth column to the eighth column
  • the second data line D2-2 is electrically connected to the pixels arranged in the seventh column to the tenth column.
  • the first main data line D1-1 is electrically connected to the pixels arranged in the second column and the third column
  • the second main data line D2-1 is electrically connected to the pixels arranged in the fourth column and the sixth column.
  • the first data line D1-2 is electrically connected to the pixels arranged in the fifth column and the eighth column
  • the second data line D2-2 is electrically connected to the pixels arranged in the seventh column and the ninth column.
  • the first main data line D1-1 is electrically connected to the pixels arranged in the first column and the fourth column
  • the second main data line D2-1 is electrically connected to the pixels arranged in the third column and the fifth column
  • the first data line D1-2 is electrically connected to the pixels arranged in the sixth column and the seventh column
  • the second data line D2-2 is electrically connected to the pixels arranged in the eighth column and the tenth column.
  • pixels in the same row are controlled by two adjacent gate lines, and two gate lines are arranged between pixels in two adjacent rows.
  • the first row of pixels is disposed between the first gate line G1 and the second gate line G2
  • the second gate line G2 and the third gate line are disposed between the first row of pixels and the second row of pixels.
  • the pixels in the same row are correspondingly connected to two adjacent gate lines, for example, the first gate line G1 is connected to at least one pixel in the first row of pixels, and the second gate line G2 is connected to the second gate line G2. At least one other pixel in a row of pixels corresponds to a connection.
  • the third gate line G3 is correspondingly connected to at least one pixel in the second row of pixels
  • the fourth gate line G4 is correspondingly connected to at least one pixel in the second row of pixels.
  • the corresponding connections of the gate lines include ordered or disordered connections, that is to say, pixels in the same row can be correspondingly connected to two adjacent gate lines at intervals of the same or different number of pixels.
  • the data line sharing architecture is realized through the design that the same data line is connected to pixels in different columns and the same row of pixels is connected to two gate lines correspondingly. Therefore, in this embodiment, the number of connectors used to connect the source driver and the display panel can be reduced to half of that of the conventional structure, thereby reducing the risk of poor bonding caused by setting multiple connectors and reducing costs .
  • the display panel 300 includes liquid crystals.
  • the liquid crystal unit corresponding to each pixel has its own signal electrode.
  • the connected primary and secondary data lines are configured to transmit signals of the same polarity, and two adjacent data lines are configured to transmit signals of opposite polarities.
  • the first main data line D1-1 and the first data line D1-2 are configured to transmit signals of the first polarity
  • the second main data line D2-1 and the second data line D2-2 are configured To transmit a signal with a second polarity opposite to the first polarity, and so on.
  • the second main data line D2-1 and the second data line D2-2 configured to pass signals of negative polarity.
  • the cause of horizontal crosstalk in a special picture is strongly related to the polarity of pixels.
  • the pixels in the same row have the same color, and the polarities of two adjacent pixels in the same row of pixels are opposite. Also, in the same row of pixels, the polarity of the pixels presents an arrangement rule of "-+ - -+ - + +" or "+ - ++-+--".
  • the overall perceived crosstalk can be reduced.
  • the display panel 300 displays a special picture with one column of red lines and two columns of white lines alternately, a special picture with one column of white lines and one column of black lines alternately, a special picture with two columns of red lines and two columns of white lines alternately screen, or a special screen in which two columns of white lines and two columns of black lines are alternately arranged
  • the number of pixels of positive polarity and pixels of negative polarity connected to the same gate line in the same row of pixels is the same.
  • the display panel 300 displays a special picture containing a plurality of continuous W characters
  • the ratio of two pixels with opposite polarities connected to the same gate line in the same row of pixels is between 3/4 and 1.
  • the risk of horizontal crosstalk is low, thereby improving the image quality of the display panel.
  • the polarity of the pixels is reversed at intervals of one or two pixels, that is, (1+2) dot inversion (1+2 dot inversion) driving in the row direction is realized.
  • the display device 20 includes a display panel 100 , a controller 21 , a gate driver 22 , a source driver 23 and a plurality of connectors 24 .
  • the display panel 100 includes a fan-out area 101 , a connection area 102 and a display area 103 , wherein the connection area 102 is between the fan-out area 101 and the display area 103 .
  • the display panel 100 may be the display panel 200 of the above-mentioned first embodiment or the display panel 300 of the above-mentioned second embodiment.
  • the display panel 200 of FIG. 2 and the display panel 300 of FIG. 3 only show a connection area and a display area corresponding to the display panel 100 of FIG. 4 .
  • the controller 21 is connected to a power supply to provide power to the display device 20 , and then controls the display device 20 to be turned on or off.
  • the controller 21 may include a timing controller, a microprocessor, a gamma voltage generator, and the like.
  • the controller 21 is connected with the gate driver 22 and the source driver 23 , and the gate driver 22 and the source driver 23 are connected with the display panel 100 .
  • the connector 24 is configured to bond the source driver 23 to the display panel 100 .
  • the connector 24 may include but not limited to a chip on film (COF).
  • the display panel 100 includes a plurality of data lines DL, a plurality of gate lines GL and a plurality of pixels P, wherein the plurality of data lines DL extend along the column direction, the plurality of gate lines GL extend along the row direction, and the plurality of pixels P Arranged in arrays along the row and column directions.
  • the source driver 23 is correspondingly connected to a plurality of pixels P through a plurality of data lines DL.
  • the source driver 23 is correspondingly connected to a plurality of pixels P through a plurality of gate lines GL.
  • the plurality of pixels P include pixels of different colors, such as red pixels, green pixels, blue pixels or white pixels, configured to emit red, green, blue or white light correspondingly. It should be noted that one or more columns of pixels P may be disposed between two adjacent data lines DL of the display panel 100 .
  • the controller 21 is configured to generate gate control signals and data control signals.
  • the gate driver 22 generates a gate signal according to the gate control signal, and transmits the gate signal to a plurality of pixels P through a plurality of gate lines GL.
  • the controller 21 transmits data control signals (such as analog video signals, reference gamma voltage signals, etc.) to the source driver 23 .
  • the source driver 23 generates a corresponding data signal according to the data control signal, and transmits the data signal to a plurality of pixels P through a plurality of data lines DL.
  • a plurality of wires W are provided in the fan-out area 101 .
  • the connection area 102 is provided with a plurality of data lines DL and a plurality of connection lines, such as a first connection line C1 and a second connection line C2.
  • the display area 103 is provided with a plurality of pixels P, a plurality of data lines DL and a plurality of gate lines GL, wherein the plurality of data lines DL extend from the connection area 102 to the display area 103 .
  • the multiple wirings W in the fan-out area 101 are configured to connect the source driver 23 and the main data lines of the corresponding multiple data lines DL (such as the first main data line D1-1, the second main data line D2) through the connector 24. -1 etc.).
  • the controller 21 acquires an image data signal related to one frame of image to generate a corresponding gate control signal and data control signal, and then controls the display area 103 of the display panel 100 to display the image.
  • connection lines connecting the main data lines and the sub data lines are arranged in the connection area 102 .
  • the connecting wires are arranged between the plurality of wires W located in the fan-out area 101 and the first row of pixels P located in the display area 103 . That is, the connection line is disposed between one end of the wire W and the first row of pixels P, and the end is the connection end of the wire W and the corresponding main data line.
  • the present application reduces the number of connectors used to connect the source driver and the display panel to half of that of the traditional architecture by setting the secondary data lines connected to the main data lines in the display panel, thereby reducing the number of connections due to Risk of poor fit caused by multiple connectors and cost reduction. Furthermore, through the pixel circuit of the display panel of the present application, the number of positive and negative pixels in the same row of pixels can be similar, thereby improving the horizontal crosstalk problem of the display panel and improving the picture quality of the display panel.

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Abstract

一种显示面板(200)，包括：多个画素、第一主数据线(D1-1)和第一次数据线(D1-2)以及第一连接线(C1)。第一主数据线(D1-1)与排列在至少两列的画素电连接。第一次数据线(D1-2)与第一主数据线(D1-1)间隔M列画素，并且第一次数据线(D1-2)与排列在至少另两列的画素电连接。第一连接线(C1)连接第一主数据线(D1-1)与第一次数据线(D1-2)。

Description

显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
随着面板产业的发展，面板的解析度和刷新频率也随之提高，但也导致了设置在源极驱动器中的薄膜覆晶封装（chip on film，COF）的数量增加，进而提高了COF贴合（bonding）不良的风险，以及增加了成本。因此，一种数据线共享（data line share，DLS）架构被提出。在DLS架构中，COF的数量减少为传统架构的一半，如此降低了因为设置多个COF而引起的贴合不良的风险和降低成本。
图1显示现有技术中的显示面板10的示意图。显示面板10包含多条数据线D1-D7、多条栅极线G1-G16和多个画素P，其中多个画素包含多个红色画素R、多个绿色画素G和多个蓝色画素B。显示面板10采用DLS架构，即不同列的画素连接至同一条数据线。相邻的两条数据线传递的信号极性相反。如图1所示，当显示面板10显示以两列红线和两列白线交替排列的图像时，第一至第三列画素显示第一列白线，第四至第六列画素显示第二列白线，第七列画素显示第一列红线，第十列画素显示第二列红线，其余列画素的开关关闭显示黑色。
然而，如图1所示，当第一条栅极线G1打开时，正极性的画素与负极性的画素比例为3：1。又，当第十一条栅极线G11打开时，正极性的画素与负极性的画素比例为1：3。即，同一行画素中连接同一条栅极线的正极性的画素与负极性的画素的数量差异大，使得现有的DLS架构存在严重的水平串扰问题，降低了面板的画质。
有鉴于此，有必要提出一种显示面板，以解决现有技术中存在的问题。
 技术问题
为解决上述现有技术的问题，本申请的目的在于提供一种显示面板，以改善显示面板的水平串扰问题和提升显示面板的画面质量。
 技术解决方案
为达成上述目的，本申请提供一种显示面板，包括：多个画素，沿着行方向和列方向阵列排列；第一主数据线，沿着所述列方向延伸，其中所述第一主数据线与排列在至少两列的画素电连接；第一次数据线，沿着所述列方向延伸，其中所述第一次数据线与所述第一主数据线间隔M列画素，并且所述第一次数据线与排列在至少另两列的画素电连接；第一连接线，连接所述第一主数据线与所述第一次数据线；第二主数据线，沿着所述列方向延伸，且与所述第一主数据线相邻；第二次数据线，沿着所述列方向延伸，且与所述第一次数据线相邻，其中所述第二次数据线与所述第二主数据线间隔M列画素，并且所述第二主数据线和所述第二次数据线分别与排列在至少两列的画素电连接；第二连接线，连接所述第二主数据线与所述第二次数据线，其中所述第一主数据线与所述第一次数据线配置为传递第一极性的信号，以及所述第二主数据线与所述第二次数据线配置为传递与所述第一极性相反的第二极性的信号；以及多条栅极线，沿着所述行方向延伸，其中两相邻行画素之间设置有两条栅极线，所述多条栅极线包括第一栅级线和第二栅极线，分别设置在第一行画素的两侧，所述第一栅级线和所述第二栅极线分别与所述第一行画素中的至少一画素连接，以及在所述第一行画素中，正极性的画素与负极性的画素的数量相等。
在一些实施例中，所述第一主数据线交替地连接排列在第一列的画素和排列在第二列的画素，以及所述第一次数据线交替地连接排列在第N列的画素和排列在第N+1列的画素；以及所述第二主数据线交替地连接排列在所述第二列的画素和排列在第三列的画素，以及所述第二次数据线交替地连接排列在所述第N+1列的画素和列在第N+2列的画素。
在一些实施例中，所述第一主数据线连接第一行第二列的画素和第二行第一列的画素，以及所述第二主数据线连接第一行第三列的画素和第二行第二列的画素。
在一些实施例中，所述第一主数据线与排列在四列的画素电连接，以及所述第一次数据线与排列在另四列的画素电连接；在奇数行画素中，所述第一主数据线和所述第一次数据线与各自对应的四列画素的其中两列的画素电连接；以及在偶数行画素中，所述第一主数据线和所述第一次数据线与各自对应的四列画素的另外两列的画素电连接。
在一些实施例中，在所述奇数行画素中，所述第一主数据线与对应的四列画素中的第二列和第三列的画素电连接，所述第一次数据线与对应的四列画素的第一列和第四列的画素电连接；以及在所述偶数行画素中，所述第一主数据线与对应的四列画素中的第一列和第四列的画素电连接，所述第一次数据线与对应的四列画素的第二列和第三列的画素电连接。
在一些实施例中，所述第二主数据线与排列在四列的画素电连接，以及所述第二次数据线与排列在另四列的画素电连接；在奇数行画素中，所述第二主数据线和所述第二次数据线与各自对应的四列画素的其中两列的画素电连接；以及在偶数行画素中，所述第二主数据线和所述第二次数据线与各自对应的四列画素的另外两列的画素电连接。
在一些实施例中，所述第一主数据线与排列在第X列、第X+1列、第X+2列、第X+3列的画素电连接，以及第二主数据线与排列在第X+2列、第X+3列、第X+4列、第X+5列的画素电连接；在所述奇数行画素中，所述第一主数据线与排列在第X+1列和第X+2列的画素电连接，以及所述第二主数据线与排列在第X+3列和第X+5列的画素电连接；以及在所述偶数行画素中，所述第一主数据线与排列在第X列和第X+3列的画素电连接，以及所述第二主数据线与排列在第X+2列和第X+4列的画素电连接。
在一些实施例中，所述显示面板还包含：源极驱动器；以及布线，连接所述源极驱动器和所述第一主数据线，其中所述第一连接线设置在所述布线的一端和第一行画素之间，以及所述端为所述布线和所述第一主数据线的连接端。
本申请还提供一种显示面板，包括：多个画素，沿着行方向和列方向阵列排列；第一主数据线，沿着所述列方向延伸，其中所述第一主数据线与排列在至少两列的画素电连接；第一次数据线，沿着所述列方向延伸，其中所述第一次数据线与所述第一主数据线间隔M列画素，并且所述第一次数据线与排列在至少另两列的画素电连接；以及第一连接线，连接所述第一主数据线与所述第一次数据线。
在一些实施例中，所述显示面板还包括：第二主数据线，沿着所述列方向延伸，且与所述第一主数据线相邻；第二次数据线，沿着所述列方向延伸，且与所述第一次数据线相邻，其中所述第二次数据线与所述第二主数据线间隔M列画素，并且所述第二主数据线和所述第二次数据线分别与排列在至少两列的画素电连接；以及第二连接线，连接所述第二主数据线与所述第二次数据线，其中所述第一主数据线与所述第一次数据线配置为传递第一极性的信号，以及所述第二主数据线与所述第二次数据线配置为传递与所述第一极性相反的第二极性的信号。
在一些实施例中，所述第一主数据线交替地连接排列在第一列的画素和排列在第二列的画素，以及所述第一次数据线交替地连接排列在第N列的画素和排列在第N+1列的画素；以及所述第二主数据线交替地连接排列在所述第二列的画素和排列在第三列的画素，以及所述第二次数据线交替地连接排列在所述第N+1列的画素和列在第N+2列的画素。
在一些实施例中，所述第一主数据线连接第一行第二列的画素和第二行第一列的画素，以及所述第二主数据线连接第一行第三列的画素和第二行第二列的画素。
在一些实施例中，所述第一主数据线与排列在四列的画素电连接，以及所述第一次数据线与排列在另四列的画素电连接；
在奇数行画素中，所述第一主数据线和所述第一次数据线与各自对应的四列画素的其中两列的画素电连接；以及在偶数行画素中，所述第一主数据线和所述第一次数据线与各自对应的四列画素的另外两列的画素电连接。
在一些实施例中，在所述奇数行画素中，所述第一主数据线与对应的四列画素中的第二列和第三列的画素电连接，所述第一次数据线与对应的四列画素的第一列和第四列的画素电连接；以及在所述偶数行画素中，所述第一主数据线与对应的四列画素中的第一列和第四列的画素电连接，所述第一次数据线与对应的四列画素的第二列和第三列的画素电连接。
在一些实施例中，所述第二主数据线与排列在四列的画素电连接，以及所述第二次数据线与排列在另四列的画素电连接；在奇数行画素中，所述第二主数据线和所述第二次数据线与各自对应的四列画素的其中两列的画素电连接；以及在偶数行画素中，所述第二主数据线和所述第二次数据线与各自对应的四列画素的另外两列的画素电连接。
在一些实施例中，所述第一主数据线与排列在第X列、第X+1列、第X+2列、第X+3列的画素电连接，以及第二主数据线与排列在第X+2列、第X+3列、第X+4列、第X+5列的画素电连接；在所述奇数行画素中，所述第一主数据线与排列在第X+1列和第X+2列的画素电连接，以及所述第二主数据线与排列在第X+3列和第X+5列的画素电连接；以及在所述偶数行画素中，所述第一主数据线与排列在第X列和第X+3列的画素电连接，以及所述第二主数据线与排列在第X+2列和第X+4列的画素电连接。
在一些实施例中，所述显示面板还包含：源极驱动器；以及布线，连接所述源极驱动器和所述第一主数据线，其中所述第一连接线设置在所述布线的一端和第一行画素之间，以及所述端为所述布线和所述第一主数据线的连接端。
在一些实施例中，所述显示面板还包括多条栅极线，沿着所述行方向延伸，并且两相邻行画素之间设置有两条栅极线；所述多条栅极线包括第一栅级线和第二栅极线，分别设置在第一行画素的两侧，并且所述第一栅级线和所述第二栅极线分别与所述第一行画素中的至少一画素连接；以及在所述第一行画素中，正极性的画素与负极性的画素的数量相等。
 有益效果
相较于先前技术，本申请通过在显示面板中设置与主数据线连接的次数据线，可在使用较少数量的用于连接源极驱动器和显示面板的连接件的同时，实现了同一行画素中正极性的画素与负极性的画素的数量相近，进而改善显示面板的串扰问题和提升显示面板的画面质量。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1显示现有技术中的显示面板的示意图。
图2显示根据本申请的第一实施例的显示面板的画素电路示意图。
图3显示根据本申请的第二实施例的显示面板的画素电路示意图。
图4显示根据本申请的实施例的显示装置的示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参照图2，其显示根据本申请的实施例的显示面板200的画素电路示意图，显示面板200包含多个画素、多条数据线（包含主数据线D1-1至D8-1、次数据线D1-2至D8-2、多条连接线C1-C8）、多条栅极线G1-G6。多个画素沿着行方向和列方向阵列排列，并且包含红色画素R、绿色画素G和蓝色画素B。多条数据线沿着列方向延伸，以及多条栅极线沿着行方向延伸。
如图2所示，每一数据线包含主数据线、次数据线和连接线，如第一数据线包含第一主数据线D1-1、第一次数据线D1-2和第一连接线C1，第二数据线包含第二主数据线D2-1、第二次数据线D2-2和第二连接线C2。第一主数据线D1-1和第一次数据线D1-2通过第一连接线C1连接，第二主数据线D2-1和第二次数据线D2-2通过第二连接线C2连接。第一主数据线D1-1和第二主数据线D2-1相邻，且第一次数据线D1-2和第二次数据线D2-2相邻。应当注意的是，第一数据线不限定于显示面板200中排列在第一条的数据线，可以为任意一条数据线，即，第一数据线和第二数据线应当理解为显示面板200中任意相邻的两条数据线。
如图2所示，第一主数据线D1-1与第一次数据线D1-2之间间隔M列画素。第二主数据线D2-1与第二次数据线D2-2也间隔M列画素，其中M为大于或等于1的正整数。在本实施例中，M为4，即连接的主数据线与次数据线间隔四列画素。在一些实施例中，M较佳地小于或等于2，这可有效地避免因为连接主数据线与次数据线的连接线包含过多的跨线设计所导致的静电放电（electrostatic discharge，ESD）的风险和降低画素P的充电速度。
在本实施例中，连接的一组数据线中，主数据线与排列在至少两列的画素电连接，次数据线与排列在至少另两列的画素电连接。应当理解的是，数据线与排列在一特定列的画素连接意旨与该列画素中的至少一画素连接，而非与该列画素的所有画素连接。如图2所示，同一条主数据线或次数据线交替地连接排列在两列的画素。举例来说，第一主数据线D1-1设置在第一列画素和第二列画素之间，且第一主数据线D1-1交替地连接排列在第一列的画素和排列在第二列的画素。又，第一次数据线D1-2设置在第N列画素和第N+1列画素之间，且第一次数据线D1-2交替地连接排列在第N列的画素和排列在第N+1列的画素，其中N为大于或等于1的正整数。在本实施例中，N为5。即，第一次数据线D1-2设置在第五列画素和第六列画素之间，且交替地连接排列在第五列的画素和排列在第六列的画素。第二主数据线D2-1设置在第二列画素和第三列画素之间，且第二主数据线D2-1交替地连接排列在第二列的画素和排列在第三列的画素。又，第二次数据线D2-2设置在第六列画素和第七列画素之间，且第二次数据线D2-2交替地连接排列在第六列的画素和排列在第七列的画素。
应当理解的是，在本实施例中，数据线的交替连接意旨数据线连接同一列画素中的奇数行画素或偶数行画素。也就是说，交替地连接包含同一条数据线连接至一列画素中的奇数行画素和连接至另一相邻列画素中的偶数行画素，或者是同一条数据线连接至两相邻列画素中的奇数行画素，或者是同一条数据线连接至两相邻列画素中的偶数行画素。如图2所示，第一主数据线D1-1连接第一行第二列的画素和第二行第一列的画素。因此，对于第一主数据线D1-1而言，数据线的交替连接意旨第一主数据线D1-1连接至第一列画素中的偶数行画素和连接至第二列画素中的奇数行画素。同理，第二主数据线D2-1连接第一行第三列的画素和第二行第二列的画素。对于第二主数据线D2-1而言，数据线的交替连接意旨第二主数据线D2-1连接至第二列画素中的偶数行画素和连接至第三列画素中的奇数行画素。
如图2所示，同一行画素通过相邻的两条栅极线控制，且两相邻行画素之间设置有两条栅极线。举例来说，第一行画素设置在第一栅极线G1和第二栅极线G2之间，且第一行画素和第二行画素之间设置有第二栅极线G2和第三栅极线G3。在本实施例中，同一行画素与相邻的两条栅极线对应连接，如第一栅极线G1与第一行画素中的至少一画素对应连接，以及第二栅极线G2与第一行画素中的至少另一画素对应连接。同理，第三栅极线G3与第二行画素中的至少一画素对应连接，以及第四栅极线G4与第二行画素中的至少一画素对应连接。应当理解的是，栅极线的对应连接包含有序或无序的连接，也就是说，同一行画素可以相同或不同数量的画素为间隔与相邻的两条栅极线对应连接。如图2所示，在一行画素中以四个画素为一组，与相邻的两条栅极线交替地连接。举例来说，第一栅极线G1与第一行画素中第一至四列和第九至十二列的画素连接。第二栅极线G2与第一行画素中第五至八列和第十三至十六列的画素连接。在一些实施例中，同一行画素可以相同或不同数量的画素为间隔与相邻的两条栅极线对应连接。
在本实施例中，通过同一条数据线交替地连接排列在不同列的画素以及同一行画素与相邻的两条栅极线对应地连接的设计，实现了数据线共享（data line share，DLS）架构。因此，在本实施例中，用于连接源极驱动器和显示面板的连接件的数量可减少为传统架构的一半，进而降低了因为设置多个连接件而引起的贴合不良的风险和降低成本。
应当理解的是，在本实施例中，显示面板200包含液晶。每个画素对应的液晶单元具有各自的信号电极。为了防止液晶极化，需要通过交替变更极性电场来驱动液晶单元。即，在连续两帧时反转施加每一液晶单元的电压极性。对于液晶单元，如果在当前时间帧中将电压极性驱动为正极性时，则随后在下一时间帧中，将电压极性驱动为负极性。
如图2所示，连接的主数据线和次数据线配置为传递相同极性的信号，以及两相邻的数据线配置为传递相反极性的信号。举例来说，第一主数据线D1-1与第一次数据线D1-2配置为传递第一极性的信号，以及第二主数据线D2-1与第二次数据线D2-2配置为传递与第一极性相反的第二极性的信号，以此类推。如图2所示，当第一主数据线D1-1与第一次数据线D1-2配置为传递负极性的信号时，第二主数据线D2-1与第二次数据线D2-2配置为传递正极性的信号。
如图2所示，同一列画素为相同的颜色。又，同一列画素中的两相邻画素的极性相反。举例来说，当第一主数据线D1-1与第一次数据线D1-2配置为传递负极性的信号时，第一行第一列的画素为正极性，第二行第一列的画素为负极性，第三行第一列的画素为正极性，以此类推。
特殊画面的水平串扰的产生原因与画素的极性强相关。当显示的画面中，同一行画素中正极性的画素与负极性的画素的数量越相近，可消除与共通电极的耦合电容，进而使得显示面板的水平串扰越轻微。
故而，如图2所示，在同一行画素中，画素的极性呈现“-+ - -+ - + +”或“+ - ++-+--”的排列规则。在显示特殊画面时，同一行画素中，若相邻两个画素具有相反的列反转电压极性模式，可减少整体感知的串扰。举例来说，当显示面板200显示以两列红线和两列白线交替排列的特殊画面，以一列红线和两列白线交替排列的特殊画面，或者是以一列白线和一列黑线交替排列的特殊画面时，同一行画素中连接同一条栅极线的正极性的画素与负极性的画素的数量相同。又，当显示面板200显示包含连续的多个W文字的特殊画面时，同一行画素中连接同一条栅极线的正极性的画素与负极性的画素的比值介于3/4至1之间。又，当显示面板200显示以两列白线和两列黑线交替排列的特殊画面时，同一行画素中连接同一条栅极线的正极性的画素与负极性的画素的比值介于2/3至3/4之间。由此可知，当显示面板200显示上述举例的五种特殊画面时，水平串扰发生的风险低，进而提高显示面板的画面质量。此外，在同一行画素中，每间隔一个或两个画素，画素的极性反转，即，实现了行方向的（1+2）点反转（1+2 dot inversion）驱动。
应当理解的是，如果两相邻画素施加的电压大小相同但极性相反时，能消除与对公共电极产生的耦合电容，进而避免串扰发生。具体来说，画素与数据线之间会产生耦合电容，且耦合电容的数值与画素和数据线之间的距离成反比。也就是说，画素和数据线之间的距离越大，两者的电容值越小。如图2所示，由于每一画素的相对两侧边皆邻近数据线，且画素的侧边与数据线之间无设置另一画素。两相邻的数据线配置为传递相反极性的信号，故每一画素的两侧边的耦合电容的极性相反，使得每一画素与其中之一数据线之间的耦合电容相近于与另一数据线之间的耦合电容。因此，本申请可改善画素与其两侧相邻的两数据线的距离相差较大，画素两侧耦合电容不对称引起的画质粗糙和垂直串扰问题。
参照图3，其显示根据本申请的第二实施例的显示面板300的画素电路示意图，显示面板300包含多个画素、多条数据线（包含主数据线D1-1至D4-1、次数据线D1-2至D4-2、多条连接线C1-C4）、多条栅极线G1-G4。多个画素沿着行方向和列方向阵列排列，并且包含红色画素R、绿色画素G和蓝色画素B。多条数据线沿着列方向延伸，以及多条栅极线沿着行方向延伸。
如图3所示，每一数据线包含主数据线、次数据线和连接线，如第一数据线包含第一主数据线D1-1、第一次数据线D1-2和第一连接线C1，第二数据线包含第二主数据线D2-1、第二次数据线D2-2和第二连接线C2。第一主数据线D1-1和第一次数据线D1-2通过第一连接线C1连接，第二主数据线D2-1和第二次数据线D2-2通过第二连接线C2连接。第一主数据线D1-1和第二主数据线D2-1相邻，且第一次数据线D1-2和第二次数据线D2-2相邻。应当注意的是，第一数据线不限定于显示面板300中排列在第一条的数据线，可以为任意一条数据线，即，第一数据线和第二数据线应当理解为显示面板300中任意相邻的两条数据线。
如图3所示，第一主数据线D1-1与第一次数据线D1-2之间间隔M列画素。第二主数据线D2-1与第二次数据线D2-2也间隔M列画素。在本实施例中，M为4，即连接的主数据线与次数据线间隔四列画素。在一些实施例中，M较佳地小于或等于2，这可有效地避免因为连接主数据线与次数据线的连接线包含过多的跨线设计所导致的静电放电的风险和降低画素P的充电速度。
如图3所示，在本实施例中，连接的一组数据线中，主数据线与排列在四列的画素电连接，次数据线与排列在另四列的画素电连接。举例来说，第一主数据线D1-1与排列在第一列至第四列画素电连接。第一次数据线D1-2与排列在第N列至第N+3列的画素电连接。在本实施例中，N为5。即，第一次数据线D1-2与排列在第五列至第八列的画素电连接。
如图3所示，在奇数行画素中，连接的主数据线和次数据线与各自对应的四列画素的其中两列的画素电连接。在偶数行画素中，连接的主数据线和次数据线与各自对应的四列画素的另外两列的画素电连接。举例来说，在奇数行画素中，第一主数据线D1-1与对应的四列画素中的第二列和第三列的画素电连接，第一次数据线D1-2与对应的四列画素的第一列和第四列的画素电连接。又，在奇数行画素中，第二主数据线D2-1与对应的四列画素中的第二列和第四列的画素电连接，第二次数据线D2-2与对应的四列画素的第一列和第三列的画素电连接。在所述偶数行画素中，第一主数据线D1-1与对应的四列画素中的第一列和第四列的画素电连接，第一次数据线D1-2与对应的四列画素的第二列和第三列的画素电连接。又，在所述偶数行画素中，第二主数据线D2-1与对应的四列画素中的第一列和第三列的画素电连接，第二次数据线D2-2与对应的四列画素的第二列和第四列的画素电连接。
如图3所示，同一列画素与不同的数据线对应连接。其中之一主或次数据线与排列在第X列、第X+1列、第X+2列、第X+3列的画素电连接，以及另一相邻的主或次数据线与排列在第X+2列、第X+3列、第X+4列、第X+5列的画素电连接，其中X为大于或等于1的正整数。举例来说，第一主数据线D1-1与排列在第一列至第四列的画素电连接，以及第二主数据线D2-1与排列在第三列至第六列的画素电连接。又，第一次数据线D1-2与排列在第五列至第八列的画素电连接，以及第二次数据线D2-2与排列在第七列至第十列的画素电连接。在奇数行画素中，第一主数据线D1-1与排列在第二列和第三列的画素电连接，第二主数据线D2-1与排列在第四列和第六列的画素电连接，第一次数据线D1-2与排列在第五列和第八列的画素电连接，第二次数据线D2-2与排列在第七列和第九列的画素电连接。在偶数行画素中，第一主数据线D1-1与排列在第一列和第四列的画素电连接，第二主数据线D2-1与排列在第三列和第五列的画素电连接，第一次数据线D1-2与排列在第六列和第七列的画素电连接，第二次数据线D2-2与排列在第八列和第十列的画素电连接。
如图3所示，同一行画素通过相邻的两条栅极线控制，且两相邻行画素之间设置有两条栅极线。举例来说，第一行画素设置在第一栅极线G1和第二栅极线G2之间，且第一行画素和第二行画素之间设置有第二栅极线G2和第三栅极线G3。在本实施例中，同一行画素与相邻的两条栅极线对应连接，如第一栅极线G1与第一行画素中的至少一画素对应连接，以及第二栅极线G2与第一行画素中的至少另一画素对应连接。同理，第三栅极线G3与第二行画素中的至少一画素对应连接，以及第四栅极线G4与第二行画素中的至少一画素对应连接。应当理解的是，栅极线的对应连接包含有序或无序的连接，也就是说，同一行画素可以相同或不同数量的画素为间隔与相邻的两条栅极线对应连接。在本实施例中，通过同一条数据线连接不同列的画素以及同一行画素与两条栅极线对应地连接的设计，实现了数据线共享架构。因此，在本实施例中，用于连接源极驱动器和显示面板的连接件的数量可减少为传统架构的一半，进而降低了因为设置多个连接件而引起的贴合不良的风险和降低成本。
应当理解的是，在本实施例中，显示面板300包含液晶。每个画素对应的液晶单元具有各自的信号电极。为了防止液晶极化，需要通过交替变更极性电场来驱动液晶单元。即，在连续两帧时反转施加每一液晶单元的电压极性。对于液晶单元，如果在当前时间帧中将电压极性驱动为正极性时，则随后在下一时间帧中，将电压极性驱动为负极性。
如图3所示，连接的主数据线和次数据线配置为传递相同极性的信号，以及两相邻的数据线配置为传递相反极性的信号。举例来说，第一主数据线D1-1与第一次数据线D1-2配置为传递第一极性的信号，以及第二主数据线D2-1与第二次数据线D2-2配置为传递与第一极性相反的第二极性的信号，以此类推。如图3所示，当第一主数据线D1-1与第一次数据线D1-2配置为传递正极性的信号时，第二主数据线D2-1与第二次数据线D2-2配置为传递负极性的信号。
特殊画面的水平串扰的产生原因与画素的极性强相关。当显示的画面中，同一行画素中正极性的画素与负极性的画素的数量越相近，可消除与共通电极的耦合电容，进而使得显示面板的水平串扰越轻微。
故而，如图3所示，同一列画素为相同的颜色，且同一列画素中的两相邻画素的极性相反。又，在同一行画素中，画素的极性呈现“-+ - -+ - + +”或“+ - ++-+--”的排列规则。在显示特殊画面时，同一行画素中，若相邻两个画素具有相反的列反转电压极性模式，可减少整体感知的串扰。举例来说，当显示面板300显示以一列红线和两列白线交替排列的特殊画面，以一列白线和一列黑线交替排列的特殊画面，以两列红线和两列白线交替排列的特殊画面，或者是以两列白线和两列黑线交替排列的特殊画面时，同一行画素中连接同一条栅极线的正极性的画素与负极性的画素的数量相同。又，当显示面板300显示包含连续的多个W文字的特殊画面时，同一行画素中连接同一条栅极线的两相反极性的画素的比值介于3/4至1之间。由此可知，当显示上述举例的五种特殊画面时，水平串扰发生的风险低，进而提高显示面板的画面质量。此外，在一行画素中，每间隔一个或两个画素，画素的极性反转，即，实现了行方向的（1+2）点反转（1+2 dot inversion）驱动。
参照图4，其显示根据本申请的实施例的显示装置的示意图。显示装置20包含显示面板100、控制器21、栅极驱动器22、源极驱动器23和多个连接件24。显示面板100包含扇出区101、连接区102和显示区103，其中连接区102在扇出区101和显示区103之间。应当理解的是，显示面板100可为上述第一实施例的显示面板200或上述第二实施例的显示面板300。图2的显示面板200和图3的显示面板300仅示出对应于图4的显示面板100的连接区和显示区。
如图4所示，控制器21与电源供应器连接以将电力提供至显示装置20，进而控制显示装置20开启或关闭。控制器21可包含定时控制器、微处理器、伽马电压产生器等。控制器21与栅极驱动器22和源极驱动器23连接，且栅极驱动器22和源极驱动器23与显示面板100连接。连接件24配置为将源极驱动器23结合（bonding）至显示面板100。连接件24可包含但不限于薄膜覆晶封装（chip on film，COF）。显示面板100包含多条数据线DL、多条栅极线GL和多个画素P，其中多条数据线DL沿着列方向延伸，多条栅极线GL沿着行方向延伸，多个画素P沿着行方向和列方向阵列排列。
如图4所示，源极驱动器23通过多条数据线DL与多个画素P对应连接。源极驱动器23通过多条栅极线GL与多个画素P对应连接。多个画素P包含不同的颜色画素，如红色画素、绿色画素、蓝色画素或白色画素，配置为对应发出红色、绿色、蓝色或白色光。应当注意的是，在显示面板100的两相邻数据线DL之间可设置一列或一列以上的画素P。
如图4所示，控制器21配置为产生栅极控制信号和数据控制信号。栅极驱动器22根据栅极控制信号产生栅极信号，并且通过多条栅极线GL将栅极信号传递至多个画素P。另一方面，控制器21将数据控制信号（如模拟视频信号、参考伽马电压信号等）传送至源极驱动器23。源极驱动器23根据数据控制信号产生对应的数据信号，并且通过多条数据线DL将数据信号传递至多个画素P。
如图4所示，扇出区101设置有多条布线W。连接区102设置有多条数据线DL和多条连接线，如第一连接线C1和第二连接线C2。显示区103设置有多个画素P、多条数据线DL和多条栅极线GL，其中多条数据线DL从连接区102延伸至显示区103。在扇出区101的多条布线W配置为通过连接件24连接源极驱动器23和对应的多条数据线DL的主数据线（如第一主数据线D1-1、第二主数据线D2-1等）。在显示装置20开启时，控制器21获取关于一帧画面的图像数据信号以产生对应的栅极控制信号和数据控制信号，进而控制显示面板100的显示区103显示画面。
如图4所示，在本实施例中，连接主数据线与次数据线的连接线设置在连接区102。具体地，连接线设置在位于扇出区101的多条布线W和位于显示区103的第一行画素P之间。也就是说，连接线设置在布线W的一端和第一行画素P之间，并且所述端为布线W和对应的主数据线的连接端。通过将连接线设置在连接区102，而不设置在扇出区101，可避免因扇出区101的线路布局过于密集所导致的ESD的风险和降低画素P的充电速度。
综上所述，本申请通过在显示面板中设置与主数据线连接的次数据线，使得用于连接源极驱动器和显示面板的连接件的数量可减少为传统架构的一半，进而降低了因为设置多个连接件而引起的贴合不良的风险和降低成本。再者，通过本申请的显示面板的画素电路，可实现同一行画素中正极性的画素与负极性的画素的数量相近，进而改善显示面板的水平串扰问题和提升显示面板的画面质量。
以上对本申请的实施例所提供的一种显示面板进行了详细介绍。本文中应用了具体实施例对本申请的原理及实施方式进行了阐述。以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想。本领域的普通技术人员应当理解，其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (18)

  1. 一种显示面板，包括：
    多个画素，沿着行方向和列方向阵列排列；
    第一主数据线，沿着所述列方向延伸，其中所述第一主数据线与排列在至少两列的画素电连接；
    第一次数据线，沿着所述列方向延伸，其中所述第一次数据线与所述第一主数据线间隔M列画素，并且所述第一次数据线与排列在至少另两列的画素电连接；
    第一连接线，连接所述第一主数据线与所述第一次数据线；
    第二主数据线，沿着所述列方向延伸，且与所述第一主数据线相邻；
    第二次数据线，沿着所述列方向延伸，且与所述第一次数据线相邻，其中所述第二次数据线与所述第二主数据线间隔M列画素，并且所述第二主数据线和所述第二次数据线分别与排列在至少两列的画素电连接；
    第二连接线，连接所述第二主数据线与所述第二次数据线，其中所述第一主数据线与所述第一次数据线配置为传递第一极性的信号，以及所述第二主数据线与所述第二次数据线配置为传递与所述第一极性相反的第二极性的信号；以及
    多条栅极线，沿着所述行方向延伸，其中两相邻行画素之间设置有两条栅极线，所述多条栅极线包括第一栅级线和第二栅极线，分别设置在第一行画素的两侧，所述第一栅级线和所述第二栅极线分别与所述第一行画素中的至少一画素连接，以及在所述第一行画素中，正极性的画素与负极性的画素的数量相等。
  2. 如权利要求1所述的显示面板，其中所述第一主数据线交替地连接排列在第一列的画素和排列在第二列的画素，以及所述第一次数据线交替地连接排列在第N列的画素和排列在第N+1列的画素；以及
    所述第二主数据线交替地连接排列在所述第二列的画素和排列在第三列的画素，以及所述第二次数据线交替地连接排列在所述第N+1列的画素和列在第N+2列的画素。
  3. 如权利要求2所述的显示面板，其中所述第一主数据线连接第一行第二列的画素和第二行第一列的画素，以及所述第二主数据线连接第一行第三列的画素和第二行第二列的画素。
  4. 如权利要求1所述的显示面板，其中所述第一主数据线与排列在四列的画素电连接，以及所述第一次数据线与排列在另四列的画素电连接；
    在奇数行画素中，所述第一主数据线和所述第一次数据线与各自对应的四列画素的其中两列的画素电连接；以及
    在偶数行画素中，所述第一主数据线和所述第一次数据线与各自对应的四列画素的另外两列的画素电连接。
  5. 如权利要求4所述的显示面板，其中在所述奇数行画素中，所述第一主数据线与对应的四列画素中的第二列和第三列的画素电连接，所述第一次数据线与对应的四列画素的第一列和第四列的画素电连接；以及
    在所述偶数行画素中，所述第一主数据线与对应的四列画素中的第一列和第四列的画素电连接，所述第一次数据线与对应的四列画素的第二列和第三列的画素电连接。
  6. 如权利要求5所述的显示面板，其中所述第二主数据线与排列在四列的画素电连接，以及所述第二次数据线与排列在另四列的画素电连接；
    在奇数行画素中，所述第二主数据线和所述第二次数据线与各自对应的四列画素的其中两列的画素电连接；以及
    在偶数行画素中，所述第二主数据线和所述第二次数据线与各自对应的四列画素的另外两列的画素电连接。
  7. 如权利要求6所述的显示面板，其中所述第一主数据线与排列在第X列、第X+1列、第X+2列、第X+3列的画素电连接，以及第二主数据线与排列在第X+2列、第X+3列、第X+4列、第X+5列的画素电连接；
    在所述奇数行画素中，所述第一主数据线与排列在第X+1列和第X+2列的画素电连接，以及所述第二主数据线与排列在第X+3列和第X+5列的画素电连接；以及
    在所述偶数行画素中，所述第一主数据线与排列在第X列和第X+3列的画素电连接，以及所述第二主数据线与排列在第X+2列和第X+4列的画素电连接。
  8. 如权利要求1所述的显示面板，其中所述显示面板还包含：
    源极驱动器；以及
    布线，连接所述源极驱动器和所述第一主数据线，其中所述第一连接线设置在所述布线的一端和第一行画素之间，以及所述端为所述布线和所述第一主数据线的连接端。
  9. 一种显示面板，包括：
    多个画素，沿着行方向和列方向阵列排列；
    第一主数据线，沿着所述列方向延伸，其中所述第一主数据线与排列在至少两列的画素电连接；
    第一次数据线，沿着所述列方向延伸，其中所述第一次数据线与所述第一主数据线间隔M列画素，并且所述第一次数据线与排列在至少另两列的画素电连接；以及
    第一连接线，连接所述第一主数据线与所述第一次数据线。
  10. 如权利要求9所述的显示面板，其中所述显示面板还包括：
    第二主数据线，沿着所述列方向延伸，且与所述第一主数据线相邻；
    第二次数据线，沿着所述列方向延伸，且与所述第一次数据线相邻，其中所述第二次数据线与所述第二主数据线间隔M列画素，并且所述第二主数据线和所述第二次数据线分别与排列在至少两列的画素电连接；以及
    第二连接线，连接所述第二主数据线与所述第二次数据线，其中所述第一主数据线与所述第一次数据线配置为传递第一极性的信号，以及所述第二主数据线与所述第二次数据线配置为传递与所述第一极性相反的第二极性的信号。
  11. 如权利要求10所述的显示面板，其中所述第一主数据线交替地连接排列在第一列的画素和排列在第二列的画素，以及所述第一次数据线交替地连接排列在第N列的画素和排列在第N+1列的画素；以及
    所述第二主数据线交替地连接排列在所述第二列的画素和排列在第三列的画素，以及所述第二次数据线交替地连接排列在所述第N+1列的画素和列在第N+2列的画素。
  12. 如权利要求11所述的显示面板，其中所述第一主数据线连接第一行第二列的画素和第二行第一列的画素，以及所述第二主数据线连接第一行第三列的画素和第二行第二列的画素。
  13. 如权利要求10所述的显示面板，其中所述第一主数据线与排列在四列的画素电连接，以及所述第一次数据线与排列在另四列的画素电连接；
    在奇数行画素中，所述第一主数据线和所述第一次数据线与各自对应的四列画素的其中两列的画素电连接；以及
    在偶数行画素中，所述第一主数据线和所述第一次数据线与各自对应的四列画素的另外两列的画素电连接。
  14. 如权利要求13所述的显示面板，其中在所述奇数行画素中，所述第一主数据线与对应的四列画素中的第二列和第三列的画素电连接，所述第一次数据线与对应的四列画素的第一列和第四列的画素电连接；以及
    在所述偶数行画素中，所述第一主数据线与对应的四列画素中的第一列和第四列的画素电连接，所述第一次数据线与对应的四列画素的第二列和第三列的画素电连接。
  15. 如权利要求14所述的显示面板，其中所述第二主数据线与排列在四列的画素电连接，以及所述第二次数据线与排列在另四列的画素电连接；
    在奇数行画素中，所述第二主数据线和所述第二次数据线与各自对应的四列画素的其中两列的画素电连接；以及
    在偶数行画素中，所述第二主数据线和所述第二次数据线与各自对应的四列画素的另外两列的画素电连接。
  16. 如权利要求15所述的显示面板，其中所述第一主数据线与排列在第X列、第X+1列、第X+2列、第X+3列的画素电连接，以及第二主数据线与排列在第X+2列、第X+3列、第X+4列、第X+5列的画素电连接；
    在所述奇数行画素中，所述第一主数据线与排列在第X+1列和第X+2列的画素电连接，以及所述第二主数据线与排列在第X+3列和第X+5列的画素电连接；以及
    在所述偶数行画素中，所述第一主数据线与排列在第X列和第X+3列的画素电连接，以及所述第二主数据线与排列在第X+2列和第X+4列的画素电连接。
  17. 如权利要求9所述的显示面板，其中所述显示面板还包含：
    源极驱动器；以及
    布线，连接所述源极驱动器和所述第一主数据线，其中所述第一连接线设置在所述布线的一端和第一行画素之间，以及所述端为所述布线和所述第一主数据线的连接端。
  18. 如权利要求9所述的显示面板，其中所述显示面板还包括多条栅极线，沿着所述行方向延伸，并且两相邻行画素之间设置有两条栅极线；
    所述多条栅极线包括第一栅级线和第二栅极线，分别设置在第一行画素的两侧，并且所述第一栅级线和所述第二栅极线分别与所述第一行画素中的至少一画素连接；以及
    在所述第一行画素中，正极性的画素与负极性的画素的数量相等。
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