WO2023035366A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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WO2023035366A1
WO2023035366A1 PCT/CN2021/125023 CN2021125023W WO2023035366A1 WO 2023035366 A1 WO2023035366 A1 WO 2023035366A1 CN 2021125023 W CN2021125023 W CN 2021125023W WO 2023035366 A1 WO2023035366 A1 WO 2023035366A1
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trench
bit line
active region
semiconductor structure
layer
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PCT/CN2021/125023
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English (en)
French (fr)
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张俊逸
李新
应战
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长鑫存储技术有限公司
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Publication of WO2023035366A1 publication Critical patent/WO2023035366A1/zh

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  • the present disclosure relates to the technical field of semiconductors, in particular to a bit line structure and a preparation method thereof, a semiconductor structure and a preparation method thereof.
  • Dynamic Random Access Memory is a semiconductor memory, the main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit (bit) is 1 or 0.
  • the purpose of the present disclosure is to provide a bit line structure and its preparation method, a semiconductor structure and its preparation method to solve the problem of poor signal transmission performance of highly integrated dynamic random access memory in the prior art.
  • a method for fabricating a semiconductor structure may include:
  • a substrate is provided, and criss-cross isolation layers are formed on the substrate;
  • a gate is formed around the conductive channel.
  • trenches are formed on the substrate, which may specifically be:
  • Grooves are formed on the substrate by a dry etching process.
  • forming the bit line in the trench may include:
  • the bit line metal layer includes a stacked first barrier layer, a metal layer and a second barrier layer;
  • a bit line metal layer and a first sacrificial layer are sequentially deposited in the trench by a deposition process to obtain a first filling structure that fills the trench, which can be specifically:
  • a first barrier layer, a bit line metal, a second barrier layer and a first sacrificial layer are sequentially deposited inside the trench by a deposition process to obtain a first filling structure filling the trench.
  • bit line is formed in the trench before the bit line metal layer and the first sacrificial layer are sequentially deposited in the trench by a deposition process to obtain the first filling structure filling the trench,
  • bit line metal layer is sequentially deposited in the trench by a deposition process to obtain the first filling structure filling the trench,
  • first sacrificial layer are sequentially deposited in the trench by a deposition process to obtain the first filling structure filling the trench
  • the method for preparing the semiconductor structure further includes:
  • Part of the second sacrificial layer is removed by etching, and the remaining part of the second sacrificial layer is used to support the bit line metal layer.
  • etching and removing part of the second sacrificial layer may specifically be:
  • a part of the second sacrificial layer is removed by wet etching.
  • the region of the first filling structure close to the sidewall of the trench is removed by etching, so that there is a gap between the first filling structure and the sidewall of the trench, which may specifically be:
  • the region of the first filling structure close to the sidewall of the trench is removed by dry etching, so that there is a gap between the first filling structure and the sidewall of the trench.
  • the deposition process may be:
  • conductive channels there are multiple conductive channels, and gates are formed around the conductive channels, which may include:
  • a conductive layer is filled between the plurality of conductive channels, and the gate oxide dielectric layer and the conductive layer form a gate.
  • the method for fabricating the semiconductor structure may further include:
  • the second active region is deposited on the conductive layer by epitaxial growth process.
  • the method for preparing the semiconductor structure may further include:
  • the second active region is patterned and etched to form a columnar active region structure.
  • a semiconductor structure is provided, and the semiconductor structure may include:
  • bit line is located in the trench
  • first active region covers the bit line and fills the trench
  • the columnar conductive channels are located in the first active region
  • the grid, the columnar grid is located between a plurality of columnar conductive channels.
  • it may also include:
  • the second active area, the second active area is located on the columnar conductive channel.
  • the second active region may be columnar.
  • the materials of the first active region and the second active region may be:
  • Silicon material doped with n-type impurities Silicon material doped with n-type impurities
  • Silicon germanium material doped with n-type impurities Silicon germanium material doped with n-type impurities
  • Silicon germanium material doped with P-type impurities.
  • the method in the embodiment of the present disclosure provides a substrate; forms a trench on the substrate; forms a bit line in the trench; fills the trench with an epitaxial growth process and deposits it on the surface of the substrate to form a first active region, the first active region Covering the bit line; patterning the first active area to form a columnar conductive channel; forming a gate around the conductive channel.
  • the first source region can be wrapped around the bit line, which increases the contact area between the first active region and the bit line, reduces the contact resistance between the first active region and the bit line, and improves the contact resistance between the first active region and the bit line.
  • the charge transmission speed ensures the signal transmission performance.
  • FIG. 1 is a schematic flow diagram of a method for preparing a semiconductor structure in an exemplary embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a substrate structure in an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a substrate structure in which grooves are formed in an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of forming a first filling structure in an exemplary embodiment of the present disclosure
  • Fig. 5 is a schematic structural diagram after etching a gap in an exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of removing the entire first sacrificial layer by etching in an exemplary embodiment of the present disclosure
  • Fig. 7 is a schematic structural diagram of etching and removing part of the first sacrificial layer in an exemplary embodiment of the present disclosure
  • Fig. 8 is a schematic structural view of a first active region grown by epitaxial growth in an exemplary embodiment of the present disclosure
  • FIG. 9 is a schematic structural view of the epitaxially grown first active region in another exemplary embodiment of the present disclosure.
  • Fig. 10 is a schematic structural diagram of forming columnar conductive channels in an exemplary embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of forming a gate in an exemplary embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of depositing a bit line and a first sacrificial layer in an exemplary embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of depositing a bit line and a first sacrificial layer in another exemplary embodiment of the present disclosure
  • Fig. 14 is a schematic structural diagram after removing the sacrificial layer by wet etching in another exemplary embodiment of the present disclosure
  • Fig. 15 is a schematic structural diagram after etching gaps in another exemplary embodiment of the present disclosure.
  • Fig. 16 is a schematic diagram of a semiconductor structure prepared in an exemplary embodiment of the present disclosure.
  • Fig. 17 is a schematic diagram of a semiconductor structure in another exemplary embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a semiconductor structure in another exemplary embodiment of the present disclosure.
  • FIG. 1 A schematic diagram of a layer structure according to an embodiment of the present disclosure is shown in the accompanying drawings.
  • the figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity.
  • the shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.
  • the present disclosure provides a method of fabricating a semiconductor structure to solve this problem.
  • a method for preparing a semiconductor structure is provided, and the method may include:
  • S110 providing a substrate 1, on which a criss-cross isolation layer is formed;
  • S140 Filling the trench with an epitaxial growth process and depositing a first active region 4 on the surface of the substrate 1, the first active region 4 covers the bit line 2;
  • the first source region of the semiconductor structure prepared by the method in the above embodiment can be wrapped around the bit line 2, which increases the contact area between the first active region 4 and the bit line 2, and reduces the contact area between the first active region 4 and the bit line 2.
  • the contact resistance between the bit lines 2 increases the charge transmission speed and ensures the signal transmission performance.
  • step S110 providing a substrate 1 with criss-cross isolation layers formed on the substrate 1 .
  • the material of substrate 1 in this step includes but not limited to silicon crystal or germanium crystal, silicon on insulator (Silicon On Insulator, SOI) structure or epitaxial layer structure on silicon, compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide , indium phosphide, indium arsenide, or indium dysprosium), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof).
  • a silicon-on-insulator substrate 1 is provided, as shown in FIG. 2 .
  • step S120 forming a trench 11 in the substrate 1 , the trench passing through the isolation layer.
  • the formation of the trench 11 on the substrate 1 in this step may be performed by dry etching or wet etching, as long as the trench 11 with a predetermined size can be formed on the substrate 1 .
  • dry etching is performed in the substrate 1 to form trenches 11 , that is, bit line grooves, as shown in FIG. 3 .
  • step S130 forming the bit line 2 in the trench 11 .
  • the bit line 2 and the first sacrificial layer 31 may be sequentially deposited inside the trench 11 by a deposition method to obtain a first filling structure filling the trench 11 , as shown in FIG. 4 .
  • the deposition method may be a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process;
  • the material of the sacrificial layer may include silicon oxide;
  • the bit line metal layer may include a barrier layer and a metal layer, wherein the material of the barrier layer Titanium nitride (TiN) may be included as the barrier layer to improve wear resistance, reduce the coefficient of friction, and prevent sticking, and the material of the metal layer may include metal tungsten (W).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the region of the first filling structure close to the sidewall of the trench 11 is removed by etching, so that there is a gap between the first filling structure and the sidewall of the trench 11 , as shown in FIG. 5 .
  • the etching method may be dry etching with better controllability and flexibility, and dry etching is used to etch the first filling structure to obtain side-by-side gap structures corresponding to the channel region.
  • the first sacrificial layer 31 is removed by etching.
  • the etching method may be wet etching, using wet etching to remove the first sacrificial layer 31 on the structure of the bit line 2 to form the structure shown in Figure 6, or using wet etching to remove the bit line 2.
  • the first sacrificial layer 31 on the structure of the line 2 is shown in FIG. 7 .
  • the reason why wet etching is selected is that wet etching has the characteristics of good selectivity, good repeatability, high production efficiency, simple equipment, and low cost.
  • step S140 filling the trench 11 by epitaxial growth process and depositing the first active region 4 on the surface of the substrate 1 , and the first active region 4 covers the bit line 2 .
  • a semiconductor thin film is deposited and grown inside the trench 11 and on the surface of the substrate 1 by using an epitaxial growth process, that is, the first active region 4 covering the bit line 2 in this embodiment, as shown in FIG. 8 , the first active region 4
  • the source region 4 can be silicon (Si) material doped with n-type impurities; silicon (Si) material doped with p-type impurities; silicon germanium (SiGe) material doped with n-type impurities; or silicon doped with p-type impurities Germanium (SiGe) material, the wrapping contact method of the bit line 2 structure can greatly increase the contact area between the first active region 4 and the bit line 2, thereby reducing the contact area between the first active region 4 and the bit line 2.
  • epitaxial growth may be performed on the basis that the first sacrificial layer 31 is not completely etched away to form a structure with part of the first sacrificial layer 31 , as shown in FIG. 9 .
  • the first active region 4 can be wrapped around the bit line metal, which increases the contact area between the first active region 4 and the bit line metal, thus reducing the size of the second active region 4.
  • a contact resistance between the active region 4 and the metal of the bit line thereby increasing the charge transmission speed and ensuring the signal transmission performance.
  • an epitaxial process and dry etching are performed on the first active region 4 to form a columnar conductive channel 5, as shown in FIG. channel, add a layer of photomask, etch to form a columnar channel structure, the doping material of the channel can be the same (no junction type) or different (junction type) from the first active region 4, and the doped impurities can be It can be n-type or p-type.
  • step S160 forming a gate around the conductive channel 5 .
  • This step is to perform single atom deposition on the sidewall of the columnar conductive channel 5 to form a gate oxide dielectric layer 6; wherein there are multiple columnar conductive channels 5, and a conductive layer 7 is filled between the plurality of columnar conductive channels 5, and the gate oxide dielectric layer 6 and the conductive layer 7 form a gate, as shown in FIG. 11 .
  • the gate oxide dielectric layer 6 is formed by performing single-atom deposition on the sidewall of the columnar conductive channel 5. Specifically, single-atom deposition is performed on the sidewall, and the top and bottom dielectric layers are removed by dry etching, and finally the gate oxide dielectric layer 6 is formed. A flush sidewall gate oxide dielectric layer 6 is formed, and the material of the gate oxide dielectric layer 6 may include silicon oxide.
  • a conductive material is filled on the structure of the bit line 2 to form a conductive layer 7 surrounding the gate oxide dielectric layer 6, which can be filled with a conductive material in the gap between the gate oxide dielectric layer 6, and the conductive material can include Titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), tungsten (W), ruthenium (Ru), copper (Cu), etc., the above structures are polished to form the conductive layer 7 .
  • TiN Titanium nitride
  • TaN tantalum nitride
  • Al aluminum
  • W tungsten
  • Ru ruthenium
  • Cu copper
  • the first source region of the semiconductor structure obtained through the above steps can be wrapped around the bit line 2, which increases the contact area between the first active region 4 and the bit line 2, and reduces the contact area between the first active region 4 and the bit line 2.
  • the contact resistance between the bit lines 2 increases the charge transmission speed and ensures the signal transmission performance.
  • the trench 11 is formed on the substrate 1, which may specifically be:
  • a trench 11 is formed in the substrate 1 by a dry etching process.
  • forming the bit line 2 in the trench 11 may include:
  • the first sacrificial layer 31 is removed by etching to obtain the bit line 2 .
  • the bit line metal layer includes a stacked first barrier layer, a metal layer and a second barrier layer;
  • the bit line metal layer and the first sacrificial layer 31 are sequentially deposited in the trench 11 by a deposition process to obtain a first filling structure filling the trench 11, which may specifically be:
  • a first barrier layer, a bit line metal, a second barrier layer and a first sacrificial layer 31 are sequentially deposited inside the trench 11 by a deposition process to obtain a first filling structure filling the trench 11 .
  • the material of the first barrier layer and the second barrier layer may include titanium nitride (TiN), and the material of the metal layer may include tungsten metal (W).
  • TiN titanium nitride
  • W tungsten metal
  • bit line metal layer and the first sacrificial layer 31 are sequentially deposited in the trench 11 by a deposition process to obtain the first filling structure filling the trench 11.
  • Forming the bit line 2 may also include:
  • the method for preparing the semiconductor structure further includes:
  • Part of the second sacrificial layer 32 is removed by etching, and the remaining part of the second sacrificial layer 32 is used to support the metal layer of the bit line 2 .
  • two sacrificial layers, the first sacrificial layer 31 and the second sacrificial layer 32 are deposited inside the trench 11 .
  • the second sacrificial layer 32 , the first barrier layer, the metal layer, the second barrier layer and the first sacrificial layer 31 are sequentially deposited inside the trench 11 by a deposition method to form a first filling structure filling the trench 11 .
  • etch to remove the bottom portion of the second sacrificial layer 32 , and the remaining portion of the second sacrificial layer 32 is used to support the upper bit line 2 structure.
  • the bit line 2 greatly increases the contact area between the active area and the bit line 2, and reduces the contact resistance between the active area and the bit line 2, thereby increasing the charge transmission speed and ensuring the signal transmission performance.
  • part of the second sacrificial layer 32 is removed by etching, which may specifically be:
  • Part of the second sacrificial layer 32 is removed by wet etching, as shown in FIG. 14 .
  • the region of the first filling structure close to the sidewall of the trench 11 is etched away, so that there is a gap between the first filling structure and the sidewall of the trench 11 , specifically can be:
  • the region of the first filling structure close to the sidewall of the trench 11 is removed by dry etching, so that there is a gap between the first filling structure and the sidewall of the trench 11 .
  • the deposition process may be:
  • the method for fabricating the semiconductor structure may further include:
  • the second active region 8 is formed on the conductive layer 7 by epitaxial growth process.
  • the method for preparing the semiconductor structure may further include:
  • the second active region 8 is patterned and etched to form a columnar active region structure.
  • the method may further include: forming an insulating isolation structure 9 on the sidewall of the columnar second active region 8 , and the insulating isolation structure 9 surrounds the sidewall of the columnar second active region 8 .
  • the columnar second active region 8 of GAA is formed by using EPI
  • the doping material of the columnar second active region 8 can be the same as that of the first active region 4, a layer of photomask is added, and the columnar second active region 8 is formed after dry etching Structure: gaps between the plurality of columnar second active regions 8 are filled with an insulating material (silicon oxide, etc.) to form an insulating isolation structure 9 .
  • a semiconductor structure As shown in FIG. 17, in a second aspect of an embodiment of the present disclosure, a semiconductor structure is provided, and the semiconductor structure may include:
  • bit line 2 is located in the trench 11, and the trench passes through the isolation layer;
  • the first active region 4 covers the bit line 2 and fills the trench 11;
  • a plurality of columnar conductive channels 5, the columnar conductive channels 5 are located in the first active region 4;
  • the grid, the columnar grid is located between the plurality of columnar conductive channels 5 .
  • the material of substrate 1 in this step includes but not limited to silicon crystal or germanium crystal, silicon on insulator (Silicon On Insulator, SOI) structure or epitaxial layer structure on silicon, compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide , indium phosphide, indium arsenide, or indium dysprosium), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof).
  • the first source region of the semiconductor structure is wrapped around the bit line 2, which increases the contact area between the first active region 4 and the bit line 2, and reduces the distance between the first active region 4 and the bit line 2.
  • the contact resistance between them improves the charge transmission speed and ensures the signal transmission performance.
  • it may also include:
  • the second active region 8 , the second active region 8 is located on the columnar conductive channel 5 .
  • the second active region 8 may be columnar.
  • the first source region of the semiconductor structure in the above embodiment is wrapped around the bit line 2, which increases the contact area between the first active region 4 and the bit line 2, and reduces the distance between the first active region 4 and the bit line 2.
  • the contact resistance between them improves the charge transmission speed and ensures the signal transmission performance.
  • the materials of the first active region 4 and the second active region 8 may be:
  • Silicon material doped with n-type impurities Silicon material doped with n-type impurities
  • Silicon germanium material doped with n-type impurities Silicon germanium material doped with n-type impurities
  • Silicon germanium material doped with P-type impurities.

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Abstract

本公开公开了一种半导体结构及其制备方法,属于半导体技术领域,其中，半导体结构的制备方法，包括：提供衬底；于衬底形成沟槽；于沟槽内形成位线；利用外延生长工艺填充沟槽并在衬底表面沉积形成第一有源区，第一有源区包覆位线；图形化刻蚀第一有源区形成柱状导电通道；在导电通道周围形成栅极。该方法制备得到的半导体结构第一源区就可以包绕在位线的周围，增大了第一有源区与位线的接触面积，减小了第一有源区与位线之间的接触电阻，进而提高电荷传输速度，保证了信号传输性能。

Description

半导体结构及其制备方法
交叉引用
本公开基于申请号为202111045528.7、申请日为2021年09月07日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种位线结构及其制备方法、半导体结构及其制备方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种半导体存储器，主要的作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是1还是0。
近来，在半导体工业中，为了提高集成度，正在开发40nm以下的动态随机存取存储器。但是，目前开发的40nm以下的动态随机存取存储器，却存在随着集成度越高，信号传输性能下降的问题。
发明内容
本公开的目的是提供一种位线结构及其制备方法、半导体结构及其制备方法以解决现有技术中高集成度动态随机存取存储器信号传 输性能差的问题。
根据本公开实施例的第一方面，提供了一种半导体结构的制备方法，该方法可以包括：
提供衬底，衬底上形成有纵横交错的隔绝层；
于衬底形成沟槽，沟槽穿越隔绝层；
于沟槽内形成位线；
利用外延生长工艺填充沟槽并在衬底表面沉积形成第一有源区，第一有源区包覆位线；
图形化刻蚀第一有源区形成柱状导电通道；
在导电通道周围形成栅极。
在本公开的一些可选实施例中，于衬底形成沟槽，具体可以为：
利用干法刻蚀工艺于衬底形成沟槽。
在本公开的一些可选实施例中，于沟槽内形成位线，可以包括：
利用沉积工艺于沟槽内依次沉积位线金属层及第一牺牲层，得到充满沟槽的第一填充结构；
刻蚀去除第一填充结构靠近沟槽侧壁的区域，以使第一填充结构与沟槽侧壁之间留有间隙；
刻蚀去除第一牺牲层，得到位线。
在本公开的一些可选实施例中，位线金属层包括层叠的第一阻挡层、金属层及第二阻挡层；
利用沉积工艺于沟槽内依次沉积位线金属层及第一牺牲层，得到充满沟槽的第一填充结构，具体可以为：
利用沉积工艺于沟槽内部依次沉积第一阻挡层、位线金属、第二阻挡层及第一牺牲层，得到充满沟槽的第一填充结构。
在本公开的一些可选实施例中，在利用沉积工艺于沟槽内依次沉积位线金属层及第一牺牲层，得到充满沟槽的第一填充结构之前，于 沟槽内形成位线，还可以包括：
于沟槽内沉积形成第二牺牲层；
在刻蚀去除第一填充结构靠近沟槽侧壁的区域，以使第一填充结构与沟槽侧壁之间留有间隙之后，半导体结构的制备方法还包括：
刻蚀去除部分第二牺牲层，第二牺牲层的剩余部分用以支撑位线金属层。
在本公开的一些可选实施例中，刻蚀去除部分第二牺牲层，具体可以为：
利用湿法刻蚀去除部分第二牺牲层。
在本公开的一些可选实施例中，刻蚀去除第一填充结构靠近沟槽侧壁的区域，以使第一填充结构与沟槽侧壁之间留有间隙，具体可以为：
利用干法刻蚀去除第一填充结构靠近沟槽侧壁的区域，以使第一填充结构与沟槽侧壁之间留有间隙。
在本公开的一些可选实施例中，沉积工艺可以为：
化学气相沉积工艺；或
原子层沉积工艺。
在本公开的一些可选实施例中，导电通道为多个，在导电通道周围形成栅极，可以包括：
于柱状导电通道的侧壁沉积形成栅氧介质层；
于多个导电通道之间填充导电层，栅氧介质层与导电层构成栅极。
在本公开的一些可选实施例中，在导电通道周围形成栅极之后，半导体结构的制备方法，还可以包括：
利用外延生长工艺于导电层上沉积形成第二有源区。
在本公开的一些可选实施例中，在利用外延生长工艺于导电层上 沉积形成第二有源区之后，半导体结构的制备方法，还可以包括：
图形化刻蚀第二有源区形成柱状有源区结构。
根据本公开实施例的第二方面，提供一种半导体结构，该半导体结构可以包括：
衬底，衬底上有纵横交错的隔绝层和沟槽，沟槽穿越沟槽；
位线，位线位于沟槽内；
第一有源区，第一有源区包覆位线并填充沟槽；
多个柱状导电通道，柱状导电通道位于第一有源区；
栅极，柱状栅极位于多个柱状导电通道之间。
在本公开的一些可选实施例中，还可以包括：
第二有源区，第二有源区位于柱状导电通道之上。
在本公开的一些可选实施例中，第二有源区可以呈柱状。
在本公开的一些可选实施例中，第一有源区与第二有源区的材料可以为：
掺杂n型杂质的硅材料；
掺杂P型杂质的硅材料；
掺杂n型杂质的硅锗材料；或
掺杂P型杂质的硅锗材料。
本公开的上述技术方案具有如下有益的技术效果：
本公开实施例方法通过提供衬底；于衬底形成沟槽；于沟槽内形成位线；利用外延生长工艺填充沟槽并在衬底表面沉积形成第一有源区，第一有源区包覆位线；图形化刻蚀第一有源区形成柱状导电通道；在导电通道周围形成栅极。这样有第一源区就可以包绕在位线的周围，增大了第一有源区与位线的接触面积，减小了第一有源区与位线之间的接触电阻，进而提高电荷传输速度，保证了信号传输性能。
附图说明
图1是本公开一示例性实施例中半导体结构的制备方法流程示意图；
图2是本公开一示例性实施例中衬底结构示意图；
图3是本公开一示例性实施例中形成沟槽的衬底结构示意图；
图4是本公开一示例性实施例中形成第一填充结构的结构示意图；
图5是本公开一示例性实施例中刻蚀间隙后的结构示意图；
图6是本公开一示例性实施例中刻蚀除去完全第一牺牲层的结构示意图；
图7是本公开一示例性实施例中刻蚀除去部分第一牺牲层的结构示意图；
图8是本公开一示例性实施例中外延生长第一有源区的结构示意图；
图9是本公开另一示例性实施例中外延生长第一有源区的结构示意图；
图10是本公开一示例性实施例中形成柱状导电通道的结构示意图；
图11是本公开一示例性实施例中形成栅极的结构示意图；
图12是本公开一示例性实施例中沉积位线及第一牺牲层的结构示意图；
图13是本公开另一示例性实施例中沉积位线及第一牺牲层的结构示意图；
图14是本公开另一示例性实施例中利用湿法刻蚀去除牺牲层后的结构示意图；
图15是本公开另一示例性实施例中刻蚀间隙后的结构示意图；
图16是本公开一示例性实施例中制备得到半导体结构示意图；
图17是本公开另一示例性实施例中半导体结构示意图；
图18是本公开又一示例性实施例中半导体结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本公开进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的层结构示意图。这些图并非是按比例绘制的，其中为了清楚的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要说明的是，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，下面所描述的本公开不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
目前，为了提高动态随机存取存储器的集成度，均采用垂直沟道晶体管，但是，随着集成度越高，同时也存在着信号传输性能下降的 问题。发明人经研究发现导致信号传输性能下降的原因是位线接触结构与有源区之间存在接触电阻。为此，本公开提供半导体结构的制备方法以解决该问题。
下面结合附图，通过具体的实施例及其应用场景对本公开实施例提供的半导体结构的制备方法进行详细地说明。
如图1所示，根据本公开实施例的第一方面，提供了一种半导体结构的制备方法，该方法可以包括：
S110:提供衬底1，衬底上形成有纵横交错的隔绝层；
S120:于衬底1形成沟槽，沟槽穿越隔绝层；
S130:于沟槽内形成位线2；
S140:利用外延生长工艺填充沟槽并在衬底1表面沉积形成第一有源区4，第一有源区4包覆位线2；
S150:图形化刻蚀第一有源区4形成柱状导电通道5；
S160:在导电通道5周围形成栅极。
上述实施例方法制备的半导体结构第一源区就可以包绕在位线2的周围，增大了第一有源区4与位线2的接触面积，减小了第一有源区4与位线2之间的接触电阻，进而提高电荷传输速度，保证了信号传输性能。
为了更详细介绍，下面对上述步骤进行分别说明：
首先是步骤S110：提供衬底1，衬底1上形成有纵横交错的隔绝层。
本步骤中衬底1的材料包括但不限于硅晶体或锗晶体、绝缘体上硅(Silicon On Insulator，SOI)结构或硅上外延层结构、化合物半导体(例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、或镝化铟)、合金半导体(例如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或者它们的组合)。示例性的，提供绝缘体上硅衬底1，如图2所示。
接下来是步骤S120：于衬底1形成沟槽11，沟槽穿越隔绝层。
本步骤中的在衬底1上形成沟槽11可以是利用干法刻蚀也可以是湿法刻蚀，只要可以在衬底1上形成预设尺寸沟槽11即可。
示例性的，在衬底1内进行干法刻蚀以形成沟槽11，即位线凹槽，如图3所示。
接下来是步骤S130：于沟槽11内形成位线2。
在本步骤中，首先，可以是利用沉积法于沟槽11内部依次沉积位线2及第一牺牲层31，得到充满沟槽11的第一填充结构，如图4所示。
示例性的，沉积方法可以为化学气相沉积(CVD)工艺或原子层沉积(ALD)工艺；牺牲层的材料可以包括氧化硅；位线金属层可以包括阻挡层和金属层，其中阻挡层的材料可以包括氮化钛(TiN)该阻挡层可以提高耐磨性，减小摩擦系数，防止粘结，金属层的材料可以包括金属钨(W)。
然后，刻蚀去除第一填充结构靠近沟槽11侧壁的区域，以使第一填充结构与沟槽11侧壁之间留有间隙，如图5所示。
示例性的，刻蚀方法可以选用可控性、灵活性更好的干法刻蚀，利用干法刻蚀对第一填充结构进行刻蚀，得到对应沟道区域的并排的间隙结构。
最后，刻蚀去除第一牺牲层31。
示例性的，刻蚀方法可以是湿法刻蚀，利用湿法刻蚀去除位线2结构上的第一牺牲层31，形成如图6所示结构，也可以是利用湿法刻蚀去除位线2结构上部分的第一牺牲层31，如图7所示。之所以选用湿法刻蚀，是因为湿法刻蚀具有选择性好、重复性好、生严效率高、设备简单、成本底等特点。
接下来是步骤S140：利用外延生长工艺填充沟槽11并在衬底1 表面沉积形成第一有源区4，第一有源区4包覆位线2。
本步骤是利用外延生长工艺在沟槽11内部、衬底1表面沉积生长出半导体薄膜，即本实施例包覆位线2的第一有源区4，如图8所示，该第一有源区4可以为掺杂n型杂质的硅(Si)材料；掺杂P型杂质的硅(Si)材料；掺杂n型杂质的硅锗(SiGe)材料；或掺杂P型杂质的硅锗(SiGe)材料，这种包覆位线2结构的环绕接触方式可以大大增加第一有源区4与位线2的接触面积，从而减小第一有源区4与位线2之间的接触电阻，进而提高了提高电荷传输速度，保证了信号传输性能。本步骤也可以是在第一牺牲层31没有完全被刻蚀掉的基础上进行外延生长，形成带有部分第一牺牲层31的结构，如图9所示。
经过上述方法步骤制备得到的位线2结构，第一有源区4可以包绕在位线金属的周围，增大了第一有源区4与位线金属的接触面积，从而减小了第一有源区4与位线金属之间的接触电阻，进而提高电荷传输速度，保证了信号传输性能。
接下来是S150：图形化刻蚀第一有源区4形成柱状导电通道5。
本步骤于第一有源区4上进行外延工艺和干法刻蚀，形成柱状导电通道5，如图10所示；示例性的，于第一有源区4上利用EPI外延形成GAA的沟道，增加一层光罩，刻蚀形成柱状的沟道结构，沟道的掺杂材料可与第一有源区4相同(无结型)或者不同(有结型)，掺杂的杂质可以是n型，也可以是p型。
最后是步骤S160：在导电通道5周围形成栅极。
本步骤是于柱状导电通道5的侧壁进行单原子沉积形成栅氧介质层6；其中柱状导电通道5为多个，于多个柱状导电通道5之间填充导电层7，栅氧介质层6与导电层7构成栅极，如图11所示。
示例性的，于柱状导电通道5的侧壁进行单原子沉积形成栅氧介 质层6具体可以为侧壁进行单原子沉积，并采用干法刻蚀去除顶部和底部的介质层，最后形成与沟道齐平的侧壁栅氧介质层6，栅氧介质层6的材料可以包括氧化硅。其中，柱状导电通道5为多个，于位线2结构上填充导电材料形成包绕栅氧介质层6的导电层7可以为在栅氧介质层6间隙，填充导电材料，该导电材料可以包括氮化钛(TiN)、氮化钽(TaN)、铝(Al)、钨(W)、钌(Ru)、铜(Cu)等，上述结构经过研磨形成导电层7。
通过上述步骤制得的半导体结构第一源区就可以包绕在位线2的周围，增大了第一有源区4与位线2的接触面积，减小了第一有源区4与位线2之间的接触电阻，进而提高电荷传输速度，保证了信号传输性能。
在本公开的一些可选实施例中，由于干法刻蚀各向异性好，选择比高，可控性、灵活性、重复性好，细线条操作安全，易实现自动化，无化学废液，处理过程未引入污梁，洁净度高。因此，于衬底1形成沟槽11，具体可以为：
利用干法刻蚀工艺于衬底1形成沟槽11。
在本公开的一些可选实施例中，于沟槽11内形成位线2，可以包括：
利用沉积工艺于沟槽11内依次沉积位线金属层及第一牺牲层31，得到充满沟槽11的第一填充结构；
刻蚀去除第一填充结构靠近沟槽11侧壁的区域，以使第一填充结构与沟槽11侧壁之间留有间隙；
刻蚀去除第一牺牲层31，得到位线2。
上述实施例方法制备的半导体结构第一填充结构与沟槽11侧壁之间留有间隙，进而可以使有源区多方位地包覆位线2，增大了有源区与位线2的接触面积，减小了有源区与位线2之间的接触电阻，进 而提高电荷传输速度，保证了信号传输性能。
如图12所示，在本公开的一些可选实施例中，位线金属层包括层叠的第一阻挡层、金属层及第二阻挡层；
利用沉积工艺于沟槽11内依次沉积位线金属层及第一牺牲层31，得到充满沟槽11的第一填充结构，具体可以为：
利用沉积工艺于沟槽11内部依次沉积第一阻挡层、位线金属、第二阻挡层及第一牺牲层31，得到充满沟槽11的第一填充结构。
本实施例中第一阻挡层和第二阻挡层的材料可以包括氮化钛(TiN)，金属层的材料可以包括钨金属(W)。沉积第一阻挡层和第二阻挡层可以提高位线2结构的耐磨性，减小位线2结构的摩擦系数，防止牺牲层与位线2结构的粘结。
在本公开的一些可选实施例中，在利用沉积工艺于沟槽11内依次沉积位线金属层及第一牺牲层31，得到充满沟槽11的第一填充结构之前，于沟槽11内形成位线2，还可以包括：
于沟槽11内沉积形成第二牺牲层32，如图13所示；
在刻蚀去除第一填充结构靠近沟槽11侧壁的区域，以使第一填充结构与沟槽11侧壁之间留有间隙之后，半导体结构的制备方法还包括：
刻蚀去除部分第二牺牲层32，第二牺牲层32的剩余部分用以支撑位线2金属层。
本实施例是沟槽11内部沉积两个牺牲层，第一牺牲层31和第二牺牲层32。
示例性的，利用沉积法在沟槽11内部依次沉积第二牺牲层32、第一阻挡层、金属层、第二阻挡层及第一牺牲层31，形成充满沟槽11的第一填充结构。在形成该结构之后，刻蚀去除第一填充结构靠近沟槽11侧壁的区域，以使第一填充结构与沟槽11侧壁之间留有间 隙，这样就可以利用该间隙进行湿法刻蚀，去除底部部分的第二牺牲层32，剩余部分的第二牺牲层32用于支撑上部的位线2结构。
上述实施例方法制备的半导体结构第一填充结构与沟槽11侧壁之间留有间隙，并且位线底部与衬底1之间同样留有间隙，进而可以使有源区全方位地包覆位线2，大大增加了有源区与位线2的接触面积，减小了有源区与位线2之间的接触电阻，进而提高电荷传输速度，保证了信号传输性能。
在本公开的一些可选实施例中，刻蚀去除部分第二牺牲层32，具体可以为：
利用湿法刻蚀去除部分第二牺牲层32，如图14所示。
如图15所示，在本公开的一些可选实施例中，刻蚀去除第一填充结构靠近沟槽11侧壁的区域，以使第一填充结构与沟槽11侧壁之间留有间隙，具体可以为：
利用干法刻蚀去除第一填充结构靠近沟槽11侧壁的区域，以使第一填充结构与沟槽11侧壁之间留有间隙。
在本公开的一些可选实施例中，沉积工艺可以为：
化学气相沉积工艺；或
原子层沉积工艺。
在本公开的一些可选实施例中，在导电通道5周围形成栅极之后，半导体结构的制备方法，还可以包括：
利用外延生长工艺于导电层7上沉积形成第二有源区8。
在本公开的一些可选实施例中，在利用外延生长工艺于导电层7上沉积形成第二有源区8之后，半导体结构的制备方法，还可以包括：
图形化刻蚀第二有源区8形成柱状有源区结构。
在本实施例之后，该方法还可以包括：在柱状第二有源区8侧壁形成绝缘隔离结构9，绝缘隔离结构9包绕柱状第二有源区8的侧壁。
示例性的，利用EPI形成GAA的柱状第二有源区8，柱状第二有源区8掺杂材料可与第一有源区4相同,增加一层光罩，干法刻蚀后形成柱状结构；在多个柱状第二有源区8之间的间隔间隙填充绝缘材料(氧化硅等)，形成绝缘隔离结构9。
如图17所示，在本公开实施例的第二方面，提供一种半导体结构，该半导体结构可以包括：
衬底1，衬底1上有纵横交错的隔绝层(未示出)隔绝层和沟槽11；
位线2，位线2位于沟槽11内，沟槽穿越隔绝层；
第一有源区4，第一有源区4包覆位线2并填充沟槽11；
多个柱状导电通道5，柱状导电通道5位于第一有源区4；
栅极，柱状栅极位于多个柱状导电通道5之间。
本步骤中衬底1的材料包括但不限于硅晶体或锗晶体、绝缘体上硅(Silicon On Insulator，SOI)结构或硅上外延层结构、化合物半导体(例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、或镝化铟)、合金半导体(例如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或者它们的组合)。
本实施例的半导体结构第一源区包绕在位线2的周围，增大了第一有源区4与位线2的接触面积，减小了第一有源区4与位线2之间的接触电阻，进而提高电荷传输速度，保证了信号传输性能。
在本公开的一些可选实施例中，还可以包括：
第二有源区8，第二有源区8位于柱状导电通道5之上。
在本公开的一些可选实施例中，第二有源区8可以呈柱状。
上述实施例的半导体结构第一源区包绕在位线2的周围，增大了第一有源区4与位线2的接触面积，减小了第一有源区4与位线2之间的接触电阻，进而提高电荷传输速度，保证了信号传输性能。
在本公开的一些可选实施例中，第一有源区4与第二有源区8的材料可以为：
掺杂n型杂质的硅材料；
掺杂P型杂质的硅材料；
掺杂n型杂质的硅锗材料；或
掺杂P型杂质的硅锗材料。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本公开的保护之内。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供衬底，所述衬底上形成有纵横交错的隔绝层；
    于所述衬底形成沟槽，所述沟槽穿越所述隔绝层；
    于所述沟槽内形成位线；
    利用外延生长工艺填充所述沟槽并在衬底表面沉积形成第一有源区，所述第一有源区包覆所述位线；
    图形化刻蚀所述第一有源区形成柱状导电通道；
    在所述导电通道周围形成栅极。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述于所述衬底形成沟槽，具体为：
    利用干法刻蚀工艺于所述衬底形成沟槽。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，所述于所述沟槽内形成位线，包括：
    利用沉积工艺于所述沟槽内依次沉积位线金属层及第一牺牲层，得到充满所述沟槽的第一填充结构；
    刻蚀去除所述第一填充结构靠近所述沟槽侧壁的区域，以使所述第一填充结构与所述沟槽侧壁之间留有间隙；
    刻蚀去除所述第一牺牲层，得到所述位线。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，所述位线金属层包括层叠的第一阻挡层、金属层及第二阻挡层；
    所述利用沉积工艺于所述沟槽内依次沉积位线金属层及第一牺牲层，得到充满所述沟槽的第一填充结构，具体为：
    利用沉积工艺于所述沟槽内部依次沉积第一阻挡层、位线金属、第二阻挡层及第一牺牲层，得到充满所述沟槽的第一填充结构。
  5. 根据权利要求3所述的半导体结构的制备方法，其中，在所 述利用沉积工艺于所述沟槽内依次沉积位线金属层及第一牺牲层，得到充满所述沟槽的第一填充结构之前，所述于所述沟槽内形成位线，还包括：
    于所述沟槽内沉积形成第二牺牲层；
    在所述刻蚀去除所述第一填充结构靠近所述沟槽侧壁的区域，以使所述第一填充结构与所述沟槽侧壁之间留有间隙之后，所述半导体结构的制备方法还包括：
    刻蚀去除部分所述第二牺牲层，所述第二牺牲层的剩余部分用以支撑所述位线金属层。
  6. 根据权利要求5所述的半导体结构的制备方法，其中，所述刻蚀去除部分所述第二牺牲层，具体为：
    利用湿法刻蚀去除部分所述第二牺牲层。
  7. 根据权利要求3所述的半导体结构的制备方法，其中，所述刻蚀去除所述第一填充结构靠近所述沟槽侧壁的区域，以使所述第一填充结构与所述沟槽侧壁之间留有间隙，具体为：
    利用干法刻蚀去除所述第一填充结构靠近所述沟槽侧壁的区域，以使所述第一填充结构与所述沟槽侧壁之间留有间隙。
  8. 根据权利要求3所述的半导体结构的制备方法，其中，所述沉积工艺为：
    化学气相沉积工艺；或
    原子层沉积工艺。
  9. 根据权利要求1所述的半导体结构的制备方法，其中，所述导电通道为多个，所述在所述导电通道周围形成栅极，包括：
    于所述柱状导电通道的侧壁沉积形成栅氧介质层；
    于多个所述导电通道之间填充导电层，所述栅氧介质层与所述导电层构成栅极。
  10. 根据权利要求1-9任一项所述的半导体结构的制备方法，其中，在所述导电通道周围形成栅极之后，所述半导体结构的制备方法，还包括：
    利用外延生长工艺于所述导电层上沉积形成第二有源区。
  11. 根据权利要求10所述的半导体结构的制备方法，其中，在所述利用外延生长工艺于所述导电层上沉积形成第二有源区之后，所述半导体结构的制备方法，还包括：
    图形化刻蚀所述第二有源区形成柱状有源区结构。
  12. 一种半导体结构，包括：
    衬底，所述衬底上设置有纵横交错的隔绝层和沟槽，所述沟槽穿越所述隔绝层；
    位线，所述位线位于所述沟槽内；
    第一有源区，所述第一有源区包覆所述位线并填充所述沟槽；
    多个柱状导电通道，所述柱状导电通道位于所述第一有源区；
    栅极，所述柱状栅极位于多个所述柱状导电通道之间。
  13. 根据权利要求12所述的半导体结构，其中，还包括：
    第二有源区，所述第二有源区位于所述柱状导电通道之上。
  14. 根据权利要求13所述的半导体结构，其中，所述第二有源区呈柱状。
  15. 根据权利要求13所述的半导体结构，其中，所述第一有源区与所述第二有源区的材料为：
    掺杂n型杂质的硅材料；
    掺杂P型杂质的硅材料；
    掺杂n型杂质的硅锗材料；或
    掺杂P型杂质的硅锗材料。
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US20110127605A1 (en) * 2009-11-30 2011-06-02 Hynix Semiconductor Inc. Semiconductor device with buried bit lines and method for fabricating the same
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CN102760669A (zh) * 2011-04-26 2012-10-31 南亚科技股份有限公司 具有埋入式位线及垂直晶体管的存储装置以及其制作方法
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