WO2023032833A1 - 基板処理方法及び基板処理装置 - Google Patents

基板処理方法及び基板処理装置 Download PDF

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Publication number
WO2023032833A1
WO2023032833A1 PCT/JP2022/032169 JP2022032169W WO2023032833A1 WO 2023032833 A1 WO2023032833 A1 WO 2023032833A1 JP 2022032169 W JP2022032169 W JP 2022032169W WO 2023032833 A1 WO2023032833 A1 WO 2023032833A1
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Prior art keywords
substrate
wafer
layer
laser beam
substrate processing
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Ceased
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PCT/JP2022/032169
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English (en)
French (fr)
Japanese (ja)
Inventor
康隆 溝本
陽平 山下
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to JP2023545522A priority Critical patent/JP7690038B2/ja
Priority to US18/689,484 priority patent/US20240355669A1/en
Priority to KR1020247011400A priority patent/KR20240050470A/ko
Priority to CN202280058622.2A priority patent/CN117882173A/zh
Publication of WO2023032833A1 publication Critical patent/WO2023032833A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H10P72/0422—Apparatus for fluid treatment for etching for wet etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/30—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations
    • H10P72/32—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations between different workstations
    • H10P72/3218—Conveying cassettes, containers or carriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7618—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating carrousel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7624—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

  • the present disclosure relates to a substrate processing method and a substrate processing apparatus.
  • Patent Document 1 discloses a method of manufacturing a semiconductor device using a SIMOX (Separation by Implanted Oxygen) substrate. According to the description of Patent Document 1, after forming a layer including a memory element and a field effect transistor having a first single crystal semiconductor layer as an active layer on one surface of a SIMOX substrate, a second silicon substrate is formed on the surface opposite to the one surface. is removed by at least one of etching and grinding/polishing.
  • SIMOX Separatation by Implanted Oxygen
  • the technique according to the present disclosure appropriately thins the first substrate in the superimposed substrate in which the first substrate and the second substrate are bonded.
  • One aspect of the present disclosure is a method of processing a polymerized substrate having a first substrate and a second substrate bonded together, wherein a device layer including a plurality of devices is formed on a front side of the first substrate. and forming a leakage light prevention layer by irradiating a first laser beam to an oxygen-containing film formed between a formation position of a modified layer serving as a starting point for peeling of the first substrate and the device layer. forming the modified layer by irradiating the interior of the first substrate with a second laser beam after forming the light leakage prevention layer; and exfoliating and thinning the substrate.
  • the first substrate can be appropriately thinned in the superimposed substrate in which the first substrate and the second substrate are bonded.
  • FIG. 4 is a side view showing a configuration example of a superposed wafer; 1 is a plan view showing a schematic configuration of a wafer processing system according to an embodiment; FIG. It is a front view showing an outline of composition of an interfacial modification device concerning an embodiment. It is a front view which shows the outline of a structure of a separation apparatus.
  • FIG. 2 is an explanatory diagram showing an example of main steps in a semiconductor wafer manufacturing process;
  • FIG. 2 is a flowchart showing an example of main steps in a semiconductor wafer manufacturing process;
  • FIG. 4 is an explanatory diagram showing an example of another process in the semiconductor wafer manufacturing process;
  • FIG. 4 is an explanatory view showing an example of a process of forming an oxygen-containing film on the first wafer;
  • FIG. 4 is an explanatory diagram showing an example of another process in the semiconductor wafer manufacturing process;
  • It is a longitudinal cross-sectional view which shows the structural example of a laser irradiation apparatus.
  • a semiconductor substrate (hereinafter sometimes referred to as a "wafer") having a device layer including a plurality of electronic circuits formed on its surface is thinned. ing.
  • wafer thinning is performed by irradiating the inside of a wafer to be processed with a laser beam to form a modified layer, and using the modified layer as a starting point, the wafer is divided into a device wafer on the front side and a separation wafer on the back side. It is done separately from
  • SOI substrates in which a single crystal semiconductor layer (for example, single crystal silicon) and an insulating layer (for example, SiO 2 ) are laminated have been used for the purpose of improving the efficiency of semiconductor devices (transistors) as products.
  • a single crystal semiconductor layer for example, single crystal silicon
  • an insulating layer for example, SiO 2
  • SOI substrate is the SIMOX substrate described in Patent Document 1.
  • the irradiated laser light for example, near-infrared (NIR: Near Infrared) light is transmitted through the single crystal semiconductor layer and the insulating layer, resulting in leakage light. It may affect the device layer.
  • NIR near Infrared
  • the focal point of the laser light inside the wafer (the position where the modified layer is formed) is moved upward (on the back side opposite to the surface on which the device layer is formed). and defocusing the light that is transmitted to the device layer.
  • the position of the modified layer is shifted upward, and the separation surface position (thinned interface) of the wafer is also shifted upward, which may cause a problem that the amount of grinding of the back surface of the wafer in the subsequent process increases.
  • a superposed substrate in which a first wafer W as a first substrate and a second wafer S as a second substrate are bonded together.
  • the process is performed on the superposed wafer T as .
  • the surface of the first wafer W to be bonded to the second wafer S will be referred to as a front surface Wa
  • the surface opposite to the front surface Wa will be referred to as a rear surface Wb.
  • the surface on the side bonded to the first wafer W is referred to as a front surface Sa
  • the surface opposite to the front surface Sa is referred to as a rear surface Sb.
  • the first wafer W is, for example, a semiconductor wafer such as a silicon substrate.
  • a SiO 2 film is formed as an insulating layer on the surface Wa side of the first wafer W.
  • the SiO 2 film may be, for example, an oxygen-doped silicon layer in which part of the thickness of the first wafer W is modified by doping with oxygen (O 2 ).
  • the SiO 2 film is further formed with a Si film as a single crystal silicon layer (single crystal semiconductor layer) and a device layer Dw including a plurality of devices. That is, the first wafer W has a structure as an SOI substrate in which an insulating layer and a single crystal semiconductor layer are laminated.
  • a surface film Fw is further formed on the device layer Dw, and the first wafer W is bonded to the second wafer S via the surface film Fw.
  • the surface film Fw includes, for example, an oxide film (THOX film, SiO2 film, TEOS film), SiC film, SiCN film, adhesive, or the like.
  • the peripheral edge portion We of the first wafer W is chamfered, and the thickness of the cross section of the peripheral edge portion We decreases toward its tip.
  • the SiO 2 film formed on the first wafer W does not necessarily have to be an oxygen-doped silicon layer, and may be a general oxide film.
  • the SiO 2 film may be formed by modifying the inside of the first wafer W, or may be formed so as to cover the outer surface of the first wafer W. As shown in FIG. In other words, the first wafer W is formed with an oxygen-containing film.
  • the second wafer S is a wafer that supports the first wafer W, for example.
  • a surface film Fs is formed on the second wafer S, and is bonded to the first wafer W via the surface film Fs.
  • the second wafer S does not need to be a support wafer for supporting the first wafer W, and may be a device wafer having a device layer (not shown) formed on the surface Sa side, for example. In such a case, the surface film Fs is formed on the second wafer S through the device layer.
  • the wafer processing system 1 has a configuration in which a loading/unloading station 2 and a processing station 3 are integrally connected.
  • a cassette C capable of accommodating a plurality of superposed wafers T and the like is loaded/unloaded to/from the outside.
  • the processing station 3 includes various processing devices for performing desired processing on the superposed wafer T.
  • the loading/unloading station 2 is provided with a cassette mounting table 10 on which a plurality of, for example, three cassettes C are mounted.
  • a wafer transfer device 20 is provided adjacent to the cassette mounting table 10 on the X-axis negative direction side of the cassette mounting table 10 .
  • the wafer transfer device 20 moves on a transfer path 21 extending in the Y-axis direction, and is configured to transfer superimposed wafers T and the like between a cassette C on the cassette mounting table 10 and a transition device 30 which will be described later.
  • the loading/unloading station 2 is provided with a transition device 30 adjacent to the wafer transport device 20 on the X-axis negative direction side of the wafer transport device 20 and for transferring the superimposed wafers T and the like to and from the processing station 3 . It is
  • the processing station 3 is provided with, for example, three processing blocks B1 to B3.
  • the first processing block B1, the second processing block B2, and the third processing block B3 are arranged in this order from the X-axis positive direction side (carrying in/out station 2 side) to the negative direction side.
  • the first processing block B1 includes an etching device 40 for etching the ground surface of the first wafer W ground by a processing device 80 described later, a cleaning device 41 for cleaning the ground surface of the first wafer W, A wafer carrier 50 is provided.
  • the etching device 40 and the cleaning device 41 are stacked and arranged. The number and arrangement of the etching device 40 and the cleaning device 41 are not limited to this.
  • the wafer transfer device 50 is arranged on the X-axis negative direction side of the transition device 30 .
  • the wafer transfer device 50 has, for example, two transfer arms 51, 51 that hold and transfer the superposed wafer T. As shown in FIG.
  • Each transport arm 51 is configured to be movable in the horizontal direction, the vertical direction, around the horizontal axis, and around the vertical axis.
  • the wafer transport device 50 transports the superposed wafer T and the like to the transition device 30, the etching device 40, the cleaning device 41, the interface reforming device 60 described later, the internal reforming device 61 described later, and the separating device 62 described later. configured as possible.
  • an interface reforming device 60 for forming a leakage light prevention layer which will be described later
  • a separating device 62 for separating the first wafer W and a wafer transfer device 70 are provided.
  • the interfacial reformer 60, the internal reformer 61 and the separation device 62 are arranged in layers.
  • the number and arrangement of the interfacial reforming device 60, the internal reforming device 61 and the separation device 62 are not limited to this. For example, instead of arranging the interfacial reforming device 60, the internal reforming device 61 and the separation device 62 in layers, at least one of them may be arranged adjacent to each other in the horizontal direction.
  • the interface modification device 60 as a first laser beam irradiation unit applies an interface laser beam L1 (for example, CO 2 laser).
  • the interface laser beam L1 has a wavelength of, for example, 5 ⁇ m or more, preferably 9 ⁇ m to 10 ⁇ m.
  • the Si film is modified at the focal point position of the interface laser beam L1 to form a leakage light prevention layer M1 that suppresses transmission of the internal laser beam L2, which will be described later.
  • the interface modification device 60 has a chuck 100 that holds the superposed wafer T on its upper surface.
  • the chuck 100 holds the non-bonding surface side of the second wafer S with the first wafer W by suction.
  • the chuck 100 is supported by a slider table 102 via air bearings 101 .
  • a rotating mechanism 103 is provided on the lower surface side of the slider table 102 .
  • the rotation mechanism 103 incorporates, for example, a motor as a drive source.
  • the chuck 100 is configured to be rotatable around the ⁇ axis (vertical axis) via an air bearing 101 by a rotating mechanism 103 .
  • the slider table 102 is configured to be movable along a rail 105 extending in the Y-axis direction by means of a horizontal movement mechanism 104 provided on its underside. Rail 105 is provided on base 106 .
  • the drive source for the horizontal movement mechanism 104 is not particularly limited, for example, a linear motor is used.
  • a laser irradiation system 110 is provided above the chuck 100 .
  • a laser irradiation system 110 has a laser head 111 and a lens 112 .
  • the lens 112 may be configured to be vertically movable by a lifting mechanism (not shown).
  • the laser head 111 has a laser oscillator (not shown) that oscillates a pulsed laser beam. That is, the laser light irradiated from the laser irradiation system 110 to the superimposed wafer T held by the chuck 100 is a so-called pulse laser, and its power alternates between 0 (zero) and the maximum value. Note that the laser head 111 may have a device other than the laser oscillator, such as an amplifier.
  • the lens 112 is a tubular member and irradiates the superposed wafer T held by the chuck 100 with the interface laser light L1.
  • the internal reforming device 61 as a second laser beam irradiation unit irradiates the inside of the first wafer W with an internal laser beam L2 (for example, NIR light such as a YAG laser) as a second laser beam.
  • the internal laser beam L2 has a wavelength of 1 ⁇ m to 1.5 ⁇ m, for example.
  • the first wafer W is reformed at the position of the focal point of the internal laser beam L2 to form the internal surface reforming layer M2 that serves as the starting point for separating the first wafer W.
  • the internal reforming device 61 has the same configuration as the interfacial reforming device 60. That is, as shown in FIG. 3, the internal reforming device 61 includes a chuck 200 for holding the superposed wafer T, an air bearing 201, a slider table 202, a rotating mechanism 203, a horizontal moving mechanism 204, a rail 205, a base 206, and a laser irradiation device. It has a system 210 . Also, the laser irradiation system 210 has a laser head 211 and a lens 212 . The laser irradiation system 210 irradiates the superposed wafer T held by the chuck 200 with the internal laser beam L2.
  • a separating device 62 as a separating unit separates the first wafer W into a device wafer Wd1 and a separated wafer Wd2 with the inner surface modified layer M2 formed by the internal modifying device 61 as a base point.
  • the separation device 62 has a chuck 130 that holds the second wafer S on its upper surface, and a separation arm 131 that holds the first wafer W on its suction holding surface.
  • the separation arm 131 sucks and holds the first wafer W, and in this state, the separation arm 131 is lifted. , the first wafer W is separated.
  • the method of separating the first wafer W in the separating device 62 is not limited to this, and can be arbitrarily determined.
  • the wafer transfer device 70 is arranged, for example, on the Y-axis positive direction side of the interface reforming device 60 and the internal reforming device 61 .
  • the wafer transfer device 70 has, for example, two transfer arms 71, 71 for transferring the superposed wafer T while holding it by suction with a suction holding surface (not shown).
  • Each transport arm 71 is supported by a multi-joint arm member 72, and is configured to be movable in the horizontal direction, the vertical direction, around the horizontal axis, and around the vertical axis.
  • the wafer transport device 70 is configured to be capable of transporting the superposed wafer T and the like to the etching device 40, the cleaning device 41, the interface reforming device 60, the internal reforming device 61, the separating device 62, and the processing device 80, which will be described later. ing.
  • a processing device 80 is provided in the third processing block B3.
  • the processing device 80 has a rotary table 81 .
  • the rotary table 81 is rotatable around a vertical center line 82 of rotation by a rotary mechanism (not shown).
  • Two chucks 83 for holding the superposed wafer T by suction are provided on the rotary table 81 .
  • the chucks 83 are evenly arranged on the same circumference as the rotary table 81 .
  • the two chucks 83 are movable to the delivery position A0 and the processing position A1 by rotating the rotary table 81 .
  • Each of the two chucks 83 is configured to be rotatable about a vertical axis by a rotating mechanism (not shown).
  • a grinding unit 84 is arranged at the processing position A1, and grinds the first wafer W while the second wafer S is held by the chuck 83 by suction. Grinding unit 84 has a grinding section 85 with an annular, rotatable grinding wheel (not shown). Further, the grinding part 85 is configured to be movable in the vertical direction along the support 86 .
  • a controller 90 is provided in the wafer processing system 1 described above.
  • the control device 90 is, for example, a computer having a CPU, a memory, etc., and has a program storage unit (not shown).
  • the program storage unit stores programs for controlling the processing of the superposed wafers T in the wafer processing system 1 .
  • the program may be recorded in a computer-readable storage medium H and installed in the control device 90 from the storage medium H.
  • the superimposed wafer T is formed in advance in a bonding apparatus (not shown) outside the wafer processing system 1 . Further, in the polymerized wafer T to be processed according to the present embodiment, as shown in FIGS. 1 and 5A, a SiO 2 film, a Si film, a device layer Dw and A surface film Fw is formed by stacking.
  • a cassette C containing a plurality of superposed wafers T is mounted on the cassette mounting table 10 of the loading/unloading station 2 .
  • the superposed wafer T in the cassette C is taken out by the wafer transfer device 20 and transferred to the transition device 30 .
  • the superposed wafer T transferred to the transition device 30 is then transferred to the interface modification device 60 by the wafer transfer device 50 .
  • the SiO 2 film formed on the first wafer W is irradiated with the interface laser beam L1 as shown in FIG. 5(a).
  • the irradiated interface laser light L1 is absorbed by the SiO 2 film and reforms the SiO 2 film to form the leakage light prevention layer M1 (step P1 in FIG. 6).
  • the leakage light prevention layer M1 is desirably formed so as to cover the entire effective device surface to be protected in plan view.
  • the temperature of silicon forming the first wafer W is raised by raising the temperature of the SiO 2 film by absorbing the interface laser beam L1 (CO 2 laser). to improve the light absorption rate of the silicon.
  • the silicon absorbs the wavelength of the interface laser light L1 (CO 2 laser) and is reformed to form the leakage light prevention layer M1. That is, the "modification" of the SiO 2 film in the interface modification apparatus 60 in this embodiment includes the modification of the silicon forming the first wafer W.
  • the polymerized wafer T on which the leakage light prevention layer M1 is formed is subsequently transferred to the internal reforming device 61 by the wafer transfer device 50 .
  • the internal reforming device 61 as shown in FIG. 5B, the internal surface reforming layer M2 is formed inside the first wafer W (step P2 in FIG. 6).
  • the laser irradiation system 210 In forming the inner surface modified layer M2, while rotating the superposed wafer T (first wafer W), the laser irradiation system 210 periodically irradiates the internal laser beam L2, and the irradiation position of the laser beam is set to the first position. One wafer W is moved radially inward. As a result, the inner surface modified layer M2 is formed inside the first wafer W over the entire surface along the surface direction, and has a substantially spiral or concentric circular shape in a plan view. The formation interval in the radial direction of the inner surface modified layer M2 can be determined arbitrarily. In forming the inner surface modified layer M2, the laser beam irradiation position is relatively scanned horizontally with respect to the superposed wafer T (first wafer W) so that the inner surface modified layer M2 is formed. may be formed substantially linearly.
  • the cracks C2 extending from each of the inner surface modified layers M2 formed adjacent to each other in the surface direction are connected to each other.
  • the crack C2 extending from the inner surface modified layer M2 can be controlled by adjusting conditions such as the output and frequency of the internal laser beam L2 or the number of revolutions of the superposed wafer T, for example.
  • the internal laser beam L2 irradiated when forming the internal surface modified layer M2 is NIR light and has transparency to silicon (Si). For this reason, part of the internal laser beam L2 irradiated to the inside of the first wafer W leaks from the focal point (formation position of the internal surface modified layer M2), further penetrates the SiO 2 film, and reaches the device layer. There was concern that it would affect Dw.
  • the leakage light prevention layer M1 is formed in the interface modification device 60 prior to the formation of the internal surface modification layer M2. Then, the formed leakage light prevention layer M1 absorbs or scatters the leakage light of the internal laser beam L2 (NIR light), thereby reducing the leakage light reaching the device layer Dw and affecting the device layer Dw. can be suppressed.
  • NIR light the internal laser beam L2
  • the inner surface modified layer M2 formed inside the first wafer W has a lower end which is the first layer after grinding the separation surface in step P4 described later. It is desirable to be above the target thickness of the wafer W (broken line in FIG. 5(b)).
  • the superposed wafer T on which the inner surface modified layer M2 is formed is then transferred to the separation device 62 by the wafer transfer device 50.
  • the first wafer W is divided into a device wafer Wd1 on the front surface Wa side and a separated wafer Wd2 on the rear surface Wb side with the inner surface modified layer M2 and the crack C2 as base points. Separate (step P3 in FIG. 6).
  • the chuck 130 In the separation of the first wafer W in step P3, the chuck 130 (see FIG. 4) sucks and holds the second wafer S while sucking and holding the first wafer W on the sucking and holding surface of the separation arm 131 . .
  • the first wafer W is separated into the device wafer Wd1 and the separation wafer Wd2 by raising the separation arm 131 while the suction holding surface holds the first wafer W by suction.
  • shear stress may be generated at the separation interface between the device wafer Wd1 and the separation wafer Wd2 by relatively rotating or moving the chuck 130 and the separation arm 131 in the horizontal direction.
  • the separation arm 131 is used in the separation device 62 to separate the first wafer W. Separation of one wafer W may be performed.
  • the processing device 80 functions as a "peeling section" according to the technique of the present disclosure.
  • a separated wafer Wd2 separated from the first wafer W is collected outside the wafer processing system 1, for example.
  • a recovery section (not shown) may be provided within the movable range of the transfer arm 71, and the separated wafer Wd2 may be recovered in the recovery section.
  • the superposed wafer T from which the first wafer W has been separated is subsequently transferred to the chuck 83 of the processing device 80 by the wafer transfer device 70 .
  • the chuck 83 is moved to the processing position A1, and as shown in FIG. 5(d), the separation surface of the device wafer Wd1 is ground by the grinding unit 84 (step P4 in FIG. 6).
  • the internal surface modified layer M2 remaining on the separation surface of the device wafer Wd1 is removed, and the device wafer Wd1 is reduced to a desired target thickness.
  • the inner surface modified layer M2 is formed such that the lower end thereof is located above the target thickness (the height position of the final finished thickness) of the first wafer W after grinding. , the internal surface modified layer M2 remaining on the separation surface can be appropriately removed by grinding.
  • the superposed wafer T obtained by thinning the first wafer W to the target thickness in the processing device 80 is transferred to the cleaning device 41 by the wafer transfer device 70, and the ground surface of the device wafer Wd1 is cleaned (step P5 in FIG. 6). .
  • step P6 the ground surface of the device wafer Wd1 is planarized by wet etching the ground surface.
  • the superposed wafer T that has undergone all the processes is transferred to the transition device 30 by the wafer transfer device 50 and further transferred to the cassette C on the cassette mounting table 10 by the wafer transfer device 20 .
  • a series of wafer processing in the wafer processing system 1 is completed.
  • the polymerized wafer T that has undergone all the processes may be further subjected to CMP (Chemical Mechanical Polishing) to smooth the ground surface.
  • CMP Chemical Mechanical Polishing
  • the CMP process may be performed outside the wafer processing system 1 or may be performed inside.
  • the CMP apparatus for performing the CMP process can be stacked with the etching apparatus 40 and the cleaning apparatus 41 in the first processing block B1, for example.
  • the SiO 2 film provided between the first wafer W and the device layer Dw is modified, and the internal laser beam L2 is generated.
  • a leakage light prevention layer M1 is formed to absorb or scatter leakage light.
  • the leakage light prevention layer M1 by forming the leakage light prevention layer M1 in this way, the position of the condensing point (the position where the inner surface modification layer M2 is formed) inside the first wafer W is brought closer to the device layer Dw. It is possible to reduce the amount of grinding in the subsequent grinding process (step P4).
  • the amount of the internal laser beam L2 that passes through the device layer Dw when forming the internal surface modified layer M2 increases as the focal point position of the internal laser beam L2 approaches the device layer Dw. .
  • the focal point position of the internal laser beam L2 the position where the internal surface modified layer M2 is formed
  • the leaked light can be absorbed and scattered by the leaked light prevention layer M1. Therefore, the focal point position of the internal laser beam L2 can be brought closer to the device layer Dw (more specifically, the target thickness in the grinding process), and the amount of grinding in the grinding process (step P4) can be reduced.
  • the superposed wafer T after separation of the first wafer W is sequentially subjected to the grinding process (step P4), the cleaning of the ground surface (step P5), and the wet etching process (step P6).
  • the grinding process of the superposed wafer T can be omitted as appropriate. That is, the purpose of the grinding process in step P4 is to reduce the device wafer Wd1 to a desired target thickness. If the first wafer W can be separated near the position, the grinding process in step P4 can be omitted.
  • the inner surface modified layer M2 remaining on the separation surface of the device wafer Wd1 can be removed by wet etching treatment applied to the superposed wafer T without performing the grinding treatment. Further, in such a wet etching process, the separation surface of the superposed wafer T is flattened. Further, the separation surface of the superposed wafer T flattened by the wet etching process may be further smoothed by the CMP process as described above.
  • the crack C2 extending in the surface direction from the inner surface modified layer M2 reaches the outer peripheral edge of the first wafer W as shown in FIG. 5(b).
  • the device wafer Wd1 after removal of the separation wafer Wd2 has a sharply pointed peripheral edge We (so-called knife-edge shape) as shown in FIG. 5(c).
  • chipping may occur at the peripheral edge We of the wafer, and the wafer may be damaged.
  • the peripheral edge We of the first wafer W is removed integrally with the separated wafer Wd2 (so-called edge trim processing). That is, the separation device 62 or the processing device 80 that separates the first wafer W can function as a peripheral edge removal section that removes the peripheral edge portion We of the first wafer W.
  • the SiO 2 film is modified in the interface modification device 60 to form the leakage light prevention layer M1 in the same manner as in the above embodiment.
  • Dw or the surface film Fw (surface film Fw in the illustrated example) is used to form an unbonded area Ae in which the bonding strength between the first wafer W and the second wafer S is reduced.
  • the unbonded region Ae is formed, for example, by amorphizing or removing the irradiated portion of the interface laser beam L1.
  • an inner surface modified layer M2 and a peripheral edge modified layer M3 are sequentially formed in the internal modification device 61.
  • FIG. The modified peripheral layer M3 serves as a starting point for peeling (edge trim) of the peripheral edge We.
  • the formation order of the inner surface modified layer M2 and the peripheral edge modified layer M3 is not particularly limited.
  • the crack C2 extends from the inner surface modified layer M2 along the surface direction of the first wafer W
  • the crack C3 extends from the peripheral edge modified layer M3 along the thickness direction of the first wafer W. Extend.
  • the radially outer end of the crack C2 is formed at the uppermost side (on the rear surface Wb side of the first wafer W) inside the first wafer W as shown in FIG. 7(c). It connects with the upper end of layer M3 or crack C3.
  • the crack C2 does not extend to the edge of the first wafer W.
  • the crack C3 does not extend to the rear surface Wb of the first wafer W.
  • the first wafer W is formed with the inner surface modified layer M2, the peripheral edge modified layer M3, and the cracks C2 and C3 formed inside the first wafer W as base points. is separated into a device wafer Wd1 and a separation wafer Wd2 and thinned.
  • the polymerized wafer T to be processed is the first layer formed by laminating the SiO 2 film, the Si film, the device layer Dw and the surface film Fw on the surface Wa side.
  • the SiO 2 film of the first wafer W is partially doped with oxygen (O 2 ). It may be a modified oxygen-doped silicon layer.
  • a SiO2 layer is formed as an insulating layer as shown in (b).
  • the SiO 2 layer is formed at the thickness direction position of the first wafer W implanted with O ions.
  • an SOI structure is formed in which a single crystal silicon layer and an SiO 2 layer as an insulating layer are arranged in the thickness direction.
  • the implantation position of oxygen ions may be appropriately adjusted to a desired position. It is set closer to the surface Wa than the position where the modified layer M2 is to be formed.
  • the method of forming the SiO 2 layer on the first wafer W is not limited to this.
  • high-concentration carbon (C ) After the ion implantation, the first wafer W into which the carbon ions are implanted may be subjected to a heat treatment (annealing treatment) at a high temperature to form an oxygen precipitation layer.
  • the device layer Dw includes multiple devices.
  • the surface film Fw is, for example, a TEOS film.
  • FIG. 8(d) the first wafer W and the second wafer S are bonded to form a superimposed wafer T.
  • FIG. 8(d) the first wafer W and the second wafer S are bonded to each other via surface films Fw and Fs, respectively.
  • the superposed wafer T formed as described above is then loaded into the wafer processing system 1 .
  • the polymerized wafer T loaded into the wafer processing system 1 is first transported to the interface modification device 60, and as shown in FIG .
  • the SiO 2 layer is modified to form the leakage light prevention layer M1.
  • the polymerized wafer T on which the leakage light prevention layer M1 is formed is transported to the internal reforming device 61, and as shown in FIG. 9B, the inside of the first wafer W is irradiated with the internal laser beam L2.
  • an inner surface modified layer M2 which serves as a starting point for delamination of the first wafer W, is formed.
  • a crack C2 extending in the surface direction of the first wafer W extends from the inner surface modified layer M2.
  • the leakage light prevention layer M1 is formed between the formation position of the internal surface modified layer M2 and the device layer Dw, the device layer Dw is not exposed when the internal laser beam L2 is irradiated. It is possible to appropriately suppress the influence of leaked light on the Further, since the leakage light prevention layer M1 is formed in this way, as shown in FIG. It can be brought closer to the device layer Dw.
  • the polymerized wafer T on which the inner surface modified layer M2 is formed is subsequently transported to the separation device 62.
  • the separating device 62 separates the first wafer W into a device wafer Wd1 and a separated wafer Wd2 with the inner surface modified layer M2 and the crack C2 as base points.
  • the device wafer Wd1 after separation of the first wafer W may be transferred to the cleaning device 41 and the separated surface may be cleaned.
  • the formation position of the internal surface modified layer M2 (position of the focal point of the internal laser beam L2) can be brought closer to the device layer Dw. .
  • the amount of grinding of the first wafer W after separation in the processing device 80 can be reduced or eliminated. Therefore, in the present embodiment, the device wafer Wd1 after separation of the first wafer W is transferred to the etching device 40 without being transferred to the processing device 80 .
  • the peeled surface of the superimposed wafer T (device wafer Wd1) thinned by separation is etched without being subjected to the grinding process in the processing apparatus 80.
  • Processing may be applied.
  • the SiO 2 layer and the leakage light preventing layer M1 formed inside the first wafer W may be further removed as shown in FIG. 9(d).
  • the CMP process may be further performed inside or outside the wafer processing system 1 on the superposed wafer T on which all the processes have been performed.
  • the structure of the superposed wafer T processed by the wafer processing system 1 is not particularly limited, and the SiO 2 film as the oxygen-containing film is formed on the surface Wa of the first wafer W.
  • a SiO 2 layer may be formed inside the first wafer W as an oxygen-containing film.
  • the overlapping wafer T is etched without being ground.
  • the interface modification device 60 for forming the leakage light prevention layer M1 and the internal modification device 61 for forming the internal surface modification layer M2 (and the periphery modification layer M3) are arranged independently, but these laser irradiation devices may be configured integrally.
  • one laser irradiation system 161 for irradiating interface laser light L1 (CO 2 laser) and internal laser light L2 (NIR Another laser irradiation system 162 for irradiating light) may be arranged.
  • One laser irradiation system 161 includes a laser head 161a and a lens 161b.
  • Another laser illumination system 162 comprises a laser head 162a and a lens 162b.
  • one laser irradiation system 161 and another laser irradiation system 162 may be arranged independently as shown in FIG.
  • one laser irradiation system 161 and another laser irradiation system 162 are integrally configured, and, for example, under the control of the control device 90, the irradiation of the interface laser light L1 and the internal laser light L2 is switched. may be configured to allow
  • the SiO 2 film is irradiated with the interfacial laser light L1, and the inside of the first wafer W is irradiated with the internal laser light L2. Irradiation may be performed simultaneously. More specifically, while moving the lens 161b, the SiO 2 film is irradiated with the interface laser light L1, and the lens 162b is moved so as to follow the irradiation of the SiO 2 film with the interface laser light L1. It is moved and irradiated with the internal laser beam L2.
  • the inner surface modification layer M2 is subsequently formed, but immediately after the formation of the light leakage prevention layer M1. Then, the internal laser beam L2 may be irradiated at a position corresponding to the formed leakage light prevention layer M1.
  • the output of the internal laser beam L2 or the relative distance between the irradiation axis of the interface laser beam L1 and the irradiation axis of the internal laser beam L2 is determined by the crack C2 that extends during the formation of the internal surface modified layer M2. is preferably controlled so as not to reach directly under the irradiation of the interface laser beam L1.
  • the formation of the leakage light prevention layer M1 and the formation of the internal surface modification layer M2 can be performed substantially simultaneously as described above, so that the time required for a series of processes on the superposed wafer T in the wafer processing system 1 can be greatly reduced. can be shortened.
  • the interface laser beam L1 is a CO 2 laser and the internal laser beam L2 is an NIR beam has been described as an example.
  • the type of laser light is not particularly limited as long as the can be formed appropriately.
  • the wafer to be processed is an SIO wafer (for example, SIMOX wafer) has been described as an example, but the structure of the wafer is not particularly limited.
  • Wafer Processing System 60 Interface Modification Device 61 Internal Modification Device 80 Processing Device 90 Control Device Dw Device Layer L1 Interface Laser Light L2 Internal Laser Light M1 Leakage Prevention Layer M2 Internal Surface Modification Layer S Second Wafer T Superimposed wafer W First wafer

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JP2016097419A (ja) * 2014-11-19 2016-05-30 キヤノンマシナリー株式会社 レーザ加工方法、レーザ加工装置、およびレーザ加工品
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