WO2023029539A1 - 非易失性存储器及其写入方法和读取方法 - Google Patents

非易失性存储器及其写入方法和读取方法 Download PDF

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WO2023029539A1
WO2023029539A1 PCT/CN2022/090355 CN2022090355W WO2023029539A1 WO 2023029539 A1 WO2023029539 A1 WO 2023029539A1 CN 2022090355 W CN2022090355 W CN 2022090355W WO 2023029539 A1 WO2023029539 A1 WO 2023029539A1
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storage unit
storage
unit
signal value
state
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PCT/CN2022/090355
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French (fr)
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王晓光
曾定桂
章纬
曹堪宇
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长鑫存储技术有限公司
北京超弦存储器研究院
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Publication of WO2023029539A1 publication Critical patent/WO2023029539A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00

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  • the present disclosure relates to the technical field of semiconductors, in particular to a non-volatile memory and its writing method and reading method.
  • the memory uses data combination to store information.
  • Each storage device unit that makes up a large-capacity memory can store a single data.
  • the memory is composed of multiple basic unit arrays. The storage density and storage capacity of the memory are determined by the basic units in the storage array.
  • the basic unit mainly has two structures: 1T1R structure (a transistor and a variable resistance or a variable voltage memory, such as a transistor and a phase change resistance) and 2T2R structure (two transistors and two variable resistance or variable voltage The memory structure of variable voltage, such as two transistors and two phase-changing resistors).
  • the 1T1R cell area is small and the storage density is high, but an external reference source is required to distinguish the two logic states ("1" and "0"); for the 2T2R structure, no reference source is required, but two
  • the 1T1R structure forms a bit reference, that is, one is used for data storage, and the other is used to form a reference bit. Under the same storage area, the storage array density is high but the storage capacity is small, resulting in low memory density of the memory.
  • the purpose of the present disclosure is to provide a non-volatile memory that does not need an external reference source and has high memory density and high integration.
  • a nonvolatile memory includes a first storage unit, a second storage unit, and a reference unit, the first storage unit and the second storage unit share the reference unit, and the reference unit uses To provide a reference signal to judge the storage states of the first storage unit and the second storage unit.
  • the present disclosure also proposes a writing method of a non-volatile memory, the non-volatile memory includes a first storage unit, a second storage unit and a reference unit, the first storage unit and the second storage The units share the reference unit, and the reference unit is used to provide a reference signal value to judge the storage status of the first storage unit and the second storage unit;
  • the writing method includes:
  • a fourth electrical signal is applied to the second storage unit to provide a fourth storage signal value less than the reference signal value such that the second storage unit is in a fourth storage state.
  • the present disclosure also proposes a method for reading a non-volatile memory
  • the non-volatile memory includes a first storage unit, a second storage unit and a reference unit, the first storage unit and the second storage
  • the units share the reference unit, and the reference unit is used to provide a reference signal to judge the storage status of the first storage unit and the second storage unit;
  • the reading methods include:
  • the first storage unit is read as A first storage state, when the storage signal value of the first storage unit is smaller than the reference signal value, the first storage unit is read as a second storage state;
  • the second storage unit is read as In the third storage state, when the stored signal value of the second storage unit is smaller than the reference signal value, the second storage unit is read as a fourth storage state.
  • the first storage unit and the second storage unit share the same reference unit, so that no external reference source is needed, the structure of the non-volatile memory can be simplified, and tail effects can be avoided.
  • the performance of the memory, and two memory units share a reference unit, the memory under the same area can increase the memory density and storage capacity of the memory, and the memory of the same memory can also reduce the setting of the basic unit, making the memory area Smaller, improving the integration of non-volatile memory.
  • FIG. 1 is a schematic structural diagram of a non-volatile memory according to an embodiment of the disclosure
  • FIG. 2 is a schematic flowchart of a writing method of a non-volatile memory according to an embodiment of the present disclosure
  • FIG. 3 is a schematic flowchart of a method for reading a non-volatile memory according to an embodiment of the disclosure.
  • 11 the first storage unit, 12: the first bit line, 13: the first gate transistor;
  • 21 second storage unit, 22: second bit line, 23: second gate transistor;
  • a nonvolatile memory includes a first storage unit 11, a second storage unit 21 and a reference unit 31, and the first storage unit 11 and the second storage unit 21 share the reference unit 31,
  • the reference unit 31 is used to provide a reference signal to determine the storage states of the first storage unit 11 and the second storage unit 21 .
  • Both the first storage unit 11 and the second storage unit 21 are used to realize data information storage, and the reference unit 31 is formed as the reference unit 31 of the first storage unit 11 and the second storage unit 21, through the first storage unit 11 and the reference unit 31
  • the storage state of the first storage unit 11 is judged by the comparison of the second storage unit 21 and the reference unit 31
  • the storage state of the second storage unit 21 is judged by the comparison between the second storage unit 21 and the reference unit 31 .
  • the storage state of the first storage unit 11 can be judged, for example, by comparing the first storage unit 11 with the reference unit 31, when it is judged that the first storage unit 11 is in a high-impedance state, it is defined that the first storage unit 11 is in the first storage state; when the first storage unit 11 is compared with the reference unit 31, it is judged that the first storage unit 11 is in the first storage state. When a storage unit 11 is in the low resistance state, it is defined that the first storage unit 11 is in the second storage state.
  • the comparison between the second storage unit 21 and the reference unit 31 and the judgment of the storage state are the same as the first storage unit 11.
  • the first storage unit 11 and the second storage unit 21 share the same reference unit 31, so that no external reference source is needed, the structure of the nonvolatile memory can be simplified, and the occurrence of Tail effect affects the performance of the memory, and two memory units share a reference unit 31, the memory under the same area can increase the memory density and storage capacity of the memory, and can also reduce the basic unit when forming the memory of the same memory
  • the setting makes the memory area smaller and improves the integration degree of the non-volatile memory.
  • the reference signal of the reference unit 31 is the same, that is, when comparing the first storage unit 11 and the reference unit 31, and the second
  • the reference signal provided by the reference unit 31 is the same, thereby making the reference standards of the storage states of the first storage unit 11 and the second storage unit 21 the same, which is beneficial to the first storage unit 11 and the judgment of the storage state of the second storage unit 21 without changing the reference signal of the reference unit 31, and can also simplify the structure of the non-volatile memory.
  • the first storage unit 11 is connected to the first bit line 12 and the first gate transistor 13
  • the second storage unit 21 is connected to the second bit line 22 and the second gate transistor 23, and the reference unit 31 Connect the reference bit line 32 and the reference gate tube 33 .
  • one end of the first storage unit 11 is connected in series with the first gate transistor 13
  • the other end of the second storage unit 21 is connected to the first bit line 12
  • one end of the first gate transistor 13 is connected to the second gate transistor 23.
  • the first gate transistor 13 , the second gate transistor 23 and the reference gate transistor 33 may all be transistors, for example, all may be diodes or triodes, which are not specifically limited in the present disclosure.
  • the first storage unit 11 and the first gate transistor 13 connected in series, the second storage unit 21 and the second gate transistor 23 connected in series, and the reference unit 31 connected in series and the reference gate transistor 33 are connected in parallel and connected in series.
  • the reference unit 31 and the reference gate transistor 33 are located between the first storage unit 11 and the first gate transistor 13 connected in series and the second storage unit 21 and the second gate transistor 23 connected in series.
  • the first gating transistor 13, the second gating transistor 23 and the reference gating transistor 33 are all connected to the same word line 41, the source end of the first gating transistor 13, the source end of the second gating transistor 23 and the reference gating transistor
  • the source ends of the through pipes 33 are all connected to the same source line 42 .
  • the drain end of the first gating tube 13 is directly connected to the first storage unit 11
  • the drain end of the second gating tube 23 is directly connected to the second storage unit 21
  • the drain end of the reference gating tube 33 is connected to the reference unit 31 is directly connected
  • the gate end of the first gate transistor 13, the gate end of the second gate transistor 23 and the gate end of the reference gate transistor 33 are simultaneously connected in parallel to the same word line 41
  • the source end of the first gate transistor 13 , the source end of the second gating tube 23 and the source end of the reference gating tube 33 are simultaneously connected in parallel to the same source line 42, so that the first gating tube 13, the second gating tube 23 and the reference gating tube 33 have the same
  • the structural parameters of the first storage unit 11 and the second storage unit 21 and the reference unit 31 have the same structural parameters.
  • the first storage unit 11, the second storage unit 21 and the reference unit 31 are units of the same type of memory, that is, the first storage unit 11, the second storage unit 21 and the reference unit 31 use the same type of semiconductor storage structure, for example, the first storage unit 11, the second storage unit 21 and the reference unit 31 may all be magnetic memory units, phase change memory units, ferroelectric memory units or resistive change memory units.
  • the first storage unit 11, the second storage unit 21 and the reference unit 31 are all units of a magnetic memory
  • the nonvolatile memory is formed as a magnetic memory (MRAM)
  • the unit of the magnetic memory includes a free layer , the middle layer and the fixed layer store information through the change of the magnetic moment direction of the free layer and the fixed layer, and the memory reading circuit judges the information of the memory by applying the same voltage to judge the magnitude of the output current.
  • the first storage unit 11, the second storage unit 21 and the reference unit 31 are all phase-change memory units
  • the non-volatile memory is a phase-change memory (PCRAM).
  • the first storage unit 11, the second storage unit 21 and the reference unit 31 may also all be units of ferroelectric memory, and the nonvolatile memory is a ferroelectric memory (FeRAM); or
  • the first storage unit 11 , the second storage unit 21 and the reference unit 31 are all units of a resistive memory, and the non-volatile memory is a resistive memory (RRAM).
  • the nonvolatile memory may further include a comparator 43, the first bit line 12, the second bit line 22 and the reference bit line 32 are all connected to the input end of the comparator 43, by sharing the reference
  • the setting of the unit 31 can use the comparator 43 to perform data comparison, without the need to set structures such as sense amplifiers, which can not only improve the sensing efficiency and sensing reliability, but also simplify the structure of the peripheral circuit of the non-volatile memory, further improve the integration of memory.
  • the nonvolatile memory includes a first storage unit 11, a second storage unit 21 and a reference unit 31, the first storage unit 11 and the second storage unit 21 share the reference unit 31, and the reference unit 31 is used to provide Refer to the signal value to judge the storage status of the first storage unit 11 and the second storage unit 21; the writing method is applicable to the non-volatile memory in any of the above-mentioned embodiments.
  • the writing method according to an embodiment of the present disclosure may include the following steps:
  • an electrical signal such as a current can be applied to the first storage unit 11 and the reference unit 31 through the word line 41 and the bit line.
  • 11 Write data is different.
  • a programming operation such as writing a first value to the first storage unit 11, so that the first storage unit 11 is in the first storage state
  • a first electrical signal is applied to the first storage unit 11
  • To provide the first storage signal value greater than the reference signal value when writing the second value into the first storage unit 11, so that the first storage unit 11 is in the second storage state, then apply the second voltage to the first storage unit 11 signal to provide a second stored signal value less than the reference signal value.
  • the first storage state and the second storage state can be a voltage state, a resistance state, or a current state.
  • the data state of the storage unit is different for different types of memory. For the convenience of description, the storage state is presented as a resistance state for description below.
  • the write data value of the storage unit such as the first value and the second value, can be defined as a binary number.
  • the first value can be defined as a binary number 0, and the second value is a binary number 1.
  • the data value corresponding to the specific programming operation is "1". Or "0" can be defined according to needs, which is not limited here.
  • the first storage state can be defined as a high resistance state
  • the second storage state can be defined as a low resistance state.
  • the first storage unit 11 When the first storage unit 11 is in the second storage state, that is, the low resistance state, a second electrical signal is applied to the first storage unit 11, so that the second storage unit 11 generates
  • the stored signal value is smaller than the reference signal value of the reference unit 31, so that the first storage unit 11 is in a low resistance state, and the corresponding written second value is recorded as “1”.
  • an electrical signal such as a current can be applied to the second storage unit 21 and the reference unit 31 through the word line 41 and the bit line.
  • 21 Write data is different.
  • the third storage state of the second storage unit 21 can be defined as a high resistance state
  • the fourth storage state of the second storage unit 21 can be defined as a low resistance state.
  • a third electrical signal is applied to the second storage unit 21, so that the value of the third storage signal generated by the second storage unit 21 is greater than the value of the reference signal of the reference unit 31, so that the second storage unit 21 behaves as In the high resistance state, the corresponding write data value is recorded as "0".
  • a fourth electrical signal is applied to the second storage unit 21, so that the second storage unit
  • the value of the fourth storage signal generated by 21 is smaller than the reference signal value of the reference unit 31, so that the second storage unit 21 is in a low resistance state, and the corresponding written data value is recorded as "1".
  • the reference signal value of the reference unit 31 when an electrical signal is applied to the first storage unit 11 and the second storage unit 21, the reference signal value of the reference unit 31 is the same, so that when the electrical signal is applied to the first storage unit 11 and the second storage unit 21 When writing data, the electrical signal applied to the reference unit 31 is the same, and there is no need to perform an operation to change the electrical signal applied to the reference unit 31, which is also beneficial to the electrical signals generated when the first storage unit 11 and the second storage unit 21 write data.
  • the reference comparison of the signals and the consistent reference standards make the judgment of the storage states of the first storage unit 11 and the second storage unit 21 more accurate.
  • the nonvolatile memory further includes a comparator 43.
  • the comparator 43 When the storage unit is in the first storage state or the third storage state, the comparator 43 is in the first signal state; when the storage unit is in the second In the storage state or the fourth storage state, the comparator 43 is in the second signal state, wherein the first signal state and the second signal state may represent a data state, for example, a data value "1" or "0".
  • the first storage unit 11 when the first storage unit 11 is applied with the first electrical signal, it is in the first storage state, such as in a high-impedance state; when the second storage unit 21 is applied with the third electrical signal, it is in the third storage state.
  • the comparator 43 When the storage state is in the high-impedance state, the comparator 43 is in the first signal state, stores the first data value, and presents a programming operation of "0".
  • the first storage unit 11 is applied with the second electrical signal, it is in the first If it is in a low resistance state during the second storage state, when the second storage unit 21 is applied with a fourth electrical signal and is in the fourth storage state, that is, in a low resistance state, the comparator 43 is in the second signal state and stores the second data. state, presenting a "1" for a program operation.
  • the disclosure also proposes a method for reading a non-volatile memory.
  • the non-volatile memory includes a first storage unit 11, a second storage unit 21 and a reference unit 31, the first storage unit 11 and the second storage unit 21 share the reference unit 31, and the reference unit 31 is used to provide a reference signal to judging the storage states of the first storage unit 11 and the second storage unit 21,
  • the reading method according to an embodiment of the present disclosure includes the following steps:
  • the storage signal value of the first storage unit 11 is compared with the reference signal value of the reference unit 31, when the storage signal value of the first storage unit 11 is greater than the reference signal value, the first storage unit 11 is read as the first storage state, when When the storage signal value of the first storage unit 11 is less than the reference signal value, the first storage unit 11 is read as the second storage state;
  • the storage signal value of the second storage unit 21 is compared with the reference signal value of the reference unit 31, when the storage signal value of the second storage unit 21 is greater than the reference signal value, the second storage unit 21 is read as the third storage state, when When the stored signal value of the second storage unit 21 is smaller than the reference signal value, the second storage unit 21 is read as the fourth storage state.
  • the stored signal value and the reference signal value here can be a voltage value, a resistance value or a current value, which can be selected according to the type of the memory.
  • the storage signal value and the reference signal value are described below as an example of a resistance value.
  • an electrical signal is applied to the first storage unit 11, so that the first storage unit 11 generates a stored signal value, and the first storage unit 11 is judged by comparing the stored signal value with the reference signal value of the reference unit 31 to read the data state of the first storage unit 11.
  • the storage signal value generated by the first storage unit 11 is greater than the reference signal value, it is judged that the first storage unit 11 is in the first storage state, that is, a high-impedance state, and the stored information of the first storage unit 11 can be read as “0”,
  • the stored signal value generated by the first storage unit 11 is smaller than the reference signal value, it is judged that the first storage unit 11 is in the second storage state, ie, the low resistance state, and the stored information of the first storage unit 11 can be read as “1”.
  • an electrical signal is applied to the second storage unit 21, so that the second storage unit 21 generates a stored signal value, and the second storage unit 21 is judged by comparing the stored signal value with the reference signal value of the reference unit 31 to read the data state of the second storage unit 21.
  • the second storage unit 21 when the stored signal value generated by the second storage unit 21 is greater than the reference signal value, it is judged that the second storage unit 21 is in the third storage state, that is, a high-impedance state, and the stored information of the second storage unit 21 can be read as "0", When the stored signal value generated by the first storage unit 11 is smaller than the reference signal value, it is judged that the first storage unit 11 is in the fourth storage state, ie, the low resistance state, and the stored information of the second storage unit 21 can be read as “1”.

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Abstract

该发明公开了一种非易失性存储器及其写入方法和读取方法，所述非易失性存储器包括第一存储单元、第二存储单元和参考单元，所述第一存储单元和所述第二存储单元共享所述参考单元，所述参考单元用于提供参考信号，以判断所述第一存储单元和所述第二存储单元的存储状态。根据本公开实施例的非易失性存储器，第一存储单元和第二存储单元共享同一参考单元，不需要外接参考源，可以简化非易失性存储器的结构，也能够增加存储器的内存密度和存储容量，提高非易失性存储器的集成度。

Description

非易失性存储器及其写入方法和读取方法
相关申请引用说明
本申请要求于2021年08月31日递交的中国专利申请号2021110128815、申请名为“非易失性存储器及其写入方法和读取方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体技术领域，具体涉及一种非易失性存储器及其写入方法和读取方法。
背景技术
半导体存储器使用数据组合来存储信息，组成大容量存储器的每个存储器件单元可以存储单个数据，存储器由多个基本单元阵列排列构成，存储器的存储密度和存储容量由存储阵列中的基本单元决定，基本单元主要有两种结构：1T1R结构(一个晶体管和一个可变电阻或可变电压的存储器构成，如一个晶体管和一个相变电阻)和2T2R结构(两个晶体管和两个可变电阻或可变电压的存储器构成，如两个晶体管和两个相变电阻)。对于1T1R的结构，1T1R单元面积小，存储密度高，但需要外接参考源以实现两种逻辑状态(“1”和“0”)的区分；对于2T2R的结构，无需参考源，但利用两个1T1R结构形成对位参考，即一个用于数据存储，一个用于形成参考位，在相同存储面积下，存储阵列密度大但存储容量小，导致存储器的内存密度小。
发明内容
本公开的目的在于提供一种非易失性存储器，无需外接参考源且内存密度大，集成度高。
根据本公开实施例的非易失性存储器，包括第一存储单元、第二存储单元和参考单元，所述第一存储单元和所述第二存储单元共享所述参考单元，所述参考单元用于提供参考信号，以判断所述第一存储单元和所述第二存储单元的存储状态。
本公开还提出了一种非易失性存储器的写入方法，所述非易失性存储器包括第一存储单元、第二存储单元和参考单元，所述第一存储单元和所述第二存储单元共享所述参考单元，所述参考单元用于提供参考信号值，以判断所述第 一存储单元和所述第二存储单元的存储状态；
所述写入方法包括：
向所述第一存储单元施加第一电信号以提供大于所述参考信号值的第一存储信号值，使得所述第一存储单元处于第一存储状态；
向所述第一存储单元施加第二电信号以提供小于所述参考信号值的第二存储信号值，使得所述第一存储单元处于第二存储状态；
向所述第二存储单元施加第三电信号以提供大于所述参考信号值的第三存储信号值，使得所述第二存储单元处于第三存储状态；
向所述第二存储单元施加第四电信号以提供小于所述参考信号值的第四存储信号值，使得所述第二存储单元处于第四存储状态。
本公开还提出了一种非易失性存储器的读取方法，所述非易失性存储器包括第一存储单元、第二存储单元和参考单元，所述第一存储单元和所述第二存储单元共享所述参考单元，所述参考单元用于提供参考信号，以判断所述第一存储单元和所述第二存储单元的存储状态；
所述读取方法包括：
向所述第一存储单元施加电信号并产生第一存储单元的存储信号值；
将所述第一存储单元的存储信号值与所述参考单元的参考信号值比较，当所述第一存储单元的存储信号值大于所述参考信号值时，所述第一存储单元读取为第一存储状态，当所述第一存储单元的存储信号值小于所述参考信号值时，所述第一存储单元读取为第二存储状态；
向所述第二存储单元施加电信号并产生第二存储单元的存储信号值；
将所述第二存储单元的存储信号值与所述参考单元的参考信号值比较，当所述第二存储单元的存储信号值大于所述参考信号值时，所述第二存储单元读取为第三存储状态，当所述第二存储单元的存储信号值小于所述参考信号值时，所述第二存储单元读取为第四存储状态。
根据本公开实施例的非易失性存储器，第一存储单元和第二存储单元共享同一参考单元，这样不需要外接参考源，可以简化非易失性存储器的结构，避免产生尾位效应而影响存储器的性能，而且两个存储单元共用一个参考单元，在相同面积下的存储器，从而能够增加存储器的内存密度和存储容量，在形成 相同内存的存储器，也能够减少基本单元的设置，使得存储器面积较小，提高非易失性存储器的集成度。
附图说明
图1为根据本公开实施例的非易失性存储器的结构示意图；
图2为根据本公开实施例的非易失性存储器的写入方法的流程示意图；
图3为根据本公开实施例的非易失性存储器的读取方法的流程示意图。
附图标记：
11：第一存储单元，12：第一位线，13：第一选通管；
21：第二存储单元，22：第二位线，23：第二选通管；
31：参考单元，32：参考位线，33：参考选通管；
41：字线，42：源线，43：比较器。
具体实施方式
以下结合附图和具体实施方式对本公开提出的一种非易失性存储器作进一步详细说明。
下面参考附图描述根据本公开实施例的非易失性存储器。
如图1所示，根据本公开实施例的非易失性存储器包括第一存储单元11、第二存储单元21和参考单元31，第一存储单元11和第二存储单元21共享参考单元31，参考单元31用于提供参考信号，以判断第一存储单元11和第二存储单元21的存储状态。
第一存储单元11和第二存储单元21均用于实现数据信息存储，参考单元31形成为第一存储单元11和第二存储单元21的参考单元31，通过第一存储单元11和参考单元31的对比，来判断第一存储单元11的存储状态，通过第二存储单元21和参考单元31的对比，来判断第二存储单元21的存储状态。
具体地，在一些示例中，可通过第一存储单元11和参考单元31的对比，判断第一存储单元11处于高阻态或低阻态，进而判断第一存储单元11的存储状态，例如，通过第一存储单元11与参考单元31对比，判断第一存储单元11为高阻态时，定义第一存储单元11处于第一存储状态，当第一存储单元11与参考单元31对比，判断第一存储单元11为低阻态时，则定义第一存储单元11处于第二存储状态。第二存储单元21与参考单元31的对比以及存储状态的判 断与第一存储单元11相同。
由此根据本公开实施例的非易失性存储器，第一存储单元11和第二存储单元21共享同一参考单元31，这样不需要外接参考源，可以简化非易失性存储器的结构，避免产生尾位效应而影响存储器的性能，而且两个存储单元共用一个参考单元31，在相同面积下的存储器，从而能够增加存储器的内存密度和存储容量，在形成相同内存的存储器，也能够减少基本单元的设置，使得存储器面积较小，提高非易失性存储器的集成度。
在一些示例中，在判断第一存储单元11和第二存储单元21的存储状态时，参考单元31的参考信号相同，即在对第一存储单元11和参考单元31进行对比时，以及第二存储单元21与参考单元31进行对比时，参考单元31提供的参考信号相同，由此，使得第一存储单元11和第二存储单元21的存储状态的参考标准相同，有利于第一存储单元11和第二存储单元21的存储状态的判断，且可不需要改变参考单元31的参考信号，也能够简化非易失性存储器的结构。
在本公开的一些实施例中，第一存储单元11连接第一位线12和第一选通管13，第二存储单元21连接第二位线22和第二选通管23，参考单元31连接参考位线32和参考选通管33。具体地，第一存储单元11的一端与第一选通管13串联，第二存储单元21的另一端与第一位线12连接，第一选通管13的一端与第二选通管23串联，第二储存单元的另一端与第二位线22连接，参考单元31的一端与参考选通管33串联，参考单元31的另一端与参考位线32连接，第一选通管13、第二选通管23和参考选通管33可以通过电信号使其导通与关断。可选地，第一选通管13、第二选通管23和参考选通管33可以均为晶体管，例如均可以为二极管或三极管等，对此本公开不作特殊限定。
如图1所示，串联的第一存储单元11和第一选通管13、串联的第二存储单元21和第二选通管23以及串联的参考单元31和参考选通管33并联，串联的参考单元31和参考选通管33位于串联的第一存储单元11和第一选通管13以及串联的第二存储单元21和第二选通管23之间。第一选通管13、第二选通管23和参考选通管33还均连接至同一字线41，第一选通管13的源端、第二选通管23的源端和参考选通管33的源端均连接至同一源线42。具体地，第一选通管13的漏端与第一存储单元11直接连接，第二选通管23的漏端与第二 存储单元21直接连接，参考选通管33的漏端与参考单元31直接连接，第一选通管13的栅端、第二选通管23的栅端和参考选通管33的栅端同时并联连接至同一字线41，第一选通管13的源端、第二选通管23的源端和参考选通管33的源端同时并联连接至同一源线42，使得第一选通管13、第二选通管23和参考选通管33具有相同的结构参数，以及第一存储单元11和第二存储单元21以及参考单元31具有相同的结构参数。
在本公开的一些实施例中，第一存储单元11、第二存储单元21和参考单元31为同一类型存储器的单元，即第一存储单元11、第二存储单元21和参考单元31采用同以类型的半导体存储结构，例如，第一存储单元11、第二存储单元21和参考单元31可以均为磁性存储器的单元、相变存储器的单元、铁电存储器的单元或阻变存储器的单元。
在一些具体示例中，第一存储单元11、第二存储单元21和参考单元31均为磁性存储器的单元，所述非易失性存储器形成为磁性存储器(MRAM)，磁性存储器的单元包括自由层、中间层和固定层，通过自由层和固定层磁矩方向的变化来存储信息，存储器读取电路是通过加载相同的电压判断输出电流的大小从而判断存储器的信息。在另一些具体示例中，第一存储单元11、第二存储单元21和参考单元31均为相变存储器的单元，所述非易失性存储器为相变存储器(PCRAM)，通过相变材料在电流的焦耳热作用下，在结晶相态和非晶相态之间快速并可逆的转换时，会呈现出的不同电阻率这一特性来实现数据存储。
在本公开的又一些示例中，第一存储单元11、第二存储单元21和参考单元31还可以均为铁电存储器的单元，所述非易失性存储器为铁电存储器(FeRAM)；或者第一存储单元11、第二存储单元21和参考单元31均为阻变存储器的单元，所述非易失性存储器为阻变存储器(RRAM)。
在本公开的一些实施例中，非易失性存储器还可以包括比较器43，第一位线12、第二位线22和参考位线32均连接于比较器43的输入端，通过共享参考单元31的设置可采用比较器43进行数据比较，而不需要设置感测放大器等结构，不仅可以提高感测效率和感测可靠性，也可简化非易失性存储器的外围电路的结构，进一步地提高存储器的集成度。
下面参考附图描述一种非易失性存储器的写入方法。
根据本公开实施例的非易失性存储器包括第一存储单元11、第二存储单元21和参考单元31，第一存储单元11和第二存储单元21共享参考单元31，参考单元31用于提供参考信号值，以判断第一存储单元11和第二存储单元21的存储状态；所述写入方法适用于上述任一实施例的非易失性存储器。
如图2所示，根据本公开实施例的写入方法可以包括如下步骤：
向第一存储单元11施加第一电信号以提供大于参考信号值的第一存储信号值，使得第一存储单元11处于第一存储状态；向第一存储单元11施加第二电信号以提供小于参考信号值的第二存储信号值，使得第一存储单元11处于第二存储状态。
具体地，可通过字线41和位线向第一存储单元11和参考单元31施加电信号如电流，施加的电信号值不同，第一存储单元11的存储状态不同，则向第一存储单元11写入数据不同。在对第一存储单元11进行编程操作时，如向第一存储单元11写入第一值时，使得第一存储单元11处于第一存储状态，则向第一存储单元11施加第一电信号以提供大于参考信号值的第一存储信号值，在向第一存储单元11写入第二值时，使得第一存储单元11处于第二存储状态，则向第一存储单元11施加第二电信号以提供小于参考信号值的第二存储信号值。
其中第一存储状态和第二存储状态可以为电压状态、电阻状态或电流状态，存储器的类型不同，则存储单元表现的数据状态不同，为了便于描述，下面以存储状态呈现为电阻状态进行描述。存储单元的写入数据值如第一值和第二值可以定义为二进制数，例如可定义第一值为二进制数0，第二值为二进制数1，具体编程操作对应的数据值“1”或“0”的可根据需要进行定义，在此不作限定。
在一些具体示例中，第一存储状态可定义为高阻态，第二存储状态可定义为低阻态，在进行编程操作时，当第一存储单元11为第一存储状态即高阻态时，向第一存储单元11施加第一电信号，使得第一存储单元11产生的第一存储信号值大于参考单元31的参考信号值，以使得第一存储单元11表现为高阻态，对应的写入第一值记作“0”，当第一存储单元11为第二存储状态即低阻 态时，向第一存储单元11施加第二电信号，使得第一存储单元11产生的第二存储信号值小于参考单元31的参考信号值，使得第一存储单元11表现为低阻态，对应的写入第二值记作“1”。
向第二存储单元21施加第三电信号以提供大于参考信号值的第三存储信号值，使得第二存储单元21处于第三存储状态；向第二存储单元21施加第四电信号以提供小于参考信号值的第四存储信号值，使得第二存储单元21处于第四存储状态。
具体地，可通过字线41和位线向第二存储单元21和参考单元31施加电信号如电流，施加的电信号值不同，第二存储单元21的存储状态不同，则向第二存储单元21写入数据不同。第二存储单元21的第三存储状态可定义为高阻态，第二存储单元21的第四存储状态可定义为低阻态，在进行编程操作时，当第二存储单元21为第三存储状态即高阻态时，向第二存储单元21施加第三电信号，使得第二存储单元21产生的第三存储信号值大于参考单元31的参考信号值，以使得第二存储单元21表现为高阻态，对应的写入数据值记作“0”，当第二存储单元21为第四存储状态即低阻态时，向第二存储单元21施加第四电信号，使得第二存储单元21产生的第四存储信号值小于参考单元31的参考信号值，使得第二存储单元21表现为低阻态，对应的写入数据值记作“1”。
在本公开的一些实施例中，在向第一存储单元11和第二存储单元21施加电信号时，参考单元31的参考信号值相同，由此在向第一存储单元11和第二存储单元21写入数据时，参考单元31被施加的电信号相同，不需要执行改变参考单元31施加的电信号的操作，也利于第一存储单元11和第二存储单元21写入数据时产生的电信号的参考对比，参考标准一致，使得第一存储单元11和第二存储单元21的存储状态的判断更加准确。
在本公开的一些实施例中，非易失性存储器还包括比较器43，当存储单元为第一存储状态或第三存储状态时，比较器43为第一信号状态；当存储单元为第二存储状态或第四存储状态时，比较器43为第二信号状态，其中第一信号状态和第二信号状态可呈现为数据状态，例如呈现数据值“1”或“0”。
在本公开的一些具体示例中，当第一存储单元11被施加第一电信号，处于第一存储状态时如处于高阻态，当第二存储单元21被施加第三电信号，处 于第三存储状态即处于高阻态时，比较器43均为第一信号状态，存储了第一数据值，呈现了“0”的编程操作，当第一存储单元11被施加第二电信号，处于第二存储状态时如处于低阻态，当第二存储单元21被施加第四电信号，处于第四存储状态即处于低阻态时，比较器43均为第二信号状态，存储了第二数据状态，呈现了“1”的编程操作。
本公开还提出了一种非易失性存储器的读取方法。
所述非易失性存储器包括第一存储单元11、第二存储单元21和参考单元31，第一存储单元11和第二存储单元21共享参考单元31，参考单元31用于提供参考信号，以判断第一存储单元11和第二存储单元21的存储状态，
如图3所示，根据本公开实施例的读取方法包括以下步骤包括：
向第一存储单元11施加电信号并产生第一存储单元11的存储信号值；
将第一存储单元11的存储信号值与参考单元31的参考信号值比较，当第一存储单元11的存储信号值大于参考信号值时，第一存储单元11读取为第一存储状态，当第一存储单元11的存储信号值小于参考信号值时，第一存储单元11读取为第二存储状态；
向第二存储单元21施加电信号并产生第二存储单元21的存储信号值；
将第二存储单元21的存储信号值与参考单元31的参考信号值比较，当第二存储单元21的存储信号值大于参考信号值时，第二存储单元21读取为第三存储状态，当第二存储单元21的存储信号值小于参考信号值时，第二存储单元21读取为第四存储状态。
需要说明的是，这里的存储信号值和参考信号值可以为电压值、电阻值或电流值，具体可根据存储器的类型选择，下面以存储信号值和参考信号值为电阻值为例进行描述。
在进行读取操作时，向第一存储单元11施加电信号，使得第一存储单元11产生存储信号值，通过将存储信号值与参考单元31的参考信号值进行比较来判断第一存储单元11的存储状态，以读取第一存储单元11的数据状态。
例如第一存储单元11产生的存储信号值大于参考信号值时，则判断第一存储单元11处于第一存储状态即高阻态，则可以读取第一存储单元11存储信息为“0”，当第一存储单元11产生的存储信号值小于参考信号值时，则判断 第一存储单元11处于第二存储状态即低阻态，则可以读取第一存储单元11存储信息为“1”。
在进行读取操作时，向第二存储单元21施加电信号，使得第二存储单元21产生存储信号值，通过将存储信号值与参考单元31的参考信号值进行比较来判断第二存储单元21的存储状态，以读取第二存储单元21的数据状态。
例如第二存储单元21产生的存储信号值大于参考信号值时，则判断第二存储单元21处于第三存储状态即高阻态，则可以读取第二存储单元21存储信息为“0”，当第一存储单元11产生的存储信号值小于参考信号值时，则判断第一存储单元11处于第四存储状态即低阻态，则可以读取第二存储单元21存储信息为“1”。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (16)

  1. 一种非易失性存储器，其中，包括第一存储单元、第二存储单元和参考单元，所述第一存储单元和所述第二存储单元共享所述参考单元，所述参考单元用于提供参考信号，以判断所述第一存储单元和所述第二存储单元的存储状态。
  2. 根据权利要求1所述的非易失性存储器，其中，所述第一存储单元连接第一位线和第一选通管，所述第二存储单元连接第二位线和第二选通管，所述参考单元连接参考位线和参考选通管。
  3. 根据权利要求2所述的非易失性存储器，其中，串联的所述第一存储单元和所述第一选通管、串联的所述第二存储单元和所述第二选通管以及串联的所述参考单元和所述参考选通管并联。
  4. 根据权利要求2所述的非易失性存储器，其中，所述第一选通管、所述第二选通管和所述参考选通管均为晶体管。
  5. 根据权利要求2所述的非易失性存储器，其中，所述第一选通管、所述第二选通管和所述参考选通管连接至同一字线，所述第一选通管的源端、所述第二选通管的源端和所述参考选通管的源端连接至同一源线。
  6. 根据权利要求1所述的非易失性存储器，其中，所述第一存储单元、所述第二存储单元和所述参考单元为同一类型存储器的单元。
  7. 根据权利要求6所述的非易失性存储器，其中，在判断所述第一存储单元和所述第二存储单元的存储状态时，所述参考单元的参考信号相同。
  8. 根据权利要求6所述的非易失性存储器，其中，所述第一存储单元、所述第二存储单元和所述参考单元均为磁性存储器的单元。
  9. 根据权利要求6所述的非易失性存储器，其中，所述第一存储单元、所述第二存储单元和所述参考单元均为相变存储器的单元。
  10. 根据权利要求6所述的非易失性存储器，其中，所述第一存储单元、所述第二存储单元和所述参考单元均为铁电存储器的单元。
  11. 根据权利要求6所述的非易失性存储器，其中，所述第一存储单元、所述第二存储单元和所述参考单元均为阻变存储器的单元。
  12. 根据权利要求2所述的非易失性存储器，其中，还包括比较器，所述第一位线、第二位线和所述参考位线均连接于所述比较器的输入端。
  13. 一种非易失性存储器的写入方法，其中，所述非易失性存储器包括第一存储单元、第二存储单元和参考单元，所述第一存储单元和所述第二存储单元共享所述参考单元，所述参考单元用于提供参考信号值，以判断所述第一存储单元和所述第二存储单元的存储状态；
    所述写入方法包括：
    向所述第一存储单元施加第一电信号以提供大于所述参考信号值的第一存储信号值，使得所述第一存储单元处于第一存储状态；
    向所述第一存储单元施加第二电信号以提供小于所述参考信号值的第二存储信号值，使得所述第一存储单元处于第二存储状态；
    向所述第二存储单元施加第三电信号以提供大于所述参考信号值的第三存储信号值，使得所述第二存储单元处于第三存储状态；
    向所述第二存储单元施加第四电信号以提供小于所述参考信号值的第四存储信号值，使得所述第二存储单元处于第四存储状态。
  14. 根据权利要求13所述的写入方法，其中，在向所述第一存储单元和所述第二存储单元施加电信号时，所述参考单元的参考信号值相同。
  15. 根据权利要求13所述的写入方法，其中，所述非易失性存储器还包括比较器，当所述存储单元为所述第一存储状态或所述第三存储状态时，所述比较器为第一信号状态；
    当所述存储单元为所述第二存储状态或所述第四存储状态时，所述比较器为第二信号状态。
  16. 一种非易失性存储器的读取方法，其中，所述非易失性存储器包括第一存储单元、第二存储单元和参考单元，所述第一存储单元和所述第二存储单元共享所述参考单元，所述参考单元用于提供参考信号，以判断所述第一存储单元和所述第二存储单元的存储状态；
    所述读取方法包括：
    向所述第一存储单元施加电信号并产生第一存储单元的存储信号值；
    将所述第一存储单元的存储信号值与所述参考单元的参考信号值比较，当所述第一存储单元的存储信号值大于所述参考信号值时，所述第一存储单元读取为第一存储状态，当所述第一存储单元的存储信号值小于所述参考 信号值时，所述第一存储单元读取为第二存储状态；
    向所述第二存储单元施加电信号并产生第二存储单元的存储信号值；
    将所述第二存储单元的存储信号值与所述参考单元的参考信号值比较，当所述第二存储单元的存储信号值大于所述参考信号值时，所述第二存储单元读取为第三存储状态，当所述第二存储单元的存储信号值小于所述参考信号值时，所述第二存储单元读取为第四存储状态。
PCT/CN2022/090355 2021-08-31 2022-04-29 非易失性存储器及其写入方法和读取方法 WO2023029539A1 (zh)

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CN103903650A (zh) * 2014-03-17 2014-07-02 上海华虹宏力半导体制造有限公司 存储器阵列及其控制方法和闪存
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CN103035290A (zh) * 2012-11-30 2013-04-10 珠海艾派克微电子有限公司 Eeprom电路、数据读取方法以及非易失性存储器
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