WO2023029133A1 - 显示装置 - Google Patents

显示装置 Download PDF

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Publication number
WO2023029133A1
WO2023029133A1 PCT/CN2021/120883 CN2021120883W WO2023029133A1 WO 2023029133 A1 WO2023029133 A1 WO 2023029133A1 CN 2021120883 W CN2021120883 W CN 2021120883W WO 2023029133 A1 WO2023029133 A1 WO 2023029133A1
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WO
WIPO (PCT)
Prior art keywords
module
clock
input terminal
output
signal
Prior art date
Application number
PCT/CN2021/120883
Other languages
English (en)
French (fr)
Inventor
刘金风
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/607,844 priority Critical patent/US12008938B2/en
Publication of WO2023029133A1 publication Critical patent/WO2023029133A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal

Definitions

  • the present application relates to the field of display technology, in particular to a display device.
  • P2P point-to-point transmission protocol
  • the advantage of the P2P protocol is that the clock signal is not directly transmitted during the actual transmission process, but the clock signal is embedded in the data channel, and the clock signal is recovered from the data signal by the data driver chip, which is used as the reference clock inside the data driver chip. Since the clock signal is not actually transmitted, there is no need to be limited by the distortion of the clock waveform, and the transmission speed is greatly improved.
  • the present application provides a display device, which can solve the technical problem that the test performance of electromagnetic interference in the display device fluctuates greatly, resulting in unstable performance of electromagnetic interference.
  • the present application provides a display device, which includes:
  • the clock control chip is used to transmit display signals
  • a data driving chip is connected to the clock control chip, and the data driving chip is used to adjust the phase of the clock signal output by the data driving chip based on the display signal.
  • the data driver chip includes a clock generation module, a frequency confirmation module, a pattern detection module and an output control module, the clock generation module is connected to the frequency confirmation module, and the clock generation module And the pattern detection module is connected with the output control module;
  • the clock generating module is used to generate an initial clock signal
  • the frequency confirmation module is used to receive the display signal and the initial clock signal, and output a feedback signal to the clock generation module based on the display signal and the initial clock signal, so as to control the clock generation module to adjust the the frequency of the initial clock signal, and output the adjusted initial clock signal to the output control module;
  • the pattern detection module is used to receive the display signal, and obtain phase alignment starting point information based on the display signal and output it to the output control module;
  • the output control module is configured to output the clock signal based on the adjusted initial clock signal and the phase alignment starting point information.
  • the clock generating module has a first clock output terminal, a second clock output terminal and a feedback input terminal;
  • the first clock output terminal is connected to the frequency confirmation module, and the clock generation module outputs the initial clock signal to the frequency confirmation module through the first clock output terminal;
  • the second clock output terminal is connected to the output control module, and the clock generation module outputs the adjusted initial clock signal to the output control module through the second clock output terminal;
  • the feedback input terminal is connected to the frequency confirmation module, and the clock generation module receives the feedback signal through the feedback input terminal.
  • the frequency confirmation module has a first frequency confirmation input terminal, a second frequency confirmation input terminal and a feedback output terminal;
  • the first frequency confirmation input terminal is connected to the clock generation module, and the frequency confirmation module receives the initial clock signal through the first frequency confirmation input terminal;
  • the second frequency confirmation input terminal is connected to the clock control chip, and the frequency confirmation module receives the display signal through the second frequency confirmation input terminal;
  • the feedback output terminal is connected to the clock generation module, and the frequency confirmation module outputs the feedback signal through the feedback output terminal.
  • the pattern detection module has a pattern confirmation input terminal and a pattern confirmation output terminal;
  • the code pattern confirmation input terminal is connected to the clock control chip, and the code pattern detection module receives the display signal through the code pattern confirmation input terminal;
  • the pattern confirmation output terminal is connected to the output control module, and the pattern detection module outputs the phase alignment starting point information through the pattern confirmation output terminal.
  • the output control module has a first input terminal, a second input terminal and an output terminal;
  • the first input terminal is connected to the clock generation module, and the output control module receives the adjusted initial clock signal through the first input terminal;
  • the second input terminal is connected to the pattern detection module, and the output control module receives the phase alignment starting point information through the second input terminal;
  • the output control module outputs the clock signal through the output terminal.
  • the phase alignment starting point information includes a rising edge starting point or a falling edge starting point.
  • the output control module when the output control module receives the starting point of the rising edge or the starting point of the falling edge, the output control module resets the adjusted initial clock signal to Obtain the clock signal.
  • the driver chip further includes a filter module, the filter module is connected to the clock generation module and the frequency confirmation module, and the filter module is used to filter the feedback signal .
  • the filter module has a filter input terminal and a filter output terminal
  • the filter input terminal is connected to the frequency confirmation module, and the filter module receives the feedback signal through the filter input terminal;
  • the filter output terminal is connected to the output control module, and the filter module outputs the filtered feedback signal through the filter output terminal.
  • the present application also provides a display device, which includes:
  • the clock control chip is used to transmit display signals
  • a data driving chip is connected to the clock control chip, and the data driving chip is used to adjust the phase of the clock signal output by the data driving chip based on the display signal;
  • the data driver chip includes a clock generation module, a frequency confirmation module, a pattern detection module and an output control module, the clock generation module is connected to the frequency confirmation module, and the clock generation module and the pattern detection module are connected to each other.
  • the output control module is connected; wherein,
  • the clock generating module is used to generate an initial clock signal
  • the frequency confirmation module is used to receive the display signal and the initial clock signal, and output a feedback signal to the clock generation module based on the display signal and the initial clock signal, so as to control the clock generation module to adjust the the frequency of the initial clock signal, and output the adjusted initial clock signal to the output control module;
  • the pattern detection module is used to receive the display signal, and obtain phase alignment starting point information based on the display signal and output it to the output control module;
  • the output control module is configured to output the clock signal based on the adjusted initial clock signal and the phase alignment starting point information
  • the phase alignment starting point information includes a rising edge starting point or a falling edge starting point.
  • the clock generating module has a first clock output terminal, a second clock output terminal and a feedback input terminal;
  • the first clock output terminal is connected to the frequency confirmation module, and the clock generation module outputs the initial clock signal to the frequency confirmation module through the first clock output terminal;
  • the second clock output terminal is connected to the output control module, and the clock generation module outputs the adjusted initial clock signal to the output control module through the second clock output terminal;
  • the feedback input terminal is connected to the frequency confirmation module, and the clock generation module receives the feedback signal through the feedback input terminal.
  • the frequency confirmation module has a first frequency confirmation input terminal, a second frequency confirmation input terminal and a feedback output terminal;
  • the first frequency confirmation input terminal is connected to the clock generation module, and the frequency confirmation module receives the initial clock signal through the first frequency confirmation input terminal;
  • the second frequency confirmation input terminal is connected to the clock control chip, and the frequency confirmation module receives the display signal through the second frequency confirmation input terminal;
  • the feedback output terminal is connected to the clock generation module, and the frequency confirmation module outputs the feedback signal through the feedback output terminal.
  • the pattern detection module has a pattern confirmation input terminal and a pattern confirmation output terminal;
  • the code pattern confirmation input terminal is connected to the clock control chip, and the code pattern detection module receives the display signal through the code pattern confirmation input terminal;
  • the pattern confirmation output terminal is connected to the output control module, and the pattern detection module outputs the phase alignment starting point information through the pattern confirmation output terminal.
  • the output control module has a first input terminal, a second input terminal and an output terminal;
  • the first input terminal is connected to the clock generation module, and the output control module receives the adjusted initial clock signal through the first input terminal;
  • the second input terminal is connected to the pattern detection module, and the output control module receives the phase alignment starting point information through the second input terminal;
  • the output control module outputs the clock signal through the output terminal.
  • the output control module when the output control module receives the starting point of the rising edge or the starting point of the falling edge, the output control module resets the adjusted initial clock signal to Obtain the clock signal.
  • the driver chip further includes a filter module, the filter module is connected to the clock generation module and the frequency confirmation module, and the filter module is used to filter the feedback signal .
  • the filter module has a filter input terminal and a filter output terminal
  • the filter input terminal is connected to the frequency confirmation module, and the filter module receives the feedback signal through the filter input terminal;
  • the filter output terminal is connected to the output control module, and the filter module outputs the filtered feedback signal through the filter output terminal.
  • the phase of the clock signal output by the data driver chip is adjusted based on the display signal in the data driver chip, and a new clock phase alignment mechanism is added to make the phase differences of the clock signals generated inside different data driver chips consistent. Rebooting will not cause the phase difference to change, thereby improving the stability of the electromagnetic interference test performance.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a data drive chip provided by an embodiment of the present application.
  • Fig. 3 is a specific connection schematic diagram of the clock generation module provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of specific connection of the frequency confirmation module provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of the specific connection of the frequency confirmation module provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of the specific connection of the frequency confirmation module provided by the embodiment of the present application.
  • FIG. 7 is a schematic diagram of the starting point of the rising edge provided by the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a pattern detection module provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the starting point of the falling edge provided by the embodiment of the present application.
  • Fig. 10 is another schematic structural diagram of the pattern detection module provided by the embodiment of the present application.
  • FIG. 11 is another schematic structural diagram of the data driving chip provided by the embodiment of the present application.
  • An embodiment of the present application provides a display device, which can solve the technical problem that the test performance of electromagnetic interference in the display device fluctuates greatly, resulting in unstable performance of electromagnetic interference. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 10 provided by the embodiment of the present application includes a clock control chip 100 and a data driving chip 200 .
  • the data driving chip 200 is connected to the clock control chip 100 .
  • the clock control chip 100 is used for transmitting the display signal D.
  • the data driving chip 200 is used for adjusting the phase of the clock signal C2 output by the data driving chip 200 based on the display signal D.
  • the phase of the clock signal C2 output by the data driving chip 200 is adjusted based on the display signal D in the data driving chip 200, and a new clock phase alignment mechanism is added, so that the clocks generated inside different data driving chips The signal phase difference is consistent, and each restart will not cause the phase difference to change, thereby improving the stability of the electromagnetic interference test performance.
  • FIG. 2 is a schematic structural diagram of a data driving chip provided by an embodiment of the present application.
  • the data driver chip 200 includes a clock generation module 201 , a frequency confirmation module 202 , a pattern detection module 203 and an output control module 204 .
  • the clock generation module 201 is connected to the frequency confirmation module 202 .
  • Both the clock generation module 201 and the pattern detection module 203 are connected to the output control module 204 .
  • the clock generating module 201 is used to generate an initial clock signal C1.
  • the frequency confirmation module 202 is used to receive the display signal D and the initial clock signal C1, and output the feedback signal B to the clock generation module 201 based on the display signal D and the initial clock signal C1, so as to control the clock generation module 201 to adjust the frequency of the initial clock signal C1, And output the adjusted initial clock signal C1 to the output control module 204 .
  • the pattern detection module 203 is used to receive the display signal D, and obtain phase alignment starting point information A based on the display signal D, and output it to the output control module 204 .
  • the output control module 204 is configured to output the clock signal C2 based on the adjusted initial clock signal C1 and the phase alignment starting point information A.
  • FIG. 3 is a schematic diagram of specific connection of the clock generation module provided by the embodiment of the present application.
  • the clock generation module 201 has a first clock output terminal a1 , a second clock output terminal a2 and a feedback input terminal a3 .
  • the first clock output terminal a1 is connected to the frequency confirmation module 202 , and the clock generation module 201 outputs an initial clock signal C1 to the frequency confirmation module 202 through the first clock output terminal a.
  • the second clock output terminal a2 is connected to the output control module 204 , and the clock generation module 201 outputs the adjusted initial clock signal C1 to the output control module 204 through the second clock output terminal a2 .
  • the feedback input terminal a3 is connected to the frequency confirmation module 202, and the clock generation module 201 receives the feedback signal B through the feedback input terminal a3.
  • FIG. 4 is a specific connection schematic diagram of the frequency confirmation module 202 provided by the embodiment of the present application.
  • the frequency confirmation module 202 has a first frequency confirmation input terminal b1, a second frequency confirmation input terminal b2, and a feedback output terminal d3b3.
  • the first frequency confirmation input terminal b1 is connected to the clock generation module 201, and the frequency confirmation module 202 receives the initial clock signal c1 through the first frequency confirmation input terminal b1.
  • the second frequency confirmation input terminal b2 is connected to the clock control chip 100, and the frequency confirmation module 202 receives the display signal D through the second frequency confirmation input terminal b2.
  • the feedback output terminal b3 is connected to the clock generation module 201, and the frequency confirmation module 202 outputs the feedback signal B through the feedback output terminal b3.
  • FIG. 5 is a specific connection schematic diagram of the frequency confirmation module 202 provided by the embodiment of the present application.
  • the pattern detection module 203 has a pattern confirmation input terminal c1 and a pattern confirmation output terminal c2.
  • the pattern confirmation input terminal c1 is connected to the clock control chip 100 , and the pattern detection module 203 receives the display signal D through the pattern confirmation input terminal c1 .
  • the pattern confirmation output terminal c2 is connected to the output control module 204, and the pattern detection module 203 outputs phase alignment starting point information A through the pattern confirmation output terminal c2.
  • FIG. 6 is a specific connection diagram of the frequency confirmation module 202 provided by the embodiment of the present application.
  • the output control module 204 has a first input terminal d1 , a second input terminal d2 and an output terminal d3 .
  • the first input terminal d1 is connected to the clock generation module 201, and the output control module 204 receives the adjusted initial clock signal c1 through the first input terminal d1.
  • the second input terminal d2 is connected to the pattern detection module 203, and the output control module 204 receives the phase alignment starting point information A through the second input terminal d2.
  • the output control module 204 outputs the clock signal C2 through the output terminal d3.
  • the phase alignment starting point information A includes a rising edge starting point.
  • the output control module 204 receives the starting point of the rising edge, the output control module 204 resets the adjusted initial clock signal c1 to obtain the clock signal C2.
  • FIG. 7 is a schematic diagram of a starting point of a rising edge provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of the pattern detection module 203 provided by the embodiment of the present application. 7 and 8, if the display signal D is a sequence of "10000111110000111", the phase alignment start point information A can be output by detecting the sequence of the display signal D.
  • the pattern detection module 203 includes an inverter 2031 and an AND gate 2031, wherein, one end of the inverter 2031 receives the current position symbol of the display signal D, and the other end of the inverter 2031 is connected to an AND gate 2031.
  • the input terminal is connected, and the other input terminal of the AND gate 2031 receives the next position symbol of the display signal D.
  • the pattern detection module 203 outputs the phase alignment starting point information A to the output control module 204, and the output control module 204
  • the adjusted initial clock signal c1 is reset to obtain a clock signal C2.
  • the phase alignment start point information A includes a falling edge start point.
  • the output control module 204 receives the starting point of the falling edge, the output control module 204 resets the adjusted initial clock signal c1 to obtain the clock signal c2.
  • FIG. 9 is a schematic diagram of a starting point of a falling edge provided by an embodiment of the present application.
  • FIG. 10 is another schematic structural diagram of the pattern detection module 203 provided by the embodiment of the present application. 9 and 10, if the display signal D is a sequence of "10000111110000111", the phase alignment start point information A can be output by detecting the sequence of the display signal D.
  • the pattern detection module 203 includes an inverter 2031 and an AND gate 2032, wherein, an input end of the AND gate 2032 receives the current position symbol of the display signal D, and one end of the inverter 2031 receives the lower signal of the display signal D.
  • a position symbol the other end of the inverter 2031 is connected to an input end of the AND gate 2032 .
  • the pattern detection module 203 outputs the phase alignment starting point information A to the output control module 204, and the output control module 204
  • the adjusted initial clock signal c1 is reset to obtain a clock signal C2.
  • the P2P point-to-point transmission protocol adopts clock embedding technology, and the clock information contained in the display signal D needs to be recovered by the data driver chip 200.
  • the specific process is that the CD data driver chip 200 receives the display signal D, and the frequency confirmation module 202 By comparing the frequency of the Data IN display signal D with the initial clock signal c1 generated by the clock generation module 201, as a feedback input, the output clock frequency of the clock generation module 201 is controlled, and the dynamic cycle ensures that the frequency of the input display signal D is consistent with the internal clock frequency Similarly, the clock signal obtained by sampling can correctly identify the digital signal information and transmit it to the next-level circuit, so as to realize the normal driving and display of the entire data driving chip 200 .
  • FIG. 11 is another schematic structural diagram of the data driving chip provided by the embodiment of the present application.
  • the difference between the data driving chip 300 shown in FIG. 11 and the data driving chip 200 shown in FIG. 2 is that the data driving chip 300 shown in FIG. 11 further includes a filtering module 205 .
  • the filter module 205 is connected with the clock generation module 201 and the frequency confirmation module 202 .
  • the filtering module 205 is used for filtering the feedback signal B.
  • the filtering module 205 is an electronic filtering device that allows signals lower than the cutoff frequency to pass through, but signals higher than the cutoff frequency cannot pass through, and filters signals with non-effective frequencies.
  • the filtering module 205 has a filtering input terminal e1 and a filtering output terminal e2.
  • the filtering input terminal e1 is connected to the frequency confirmation module 202, and the filtering module 205 receives the feedback signal B through the filtering input terminal e1.
  • the filter output terminal e2 is connected to the output control module 204, and the filter module 205 outputs the filtered feedback signal b through the filter output terminal e2.
  • the phase of the clock signal output by the data driver chip is adjusted based on the display signal in the data driver chip, and a new clock phase alignment mechanism is added to make the phase differences of the clock signals generated inside different data driver chips consistent. Rebooting will not cause the phase difference to change, thereby improving the stability of the electromagnetic interference test performance.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示装置（10），包括：时钟控制芯片（100），时钟控制芯片（100）用于传输显示信号（D）；以及数据驱动芯片（200），数据驱动芯片（200）与时钟控制芯片（100）连接，数据驱动芯片（200）用于基于显示信号（D）调整数据驱动芯片（200）输出的时钟信号（C2）的相位。

Description

显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示装置。
 背景技术
随着显示业高解析度以及高刷新率的发展，需要更高速率的传输协议，Minilvds已经不能满足需求，目前P2P（点对点传输协议）已经成为主流。P2P协议的优势是实际传输过程中不直接传输时钟信号，而是将时钟信号内嵌到数据通道中，通过数据驱动芯片从数据信号中恢复产生时钟信号，供数据驱动芯片内部作为基准时钟。由于不实际传输时钟信号，因此无需受时钟波形的失真限制，传输速度大大提升。
然而，对于单颗数据驱动芯片而言，目前的设定只需要能解出正确的频率的时钟即可，显示装置就能正常显示。但实际应用也存在一些问题，例如大尺寸显示装置上的应用需求多颗驱动芯片，由于缺少时钟相位对齐机制，不同的数据驱动芯片内部产生的时钟信号相位差存在随机性，每次重新开机都会导致相位差变化。虽然对显示没有影响，但会导致电磁干扰的测试表现波动很大，从而造成电磁干扰表现不稳定。
 技术问题
本申请提供一种显示装置，可以解决显示装置中电磁干扰的测试表现波动很大，造成电磁干扰表现不稳定的技术问题。
 技术解决方案
第一方面，本申请提供一种显示装置，其包括：
时钟控制芯片，所述时钟控制芯片用于传输显示信号；以及
数据驱动芯片，所述数据驱动芯片与所述时钟控制芯片连接，所述数据驱动芯片用于基于所述显示信号调整所述数据驱动芯片输出的时钟信号的相位。
在本申请提供的显示装置中，所述数据驱动芯片包括时钟产生模块、频率确认模块、码型检测模块以及输出控制模块，所述时钟产生模块与所述频率确认模块连接，所述时钟产生模块以及所述码型检测模块均与所述输出控制模块连接；其中，
所述时钟产生模块用于生成初始时钟信号；
所述频率确认模块用于接收所述显示信号以及所述初始时钟信号，并基于所述显示信号以及所述初始时钟信号输出反馈信号至所述时钟产生模块，以控制所述时钟产生模块调整所述初始时钟信号的频率，并将调整后的所述初始时钟信号输出至所述输出控制模块；
所述码型检测模块用于接收所述显示信号，并基于所述显示信号获取相位对齐起始点信息输出至所述输出控制模块；
所述输出控制模块用于基于调整后的所述初始时钟信号以及所述相位对齐起始点信息输出所述时钟信号。
在本申请提供的显示装置中，所述时钟产生模块具有第一时钟输出端、第二时钟输出端以及反馈输入端；
所述第一时钟输出端与所述频率确认模块连接，所述时钟产生模块通过所述第一时钟输出端输出所述初始时钟信号至所述频率确认模块；
所述第二时钟输出端与所述输出控制模块连接，所述时钟产生模块通过所述第二时钟输出端输出调整后的所述初始时钟信号至所述输出控制模块；
所述反馈输入端与所述频率确认模块连接，所述时钟产生模块通过所述反馈输入端接收所述反馈信号。
在本申请提供的显示装置中，所述频率确认模块具有第一频率确认输入端、第二频率确认输入端以及反馈输出端；
所述第一频率确认输入端与所述时钟产生模块连接，所述频率确认模块通过所述第一频率确认输入端接收所述初始时钟信号；
所述第二频率确认输入端与所述时钟控制芯片连接，所述频率确认模块通过所述第二频率确认输入端接收所述显示信号；
所述反馈输出端与所述时钟产生模块连接，所述频率确认模块通过所述反馈输出端输出所述反馈信号。
在本申请提供的显示装置中，所述码型检测模块具有码型确认输入端以及码型确认输出端；
所述码型确认输入端与所述时钟控制芯片连接，所述码型检测模块通过所述码型确认输入端接收所述显示信号；
所述码型确认输出端与所述输出控制模块连接，所述码型检测模块通过所述码型确认输出端输出所述相位对齐起始点信息。
在本申请提供的显示装置中，所述输出控制模块具有第一输入端、第二输入端以及输出端；
所述第一输入端与所述时钟产生模块连接，所述输出控制模块通过所述第一输入端接收调整后的所述初始时钟信号；
所述第二输入端与所述码型检测模块连接，所述输出控制模块通过所述第二输入端接收所述相位对齐起始点信息；
所述输出控制模块通过所述输出端输出所述时钟信号。
在本申请提供的显示装置中，所述相位对齐起始点信息包括上升沿起始点或下降沿起始点。
在本申请提供的显示装置中，当所述输出控制模块接收到所述上升沿起始点或者所述下降沿起始点时，所述输出控制模块对调整后的所述初始时钟信号进行复位，以获得所述时钟信号。
在本申请提供的显示装置中，所述驱动芯片还包括滤波模块，所述滤波模块与所述时钟产生模块以及所述频率确认模块连接，所述滤波模块用于对所述反馈信号进行滤波处理。
在本申请提供的显示装置中，所述滤波模块具有滤波输入端以及滤波输出端；
所述滤波输入端与所述频率确认模块连接，所述滤波模块通过所述滤波输入端接收所述反馈信号；
所述滤波输出端与所述输出控制模块连接，所述滤波模块通过所述滤波输出端输出滤波后的所述反馈信号。
第二方面，本申请还提供一种显示装置，其包括：
时钟控制芯片，所述时钟控制芯片用于传输显示信号；以及
数据驱动芯片，所述数据驱动芯片与所述时钟控制芯片连接，所述数据驱动芯片用于基于所述显示信号调整所述数据驱动芯片输出的时钟信号的相位；
所述数据驱动芯片包括时钟产生模块、频率确认模块、码型检测模块以及输出控制模块，所述时钟产生模块与所述频率确认模块连接，所述时钟产生模块以及所述码型检测模块均与所述输出控制模块连接；其中，
所述时钟产生模块用于生成初始时钟信号；
所述频率确认模块用于接收所述显示信号以及所述初始时钟信号，并基于所述显示信号以及所述初始时钟信号输出反馈信号至所述时钟产生模块，以控制所述时钟产生模块调整所述初始时钟信号的频率，并将调整后的所述初始时钟信号输出至所述输出控制模块；
所述码型检测模块用于接收所述显示信号，并基于所述显示信号获取相位对齐起始点信息输出至所述输出控制模块；
所述输出控制模块用于基于调整后的所述初始时钟信号以及所述相位对齐起始点信息输出所述时钟信号；
所述相位对齐起始点信息包括上升沿起始点或下降沿起始点。
在本申请提供的显示装置中，所述时钟产生模块具有第一时钟输出端、第二时钟输出端以及反馈输入端；
所述第一时钟输出端与所述频率确认模块连接，所述时钟产生模块通过所述第一时钟输出端输出所述初始时钟信号至所述频率确认模块；
所述第二时钟输出端与所述输出控制模块连接，所述时钟产生模块通过所述第二时钟输出端输出调整后的所述初始时钟信号至所述输出控制模块；
所述反馈输入端与所述频率确认模块连接，所述时钟产生模块通过所述反馈输入端接收所述反馈信号。
在本申请提供的显示装置中，所述频率确认模块具有第一频率确认输入端、第二频率确认输入端以及反馈输出端；
所述第一频率确认输入端与所述时钟产生模块连接，所述频率确认模块通过所述第一频率确认输入端接收所述初始时钟信号；
所述第二频率确认输入端与所述时钟控制芯片连接，所述频率确认模块通过所述第二频率确认输入端接收所述显示信号；
所述反馈输出端与所述时钟产生模块连接，所述频率确认模块通过所述反馈输出端输出所述反馈信号。
在本申请提供的显示装置中，所述码型检测模块具有码型确认输入端以及码型确认输出端；
所述码型确认输入端与所述时钟控制芯片连接，所述码型检测模块通过所述码型确认输入端接收所述显示信号；
所述码型确认输出端与所述输出控制模块连接，所述码型检测模块通过所述码型确认输出端输出所述相位对齐起始点信息。
在本申请提供的显示装置中，所述输出控制模块具有第一输入端、第二输入端以及输出端；
所述第一输入端与所述时钟产生模块连接，所述输出控制模块通过所述第一输入端接收调整后的所述初始时钟信号；
所述第二输入端与所述码型检测模块连接，所述输出控制模块通过所述第二输入端接收所述相位对齐起始点信息；
所述输出控制模块通过所述输出端输出所述时钟信号。
在本申请提供的显示装置中，当所述输出控制模块接收到所述上升沿起始点或者所述下降沿起始点时，所述输出控制模块对调整后的所述初始时钟信号进行复位，以获得所述时钟信号。
在本申请提供的显示装置中，所述驱动芯片还包括滤波模块，所述滤波模块与所述时钟产生模块以及所述频率确认模块连接，所述滤波模块用于对所述反馈信号进行滤波处理。
在本申请提供的显示装置中，所述滤波模块具有滤波输入端以及滤波输出端；
所述滤波输入端与所述频率确认模块连接，所述滤波模块通过所述滤波输入端接收所述反馈信号；
所述滤波输出端与所述输出控制模块连接，所述滤波模块通过所述滤波输出端输出滤波后的所述反馈信号。
 有益效果
本申请提供的显示装置，在数据驱动芯片内基于显示信号调整数据驱动芯片输出的时钟信号的相位，新增时钟相位对齐机制，使得不同的数据驱动芯片内部产生的时钟信号相位差一致，每次重新开机不会导致相位差变化，进而提升电磁干扰的测试表现的稳定性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示装置的结构示意图；
图2为本申请实施例提供的数据驱动芯片的结构示意图；
图3为本申请实施例提供的时钟产生模块的具体连接示意图；
图4为本申请实施例提供的频率确认模块的具体连接示意图；
图5为本申请实施例提供的频率确认模块的具体连接示意图；
图6为本申请实施例提供的频率确认模块的具体连接示意图；
图7为本申请实施例提供的上升沿起始点示意图；
图8为本申请实施例提供的码型检测模块的结构示意图；
图9为本申请实施例提供的下降沿起始点示意图；
图10为本申请实施例提供的码型检测模块的另一结构示意图；
图11为本申请实施例提供的数据驱动芯片的另一结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。本申请的权利要求书以及说明书中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。
本申请实施例提供一种显示装置，其可以解决显示装置中电磁干扰的测试表现波动很大，造成电磁干扰表现不稳定的技术问题。需要说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图1，图1为本申请实施例提供的显示装置的结构示意图。如图1所示，本申请实施例提供的显示装置10包括时钟控制芯片100以及数据驱动芯片200。数据驱动芯片200与时钟控制芯片100连接。时钟控制芯片100用于传输显示信号D。数据驱动芯片200用于基于显示信号D调整数据驱动芯片200输出的时钟信号C2的相位。
本申请实施例提供的显示装置10，在数据驱动芯片200内基于显示信号D调整数据驱动芯片200输出的时钟信号C2的相位，新增时钟相位对齐机制，使得不同的数据驱动芯片内部产生的时钟信号相位差一致，每次重新开机不会导致相位差变化，进而提升电磁干扰的测试表现的稳定性。
进一步的，请参阅图2，图2为本申请实施例提供的数据驱动芯片的结构示意图。结合图1、图2所示，在本申请实施例提供的显示装置10中，数据驱动芯片200包括时钟产生模块201、频率确认模块202、码型检测模块203以及输出控制模块204。时钟产生模块201与频率确认模块202连接。时钟产生模块201以及码型检测模块203均与输出控制模块204连接。时钟产生模块201用于生成初始时钟信号C1。频率确认模块202用于接收显示信号D以及初始时钟信号C1，并基于显示信号D以及初始时钟信号C1输出反馈信号B至时钟产生模块201，以控制时钟产生模块201调整初始时钟信号C1的频率，并将调整后的初始时钟信号C1输出至输出控制模块204。码型检测模块203用于接收显示信号D，并基于显示信号D获取相位对齐起始点信息A输出至输出控制模块204。输出控制模块204用于基于调整后的初始时钟信号C1以及相位对齐起始点信息A输出时钟信号 C2。
具体的，请参阅图3，图3为本申请实施例提供的时钟产生模块的具体连接示意图。结合图1、图2、图3所示，在本申请实施例提供的显示装置10中，时钟产生模块201具有第一时钟输出端a1、第二时钟输出端a2以及反馈输入端a3。第一时钟输出端a1与频率确认模块202连接，时钟产生模块201通过第一时钟输出端a输出初始时钟信号C1至频率确认模块202。第二时钟输出端a2与输出控制模块204连接，时钟产生模块201通过第二时钟输出端输a2出调整后的初始时钟信号C1至输出控制模块204。反馈输入端a3与频率确认模块202连接，时钟产生模块201通过反馈输入端a3接收反馈信号B。
具体的，请参阅图4，图4为本申请实施例提供的频率确认模块202的具体连接示意图。结合图1、图2、图4所示，在本申请实施例提供的显示装置10中，频率确认模块202具有第一频率确认输入端b1、第二频率确认输入端b2以及反馈输出端d3b3。第一频率确认输入端b1与时钟产生模块201连接，频率确认模块202通过第一频率确认输入端b1接收初始时钟信号c1。第二频率确认输入端b2与时钟控制芯片100连接，频率确认模块202通过第二频率确认输入端b2接收显示信号D。反馈输出端b3与时钟产生模块201连接，频率确认模块202通过反馈输出端b3输出反馈信号B。
具体的，请参阅图5，图5为本申请实施例提供的频率确认模块202的具体连接示意图。结合图1、图2、图5所示，在本申请实施例提供的显示装置10中，码型检测模块203具有码型确认输入端c1以及码型确认输出端c2。码型确认输入端c1与时钟控制芯片100连接，码型检测模块203通过码型确认输入端c1接收显示信号D。码型确认输出端c2与输出控制模块204连接，码型检测模块203通过码型确认输出端c2输出相位对齐起始点信息A。
具体的，请参阅图6，图6为本申请实施例提供的频率确认模块202的具体连接示意图。结合图1、图2、图6所示，在本申请实施例提供的显示装置10中，输出控制模块204具有第一输入端d1、第二输入端d2以及输出端d3。第一输入端d1与时钟产生模块201连接，输出控制模块204通过第一输入端d1接收调整后的初始时钟信号c1。第二输入端d2与码型检测模块203连接，输出控制模块204通过第二输入端d2接收相位对齐起始点信息A。输出控制模块204通过输出端d3输出时钟信号C2。
在一种实施方式中，相位对齐起始点信息A包括上升沿起始点。当输出控制模块204接收到上升沿起始点时，输出控制模块204对调整后的初始时钟信号c1进行复位，以获得时钟信号C2。
比如，请参阅图7、图8，图7为本申请实施例提供的上升沿起始点示意图。图8为本申请实施例提供的码型检测模块203的结构示意图。结合图7、图8，若显示信号D为“10000111110000111”序列，则可以通过检测显示信号D的序列输出相位对齐起始点信息A。具体的，码型检测模块203包括一反相器2031以及一与门2031，其中，反相器2031的一端接收显示信号D的当前位置符号，反相器2031的另一端与与门2031的一输入端连接，与门2031的另一输入端接收显示信号D的下一位置符号。当显示信号D的当前位置符号为“0”，显示信号D的下一位置符号为“1”时，则码型检测模块203输出相位对齐起始点信息A至输出控制模块204，输出控制模块204对调整后的初始时钟信号c1进行复位，以获得时钟信号C2。
在另一种实施方式中，相位对齐起始点信息A包括下降沿起始点。当输出控制模块204接收到下降沿起始点时，输出控制模块204对调整后的初始时钟信号c1进行复位，以获得时钟信号c2。
比如，请参阅图9、图10，图9为本申请实施例提供的下降沿起始点示意图。图10为本申请实施例提供的码型检测模块203的另一结构示意图。结合图9、图10，若显示信号D为“10000111110000111”序列，则可以通过检测显示信号D的序列输出相位对齐起始点信息A。具体的，码型检测模块203包括一反相器2031以及一与门2032，其中，与门2032的一输入端接收显示信号D的当前位置符号，反相器2031的一端接收显示信号D的下一位置符号，反相器2031的另一端与与门2032的一输入端连接。当显示信号D的当前位置符号为“1”，显示信号D的下一位置符号为“0”时，则码型检测模块203输出相位对齐起始点信息A至输出控制模块204，输出控制模块204对调整后的初始时钟信号c1进行复位，以获得时钟信号C2。
需要说明的是，P2P点对点传输协议采用时钟内嵌技术，显示信号D中包含的时钟信息需要数据驱动芯片200来恢复，具体过程为，CD数据驱动芯片200接收到显示信号D，频率确认模块202通过对比Data IN显示信号D与时钟产生模块201生成的初始时钟信号c1的频率，作为反馈输入，控制时钟产生模块201的输出时钟频率，动态循环保证输入的显示信号D的频率与内部的时钟频率相同，再通过采样得到的时钟信号正确的识别数字信号信息，传送到下一级电路，实现整个数据驱动芯片200正常驱动显示。
请参阅图11，图11为本申请实施例提供的数据驱动芯片的另一结构示意图。图11所示的数据驱动芯片300与图2所示的数据驱动芯片200的区别在于，图11所示的数据驱动芯片300还包括滤波模块205。滤波模块205与时钟产生模块201以及频率确认模块202连接。滤波模块205用于对反馈信号B进行滤波处理。滤波模块205是容许低于截止频率的信号通过,但高于截止频率的信号不能通过的电子滤波装置，滤除非有效频率的信号。
其中，滤波模块205具有滤波输入端e1以及滤波输出端e2。滤波输入端e1与频率确认模块202连接，滤波模块205通过滤波输入端e1接收反馈信号B。滤波输出端e2与输出控制模块204连接，滤波模块205通过滤波输出端e2输出滤波后的反馈信号b。
本申请提供的显示装置，在数据驱动芯片内基于显示信号调整数据驱动芯片输出的时钟信号的相位，新增时钟相位对齐机制，使得不同的数据驱动芯片内部产生的时钟信号相位差一致，每次重新开机不会导致相位差变化，进而提升电磁干扰的测试表现的稳定性。
以上对本申请实施例所提供的显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种显示装置，其包括：
    时钟控制芯片，所述时钟控制芯片用于传输显示信号；以及
    数据驱动芯片，所述数据驱动芯片与所述时钟控制芯片连接，所述数据驱动芯片用于基于所述显示信号调整所述数据驱动芯片输出的时钟信号的相位。
  2. 根据权利要求1所述的显示装置，其中，所述数据驱动芯片包括时钟产生模块、频率确认模块、码型检测模块以及输出控制模块，所述时钟产生模块与所述频率确认模块连接，所述时钟产生模块以及所述码型检测模块均与所述输出控制模块连接；其中，
    所述时钟产生模块用于生成初始时钟信号；
    所述频率确认模块用于接收所述显示信号以及所述初始时钟信号，并基于所述显示信号以及所述初始时钟信号输出反馈信号至所述时钟产生模块，以控制所述时钟产生模块调整所述初始时钟信号的频率，并将调整后的所述初始时钟信号输出至所述输出控制模块；
    所述码型检测模块用于接收所述显示信号，并基于所述显示信号获取相位对齐起始点信息输出至所述输出控制模块；
    所述输出控制模块用于基于调整后的所述初始时钟信号以及所述相位对齐起始点信息输出所述时钟信号。
  3. 根据权利要求2所述的显示装置，其中，所述时钟产生模块具有第一时钟输出端、第二时钟输出端以及反馈输入端；
    所述第一时钟输出端与所述频率确认模块连接，所述时钟产生模块通过所述第一时钟输出端输出所述初始时钟信号至所述频率确认模块；
    所述第二时钟输出端与所述输出控制模块连接，所述时钟产生模块通过所述第二时钟输出端输出调整后的所述初始时钟信号至所述输出控制模块；
    所述反馈输入端与所述频率确认模块连接，所述时钟产生模块通过所述反馈输入端接收所述反馈信号。
  4. 根据权利要求2所述的显示装置，其中，所述频率确认模块具有第一频率确认输入端、第二频率确认输入端以及反馈输出端；
    所述第一频率确认输入端与所述时钟产生模块连接，所述频率确认模块通过所述第一频率确认输入端接收所述初始时钟信号；
    所述第二频率确认输入端与所述时钟控制芯片连接，所述频率确认模块通过所述第二频率确认输入端接收所述显示信号；
    所述反馈输出端与所述时钟产生模块连接，所述频率确认模块通过所述反馈输出端输出所述反馈信号。
  5. 根据权利要求2所述的显示装置，其中，所述码型检测模块具有码型确认输入端以及码型确认输出端；
    所述码型确认输入端与所述时钟控制芯片连接，所述码型检测模块通过所述码型确认输入端接收所述显示信号；
    所述码型确认输出端与所述输出控制模块连接，所述码型检测模块通过所述码型确认输出端输出所述相位对齐起始点信息。
  6. 根据权利要求2所述的显示装置，其中，所述输出控制模块具有第一输入端、第二输入端以及输出端；
    所述第一输入端与所述时钟产生模块连接，所述输出控制模块通过所述第一输入端接收调整后的所述初始时钟信号；
    所述第二输入端与所述码型检测模块连接，所述输出控制模块通过所述第二输入端接收所述相位对齐起始点信息；
    所述输出控制模块通过所述输出端输出所述时钟信号。
  7. 根据权利要求1所述的显示装置，其中，所述相位对齐起始点信息包括上升沿起始点或下降沿起始点。
  8. 根据权利要求7所述的显示装置，其中，当所述输出控制模块接收到所述上升沿起始点或者所述下降沿起始点时，所述输出控制模块对调整后的所述初始时钟信号进行复位，以获得所述时钟信号。
  9. 根据权利要求2所述的显示装置，其中，所述驱动芯片还包括滤波模块，所述滤波模块与所述时钟产生模块以及所述频率确认模块连接，所述滤波模块用于对所述反馈信号进行滤波处理。
  10. 根据权利要求9所述的显示装置，其中，所述滤波模块具有滤波输入端以及滤波输出端；
    所述滤波输入端与所述频率确认模块连接，所述滤波模块通过所述滤波输入端接收所述反馈信号；
    所述滤波输出端与所述输出控制模块连接，所述滤波模块通过所述滤波输出端输出滤波后的所述反馈信号。
  11. 一种显示装置，其包括：
    时钟控制芯片，所述时钟控制芯片用于传输显示信号；以及
    数据驱动芯片，所述数据驱动芯片与所述时钟控制芯片连接，所述数据驱动芯片用于基于所述显示信号调整所述数据驱动芯片输出的时钟信号的相位；
    所述数据驱动芯片包括时钟产生模块、频率确认模块、码型检测模块以及输出控制模块，所述时钟产生模块与所述频率确认模块连接，所述时钟产生模块以及所述码型检测模块均与所述输出控制模块连接；其中，
    所述时钟产生模块用于生成初始时钟信号；
    所述频率确认模块用于接收所述显示信号以及所述初始时钟信号，并基于所述显示信号以及所述初始时钟信号输出反馈信号至所述时钟产生模块，以控制所述时钟产生模块调整所述初始时钟信号的频率，并将调整后的所述初始时钟信号输出至所述输出控制模块；
    所述码型检测模块用于接收所述显示信号，并基于所述显示信号获取相位对齐起始点信息输出至所述输出控制模块；
    所述输出控制模块用于基于调整后的所述初始时钟信号以及所述相位对齐起始点信息输出所述时钟信号；
    所述相位对齐起始点信息包括上升沿起始点或下降沿起始点。
  12. 根据权利要求11所述的显示装置，其中，所述时钟产生模块具有第一时钟输出端、第二时钟输出端以及反馈输入端；
    所述第一时钟输出端与所述频率确认模块连接，所述时钟产生模块通过所述第一时钟输出端输出所述初始时钟信号至所述频率确认模块；
    所述第二时钟输出端与所述输出控制模块连接，所述时钟产生模块通过所述第二时钟输出端输出调整后的所述初始时钟信号至所述输出控制模块；
    所述反馈输入端与所述频率确认模块连接，所述时钟产生模块通过所述反馈输入端接收所述反馈信号。
  13. 根据权利要求11所述的显示装置，其中，所述频率确认模块具有第一频率确认输入端、第二频率确认输入端以及反馈输出端；
    所述第一频率确认输入端与所述时钟产生模块连接，所述频率确认模块通过所述第一频率确认输入端接收所述初始时钟信号；
    所述第二频率确认输入端与所述时钟控制芯片连接，所述频率确认模块通过所述第二频率确认输入端接收所述显示信号；
    所述反馈输出端与所述时钟产生模块连接，所述频率确认模块通过所述反馈输出端输出所述反馈信号。
  14. 根据权利要求11所述的显示装置，其中，所述码型检测模块具有码型确认输入端以及码型确认输出端；
    所述码型确认输入端与所述时钟控制芯片连接，所述码型检测模块通过所述码型确认输入端接收所述显示信号；
    所述码型确认输出端与所述输出控制模块连接，所述码型检测模块通过所述码型确认输出端输出所述相位对齐起始点信息。
  15. 根据权利要求11所述的显示装置，其中，所述输出控制模块具有第一输入端、第二输入端以及输出端；
    所述第一输入端与所述时钟产生模块连接，所述输出控制模块通过所述第一输入端接收调整后的所述初始时钟信号；
    所述第二输入端与所述码型检测模块连接，所述输出控制模块通过所述第二输入端接收所述相位对齐起始点信息；
    所述输出控制模块通过所述输出端输出所述时钟信号。
  16. 根据权利要求11所述的显示装置，其中，当所述输出控制模块接收到所述上升沿起始点或者所述下降沿起始点时，所述输出控制模块对调整后的所述初始时钟信号进行复位，以获得所述时钟信号。
  17. 根据权利要求11所述的显示装置，其中，所述驱动芯片还包括滤波模块，所述滤波模块与所述时钟产生模块以及所述频率确认模块连接，所述滤波模块用于对所述反馈信号进行滤波处理。
  18. 根据权利要求17所述的显示装置，其中，所述滤波模块具有滤波输入端以及滤波输出端；
    所述滤波输入端与所述频率确认模块连接，所述滤波模块通过所述滤波输入端接收所述反馈信号；
    所述滤波输出端与所述输出控制模块连接，所述滤波模块通过所述滤波输出端输出滤波后的所述反馈信号。
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