WO2023029061A1 - Circuit d'acquisition de pixels et capteur d'image - Google Patents

Circuit d'acquisition de pixels et capteur d'image Download PDF

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Publication number
WO2023029061A1
WO2023029061A1 PCT/CN2021/116832 CN2021116832W WO2023029061A1 WO 2023029061 A1 WO2023029061 A1 WO 2023029061A1 CN 2021116832 W CN2021116832 W CN 2021116832W WO 2023029061 A1 WO2023029061 A1 WO 2023029061A1
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Prior art keywords
row
pixel acquisition
module
acquisition circuit
subunit
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PCT/CN2021/116832
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English (en)
Chinese (zh)
Inventor
陈守顺
郭梦晗
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豪威芯仑传感器(上海)有限公司
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Publication of WO2023029061A1 publication Critical patent/WO2023029061A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array

Definitions

  • the present disclosure relates to the technical field of image sensors, in particular to a novel image sensor.
  • dynamic vision image sensors Compared with traditional image sensors (such as active pixel sensors), dynamic vision image sensors (hereinafter referred to as dynamic vision sensors) have gradually attracted people's attention due to their unique advantages.
  • the dynamic vision sensor can continuously respond to the light intensity changes in the field of view in real time without any exposure time, which makes it easier to detect high-speed motion object.
  • the dynamic vision sensor only responds to and outputs the position information of the pixel unit corresponding to the area where the light intensity changes in the field of view, and automatically shields useless background information, it also has the advantages of small output data and low occupied bandwidth.
  • the above characteristics of the dynamic vision sensor enable the back-end image processing system to directly acquire and process useful dynamic information in the field of view, thereby greatly reducing the requirements for its storage and computing power, and achieving better real-time performance.
  • the non-response time can ensure that it is reliably and stably reset after detecting an event, and can limit the maximum amount of events it can output per unit time.
  • a weak current source is used to charge the capacitor to generate a ramp signal to control the non-response time.
  • the present disclosure provides a new pixel acquisition circuit and image sensor in an attempt to solve or at least alleviate at least one of the above problems.
  • a pixel acquisition circuit including: a photodetection module, adapted to monitor the light signal irradiated thereon in real time, and output an electrical signal; a trigger generation module, coupled to the photodetection module, adapted to Generate a trigger signal when the electrical signal satisfies a predetermined trigger condition; and a state latch module, coupled to the trigger generation module, adapted to enter the trigger state and cache this trigger event when receiving the trigger signal; row reset strobe module, respectively coupled to the trigger generation module and the state latch module, adapted to generate a reset signal to the trigger generation module based at least on the output of the state latch module; and a readout module, coupled to the state latch module, adapted to output This trigger event.
  • the row reset gating module is coupled to the row reset signal line, and is also adapted to receive the row reset signal through the row reset signal line, and when the row reset signal is valid and the state is latched When the output of the module is high, a reset signal is generated.
  • the state latch module is coupled to the row event clearing signal line, and is further adapted to receive the row event clearing signal through the row event clearing signal line, and when the row event clearing signal is valid , is reset.
  • the row reset strobe signal is also adapted to receive a row reset signal when the row where the pixel acquisition circuit is located is selected; the state latch module is also adapted to receive a row reset signal when the row reset signal ends Before, a line event clear signal was received.
  • the trigger generating module includes: a preprocessing subunit, the input end of which is coupled to the output end of the photodetection module, and is suitable for preprocessing the electrical signal, and generates a preprocessed
  • the threshold comparison subunit whose input terminal is coupled to the output terminal of the preprocessing subunit, is adapted to receive the preprocessed electrical signal, and generate a trigger signal when the preprocessed electrical signal meets a predetermined condition.
  • the row reset gating module is further adapted to be coupled to the preprocessing subunit, and output the generated reset signal to the preprocessing subunit.
  • the row reset gating module includes: a first operation subunit, the first input terminal of which is connected to the row reset signal line, and the second input terminal of which is connected to the output of the state latch module terminal, the output terminal of which is coupled to the preprocessing subunit, and the row reset gating module is adapted to output a valid reset signal to the preprocessing subunit when the pixel acquisition circuit enters a trigger state and the row reset signal is valid.
  • the row reset gating module includes: a first switch whose first end is connected to the row reset signal line, whose second end is connected to the preprocessing subunit, and whose control end connected to the output terminal of the state latch module; the second switch, its first terminal connected to the ground, its second terminal connected to the preprocessing subunit, its control terminal connected to the second operation subunit; the second operation subunit, its first terminal connected to The output terminal of the state latch module, its second terminal is connected to the control terminal of the second switch, and the row reset gating module is also suitable for disconnecting the second switch and closing the first switch when the pixel acquisition circuit enters the trigger state, and outputting the row reset signal, and when the row reset signal is valid, output a valid reset signal to the preprocessing subunit.
  • an image sensor including: a pixel acquisition circuit array, including a plurality of pixel acquisition circuits as described above; a global control unit, coupled to the pixel acquisition circuit array through a global reset signal line, It is suitable for resetting the pixel acquisition circuit array when the image sensor is powered on; the readout unit communicates with the pixel acquisition circuit array via a row selection line, a row request line, a row event clearing signal line, a row reset signal line and a column state signal line. Coupled, adapted to read out event information of events generated by the array of pixel acquisition circuits.
  • the pixel acquisition circuits are spatially arranged two-dimensionally.
  • the readout unit includes: a row selection subunit, coupled to each row of pixel acquisition circuits via a row selection line, a row request line, a row event clearing signal line, and a row reset signal line, It is suitable for managing the pixel acquisition circuit array in the row direction;
  • the column selection subunit is coupled with the pixel acquisition circuit of each column through the column state signal line, and is suitable for managing the pixel acquisition circuit array in the column direction;
  • the readout control subunit is respectively coupled Connected to the row selection subunit and the column selection subunit, suitable for controlling the row selection subunit and the column selection subunit.
  • the row selection subunit includes: a non-response time circuit module, which is coupled to the row reset gating module in the pixel acquisition circuit via the row reset signal line, and is suitable for selecting a certain row of pixels When the acquisition circuit is selected, a row reset signal is generated to the row reset gating module to control the non-response time of the pixel acquisition circuit through the effective time of the row reset signal.
  • the non-response time circuit module is coupled to the state latch module in the pixel acquisition circuit via the row event clearing signal line, and is also suitable for generating a row event before the end of the row reset signal
  • the clear signal is given to the status latch module to clear the events buffered in the status latch module.
  • a row reset gating unit is added to generate a reset signal triggering the preprocessing subunit in the generation module. Further, when the row reset signal is valid and the output of the state latch module is high level (that is, the pixel acquisition circuit is in the triggered state), the row reset gating module generates a reset signal. In this way, through the row reset gating unit, the reset of the pixel acquisition circuit in the triggered state in a row of pixel acquisition circuits is realized, and by controlling the effective duration of the row reset signal, the control of its non-response time can be realized.
  • the reset signal of the state latch module is the row event clear signal output by the row selection subunit, and the row event clear signal is valid for a short period of time at the end of the row reset signal, and it resets the state latch module.
  • FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present disclosure
  • FIG. 2 shows a schematic diagram of a pixel acquisition circuit 200 according to some embodiments of the present disclosure
  • FIG. 3 shows a timing diagram of control signals of a pixel acquisition circuit in the row direction according to some embodiments of the present disclosure
  • FIGS. 4A and 4B respectively show schematic diagrams of the row reset gating module 240 according to some embodiments of the present disclosure.
  • FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present disclosure.
  • the image sensor 100 includes a pixel acquisition circuit array 110 , a global control unit 120 and a readout unit 130 .
  • the pixel acquisition circuit array 110 is coupled to the global control unit 120 and the readout unit 130 respectively.
  • the global control unit 120 is coupled to the pixel acquisition circuit array 110 via a global reset signal line.
  • the readout unit 130 is coupled to the pixel acquisition circuit array 110 via a row selection line, a row request line, a row event clear signal line, a row reset signal line and a column state signal line.
  • the pixel acquisition circuit array 110 is composed of the same plurality of pixel acquisition circuits 200 (that is, pixel units) arranged two-dimensionally in space (as shown in FIG. this).
  • the pixel acquisition circuit 200 monitors the light intensity change in the field of view in real time, and enters the trigger state when the light intensity change meets a certain condition, that is, triggers and generates an event to indicate the corresponding position in the field of view at this time There is a motion event.
  • the readout unit 130 is capable of reading out event information of events generated by the pixel acquisition circuit array 110 .
  • the event information includes event location information and triggered time information.
  • the global control unit 120 resets the entire pixel acquisition circuit array 110 when the image sensor 100 is powered on, so as to ensure that each pixel acquisition circuit 200 has a stable initial state.
  • the readout unit 130 further includes a row selection subunit 132 , a column selection subunit 134 and a readout control subunit 136 .
  • the readout control subunit 136 is coupled to the row selection subunit 132 and the column selection subunit 134 respectively.
  • the row selection subunit 132 is coupled to each row of pixel acquisition circuits in the pixel acquisition circuit array 110 via a row selection line, a row request line, a row event clear signal line, and a row reset signal line.
  • the column selection subunit 134 is coupled to each column of pixel acquisition circuits in the pixel acquisition circuit array 110 via a column state signal line. Wherein, the row selection subunit 132 manages the pixel acquisition circuit array in the row direction; the column selection subunit 134 manages the pixel acquisition circuit array in the column direction.
  • the readout control subunit 136 controls the row selection subunit 132 and the column selection subunit 134 .
  • the row selection unit and the column selection unit may be a decision device for random scanning, or a selection scanning circuit for sequential scanning. Since these circuits are some general-purpose circuit modules, the embodiments of the present disclosure do not limit this, nor do they repeat.
  • a non-response time circuit module is added to the row selection subunit 132 .
  • the non-response time circuit module is coupled to each pixel acquisition circuit 200 via a row reset signal line and a row event clear signal line.
  • the readout control subunit 136 first controls the row selection subunit 132 to select a row of pixel acquisition circuits, for example, the row selection subunit 132 receives a row request signal from the pixel acquisition circuit array 110, and then sends a The pixel acquisition circuit sends a row selection signal to indicate that the row of pixel acquisition circuits is selected. Afterwards, the readout control subunit 136 controls the column selection subunit 134 to read the event information of the triggered event in the row of pixel acquisition circuits.
  • the non-response time circuit module When a row of pixel acquisition circuits is selected, the non-response time circuit module generates a row reset signal, and transmits it to all pixel acquisition circuits of the row through the row reset signal line, so as to control the pixel non-response time.
  • the effective time of the row reset signal is the non-response time of the pixel acquisition circuit.
  • the non-response duration of the pixel acquisition circuit is controlled by the length of the effective time of the row reset signal.
  • the non-response time circuit module also generates a row event clear signal, and transmits it to all the pixel acquisition circuits of the row through the row event clear signal line, for clearing the generated pixels in the row of pixel acquisition circuits. event.
  • the non-response time circuit module can be realized by using a traditional ramp generator and a comparator circuit; it can also be realized by using a digital circuit, for example, a sequential logic circuit coordinated by a counter. Since these circuits are some common circuit modules, details will not be repeated here.
  • a non-response time circuit module is added in the row selection subunit 132, and the non-response time circuit module is moved from the inside of the pixel acquisition circuit to the external row selection subunit, and by adding the row reset signal line As well as the row event clearing signal line, the row selection subunit controls the pixel acquisition circuit through the non-response time circuit module, and can precisely control the non-response time of a row of pixel acquisition circuits.
  • the non-response time circuit module originally located inside the pixel acquisition circuit is removed, the complexity of the pixel acquisition circuit is reduced, so its area and power consumption can be reduced accordingly.
  • the non-response time circuit module is implemented in the row selection sub-unit without being limited by the area factor, the mismatch of the non-response time can be greatly reduced and precise control thereof can be realized.
  • the pixel acquisition circuit 200 will be described in detail below.
  • FIG. 2 shows a schematic diagram of a pixel acquisition circuit 200 according to some embodiments of the present disclosure.
  • the pixel acquisition circuit 200 mainly includes: a photodetection module 210 , a trigger generation module 220 , a state latch module 230 , a row reset gating module 240 , and a readout module 250 .
  • the trigger generation module 220 is coupled to the photodetection module 210
  • the state latch module 230 is coupled to the trigger generation module 220
  • the row reset gating module 240 is respectively coupled to the trigger
  • the reading module 250 is coupled to the state latching module 230 .
  • the pixel acquisition circuit 200 is coupled to the global control unit 120 through the global reset signal line, and is connected to the row selector through the row request line, the row selection line, the row reset signal line and the row event clearing signal line.
  • the unit 132 is coupled to the column selection sub-unit 134 through a column status signal line.
  • the photoelectric detection module 210 monitors the light signal irradiated thereon in real time, and outputs an electric signal.
  • the trigger generation module 220 generates a trigger signal when the electrical signal satisfies a predetermined trigger condition (for example, the illuminance change amount and change rate of the light signal pointed to by the electrical signal can exceed respective thresholds).
  • a predetermined trigger condition for example, the illuminance change amount and change rate of the light signal pointed to by the electrical signal can exceed respective thresholds.
  • the state latch module 230 receives the trigger signal, it enters the trigger state and buffers the current trigger event. Afterwards, the readout module 250 outputs the current trigger event.
  • the trigger generation module 220 further includes a preprocessing subunit 222 and a threshold comparison subunit 224 .
  • the input terminal of the preprocessing subunit 222 is coupled to the output terminal of the photodetection module 210
  • the input terminal of the threshold comparison subunit 224 is coupled to the output terminal of the preprocessing subunit 222
  • the output terminal of the threshold comparison subunit 224 is coupled to to the state latch module 230 .
  • the preprocessing subunit 222 preprocesses the electrical signal to generate a preprocessed electrical signal.
  • the preprocessing operation includes at least one of an amplification operation and a filtering operation.
  • the amplification operation is to increase the sensitivity of the pixel acquisition circuit 200 to light intensity detection, but this is not necessary.
  • the filtering operation is generally high-pass filtering, that is, it only responds to high-frequency light intensity changes that are fast enough, thereby filtering out those slow light intensity changes.
  • the preprocessing subunit 222 is implemented as a high-pass filter amplifier, but is not limited thereto.
  • the threshold comparison subunit 224 receives the preprocessed electrical signal, judges whether the preprocessed electrical signal satisfies a predetermined condition (for example, greater than the first threshold, less than the second threshold, not limited thereto), and when the preprocessed electrical signal satisfies A trigger signal is generated when a predetermined condition is met.
  • a predetermined condition for example, greater than the first threshold, less than the second threshold, not limited thereto
  • FIG. 2 exemplarily shows an implementation manner of each part in the pixel acquisition circuit 200 .
  • the photodetection module 210 is, for example, a logarithmic photodetector (comprising a coupled photodiode PD1, a transistor T1 and an amplifier A1), the preprocessing subunit 222 can adopt various known filtering and amplification techniques, and the threshold comparison subunit 224 can pass Voltage comparators (in FIG. 2 , including voltage comparators VC1 and VC2 , and an OR gate), the state latch module 230 may be a latch, but it is not limited thereto. Since the functions of the above parts are not different from those of general dynamic vision sensors, they will not be repeated here.
  • a row reset gating module 240 is added, which at least based on the output of the state latch module 230 generates a reset signal to Trigger generation module 220 . More specifically, the reset signal generated by the row reset gating module 240 is output to the preprocessing subunit 222 .
  • the input terminals of the preprocessing subunit 222 include a "global reset” terminal and a "local reset” terminal.
  • the “global reset” terminal receives a global reset signal from the global control unit 120 , and the global reset signal is only valid when the image sensor 100 is powered on.
  • the reset signal received by the “local reset” terminal is generated by the above-mentioned row reset gating module 240 .
  • one input terminal of the row reset gating module 240 is connected to the state latch module 230 to receive the output of the state latch module 230; the other input terminal is connected to the row reset signal line and received through the row reset signal line.
  • the row reset gating module 240 When the row reset signal is valid and the output of the state latch module 230 is at a high level, the row reset gating module 240 generates a reset signal.
  • the corresponding row reset signal is valid.
  • the output of the state latch module 230 is set to 1 (ie, high level), at this time, the output of the row reset gating module 240 is valid, and the preprocessing subunit 222 is reset.
  • the output of the state latch module 230 maintains 0 (ie, low level), at this time, the output of the row reset gating module 240 is invalid, and the preprocessing subunit 222 is not affected.
  • the reset of the pixel acquisition circuit in the trigger state in a row of pixel acquisition circuits is realized, and by controlling the length of the effective time of the row reset signal, the control of its non-response time can be realized, while for the untriggered The pixel acquisition circuit is not affected.
  • the state latch module 230 is coupled to the row event clear signal line to receive the row event clear signal from the non-response time circuit module via the row event clear signal line. And, when the row event clear signal is active, the state latch module 230 is reset.
  • the row event clear signal when the global reset signal is valid at the initial power-on moment, the row event clear signal is also valid, and at this time, the state latch modules 230 of all pixel acquisition circuits in the entire pixel acquisition circuit array 110 are reset. Subsequently, in the normal operation of the image sensor 100, when a certain row of pixel acquisition circuits is selected by the row selection subunit 132, the row event clear signal is valid for a short period of time at the end of the row reset signal to clear the generated events of the row.
  • the present disclosure does not place too many restrictions on the specific length of a short period of time. Generally speaking, the valid period of the row event clear signal is much shorter than the valid period of the row reset signal.
  • the main body of the pixel acquisition circuit of the present disclosure is consistent with it, but the differences are mainly reflected in the following two points.
  • a row reset gating unit is added to generate a reset signal that triggers the preprocessing subunit in the generation module.
  • a local reset signal of a high pass filter amplifier is generated.
  • the reset signal of the state latch module is the row event clearing signal (through the row event clearing signal line) output by the row selection subunit, which resets the latches of all pixel acquisition circuits in the row.
  • FIG. 3 shows a timing diagram of control signals of the pixel acquisition circuit in the row direction according to some embodiments of the present disclosure.
  • the working timing of the pixel acquisition circuit 200 and the image sensor 100 will be further described below with reference to FIGS. 1-3 . It should be understood that the contents in Figs. 1-3 are complementary to each other, and repeated descriptions will not be repeated.
  • Figure 3 shows row request signal, row selection signal, row reset signal and row event clear signal respectively, and all signals are set to be high level active (of course, the present disclosure is not limited to this, space is limited, this will not be listed here).
  • the state latch module 230 in the pixel acquisition circuit 200 is set, and the readout module 250 pulls up the row request signal (as shown in a in FIG. 3 ).
  • the row selection signal and the row reset signal are valid at the same time (as shown in b in FIG. 3 ).
  • the row selection signal is valid, and the state information of the state latch module 230 of the row pixel acquisition circuit 200 is sent to the column state signal line (obtained by the column selection subunit 134) through the readout module 250, and then the row selection signal is invalid ( As shown in c in Figure 3).
  • the row reset signal is set to be effective when the row is selected, and for the pixel acquisition circuit 200 triggered in the pixel acquisition circuit 200 of this row, the output of the row reset gating module 240 is valid, and the preprocessing subunit 222 in the pixel acquisition circuit 200 is reset, the pixel acquisition circuit 200 enters a non-response time. For the untriggered pixel acquisition circuits 200 in the row of pixel acquisition circuits 200 , the output of the row reset gating module 240 remains invalid, and the working state of the pixel acquisition circuits 200 is not affected.
  • the row reset signal becomes invalid.
  • the output of its row reset gating module 240 is invalid, and the reset state of the preprocessing subunit 222 is released.
  • the pixel acquisition circuit 200 exits the non-response time, and restarts to detect changes in the external light intensity.
  • the row event clear signal is valid, the state latch module 230 in the pixel acquisition circuit 200 of this row is reset, and the event information stored before is all cleared .
  • the length of time the row reset signal is active ie, from b to e in FIG. 3
  • the time length of the row event clear signal ie, from d to e in FIG. 3
  • the valid time period of the row event clear signal is included in the valid time period of the row reset signal, and the valid row event clear signal is usually located at the end of the valid row reset signal.
  • the row reset signal and the row event clear signal become invalid at the same moment (e in FIG. 3 ).
  • FIG. 4A and FIG. 4B respectively show schematic diagrams of the row reset gating module 240 according to some embodiments of the present disclosure. It should be understood that FIG. 4A and FIG. 4B are supplements to the aforementioned content about FIG. 1-FIG. 3 , and repeated descriptions will not be repeated.
  • FIG. 4A and FIG. 4B are only examples, and do not limit the implementation of the row reset gating module 240. Based on the embodiments and descriptions of the present disclosure, those skilled in the art can easily think of other ways to realize the row reset gating modules are all within the protection scope of the present disclosure.
  • the row reset gating module 240 includes a first operation subunit, the first input terminal of the first operation subunit is connected to the row reset signal line, the second input terminal is connected to the output terminal of the state latch module 230, and the first The output terminal of the operation subunit is coupled to an input terminal of the preprocessing subunit 222 (such as the “local reset” terminal in FIG. 2 ).
  • the row reset gating module 240 outputs a valid reset signal to the preprocessing subunit 222 when the pixel acquisition circuit 200 enters the trigger state and the row reset signal is valid.
  • the first operation subunit is implemented as a simple AND gate, only when the output signal of the state latch module 230 is high level (for example, when the output signal is 1, it means that the pixel acquisition circuit is in trigger state) and the row reset signal is valid, the output of the row reset gating module 240 is valid (for example, the output is 1, that is, the reset signal received by the preprocessing subunit 222 is 1).
  • the default signal is valid when the signal is high (ie, the signal is 1).
  • the reset signal of the preprocessing subunit 222 is low valid, then the AND gate can be further simplified into a NAND gate circuit.
  • the use of dynamic logic can also simplify its implementation, which will not be listed in this disclosure.
  • the row reset gating module 240 at least includes: a first switch S1 and a second switch S2. Wherein, the first terminal of the first switch S1 is connected to the row reset signal line, and the second terminal is connected to an input terminal of the preprocessing subunit 222 (such as the "local reset" terminal in Figure 2). In addition, the control of the first switch S1 The terminal is connected to the output terminal of the state latch module 230 . The first terminal of the second switch S2 is connected to the ground, and the second terminal of the second switch is also connected to the input terminal of the preprocessing subunit as the first switch S1. In some embodiments, the row reset gating module 240 further includes a second operation subunit, and the control terminal of the second switch S2 is connected to the output terminal of the state latch module 230 through the second operation subunit.
  • the second operation subunit is implemented as a NOT gate, that is, the control signal of the second switch S2 is the inverted output of the state latch module 230 .
  • the output of the state latch module 230 is 0, the first switch S1 is open, the second switch S2 is closed, and the row reset signal is invalid, that is, the preprocessing subunit 222 has not received a valid reset Signal.
  • the output of the state latch module 230 is 1, the second switch S2 is disconnected, the first switch S1 is closed, and the output of the row reset gating module 240 is a row reset signal.
  • the row reset signal is valid
  • the reset signal of the preprocessing subunit 222 is valid.
  • the circuit structure of the row reset gating module 240 is very simple, and can be realized by simple AND gate logic or switches without increasing the complexity of the pixel acquisition circuit. Furthermore, compared with general pixel acquisition circuits, the area and power consumption of the pixel acquisition circuit 200 of the present disclosure will be correspondingly reduced.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components are in physical contact or have an electrical signal path, for example, two components are electrically connected through a signal line, or two components There are other electrical components or circuits between them, but there is a signal path between the two components through other electrical components.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • modules or units or components of the devices in the examples disclosed herein may be arranged in the device as described in this embodiment, or alternatively may be located in a different location than the device in this example. in one or more devices.
  • the modules in the preceding examples may be combined into one module or furthermore may be divided into a plurality of sub-modules.
  • modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment.
  • Modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of sub-modules or sub-units or sub-assemblies.
  • All features disclosed in this specification including accompanying claims, abstract and drawings) and any method or method so disclosed may be used in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of equipment are combined.
  • Each feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
  • a processor with the necessary instructions for carrying out the described method or element of a method forms a means for carrying out the method or element of a method.
  • an element described herein of an apparatus embodiment is an example of a means for carrying out the function performed by the element for the purpose of carrying out the disclosure.

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Abstract

La présente demande concerne un circuit d'acquisition de pixels et un capteur d'image. Le capteur d'image comprend : un réseau de circuits d'acquisition de pixels, comprenant une pluralité de circuits d'acquisition de pixels ; une unité de commande globale, couplée au réseau de circuits d'acquisition de pixels au moyen d'une ligne de signal de réinitialisation globale et configurée pour réinitialiser le réseau de circuits d'acquisition de pixels lorsque le capteur d'image est mis sous tension ; et une unité de lecture, couplée au réseau de circuits d'acquisition de pixels au moyen d'une ligne de sélection de rangée, d'une ligne de demande de rangée, d'une ligne de signal de suppression d'événement de rangée, d'une ligne de signal de réinitialisation de rangée et d'une ligne de signal d'état de colonne et configurée pour lire des informations d'événement d'un événement généré par le réseau de circuits d'acquisition de pixels.
PCT/CN2021/116832 2021-09-01 2021-09-07 Circuit d'acquisition de pixels et capteur d'image WO2023029061A1 (fr)

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CN202111021537.2A CN113747090B (zh) 2021-09-01 2021-09-01 一种像素采集电路及图像传感器

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