WO2023029061A1

WO2023029061A1 - Pixel acquisition circuit and image sensor

Info

Publication number: WO2023029061A1
Application number: PCT/CN2021/116832
Authority: WO
Inventors: 陈守顺; 郭梦晗
Original assignee: 豪威芯仑传感器(上海)有限公司
Priority date: 2021-09-01
Filing date: 2021-09-07
Publication date: 2023-03-09
Also published as: CN113747090A; CN113747090B

Abstract

The present application discloses a pixel acquisition circuit and an image sensor. The image sensor comprises: a pixel acquisition circuit array, comprising a plurality of pixel acquisition circuits; a global control unit, coupled to the pixel acquisition circuit array by means of a global reset signal line and configured to reset the pixel acquisition circuit array when the image sensor is powered on; and a readout unit, coupled to the pixel acquisition circuit array by means of a row selection line, a row request line, a row event clearing signal line, a row reset signal line, and a column state signal line and configured to read out event information of an event generated by the pixel acquisition circuit array.

Description

A pixel acquisition circuit and image sensor

technical field

The present disclosure relates to the technical field of image sensors, in particular to a novel image sensor.

Background technique

Among the many application fields of image sensors, the detection of moving objects is one of the important aspects. In this application field, compared with traditional image sensors (such as active pixel sensors), dynamic vision image sensors (hereinafter referred to as dynamic vision sensors) have gradually attracted people's attention due to their unique advantages.

Based on the pixel unit (or pixel acquisition circuit) designed based on the bionic principle, the dynamic vision sensor can continuously respond to the light intensity changes in the field of view in real time without any exposure time, which makes it easier to detect high-speed motion object. In addition, because the dynamic vision sensor only responds to and outputs the position information of the pixel unit corresponding to the area where the light intensity changes in the field of view, and automatically shields useless background information, it also has the advantages of small output data and low occupied bandwidth. The above characteristics of the dynamic vision sensor enable the back-end image processing system to directly acquire and process useful dynamic information in the field of view, thereby greatly reducing the requirements for its storage and computing power, and achieving better real-time performance.

Generally, after a pixel unit of a dynamic vision sensor detects an event, it needs to be forced into a reset state for a period of time, which is called the non-response time. During this period of time, the pixel unit maintains a reset state and does not respond to external light intensity changes. For the pixel unit, the non-response time can ensure that it is reliably and stably reset after detecting an event, and can limit the maximum amount of events it can output per unit time. In the specific implementation, there is usually a special module inside the pixel unit to complete this function. Generally, a weak current source is used to charge the capacitor to generate a ramp signal to control the non-response time. However, this specialized module will increase the overhead of the pixel unit in terms of area and power consumption. Moreover, due to the deviation of the integrated circuit manufacturing process, there is also a certain mismatch in the non-response time of different pixel units, which is very critical for some applications of dynamic vision sensors (such as high-speed video reconstruction) .

In view of this, there is an urgent need for a new image sensor to solve the above problems.

Contents of the invention

The present disclosure provides a new pixel acquisition circuit and image sensor in an attempt to solve or at least alleviate at least one of the above problems.

According to one aspect of the present disclosure, a pixel acquisition circuit is provided, including: a photodetection module, adapted to monitor the light signal irradiated thereon in real time, and output an electrical signal; a trigger generation module, coupled to the photodetection module, adapted to Generate a trigger signal when the electrical signal satisfies a predetermined trigger condition; and a state latch module, coupled to the trigger generation module, adapted to enter the trigger state and cache this trigger event when receiving the trigger signal; row reset strobe module, respectively coupled to the trigger generation module and the state latch module, adapted to generate a reset signal to the trigger generation module based at least on the output of the state latch module; and a readout module, coupled to the state latch module, adapted to output This trigger event.

Optionally, in the pixel acquisition circuit according to the present disclosure, the row reset gating module is coupled to the row reset signal line, and is also adapted to receive the row reset signal through the row reset signal line, and when the row reset signal is valid and the state is latched When the output of the module is high, a reset signal is generated.

Optionally, in the pixel acquisition circuit according to the present disclosure, the state latch module is coupled to the row event clearing signal line, and is further adapted to receive the row event clearing signal through the row event clearing signal line, and when the row event clearing signal is valid , is reset.

Optionally, in the pixel acquisition circuit according to the present disclosure, the row reset strobe signal is also adapted to receive a row reset signal when the row where the pixel acquisition circuit is located is selected; the state latch module is also adapted to receive a row reset signal when the row reset signal ends Before, a line event clear signal was received.

Optionally, in the pixel acquisition circuit according to the present disclosure, the trigger generating module includes: a preprocessing subunit, the input end of which is coupled to the output end of the photodetection module, and is suitable for preprocessing the electrical signal, and generates a preprocessed The threshold comparison subunit, whose input terminal is coupled to the output terminal of the preprocessing subunit, is adapted to receive the preprocessed electrical signal, and generate a trigger signal when the preprocessed electrical signal meets a predetermined condition.

Optionally, in the pixel acquisition circuit according to the present disclosure, the row reset gating module is further adapted to be coupled to the preprocessing subunit, and output the generated reset signal to the preprocessing subunit.

Optionally, in the pixel acquisition circuit according to the present disclosure, the row reset gating module includes: a first operation subunit, the first input terminal of which is connected to the row reset signal line, and the second input terminal of which is connected to the output of the state latch module terminal, the output terminal of which is coupled to the preprocessing subunit, and the row reset gating module is adapted to output a valid reset signal to the preprocessing subunit when the pixel acquisition circuit enters a trigger state and the row reset signal is valid.

Optionally, in the pixel acquisition circuit according to the present disclosure, the row reset gating module includes: a first switch whose first end is connected to the row reset signal line, whose second end is connected to the preprocessing subunit, and whose control end connected to the output terminal of the state latch module; the second switch, its first terminal connected to the ground, its second terminal connected to the preprocessing subunit, its control terminal connected to the second operation subunit; the second operation subunit, its first terminal connected to The output terminal of the state latch module, its second terminal is connected to the control terminal of the second switch, and the row reset gating module is also suitable for disconnecting the second switch and closing the first switch when the pixel acquisition circuit enters the trigger state, and outputting the row reset signal, and when the row reset signal is valid, output a valid reset signal to the preprocessing subunit.

According to another aspect of the present disclosure, an image sensor is provided, including: a pixel acquisition circuit array, including a plurality of pixel acquisition circuits as described above; a global control unit, coupled to the pixel acquisition circuit array through a global reset signal line, It is suitable for resetting the pixel acquisition circuit array when the image sensor is powered on; the readout unit communicates with the pixel acquisition circuit array via a row selection line, a row request line, a row event clearing signal line, a row reset signal line and a column state signal line. Coupled, adapted to read out event information of events generated by the array of pixel acquisition circuits.

Optionally, in the image sensor according to the present disclosure, the pixel acquisition circuits are spatially arranged two-dimensionally.

Optionally, in the image sensor according to the present disclosure, the readout unit includes: a row selection subunit, coupled to each row of pixel acquisition circuits via a row selection line, a row request line, a row event clearing signal line, and a row reset signal line, It is suitable for managing the pixel acquisition circuit array in the row direction; the column selection subunit is coupled with the pixel acquisition circuit of each column through the column state signal line, and is suitable for managing the pixel acquisition circuit array in the column direction; the readout control subunit is respectively coupled Connected to the row selection subunit and the column selection subunit, suitable for controlling the row selection subunit and the column selection subunit.

Optionally, in the image sensor according to the present disclosure, the row selection subunit includes: a non-response time circuit module, which is coupled to the row reset gating module in the pixel acquisition circuit via the row reset signal line, and is suitable for selecting a certain row of pixels When the acquisition circuit is selected, a row reset signal is generated to the row reset gating module to control the non-response time of the pixel acquisition circuit through the effective time of the row reset signal.

Optionally, in the image sensor according to the present disclosure, the non-response time circuit module is coupled to the state latch module in the pixel acquisition circuit via the row event clearing signal line, and is also suitable for generating a row event before the end of the row reset signal The clear signal is given to the status latch module to clear the events buffered in the status latch module.

According to the pixel acquisition circuit of the present disclosure, a row reset gating unit is added to generate a reset signal triggering the preprocessing subunit in the generation module. Further, when the row reset signal is valid and the output of the state latch module is high level (that is, the pixel acquisition circuit is in the triggered state), the row reset gating module generates a reset signal. In this way, through the row reset gating unit, the reset of the pixel acquisition circuit in the triggered state in a row of pixel acquisition circuits is realized, and by controlling the effective duration of the row reset signal, the control of its non-response time can be realized.

In addition, the reset signal of the state latch module is the row event clear signal output by the row selection subunit, and the row event clear signal is valid for a short period of time at the end of the row reset signal, and it resets the state latch module.

Description of drawings

To the accomplishment of the foregoing and related ends, certain illustrative aspects are herein described, taken in conjunction with the following description and drawings, which are indicative of the various ways in which the principles disclosed herein may be practiced, and all aspects and their equivalents are intended to fall within the scope of within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent by reading the following detailed description in conjunction with the accompanying drawings. Like reference numerals generally refer to like parts or elements throughout this disclosure.

FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present disclosure;

FIG. 2 shows a schematic diagram of a pixel acquisition circuit 200 according to some embodiments of the present disclosure;

FIG. 3 shows a timing diagram of control signals of a pixel acquisition circuit in the row direction according to some embodiments of the present disclosure;

4A and 4B respectively show schematic diagrams of the row reset gating module 240 according to some embodiments of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present disclosure.

The image sensor 100 includes a pixel acquisition circuit array 110 , a global control unit 120 and a readout unit 130 . As shown in FIG. 1 , the pixel acquisition circuit array 110 is coupled to the global control unit 120 and the readout unit 130 respectively. Specifically, the global control unit 120 is coupled to the pixel acquisition circuit array 110 via a global reset signal line. The readout unit 130 is coupled to the pixel acquisition circuit array 110 via a row selection line, a row request line, a row event clear signal line, a row reset signal line and a column state signal line.

Wherein, the pixel acquisition circuit array 110 is composed of the same plurality of pixel acquisition circuits 200 (that is, pixel units) arranged two-dimensionally in space (as shown in FIG. this). According to the embodiment of the present disclosure, the pixel acquisition circuit 200 monitors the light intensity change in the field of view in real time, and enters the trigger state when the light intensity change meets a certain condition, that is, triggers and generates an event to indicate the corresponding position in the field of view at this time There is a motion event.

The readout unit 130 is capable of reading out event information of events generated by the pixel acquisition circuit array 110 . In one embodiment, the event information includes event location information and triggered time information.

The global control unit 120 resets the entire pixel acquisition circuit array 110 when the image sensor 100 is powered on, so as to ensure that each pixel acquisition circuit 200 has a stable initial state.

According to an embodiment of the present disclosure, the readout unit 130 further includes a row selection subunit 132 , a column selection subunit 134 and a readout control subunit 136 . The readout control subunit 136 is coupled to the row selection subunit 132 and the column selection subunit 134 respectively.

Further, the row selection subunit 132 is coupled to each row of pixel acquisition circuits in the pixel acquisition circuit array 110 via a row selection line, a row request line, a row event clear signal line, and a row reset signal line. The column selection subunit 134 is coupled to each column of pixel acquisition circuits in the pixel acquisition circuit array 110 via a column state signal line. Wherein, the row selection subunit 132 manages the pixel acquisition circuit array in the row direction; the column selection subunit 134 manages the pixel acquisition circuit array in the column direction. The readout control subunit 136 controls the row selection subunit 132 and the column selection subunit 134 . The row selection unit and the column selection unit may be a decision device for random scanning, or a selection scanning circuit for sequential scanning. Since these circuits are some general-purpose circuit modules, the embodiments of the present disclosure do not limit this, nor do they repeat.

It should be noted that, according to the embodiments of the present disclosure, in addition to general circuit modules, a non-response time circuit module is added to the row selection subunit 132 . The non-response time circuit module is coupled to each pixel acquisition circuit 200 via a row reset signal line and a row event clear signal line.

In one embodiment, the readout control subunit 136 first controls the row selection subunit 132 to select a row of pixel acquisition circuits, for example, the row selection subunit 132 receives a row request signal from the pixel acquisition circuit array 110, and then sends a The pixel acquisition circuit sends a row selection signal to indicate that the row of pixel acquisition circuits is selected. Afterwards, the readout control subunit 136 controls the column selection subunit 134 to read the event information of the triggered event in the row of pixel acquisition circuits.

When a row of pixel acquisition circuits is selected, the non-response time circuit module generates a row reset signal, and transmits it to all pixel acquisition circuits of the row through the row reset signal line, so as to control the pixel non-response time. Wherein, the effective time of the row reset signal is the non-response time of the pixel acquisition circuit. In other words, the non-response duration of the pixel acquisition circuit is controlled by the length of the effective time of the row reset signal.

In addition, at the end of the row reset signal, the non-response time circuit module also generates a row event clear signal, and transmits it to all the pixel acquisition circuits of the row through the row event clear signal line, for clearing the generated pixels in the row of pixel acquisition circuits. event.

According to the embodiments of the present disclosure, the non-response time circuit module can be realized by using a traditional ramp generator and a comparator circuit; it can also be realized by using a digital circuit, for example, a sequential logic circuit coordinated by a counter. Since these circuits are some common circuit modules, details will not be repeated here.

According to the image sensor 100 of the present disclosure, a non-response time circuit module is added in the row selection subunit 132, and the non-response time circuit module is moved from the inside of the pixel acquisition circuit to the external row selection subunit, and by adding the row reset signal line As well as the row event clearing signal line, the row selection subunit controls the pixel acquisition circuit through the non-response time circuit module, and can precisely control the non-response time of a row of pixel acquisition circuits.

In this way, since the non-response time circuit module originally located inside the pixel acquisition circuit is removed, the complexity of the pixel acquisition circuit is reduced, so its area and power consumption can be reduced accordingly. In addition, since the non-response time circuit module is implemented in the row selection sub-unit without being limited by the area factor, the mismatch of the non-response time can be greatly reduced and precise control thereof can be realized.

The pixel acquisition circuit 200 will be described in detail below.

FIG. 2 shows a schematic diagram of a pixel acquisition circuit 200 according to some embodiments of the present disclosure. The pixel acquisition circuit 200 mainly includes: a photodetection module 210 , a trigger generation module 220 , a state latch module 230 , a row reset gating module 240 , and a readout module 250 . In one embodiment, in the pixel acquisition circuit 200, the trigger generation module 220 is coupled to the photodetection module 210, the state latch module 230 is coupled to the trigger generation module 220, and the row reset gating module 240 is respectively coupled to the trigger The generating module 220 and the state latching module 230 , the reading module 250 is coupled to the state latching module 230 .

As shown in Fig. 2, as mentioned above, the pixel acquisition circuit 200 is coupled to the global control unit 120 through the global reset signal line, and is connected to the row selector through the row request line, the row selection line, the row reset signal line and the row event clearing signal line. The unit 132 is coupled to the column selection sub-unit 134 through a column status signal line.

Wherein, the photoelectric detection module 210 monitors the light signal irradiated thereon in real time, and outputs an electric signal. The trigger generation module 220 generates a trigger signal when the electrical signal satisfies a predetermined trigger condition (for example, the illuminance change amount and change rate of the light signal pointed to by the electrical signal can exceed respective thresholds). When the state latch module 230 receives the trigger signal, it enters the trigger state and buffers the current trigger event. Afterwards, the readout module 250 outputs the current trigger event.

The trigger generation module 220 further includes a preprocessing subunit 222 and a threshold comparison subunit 224 . The input terminal of the preprocessing subunit 222 is coupled to the output terminal of the photodetection module 210, the input terminal of the threshold comparison subunit 224 is coupled to the output terminal of the preprocessing subunit 222, and the output terminal of the threshold comparison subunit 224 is coupled to to the state latch module 230 .

The preprocessing subunit 222 preprocesses the electrical signal to generate a preprocessed electrical signal. Wherein the preprocessing operation includes at least one of an amplification operation and a filtering operation. According to an implementation manner of the present disclosure, in the preprocessing operation, the amplification operation is to increase the sensitivity of the pixel acquisition circuit 200 to light intensity detection, but this is not necessary. The filtering operation is generally high-pass filtering, that is, it only responds to high-frequency light intensity changes that are fast enough, thereby filtering out those slow light intensity changes. In one embodiment, the preprocessing subunit 222 is implemented as a high-pass filter amplifier, but is not limited thereto.

The threshold comparison subunit 224 receives the preprocessed electrical signal, judges whether the preprocessed electrical signal satisfies a predetermined condition (for example, greater than the first threshold, less than the second threshold, not limited thereto), and when the preprocessed electrical signal satisfies A trigger signal is generated when a predetermined condition is met.

FIG. 2 exemplarily shows an implementation manner of each part in the pixel acquisition circuit 200 . The photodetection module 210 is, for example, a logarithmic photodetector (comprising a coupled photodiode PD1, a transistor T1 and an amplifier A1), the preprocessing subunit 222 can adopt various known filtering and amplification techniques, and the threshold comparison subunit 224 can pass Voltage comparators (in FIG. 2 , including voltage comparators VC1 and VC2 , and an OR gate), the state latch module 230 may be a latch, but it is not limited thereto. Since the functions of the above parts are not different from those of general dynamic vision sensors, they will not be repeated here.

On the one hand, in the pixel acquisition circuit 200 according to the present disclosure, in order to reset only the triggered pixel acquisition circuit, a row reset gating module 240 is added, which at least based on the output of the state latch module 230 generates a reset signal to Trigger generation module 220 . More specifically, the reset signal generated by the row reset gating module 240 is output to the preprocessing subunit 222 .

As shown in FIG. 2 , the input terminals of the preprocessing subunit 222 include a "global reset" terminal and a "local reset" terminal. Wherein, the “global reset” terminal receives a global reset signal from the global control unit 120 , and the global reset signal is only valid when the image sensor 100 is powered on. The reset signal received by the “local reset” terminal is generated by the above-mentioned row reset gating module 240 .

In one embodiment, one input terminal of the row reset gating module 240 is connected to the state latch module 230 to receive the output of the state latch module 230; the other input terminal is connected to the row reset signal line and received through the row reset signal line. The row reset signal from the unresponsive time circuit module; its output terminal is connected to the preprocessing subunit 222 . When the row reset signal is valid and the output of the state latch module 230 is at a high level, the row reset gating module 240 generates a reset signal.

Specifically, when the row where the pixel acquisition circuit 200 is located is selected by the row selection subunit 132 , the corresponding row reset signal is valid. For the triggered pixel acquisition circuit, the output of the state latch module 230 is set to 1 (ie, high level), at this time, the output of the row reset gating module 240 is valid, and the preprocessing subunit 222 is reset. For the untriggered pixel acquisition circuit, the output of the state latch module 230 maintains 0 (ie, low level), at this time, the output of the row reset gating module 240 is invalid, and the preprocessing subunit 222 is not affected.

Through the above method, the reset of the pixel acquisition circuit in the trigger state in a row of pixel acquisition circuits is realized, and by controlling the length of the effective time of the row reset signal, the control of its non-response time can be realized, while for the untriggered The pixel acquisition circuit is not affected.

On the other hand, the state latch module 230 is coupled to the row event clear signal line to receive the row event clear signal from the non-response time circuit module via the row event clear signal line. And, when the row event clear signal is active, the state latch module 230 is reset.

According to an implementation manner, when the global reset signal is valid at the initial power-on moment, the row event clear signal is also valid, and at this time, the state latch modules 230 of all pixel acquisition circuits in the entire pixel acquisition circuit array 110 are reset. Subsequently, in the normal operation of the image sensor 100, when a certain row of pixel acquisition circuits is selected by the row selection subunit 132, the row event clear signal is valid for a short period of time at the end of the row reset signal to clear the generated events of the row.

It should be noted that the present disclosure does not place too many restrictions on the specific length of a short period of time. Generally speaking, the valid period of the row event clear signal is much shorter than the valid period of the row reset signal.

Based on the above description, compared with the pixel acquisition circuit of a general dynamic vision sensor, the main body of the pixel acquisition circuit of the present disclosure is consistent with it, but the differences are mainly reflected in the following two points.

First, a row reset gating unit is added to generate a reset signal that triggers the preprocessing subunit in the generation module. In one embodiment, more specifically, a local reset signal of a high pass filter amplifier is generated.

Second, the reset signal of the state latch module is the row event clearing signal (through the row event clearing signal line) output by the row selection subunit, which resets the latches of all pixel acquisition circuits in the row.

FIG. 3 shows a timing diagram of control signals of the pixel acquisition circuit in the row direction according to some embodiments of the present disclosure. The working timing of the pixel acquisition circuit 200 and the image sensor 100 will be further described below with reference to FIGS. 1-3 . It should be understood that the contents in Figs. 1-3 are complementary to each other, and repeated descriptions will not be repeated.

Figure 3 shows row request signal, row selection signal, row reset signal and row event clear signal respectively, and all signals are set to be high level active (of course, the present disclosure is not limited to this, space is limited, this will not be listed here).

When a pixel acquisition circuit 200 in a row of pixel acquisition circuits is triggered, the state latch module 230 in the pixel acquisition circuit 200 is set, and the readout module 250 pulls up the row request signal (as shown in a in FIG. 3 ). When the row is selected by the row selection subunit 132, the row selection signal and the row reset signal are valid at the same time (as shown in b in FIG. 3 ). The row selection signal is valid, and the state information of the state latch module 230 of the row pixel acquisition circuit 200 is sent to the column state signal line (obtained by the column selection subunit 134) through the readout module 250, and then the row selection signal is invalid ( As shown in c in Figure 3).

The row reset signal is set to be effective when the row is selected, and for the pixel acquisition circuit 200 triggered in the pixel acquisition circuit 200 of this row, the output of the row reset gating module 240 is valid, and the preprocessing subunit 222 in the pixel acquisition circuit 200 is reset, the pixel acquisition circuit 200 enters a non-response time. For the untriggered pixel acquisition circuits 200 in the row of pixel acquisition circuits 200 , the output of the row reset gating module 240 remains invalid, and the working state of the pixel acquisition circuits 200 is not affected.

After a period of time (as shown in e in FIG. 3 ), the row reset signal becomes invalid. At this time, for the triggered pixel acquisition circuit 200, the output of its row reset gating module 240 is invalid, and the reset state of the preprocessing subunit 222 is released. , the pixel acquisition circuit 200 exits the non-response time, and restarts to detect changes in the external light intensity.

At the same time, at the end of the row reset signal (as shown in d to e in the figure), the row event clear signal is valid, the state latch module 230 in the pixel acquisition circuit 200 of this row is reset, and the event information stored before is all cleared .

According to an embodiment of the present disclosure, the length of time the row reset signal is active (ie, from b to e in FIG. 3 ) is longer than the time length of the row event clear signal (ie, from d to e in FIG. 3 ). In addition, the valid time period of the row event clear signal is included in the valid time period of the row reset signal, and the valid row event clear signal is usually located at the end of the valid row reset signal. In addition, referring to FIG. 3 , in the acquisition of a pixel event as shown in FIG. 3 , the row reset signal and the row event clear signal become invalid at the same moment (e in FIG. 3 ).

It should be understood that, except for the above description, the present disclosure does not place too many restrictions on the valid time length of the row reset signal and the valid time length of the row event clear signal.

To further illustrate the row reset gating module 240, FIG. 4A and FIG. 4B respectively show schematic diagrams of the row reset gating module 240 according to some embodiments of the present disclosure. It should be understood that FIG. 4A and FIG. 4B are supplements to the aforementioned content about FIG. 1-FIG. 3 , and repeated descriptions will not be repeated.

It should be noted that FIG. 4A and FIG. 4B are only examples, and do not limit the implementation of the row reset gating module 240. Based on the embodiments and descriptions of the present disclosure, those skilled in the art can easily think of other ways to realize the row reset gating modules are all within the protection scope of the present disclosure.

As shown in Figure 4A, the row reset gating module 240 includes a first operation subunit, the first input terminal of the first operation subunit is connected to the row reset signal line, the second input terminal is connected to the output terminal of the state latch module 230, and the first The output terminal of the operation subunit is coupled to an input terminal of the preprocessing subunit 222 (such as the “local reset” terminal in FIG. 2 ). The row reset gating module 240 outputs a valid reset signal to the preprocessing subunit 222 when the pixel acquisition circuit 200 enters the trigger state and the row reset signal is valid.

In FIG. 4A, the first operation subunit is implemented as a simple AND gate, only when the output signal of the state latch module 230 is high level (for example, when the output signal is 1, it means that the pixel acquisition circuit is in trigger state) and the row reset signal is valid, the output of the row reset gating module 240 is valid (for example, the output is 1, that is, the reset signal received by the preprocessing subunit 222 is 1).

Here, the default signal is valid when the signal is high (ie, the signal is 1). Of course, it should be understood that if the reset signal of the preprocessing subunit 222 is low valid, then the AND gate can be further simplified into a NAND gate circuit. In addition, the use of dynamic logic can also simplify its implementation, which will not be listed in this disclosure.

Fig. 4B shows another embodiment. The row reset gating module 240 at least includes: a first switch S1 and a second switch S2. Wherein, the first terminal of the first switch S1 is connected to the row reset signal line, and the second terminal is connected to an input terminal of the preprocessing subunit 222 (such as the "local reset" terminal in Figure 2). In addition, the control of the first switch S1 The terminal is connected to the output terminal of the state latch module 230 . The first terminal of the second switch S2 is connected to the ground, and the second terminal of the second switch is also connected to the input terminal of the preprocessing subunit as the first switch S1. In some embodiments, the row reset gating module 240 further includes a second operation subunit, and the control terminal of the second switch S2 is connected to the output terminal of the state latch module 230 through the second operation subunit.

As shown in FIG. 4B , the second operation subunit is implemented as a NOT gate, that is, the control signal of the second switch S2 is the inverted output of the state latch module 230 .

When the pixel acquisition circuit 200 is not triggered, the output of the state latch module 230 is 0, the first switch S1 is open, the second switch S2 is closed, and the row reset signal is invalid, that is, the preprocessing subunit 222 has not received a valid reset Signal. When the pixel acquisition circuit 200 enters the trigger state, the output of the state latch module 230 is 1, the second switch S2 is disconnected, the first switch S1 is closed, and the output of the row reset gating module 240 is a row reset signal. When the row reset signal is valid , the reset signal of the preprocessing subunit 222 is valid.

It can be seen from the embodiments shown in FIG. 4A and FIG. 4B that the circuit structure of the row reset gating module 240 is very simple, and can be realized by simple AND gate logic or switches without increasing the complexity of the pixel acquisition circuit. Furthermore, compared with general pixel acquisition circuits, the area and power consumption of the pixel acquisition circuit 200 of the present disclosure will be correspondingly reduced.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Similarly, it should be appreciated that in the above description of exemplary embodiments of the disclosure, in order to streamline the disclosure and to facilitate an understanding of one or more of the various disclosed aspects, various features of the disclosure are sometimes grouped together into a single embodiment, figure, or its description. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this disclosure.

In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used when describing some embodiments to indicate that two or more components are in physical contact or have an electrical signal path, for example, two components are electrically connected through a signal line, or two components There are other electrical components or circuits between them, but there is a signal path between the two components through other electrical components. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited by the context herein.

Those skilled in the art will understand that the modules or units or components of the devices in the examples disclosed herein may be arranged in the device as described in this embodiment, or alternatively may be located in a different location than the device in this example. in one or more devices. The modules in the preceding examples may be combined into one module or furthermore may be divided into a plurality of sub-modules.

Those skilled in the art can understand that the modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment. Modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method or method so disclosed may be used in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of equipment are combined. Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

In addition, those skilled in the art will understand that although some embodiments described herein include some features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of the present disclosure. and form different embodiments. For example, any one of the claimed embodiments may be used in any combination.

Furthermore, some of the described embodiments are described herein as a method or combination of method elements that may be implemented by a processor of a computer system or by other means for performing the described function. Thus, a processor with the necessary instructions for carrying out the described method or element of a method forms a means for carrying out the method or element of a method. Furthermore, an element described herein of an apparatus embodiment is an example of a means for carrying out the function performed by the element for the purpose of carrying out the disclosure.

As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe generic objects merely means referring to different instances of similar objects and is not intended to imply such The described objects must have a given order temporally, spatially, sequentially or in any other way.

While the disclosure has been described in terms of a limited number of embodiments, it will be apparent to a person skilled in the art having the benefit of the above description that other embodiments are conceivable within the scope of the disclosure thus described. In addition, it should be noted that the language used in the specification has been chosen primarily for the purpose of readability and instruction rather than to explain or delineate the disclosed subject matter. Accordingly, many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. With regard to the scope of the present disclosure, the disclosure of the present disclosure is intended to be illustrative rather than restrictive, and the scope of the present disclosure is defined by the appended claims.

Claims

A pixel acquisition circuit, comprising:

The photoelectric detection module is suitable for real-time monitoring of the optical signal irradiated thereon, and outputs an electrical signal;

a trigger generating module, coupled to the photodetection module, adapted to generate a trigger signal when the electrical signal meets a predetermined trigger condition; and

A state latch module, coupled to the trigger generating module, is adapted to enter a trigger state and cache this trigger event when receiving the trigger signal;

A row reset gating module, coupled to the trigger generation module and the state latch module, respectively, adapted to generate a reset signal to the trigger generation module based at least on the output of the state latch module; and

The readout module, coupled to the state latch module, is adapted to output the current trigger event.
The pixel acquisition circuit as claimed in claim 1, wherein,

The row reset gating module is coupled to a row reset signal line, and is also suitable for receiving a row reset signal through the row reset signal line, and when the row reset signal is valid and the output of the state latch module is high Normally, a reset signal is generated.
The pixel acquisition circuit as claimed in claim 2, wherein,

The state latch module is coupled to a row event clearing signal line, and is adapted to receive a row event clearing signal through the row event clearing signal line, and be reset when the row event clearing signal is valid.
The pixel acquisition circuit according to claim 3, wherein,

The row reset strobe signal is also suitable for receiving the row reset signal when the row where the pixel acquisition circuit is located is selected;

The state latch module is further adapted to receive the row event clear signal before the end of the row reset signal.
The pixel acquisition circuit according to any one of claims 1-4, wherein the trigger generating module comprises:

A preprocessing subunit, the input terminal of which is coupled to the output terminal of the photodetection module, is suitable for preprocessing the electrical signal to generate a preprocessed electrical signal;

A threshold comparison subunit, whose input terminal is coupled to the output terminal of the preprocessing subunit, is adapted to receive the preprocessed electrical signal, and generate a trigger when the preprocessed electrical signal satisfies a predetermined condition Signal.
The pixel acquisition circuit as claimed in claim 5, wherein,

The row reset gating module is further adapted to be coupled to the preprocessing subunit, and output the generated reset signal to the preprocessing subunit.
The pixel acquisition circuit according to claim 5 or 6, wherein the row reset gating module comprises:

The first operation subunit, its first input terminal is connected to the row reset signal line, its second input terminal is connected to the output terminal of the state latch module, and its output terminal is coupled to the preprocessing subunit,

The row reset gating module is adapted to output a valid reset signal to the preprocessing subunit when the pixel acquisition circuit enters a trigger state and the row reset signal is valid.
The pixel acquisition circuit according to claim 5 or 6, wherein the row reset gating module comprises:

The first switch, its first end is connected to the row reset signal line, its second end is connected to the preprocessing subunit, and its control end is connected to the output end of the state latch module;

The second switch has its first terminal connected to the ground, its second terminal connected to the preprocessing subunit, and its control terminal connected to the second operation subunit;

The second operation subunit, the first end of which is connected to the output end of the state latch module, and the second end of which is connected to the control end of the second switch;

The row reset gating module is further adapted to turn off the second switch, close the first switch, and output the row reset signal when the pixel acquisition circuit enters the trigger state, and output the row reset signal when the row reset signal is valid. A valid reset signal is given to the pre-processing subunit.
An image sensor comprising:

An array of pixel acquisition circuits, comprising a plurality of pixel acquisition circuits according to any one of claims 1-8;

A global control unit, coupled to the pixel acquisition circuit array via a global reset signal line, is adapted to reset the pixel acquisition circuit array when the image sensor is powered on;

The readout unit is coupled to the pixel acquisition circuit array via a row selection line, a row request line, a row event clearing signal line, a row reset signal line and a column state signal line, and is suitable for reading out the output generated by the pixel acquisition circuit array. Event information for the event.
The image sensor according to claim 9, wherein the pixel acquisition circuits are spatially arranged two-dimensionally, and

The readout unit includes:

The row selection subunit is coupled to the pixel acquisition circuits of each row through the row selection line, the row request line, the row event clearing signal line, and the row reset signal line, and is suitable for managing the pixel acquisition circuit array in the row direction;

A column selection subunit, coupled to each column of pixel acquisition circuits via a column state signal line, is suitable for managing the array of pixel acquisition circuits in the column direction;

A readout control subunit, coupled to the row selection subunit and the column selection subunit respectively, is adapted to control the row selection subunit and the column selection subunit.
The image sensor of claim 10, wherein the row selection subunit comprises:

The non-response time circuit module is coupled to the row reset gating module in the pixel acquisition circuit through the row reset signal line, and is suitable for generating a row reset signal to the row reset when a certain row of pixel acquisition circuits is selected. The gating module controls the non-response time of the pixel acquisition circuit by passing the effective time of the row reset signal.
The image sensor as claimed in claim 11, wherein,

The non-response time circuit module is coupled to the state latch module in the pixel acquisition circuit via the row event clearing signal line, and is also adapted to generate a row event clearing signal to the row event clearing signal before the end of the row reset signal A state latch module, to clear events cached in the state latch module.