CN113747090B

CN113747090B - Pixel acquisition circuit and image sensor

Info

Publication number: CN113747090B
Application number: CN202111021537.2A
Authority: CN
Inventors: 陈守顺; 郭梦晗
Original assignee: Howay Sensor Shanghai Co ltd
Current assignee: Howay Sensor Shanghai Co ltd
Priority date: 2021-09-01
Filing date: 2021-09-01
Publication date: 2022-09-30
Anticipated expiration: 2041-09-01
Also published as: WO2023029061A1; CN113747090A

Abstract

The application discloses pixel acquisition circuit and image sensor. Wherein, the image sensor includes: a pixel acquisition circuit array comprising a plurality of pixel acquisition circuits; the global control unit is coupled with the pixel acquisition circuit array through a global reset signal line and is suitable for resetting the pixel acquisition circuit array when the image sensor is electrified; and the reading unit is coupled with the pixel acquisition circuit array through a row selection line, a row request line, a row event clearing signal line, a row reset signal line and a column state signal line and is suitable for reading the event information of the event generated by the pixel acquisition circuit array.

Description

Pixel acquisition circuit and image sensor

Technical Field

The present disclosure relates to the field of image sensor technology, and more particularly, to a novel image sensor.

Background

Among the many application areas of image sensors, detection of moving objects is an important aspect. In this application field, a dynamic vision image sensor (hereinafter, referred to as a dynamic vision sensor) is increasingly gaining attention due to its unique advantages, compared to a conventional image sensor (e.g., an active pixel sensor).

Based on the pixel unit (or called as a pixel acquisition circuit) designed by the bionic principle, the dynamic vision sensor can continuously respond to the light intensity change in the visual field in real time without any exposure time, so that the dynamic vision sensor can easily detect a high-speed moving object. In addition, the dynamic vision sensor only responds to and outputs the position information of the pixel unit corresponding to the area with light intensity change in the visual field, and automatically shields useless background information, so that the dynamic vision sensor also has the advantages of small output data volume, low occupied bandwidth and the like. The characteristics of the dynamic vision sensor enable the image processing system at the rear end to directly acquire and process useful dynamic information in the visual field, thereby greatly reducing the requirements on storage and calculation capacity of the dynamic vision sensor and achieving better real-time performance.

In general, a pixel cell of a dynamic vision sensor needs to be forced into a reset state for a period of time after detecting an event, which is called a non-response time. During this time, the pixel cell maintains a reset state and does not respond to ambient light intensity changes. The non-response time for the pixel cell can ensure that it is reliably and stably reset after an event is detected, and can limit the amount of events that it can output to its maximum per unit time. In a specific implementation, a special module is usually provided inside the pixel unit to perform this function, and a weak current source is generally used to charge the capacitor to generate a ramp signal to control the non-response time. However, this special module increases the overhead of the pixel cell in terms of area and power consumption. Furthermore, due to variations in the integrated circuit manufacturing process, there is also a certain mismatch in the non-response times of different pixel cells, which is critical for certain applications of dynamic vision sensors, such as high-speed video reconstruction.

In view of the above, a new image sensor is needed to solve the above problems.

Disclosure of Invention

The present disclosure provides a new pixel acquisition circuit and image sensor in an attempt to solve or at least alleviate at least one of the problems identified above.

According to an aspect of the present disclosure, there is provided a pixel acquisition circuit comprising: the photoelectric detection module is suitable for monitoring the optical signal irradiated on the photoelectric detection module in real time and outputting an electric signal; the trigger generation module is coupled to the photoelectric detection module and is suitable for generating a trigger signal when the electric signal meets a preset trigger condition; the state latch module is coupled to the trigger generation module and is suitable for entering a trigger state and caching the trigger event when receiving the trigger signal; the row reset gating module is respectively coupled to the trigger generation module and the state latch module and is suitable for generating a reset signal to the trigger generation module at least based on the output of the state latch module; and the reading module is coupled to the state latch module and is suitable for outputting the trigger event.

Optionally, in the pixel acquisition circuit according to the present disclosure, the row reset strobe module is coupled to the row reset signal line, and is further adapted to receive a row reset signal via the row reset signal line, and generate a reset signal when the row reset signal is active and the output of the state latch module is at a high level.

Optionally, in the pixel acquisition circuit according to the present disclosure, the state latch module is coupled to the row event clear signal line, and is further adapted to receive the row event clear signal via the row event clear signal line and be reset when the row event clear signal is active.

Optionally, in the pixel acquisition circuit according to the present disclosure, the row reset strobe signal is further adapted to receive a row reset signal when the row of the pixel acquisition circuit is selected; the state latch module is further adapted to receive a row event clear signal before the row reset signal ends.

Optionally, in the pixel acquisition circuit according to the present disclosure, the trigger generation module includes: the input end of the preprocessing subunit is coupled with the output end of the photoelectric detection module and is suitable for preprocessing the electric signal to generate a preprocessed electric signal; and the input end of the threshold comparison subunit is coupled with the output end of the preprocessing subunit, and the threshold comparison subunit is suitable for receiving the preprocessed electric signal and generating a trigger signal when the preprocessed electric signal meets a preset condition.

Optionally, in the pixel acquisition circuit according to the present disclosure, the row reset gating module is further adapted to be coupled to the preprocessing subunit and output the generated reset signal to the preprocessing subunit.

Optionally, in the pixel acquisition circuit according to the present disclosure, the row reset gating module includes: the first input end of the first operation subunit is connected with the row reset signal line, the second input end of the first operation subunit is connected with the output end of the state latch module, the output end of the first operation subunit is coupled to the preprocessing subunit, and the row reset gating module is suitable for outputting an effective reset signal to the preprocessing subunit when the pixel acquisition circuit enters a trigger state and the row reset signal is effective.

Optionally, in a pixel acquisition circuit according to the present disclosure, the row reset gating module includes: the first end of the first switch is connected with the row reset signal line, the second end of the first switch is connected with the preprocessing subunit, and the control end of the first switch is connected with the output end of the state latch module; the first end of the second switch is grounded, the second end of the second switch is connected with the preprocessing subunit, and the control end of the second switch is connected with the second operation subunit; and the first end of the second operation subunit is connected with the output end of the state latch module, the second end of the second operation subunit is connected with the control end of the second switch, and the row reset gating module is also suitable for disconnecting the second switch and closing the first switch to output a row reset signal when the pixel acquisition circuit enters a trigger state, and outputting an effective reset signal to the preprocessing subunit when the row reset signal is effective.

According to another aspect of the present disclosure, there is provided an image sensor including: a pixel acquisition circuit array comprising a plurality of pixel acquisition circuits as described above; the global control unit is coupled with the pixel acquisition circuit array through a global reset signal line and is suitable for resetting the pixel acquisition circuit array when the image sensor is electrified; and the reading unit is coupled with the pixel acquisition circuit array through a row selection line, a row request line, a row event clearing signal line, a row reset signal line and a column state signal line and is suitable for reading the event information of the event generated by the pixel acquisition circuit array.

Alternatively, in an image sensor according to the present disclosure, the pixel acquisition circuits are spatially arranged in two dimensions.

Alternatively, in an image sensor according to the present disclosure, the readout unit includes: the row selection subunit is coupled with each row of pixel acquisition circuits through a row selection line, a row request line, a row event clearing signal line and a row reset signal line and is suitable for managing the pixel acquisition circuit array in the row direction; the column selection subunit is coupled with each column of pixel acquisition circuits through a column state signal line and is suitable for managing the pixel acquisition circuit array in the column direction; and the reading control subunit is respectively coupled to the row selecting subunit and the column selecting subunit and is suitable for controlling the row selecting subunit and the column selecting subunit.

Optionally, in an image sensor according to the present disclosure, the row selecting subunit includes: and the non-response time circuit module is coupled with the row reset gating module in the pixel acquisition circuit through a row reset signal line and is suitable for generating a row reset signal to the row reset gating module when a certain row of pixel acquisition circuit is selected so as to control the non-response time of the pixel acquisition circuit through the effective time of the row reset signal.

Optionally, in an image sensor according to the present disclosure, the non-response time circuit block is coupled to the state latch block in the pixel acquisition circuit via a row event clear signal line, and is further adapted to generate a row event clear signal to the state latch block to clear events buffered in the state latch block before the row reset signal ends.

According to the pixel acquisition circuit disclosed by the invention, a row reset gating unit is added and is used for generating a reset signal for triggering the preprocessing subunit in the generation module. Further, the row reset strobe block generates the reset signal when the row reset signal is active and the output of the state latch block is high (i.e., the pixel acquisition circuit is in a triggered state). Therefore, the reset of the pixel acquisition circuit in a trigger state in the pixel acquisition circuit in one row is realized through the row reset gating unit, and the control of the non-response time of the pixel acquisition circuit can be realized by controlling the effective duration of the row reset signal.

In addition, the reset signal of the state latch block is a row event clear signal output by the row select subunit, and the row event clear signal is asserted for a short period of time at the end of the row reset signal, which resets the state latch block.

Drawings

To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings, which are indicative of various ways in which the principles disclosed herein may be practiced, and all aspects and equivalents thereof are intended to be within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description read in conjunction with the accompanying drawings. Throughout this disclosure, like reference numerals generally refer to like parts or elements.

FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present disclosure;

fig. 2 illustrates a schematic diagram of a pixel acquisition circuit 200, according to some embodiments of the present disclosure;

FIG. 3 illustrates a timing diagram of control signals in a row direction for a pixel acquisition circuit according to some embodiments of the present disclosure;

fig. 4A and 4B each illustrate a schematic diagram of a row reset gating module 240, according to some embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Fig. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present disclosure.

The image sensor 100 includes a pixel acquisition circuit array 110, a global control unit 120, and a readout unit 130. As shown in fig. 1, the pixel acquisition circuit array 110 is coupled to the global control unit 120 and the readout unit 130, respectively. Specifically, the global control unit 120 is coupled to the pixel acquisition circuit array 110 via a global reset signal line. The readout unit 130 is coupled to the pixel acquisition circuit array 110 via a row select line, a row request line, a row event clear signal line, a row reset signal line, and a column status signal line.

Here, the pixel collection circuit array 110 is composed of a plurality of identical pixel collection circuits 200 (i.e., pixel units) spatially arranged in two dimensions (a 3 × 3 pixel collection circuit array is shown in fig. 1, but not limited thereto). According to the embodiment of the present disclosure, the pixel acquisition circuit 200 monitors the light intensity change in the field of view in real time, and enters a trigger state when the light intensity change meets a certain condition, that is, an event is triggered and generated to indicate that a motion event occurs at a corresponding position in the field of view at the moment.

The readout unit 130 can read out event information of events generated by the pixel acquisition circuit array 110. In one embodiment, the event information includes location information of the event and time information of the triggered event.

Global control unit 120 resets the entire pixel acquisition circuit array 110 when image sensor 100 is powered on to ensure that each pixel acquisition circuit 200 has a stable initial state.

According to an embodiment of the present disclosure, the readout unit 130 further includes a row selection subunit 132, a column selection subunit 134, and a readout control subunit 136. The readout control subunit 136 is coupled to the row selection subunit 132 and the column selection subunit 134 respectively.

Further, the row selecting subunit 132 is coupled to each row of pixel collecting circuits in the pixel collecting circuit array 110 via a row selecting line, a row requesting line, a row event clearing signal line and a row resetting signal line. The column selection subunit 134 is coupled to each column of pixel acquisition circuits in the pixel acquisition circuit array 110 via a column status signal line. Wherein, the row selection subunit 132 manages the pixel acquisition circuit array in the row direction; the column selection sub-unit 134 manages the pixel acquisition circuit array in the column direction. The readout control subunit 136 controls the row selection subunit 132 and the column selection subunit 134. The row selecting unit and the column selecting unit may be a randomly scanned decision device or a sequentially scanned selection scanning circuit, and since these circuits are all general circuit modules, this is not limited in the embodiments of the present disclosure, and is not described in detail.

It should be noted that, according to the embodiment of the present disclosure, in addition to the general circuit blocks, a non-response time circuit block is added to the row selection subunit 132. The non-response time circuit block is coupled to each pixel capture circuit 200 via a row reset signal line and a row event clear signal line.

In one embodiment, the readout control subunit 136 first controls the row selection subunit 132 to select a row of pixel acquisition circuits, for example, the row selection subunit 132 receives a row request signal from the pixel acquisition circuit array 110, and then sends a row selection signal to one of the rows of pixel acquisition circuits to indicate that the row of pixel acquisition circuits is selected. Then, the readout control subunit 136 controls the column selection subunit 134 to read the event information of the triggered event in the row of pixel acquisition circuits.

When a certain row of pixel acquisition circuits is selected, the non-response time circuit module generates a row reset signal, and transmits the row reset signal to all the pixel acquisition circuits in the row through a row reset signal line, so as to realize the control of the non-response time of the pixels. The time during which the row reset signal is active is the non-response time of the pixel acquisition circuit. In other words, the non-response time of the pixel acquisition circuit is controlled by the length of the active time of the row reset signal.

In addition, at the end of the row reset signal, the non-response time circuit module also generates a row event clear signal and transmits the row event clear signal to all the pixel acquisition circuits in the row through a row event clear signal line, so as to clear the generated events in the pixel acquisition circuits in the row.

According to embodiments of the present disclosure, the non-response time circuit block may be implemented using conventional ramp generator and comparator circuits; digital circuits may also be implemented, for example, by counter-coordinated sequential logic circuits. Since the circuits are all general circuit modules, detailed description is omitted here.

According to the image sensor 100 of the present disclosure, the non-response time circuit module is added in the row selection subunit 132, the non-response time circuit module is moved from the inside of the pixel acquisition circuit to the external row selection subunit, and by adding the row reset signal line and the row event clearing signal line, the row selection subunit controls the pixel acquisition circuit through the non-response time circuit module, and the non-response time of the row pixel acquisition circuit can be precisely controlled.

In this way, since the non-response time circuit block originally located inside the pixel acquisition circuit is removed, the complexity of the pixel acquisition circuit is reduced, and thus the area and power consumption thereof can be correspondingly reduced. In addition, due to the fact that the circuit module is not limited by area factors, mismatch of non-response time can be greatly reduced by realizing the non-response time circuit module in the row selection subunit, and accurate control over the circuit module is achieved.

The pixel acquisition circuit 200 is described in detail below.

Fig. 2 illustrates a schematic diagram of a pixel acquisition circuit 200 according to some embodiments of the present disclosure. The pixel acquisition circuit 200 mainly includes: a photodetection module 210, a trigger generation module 220, a state latch module 230, a row reset strobe module 240, and a readout module 250. In one embodiment, in the pixel acquisition circuit 200, the trigger generation module 220 is coupled to the photo detection module 210, the state latch module 230 is coupled to the trigger generation module 220, the row reset strobe module 240 is coupled to the trigger generation module 220 and the state latch module 230, respectively, and the readout module 250 is coupled to the state latch module 230.

As shown in fig. 2, the pixel acquisition circuit 200 is coupled to the global control unit 120 via a global reset signal line, the row select subunit 132 via a row request line, a row select line, a row reset signal line and a row event clear signal line, and the column select subunit 134 via a column status signal line, as described above.

The photo detection module 210 monitors the optical signal irradiated thereon in real time and outputs an electrical signal. The trigger generation module 220 generates the trigger signal when the electrical signal satisfies a predetermined trigger condition (e.g., the amount of change in the illuminance of the optical signal pointed to by the electrical signal, the rate of change can exceed respective thresholds). The state latch module 230 enters a trigger state and buffers the trigger event when receiving the trigger signal. Then, the readout module 250 outputs the current trigger event.

The trigger generation module 220 in turn comprises a preprocessing subunit 222 and a threshold comparison subunit 224. An input of the preprocessing subunit 222 is coupled to an output of the photodetection module 210, an input of the threshold comparing subunit 224 is coupled to an output of the preprocessing subunit 222, and an output of the threshold comparing subunit 224 is coupled to the state latch module 230.

The preprocessing subunit 222 preprocesses the electrical signal to generate a preprocessed electrical signal. Wherein the preprocessing operation includes at least one of an amplifying operation and a filtering operation. In the preprocessing operation, the amplification operation is to increase the sensitivity of the pixel acquisition circuit 200 to light intensity detection, but this is not required, according to one implementation of the present disclosure. The filtering operation is typically high-pass filtering, i.e. responding only to high frequencies, i.e. light intensity variations that are fast enough to filter out those slow light intensity variations. In one embodiment, the pre-processing subunit 222 is implemented as a high pass filter amplifier, but is not limited thereto.

The threshold comparing subunit 224 receives the preprocessed electrical signal, determines whether the preprocessed electrical signal satisfies a predetermined condition (for example, greater than the first threshold, less than the second threshold, but not limited thereto), and generates the trigger signal when the preprocessed electrical signal satisfies the predetermined condition.

Fig. 2 schematically illustrates one implementation of portions of a pixel acquisition circuit 200. The photodetection module 210 is, for example, a logarithmic photodetector (including a coupled photodiode PD1, a transistor T1, and an amplifier a1), the preprocessing subunit 222 may employ a variety of well-known filtering and amplifying techniques, the threshold comparison subunit 224 may be implemented by a voltage comparator (in fig. 2, including voltage comparators VC1 and VC2, or a gate), and the state latch module 230 may be a latch, but is not limited thereto. Since the functions of the above parts are not different from those of a general dynamic vision sensor, they are not described herein again.

In one aspect, in the pixel acquisition circuit 200 according to the present disclosure, to reset only the triggered pixel acquisition circuit, a row reset strobe block 240 is added, which generates a reset signal to the trigger generation block 220 based on at least the output of the state latch block 230. More specifically, the reset signal generated by the row reset strobe block 240 is output to the preprocessing subunit 222.

As shown in fig. 2, the input terminals of the preprocessing subunit 222 include a "global reset" terminal and a "local reset" terminal. Here, the "global reset" terminal receives a global reset signal from the global control unit 120, and the global reset signal is valid only at the time of power-on of the image sensor 100. The reset signal received at the "local reset" terminal is generated by the row reset strobe block 240.

In one embodiment, one input of the row reset strobe block 240 terminates the status latch block 230, receiving the output of the status latch block 230; the other input end is connected to a row reset signal line and receives a row reset signal from the non-response time circuit module through the row reset signal line; the output of which is connected to the preprocessing subunit 222. The row reset strobe block 240 generates a reset signal when the row reset signal is active and the output of the state latch block 230 is high.

Specifically, when the row in which the pixel acquisition circuit 200 is located is selected by the row selection subunit 132, its corresponding row reset signal is active. For a triggered pixel acquisition circuit, the output of the state latch block 230 is set to 1 (i.e., high), at which time the output of the row reset strobe block 240 is active and the pre-processing subunit 222 is reset. For an un-triggered pixel capture circuit, the output of the state latch block 230 remains 0 (i.e., low), and at this time, the output of the row reset strobe block 240 is inactive and the pre-processing subunit 222 is not affected.

Through the above mode, the reset of the pixel acquisition circuit in the triggered state in one row of pixel acquisition circuits is realized, and the control of the non-response time of the pixel acquisition circuit can be realized by controlling the length of the effective time of the row reset signal, while the pixel acquisition circuit which is not triggered is not influenced.

The state latch module 230, on the other hand, is coupled to the row event clear signal line to receive the row event clear signal from the non-response time circuit module via the row event clear signal line. Also, the state latch module 230 is reset when the row event clear signal is asserted.

According to one implementation, at the initial power-on time, when the global reset signal is active, the row event clear signal is also active, and at this time, the status latch modules 230 of all the pixel acquisition circuits in the entire pixel acquisition circuit array 110 are reset. Subsequently, in normal operation of the image sensor 100, when a row of pixel acquisition circuits is selected by the row select subunit 132, the row event clear signal is asserted at the end of the row reset signal for a short period of time to clear the generated events for that row.

It should be noted that the present disclosure is not limited to a specific length of the short period, and generally, the duration of the active row event clear signal is much shorter than the duration of the active row reset signal.

Based on the above description, compared with the pixel acquisition circuit of a general dynamic vision sensor, the pixel acquisition circuit of the present disclosure is consistent with it, but the differences are mainly reflected in the following two points.

Firstly, a row reset gating unit is added for generating a reset signal for triggering a preprocessing subunit in a generating module. In one embodiment, more specifically, a local reset signal of the high pass filtered amplifier is generated.

Second, the reset signal of the state latch module is a row event clear signal (via a row event clear signal line) output by the row select subunit, which resets the latches of all the pixel acquisition circuits of the row.

Fig. 3 illustrates a timing diagram of control signals in a row direction for a pixel acquisition circuit according to some embodiments of the present disclosure. The operation timing of the pixel acquisition circuit 200 and the image sensor 100 will be further described with reference to fig. 1 to 3. It should be understood that the contents of fig. 1-3 are complementary and repeated here.

The row request signal, the row select signal, the row reset signal, and the row event clear signal are shown in FIG. 3, respectively, and all of the signals are asserted high (although the disclosure is not limited thereto, and will not be limited to the details).

When a row of pixel acquisition circuits has a pixel acquisition circuit 200 triggered, the state latch module 230 in the pixel acquisition circuit 200 is set, and the readout module 250 pulls the row request signal high (as shown in a in fig. 3). When the row is selected by the row select subunit 132, the row select signal and the row reset signal are active simultaneously (as shown in fig. 3 b). The row selection signal is asserted, the state information of the state latch module 230 of the row pixel capture circuit 200 is sent to the column state signal line (obtained by the column selection subunit 134) through the readout module 250, and then the row selection signal is de-asserted (as shown in c in fig. 3).

The row reset signal is asserted when the row is selected, the output of the row reset strobe block 240 is asserted for the triggered pixel acquisition circuit 200 in the row of pixel acquisition circuits 200, the preprocessing subunit 222 in the pixel acquisition circuit 200 is reset, and the pixel acquisition circuit 200 enters the non-response time. For the pixel acquisition circuits 200 not yet triggered in the row of pixel acquisition circuits 200, the output of the row reset gating module 240 remains invalid, and the operating state of the pixel acquisition circuits 200 is not affected.

After a period of time (as shown in e in fig. 3), the row reset signal becomes invalid, and at this time, for the triggered pixel acquisition circuit 200, the output of the row reset gating module 240 is invalid, the reset state of the preprocessing subunit 222 is released, and the pixel acquisition circuit 200 exits the non-response time and starts detecting the external light intensity change again.

At the same time, at the end of the row reset signal (as shown in d-e), the row event clear signal is asserted, the state latch module 230 in the row pixel capture circuit 200 is reset, and the previously stored event information is all cleared.

According to an embodiment of the present disclosure, the length of time that the row reset signal is active (i.e., from b to e in fig. 3) is greater than the length of time that the row event clear signal is active (i.e., from d to e in fig. 3). Also, the period in which the row event clear signal is active is included in the period in which the row reset signal is active, and the active row event clear signal is usually at the end of the active row reset signal. Further, referring to FIG. 3, in the acquisition of a pixel event as shown in FIG. 3, the row reset signal and the row event clear signal are inactive at the same time (e in FIG. 3).

It should be appreciated that the present disclosure is not unduly limited by the length of time that the row reset signal is active, and the length of time that the row event clear signal is active, other than as described above.

To further illustrate the row reset strobe module 240, fig. 4A and 4B respectively show schematic diagrams of the row reset strobe module 240 according to some embodiments of the present disclosure. It should be understood that fig. 4A and 4B are supplementary to those described above with respect to fig. 1-3, and the repetition thereof will not be repeated.

It should be noted that fig. 4A and 4B are only examples and do not limit the implementation manner of the row reset gating module 240, and based on the embodiments and descriptions of the present disclosure, a person skilled in the art may easily think of other ways to implement the row reset gating module, which are within the protection scope of the present disclosure.

Referring to fig. 4A, the row reset strobe block 240 includes a first operation subunit having a first input connected to the row reset signal line and a second input connected to the output of the state latch block 230, the output of the first operation subunit being coupled to an input (e.g., "local reset" in fig. 2) of the preprocessing subunit 222. The row reset gating module 240 outputs an active reset signal to the preprocessing subunit 222 when the pixel acquisition circuit 200 enters the triggered state and the row reset signal is active.

In fig. 4A, the first operation subunit is implemented as a simple and gate, and the output of the row reset gating module 240 is only valid (for example, the output is 1, i.e., the reset signal received by the preprocessing subunit 222 is 1) when the output signal of the state latch module 230 is high (for example, when the output signal is 1, it indicates that the pixel acquisition circuit is in a triggered state) and the row reset signal is valid.

The default signal is active here when high (i.e. the signal is 1), but it should be understood that the and gate can be further simplified to be a nand gate if the reset signal of the preprocessing subunit 222 is active low. In addition, the implementation mode can be further simplified by adopting dynamic logic, which is not listed in the disclosure.

Fig. 4B shows another embodiment. The row reset gating module 240 includes at least: a first switch S1 and a second switch S2. Wherein the first terminal of the first switch S1 is connected to the row reset signal line, the second terminal is connected to an input terminal (e.g. the "local reset" terminal in fig. 2) of the preprocessing subunit 222, and the control terminal of the first switch S1 is connected to the output terminal of the state latch module 230. The first terminal of the second switch S2 is grounded, and the second terminal of the second switch is also connected to the input terminal of the pre-processing subunit, as is the first switch S1. In some embodiments, the row reset gating module 240 further includes a second operation subunit, and the control terminal of the second switch S2 is connected to the output terminal of the state latch module 230 through the second operation subunit.

As shown in fig. 4B, the second operation subunit is implemented as a not gate, i.e., the control signal of the second switch S2 is the inverted output of the state latch module 230.

When the pixel capture circuit 200 is not triggered, the output of the state latch module 230 is 0, the first switch S1 is open, the second switch S2 is closed, and the row reset signal is inactive, i.e., the pre-processing subunit 222 does not receive a valid reset signal. When the pixel acquisition circuit 200 enters the trigger state, the output of the state latch module 230 is 1, the second switch S2 is open, the first switch S1 is closed, the output of the row reset strobe module 240 is a row reset signal, and when the row reset signal is active, the reset signal of the preprocessing subunit 222 is active.

As can be seen from the embodiments shown in fig. 4A and 4B, the circuit structure of the row reset gating module 240 is very simple, and can be implemented by simple and gate logic or switches, without increasing the complexity of the pixel acquisition circuit. Further, compared to a general pixel acquisition circuit, the area and power consumption of the pixel acquisition circuit 200 of the present disclosure can be reduced accordingly.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: rather, the present disclosure is directed to features more specifically recited in each claim. Rather, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, some embodiments may be described using the term "connected" to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in physical contact or that an electrical signal path exists, for example, two elements are in electrical communication with each other via a signal line, or that another electrical component or circuit exists between the two elements but a signal path exists between the two elements via another electrical component. The terms "coupled" or "communicatively coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in a device as described in this embodiment or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may be further divided into multiple sub-modules.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Moreover, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the disclosure and form different embodiments. For example, any of the claimed embodiments may be used in any combination.

Furthermore, some of the described embodiments are described herein as a method or combination of method elements that can be performed by a processor of a computer system or by other means of performing the described functions. A processor having the necessary instructions for carrying out the method or method elements thus forms a means for carrying out the method or method elements. Further, the elements of the apparatus embodiments described herein are examples of the following apparatus: the apparatus is used to implement the functions performed by the elements for the purposes of this disclosure.

As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this description, will appreciate that other embodiments can be devised which do not depart from the scope of the disclosure as described herein. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the disclosed subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The disclosure of the present disclosure is intended to be illustrative, but not limiting, of the scope of the disclosure, which is set forth in the following claims.

Claims

1. A pixel acquisition circuit comprising:

the photoelectric detection module is suitable for monitoring the optical signal irradiated on the photoelectric detection module in real time and outputting an electric signal;

a trigger generation module, coupled to the photodetection module, adapted to generate a trigger signal when the electrical signal satisfies a predetermined trigger condition; and

the state latch module is coupled to the trigger generation module and is suitable for entering a trigger state and caching the trigger event when receiving the trigger signal;

a row reset gating module, which is respectively coupled to the trigger generation module, the state latch module and the row reset signal line, and is adapted to receive a row reset signal through the row reset signal line, and generate a reset signal to the trigger generation module when the row reset signal is valid and the output of the state latch module is at a high level, wherein the row reset signal is set to be valid when a row of pixel acquisition circuits is selected, and set to be invalid after a period of time; and

and the reading module is coupled to the state latch module and is suitable for outputting the trigger event.

2. The pixel acquisition circuit of claim 1,

the state latch module is coupled to a row event clear signal line, and is further adapted to receive a row event clear signal via the row event clear signal line and to be reset when the row event clear signal is active.

3. The pixel acquisition circuit of claim 2,

the row reset strobe signal is also suitable for receiving the row reset signal when the row of the pixel acquisition circuit is selected;

the state latch module is further adapted to receive the row event clear signal before the row reset signal ends.

4. The pixel acquisition circuit of claim 1, wherein the trigger generation module comprises:

the input end of the preprocessing subunit is coupled with the output end of the photoelectric detection module and is suitable for preprocessing the electric signal to generate a preprocessed electric signal;

and the input end of the threshold comparison subunit is coupled with the output end of the preprocessing subunit, and the threshold comparison subunit is suitable for receiving the preprocessed electric signal and generating a trigger signal when the preprocessed electric signal meets a preset condition.

5. The pixel acquisition circuit of claim 4,

the row reset strobe module is further adapted to be coupled to the pre-processing subunit and output the generated reset signal to the pre-processing subunit.

6. The pixel acquisition circuit of claim 4 or 5, wherein the row reset strobe module comprises:

a first operation subunit, a first input end of which is connected to the row reset signal line, a second input end of which is connected to the output end of the state latch module, an output end of which is coupled to the preprocessing subunit,

the row reset gating module is suitable for outputting an effective reset signal to the preprocessing subunit when the pixel acquisition circuit enters a trigger state and the row reset signal is effective.

7. The pixel acquisition circuit of claim 4 or 5, wherein the row reset strobe module comprises:

the first end of the first switch is connected with a row reset signal line, the second end of the first switch is connected with the preprocessing subunit, and the control end of the first switch is connected with the output end of the state latch module;

the first end of the second switch is grounded, the second end of the second switch is connected with the preprocessing subunit, and the control end of the second switch is connected with the second operation subunit;

the first end of the second operation subunit is connected with the output end of the state latch module, and the second end of the second operation subunit is connected with the control end of the second switch;

the row reset gating module is further adapted to open the second switch, close the first switch, output the row reset signal when the pixel acquisition circuit enters a trigger state, and output an effective reset signal to the preprocessing subunit when the row reset signal is effective.

8. An image sensor, comprising:

an array of pixel acquisition circuits comprising a plurality of pixel acquisition circuits according to any one of claims 1-7;

the global control unit is coupled with the pixel acquisition circuit array through a global reset signal line and is suitable for resetting the pixel acquisition circuit array when the image sensor is electrified;

and the reading unit is coupled with the pixel acquisition circuit array through a row selection line, a row request line, a row event clearing signal line, a row reset signal line and a column state signal line and is suitable for reading out event information of the events generated by the pixel acquisition circuit array.

9. The image sensor of claim 8 wherein the pixel acquisition circuits are spatially arranged in two dimensions, an

The readout unit includes:

the row selection subunit is coupled with each row of pixel acquisition circuits through a row selection line, a row request line, a row event clearing signal line and a row reset signal line and is suitable for managing the pixel acquisition circuit array in the row direction;

the column selection sub-unit is coupled with each column of pixel acquisition circuits through a column state signal line and is suitable for managing the pixel acquisition circuit array in the column direction;

and a readout control subunit, respectively coupled to the row selection subunit and the column selection subunit, and adapted to control the row selection subunit and the column selection subunit.

10. The image sensor of claim 9, wherein the row select subunit comprises:

and the non-response time circuit module is coupled with the row reset gating module in the pixel acquisition circuit through the row reset signal line, and is suitable for generating a row reset signal to the row reset gating module when a certain row of pixel acquisition circuits is selected so as to control the non-response time of the pixel acquisition circuit through the effective time of the row reset signal.

11. The image sensor of claim 10,

the non-response time circuit module is coupled to a state latch module in the pixel acquisition circuit via the row event clear signal line and is further adapted to generate a row event clear signal to the state latch module to clear events buffered in the state latch module before the row reset signal is ended.