WO2023028885A1 - 显示控制方法、显示控制装置和显示装置 - Google Patents

显示控制方法、显示控制装置和显示装置 Download PDF

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Publication number
WO2023028885A1
WO2023028885A1 PCT/CN2021/115812 CN2021115812W WO2023028885A1 WO 2023028885 A1 WO2023028885 A1 WO 2023028885A1 CN 2021115812 W CN2021115812 W CN 2021115812W WO 2023028885 A1 WO2023028885 A1 WO 2023028885A1
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WIPO (PCT)
Prior art keywords
display
image data
control signal
display control
rearranged
Prior art date
Application number
PCT/CN2021/115812
Other languages
English (en)
French (fr)
Inventor
郭鲁强
栗首
韩天洋
马越
王鑫
李晓光
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/904,509 priority Critical patent/US20240194164A1/en
Priority to DE112021008162.4T priority patent/DE112021008162T5/de
Priority to PCT/CN2021/115812 priority patent/WO2023028885A1/zh
Priority to CN202180002387.2A priority patent/CN116097204A/zh
Publication of WO2023028885A1 publication Critical patent/WO2023028885A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/048—Interaction techniques based on graphical user interfaces [GUI]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to a display control method, a display control device and a display device.
  • At least some embodiments of the present disclosure provide a display control method, including executing a first display mode using input image data, wherein the first display mode includes: rearranging the input image data to obtain rearranged image data , wherein the input image data includes an effective line portion for actual display on the display panel and an invalid line portion for non-actual display on the display panel, and the rearrangement image data includes Rearrange the valid row part and rearrange the invalid row part corresponding to the part and the invalid row part respectively; corresponding to the rearranged image data, generate a first image display control signal and a first delay control signal; output the rearranged image data , the first image display control signal and the first delay control signal are used to perform a display operation on the display panel, wherein the first image display control signal is used to correspond to the display operation during the display operation
  • the frame display is performed on the rearranged image data, and the first delay control signal is used to trigger a row scanning process in the display panel for the rearranged effective row portion during the frame display process.
  • rearranging the input image data to obtain the rearranged image data includes: performing an overall inversion and rearrangement operation on the input image data to obtain The rearranged image data, wherein the first delay control signal is obtained according to the position of the rearranged effective line part in the rearranged image data, or the first delay control signal is obtained by preset .
  • the display control method provided by at least some embodiments of the present disclosure further includes: acquiring a display control instruction; and in response to the display control instruction, selecting to perform the first display mode or to perform the second display mode, wherein the second The display mode is different from said first display mode.
  • the second display mode includes: generating the second image display control signal corresponding to the input image data, wherein the second image display The control signal is used for frame display corresponding to the input image data during the display operation; the input image data and the second image display control signal are output for display operation on the display panel.
  • obtaining the display control instruction includes: reading the input port of the display system to which the display panel belongs, and obtaining the input port according to different states of the input port.
  • the display system includes a first executable code corresponding to the first display mode and a second executable code corresponding to the second display mode.
  • the code for selecting to execute the first display mode or the second display mode in response to the display control instruction includes: selecting and executing the first executable code or the second executable code according to the display control instruction Execute the code.
  • the display panel in the first display mode, the display panel is in an inverted state relative to a reference position; in the second display mode, the display The panel is in an upright state relative to the reference position.
  • the display panel includes a gate drive circuit for implementing the row scanning process, and the first delay control signal is used to generate the gate The scan start signal of the drive circuit.
  • the display control method provided by at least some embodiments of the present disclosure further includes: receiving and storing the input image data.
  • a display control device including: an image processing module, a timing generation module, a delay processing module and an output circuit.
  • the image processing module is configured to rearrange the received input image data to obtain rearranged image data, wherein the input image data includes effective line parts for actual display on the display panel and for displaying in the The invalid line part that is not actually displayed on the display panel, the rearranged image data includes the rearranged valid line part and the rearranged invalid line part corresponding to the valid line part and the invalid line part respectively;
  • the timing generation module is It is configured to generate a first image display control signal corresponding to the rearranged image data, wherein the first image display control signal is used to perform frame display corresponding to the rearranged image data during the display operation;
  • the delay processing module is configured to generate a first delay control signal corresponding to the rearranged image data, wherein the first delay control signal is used to trigger the The row scanning process of rearranging the effective row part in the display panel;
  • the output circuit is configured to output the rearranged image data
  • the image processing module includes an image data rearrangement circuit, wherein the image data rearrangement circuit is configured to reverse and rearrange the input image data as a whole row operation to obtain the rearranged image data.
  • the first delay control signal is obtained according to the position of the rearranged effective line part in the rearranged image data, or the first delay
  • the timing control signal is obtained by preset.
  • the delay processing module includes a gate signal timing adjustment module, wherein the gate signal timing adjustment module is configured to control the first delay
  • the signal is set later than the first image display control signal by a predetermined time, the predetermined time is obtained according to the position of the rearranged effective line part in the rearranged image data, or the predetermined time is passed by the preset get.
  • the display control device provided in at least some embodiments of the present disclosure further includes a control device, wherein the control device is configured to, in response to a display control instruction, select to perform the first display mode or to perform the second display mode, wherein , the second display mode is different from the first display mode, the first display mode includes using the rearranged image data, the image display control signal and the first delay control signal, in the The display panel performs display operations.
  • the timing generation module is further configured to generate a second image display control signal corresponding to the input image data, wherein the second image display The control signal is used to perform frame display corresponding to the input image data during the display operation; the second display mode includes using the input image data and the image display control signal to display on the display panel Operation; the output circuit is further configured to output the input image data and the second image display control signal for performing a display operation in the second display mode on the display panel.
  • the display control device provided in at least some embodiments of the present disclosure further includes: a second storage device, wherein the second storage device is configured to store the first executable code corresponding to the first display mode and the corresponding For the second executable code in the second display mode, the display control device is further configured to, in response to the indication of the display control instruction, select to execute the first executable code or Second executable code.
  • the display control device provided in at least some embodiments of the present disclosure further includes an input port, wherein the input port is configured to obtain the display control instruction according to different states of the input port.
  • the display control device provided in at least some embodiments of the present disclosure further includes a first storage device, wherein the first storage device is configured to store the received input image data.
  • At least some embodiments of the present disclosure further provide a display device, including: any one of the above display control devices and a display panel.
  • the display panel includes a gate driving circuit, a data driving circuit and a pixel array.
  • the gate drive circuit is configured to receive a scan control signal to scan the pixel array;
  • the data drive circuit is configured to receive an image data signal and provide the image data signal to the pixel array;
  • the pixel array is configured To receive the image data from the data driving circuit for display operation under the control of the gate driving circuit.
  • the first image display control signal includes the scan control signal, and the image data signal includes the rearranged image data.
  • Fig. 1 is a schematic diagram of a display process of a bar display
  • Fig. 2 is a schematic diagram of a display process of an inverted bar display
  • FIG. 3 is a schematic structural view of a display panel device
  • FIG. 4 is a schematic diagram of a gate drive circuit
  • FIG. 5A is a schematic structural diagram of a shift register
  • Fig. 5B is a timing diagram of the shift register in Fig. 5A;
  • FIG. 6 is a flowchart of a display driving method provided by an embodiment of the present disclosure.
  • Figure 7A is an exemplary input image
  • Fig. 7B is a rearranged image after rearranging the input image in Fig. 7A;
  • FIG. 7C is a timing diagram of delay processing of the display driving method provided by the embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a display driving method provided by another embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display driving device provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display driving device provided by another embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the input image data for the strip display is usually still in full-frame format.
  • the full-frame specifications include, for example, standard definition (480*320, 640*480), high definition (1024*720p, 1920*1080i), full high definition (1920*1080p), ultra high definition (3840*2160, 7680*4320), etc.
  • FIG. 1 is a schematic diagram of a display process of a bar display.
  • the input image data input to display the bar display can be obtained from a storage device (such as a hard disk) or received from a receiving device (such as a modem), for example, the input image data can be 1920*1080 size.
  • the resolution of the bar display is, for example, 1920*360, and includes a timing controller (Timing Controller, TCON).
  • TCON Timing Controller
  • the size of the input image data in the column direction i.e. the number of rows
  • the size of the input image data in the column direction is greater than the size of the actual displayed image of the bar display in the column direction, so only a part of the input image data is displayed in the bar display, and this part can be called an effective row part.
  • the rest are invalid line parts.
  • the "invalid line part” may also have substantial image content, which is not limited by the embodiments of the present disclosure.
  • the invalid line portion may be a valid line portion for display on other display panels.
  • different effective line parts can be spliced into a complete image on the splicing screen, and for the display panel of a splicing unit of the splicing screen, the corresponding invalid part can be the display panel of other splicing units valid part of .
  • the timing controller generates a timing control signal for controlling the display panel to display according to the input image data corresponding to the input image data.
  • the TCON provides the input image data and the generated timing control signal to the bar display, and the bar display performs display according to the timing control signal and the input image data.
  • the first 360 lines of the input image data are valid lines (pointed by the upward arrow in the figure), which can be displayed normally through the bar display, while the remaining invalid lines from the 361st to 1080th lines (720 lines in total) are will not be displayed on the bar display (indicated by the dotted line in the figure).
  • the timing control signal corresponding to the invalid line portion will not actually drive the bar display, and the bar display is not refreshed but keeps displaying the image portion corresponding to the aforementioned valid line portion during the corresponding time period.
  • FIG. 2 is a schematic diagram of a display process of an inverted bar display.
  • the difference in Figure 2 is only that the bar display is placed upside down, for example, the bar display is unintentionally inverted during installation, or in some application scenarios, the bar display was intentionally inverted.
  • the gate signal scanning direction of the gate driver of the bar display is fixed, if the bar display is used in an inverted state, the picture displayed on the bar display will be inverted, as shown in the figure 2.
  • the inverted image data is input in the above-mentioned bar-shaped display, the invalid line portion in the original input image data to be displayed in the bar-shaped display cannot be displayed normally.
  • FIG. 3 is a schematic structural diagram of a display panel device.
  • the display panel in the bar display in FIG. 1 or FIG. 2 may be as shown in FIG. 3 .
  • the display panel device 1 includes an array substrate 11 , a gate driver 12 , a timing controller 13 and a data driver 14 , and the array substrate 11 is electrically connected to the gate driver 12 , the timing controller 13 and the data driver 14 .
  • the array substrate 11 includes a pixel array, the pixel array includes a plurality of rows and columns of pixel units, each pixel unit is used to realize the display of a sub-pixel, and the array substrate 11 also includes a plurality of scanning lines GL and a plurality of data lines DL, a plurality of scanning lines GL respectively provide gate signals for multiple rows of pixel units, and a plurality of data lines DL respectively provide data signals for multiple rows of pixel units.
  • the gate driver 12 is connected to a plurality of scan lines GL for providing gate scan signals to drive the plurality of scan lines GL.
  • the data driver 14 is connected to a plurality of data lines DL for providing data signals to drive the plurality of data lines DL.
  • the timing controller 13 is used to process image data RGB input from the outside of the display panel device 1, provide processed image data RGB, line data start signal (STH), data clock signal (CPH) or data output signal ( TP), and output frame start trigger signal STV, one or more clock signals CLK, reset signal RST, etc. to gate driver 12 and data driver 14 to control gate driver 12 and data driver 14, so that the pixel
  • the array can display the image data RGB progressively or interlaced by, for example, progressive scan or interlaced scan.
  • FIG. 4 is a schematic diagram of a gate driving circuit.
  • the gate driver 12 in FIG. 3 can be implemented as the gate driving circuit shown in FIG. 4 , but is not limited to this gate driving circuit, and can also be other types of gate driving circuits.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units 10 .
  • the input terminals INPUT of the shift register units of other stages are connected to the first output terminals OUTPUT of the shift register units of the previous stage.
  • the reset terminals RESET of the shift register units of other stages are connected to the first output terminal OUTPUT of the shift register unit of the next stage.
  • the input terminal INPUT of the shift register unit of the first stage may be configured to receive the trigger signal STV
  • the reset terminal RESET of the shift register unit of the last stage may be configured to receive the reset signal RST.
  • the shift register units of each stage are configured to output corresponding gate scan signals in response to the clock signal CLK.
  • the clock signal CLK may include, for example, different clock signals CLK1 and CLK2.
  • the timing controller 30 is configured to provide one or more clock signals CLK to the shift register units of each stage, and the timing controller 30 may also be configured to provide a trigger signal STV and a reset signal RST.
  • the timing controller 30 provides two different clock signals to the shift register units at various levels through two clock signal lines.
  • the shift register units at all levels provide four different clock signals, etc., which are not limited in the embodiments of the present disclosure.
  • FIG. 5A shows a circuit structure of an exemplary shift register unit.
  • the shift register units at all levels in the gate drive circuit shown in FIG. 4 can be implemented as the shift register unit circuit shown in FIG. 5A, but is not limited to the structure shown in FIG. 5A, and can also be other types of circuit structures, Embodiments of the present disclosure do not limit this.
  • the shift register unit includes: an input circuit, a pull-up node reset circuit, an output circuit, a pull-down circuit, a pull-down control circuit and an output reset circuit.
  • the input circuit includes a first transistor M1, the gate of the first transistor M1 is connected to the input terminal INPUT of the shift register unit, the first pole is connected to the first voltage terminal VGH (for example, input high level), the second pole is connected to the upper Pull node PU connection.
  • the pull-up node reset circuit includes a second transistor M2 and a third transistor M3, the gate of the second transistor M2 is connected to the reset terminal of the shift register unit, the first pole is connected to the pull-up node PU, the second pole is connected to the second The voltage terminal VGL (for example input low level) is connected; the gate of the third transistor M3 is connected to the pull-down node PD, the first pole is connected to the pull-up node PU, and the second pole is connected to the second voltage terminal VGL.
  • VGL for example input low level
  • the output circuit includes a fourth transistor M4 and a storage capacitor C1, the gate of the fourth transistor M4 is connected to the pull-up node PU, the first pole is connected to the clock signal terminal CLK, and the second pole is connected to the first output terminal of the shift register unit. OUTPUT connection; the storage capacitor C1 is connected in parallel between the gate and the second electrode of the output transistor M4.
  • the pull-down circuit includes a fifth transistor M5 and a sixth transistor M6, the gate of the fifth transistor M5 is connected to the first pull-down control node PD_CN, the first pole is connected to the first voltage terminal VGH, and the second pole is connected to the pull-down node PD.
  • the gate of the sixth transistor M6 is connected to the pull-up node PU, the first pole is connected to the pull-down node PD, and the second pole is connected to the second voltage terminal VGL.
  • the pull-down control circuit includes a seventh transistor M7 and an eighth transistor M8, the gate of the seventh transistor M7 is connected to the first pole and the first voltage terminal VGH, and the second pole of the seventh transistor is connected to the first pull-down control node PD_CN;
  • the gate of the transistor M8 is connected to the pull-up node PU, the first pole is connected to the first pull-down control node PD_CN, and the second pole is connected to the second voltage terminal VGL.
  • the output reset circuit includes a ninth transistor M9, the gate of the ninth transistor M9 is connected to the pull-down node PD, the first pole is connected to the first output terminal OUTPUT, and the second pole is connected to the second voltage terminal VGL.
  • the above-mentioned transistors are all N-type transistors, but embodiments of the present disclosure are not limited to this case.
  • the shift register unit shown in FIG. 5A operates as follows.
  • the clock signal terminal CLK inputs a low level
  • the first voltage terminal VGH inputs a high level (for example, the first voltage terminal can be set to keep inputting a high level signal)
  • the input terminal INPUT inputs a high level
  • the high-level signal is the STV signal
  • the high-level signal is the output of the cascaded upper stage Signal (OUT). Since the input terminal INTPUT inputs a high level, the first transistor M1 is turned on, so that the high level input from the first voltage terminal VGH charges the pull-up node PU, and the potential of the pull-up node PU is charged to the first high level.
  • the seventh transistor M7 is turned on to charge the first pull-down control node PD_CN, so that the fifth transistor M5 is turned on, and the high level input by the first voltage terminal VGH is The pull-down node PD is also charged. Since the pull-up node PU is at the first high level, the sixth transistor M6 and the eighth transistor M8 are turned on, so that the pull-down node PD, the first pull-down control node PD_CN and the second voltage terminal VGL are electrically connected (for example, the second voltage terminal can be set to keep the input low level signal).
  • the seventh transistor M7 and the eighth transistor M8 can be configured (for example, for their size ratio, threshold voltage, etc.) when both M7 and M8 are turned on, the first pull-down control node PD_CN The level of the transistor is pulled down to a low level; similarly, the fifth transistor M5 and the sixth transistor M6 can be configured (for example, for their size ratio, threshold voltage, etc.) to be when both M5 and M6 are turned on, The level of the pull-down node PD is pulled down to a low level, thereby ensuring that the third transistor M3 and the ninth transistor M9 are in a cut-off state at this stage.
  • the fourth transistor M4 Since the pull-up node PU is at the first high level, the fourth transistor M4 is turned on, and the clock signal terminal CLK inputs a low level at this time, so at this stage, the first output terminal OUTPUT outputs the low level signal.
  • the clock signal terminal CLK inputs a high level
  • the first voltage terminal VGH still inputs a high level
  • the input terminal INPUT inputs a low level. Since the input terminal INPUT inputs a low level, the first transistor M1 is turned off, and the pull-up node PU maintains the first high level of the previous stage, so that the fourth transistor M4 remains turned on. level, so the first output terminal OUTPUT outputs a high level signal.
  • the level of the pull-up node PU is further pulled up to reach the second high level, so that the turn-on of the fourth transistor M4 is more sufficient. Since the potential of the pull-up node PU is at a high level, the sixth transistor M6 and the eighth transistor M8 continue to conduct, and respectively pull down the potentials of the pull-down node PD and the first pull-down control node PD_CN to the low level input by the second voltage terminal. flat. Since the potential of the pull-down node PD is at a low level, the third transistor M3 and the ninth transistor M9 are kept in a cut-off state, which will not affect the normal output of the shift signal by the shift register unit.
  • the clock signal terminal CLK inputs a low level
  • the first voltage terminal VGH continues to input a high level
  • the input terminal INPUT continues to input a low level
  • the reset terminal RESET inputs a high level
  • the high-level signal is the RST signal
  • the high-level signal is the output signal (OUTPUT) of the next cascaded stage. Since the reset terminal RESET inputs a high level, the second transistor M2 is turned on, and the potential of the pull-up node PU is pulled down to a low level input by the second voltage terminal VGL, so that the fourth transistor M4 is turned off.
  • the seventh transistor M7 is turned on to charge the first pull-down control node PD_CN, and then the fifth transistor M5 is turned on to charge the pull-down node PD. Since the potential of the pull-up node PU is at a low level, the sixth transistor M6 and the eighth transistor M8 are turned off, the discharge path of the pull-down node PD is turned off, and the pull-down node PD is charged to a high level, thereby making the third transistor M3 and the ninth transistor M9 are turned on, so that the potentials of the pull-up node PU and the first output terminal OUTPUT are respectively pulled down to the low level input by the second voltage terminal VGL, and the first output of the shift register unit is eliminated in the non-output phase. Noise that may be generated at terminal OUTPUT and pull-up node PU.
  • FIG. 5A and FIG. 5B are only an exemplary illustration, and the present disclosure is not limited to the shift register circuit shown in FIG. 5A and the timing diagram shown in FIG. 5B .
  • FIG. 6 is a flowchart of a display driving method provided by an embodiment of the present disclosure.
  • the display driving method may include performing a first display mode using input image data.
  • the first display mode includes the following steps:
  • Step S102 rearranging the input image data to obtain rearranged image data
  • Step S103 generating a first image display control signal and a first delay control signal corresponding to the rearranged image data
  • Step S104 outputting the rearranged image data, the first image display control signal and the first delay control signal.
  • the input image data may include an effective line portion for actual display on the display panel and an invalid line portion for non-actual display on the display panel
  • the rearranged image data may include the effective line portion and the invalid line portion for non-actual display on the display panel.
  • the invalid row part corresponds to the rearranged valid row part and the rearranged invalid row part respectively.
  • the first image display control signal is used for frame display corresponding to the rearrangement of image data during the display operation
  • the first delay control signal is used for triggering the rearrangement of the effective row part during the frame display process
  • first image display control signal is used for frame display corresponding to the rearrangement of image data during the display operation
  • first delay control signal is used for triggering the rearrangement of the effective row part during the frame display process
  • first image display control signal is only used for distinction, not for limitation. Therefore, in an appropriate context, it is also Directly use "image display control signal", “delay control signal” and so on.
  • the display driving method of the embodiments of the present disclosure is applicable to the situation where only part of the row data of the input image is displayed on the display panel, such as a bar-shaped display panel (only part of the picture is displayed instead of the entire full-frame picture), which includes gate A driving circuit, a data driving circuit and a pixel array.
  • the gate driving circuit is used to receive the gate scanning signal to scan the pixel array;
  • the data driving circuit is used to receive the image data signal and provide the image data signal to the pixel array;
  • the data driving circuit receives image data for display operation.
  • the above-mentioned first display mode can enable the bar display used upside down to realize normal square viewing without changing the size specification of the input image data and without changing the scanning direction of the gate drive circuit of the display panel in the opposite direction), thus saving costs and expanding the applicable scenarios of the bar display.
  • the input image can be full-frame, for example, can be a size of 1920*1080 (that is, 1920 columns and 1080 rows); the input image has valid line parts and invalid line parts, for example, the first 360 lines of the input image are the The valid line portion of the input image, while the remaining last 720 lines are the invalid line portion of the input image.
  • the display panel may be a bar-shaped display panel, for example, a bar-shaped display area of 1920*360 (that is, 1920 columns and 360 rows). It should be noted that the embodiments of the present disclosure are not limited to the above-mentioned size of the input image and the above-mentioned size of the display panel.
  • the inverted bar display panel will only display the first 360 lines of the 1920*1080 image, and the remaining 720 lines will not be displayed on the bar display panel, but due to the
  • the shape display panel is, for example, inverted relative to the ground (here as a reference plane), so the viewer standing on the ground also sees an inverted image.
  • upside down, forward direction, etc. are all relative to the ground, but embodiments of the present disclosure are not limited to such scenarios.
  • the input images are rearranged so that the display panel can be used normally without changing the placement state of the display panel.
  • the entire input image may be rearranged upside down, or only the above-mentioned valid line portion may be rearranged upside down.
  • the input image has a valid line portion and an invalid line portion, and correspondingly, the rearranged image includes a rearranged valid line portion and a rearranged invalid line portion.
  • the effective lines of the inverted and rearranged image can be 721 to 1080 lines at the bottom (a total of 360 lines), that is, valid lines corresponding to 1 to 360 lines of the original input image
  • the invalid lines of the inverted rearranged image may be the 1-720 lines at the top, that is, the invalid lines corresponding to the 361-1080 lines of the original image.
  • a first image display control signal and a first delay control signal are generated corresponding to the rearranged image data.
  • the first image display control signal may include various control signals generated corresponding to the above rearranged rearranged image, for example, these control signals may include STH (row data start signal), CPH, etc. for the data driving circuit. (data clock signal), data output signal (TP), etc., can also include STV (frame scan start signal) for the gate drive circuit, CLK signal (clock signal), etc., but the STV signal does not The actual work is only used to set the start time of a frame display, so that the time point when the delay control signal takes effect can be determined.
  • the first delay control signal can be used to generate a scan start signal of the gate drive circuit of the display panel.
  • the first delay control signal (DCI) may be a trigger signal similar to the STV signal, but delayed by a set time compared to the above STV signal.
  • the first delay control signal can be obtained corresponding to the position of the rearranged effective line part in the rearranged image data.
  • the position of the first line of the rearranged effective line part in the rearranged image data is the 721st line, thus The time from scanning the 1st row to the 720th row can be calculated, that is, the time to rearrange the invalid row part to determine the first delay control signal.
  • the rearranged image data, the first image display control signal and the first delay control signal are output to the display panel for display.
  • the first image display control signal is used to perform frame display corresponding to the rearranged image data during the display operation
  • the first delay control signal is used to trigger the rearrangement of valid lines during the frame display process part of the row scanning process in the display panel.
  • the first image display control signal can be normally generated and output, but it is in an inactive state before the arrival of the first delay control signal, that is, it is not actually provided to the display panel, or, at least
  • the STV frame scanning start signal
  • the gate driving circuit of the display panel does not output the gate scanning signal, so the display operation is not actually performed;
  • the image display control signal is actually applied to the frame display of the display panel.
  • the gate drive circuit of the display panel is triggered by the first delay control signal to start
  • the gate scanning signal is generated according to the timing signal, and the data driving circuit of the display panel synchronously outputs the data signal to realize, for example, progressive display or interlaced display.
  • the CLK signal may be provided to the gate driving circuit of the display panel during the delay interval generated by rearranging image data (corresponding to the rearrangement invalid line part of rearrangement image data).
  • the CLK signal is not actually supplied to the gate driving circuit of the display panel or is not actually generated during the delay period of rearranging the image data (corresponding to the rearrangement invalid row portion of the rearranged image data).
  • the reverse rearranged image data (that is, the image data of the rearranged image), the first image display control signal and the first delay control signal can be output at the same time, but the rearrangement effective row part displayed by the display panel is at the first Line scanning is performed under the trigger of a delay control signal (for example, another signal similar to the STV signal).
  • a delay control signal for example, another signal similar to the STV signal.
  • the first row of the effective row part is rearranged to the 721st row in the rearranged image data, so the first row displayed in the first image
  • the start time of the control signal i.e.
  • the first delay control signal triggers the gate drive circuit of the display panel, by
  • the gate drive circuit starts to output the gate scan signal sequentially from each output port OUT1 (corresponding to the actual first line of the display panel) to OUT360 (corresponding to the actual 360th line of the display panel), and at the same time the data drive circuit starts to sequentially
  • the image data is output by row, so that the rearranged effective row part (ie, the 721st to 1080th row) of the rearranged image data is output and displayed on the display panel (for this, refer to FIG. 7C which will be described later).
  • the gate circuit of the display panel outputs the gate scan signal one by one in the order from the output port OUT1 to OUT360, synchronously, the data driving circuit will rearrange the effective row part from the 721st row
  • the image data is output line by line in order to the 1080th line, thereby realizing display.
  • the 360th line (corresponding to the 721st line of the rearrangement valid part) of the effective line part of the input image data is displayed first, and the 1st line of the valid line part of the input image data (corresponding to the 1080th line of the rearrangement valid part ) is displayed last, therefore, for the display panel itself, the effective line portion of the input image data is displayed in an inverted manner, but for a viewer standing on the ground and looking at the display panel inverted relative to the ground, the viewer sees The image being played.
  • the above display driving method may further include step S101 and/or step S105.
  • step S101 input image data is received, and the input image data is received for subsequent processing.
  • the input image may be, for example, input image data from a modem received by the modem, for example, over a wired or wireless network.
  • the input image data can be a static image, a dynamic image, or a video.
  • the input image may be, for example, a storage device understood by the display device itself.
  • the storage device may be a hard disk (mechanical hard disk or solid state disk), or a pluggable storage device such as a U disk.
  • step S105 the input image data is stored, for example, but not limited to a volatile storage method or a non-volatile storage method to store the input image data, so as to perform subsequent image data processing.
  • the technical problem of inversion of the picture displayed on the strip-shaped display can be solved when the bar-shaped display is used upside down, so that the image data input can be processed on the client side of the above-mentioned system without inversion processing.
  • the strip display can still normally display the technical effect of the input image, and also improves the versatility and compatibility of the strip display.
  • FIG. 8 is a flowchart of a display driving method provided by another embodiment of the present disclosure. As shown in FIG. 8, for example, on the basis of the display control method shown in FIG. 6, the display control method may further include:
  • Step S202 acquiring a display control instruction
  • Step S203 in response to the display control instruction, select to perform the first display mode or to perform the second display mode.
  • the display control method may include two display modes, namely a first display mode and a second display mode.
  • the display driving method described in the above embodiments corresponds to the first display mode, using the rearranged image data, the first image display control signal and the first delay control signal to perform display operation on the display panel, and in the In the first display mode, the display panel is placed upside down, for example, relative to its normal placement reference pointing, the display panel is installed upside down.
  • the display operation is performed on the display panel using the input image data and the second image display control signal.
  • the display panel is placed forward, that is, according to its normal placement Reference points for placement or installation.
  • the display driving method of this embodiment includes:
  • Step S221 corresponding to the input image data, generating the second image display control signal
  • Step S222 outputting the input image data and the second image display control signal.
  • the display control instruction is obtained, for example, the input port of the display system to which the display panel belongs may be read, and the display control instruction is obtained according to different states of the input port.
  • the display control instruction may be obtained when the input image data is received, or may be obtained at other times, such as after the input image is received.
  • the input port can be a certain pin (pin) or switch of the display device. If the pin or switch is set to high (H), it means that the first display mode is used, and it is set to low (L). , it means to use the second display mode.
  • the input port communicates (for example, directly connects) with a sensing element (eg, gravity sensing element), and the sensing element can sense the orientation of the display panel relative to a preset direction (eg, gravity direction).
  • a sensing element eg, gravity sensing element
  • the sensing element can sense the orientation of the display panel relative to a preset direction (eg, gravity direction).
  • a preset direction eg, gravity direction
  • the sensor output is high (H), indicating that the second display mode is used
  • the sensor output is Low (L)
  • the gravity sensing element is, for example, a switch that uses gravity to open and close. For example, when it is placed upright, it is closed due to the gravity of the switch blade itself, and when it is reversed, it is opened due to the gravity of the switch blade itself.
  • the display control instruction may be executable instruction data for judging whether to select the first display mode or the second display mode, for example, it may be the first executable code representing the first display mode, such as instruction code code1;
  • the second executable code of the display mode such as instruction code code2.
  • step S203 in response to the display control instruction, the first executable code or the second executable code is selected to be executed, thereby selecting to perform the first display mode or the second display mode.
  • the first display mode is selected
  • the instruction code code2 is received
  • the second display mode is selected.
  • the first executable code and the second executable code can be stored in the storage device, so as to be called by the system and executed by the processor, so as to perform the operation in the first display mode or the operation in the second display mode accordingly .
  • the second image display control signal is generated corresponding to the input image data.
  • the second image display control signal may be used for frame display corresponding to the input image data during the display operation.
  • step S222 the input image data and the second image display control signal are output, and the input image data and the second image display control signal may be directly output to the output circuit without image inversion processing and delay processing, so as to
  • the display panel performs normal display operations to realize the second display mode, for example, the display mode in the forward placement state when the display panel is in normal use.
  • the second image display control signal and the above-mentioned first image display control signal are similar, that is, they have the same STV, CLK, STH, CPH, TP, etc.
  • the difference between the two is that the first image display control signal cooperates with the first delay control signal. At the beginning, it does not directly drive the display panel but only drives the gate drive circuit of the display panel to display when there is the first delay control signal.
  • delay driving the gate drive circuit of the display panel, so as to achieve the effect of delayed display, and the second image display control signal may not have a corresponding delay control signal, so the gate drive circuit of the display panel can be directly driven from the beginning Displaying is performed, that is, the STV included in the second image display control signal is applied to the gate driving circuit of the display panel from the beginning, so that the gate driving circuit sequentially generates gate scanning signals.
  • the effective line portion of the input image is the 1st line to the 360th line
  • the second image display control signal used to display the input image on the display panel it is to drive the gate drive circuit of the display panel at the beginning. show.
  • the input image data is 1920*1080
  • the effective line part is from the 281st line to the 720th line, that is, including the roughly middle part of the input image; correspondingly, the inverted
  • the rearranged image data is also 1920*1080, and the effective rearrangement part is from the 361st to the 800th row in the rearranged image.
  • the first image display control signal is generated based on the rearranged image data and includes a first delay control signal delayed by 360 line scan times, so that the inverted image display can be realized in the inverted display panel;
  • a second image display control signal is generated based on the input image data and includes a second delay control signal delayed by 280 line scan times, so that the forward image display can be realized in the display panel being placed. Therefore, for the case where the effective line portion is located in the middle of the input image, in the second display mode, a corresponding delay control signal also needs to be added to the input image data that has not been rearranged.
  • Fig. 9 is a schematic diagram of a display driving device provided by at least some embodiments of the present disclosure.
  • the display driving device can be used to implement the display driving method shown in FIG. 6 .
  • the display driving device 100 may include: an image processing module 101 , a timing generation module 102 , a delay processing module 103 , an output circuit 104 , an input port 105 and a first storage device 106 .
  • the display control device may be at least partially implemented in the form of a TCON chip, for example, the TCON chip includes the above-mentioned image processing module 101, timing generation module 102, delay processing module 103, output circuit 104, for example, the first storage device 206 It can be inside the TCON chip, or outside the TCON chip, but on the same printed circuit board, so that the two are connected through a bus.
  • the display control device may also be implemented as a combination of a CPU and a memory, or may be implemented as a form of SoC, FPGA, ASIC, etc.
  • the embodiment of the present disclosure does not limit the implementation of the display control device.
  • the image processing module 101 , the timing generation module 102 , the delay processing module 103 , the output circuit 104 , etc. can be arbitrarily combined in one or more circuit devices or components.
  • the image processing module 101 may be used to rearrange the received input image data to obtain rearranged image data.
  • the image processing module 101 may include an image data rearrangement circuit, and the image data rearrangement circuit may be used to perform an overall inverse rearrangement operation on the input image data, for example, perform an inverse rearrangement on the entire 1920*1080, or In some examples, the rearrangement operation may only be performed on the effective line portion, for example, only the 1920*360 effective line portion is reversely rearranged to obtain the rearranged image data.
  • the timing generation module 102 can be used to generate the first image display control signal corresponding to the rearranged image data (the number of rows and columns of the image) and considering the display refresh rate of the display panel, such as for the data driving circuit STH (line data start signal), CPH (data clock signal), etc.
  • the first image display control signal may also include STV (frame scanning start signal), CLK signal (clock signal) and the like for the gate drive circuit, wherein the first image display control signal is used for the display operation process During the frame display corresponding to the rearranged image data, the STV signal does not actually work during the scanning process but is only used to set the start time of a frame display, so that the time point at which the delay control signal takes effect can be determined. For example, when the display panel is performing image display, the rearranged image data will be displayed according to the first image display control signal.
  • the delay processing module 103 is used to generate a first delay control signal corresponding to the rearrangement of image data, for example, the first delay control signal is used to trigger the rearrangement to be valid during the frame display process.
  • the row scanning process of the row portion in the display panel for example, triggers the process of correctly displaying the rearranged image data according to the first image display control signal when the display panel is displaying images.
  • the first delay control signal is obtained according to the position of the rearranged effective line portion in the rearranged image data, or the first delay control signal is obtained by preset.
  • preset can be the output time of the delay control signal preset in the system, for example, it can be fixed and preset (for example, written in the system and cannot be changed), or it can be preset by the user according to needs or Preset according to system board instructions.
  • the delay processing module 103 may include a gate signal timing adjustment module, and the gate signal timing adjustment module may be used to set the first delay control signal later than the STV signal included in the first image display control signal A predetermined time, the predetermined time is obtained according to the position of the rearranged effective line part in the rearranged image data, or the predetermined time is obtained by preset.
  • the "preset" here may mean that the predetermined time is preset in the system, for example, it can be fixed and preset (for example, written in the system and cannot be changed), or it can be preset by the user according to needs or Preset according to system board instructions.
  • the delay processing module 103 can also be used to implement a delay control mode.
  • the above delay control mode can be that the delay processing module 103 corresponds to rearranging the number of data rows (N_Dummy) of the invalid row part and rearranging The number of data rows (N_Active) of the valid row part is calculated respectively to calculate the delay time T1 corresponding to the rearrangement of the invalid row part and the working time T2 corresponding to the rearrangement of the valid part.
  • the data drive circuit always outputs the rearranged image data of the full frame, such as 1920*1080, line by line normally. During the T1 time interval, no STV signal is applied to the gate drive circuit, and the delay processing module 103 does not send a signal to the gate drive.
  • the scan start signal STV is issued, so in the T1 time interval, the gate driver does not generate a gate output signal, such as the GOUT signal; in the T2 time interval, for example, at the junction of the T1 time interval and the T2 time interval, such as the first At the time point corresponding to the 720 rows of data, the delay processing module 103 starts to send a trigger signal (DCI) similar to the scan start signal STV to the gate driver, so within the T2 time interval, the gate driver starts to generate gate
  • DCI trigger signal
  • the pole scanning signal such as the GOUT signal, starts to display the rearranged effective line part on the display panel line by line from the 721st line of the rearranged image data.
  • the output circuit 104 communicates with the display panel, and is used to output the rearranged image data, the first image display control signal and the first delay control signal to the display panel, so that the display panel displays operate.
  • the input port 105 can be used to obtain input image data, or, in some examples, can also be used to obtain other signals related to displaying input image data, such as a display mode control command signal and the like.
  • the input port 105 is, for example, a port of an input circuit, and the input circuit may be, for example, a modem or a USB drive circuit.
  • an input port includes a pin or switch that, if set high (H), indicates that the first display mode is used, and that is set low (L), indicates that the second display mode is used. display mode.
  • the first storage device 106 can be used for temporary or long-term storage of the input image data, for example, by temporarily storing the input image data to facilitate subsequent image processing operations, for example, when the input port 105 cannot stably acquire the input image in real time at high speed , the input image data is stored in the memory in advance to realize the cache function.
  • the first storage device 106 may be, for example, a semiconductor storage device.
  • the above-mentioned display driving device can make the conventional input image appear to the viewer standing on the ground on the bar-shaped screen used upside down (relative to the ground, for example) without changing the way the system client provides the input image data. is normally displayed, thereby improving the compatibility of the display panel.
  • FIG. 10 is a schematic diagram of a display driving device provided by another embodiment of the present disclosure.
  • the display driving device 200 shown in FIG. 10 can add a control device 207 and a second storage device 208 on the basis of the display driving device 100 shown in FIG. 9 .
  • the timing generation module 202 can also be used to directly generate a second image display control signal corresponding to the input image data, for example, the second image display control signal can be used to correspond to the input image during the display operation.
  • the data is displayed in a frame, for example, when the display panel is performing image display, the input image data is correctly displayed according to the second image display control signal, for example, the second image display control signal includes STV, CLK, etc. generated corresponding to the input image Signal to control the display panel for display operation.
  • control device 207 can be used to select to perform the above-mentioned first display mode or to perform the second display mode according to the display control instruction.
  • executable codes code1 and code2 respectively corresponding to the first display mode and the second display mode are stored in the second storage device.
  • the display control instruction received by the control device 207 is to perform the first display mode
  • code1 is called from the storage device and executed, thereby entering the first display mode, so that the image processing module 201 rearranges the input image And obtain the rearranged image data
  • the delay processing module 203 generates the first delay control signal corresponding to the rearranged image data
  • the timing generation module 202 generates the first image display control signal corresponding to the rearranged image data
  • the output circuit 204 generates the above-mentioned
  • the rearranged image data, the first delay control signal, and the first image display control signal are output to the display panel for display in the first display mode.
  • the output circuit 204 can also be used to output the input image data and the second image display control signal for performing the display operation in the second display mode on the display panel.
  • the display control instruction received by the control device 207 is to perform the second display mode
  • code2 is called from the storage device and executed, thereby selecting the second display mode, and the image processing module does not rearrange the input image
  • the timing generation module 202 generates a second image display control signal corresponding to the input image data, and then the output circuit 204 outputs the input image data and the second image display control signal to the display panel for display in the second display mode.
  • the second storage device 208 may be used to store a first executable code (code1) corresponding to the first display mode and a second executable code (code2) corresponding to the second display mode, respectively.
  • the control device 207 may read the corresponding code from the second storage device 208 to determine the corresponding display mode.
  • the second storage device 208 can be a semiconductor storage device, such as EEPROM or flash memory (Flash), and is connected to a control device, an image processing module, etc., for example, through an I2C bus.
  • the above-mentioned display control device can realize multiple display modes according to the user's selection, so that no matter whether the bar-shaped display panel is placed or installed normally or upside down, the user can easily and conveniently switch between different display modes according to the needs of normal display. .
  • FIG. 7A is an exemplary input image.
  • the input image acquired from the input port is, for example, an image with a size of 1920*1080.
  • the upper striped area in FIG. 7A may be, for example, the area normally displayed by the 1920*360 striped display panel (effective row portion), and the lower blank area is an area not required to be normally displayed (invalid row portion).
  • the image in FIG. 7A can be rearranged through the above-mentioned image processing module, for example, it can be turned upside down according to the actual situation.
  • the present disclosure does not limit the specific rearrangement manner.
  • the input image can be reversed and rearranged upside down to obtain the rearranged rearranged image shown in FIG.
  • the part of 360 lines appears in the lower part of Figure 7B after inversion and rearrangement, and becomes the rearranged effective line part, such as the last 360 lines, and the invalid line part in the lower part of Figure 7A, such as the last 720 lines, appears after inversion and rearrangement
  • the upper part of FIG. 7B there is a rearrangement invalid line portion such as the first 720 line portions.
  • FIG. 7C is a processing sequence diagram corresponding to the display driving method of rearranging image data in FIG. 7B.
  • the first image display control signal generated corresponding to the rearranged image data shown in FIG. 7B includes STV and CLK1, CLK2, ..., CLK6 (more CLKs may be included as required) etc.
  • the first image display control signal may not include the STV signal; at the start point of the time period corresponding to the rearrangement of the effective row portion, a delay control signal (DCI) similar to the STV signal is provided to the gate drive circuit of the display panel, Thus, the gate driving circuit of the display panel starts to output gate scanning signals in sequence.
  • DCI delay control signal
  • H in the figure represents the actual turn-on time allocated for each row of gate lines
  • the period of each CLK signal (CLK1, CLK2, ..., CLK6) is 6H
  • the corresponding high-level phase is 3H
  • the high-level phase of the gate scanning signals OUT1, OUT2, OUT3, . . . etc. generated thereby is also 3H.
  • the STV signal and/or the DCI signal are periodic signals whose frequency is equal to the display refresh frequency of the display panel, for example, the STV signal and/or the DCI signal can be obtained by dividing the frequency of the system clock signal, and
  • the delay of the DCI signal relative to the STV signal is realized by, for example, a counting circuit driven by CLK, or, in the case of no STV signal being generated, the delay relative to the start time of preset frame display.
  • the timing control signals such as CLK and STV may be inactive, so the gate scanning signals such as OUT1, OUT2, OUT3, . . . of each output terminal of the gate driver may also be inactive.
  • the delay control signal (DCI) is applied to the input terminal of the first shift register of the gate drive circuit, whereby the gate drive circuit starts to work to sequentially generate gate scan signals OUT1, OUT2, OUT3, ..., etc., each gate scanning signal corresponds to one row of image data, and correspondingly, the data driving circuit outputs image data signals corresponding to the 721st row to the 1080th row.
  • the effective stages of the gate scanning signals OUT1, OUT2, OUT3, ... etc. after the delay control signal generally correspond to the rearrangement of image data
  • the rearranged valid line portion of In this interval, the display panel starts to work, and the rearranged effective line part can be normally displayed on the inverted strip display panel, so that the upper effective line part of the original input image is located at the lower part of the rearranged image data after being inverted and rearranged , after delaying the rearrangement of the image data, the lower part of the rearranged effective row will be displayed on the inverted bar display panel. Since the bar display panel is placed upside down, the final result will be the inverted rearranged image again. Come over so that the display effect can be an upright image.
  • the above process can achieve normal display on display panels with different placement methods by rearranging the input image data and delaying the corresponding rearranged image data without changing the way the existing system client provides image data.
  • the input image data can achieve normal display on display panels with different placement methods by rearranging the input image data and delaying the corresponding rearranged image data without changing the way the existing system client provides image data.
  • Fig. 11 is a schematic diagram of a display device provided by at least some embodiments of the present disclosure.
  • the display device 300 includes any display control device 310 provided by the embodiments of the present disclosure, and the display control device 310 may, for example, The time limit is the timing control circuit (TCON).
  • the display device 300 includes a display panel 330, and the display panel 330 includes a pixel array composed of a plurality of pixel units.
  • the display device 300 may further include a data driving circuit 320 and a gate driving circuit 340 .
  • the data driving circuit 320 is used for providing data signals to the pixel array; the gate driving circuit 340 is used for receiving the scanning control signal to provide the gate scanning signal to the pixel array.
  • the display control device 310 is electrically connected to the data drive circuit 320 through the signal line 312, the display control device 310 is electrically connected to the gate drive circuit 340 through the signal line 311, the data drive circuit 320 is electrically connected to the pixel unit through the data line 321, and the gate drive The circuit 340 is electrically connected to the pixel unit through the gate line 341 .
  • using the display device 300 upside down refers to keeping the light emitting direction of the display device 300 unchanged, and rotating the display device 300 by 180°.
  • the display device 300 is suspended from the ground, the light emitting direction of the light emitting surface is parallel to the ground, the data driving circuit 320 is located on the sky side and/or the ground side of the display device 300, and the gate driving circuit 340 is located on the sky side and/or the ground side of the display device 300. to the left and/or right of the .
  • the display device 300 is suspended and used, the light emitting direction of the light emitting surface is parallel to the ground.
  • the display device 300 can realize upright display of images when used upside down.
  • the display device 300 can be a strip display, and its display area includes a long side and a short side; wherein, the data driving circuit 320 can be located on the long side, and the gate driving circuit 340 can be located on the short side, preferably , the gate driving circuit 340 may be a GOA driving circuit.
  • the bar display can realize the upright display of the image when it is used upside down.
  • using the display device 300 upside down refers to keeping the light emitting direction of the display device 300 unchanged, and rotating the display device 300 by 180°.
  • the light output direction of the light output surface is a direction parallel to the ground
  • the grid lines 341 are arranged parallel to the ground
  • the extension direction of the data lines 321 can be the direction where the ground intersects (for example, the data lines 321 perpendicular to the ground).
  • the display device 300 can realize upright display of images when used upside down.
  • the display device 300 may be a strip display, and its display area includes a long side and a short side; wherein, the gate line 341 may extend along a direction parallel to the long side, and the data line 321 may extend along a direction parallel to the short side.
  • the sides extend parallel to each other.
  • the bar display can realize the upright display of the image when it is used upside down.
  • the display panel 330 can be, for example, a liquid crystal display panel, an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, an electronic paper display panel, a plasma display panel, etc., which are not limited in embodiments of the present disclosure.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the display device in this embodiment can be: any device with a display function such as a liquid crystal panel, a liquid crystal TV, a monitor, an OLED panel, an OLED TV, electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. products or components.
  • the display device may also include other conventional components such as a display panel, which is not limited in the embodiments of the present disclosure.

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Abstract

本公开提供了一种显示控制方法、显示控制装置和显示装置。该显示控制方法包括，使用输入图像数据执行第一显示模式。第一显示模式包括：将输入图像数据进行重排得到重排图像数据，其中，输入图像数据包括用于在显示面板上实际显示的有效行部分和用于在显示面板上非实际显示的无效行部分，重排图像数据包括与有效行部分和无效行部分分别对应的重排有效行部分和重排无效行部分；对应重排图像数据，产生第一图像显示控制信号和第一延时控制信号；输出重排图像数据、第一图像显示控制信号和第一延时控制信号，用于在显示面板进行显示操作。该显示控制方法可以增加显示器的适用场景，节省成本。

Description

显示控制方法、显示控制装置和显示装置 技术领域
本公开涉及一种显示控制方法、显示控制装置和显示装置。
背景技术
当前，随着例如室外或室内广告业务的发展，大量的屏幕被广泛应用，而长条形屏幕作为广告展示屏幕的一种被广泛使用。另外，当前屏幕使用场景也变得丰富，拼接屏、电子白板、反射式显示屏等多元化的屏幕形态逐渐出现。
发明内容
本公开至少一些实施例提供一种显示控制方法，包括，使用输入图像数据执行第一显示模式，其中，所述第一显示模式，包括：将所述输入图像数据进行重排得到重排图像数据，其中，所述输入图像数据包括用于在显示面板上实际显示的有效行部分和用于在所述显示面板上非实际显示的无效行部分，所述重排图像数据包括与所述有效行部分和无效行部分分别对应的重排有效行部分和重排无效行部分；对应所述重排图像数据，产生第一图像显示控制信号和第一延时控制信号；输出所述重排图像数据、所述第一图像显示控制信号和所述第一延时控制信号，用于在所述显示面板进行显示操作，其中，所述第一图像显示控制信号用于在所述显示操作过程中对应于所述重排图像数据进行帧显示，所述第一延时控制信号用于在所述帧显示的过程中触发用于所述重排有效行部分在所述显示面板中的行扫描过程。
例如，在本公开至少一些实施例提供的显示控制方法中，将所述输入图像数据进行重排得到所述重排图像数据，包括：将所述输入图像数据进行整体倒置重排操作，以得到所述重排图像数据，其中，所述第一延时控制信号根据所述重排有效行部分在所述重排图像数据中的位置得到，或者所述第一延时控制信号通过预设得到。
例如，本公开至少一些实施例提供的显示控制方法还包括：获取显示控制指令；响应于所述显示控制指令，选择进行所述第一显示模式或进行第二 显示模式，其中，所述第二显示模式不同于所述第一显示模式。
例如，在本公开至少一些实施例提供一种显示控制方法中，所述第二显示模式包括：对应所述输入图像数据，产生所述第二图像显示控制信号，其中，所述第二图像显示控制信号用于在所述显示操作过程中对应于所述输入图像数据进行帧显示；输出所述输入图像数据和所述第二图像显示控制信号，用于在所述显示面板进行显示操作。
例如，在本公开至少一些实施例提供的显示控制方法中，获取所述显示控制指令，包括：读取所述显示面板所属的显示系统的输入端口，根据所述输入端口的不同状态来获取所述显示控制指令。
例如，在本公开至少一些实施例提供的显示控制方法中，所述显示系统包括分别对应于所述第一显示模式的第一可执行代码和对应于所述第二显示模式的第二可执行代码，响应于所述显示控制指令指示，选择进行所述第一显示模式或进行所述第二显示模式，包括：根据所述显示控制指令，选择执行所述第一可执行代码或第二可执行代码。
例如，在本公开至少一些实施例提供的显示控制方法中，在所述第一显示模式之中，所述显示面板相对于参照位置处于倒置状态；所述第二显示模式之中，所述显示面板相对于所述参照位置处于正放状态。
例如，在本公开至少一些实施例提供的显示控制方法中，所述显示面板包括用于实现所述行扫描过程的栅极驱动电路，所述第一延时控制信号用于产生所述栅极驱动电路的扫描起始信号。
例如，本公开至少一些实施例提供的显示控制方法还包括：接收并存储所述输入图像数据。
本公开至少一些实施例提供一种显示控制装置，包括：图像处理模块、时序产生模块、延时处理模块和输出电路。所述图像处理模块被配置为，将接收到的输入图像数据进行重排得到重排图像数据，其中，所述输入图像数据包括用于在显示面板上实际显示的有效行部分和用于在所述显示面板上非实际显示的无效行部分，所述重排图像数据包括与所述有效行部分和无效行部分分别对应的重排有效行部分和重排无效行部分；所述时序产生模块被配置为，对应所述重排图像数据，产生第一图像显示控制信号，其中，所述第一图像显示控制信号用于在所述显示操作过程中对应于所述重排图像数据进行帧显示；所述延时处理模块被配置为，对应所述重排图像数据，产生 第一延时控制信号，其中，所述第一延时控制信号用于在所述帧显示的过程中触发用于所述重排有效行部分在所述显示面板中的行扫描过程；所述输出电路被配置为，输出所述重排图像数据、所述第一图像显示控制信号和所述第一延时控制信号，用于在所述显示面板进行显示操作。
例如，在本公开至少一些实施例提供的显示控制装置中，所述图像处理模块包括图像数据重排电路，其中，所述图像数据重排电路被配置为将所述输入图像数据进行整体倒置重排操作，以得到所述重排图像数据。
例如，在本公开至少一些实施例提供的显示控制装置中，所述第一延时控制信号根据所述重排有效行部分在所述重排图像数据中的位置得到，或者所述第一延时控制信号通过预设得到。
例如，在本公开至少一些实施例提供的显示控制装置中，所述延时处理模块包括栅信号时序调整模块，其中，所述栅信号时序调整模块被配置为，将所述第一延时控制信号设置得晚于所述第一图像显示控制信号预定时间，所述预定时间根据所述重排有效行部分在所述重排图像数据中的位置得到，或者所述预定时间通过所述预设得到。
例如，本公开至少一些实施例提供的显示控制装置还包括控制装置，其中，所述控制装置被配置为，响应于显示控制指令，选择进行所述第一显示模式或进行第二显示模式，其中，所述第二显示模式不同于所述第一显示模式，所述第一显示模式包括使用所述重排图像数据、所述图像显示控制信号和所述第一延时控制信号，在所述显示面板进行显示操作。
例如，在本公开至少一些实施例提供一种显示控制装置中，所述时序产生模块还被配置为，对应所述输入图像数据，产生第二图像显示控制信号，其中，所述第二图像显示控制信号用于在所述显示操作过程中对应于所述输入图像数据进行帧显示；所述第二显示模式包括使用所述输入图像数据和所述图像显示控制信号，在所述显示面板进行显示操作；所述输出电路还被配置为，输出所述输入图像数据和所述第二图像显示控制信号，用于在所述显示面板进行所述第二显示模式的显示操作。
例如，本公开至少一些实施例提供的显示控制装置还包括：第二存储装置，其中，所述第二存储装置被配置为存储分别对应于所述第一显示模式的第一可执行代码和对应于所述第二显示模式的第二可执行代码，所述显示控制装置还被配置为，响应于所述显示控制指令指示，根据所述显示控制指令， 选择执行所述第一可执行代码或第二可执行代码。
例如，本公开至少一些实施例提供的显示控制装置还包括输入端口，其中，所述输入端口被配置为根据所述输入端口的不同状态来获取所述显示控制指令。
例如，本公开至少一些实施例提供的显示控制装置还包括第一存储装置，其中，所述第一存储装置被配置为用于存储接收到的所述输入图像数据。
本公开至少一些实施例还提供一种显示装置，包括：上述任一的显示控制装置以及显示面板。
例如，在本公开至少一些实施例提供的显示装置中，所述显示面板包括栅极驱动电路、数据驱动电路和像素阵列。所述栅极驱动电路配置为接收扫描控制信号对所述像素阵列进行扫描；所述数据驱动电路配置为接收图像数据信号并将所述图像数据信号提供给所述像素阵列；所述像素阵列配置为在所述栅极驱动电路的控制下从所述数据驱动电路接收所述图像数据以进行显示操作。所述第一图像显示控制信号包括所述扫描控制信号，所述图像数据信号包括所述重排图像数据。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是一种条形显示器的显示过程的示意图；
图2是一种倒置的条形显示器的显示过程的示意图；
图3是一种显示面板装置的结构示意图；
图4是一种栅极驱动电路的示意图；
图5A是一种移位寄存器的结构示意图；
图5B是图5A中的移位寄存器的时序图；
图6是本公开实施例提供的一种显示驱动方法的流程图；
图7A是一种示例性的输入图像；
图7B是将图7A的输入图像经过重排后的重排图像；
图7C是本公开实施例提供的显示驱动方法的延时处理时序图；
图8是本公开另一实施例提供的显示驱动方法的流程图；
图9是本公开实施例提供的显示驱动装置的示意图；
图10是本公开另一实施例提供的一种显示驱动装置的示意图；以及
图11是本公开实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部(元)件的详细说明。当本公开实施例的任一部(元)件在一个以上的附图中出现时，该部(元)件在每个附图中由相同或类似的参考标号表示。
当前的显示器驱动方式下，对于长条形显示器(或显示屏幕)的输入图像数据通常仍然是全画幅规格的。该全画幅规格例如包括标清(480*320、640*480)、高清(1024*720p、1920*1080i)、全高清(1920*1080p)、超高清(3840*2160、7680*4320)等。
图1是一种条形显示器的显示过程的示意图。如图1所示，输入到显示该条形显示器的输入图像数据可以是从存储装置(例如硬盘)获取或从接收装置(例如调制解调器)接收的，例如，该输入图像数据可以是1920*1080 的大小。该条形显示器的分辨率例如为1920*360，包含定时控制器(Timing Controller,TCON)。输入图像数据在列方向的尺寸(即行数)大于条形显示器实际显示的图像在列方向的尺寸，因此输入图像数据仅有一部分在条形显示器中显示，这部分可以被称为有效行部分，其余的则是无效行部分。然而，需要指出的是，“无效行部分”也可以具有实质的图像内容，本公开的实施例对此不作限制。例如，该无效行部分可以是用于其他显示面板上显示的有效行部分。例如，对于拼接屏而言，不同的有效行部分可以在拼接屏上拼接成完整的图像，对于拼接屏的一个拼接单元的显示面板来说，其对应的无效部分可以是其他拼接单元的显示面板的有效部分。
例如，该定时控制器对应该输入图像数据，生成控制显示面板根据该输入图像数据进行显示的时序控制信号。TCON将输入图像数据以及生成的时序控制信号提供至条形显示器，该条形显示器根据该时序控制信号和该输入图像数据进行显示。例如，输入图像数据的前360行为有效行部分(图中向上箭头指代部分)，可以通过该条形显示器正常显示，而剩余的第361至第1080行(共720行)的无效行部分则不会显示在该条形显示器上(在图中以虚线部分表示)。并且，对应于无效行部分的时序控制信号将不会实际驱动该条形显示器，在对应的时间段内，该条形显示器没有被刷新而是保持显示前述有效行部分对应的图像部分。
图2是一种倒置的条形显示器的显示过程的示意图。与图1相比，图2的区别仅在于该条形显示器是倒置放置，例如，该条形显示器的安装过程中被无意地倒置，或者某些应用场景中，该条形显示器根据使用需要，被有意地倒置。例如，该条形显示器的栅极驱动器的栅极信号扫描方向是固定的，如果在倒置的情况下使用该条形显示器，则该条形显示器上显示的画面就会出现倒置的情况，如图2所示。此时，如果在上述条形显示中输入倒置的图像数据，该条形显示器中将显示的原输入图像数据中的无效行部分，则不能实现正常显示。
图3是一种显示面板装置的结构示意图。例如，图1或图2中的条形显示器中的显示面板可以如图3所示。如图3所示，显示面板装置1包括阵列基板11、栅极驱动器12、定时控制器13和数据驱动器14，阵列基板11与栅极驱动器12、定时控制器13和数据驱动器14电连接。该阵列基板11包括像素阵列，所述像素阵列包括多行和多列像素单元，每个像素单元用于实 现一个子像素的显示，该阵列基板11还包括多条扫描线GL和多条数据线DL，多条扫描线GL分别为多行像素单元提供栅信号，多条数据线DL分别为多行像素单元提供数据信号。栅极驱动器12与多条扫描线GL连接，用于提供栅极扫描信号以驱动多条扫描线GL。数据驱动器14与多条数据线DL连接，用于提供数据信号以驱动多条数据线DL。定时控制器13用于处理从显示面板装置1外部输入的图像数据RGB、向数据驱动器14提供处理的图像数据RGB、行数据起始信号(STH)、数据时钟信号(CPH)或数据输出信号(TP)，以及向栅极驱动器12和数据驱动器14输出帧起始触发信号STV、一个或多个时钟信号CLK、复位信号RST等，以对栅极驱动器12和数据驱动器14进行控制，从而使得像素阵列可以通过例如逐行扫描或隔行扫描的方式逐行或隔行显示图像数据RGB。
图4是一种栅极驱动电路的示意图。图3中的栅极驱动器12可以实施为图4所示的栅极驱动电路，但不限于这种栅极驱动电路，还可以为其他类型的栅极驱动电路。
如图4所示，该栅极驱动电路20包括多个级联的移位寄存器单元10。如图4所示，除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端INPUT和上一级移位寄存器单元的第一输出端OUTPUT连接。除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端RESET和下一级移位寄存器单元的第一输出端OUTPUT连接。例如，第一级移位寄存器单元的输入端INPUT可以被配置为接收触发信号STV，最后一级移位寄存器单元的复位端RESET可以被配置为接收复位信号RST。
如图4所示，各级移位寄存器单元被配置为响应于时钟信号CLK输出相应的栅极扫描信号。时钟信号CLK例如可以包括不同的时钟信号CLK1和CLK2。定时控制器30被配置为向各级移位寄存器单元提供一个或多个时钟信号CLK，定时控制器30还可以被配置为提供触发信号STV和复位信号RST。在图4中，定时控制器30过两条时钟信号线向各级移位寄存器单元提供两个不同的时钟信号，在其他情形中，定时控制器30也可以被配置为通过四条时钟信号线向各级移位寄存器单元提供四个不同的时钟信号等，本公开的实施例对此不作限定。
图5A示出了一种示例性移位寄存器单元的电路结构。图4所示的栅极驱动电路中的各级移位寄存器单元可以实施为图5A所示的移位寄存器单元 电路，但不限于图5A所示的结构，还可以为其他类型的电路结构，本公开的实施例对此不作限定。
如图5A所示，该移位寄存器单元包括：输入电路、上拉节点复位电路、输出电路、下拉电路、下拉控制电路以及输出复位电路。
该输入电路包括第一晶体管M1，第一晶体管M1的栅极和移位寄存器单元的输入端INPUT连接，第一极和第一电压端VGH(例如输入高电平)连接，第二极和上拉节点PU连接。
该上拉节点复位电路包括第二晶体管M2以及第三晶体管M3，第二晶体管M2的栅极和移位寄存器单元的复位端连接，第一极和上拉节点PU连接，第二极和第二电压端VGL(例如输入低电平)连接；第三晶体管M3的栅极和下拉节点PD连接，第一极和上拉节点PU连接，第二极和第二电压端VGL连接。
该输出电路包括第四晶体管M4以及存储电容C1，第四晶体管M4的栅极和上拉节点PU连接，第一极和时钟信号端CLK连接，第二极和移位寄存器单元的第一输出端OUTPUT连接；存储电容C1并联连接在输出晶体管M4的栅极和第二极之间。
该下拉电路包括第五晶体管M5以及第六晶体管M6，第五晶体管M5的栅极和第一下拉控制节点PD_CN连接，第一极和第一电压端VGH连接，第二极和下拉节点PD连接；第六晶体管M6的栅极和上拉节点PU连接，第一极和下拉节点PD连接，第二极和第二电压端VGL连接。
该下拉控制电路包括第七晶体管M7以及第八晶体管M8，第七晶体管M7的栅极与第一极和第一电压端VGH连接，其第二极和第一下拉控制节点PD_CN连接；第八晶体管M8的栅极和上拉节点PU连接，第一极和第一下拉控制节点PD_CN连接，第二极和第二电压端VGL连接。
该输出复位电路包括第九晶体管M9，第九晶体管M9的栅极和下拉节点PD连接，第一极和第一输出端OUTPUT连接，第二极和第二电压端VGL连接。
例如，上述晶体管均为N型晶体管，但是本公开的实施例不限于这种情形。
下面结合图5B所示的示例性信号时序来说明图5A所示的移位寄存器单元的工作原理。在图5B所示的第一阶段A、第二阶段B以及第三阶段C 三个阶段中，该移位寄存器单元进行如下操作。
在第一阶段A，时钟信号端CLK输入低电平，第一电压端VGH输入高电平(例如第一电压端可以设置为保持输入高电平信号)，输入端INPUT输入高电平，对于栅极驱动电路中的第一级移位寄存器而言，该高电平信号为STV信号，而对于其他级移位寄存器而言，例如该高电平信号则是级联的上一级的输出信号(OUT)。由于输入端INTPUT输入高电平，第一晶体管M1导通，使得第一电压端VGH输入的高电平对上拉节点PU进行充电，上拉节点PU的电位被充电至第一高电平。
由于第一电压端VGH保持输入高电平，第七晶体管M7导通，对第一下拉控制节点PD_CN充电，从而使得第五晶体管M5导通，进而第一电压端VGH输入的高电平对下拉节点PD也进行充电。由于上拉节点PU处于第一高电平，第六晶体管M6和第八晶体管M8导通，从而使得下拉节点PD、第一下拉控制节点PD_CN和第二电压端VGL电连接(例如第二电压端可以设置为保持输入低电平信号)。在晶体管的设计上，可以将第七晶体管M7与第八晶体管M8配置为(例如对二者的尺寸比、阈值电压等配置为)在M7和M8均导通时，第一下拉控制节点PD_CN的电平被下拉到低电平；类似地，可以将第五晶体管M5与第六晶体管M6配置为(例如对二者的尺寸比、阈值电压等配置)为在M5和M6均导通时，下拉节点PD的电平被下拉到低电平，从而保证第三晶体管M3和第九晶体管M9在此阶段处于截止状态。
由于上拉节点PU处于第一高电平，第四晶体管M4导通，此时时钟信号端CLK输入低电平，所以在此阶段，第一输出端OUTPUT输出该低电平信号。
在第二阶段B，时钟信号端CLK输入高电平，第一电压端VGH依然输入高电平，输入端INPUT输入低电平。由于输入端INPUT输入低电平，第一晶体管M1截止，上拉节点PU保持上一阶段的第一高电平，从而使得第四晶体管M4保持导通，由于在此阶段时钟信号端输入高电平，所以第一输出端OUTPUT输出高电平信号。
由于存储电容C1的自举效应，上拉节点PU的电平进一步被拉高，达到第二高电平，使得第四晶体管M4的导通更充分。由于上拉节点PU的电位为高电平，第六晶体管M6和第八晶体管M8继续导通，分别将下拉节点 PD和第一下拉控制节点PD_CN的电位下拉到第二电压端输入的低电平。由于下拉节点PD的电位为低电平，第三晶体管M3和第九晶体管M9保持截止状态，从而不会影响移位寄存器单元正常输出移位信号。
在第三阶段C，时钟信号端CLK输入低电平，第一电压端VGH继续输入高电平，输入端INPUT继续输入低电平，复位端RESET输入高电平，对于栅极驱动电路中的最后一级移位寄存器而言，该高电平信号为RST信号，而对于其他级移位寄存器而言，例如该高电平信号则是级联的下一级的输出信号(OUTPUT)。由于复位端RESET输入高电平，第二晶体管M2导通，将上拉节点PU的电位下拉到第二电压端VGL输入的低电平，从而第四晶体管M4截止。
由于第一电压端VGH保持输入高电平，第七晶体管M7导通，对第一下拉控制节点PD_CN充电，进而使得第五晶体管M5导通，从而对下拉节点PD充电。由于上拉节点PU的电位处于低电平，第六晶体管M6和第八晶体管M8截止，下拉节点PD的放电路径被截止，下拉节点PD被充电至的高电平，由此使得第三晶体管M3和第九晶体管M9导通，从而分别将上拉节点PU和第一输出端OUTPUT的电位下拉到第二电压端VGL输入的低电平，消除了移位寄存器单元在非输出阶段其第一输出端OUTPUT和上拉节点PU处可能产生的噪声。
需要特别指出的是，图5A和图5B所示出的仅仅是一种示例性说明，本公开不限于图5A所示的移位寄存器电路和图5B所示的时序图。
本公开至少一些实施例提供了一种显示控制方法及显示控制装置。图6是本公开实施例提供的一种显示驱动方法的流程图。
如图6所示，该显示驱动方法可以包括使用输入图像数据执行第一显示模式。该第一显示模式包括如下步骤：
步骤S102，将输入图像数据进行重排得到重排图像数据；
步骤S103，对应该重排图像数据产生第一图像显示控制信号和第一延时控制信号；以及
步骤S104，输出重排图像数据，第一图像显示控制信号和第一延时控制信号。
在步骤S102，该输入图像数据可以包括用于在显示面板上实际显示的有效行部分和用于在该显示面板上非实际显示的无效行部分，该重排图像数 据包括与该有效行部分和无效行部分分别对应的重排有效行部分和重排无效行部分。
在上述方法中，第一图像显示控制信号用于在显示操作过程中对应于重排图像数据进行帧显示，第一延时控制信号用于在帧显示的过程中触发用于重排有效行部分在显示面板中的行扫描过程。如上所述，“第一图像显示控制信号”、“第一延时控制信号”等表述中的“第一”仅用于进行区分，而非用于限定，因此在适当的语境下，也直接使用“图像显示控制信号”、“延时控制信号”等。
本公开实施例的显示驱动方法适用于输入图像仅有部分行数据在显示面板中显示的情形，该显示面板例如为条形显示面板(仅显示部分画面而非全部全幅画面)，其包括栅极驱动电路、数据驱动电路和和像素阵列。该栅极驱动电路用于接收栅极扫描信号对像素阵列进行扫描；数据驱动电路用于接收图像数据信号并将图像数据信号提供给像素阵列；像素阵列用于在栅极驱动电路的控制下从数据驱动电路接收图像数据以进行显示操作。
例如，上述第一显示模式可以在不改变输入图像数据的尺寸规格并且不改变显示面板的栅极驱动电路的扫描方向的情况下，使得倒置使用的条形显示器能够实现正常的正方观看(与倒置方向相反)，因此节省了成本，扩大了条形显示器的适用场景。
例如，输入图像可以是全画幅的，例如，可以是1920*1080的大小(即1920列1080行)；该输入图像具有有效行部分和无效行部分，例如，该输入图像的前360行是该输入图像的有效行部分，而其余的后720行是该输入图像的无效行部分。该显示面板可以是条形显示面板，例如是1920*360的条形显示区域(即1920列360行)。应当注意，本公开的实施例并不限于上述尺寸的输入图像以及上述尺寸的显示面板。
如上所述，如果该输入图像不经任何处理，倒置的条形显示面板只显示1920*1080图像其中的前360行，其余的后720行将不会显示在该条形显示面板上，但是由于条形显示面板例如是相对地面(这里作为参照面)倒置的，因此站在地面上的观众看到的也是倒置的图像。在下面的示例中，倒置、正向等都是以相对于地面而言的，但是本公开的实施例并不限于这种场景。
在本公开实施例的显示驱动方法中，对输入图像进行重排，以在不改变显示面板的放置状态的情况下正常使用该显示面板。例如，可以将该输入图 像的整体进行倒置重排，也可以仅仅对上述有效行部分进行倒置重排。
该输入图像具有有效行部分和无效行部分，对应地，经过重排后的重排图像包括重排有效行部分和重排无效行部分。例如，对上述1920*1080输入图像进行倒置重排后，倒置重排的图像的有效行可以是底部的721～1080行(共360行)，即对应原输入图像的1～360行的有效行部分，倒置重排的图像的无效行可以是顶部的1～720行，即对应原图像的361～1080行的无效行部分。
在步骤S103，对应该重排图像数据产生第一图像显示控制信号和第一延时控制信号。例如，该第一图像显示控制信号可以包括对应上述重排后的重排图像产生的各种控制信号，例如，这些控制信号可以包括用于数据驱动电路的STH(行数据起始信号)、CPH(数据时钟信号)、数据输出信号(TP)等，还可以包括用于栅极驱动电路的STV(帧扫描起始信号)、CLK信号(时钟信号)等，但是在扫描过程中STV信号并不实际工作而仅仅用于设定一帧显示的开始时间，从而可以确定延时控制信号起作用的时间点。
例如，该第一延时控制信号可以用于产生上述显示面板的栅极驱动电路的扫描起始信号。例如，该第一延时控制信号(DCI)可以是一个类似于STV信号的触发信号，但是比上述STV信号延迟了设定的时间。该第一延时控制信号可以对应重排有效行部分在该重排图像数据中的位置得到。例如，在上述示例中，输入图像数据是1920*1080时而有效行部分为1～360行，那么对应地重排有效行部分的第一行在重排图像数据中的位置是第721行，因而可以计算从第1行扫描到第720行的时间，即重排无效行部分的时间确定第一延时控制信号。
例如，假设显示面板的显示刷新率为60Hz，每帧画面(也即显示一次重排图像数据)的显示时间为1/60秒，那么在上述示例中，对于每一帧而言，在不考虑本身比较小的帧间消隐间隔(blanking)的情况下，第一延时控制信号与该帧的STV信号相比要延迟(1/60)*(720/1080)＝1/90秒，也即在STV信号之后1/90秒。
之后，输出重排图像数据、第一图像显示控制信号和第一延时控制信号至显示面板进行显示。该第一图像显示控制信号用于在该显示操作过程中对应于该重排图像数据进行帧显示，该第一延时控制信号用于在该帧显示的过程中触发用于该重排有效行部分在该显示面板中的行扫描过程。由此，在输 入图像数据的有效行部分中原本处于靠后的行，在重排图像数据的重排有效行部分中变成靠前的行，并且先在显示面板中被显示，由此对于例如相对地面被倒置的显示面板本身而言，其显示了倒置的图像，而且对于站在地面上的观众而言却看到了正放的图像。
例如，在一种实施例中，该第一图像显示控制信号可以正常产生并输出，但是在第一延时控制信号没有到来之前处于非有效状态，即并不实际提供给显示面板，或者，至少STV(帧扫描起始信号)不实际提供给显示面板的栅极驱动电路或并不实际产生，因此显示面板的栅极驱动电路没有进行栅极扫描信号的输出，因此并不实际进行显示操作；在该情形中，在第一延时控制信号到来时，图像显示控制信号才被实际作用于显示面板的帧显示，具体地，显示面板的栅极驱动电路被第一延时控制信号触发，开始根据时序信号产生栅极扫描信号，同时显示面板的数据驱动电路同步输出数据信号，实现例如逐行显示或隔行显示等。
例如，CLK信号可以在重排图像数据产生的延时区间(对应重排图像数据的重排无效行部分)提供给显示面板的栅极驱动电路。又例如，CLK信号在重排图像数据产生的延时区间(对应重排图像数据的重排无效行部分)不实际提供给显示面板的栅极驱动电路或并不实际产生。
例如，倒置重排后的图像数据(即重排图像的图像数据)、第一图像显示控制信号和第一延时控制信号可以同时输出，但是显示面板进行显示的重排有效行部分是在第一延时控制信号(例如另一类似STV信号的信号)的触发下进行行扫描的。例如，在上述输入图像数据为1920*1080且显示刷新率为60Hz的示例中，重排有效行部分的第一行在该重排图像数据中的位置的第721行，因而在第一图像显示控制信号的起始时间(即STV信号的时间)经过1/90秒时，即时间对应于在第720行进行行扫描的时候，第一延时控制信号触发显示面板的栅极驱动电路，由此栅驱动电路开始在各个输出端口OUT1(对应于显示面板实际的第一行)到OUT360(对应于显示面板实际的第360行)开始依序输出栅极扫描信号，同时数据驱动电路开始依序按行输出图像数据，从而将重排图像数据中重排有效行部分(即第721～1080行)输出，在显示面板上进行显示(对此可以参考后面将要描述的图7C)。例如，在逐行扫描的情况下，显示面板的栅极电路按照从输出端口OUT1到OUT360的顺序逐一输出栅极扫描信号，同步地，数据驱动电路将按照重排 有效行部分中从第721行到第1080行的顺序逐行输出图像数据，由此实现显示。输入图像数据的有效行部分的第360行(对应于重排有效部分的第721行)被首先显示，而输入图像数据的有效行部分的第1行(对应于重排有效部分的第1080行)被最后显示，因此，对于显示面板本身而言以倒置的方式显示了输入图像数据中的有效行部分，但是对于站在地面上且观看相对地面倒置的显示面板的观众而言，却看到了正放的图像。
例如，在本公开至少一些实施例中，上述显示驱动方法还可以进一步包括步骤S101和/或步骤S105。
在步骤S101，接收输入图像数据，将输入的图像数据进行接收以便于后续处理。输入图像例如可以是来自调制解调器，调制解调器例如通过有线或无线网络接收的输入图像数据。输入图像数据可以静态图像，也可以是动态图像，还可以是视频。或者，输入图像例如可以是来自显示装置本身所了解的存储装置，该存储装置例如可以是硬盘(机械硬盘或固态硬盘)，也可以是可插拔存储装置，例如U盘等。
在步骤S105，存储该输入的图像数据，例如可以通过但不限于易失性存储方式或非易失性存储方式存储该输入图像数据，以便进行后续的图像数据处理。
从而，通过上述技术方案，可以解决当前倒置使用该条形显示器时，该长条形显示器上显示的画面出现倒置的技术问题，达到可以在上述系统客户端将输入的图像数据不需倒置处理的情况下该条形显示器仍能正常显示输入图像的技术效果，同时也提高了该条形显示器的通用性和兼容性。
图8是本公开另一实施例提供的一种显示驱动方法的流程图。如图8所示，例如，该显示控制方法在图6所示的显示控制方法的基础上，还可以包括：
步骤S202，获取显示控制指令；
步骤S203，响应于该显示控制指令，选择进行第一显示模式或进行第二显示模式。
该显示控制方法可以包含两种显示模式，即第一显示模式和第二显示模式。例如，上述实施例描述的显示驱动方法对应于第一显示模式，使用该重排图像数据、该第一图像显示控制信号和该第一延时控制信号，在该显示面板进行显示操作，在该第一显示模式中，显示面板倒置放置，例如相对于其 自身的正常放置参考指向，进行倒置放置安装。第二显示模式中，使用该输入图像数据和该第二图像显示控制信号，在该显示面板进行显示操作，在该第二显示模式中，该显示面板正向放置，即按照其自身的正常放置参考指向进行放置或安装。应当注意，上述第一、第二只是便于区分两种不同的显示模式，并不构成对本公开实施例的限制。
例如，在第二显示模式下，该实施例的显示驱动方法包括：
步骤S221，对应该输入图像数据，产生该第二图像显示控制信号；以及
步骤S222，输出该输入图像数据和该第二图像显示控制信号。
例如，在一个示例中，在步骤S202，获取显示控制指令，例如可以读取该显示面板所属的显示系统的输入端口，根据该输入端口的不同状态来获取该显示控制指令。可以从在接收输入图像数据时获取显示控制指令，也可以在其他时间获取显示控制指令，例如接收到输入图像之后获取。例如，该输入端口可以为显示装置的某一管脚(pin)或开关，如果该管脚或开关被设置为高(H)，则表示使用第一显示模式，而被设置为低(L)，则表示使用第二显示模式。又例如，该输入端口与一感应元件(例如重力感应元件)通信(例如直接相连接)，该感应元件可以感应显示面板相对于预设方向(例如重力方向)的朝向。例如，当显示面板正放(例如相对于地正放)时，感应元件输出高(H)，表示使用第二显示模式；当显示面板倒放(例如相对于地倒放)时，感应元件输出低(L)，表示使用第一显示模式。该重力感应元件例如为利用重力进行开合的开关，例如，正放时由于开关闸刀本身重力而闭合，倒放时由于开关闸刀本身重力而开启。
该显示控制指令可以是用于判断选择第一显示模式或第二显示模式的可执行指令数据，例如，可以是代表第一显示模式的第一可执行代码，例如指令代码code1；以及代表第二显示模式的第二可执行代码，例如指令代码code2。
例如，在步骤S203，响应于该显示控制指令，选择执行该第一可执行代码或第二可执行代码，由此选择进行第一显示模式或进行第二显示模式。例如，当接收到指令代码code1时，选择进行第一显示模式，当接收到指令代码code2时，选择进行第二显示模式。例如，第一可执行代码和第二可执行代码可以保存在存储装置之中，以便于系统调取并通过处理器执行，由此 相应地进行第一显示模式的操作或第二显示模式的操作。
例如，在步骤S221，对应该输入图像数据，产生该第二图像显示控制信号。该第二图像显示控制信号可以用于在该显示操作过程中对应于该输入图像数据进行帧显示。
例如，在步骤S222，输出该输入图像数据和该第二图像显示控制信号，可以将输入图像数据和第二图像显示控制信号，而没有经过图像倒置处理和延时处理直接输出到输出电路，以该显示面板进行常规的显示操作，以实现第二显示模式，例如该显示面板正常使用时的正向放置状态显示模式。
例如，在一个实施例中，由于输入图像数据与重排图像数据二者的规格相同，即具有相同的行数和列数，因此该第二图像显示控制信号和上述第一图像显示控制信号的规格相似，即具有相同的STV、CLK、STH、CPH、TP等。二者的区别在于第一图像显示控制信号和第一延时控制信号协作，一开始并不直接驱动显示面板而是在有第一延时控制信号时才驱动显示面板的栅极驱动电路进行显示，延迟驱动显示面板的栅极驱动电路，从而实现延迟显示的效果，而第二图像显示控制信号则可以没有对应的延时控制信号，因此可以从一开始就直接驱动显示面板的栅极驱动电路进行显示，即第二图像显示控制信号包括的STV从一开始就作用到显示面板的栅极驱动电路，由此栅极驱动电路依序产生栅极扫描信号。
对于上述输入图像的有效行部分为第1行至第360行的示例，对于用于在显示面板上显示输入图像的第二图像显示控制信号，就是一开始就驱动显示面板的栅极驱动电路进行显示。
然而，在另一个示例中，输入图像数据为1920*1080，而有效行部分为从第281行至第720行，也即包括该输入图图像的大致中间部分；对应地，经过倒置处理的重排图像数据也为1920*1080，重排有效部分则是在重排图像中从第361行至第800行。那么，在第一显示模式中，基于重排图像数据产生了第一图像显示控制信号且包括延迟360行扫描时间的第一延时控制信号，从而可以在倒置的显示面板中实现倒置图像显示；在第二显示模式中，基于输入图像数据产生了第二图像显示控制信号且包括延迟280行扫描时间的第二延时控制信号，从而可以在正放的显示面板中实现正向图像显示。因此，对于有效行部分位于输入图像的中部的情况，在第二显示模式中，对于未经过重排处理的输入图像数据，也需要加入相应的延时控制信号。
图9是本公开至少一些实施例提供的一种显示驱动装置的示意图。该显示驱动装置可以用于实施如图6所示的显示驱动方法。
如图9所示，该显示驱动装置100可以包括：图像处理模块101、时序产生模块102、延时处理模块103、输出电路104、输入端口105以及第一存储装置106。例如，该显示控制装置可以至少部分通过TCON芯片的形式实现，例如，该TCON芯片包括上述图像处理模块101、时序产生模块102、延时处理模块103、输出电路104，例如，第一存储装置206可以为该TCON芯片内，也可以设置在TCON芯片之外，但是设置在同一印刷电路板上，从而二者通过总线连接。该显示控制装置也可以实现为CPU与存储器的组合，也可以实现为SoC、FPGA、ASIC等形式，本公开实施例不对该显示控制装置的实现方式作限制。并且，图像处理模块101、时序产生模块102、延时处理模块103、输出电路104等可以任意组合在一个或多个电路器件或部件之中。
例如，该图像处理模块101可以用于将接收到的输入图像数据进行重排得到重排图像数据。例如，该图像处理模块101可以包括图像数据重排电路，该图像数据重排电路可以用于将该输入图像数据进行整体倒置重排操作，例如对1920*1080的整体进行倒置重排，或者在一些示例中，可以仅对有效行部分进行重排操作，例如仅对1920*360的有效行部分进行倒置重排，以得到该重排图像数据。
例如，该时序产生模块102可以用于对应该重排图像数据(图像的行数、列数)，并且考虑显示面板的显示刷新率，产生第一图像显示控制信号，例如用于数据驱动电路的STH(行数据起始信号)、CPH(数据时钟信号)等。例如，第一图像显示控制信号还可以包括用于栅极驱动电路的STV(帧扫描起始信号)、CLK信号(时钟信号)等，其中，第一图像显示控制信号用于在该显示操作过程中对应于该重排图像数据进行帧显示，在该扫描过程中STV信号并不实际工作而仅仅用于设定一帧显示的开始时间，从而可以确定延时控制信号起作用的时间点。例如，在该显示面板进行图像显示时，将根据该第一图像显示控制信号将该重排后的图像数据进行显示。
例如，该延时处理模块103用于对应该重排图像数据，产生第一延时控制信号，例如，该第一延时控制信号用于在该帧显示的过程中触发用于该重排有效行部分在显示面板中的行扫描过程，例如在该显示面板进行图像显示 时，触发根据该第一图像显示控制信号将该重排后的图像数据正确显示的过程。例如，该第一延时控制信号根据该重排有效行部分在该重排图像数据中的位置得到，或者该第一延时控制信号通过预设得到。这里，“预设”可以为在系统中预设了延迟控制信号的输出时间，例如可以固定预设的(例如写入系统中而不可更改的)，或者可以是使用者根据需要预设的或者根据系统板指令预设的。
例如，该延时处理模块103可以包括栅信号时序调整模块，该栅信号时序调整模块可以用于，将该第一延时控制信号设置得晚于该第一图像显示控制信号中包括的STV信号预定时间，该预定时间根据该重排有效行部分在该重排图像数据中的位置得到，或者所述预定时间通过预设得到。同样地，这里的“预设”可以为在系统中预设了该预定时间，例如可以固定预设的(例如写入系统中而不可更改的)，或者可以是使用者根据需要预设的或者根据系统板指令预设的。
例如，该延时处理模块103还可以用于实现延时控制方式，例如，上述延时控制方式可以是，该延时处理模块103对应重排无效行部分的数据行数(N_Dummy)和重排有效行部分的数据行数(N_Active)分别计算出重排无效行部分所对应的延时时长T1和重排有效部分所对应的工作时长T2。例如，数据驱动电路始终正常逐行输出全画幅例如1920*1080的重排图像数据，在T1时间区间内，没有STV信号作用到栅极驱动电路，并且延时处理模块103也没有向栅极驱动器发出扫描起始信号STV，因此在T1时间区间内，栅极驱动器不产生栅极输出信号，例如GOUT信号；在T2时间区间内，例如，在T1时间区间与T2时间区间的交界点，例如第720行数据对应的时间点上，延时处理模块103开始向栅极驱动器发出类似于扫描起始信号STV的触发信号(即DCI)，因而在T2时间区间内，栅极驱动器开始逐级产生栅极扫描信号，例如GOUT信号，从而开始从重排图像数据的第721行逐行在该显示面板上显示该重排有效行部分。
例如，该输出电路104与显示面板通信，用于输出所述重排图像数据、第一图像显示控制信号和第一延时控制信号至显示面板，由此显示面板在这些信号的驱动下进行显示操作。
例如，该输入端口105可以用于获取输入图像数据，或者，在一些示例中，还可以用于获取其他与输入图像数据进行显示有关的信号，例如显示模 式控制指令信号等。该输入端口105例如是输入电路的端口，该输入电路例如可以是调制解调器或USB驱动电路等。例如，输入端口包括一个管脚(pin)或开关，如果该管脚或开关被设置为高(H)，则表示使用第一显示模式，而被设置为低(L)，则表示使用第二显示模式。
例如，该第一存储装置106可以用于临时或长期存储输入的图像数据，例如通过临时存储输入的图像数据从而有利于后续的图像处理操作，例如能够在输入端口105不能实时高速稳定获取输入图像时，预先将输入图像数据存入该存储器，以实现缓存功能。第一存储装置106例如可以是半导体存储装置。
上述显示驱动装置可以在不需要变更系统客户端提供输入图像数据的方式的前提下，使常规的输入图像在(相对于例如地面)倒置使用的条形屏幕上对于站立在地面上的观众而言是正常显示的，从而提高了显示面板的兼容性。
图10是本公开另一实施例提供的一种显示驱动装置的示意图。图10所示的显示驱动装置200可以在图9所示的显示驱动装置100的基础上增加控制装置207以及第二存储装置208。
例如，该时序产生模块202还可以用于，对应该输入图像数据，直接产生第二图像显示控制信号，例如，该第二图像显示控制信号可以用于在该显示操作过程中对应于该输入图像数据进行帧显示，例如，在该显示面板进行图像显示时，根据该第二图像显示控制信号将该输入图像数据正确显示，例如该第二图像显示控制信号包括对应输入图像产生的STV、CLK等信号，以控制显示面板进行显示操作。
例如，该控制装置207可用于根据显示控制指令选择进行上述第一显示模式或进行第二显示模式。例如，在第二存储装置中存储分别对应于第一显示模式和第二显示模式的可执行代码code1和code2。例如，该控制装置207接到的显示控制指令是进行第一显示模式时，则从存储装置中调取code1并执行，由此进入第一显示模式，使得图像处理模块201对输入图像进行重排并得到重排图像数据；延时处理模块203对应该重排图像数据生成第一延时控制信号；时序产生模块202对应该重排图像数据生成第一图像显示控制信号，之后输出电路204将上述的重排图像数据、第一延时控制信号、第一图像显示控制信号输出到该显示面板进行第一显示模式显示。
例如，该输出电路204还可以用于输出该输入图像数据和该第二图像显示控制信号，用于在该显示面板进行该第二显示模式的显示操作。例如，该控制装置207接到的显示控制指令是进行第二显示模式时，则从存储装置中调取code2并执行，由此选择第二显示模式，图像处理模块不对输入图像进行重排处理，时序产生模块202对应该输入图像数据生成第二图像显示控制信号，之后输出电路204将上述输入图像数据、第二图像显示控制信号输出到该显示面板进行第二显示模式显示。
例如，该第二存储装置208可以用于存储分别对应于该第一显示模式的第一可执行代码(code1)和对应于该第二显示模式的第二可执行代码(code2)。例如，上述控制装置207可以从该第二存储装置208中读取相应的代码以确定相应的显示模式。第二存储装置208可以半导体存储装置，例如为EEPROM或闪存(Flash)，并且例如通过I2C总线连接到控制装置、图像处理模块等。
上述显示控制装置可以根据用户的选择实现多种显示模式，从而实现了无论条形显示面板正常放置或安装还是倒置放置或安装，用户都可以根据正常显示的需要较为容易方便地切换不同的显示模式。
下面进一步结合示例性的图7A、图7B和图7C来阐述上述的显示驱动方法及显示驱动装置。图7A是是一种示例性的输入图像。如图7A所示，从输入端口获取的输入图像例如为1920*1080大小的图像。图7A中的上部的条状区域例如可以是1920*360的条形显示面板正常显示的区域(有效行部分)，下部的空白区域是无需正常显示的区域(无效行部分)。
例如，可以通过上述的图像处理模块对图7A中的图像进行重排，例如可以根据实际的情况进行上下翻转，应当注意，本公开不对具体的重排方式作限定。例如，可以对应显示面板的倒置使用，对输入图像进行上下翻转的倒置重排，得到图7B所示的重排后的重排图像，由此，原本在图7A的上部的有效行部分例如前360行的部分经过倒置重排后出现在图7B的下部，成为了重排有效行部分例如后360行部分，原本在图7A的下部的无效行部分例如后720行部分经过倒置重排后出现在图7B的上部，成为重排无效行部分例如前720行部分。
例如，图7C是对应于图7B的重排图像数据的显示驱动方法的处理时序图。如图7C所示的实施例中，对应图7B所示的重排图像数据产生的第 一图像显示控制信号包括STV和CLK1、CLK2、……、CLK6(根据需要还可以包括更多的CLK)等，然而在对应于重排无效行部分的时间段内，这些信号并不会在显示面板中产生栅极扫描信号(此时其功能可以是起到计时作用)，或者在其他实施例中，第一图像显示控制信号可以不包括STV信号；在对应于重排有效行部分的时间段的起始点，提供类似于STV信号作用的延时控制信号(DCI)至显示面板的栅极驱动电路，由此显示面板的栅极驱动电路开始依序输出栅极扫描信号。在该图示的实施例中，图中H表示为每行栅线分配的实际开启时间，每个CLK信号(CLK1、CLK2、……、CLK6)的周期为6H，相应的高电平阶段为3H，由此产生的栅极扫描信号OUT1、OUT2、OUT3、……等的高电平阶段也为3H。
显示面板的持续显示过程中，STV信号和/或DCI信号都是周期信号，其频率等于显示面板的显示刷新频率，例如STV信号和/或DCI信号可以通过对系统时钟信号进行分频得到，并且通过例如由CLK驱动的计数电路实现DCI信号相对于STV信号的延时，或者在不产生STV信号的情形，相对于预设的帧显示的起点时间的延时。
例如，在图7C所示的时序图里，空白区域之后是对应上述重排图像数据产生的延时区间，该区间对应重排图像数据的重排无效行部分，例如上述重排图像数据的前720行部分。在此延时区间，时序控制信号例如CLK、STV可以处于非有效状态，因而栅极驱动器的各个输出端的信号例如OUT1、OUT2、OUT3、……等栅极扫描信号也可以处于非有效状态。在对应于第720行的阶段，延时控制信号(DCI)被施加到栅极驱动电路的第一移位寄存器的输入端，由此栅极驱动电路开始工作，以依序产生栅极扫描信号OUT1、OUT2、OUT3、……等，每个栅极扫描信号对应于1行图像数据，对应地数据驱动电路输出对应于第721行～第1080行的图像数据信号。
图7C所示的时序里，延时控制信号之后的各个栅极扫描信号OUT1、OUT2、OUT3、……等的有效阶段(即图中波形的高电平部分)总体上对应于重排图像数据的重排有效行部分。在此区间，显示面板开始工作，该重排有效行部分可以正常显示在倒置的条形显示面板上，从而使得原来的输入图像的上部有效行部分经过倒置重排后位于重排图像数据的下部，对应该重排图像数据进行延时后，下部的重排有效行部分将显示在倒置的条形显示面板上，由于该条形显示面板倒置放置，最终结果又将倒置重排的图像再次倒置 过来，从而显示效果可以是正置的图像。
上述过程可以在不改变现有系统客户端提供图像数据的方式的情况下，通过对输入图像数据的重排和对应重排后的图像数据进行延时实现在不同放置方式的显示面板上正常显示输入的图像数据。
图11是本公开至少一些实施例提供的一种显示装置的示意图，如图11所示，该显示装置300包括本公开的实施例提供的任一显示控制装置310，该显示控制装置310例如可以时限为时序控制电路(TCON)。该显示装置300包括显示面板330，显示面板330包括由多个像素单元构成的像素阵列。例如，该显示装置300还可以包括数据驱动电路320、栅极驱动电路340。数据驱动电路320用于提供数据信号给像素阵列；栅极驱动电路340用于接收扫描控制信号以提供栅极扫描信号给像素阵列。显示控制装置310通过信号线312与数据驱动电路320电连接，显示控制装置310通过信号线311与栅极驱动电路340电连接，数据驱动电路320通过数据线321与像素单元电连接，栅极驱动电路340通过栅线341与像素单元电连接。
在一个具体实施例中，倒置使用显示装置300是指保持显示装置300的出光方向不变，将显示装置300旋转180°。例如，显示装置300相对于地面悬挂使用时，出光面的出光方向为与地面平行的方向，数据驱动电路320位于显示装置300的天侧和/或地侧，栅极驱动电路340位于显示装置300的左侧和/或右侧。例如，显示装置300悬挂使用时，出光面的出光方向为与地面平行的方向，数据驱动电路320位于显示装置300的地侧时，通过倒置显示装置300操作，此时数据驱动电路320设置于显示装置300的天侧。显示装置300可以实现倒置使用时图像的正置显示。进一步地，显示装置300可以为条形显示屏，其显示区包括长边侧和短边侧；其中，数据驱动电路320可以位于长边侧，栅极驱动电路340可以位于短边侧，优选地，栅极驱动电路340可以为GOA驱动电路。条形显示屏可以实现倒置使用时图像的正置显示。
在一个具体实施例中，倒置使用显示装置300是指保持显示装置300的出光方向不变，将显示装置300旋转180°。例如，显示装置300相对于地面悬挂使用时，出光面的出光方向为与地面平行的方向，栅线341与地面平行设置，数据线321的延伸方向可以为地面相交的方向(例如，数据线321与地面垂直)。显示装置300可以实现倒置使用时图像的正置显示。进一步 地，显示装置300可以为条形显示屏，其显示区包括长边侧和短边侧；其中，栅线341可以沿着与长边侧平行方向延伸，数据线321可以沿着与短边侧平行方向延伸。条形显示屏可以实现倒置使用时图像的正置显示。
显示面板330例如可以为液晶显示面板、有机发光二极管(OLED)显示面板、量子点发光二极管(QLED)显示面板、电子纸显示面板、等离子体显示面板等，本公开的实施例对此不作限制。
需要说明的是，本实施例中的显示装置可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置还可以包括显示面板等其他常规部件，本公开的实施例对此不作限制。
本公开的实施例提供的显示装置1的技术效果，可以参考上述实施例中关于显示控制装置的相应描述，这里不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种显示控制方法，包括：
    使用输入图像数据执行第一显示模式，其中，
    所述第一显示模式，包括：
    将所述输入图像数据进行重排得到重排图像数据，其中，所述输入图像数据包括用于在显示面板上实际显示的有效行部分和用于在所述显示面板上非实际显示的无效行部分，所述重排图像数据包括与所述有效行部分和无效行部分分别对应的重排有效行部分和重排无效行部分；
    对应所述重排图像数据，产生第一图像显示控制信号和第一延时控制信号，
    输出所述重排图像数据、所述第一图像显示控制信号和所述第一延时控制信号，用于在所述显示面板进行显示操作，
    其中，所述第一图像显示控制信号用于在所述显示操作过程中对应于所述重排图像数据进行帧显示，所述第一延时控制信号用于在所述帧显示的过程中触发用于所述重排有效行部分在所述显示面板中的行扫描过程。
  2. 根据权利要求1所述的显示控制方法，其中，将所述输入图像数据进行重排得到所述重排图像数据，包括：
    将所述输入图像数据进行整体倒置重排操作，以得到所述重排图像数据，
    其中，所述第一延时控制信号根据所述重排有效行部分在所述重排图像数据中的位置得到，或者所述第一延时控制信号通过预设得到。
  3. 根据权利要求1所述的显示控制方法，还包括：
    获取显示控制指令；
    响应于所述显示控制指令，选择进行所述第一显示模式或进行第二显示模式，其中，所述第二显示模式不同于所述第一显示模式。
  4. 根据权利要求3所述的显示控制方法，其中，
    所述第二显示模式包括：
    对应所述输入图像数据，产生所述第二图像显示控制信号，其中，所述第二图像显示控制信号用于在所述显示操作过程中对应于所述输入图像数据进行帧显示；
    输出所述输入图像数据和所述第二图像显示控制信号，用于在所述显示面板进行所述显示操作。
  5. 根据权利要求3所述的显示控制方法，其中，获取所述显示控制指令，包括：
    读取所述显示面板所属的显示系统的输入端口，
    根据所述输入端口的不同状态来获取所述显示控制指令。
  6. 根据权利要求5所述的显示控制方法，其中，所述显示系统包括分别对应于所述第一显示模式的第一可执行代码和对应于所述第二显示模式的第二可执行代码，
    响应于所述显示控制指令指示，选择进行所述第一显示模式或进行所述第二显示模式，包括：
    根据所述显示控制指令，选择执行所述第一可执行代码或第二可执行代码。
  7. 根据权利要求3所述的显示控制方法，其中，在所述第一显示模式之中，所述显示面板处于倒置状态；
    所述第二显示模式之中，所述显示面板相对于处于正放状态，所述正放状态与所述倒置状态相反。
  8. 根据权利要求1-7任一所述的显示控制方法，其中，所述显示面板包括用于实现所述行扫描过程的栅极驱动电路，
    所述第一延时控制信号用于产生所述栅极驱动电路的扫描起始信号。
  9. 根据权利要求1-7任一所述的显示控制方法，还包括：
    接收并存储所述输入图像数据。
  10. 一种显示控制装置，包括：图像处理模块、时序产生模块、延时处理模块和输出电路，
    其中，所述图像处理模块被配置为，将接收到的输入图像数据进行重排得到重排图像数据，其中，所述输入图像数据包括用于在显示面板上实际显示的有效行部分和用于在所述显示面板上非实际显示的无效行部分，所述重排图像数据包括与所述有效行部分和无效行部分分别对应的重排有效行部分和重排无效行部分；
    所述时序产生模块被配置为，对应所述重排图像数据，产生第一图像显示控制信号，其中，所述第一图像显示控制信号用于在所述显示操作过程中对应于所述重排图像数据进行帧显示；
    所述延时处理模块被配置为，对应所述重排图像数据，产生第一延时控制信号，其中，所述第一延时控制信号用于在所述帧显示的过程中触发用于所述重排有效行部分在所述显示面板中的行扫描过程；
    所述输出电路被配置为，输出所述重排图像数据、所述第一图像显示控制信号和所述第一延时控制信号，用于在所述显示面板进行显示操作。
  11. 根据权利要求10所述的显示控制装置，其中，所述图像处理模块包括图像数据重排电路，
    其中，所述图像数据重排电路被配置为将所述输入图像数据进行整体倒置重排操作，以得到所述重排图像数据。
  12. 根据权利要求10所述的显示控制装置，其中，所述第一延时控制信号根据所述重排有效行部分在所述重排图像数据中的位置得到，或者所述第一延时控制信号通过预设得到。
  13. 根据权利要求12所述的显示控制装置，其中，所述延时处理模块包括栅信号时序调整模块，
    其中，所述栅信号时序调整模块被配置为，将所述第一延时控制信号设置得晚于所述第一图像显示控制信号预定时间，所述预定时间根据所述重排 有效行部分在所述重排图像数据中的位置得到，或者所述预定时间通过所述预设得到。
  14. 根据权利要求10所述的显示控制装置，还包括控制装置，其中，所述控制装置被配置为，响应于显示控制指令，选择进行所述第一显示模式或进行第二显示模式，
    其中，所述第二显示模式不同于所述第一显示模式，所述第一显示模式包括使用所述重排图像数据、所述图像显示控制信号和所述第一延时控制信号，在所述显示面板进行所述显示操作。
  15. 根据权利要求14所述的显示控制装置，其中，
    所述时序产生模块还被配置为，对应所述输入图像数据，产生第二图像显示控制信号，
    其中，所述第二图像显示控制信号用于在所述显示操作过程中对应于所述输入图像数据进行帧显示；
    所述第二显示模式包括使用所述输入图像数据和所述图像显示控制信号，在所述显示面板进行所述显示操作；
    所述输出电路还被配置为，输出所述输入图像数据和所述第二图像显示控制信号，用于在所述显示面板进行所述第二显示模式的显示操作。
  16. 根据权利要求14所述的显示控制装置，还包括：
    第二存储装置，
    其中，所述第二存储装置被配置为存储分别对应于所述第一显示模式的第一可执行代码和对应于所述第二显示模式的第二可执行代码，
    所述显示控制装置还被配置为，响应于所述显示控制指令指示，根据所述显示控制指令，选择执行所述第一可执行代码或第二可执行代码。
  17. 根据权利要求14所述的显示控制装置，还包括输入端口，
    其中，所述输入端口被配置为根据所述输入端口的不同状态来获取所述显示控制指令。
  18. 根据权利要求10-17任一所述的显示控制装置，还包括第一存储装置，
    其中，所述第一存储装置被配置为用于存储接收到的所述输入图像数据。
  19. 一种显示装置，包括：
    根据权利要求10-18任一所述的显示控制装置，以及
    所述显示面板。
  20. 根据权利要求19所述的显示装置，其中，所述显示面板包括栅极驱动电路、数据驱动电路和像素阵列，
    所述栅极驱动电路配置为接收扫描控制信号对所述像素阵列进行扫描；
    所述数据驱动电路配置为接收图像数据信号并将所述图像数据信号提供给所述像素阵列；
    所述像素阵列配置为在所述栅极驱动电路的控制下从所述数据驱动电路接收所述图像数据以进行显示操作，
    其中，所述第一图像显示控制信号包括所述扫描控制信号，所述图像数据信号包括所述重排图像数据。
PCT/CN2021/115812 2021-08-31 2021-08-31 显示控制方法、显示控制装置和显示装置 WO2023028885A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08179739A (ja) * 1994-12-20 1996-07-12 Sharp Corp 表示装置
US6747693B1 (en) * 1999-03-09 2004-06-08 Mitsubishi Denki Kabushiki Kaisha Imaging apparatus and method with upside-down mode and normal mode transitioning
JP2005316462A (ja) * 2005-04-01 2005-11-10 Ricoh Co Ltd 通信装置
GB2455306A (en) * 2007-12-04 2009-06-10 Hexa Chain Co Ltd Vehicle display connection arrangement inverting image if required
CN102646009A (zh) * 2011-02-21 2012-08-22 中兴通讯股份有限公司 一种终端的图像显示方法及系统
US20170110085A1 (en) * 2015-10-16 2017-04-20 Samsung Electronics Co., Ltd. Methods of operating application processors and display systems
CN113038235A (zh) * 2021-03-17 2021-06-25 福建捷联电子有限公司 一种通过反转扫描消除拼接电视墙动态画面断裂的方法及系统

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08179739A (ja) * 1994-12-20 1996-07-12 Sharp Corp 表示装置
US6747693B1 (en) * 1999-03-09 2004-06-08 Mitsubishi Denki Kabushiki Kaisha Imaging apparatus and method with upside-down mode and normal mode transitioning
JP2005316462A (ja) * 2005-04-01 2005-11-10 Ricoh Co Ltd 通信装置
GB2455306A (en) * 2007-12-04 2009-06-10 Hexa Chain Co Ltd Vehicle display connection arrangement inverting image if required
CN102646009A (zh) * 2011-02-21 2012-08-22 中兴通讯股份有限公司 一种终端的图像显示方法及系统
US20170110085A1 (en) * 2015-10-16 2017-04-20 Samsung Electronics Co., Ltd. Methods of operating application processors and display systems
CN113038235A (zh) * 2021-03-17 2021-06-25 福建捷联电子有限公司 一种通过反转扫描消除拼接电视墙动态画面断裂的方法及系统

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