WO2023024212A1 - 一种埋阻电路板及加工方法 - Google Patents

一种埋阻电路板及加工方法 Download PDF

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Publication number
WO2023024212A1
WO2023024212A1 PCT/CN2021/121086 CN2021121086W WO2023024212A1 WO 2023024212 A1 WO2023024212 A1 WO 2023024212A1 CN 2021121086 W CN2021121086 W CN 2021121086W WO 2023024212 A1 WO2023024212 A1 WO 2023024212A1
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Prior art keywords
substrate
resistor
buried
conductive
resistance
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PCT/CN2021/121086
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English (en)
French (fr)
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冷科
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深南电路股份有限公司
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Application filed by 深南电路股份有限公司 filed Critical 深南电路股份有限公司
Priority to US17/565,465 priority Critical patent/US20230064497A1/en
Publication of WO2023024212A1 publication Critical patent/WO2023024212A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor

Definitions

  • the present application provides a buried resistance circuit board and a processing method thereof, so as to solve the problems of low precision and low yield of buried resistance caused by the existing buried resistance method.
  • the conductive circuit layer includes a plurality of conductive circuits, and the two ends of the resistor are respectively electrically connected to at least two different conductive circuits.
  • the resistor embedded in the substrate is flush with the surface of the substrate.
  • the resistor includes at least one of conductive ink, carbon oil, conductive resin, and conductive metal paste.
  • another technical solution adopted by the present application is to provide a processing method for a buried resistance circuit board, including: providing a substrate, the surface of which is provided with a conductive metal layer; opening a buried resistance groove on the substrate, and The resistance is embedded in the buried resistance groove; the conductive metal layer on the substrate is etched to obtain a conductive circuit layer; wherein, the conductive circuit layer is electrically connected to the resistor.
  • opening a buried resistance trench on the substrate, and before the step of embedding the resistance in the buried resistance trench, further includes: etching the first conductive metal layer, so that the substrate in the region corresponding to the buried resistance trench is exposed.
  • the step of opening a buried resistance groove on the substrate, and embedding the resistor in the buried resistance groove it also includes: polishing the surface of the substrate on the side of the first conductive metal layer, so that the surface of the substrate and the resistance are smooth .
  • the application provides a buried resistance circuit board and a processing method, by setting up a buried resistance groove on the substrate, and embedding a resistor in the buried resistance groove, a circuit board including a built-in resistor circuit board.
  • a buried resistance groove By opening the buried resistance groove, it is very easy to realize high-precision control of the shape and thickness of the buried resistance, realize ultra-high precision of buried resistance, and easily realize high-precision batch processing.
  • the resistance is built into the substrate, so during the lamination process, there will be no cracks and large deformation after lamination due to the unevenness of the buried resistance layer, thereby improving the circuit board. reliability and yield.
  • Fig. 1 is the schematic flow sheet of one embodiment of the processing method of the embedded resistance circuit board provided by the present application
  • Fig. 2a-Fig. 2h are schematic flow charts of another embodiment of the processing method of buried resistance circuit board provided by the present application.
  • Fig. 3 is a schematic cross-sectional view of Fig. 2h along the a-a' direction.
  • first”, “second”, and “third” in this application are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, features defined as “first”, “second”, and “third” may explicitly or implicitly include at least one of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise specifically defined. All directional indications (such as up, down, left, right, front, back%) in the embodiments of the present application are only used to explain the relative positional relationship between the various components in a certain posture (as shown in the drawings) , sports conditions, etc., if the specific posture changes, the directional indication also changes accordingly.
  • the circuit board in this application may be a flexible circuit board, a rigid circuit board or a rigid-flex circuit board.
  • Fig. 1 is a schematic flow chart of an embodiment of a processing method for a buried resistance circuit board provided by the present application, specifically including:
  • Step S101 providing a substrate, the surface of which is provided with a conductive metal layer.
  • the substrate may be a rigid substrate or a flexible substrate.
  • the rigid substrate can be made of an insulating material, such as a resin material.
  • the reinforced material is impregnated with resin adhesive, and is made by drying, cutting, laminating and other processes.
  • the flexible substrate may include a substrate formed of a PI (Polyimide, polyimide) substrate or a PET (Polyethylene terephthalate, terephthalic acid and ethylene glycol) substrate.
  • the conductive metal layer on the surface of the substrate includes a conductive metal layer on one side surface, and also includes a conductive metal layer on both sides of the substrate.
  • the material of the conductive metal layer may include but not limited to copper, aluminum, iron, nickel, gold, silver, platinum group, chromium, magnesium, tungsten, molybdenum, lead, tin, indium, zinc or alloys thereof.
  • Step S102 Opening a buried resistance trench on the substrate, and embedding a resistor in the buried resistance trench.
  • a buried resistor groove is opened on the substrate, and the shape of the buried resistor groove is determined according to the shape or pattern of the embedded resistor.
  • the bottom of the buried resistance groove is flush with one side of the substrate, that is, the bottom of the buried resistance groove is in contact with the conductive metal layer on one side of the substrate.
  • the embedded resistance paste can be embedded in the buried resistance groove, and the embedded resistance paste can be solidified to realize embedding the resistance in the buried resistance groove.
  • the buried resist paste may include at least one of conductive ink, carbon oil, conductive resin, and conductive metal paste. That is, the embedded resist paste can be one of conductive ink, carbon oil, conductive resin, and conductive metal paste, or a combination of several of them. Specifically, when it is a combination of several kinds of them, various kinds of slurries can be mixed and configured according to a certain ratio to obtain the required buried resistance slurry.
  • the conductive metal paste may be metal paste such as copper paste or silver paste.
  • the method of embedding the buried resist paste may include but not limited to: 3D printing, traditional screen/stencil screen printing, laser window scraping and other methods for attaching the isolation layer.
  • the method of curing the buried resist paste may be baking and heating to cure the buried resist paste. The specific curing method needs to be determined according to the properties of the buried resist paste.
  • Step S103 Etching the conductive metal layer on the substrate to obtain a conductive circuit layer; wherein the conductive circuit is electrically connected to the resistor.
  • the resistor After embedding the resistor in the substrate, the resistor is in contact with the conductive metal layer. Then, the conductive metal layer is etched to obtain a conductive circuit layer, and the conductive circuit layer is electrically connected to the resistor to realize the resistance function.
  • a circuit board including built-in resistors is obtained by opening buried resistor grooves on the substrate and embedding resistors in the buried resistor grooves.
  • the buried resistance groove By setting up the buried resistance groove, it is very easy to realize high-precision control of the shape and thickness of the buried resistance, realize ultra-high precision of buried resistance, and the precision of buried resistance can reach ⁇ 8%, and it is easy to realize high-precision batch processing.
  • the resistance is built into the substrate, so during the lamination process, there will be no cracks and large deformation after lamination due to the unevenness of the buried resistance layer, thereby improving the circuit board. reliability and yield.
  • the embedded resistance circuit board prepared by the processing method of this embodiment also greatly reduces the cost.
  • Step 1 Referring to FIG. 2 a , a substrate 210 is provided, and a first conductive metal layer 221 and a second conductive metal layer 222 are respectively provided on two sides of the substrate 210 .
  • Step 2 Etching the first conductive metal layer 221 to expose the substrate 210 corresponding to the buried resistance groove 211 .
  • the shape of the buried resistance trench 211 matches the pattern or shape of the preset buried resistor 230, and the depth of the buried resistance trench 211 is the same as the thickness of the substrate 210, so that the bottom of the buried resistance trench 211 is in contact with the substrate 210 and the second conductive metal
  • the connection surfaces of the layers 222 are on the same plane, so that the buried resistor 230 is in contact with the second conductive metal layer 222 .
  • all the metal of the first conductive metal layer 221 except the positioning part can be etched away.
  • the etching-removed area of the first conductive metal layer 221 needs to include not only the area corresponding to the buried resistance trench 211 , but also at least the area required for the subsequent grinding process. That is to say, the etching removal area of the first conductive metal layer 221 should be large enough to support the grinding equipment for grinding.
  • step S102 Please refer to FIG. 2c-FIG. 2d.
  • step S102 Please refer to the specific description of step S102, which will not be repeated here.
  • Step 4 Grinding the surface of the substrate 210 on the side of the first conductive metal layer 221 to make the surfaces of the substrate 210 and the resistor 230 flat.
  • the thickness of the resistor 230 is slightly larger than the thickness of the substrate 210, that is to say, the surface of the resistor 230 higher than the substrate 210 is in a raised state.
  • the raised portion of the resistor 230 relative to the surface of the substrate 210 is removed by grinding, so that the surface of the substrate 210 on the side of the first conductive metal layer 221 is in contact with the surface of the resistor 230. Flattening so that both surfaces are on the same level.
  • the thickness of the embedded resistor 230 is greater than that of the substrate 210, and then it is polished to make the two surfaces smooth, so as to avoid the thickness of the resistor 230 being small due to processing conditions and processing errors, so that the corresponding part of the resistor 230 in the embedded resistor plate is sunken, and at the same time
  • the grinding process also avoids the protrusion of the resistor 230, so as to avoid cracks and large deformation after lamination due to the unevenness of the buried resistance layer including the resistor 230 during the lamination process, thereby improving the reliability and reliability of the circuit board. Yield rate.
  • ceramic grinding or sand belt grinding can be used for grinding.
  • the surface has good flatness and no residue, and the surface pits are less than 5 microns.
  • the surface of the substrate 210 on the side of the first conductive metal layer 221 can also be polished. Metal plating is performed on the surface of the substrate 210, and pattern transfer is performed to obtain corresponding conductive circuits.
  • Step 5 developing and etching the second conductive metal layer 222 to obtain a conductive circuit layer, which is electrically connected to the resistor 230 .
  • the buried resistance groove 211 ensures the accuracy of the pattern and shape of the embedded resistor 230, and ensures that the embedded resistor 230 is in the plane direction of the substrate 210 and parallel to the substrate. 210 accuracy in the plane direction.
  • the laser method has better engraving accuracy. Using laser technology to open the buried resistance groove 211 on the substrate 210 can obtain a high-precision buried resistance groove 211, which further improves the resistance of the buried resistance 230 in the plane direction of the substrate 210 and parallel to the substrate. 210 accuracy in the plane direction.
  • the surface of the resistor 230 is flush with the surface of the substrate 210, which ensures the smoothness of the surface of the resistor 230 and the surface of the substrate 210, and improves the resistance of the embedded resistor 230 in the vertical direction.
  • the accuracy in the plane direction of the substrate 210 Through this embodiment, high-precision control of the shape and thickness of the buried resistor 210 is realized, ultra-high precision of the buried resistor is realized, and high-precision batch processing is easily realized.
  • the resistor 230 is built in the substrate 210, so during the lamination process, there will be no cracks and large deformation after lamination due to the unevenness of the buried resistance layer, thereby improving the Board reliability and yield.
  • the matching is performed, and the two sides of the buried resistance layer are respectively an insulating layer 240 and an outer conductive metal layer 250.
  • the insulating layer 240 mainly plays an insulating role, and in this embodiment, mainly plays an insulating role between the buried resistance layer and other circuit layers.
  • the insulating layer can be made of prepreg (also known as prepreg or pp), or it can be made of other insulating materials.
  • pattern transfer is performed on the outer conductive metal layer 250 after lamination to form an outer conductive circuit layer to obtain a buried resistance circuit board.
  • the buried resistance layer Before lamination, the buried resistance layer can also be browned, so that a dense organic browned film is formed on the surface of the metal layer or the conductive circuit layer, so as to increase the bonding force between the metal layer and the insulating layer 240 .
  • only one side surface of the substrate is respectively provided with a conductive metal layer, the side surface without the conductive metal layer is the first surface of the substrate, and the side surface with the conductive metal layer is the second surface of the substrate.
  • the first surface of the substrate is not covered by the conductive metal layer, and the substrate in the region corresponding to the buried resistance groove is exposed, so no etching process is required.
  • FIG. 2a-FIG. 2h reference may be made to the corresponding descriptions in FIG. 2a-FIG. 2h.
  • Figure 2h is a schematic structural diagram of the buried resistance circuit diagram obtained through the processing method of the buried resistance circuit diagram provided by the present application
  • Figure 3 is a diagram along a-a in Figure 2h 'direction cross-sectional schematic.
  • the embedded resistance circuit board includes a substrate 210 and a conductive circuit layer disposed on the surface of the substrate 210, wherein the conductive circuit layer corresponds to the second conductive metal layer 222 in FIG. 2h.
  • a resistor 230 is embedded in the substrate 210, and the resistor 230 is electrically connected to the conductive circuit layer.
  • the substrate 210 may be a rigid substrate or a flexible substrate.
  • the rigid substrate can be made of an insulating material, such as a resin material.
  • the reinforced material is impregnated with resin adhesive, and is made by drying, cutting, laminating and other processes.
  • the flexible substrate may include a substrate formed of a PI (Polyimide, polyimide) substrate or a PET (Polyethylene terephthalate, terephthalic acid and ethylene glycol) substrate.
  • the resistor 230 can be made of at least one of conductive ink, carbon oil, conductive resin, and conductive metal paste. That is, the resistor 230 can be made of one of conductive ink, carbon oil, conductive resin, and conductive metal paste, or can be made of a combination of them. Specifically, when it is a combination of multiple types of them, multiple types of slurries can be mixed and configured according to a certain ratio to obtain the required embedded resistance slurry, and the resistor 230 can be made.
  • the conductive metal paste may be metal paste such as copper paste or silver paste.
  • the resistor 13 embedded in the substrate 11 is flush with the surface of the substrate.
  • the buried resistance circuit board further includes an insulating layer 240 disposed on the surface of the substrate 210 and the second conductive metal layer (conductive circuit layer) 222 .
  • An outer conductive metal layer 250 is disposed on the insulating layer 240 .
  • the insulating layer 240 mainly plays an insulating role, and in this embodiment, mainly plays an insulating role between the buried resistance layer and other circuit layers.
  • the insulating layer can be made of prepreg (also known as prepreg or pp), or it can be made of other insulating materials.
  • the resistor 230 by embedding the resistor 230 in the substrate 210 , it is very easy to realize high-precision control of the shape and thickness of the embedded resistor 230 , realize ultra-high precision of embedded resistance, and easily realize high-precision mass processing. In the lamination process, there will be no cracks and large deformation after lamination due to the unevenness of the buried resistance layer, thereby improving the reliability and yield of the circuit board.

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Abstract

本申请提供一种埋阻电路板及加工方法，通过在基板上开设埋阻槽，并在埋阻槽内埋入电阻，得到包含内置电阻的电路板。通过开设埋阻槽，能够非常容易实现对埋设电阻形状以及厚度的高精度控制，实现超高的埋阻精度，且容易实现高精度批量化加工。在埋阻层中，电阻是内置在基板中的，那么在压合过程中，也就不会因为埋阻层的凹凸不平而导致压合后出现裂纹以及较大的变形，从而提高了电路板可靠性和良品率。

Description

一种埋阻电路板及加工方法 技术领域
本申请涉及电路板技术领域，特别涉及一种埋阻电路板及加工方法。
背景技术
随着电子产品小型化的趋势不断加速，将电容、电阻甚至芯片等器件内置于电路板中已经成为新趋势，尤其是高速高频产品领域。由于内置电阻没有寄生电感，阻值精度远高于分离式焊接电阻的精度，因此在高频高速应用中有广泛的应用前景。
传统的内置电阻主要有平面埋阻和内置潜入分离式电阻两种方式，但这两种方式的内置埋阻都难以实现高。平面埋阻的埋阻层薄，厚度极难进行批量化准确控制，在电路板的制程中很容易出现埋阻层裂纹，压合过程变形量大，厚度无法满足抗拉裂的基本要求，进而影响了埋阻的最终精度。电路板中内置分离式电阻的填胶问题导致电路板存在可靠性的风险，电路板良品率低。
发明内容
本申请提供一种埋阻电路板及其加工方法，以解决现有埋阻方式导致埋阻精度不高、良品率低的问题。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种埋阻电路板，包括：基板和设置在基板表面的导电线路层，其中，基板内埋设有电阻，电阻与导电线路层电连接。
可选地，导电线路层包括多个导电线路，电阻两端分别与至少两个不同的导电线路电连接。
可选地，埋设在基板内的电阻与基板表面平齐。
可选地，电阻包括导电油墨、碳油、导电树脂、导电金属浆中的至 少一种。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种埋阻电路板的加工方法，包括：提供基板，基板表面设置有导电金属层；在基板上开设埋阻槽，并在埋阻槽内埋入电阻；对基板上的导电金属层进行蚀刻，得到导电线路层；其中，导电线路层与电阻电连接。
可选地，提供基板，基板表面设置有导电金属层的步骤，包括：提供基板，基板的两侧表面分别设有第一导电金属层和第二导电金属层。
可选地，在所述基板上开设埋阻槽，并在埋阻槽内埋入电阻的步骤之前，还包括：对第一导电金属层进行蚀刻，以使埋阻槽对应区域的基板外露。
可选地，在基板上开设埋阻槽，并在埋阻槽内埋入电阻的步骤之后，还包括：对第一导电金属层一侧的基板表面进行打磨处理，以使得基板与电阻表面平整。
可选地，对基板上的导电金属层进行蚀刻，得到导电线路层的步骤，包括：对第二导电金属层进行显影蚀刻，得到导电线路层，导电线路层与电阻电连接。
可选地，在基板上开设埋阻槽，并在埋阻槽内埋入电阻的步骤，包括：通过镭射技术在基板上开设埋阻槽；在埋阻槽内埋入埋阻浆，固化埋阻浆。
本申请的有益效果是：区别于现有技术的情况，本申请提供一种埋阻电路板及加工方法，通过在基板上开设埋阻槽，并在埋阻槽内埋入电阻，得到包含内置电阻的电路板。通过开设埋阻槽，能够非常容易实现对埋设电阻形状以及厚度的高精度控制，实现超高的埋阻精度，且容易实现高精度批量化加工。在埋阻层中，电阻是内置在基板中的，那么在压合过程中，也就不会因为埋阻层的凹凸不平而导致压合后出现裂纹以及较大的变形，从而提高了电路板可靠性和良品率。
附图说明
图1是本申请提供的埋阻电路板的加工方法一实施例的流程示意 图；
图2a-图2h是本申请提供的埋阻电路板的加工方法另一实施例的流程示意图；
图3是图2h沿a-a’方向的截面示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，在不冲突的情况下，本文所描述的实施例可以与其它实施例相结合。下面通过具体实施例，分别进行详细的说明。
本申请中的电路板，可以为柔性电路板、硬性电路板或者软硬结合电路板。
参阅图1，图1是本申请提供的埋阻电路板的加工方法一实施例的流程示意图，具体包括：
步骤S101：提供基板，基板表面设置有导电金属层。
其中，基板可以为硬性基板，也可以为柔性基板。具体他，硬性基板可以采用绝缘材料制成，例如可以由树脂材料制成。用增强材料浸以树脂胶黏剂，通过烘干、裁剪、叠合等工艺制成。软性基板可以包括由PI(Polyimide，聚酰亚胺)基材或者PET(Polyethylene terephthalate，对苯二甲酸与乙二醇)基材形成基板。
一般而言，基板的两侧表面均设置有导电金属层较为常见，但在本申请中，基板表面设置有导电金属层包括单侧表面具有导电金属层，也包括双侧表面均具有导电金属层。导电金属层的材质则可以包括但不限于铜、铝、铁、镍、金、银、铂族、铬、镁、钨、钼、铅、锡、铟、锌或其合金等材料。
步骤S102：在基板上开设埋阻槽，并在埋阻槽内埋入电阻。
在基板上开设埋阻槽，埋阻槽的形状根据需要埋入电阻的形状或者说图形确定。埋阻槽的底部与基板的一侧表面平齐，即埋阻槽的底部与基板一侧的导电金属层相接触。在埋阻槽内埋入电阻后，使得电阻与导电金属层接触实现电连接，从而能够支持电阻实现其电阻功能。
在一个具体实施例中，可以按照埋阻图形，通过镭射技术在基板上开设埋阻槽。具体地，镭射方式可以选择UV、皮秒切割或CO2等方式，上述镭射方式均可以使得雕刻精度达到±5μm。可以理解的是，能够使得开槽的精度达到±5μm的其他常见开槽方式或方法，可以在本申请中进行应用，以开设埋阻槽。
在基板上开设埋阻槽后，可以通过在埋阻槽内埋入埋阻浆，使埋阻浆固化实现在埋阻槽内埋入电阻。其中，埋阻浆可以为包括导电油墨、 碳油、导电树脂、导电金属浆中的至少一种。即埋阻浆可以为导电油墨、碳油、导电树脂、导电金属浆中的其中一种，也可以为其中多种的组合。具体地，在为其中多种的组合时，可以按照一定的比例将其中多种浆料进行混合配置得到需要的埋阻浆。其中，导电金属浆可以为铜浆或者银浆等金属浆。埋入埋阻浆的方法可以包含但不限于：3D打印、传统丝网/钢网丝印、贴隔离层激光开窗刮印等方式。使埋阻浆固化的方式可以为烘烤加热来使埋阻浆固化。具体地固化方式需要根据埋阻浆的性质进行确定。
步骤S103：对基板上的导电金属层进行蚀刻，得到导电线路层；其中，导电线路与电阻电连接。
在基板中埋入电阻后，电阻与导电金属层处于接触连接状态。然后对导电金属层进行蚀刻，得到导电线路层，导电线路层与电阻电连接，实现电阻功能。
本实施例中，通过在基板上开设埋阻槽，并在埋阻槽内埋入电阻，得到包含内置电阻的电路板。通过开设埋阻槽，能够非常容易实现对埋设电阻形状以及厚度的高精度控制，实现超高的埋阻精度，埋阻精度达到±8％，且容易实现高精度批量化加工。在埋阻层中，电阻是内置在基板中的，那么在压合过程中，也就不会因为埋阻层的凹凸不平而导致压合后出现裂纹以及较大的变形，从而提高了电路板可靠性和良品率。另外，本实施例的加工方法制备得到的埋阻电路板也大大降低了成本。
进一步，请参阅图2a-图2h。图2a-图2h是本申请提供的埋阻电路板的加工方法另一实施例的流程示意图，具体包括：
步骤一、参阅图2a，提供基板210，基板210的两侧表面分别设有第一导电金属层221和第二导电金属层222。
步骤二、对第一导电金属221层进行蚀刻，以使埋阻槽211对应区域的基板210外露。
请参阅图2b-图2c，在对基板210进行开设埋阻槽211之前，需要先对基板210一侧表面的第一导电金属层221进行蚀刻，去掉埋阻槽211对应区域的金属层，使得埋阻槽211对应区域的基板210外露。然后对外露的基材210进行开槽处理。其中，埋阻槽211的形状与预设埋入电阻230的图形或者形状匹配，而埋阻槽211的深度则与基板210厚度相同，使得埋阻槽211的底部与基板210与第二导电金属层222的连接面为同一平面，从而使得埋入的电阻230与第二导电金属层222接触连接。
在一个具体实施例中，可以将第一导电金属层221除了定位部分之外的金属全部蚀刻去除。在其他具体实施例中，第一导电金属层221的蚀刻去除区域除了需要包括埋阻槽211对应区域外，还至少需要满足后续进行打磨处理的所需要的区域。也就是说，第一导电金属层221的蚀刻去除区域要足够大，以支持打磨设备进行打磨处理。
步骤三、在基板210上开设埋阻槽211，并在埋阻槽211内埋入电阻230。
请参阅图2c-图2d，此步骤参考步骤S102的具体描述，此处不进行赘述。
步骤四、对第一导电金属层221一侧的基板210表面进行打磨处理，以使得基板210与电阻230表面平整。
参阅图2d-图2e，在上一步骤中，埋入电阻230后，电阻230的厚度稍大于基板210厚度，也就是说，此时电阻230的高于基板210的表面，处于凸起状态。通过对第一导电金属层221一侧的基板210表面进行打磨处理，打磨去除电阻230相对于基板210表面的凸起部分，从而使得第一导电金属层221一侧的基板210表面与电阻230表面平整，实现两表面在同一水平面上。埋入的电阻230厚度大于基板210厚度，再进行打磨处理使两表面平整的处理，避免因为加工条件以及加工误差等原因导致电阻230厚度小，使埋阻板中电阻230对应部分出现凹陷，同时打磨处理也避免电阻230凸起，从而避免在压合过程中，因包括有电阻230的埋阻层凹凸不平，而导致压合后出现裂纹以及较大的变形，进而提高了电路板可靠性和良品率。
在本步骤中，打磨处理可以使用陶瓷研磨或者沙带研磨的方式，打磨后表面平整性好且无残留，表面凹坑小于5微米。
在其他具体实施例中，根据电路板上电路设计需求，可以在对第一导电金属层221一侧的基板210表面进行打磨处理使表面平整之后，还可以对第一导电金属层221一侧的基板210表面进行电镀金属，以及进行图形转移，得到对应的导电线路。
步骤五、对第二导电金属层222进行显影蚀刻，得到导电线路层，导电线路层与电阻230电连接。
参阅图2f，对基板210另一表面的第二导电金属层222进行显影蚀刻，即图形转移，得到导电线路层，导电线路层与电阻电连接。具体地，导电线路层包括有多条导电线路，但两条或者多条导线线路之间可以通过此电阻230实现电连接，从而实现电阻的功能，即阻碍电流。具体地，与电阻230电连接的可以为导电线路中的铜PAD。为便于描述，将图2f中的电路板结构称为埋阻层。
本实施例中，通过在基板210上开设埋阻槽211，埋阻槽211保证了埋入电阻230的图形和形状的精度，保证了埋入的电阻230在基板210平面方向上以及平行于基板210平面方向上的精度。进一步，镭射方式具有较好的雕刻精度，使用镭射技术在基板210上开设埋阻槽211能够得到精度高的埋阻槽211，进一步提高了埋入电阻230在基板210平面方向上以及平行于基板210平面方向上的精度。而通过对埋入电阻230后的基板210表面进行打磨处理，使得电阻230表面与基板210表面相平齐，保证了电阻230表面与基板210表面的平整性，提高了埋入电阻230在垂直于基板210平面方向上的精度。通过本实施例，实现对埋设电阻210形状以及厚度的高精度控制，实现超高的埋阻精度，且容易实现高精度批量化加工。在埋阻层中，电阻230是内置在基板210中的，那么在压合过程中，也就不会因为埋阻层的凹凸不平而导致压合后出现裂纹以及较大的变形，从而提高了电路板可靠性和良品率。
在一个具体实施例中，参阅图2g-图2h，在对第二导电金属层222进行显影蚀刻之后，进行配板，埋阻层两侧依次分别为绝缘层240、外 层导电金属层250，并按照图2g的顺序进行压合。其中，绝缘层240主要起到绝缘作用，在此实施例中，主要是在埋阻层与其他电路层之间起到绝缘作用。绝缘层可以为半固化片(又称prepreg或pp)制成，也可以使用其他绝缘材料制成。参阅图2h，压合后对外层导电金属层250进行图形转移，形成外层导电线路层，得到埋阻电路板。
在进行压合之前，还可以对埋阻层进行棕化，使金属层或者说导电线路层表面生成一层致密的有机棕化膜，以增加金属层与绝缘层240之间的结合力。
在另一实施例中，基板仅有一侧表面分别设有导电金属层，无导电金属层的一侧表面为基板第一表面，有导电金属层的一侧表面为基板第二表面。与上一实施例相比，基板第一表面上无导电金属层覆盖，埋阻槽对应区域的基板外露，可以不用进行蚀刻处理。其他步骤均可以参考图2a-图2h对应的描述。
本申请还提供一种埋阻电路板，参阅图2h和图3，图2h是通过本申请提供的埋阻电路图的加工方法得到的埋阻电路图的结构示意图，图3是图2h沿a-a’方向的截面示意图。
本实施例中，埋阻电路板包括基板210和设置在基板210表面的导电线路层，其中导电线路层与图2h中的第二导电金属层222对应。在其中，基板210内埋设有电阻230，电阻230与导电线路层电连接。
其中基板210可以为硬性基板，也可以为柔性基板。具体他，硬性基板可以采用绝缘材料制成，例如可以由树脂材料制成。用增强材料浸以树脂胶黏剂，通过烘干、裁剪、叠合等工艺制成。软性基板可以包括由PI(Polyimide，聚酰亚胺)基材或者PET(Polyethylene terephthalate，对苯二甲酸与乙二醇)基材形成基板。
导电线路层的材质则可以包括但不限于铜、铝、铁、镍、金、银、铂族、铬、镁、钨、钼、铅、锡、铟、锌或其合金等材料。其中，导电线路层可以包括多个导电线路，电阻230的两端分别与至少两个不同的导电线路电连接，从而使电阻230连接不同的导电线路，实现电阻功能。
电阻230可以由包括导电油墨、碳油、导电树脂、导电金属浆中的 至少一种制成。即电阻230可以为导电油墨、碳油、导电树脂、导电金属浆中的其中一种制成，也可以为其中多种的组合制成。具体地，在为其中多种的组合时，可以按照一定的比例将其中多种浆料进行混合配置得到需要的埋阻浆，并制成电阻230。其中，导电金属浆可以为铜浆或者银浆等金属浆。
进一步地，埋设在基板11内的电阻13与基板表面平齐。
在一个具体实施例中，埋阻电路板还包括设置在基板210以及第二导电金属层(导电线路层)222表面的绝缘层240。绝缘层240上设有外层导电金属层250。其中，绝缘层240主要起到绝缘作用，在此实施例中，主要是在埋阻层与其他电路层之间起到绝缘作用。绝缘层可以为半固化片(又称prepreg或pp)制成，也可以使用其他绝缘材料制成。
本实施例中，通过将电阻230埋入基板210中，能够非常容易实现对埋设电阻230形状以及厚度的高精度控制，实现超高的埋阻精度，且容易实现高精度批量化加工。在压合过程中，也就不会因为埋阻层的凹凸不平而导致压合后出现裂纹以及较大的变形，从而提高了电路板可靠性和良品率。
以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

  1. 一种埋阻电路板，其特征在于，包括：
    基板和设置在基板表面的导电线路层，其中，所述基板内埋设有电阻，所述电阻与所述导电线路层电连接。
  2. 根据权利要求1所述的埋阻电路板，其特征在于，所述导电线路层包括多个导电线路，所述电阻两端分别与至少两个不同的所述导电线路电连接。
  3. 根据权利要求1所述的埋阻电路板，其特征在于，埋设在所述基板内的所述电阻与所述基板表面平齐。
  4. 根据权利要求1所述的埋阻电路板，其特征在于，所述电阻包括导电油墨、碳油、导电树脂、导电金属浆中的至少一种。
  5. 一种埋阻电路板的加工方法，其特征在于，包括：
    提供基板，所述基板表面设置有导电金属层；
    在所述基板上开设埋阻槽，并在所述埋阻槽内埋入电阻；
    对所述基板上的所述导电金属层进行蚀刻，得到导电线路层；其中，所述导电线路层与所述电阻电连接。
  6. 根据权利要求5所述的加工方法，其特征在于，所述提供基板，所述基板表面设置有导电金属层的步骤，包括：
    提供所述基板，所述基板的两侧表面分别设有第一导电金属层和第二导电金属层。
  7. 根据权利要求6所述的加工方法，其特征在于，所述在所述基板上开设埋阻槽，并在所述埋阻槽内埋入电阻的步骤之前，还包括：
    对第一导电金属层进行蚀刻，以使所述埋阻槽对应区域的所述基板外露。
  8. 根据权利要求7所述的加工方法，其特征在于，所述在所述基板上开设埋阻槽，并在所述埋阻槽内埋入电阻的步骤之后，还包括：
    对所述第一导电金属层一侧的所述基板表面进行打磨处理，以使得所述基板与所述电阻表面平整。
  9. 根据权利要求6所述的加工方法，其特征在于，所述对所述基板上的所述导电金属层进行蚀刻，得到导电线路层的步骤，包括：
    对所述第二导电金属层进行显影蚀刻，得到所述导电线路层，所述导电线 路层与所述电阻电连接。
  10. 根据权利要求5所述的加工方法，其特征在于，所述在所述基板上开设埋阻槽，并在所述埋阻槽内埋入电阻的步骤，包括：
    通过镭射技术在所述基板上开设所述埋阻槽；
    在所述埋阻槽内埋入埋阻浆，固化所述埋阻浆。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070194390A1 (en) * 2006-02-22 2007-08-23 Chinthakindi Anil K Method of fabricating a precision buried resistor
CN201797653U (zh) * 2010-09-17 2011-04-13 昆山华扬电子有限公司 内埋电阻的印制线路板
WO2014106331A1 (zh) * 2013-01-05 2014-07-10 上海卓凯电子科技有限公司 具有内埋式电阻的电路板
CN109640520A (zh) * 2018-12-10 2019-04-16 江门崇达电路技术有限公司 一种埋阻电路板的制作方法
CN110312365A (zh) * 2019-07-03 2019-10-08 安捷利电子科技（苏州）有限公司 一种具有埋阻的电路板以及埋阻的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070194390A1 (en) * 2006-02-22 2007-08-23 Chinthakindi Anil K Method of fabricating a precision buried resistor
CN201797653U (zh) * 2010-09-17 2011-04-13 昆山华扬电子有限公司 内埋电阻的印制线路板
WO2014106331A1 (zh) * 2013-01-05 2014-07-10 上海卓凯电子科技有限公司 具有内埋式电阻的电路板
CN109640520A (zh) * 2018-12-10 2019-04-16 江门崇达电路技术有限公司 一种埋阻电路板的制作方法
CN110312365A (zh) * 2019-07-03 2019-10-08 安捷利电子科技（苏州）有限公司 一种具有埋阻的电路板以及埋阻的方法

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