WO2023024104A1 - 显示面板、显示装置及其驱动方法 - Google Patents

显示面板、显示装置及其驱动方法 Download PDF

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Publication number
WO2023024104A1
WO2023024104A1 PCT/CN2021/115138 CN2021115138W WO2023024104A1 WO 2023024104 A1 WO2023024104 A1 WO 2023024104A1 CN 2021115138 W CN2021115138 W CN 2021115138W WO 2023024104 A1 WO2023024104 A1 WO 2023024104A1
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WIPO (PCT)
Prior art keywords
transistor
sub
display panel
pixel
line
Prior art date
Application number
PCT/CN2021/115138
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English (en)
French (fr)
Inventor
张慧
侯凯
王洪润
张舜航
刘立伟
林允植
李昌峰
李付强
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180002316.2A priority Critical patent/CN116034315A/zh
Priority to US17/788,113 priority patent/US20240169948A1/en
Priority to PCT/CN2021/115138 priority patent/WO2023024104A1/zh
Publication of WO2023024104A1 publication Critical patent/WO2023024104A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0414—Vertical resolution change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a display device and a driving method thereof.
  • ultra-high resolution display has become a possibility.
  • the display with a pixel density (PPI) of up to 3000 is no longer an illusion.
  • PPI pixel density
  • ultra-high Resolution display is not popular, so a partition-driven intelligent display mode is proposed, which displays the areas that human eyes focus on normally, and reduces the resolution and refresh frequency of other areas, which can not only deal with the problem of insufficient system resources, but also meet low power consumption requirements.
  • the display products in the prior art can only realize the function of driving the horizontal partition, but cannot realize the vertical partition.
  • a display panel provided by an embodiment of the present disclosure includes:
  • a plurality of scanning lines located on one side of the first substrate, the plurality of scanning lines extending along the first direction and arranged along the second direction; the first direction and the second direction intersect;
  • a plurality of data lines located on the same side of the first substrate as the scanning lines, extending along the second direction and arranged along the first direction;
  • a plurality of sub-pixels are respectively located in an area divided by a plurality of scanning lines and a plurality of data lines; at least two adjacent sub-pixels along the first direction and the second direction form a pixel island; a plurality of sub-pixels form a plurality of pixel islands; Each pixel island includes n rows of sub-pixel rows in the second direction;
  • a plurality of scanning signal input lines correspond to the scanning lines one by one, extending along the first direction and arranged along the second direction;
  • a plurality of control signal lines extending along the second direction and arranged along the first direction;
  • a plurality of control circuits are located between adjacent sub-pixels; a pixel island is correspondingly connected to at least n control circuits; a control circuit corresponds to a row of sub-pixels in the pixel island;
  • the control circuit is configured to transmit the signal provided by the scanning signal input line or the signal provided by the fixed potential line to the scanning line under the control of the control signal line.
  • control circuit includes: a first transistor and a second transistor;
  • the control electrode of the first transistor is electrically connected to a control signal line, the first electrode of the first transistor is electrically connected to the scanning signal input line, and the second electrode of the first transistor is electrically connected to the scanning line;
  • the control electrode of the second transistor is electrically connected to a control signal line
  • the first electrode of the second transistor is electrically connected to the fixed potential line
  • the second electrode of the second transistor is electrically connected to the scanning line.
  • control circuit is located between two adjacent sub-pixels in the first direction;
  • a plurality of fixed potential lines extend along the first direction and are arranged along the second direction.
  • the display panel specifically includes:
  • the first conductive layer includes a scan line, a scan signal input line, a fixed potential line, a control electrode of the first transistor, and a control electrode of the second transistor;
  • the second conductive layer located on the side of the first conductive layer away from the first substrate, includes data lines and control signal lines;
  • the third conductive layer located on the side of the second conductive layer away from the first conductive layer, includes the first pole and the second pole of the first transistor and the first pole and the second pole of the second transistor.
  • the sub-pixel includes a driving transistor; the first conductive layer further includes: a control stage of the driving transistor electrically connected to the scanning line;
  • the second conductive layer also includes: a first pole of the driving transistor
  • the third conductive layer further includes: a second pole of the driving transistor.
  • the first transistors and the second transistors are arranged in two rows along the first direction.
  • the orthographic projection of the control electrode of the first transistor on a plane perpendicular to the first direction and the orthographic projection of the control electrode of the second transistor on a plane perpendicular to the first direction are mutually disjoint. stack.
  • the first pole and the second pole of the first transistor are arranged along the second direction;
  • the first pole and the second pole of the second transistor are arranged along the second direction.
  • the third conductive layer further includes: a first input lead, a second input lead, a first output lead, and a second output lead;
  • the first input lead is electrically connected to the first electrode of the first transistor and is electrically connected to the scanning signal input line;
  • the second input lead is electrically connected to the first electrode of the second transistor and is electrically connected to the fixed potential line;
  • the first output lead is electrically connected to the second electrode of the first transistor and is electrically connected to the scanning line;
  • the second output lead is electrically connected to the second electrode of the second transistor and is electrically connected to the scan line;
  • the first input lead, the second input lead, the first output lead and the second output lead all extend along the second direction.
  • control circuit is located between two adjacent sub-pixels in the second direction;
  • a plurality of fixed potential lines extend along the second direction and are arranged along the first direction.
  • the display panel specifically includes:
  • the first conductive layer includes a scan line, a control electrode of the first transistor, and a control electrode of the second transistor;
  • the second conductive layer located on the side of the first conductive layer away from the first base substrate, includes a scanning signal input line;
  • the third conductive layer located on the side of the second conductive layer away from the first conductive layer, includes a data line
  • the fourth conductive layer located on the side of the third conductive layer away from the second conductive layer, includes a control signal line, a fixed potential line, the first pole and the second pole of the first transistor, and the first pole and the second pole of the second transistor. Pole; the orthographic projection of the control signal line fixed potential line on the first base substrate overlaps with the partial area of the orthographic projection of the data line on the first base substrate.
  • the fourth conductive layer further includes: a plurality of first output leads and a plurality of second output leads extending along the second direction;
  • the second pole of the first transistor is electrically connected to the scan line through the first output lead;
  • the second pole of the second transistor is electrically connected to the scan line through the second output lead;
  • the orthographic projections of the first output lead and the second output lead on the first substrate overlap with a partial area of the orthographic projection of the data line on the first substrate.
  • the subpixel includes a drive transistor
  • the first conductive layer further includes: a control stage of a driving transistor electrically connected to the scanning line;
  • the second conductive layer also includes: a first pole of the driving transistor
  • the display panel also includes:
  • the fifth conductive layer located on the side of the fourth conductive layer away from the third conductive layer, includes the second electrode of the driving transistor.
  • control circuits corresponding to each pixel island are arranged in a row along the first direction.
  • the first pole of the first transistor, the control stage of the first transistor, and the second pole of the first transistor are arranged along the first direction;
  • each second transistor the first pole of the second transistor, the control stage of the second transistor and the second pole of the second transistor are arranged along the first direction.
  • the display panel further includes: an active layer located between the first conductive layer and the first base substrate; the active layer includes an active layer of the first transistor and an active layer of the second transistor;
  • the active layer of the first transistor includes a portion extending in a first direction
  • the active layer of the second transistor includes a portion extending in the first direction.
  • the fourth conductive layer further includes: a plurality of first output leads and a plurality of second output leads extending along the second direction;
  • the second pole of the first transistor is electrically connected to the scan line through the first output lead;
  • the second pole of the second transistor is electrically connected to the scan line through the second output lead;
  • the orthographic projections of the first output lead and the second output lead on the first substrate overlap with a partial area of the orthographic projection of the data line on the first substrate.
  • the display panel further includes: a first gate insulating layer located between the first conductive layer and the active layer, a second gate insulating layer located between the first conductive layer and the second conductive layer, and a second gate insulating layer located between the first conductive layer and the active layer.
  • the first interlayer insulating layer between the second conductive layer and the third conductive layer, the second interlayer insulating layer between the third conductive layer and the fourth conductive layer, and the second interlayer insulating layer between the fourth conductive layer and the fifth conductive layer The third interlayer insulating layer between;
  • the fourth conductive layer further includes: a plurality of first connection pads, a plurality of second connection pads, a plurality of third connection pads, a plurality of fourth connection pads, and a plurality of fifth connection pads;
  • the second pole of the driving transistor is electrically connected to the active layer through a via hole penetrating through the third interlayer insulating layer, the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer ;
  • the first input lead is electrically connected to the first connection pad, and the first connection pad is electrically connected to the scanning signal input line through a via hole penetrating through the second interlayer insulating layer and the first interlayer insulating layer;
  • the first output lead is electrically connected to the second connection pad, and the second connection pad is electrically connected to the scan line through a via hole penetrating through the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer;
  • the first control signal line is electrically connected to the third connection pad, and the third connection pad is connected to the control stage of the first transistor through the via hole penetrating through the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer. electrical connection;
  • the second control signal line is electrically connected to the fourth connection pad, and the fourth connection pad is connected to the control level circuit of the second transistor through a via hole penetrating through the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer. connect;
  • the second output lead is electrically connected to the fifth connection pad, and the fifth connection pad is electrically connected to the scan line through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer;
  • the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer have a first via hole;
  • the first interlayer insulating layer and the second gate insulating layer have a second via hole;
  • the second pole of the driving transistor is electrically connected to the active layer and the second connecting pad is electrically connected to the scanning line.
  • the second interlayer insulating layer has a third via hole exposing the first via hole and the second via hole.
  • the display panel also includes:
  • the pixel electrode layer is located on the side of the fifth conductive layer away from the fourth conductive layer, and includes a plurality of pixel electrodes corresponding to the sub-pixels one by one; the pixel electrode is electrically connected to the second electrode of the driving transistor;
  • the common electrode layer is located on the side of the pixel electrode layer away from the fifth conductive layer;
  • a plurality of supporting parts are located on the side of the common electrode layer away from the pixel electrode layer, the orthographic projection of the supporting parts on the first base substrate is located between adjacent sub-pixel rows, and the control circuit is located between the sub-pixel rows provided with the supporting parts between;
  • the opposite substrate is located on the side of the support part away from the common electrode layer, and includes a plurality of light-shielding parts extending along the first direction and arranged along the second direction; The orthographic projection of the base substrate and the orthographic projection of the control circuit on the first base substrate.
  • each pixel island includes: a first row of sub-pixels, a second row of sub-pixels, and a third row of sub-pixels;
  • the first sub-pixel row includes a plurality of first-color sub-pixels arranged along a first direction;
  • the second sub-pixel row includes a plurality of second-color sub-pixels arranged along the first direction;
  • the third sub-pixel row includes a plurality of third-color sub-pixels arranged along the first direction;
  • the orthographic projection of the support portion on the base substrate is located between the first sub-pixel row and the third sub-pixel row.
  • the first color sub-pixel is a red sub-pixel
  • the second color sub-pixel is a green sub-pixel
  • the third color sub-pixel is a blue sub-pixel
  • control electrode of the first transistor and the control electrode of the second transistor are electrically connected to the same control signal line;
  • the first transistor is an N-type transistor, and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.
  • control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines.
  • the colors of a row of sub-pixels arranged in the first direction are all the same.
  • the plurality of pixel islands are divided into a plurality of control regions, each control region including at least one pixel island;
  • Each scanning line includes: a plurality of sub-scanning lines arranged in the first direction and disconnected from each other; in each scanning line, the number of sub-scanning lines is the same as the number of a row of control areas arranged in the first direction, and each A sub-scanning line corresponds to a row of sub-pixels in a control area.
  • a row of pixel islands arranged in the first direction is correspondingly connected to n control circuits.
  • the display panel provided by the embodiment of the present disclosure.
  • the cylindrical lens structure is located on the light emitting side of the display panel; the cylindrical lens structure includes a plurality of cylindrical lenses arranged in an array;
  • the controller connected to the display panel, is configured to provide a driving signal to the display panel.
  • driving the gazing area to display images at a first refresh rate, and driving the non-gazing area to display images at a second refresh rate specifically includes:
  • a and B are positive integers, and A is greater than B.
  • driving each sub-pixel in the gaze area to refresh includes:
  • Control each control signal line to transmit control signals transmit the signal provided by the scanning signal input line to the scanning line corresponding to the gaze area, and transmit the signal provided by the fixed potential line to the scanning line corresponding to the non-gazing area;
  • each control signal line is controlled to transmit control signals, the signal provided by the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the signal provided by the scanning signal input line is transmitted to the non-focus area.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an arrangement of sub-pixels in a display panel provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a second light-shielding layer in a display panel provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of an active layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a first conductive layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a first interlayer insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a second conductive layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a second interlayer insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a third conductive layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a first planarization layer in a display panel provided by an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of a pixel electrode layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a common electrode layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of a first light-shielding layer in a display panel provided by an embodiment of the present disclosure
  • FIG. 17 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a second light-shielding layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of an active layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 20 is a schematic structural diagram of a first conductive layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 21 is a schematic structural diagram of a second conductive layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 22 is a schematic structural diagram of a first interlayer insulating layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 23 is a schematic structural diagram of a third conductive layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 24 is a schematic structural diagram of a second interlayer insulating layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 25 is a schematic structural diagram of a second interlayer insulating layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 26 is a schematic structural diagram of a fourth conductive layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 27 is a schematic structural diagram of a third interlayer insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 28 is a schematic structural diagram of a fifth conductive layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 29 is a schematic structural diagram of a first passivation layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 30 is a schematic structural diagram of a pixel electrode layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 31 is a schematic structural diagram of a common electrode layer in another display panel provided by an embodiment of the present disclosure.
  • Figure 32 is a sectional view along AA' in Figure 17 provided by an embodiment of the present disclosure.
  • Figure 33 is a cross-sectional view along BB' in Figure 17 provided by an embodiment of the present disclosure.
  • FIG. 34 is a schematic structural diagram of a first light-shielding layer in another display panel provided by an embodiment of the present disclosure.
  • FIG. 35 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 36 is a schematic diagram of a driving method of a display device provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a display panel. As shown in FIGS. 1 to 3 , the display panel includes:
  • a plurality of scanning lines 2 are located on one side of the first base substrate 1, and the plurality of scanning lines 2 extend along the first direction X and are arranged along the second direction Y; the first direction X crosses the second direction Y;
  • a plurality of data lines 3 are located on the same side of the first base substrate 1 as the scanning lines 2, and the plurality of data lines 3 extend along the second direction Y and are arranged along the first direction X;
  • a plurality of sub-pixels 4 are respectively located in the area divided by a plurality of scanning lines 2 and a plurality of data lines 3; at least two adjacent sub-pixels 4 along the first direction X and the second direction Y form a pixel island 5; a plurality of sub-pixels 4 The pixels 4 form a plurality of pixel islands 5; each pixel island 5 includes n rows of sub-pixel rows 6 in the second direction Y;
  • a plurality of scanning signal input lines 7 correspond to the scanning lines 2 one by one, extend along the first direction X, and are arranged along the second direction Y;
  • a plurality of control signal lines 8 extending along the second direction Y and arranged along the first direction X;
  • a plurality of control circuits 10 are located between adjacent sub-pixels 4; one pixel island 5 is correspondingly connected to at least n control circuits 10; one control circuit 10 corresponds to one sub-pixel row 6 in the pixel island 5;
  • the control circuit 10 is configured to transmit the signal provided by the scanning signal input line 7 or the signal provided by the fixed potential line 9 to the scanning line 2 under the control of the control signal line 8 .
  • the display panel provided by the embodiment of the present disclosure includes a control circuit, a control signal line, a fixed potential line, and a scanning signal input line electrically connected to the control circuit, so that the signal provided by the scanning signal input line or the signal provided by the fixed potential line can be used by the control circuit.
  • the signal is passed to the scan line. That is to say, during the image display process, the control circuit can be used to input a normal scan signal to the corresponding scan line for the area that needs to be refreshed, and a fixed potential can be input to the corresponding scan line by the control circuit for the area that does not need to be refreshed.
  • Fixed potential signal transmitted by wire That is, partition driving of pixel islands can be realized, thereby saving power consumption of display products.
  • the pixel islands are arranged in an array, and each pixel island is electrically connected to the control circuit, so that the divisional control of each pixel island in the display panel in the second direction can be realized.
  • the display panel may be a rigid display panel, or a flexible display panel, that is, the display panel is bendable and foldable.
  • the display panel provided by the embodiments of the present disclosure is a liquid crystal display panel. Its type can be Twisted Nematic (TN), Vertical Alignment (VA), In-Plane Switching (IPS) or Advanced Super Dimension Switch (ADS) and other LCD panels.
  • TN Twisted Nematic
  • VA Vertical Alignment
  • IPS In-Plane Switching
  • ADS Advanced Super Dimension Switch
  • the liquid crystal display panel includes: an array substrate and an opposite substrate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the opposite substrate.
  • the signal lines and control circuits in FIGS. 1 to 3 may be disposed on an array substrate, for example.
  • the sub-pixel 4 includes a driving transistor T3 .
  • the sub-pixel 4 also includes pixel electrodes electrically connected to the driving transistors in a one-to-one correspondence.
  • the opposite substrate includes a first light-shielding layer and a color filter. The opening area of the first light-shielding layer is provided with a color filter corresponding to the color of the sub-pixel.
  • the liquid crystal display panel further includes a common electrode layer, and the common electrode layer may be disposed on the array substrate or on the opposite substrate.
  • the display panel provided by the embodiments of the present disclosure is an electroluminescence display panel.
  • the electroluminescent display panel may be, for example, an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panel, a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED) display panel, and the like.
  • each sub-pixel includes, for example, a pixel driving circuit and an electroluminescent device electrically connected to the pixel driving circuit, and the pixel driving circuit includes, for example, a transistor, a capacitor, and the like.
  • the fixed potential line inputs a low-level signal.
  • the display panel further includes a gate driving circuit, and a plurality of scanning signal input lines are electrically connected to the gate driving circuit.
  • the gate driving circuit can be used to implement partition control on multiple rows of pixel islands, that is, to realize horizontal partition control. That is, each pixel island in the display panel can be controlled in partitions in the first direction and the second direction.
  • the colors of a row of sub-pixels 4 arranged in the first direction X are all the same.
  • a plurality of pixel islands 5 are divided into a plurality of control areas 56, and each control area 56 includes at least one pixel island 5;
  • Each scanning line 2 includes: a plurality of sub-scanning lines 11 arranged in the first direction X and disconnected from each other; in each scanning line 2, the number of sub-scanning lines 11 is the same as a row of control areas 56 arranged in the first direction X The numbers are the same, and each sub-scanning line 11 corresponds to a row of sub-pixels 4 in a control area 56 .
  • the scanning lines are disconnected between the control areas, so that the control circuit can be used to realize independent control of each control area.
  • one pixel island 5 is correspondingly connected to n control circuits.
  • a row of pixel islands 5 arranged in the first direction X is correspondingly connected to n control circuits 10 .
  • each pixel island may also be connected with n control circuits.
  • control circuit 10 includes: a first transistor T1 and a second transistor T2;
  • the control electrode of the first transistor T1 is electrically connected to a control signal line 8, the first electrode of the first transistor T1 is electrically connected to the scanning signal input line 7, and the second electrode of the first transistor T1 is electrically connected to the scanning line 2;
  • the control electrode of the second transistor T2 is electrically connected to a control signal line 8 , the first electrode of the second transistor T2 is electrically connected to the fixed potential line 9 , and the second electrode of the second transistor T2 is electrically connected to the scanning line 2 .
  • the second pole of the first transistor T1 and the second pole of the second transistor T1 in one control circuit are electrically connected to the same sub-scanning line.
  • control electrode of the first transistor T1 and the control electrode of the second transistor T1 are electrically connected to the same control signal line 8;
  • the first transistor is an N-type transistor, and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.
  • control electrode of the first transistor T1 and the control electrode of the second transistor T2 are electrically connected to different control signal lines 8 .
  • the multiple control signal lines 8 include: multiple first control signal lines 12 and multiple second control signal lines 13;
  • the control electrode of the first transistor T1 is electrically connected to the first control signal line 12
  • the control electrode of the second transistor T2 is electrically connected to the second control signal line 13 .
  • the first transistor when the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines, the first transistor can be an N-type transistor or a P-type transistor, and the second transistor can be An N-type transistor may also be a P-type transistor.
  • control circuit 10 is located between two adjacent sub-pixels 4 in the first direction X;
  • a plurality of fixed potential lines 9 extend along the first direction X and are arranged along the second direction Y.
  • control circuit 10 is located between two adjacent columns of sub-pixels 4 .
  • the display panel specifically includes:
  • the first conductive layer 14 includes the scanning line 2, the scanning signal input line 7, the fixed potential line 9, the control electrode G1 of the first transistor T1, and the control electrode G2 of the second transistor T2;
  • the second conductive layer 15 is located on the side of the first conductive layer 14 away from the first base substrate, including data lines 3 and control signal lines 8;
  • the patterns of the first conductive layer 14 , the second conductive layer 15 , and the third conductive layer 17 corresponding to FIG. 5 are shown in FIG. 8 , FIG. 10 , and FIG. 12 , respectively.
  • the first transistors T1 and the second transistors T2 are arranged in two rows along the first direction.
  • the orthographic projection of the control electrode G1 of the first transistor T1 on a plane perpendicular to the first direction and the control electrode G2 of the second transistor T2 are in Orthographic projections of planes perpendicular to the first direction do not overlap each other.
  • the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2 are not arranged along a straight line parallel to the first direction, so that even if the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2 G2 has an overlapping area in the second direction, and the control electrode G1 of the first transistor T1 and the control electrode G2 of the second transistor T2 will not be short-circuited.
  • the total width of the first transistor T1 and the second transistor T2 in the first direction can be reduced, thereby minimizing the influence of the settings of the control circuit on the aperture ratio.
  • the first pole S1 of the first transistor T1 is located on the side of the second pole D2 of the first transistor T1 ;
  • the first pole S2 of the second transistor T2 is located on one side of the second pole D2 of the second transistor T2. That is, the first pole S1 and the second pole D2 of the first transistor T1 are arranged along the second direction, and the first pole S2 and the second pole D2 of the second transistor T2 are also arranged along the second direction. In this way, it is possible to further avoid increasing the width of the first transistor T1 in the first direction and the width of the second transistor T2 in the first direction, thereby minimizing the influence of the setting of the control circuit on the aperture ratio.
  • the sub-pixel when the display panel is a liquid crystal display panel, the sub-pixel includes a driving transistor; the first conductive layer further includes: a control stage of the driving transistor electrically connected to the scanning line 2;
  • the second conductive layer also includes: a first pole of the driving transistor
  • the third conductive layer further includes: a second pole of the driving transistor.
  • the first pole and the second pole of the driving transistor are located on different conductive layers, and the first pole and the second pole of each transistor of the control circuit are located on different conductive layers from the control signal line, so that the second pole of the driving transistor can be reduced.
  • the distance between the pole and the data line and the distance between the first pole and the second pole of each transistor of the control circuit and the control signal line will be reduced, and it will not cause the second pole of the drive transistor to be short-circuited with the data line, nor will it cause The first pole and the second pole of each transistor of the control circuit are short-circuited with the control signal line, which can reduce the difficulty of layout design of the display panel.
  • the display panel further includes: a pixel electrode layer on a side of the third conductive layer away from the second conductive layer 15 , and a common electrode layer on a side of the pixel electrode layer away from the third conductive layer.
  • the pixel electrode layer includes pixel electrodes corresponding to the sub-pixels one by one.
  • the common electrode layer includes common electrodes. It should be noted that, in order to illustrate the structure of the control circuit clearly, the patterns of the common electrode layer and the pixel electrode layer are not shown in FIG. 5 . In specific implementation, the pattern of the pixel electrode layer 21 is shown in FIG. 14 , and the pattern of the common electrode layer 35 is shown in FIG. 15 .
  • the display panel further includes a second light-shielding layer 16 between the first conductive layer 14 and the first base substrate , the active layer 18 between the second light shielding layer 16 and the first conductive layer 14, the buffer layer (not shown) between the active layer 18 and the second light shielding layer 16, the first conductive layer 14 and the active layer 18 between the gate insulating layer, the first interlayer insulating layer 19 between the first conductive layer 14 and the second conductive layer 15, the second interlayer insulating layer between the second conductive layer 15 and the third conductive layer 17 20, the first planarization layer 22 between the third conductive layer 17 and the pixel electrode layer, and the second planarization layer between the pixel electrode layer and the common electrode layer.
  • Fig. 6, Fig. 7, Fig. 9, Fig. 11, Fig. 13 respectively show the second light shielding layer 16, the active layer 18, the first interlayer insulating layer 19, the second interlayer insulating layer 20, and the first planarization
  • the pattern of the layer 22 , the dotted line area in FIG. 9 , FIG. 11 , and FIG. 13 is the via hole area of the first interlayer insulating layer 19 , the second interlayer insulating layer 20 , and the first planarization layer 22 .
  • the third conductive layer further includes: a first input lead 23 , a second input lead 24 , a first output lead 25 and a second output lead 26 .
  • the first input lead 23 is electrically connected to the first pole S1 of the first transistor T1 , and is electrically connected to the scan signal input line 7 through a via hole penetrating through the second interlayer insulating layer and the first interlayer insulating layer.
  • the second input lead 24 is electrically connected to the first pole S2 of the second transistor T2 and is electrically connected to the fixed potential line 9 through the second interlayer insulating layer and the via hole of the first interlayer insulating layer.
  • the first output lead 25 is electrically connected to the second pole D2 of the first transistor T1 and is electrically connected to the scan line 2 through a via hole penetrating through the second interlayer insulating layer and the first interlayer insulating layer.
  • the second output lead 26 is electrically connected to the scanning line 2.
  • the second pole D2 of the second transistor T2 is electrically connected and electrically connected to the scan line 2 through a via hole penetrating through the second interlayer insulating layer and the first interlayer insulating layer.
  • the first input lead 23 , the second input lead 24 , the first output lead 25 and the second output lead 26 all extend along the second direction Y.
  • the first input lead 23 is integrally connected with the first pole S1 of the first transistor T1.
  • the second input lead 24 is integrally connected to the first pole S2 of the second transistor T2.
  • the first output lead 25 is integrally connected to the second pole D2 of the first transistor T1.
  • the second output lead 26 is integrally connected to the second pole D2 of the second transistor T2.
  • the first control signal line 12 is electrically connected to the control electrode G1 of the first transistor T1 through a via hole penetrating through the first interlayer insulating layer.
  • the second control signal line 13 is electrically connected to the control electrode G2 of the second transistor T2 through a via hole penetrating through the first interlayer insulating layer.
  • the first pole S1 and the second pole D2 of the first transistor T1, and the first pole S2 and the second pole D2 of the second transistor T2 pass through the second interlayer insulating layer, the first interlayer insulating layer and the gate insulating layer.
  • the vias are electrically connected to the active layer.
  • the pixel electrode is electrically connected to the second electrode of the driving transistor through the via hole penetrating the first planarization layer.
  • the first pole of the driving transistor is electrically connected to the active layer through the via hole penetrating the first interlayer insulating layer and the gate insulating layer, and the second pole of the driving transistor is through the second interlayer insulating layer, the first interlayer insulating layer and the via hole.
  • the via hole of the gate insulating layer is electrically connected with the active layer.
  • control circuit is arranged in an array, the control stages of the first transistors located in the same column in the second direction are electrically connected to the same first control signal line, and the second transistors located in the same column in the second direction The control stage is electrically connected to the same second control signal line.
  • the first electrodes of the first transistors located in the same row in the first direction are electrically connected to the same scanning signal input line, and the first electrodes of the second transistors located in the same row in the first direction are electrically connected to the same fixed potential line .
  • the first light-shielding layer in the opposite substrate includes a plurality of first light-shielding portions 36 extending along the first direction X and a plurality of second light-shielding portions extending along the second direction Y. 37.
  • the first light shielding portion 36 covers between adjacent sub-pixel rows, that is, the first light shielding portion 36 covers the scanning line, the fixed potential line and the scanning signal input line.
  • the second light-shielding portion 37 only covers between the sub-pixel columns provided with the control circuit, that is, the second light-shielding portion covers the control circuit, the control signal line and each input lead. and output leads. There is no need to arrange the second light shielding part between the sub-pixel columns without the control circuit, so that the aperture ratio of the sub-pixel can be increased as much as possible under the condition of realizing the shielding of the control circuit and under control.
  • control circuit 10 is located between two adjacent sub-pixels 4 in the second direction Y;
  • a plurality of fixed potential lines 9 extend along the second direction Y and are arranged along the first direction X.
  • control circuit 10 is located between adjacent sub-pixel rows.
  • control circuits corresponding to each pixel island are arranged in a row in the first direction X.
  • control electrodes of the first transistors arranged in a row in the second direction are electrically connected to the same first control signal line.
  • the control electrodes of the second transistors arranged in a row in the second direction are electrically connected to the same second control signal line, and the first electrodes of the second transistors arranged in a row in the second direction are connected to the same fixed potential line electrical connection.
  • the display panel specifically includes:
  • the first conductive layer 14 includes the scan line 2, the control electrode G1 of the first transistor T1, and the control electrode G2 of the second transistor T2;
  • the second conductive layer 15 is located on the side of the first conductive layer 14 away from the first base substrate, including the scanning signal input line 7;
  • the third conductive layer 17 is located on the side of the second conductive layer 15 away from the first conductive layer 14, including the data line 3;
  • the fourth conductive layer 38 located on the side of the third conductive layer 17 away from the second conductive layer 15, includes the control signal line 8, the fixed potential line 9, the first pole S1 and the second pole D1 of the first transistor T1, and the second The first pole S2 and the second pole D2 of the transistor T2; the orthographic projection of the control signal line 8 and the fixed potential line 9 on the first substrate overlap with the partial area of the orthographic projection of the data line 3 on the first substrate.
  • FIG. 17 is a pattern of a partial area within a control area, and therefore does not show the disconnected area between the sub-scanning lines.
  • the positive projection of the control signal line and the fixed potential line on the first base substrate is the same as the positive projection of the data line on the first base substrate. Part of the projected areas overlap, so that the influence of each signal line electrically connected to the control circuit on the aperture ratio of the sub-pixel can be avoided.
  • the subpixel includes a drive transistor
  • the first conductive layer further includes: a control stage of a driving transistor electrically connected to the scanning line;
  • the second conductive layer also includes: a first pole of the driving transistor
  • the display panel also includes:
  • the fifth conductive layer 42 is located on the side of the fourth conductive layer 38 away from the third conductive layer 17 , and includes the second pole D3 of the driving transistor.
  • FIG. 28 is a pattern of the fifth conductive layer 42 corresponding to FIG. 17 .
  • the first pole and the second pole of the driving transistor are located in different conductive layers, so that the distance between the second pole of the driving transistor and the data line can be reduced, and the distance between the second pole of the driving transistor and the data line will not be caused. Short circuit, thereby reducing the difficulty of layout design of the display panel.
  • the display panel further includes: a pixel electrode layer on a side of the fifth conductive layer away from the fourth conductive layer, and a common electrode layer on a side of the pixel electrode layer away from the fifth conductive layer.
  • the pixel electrode layer includes pixel electrodes corresponding to the sub-pixels one by one.
  • the common electrode layer includes common electrodes. It should be noted that, in order to illustrate the structure of the control circuit clearly, the patterns of the common electrode layer and the pixel electrode layer are not shown in FIG. 17 . During specific implementation, the pattern of the pixel electrode layer 21 is shown in FIG. 30 , and the pattern of the common electrode layer 35 is shown in FIG. 31 .
  • the pixel electrode layer and the common electrode layer may use materials with higher transmittance.
  • the pixel electrode layer and the common electrode layer may include, for example, indium tin oxide (ITO). That is, the array substrate can be provided with two ITO layers. The first layer of ITO is used as the pixel electrode layer, which can reduce the number of via holes and increase the aperture ratio.
  • the display panel further includes metal common electrode lines on the same layer as the common electrodes. In specific implementation, for example, a common electrode line is formed on the second passivation layer, and then an ITO common electrode electrically connected to the common electrode line is formed.
  • the display panel further includes a first conductive layer 14 and a second A second light-shielding layer 16 between the substrates, an active layer 18 between the second light-shielding layer 16 and the first conductive layer 14, a buffer layer 27 between the active layer 18 and the second light-shielding layer 16, the second A first gate insulating layer 28 between the conductive layer 14 and the active layer 18, a second gate insulating layer 29 between the first conductive layer 14 and the second conductive layer 15, the second conductive layer 15 and the third conductive layer 17 between the first interlayer insulating layer 19, the second interlayer insulating layer 20 between the third conductive layer 17 and the fourth conductive layer 38, the third interlayer insulating layer between the fourth conductive layer 38 and the fifth conductive layer 42
  • Fig. 18, Fig. 19, Fig. 22, Fig. 27, and Fig. 29 respectively show the second light shielding layer 16, the active layer 18, the first interlayer insulating layer 19, the third interlayer insulating layer 43, and the first passivation layer.
  • Layer 44 pattern Fig. 32 is a sectional view along AA' in Fig. 17, and Fig. 33 is a sectional view along BB' in Fig. 17.
  • the dotted line areas in FIG. 22 , FIG. 27 , and FIG. 29 are the via hole areas of the first interlayer insulating layer 19 , the third interlayer insulating layer 43 , and the first passivation layer 44 , respectively.
  • the dotted line area in FIG. 24 and FIG. 25 corresponds to the area where the via hole is formed after the second interlayer insulating layer 20 is formed.
  • the second interlayer insulating layer functions as a planarization layer.
  • a first patterning process is performed in the dotted line area shown in FIG. 24 to form via holes.
  • a second patterning process is performed in the dotted line area shown in FIG. 25 to form via holes.
  • no via holes are formed in the dotted line area shown in FIG.
  • Corresponding via holes are formed in the first interlayer insulating layer and the film layer below it, and the subsequent fourth conductive layer can be electrically connected to the active layer or the first conductive layer through the via holes formed in the dotted line area as shown in Figure 25 .
  • the first transistor T1 and the second transistor T2 in each control circuit are arranged in a row along the first direction.
  • each first transistor in each first transistor, the first pole S1 of the first transistor T1, the control stage G1 of the first transistor T1, and the second pole D1 of the first transistor T1 direction arrangement;
  • each second transistor T2 the first pole S1 of the second transistor T2, the control stage G1 of the second transistor T2, and the second pole D1 of the second transistor T are arranged along the first direction.
  • the first transistor and the second transistor in each control circuit are arranged in a row in the first direction X
  • the first pole, the control pole, and the second pole of each transistor in the control circuit are also arranged in the first direction X.
  • One row so that the size of the control circuit in the second direction Y can be reduced, and the influence of the control circuit on the aperture ratio of the sub-pixel can be further avoided.
  • the active layer of the first transistor T1 includes a portion extending along the first direction
  • the active layer of the second transistor T2 includes a portion extending in the first direction.
  • the fourth conductive layer 38 further includes: a plurality of first output leads 25 and a plurality of second output leads 26 extending along the second direction Y;
  • the second pole D1 of the first transistor T1 is electrically connected to the scan line 2 through the first output lead 25;
  • the second pole D2 of the second transistor T2 is electrically connected to the scan line 2 through the second output lead 26;
  • the orthographic projections of the first output lead 25 and the second output lead 26 on the first substrate overlap with a partial area of the orthographic projection of the data line 3 on the first substrate.
  • the first output lead, the first input lead, and the second input lead are located on different conductive layers from the data line, in this way, the first output lead, the first input lead, and the second input lead are on the first base substrate
  • the orthographic projection of the data line overlaps with the partial area of the orthographic projection of the data line on the first base substrate, so that the influence of each signal line electrically connected to the control circuit on the aperture ratio of the sub-pixel can be avoided.
  • the fourth conductive layer 38 further includes: a first input lead 23 , the first electrode S1 of the first transistor T1 is connected to the scan signal input line 7 through the first input lead 23 electrical connection.
  • the fourth conductive layer 38 further includes: a plurality of first connection pads 39, a plurality of second connection pads 40, a plurality of third connection pads 41, a plurality of first connection pads Four connection pads 45 and a plurality of fifth connection pads 46 .
  • the first input lead 23 is electrically connected to the first connection pad 39
  • the first connection pad 39 is electrically connected to the scanning signal input line 7 through a via hole penetrating through the second interlayer insulating layer and the first interlayer insulating layer. As shown in FIG.
  • the first output lead 25 is electrically connected to the second connection pad 40, and the second connection pad 40 passes through the second interlayer insulating layer 20, the first interlayer insulating layer 19, and the second gate insulating layer.
  • the via hole 33 of 29 is electrically connected to the scan line 2 .
  • the first control signal line 12 is electrically connected to the third connection pad 41, and the third connection pad 41 is connected to the first transistor through a via hole penetrating through the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer. control level electrical connections.
  • the second control signal line 13 is electrically connected to the fourth connection pad 45, and the fourth connection pad 45 is connected to the second transistor through a via hole penetrating through the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer. control level electrical connections.
  • the second output lead 26 is electrically connected to the fifth connection pad 46, and the fifth connection pad 46 is electrically connected to the scan line through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer. .
  • the second connection pad 40 passes through the fourth via hole 33 penetrating through the second interlayer insulating layer 20 , the first interlayer insulating layer 19 , and the second gate insulating layer 29 and scans The area where wire 2 is electrically connected.
  • the area corresponding to the fourth via hole 33 is firstly subjected to a patterning process to form a via hole in the second interlayer insulating layer 20, and then a second patterning process is performed.
  • the via hole is formed in the first interlayer insulating layer 19 and the second gate insulating layer 29 by the electroplating process, and the size h1 of the via hole in the second interlayer insulating layer 20 is larger than the size of the via hole in the second gate insulating layer 29.
  • the second connection pad 40 extends in a step shape in the area of the fourth via hole 33 , and the size of the planar area of the second connection pad 40 at the via hole of the second gate insulating layer 29 is h2 .
  • h1 is, for example, 4 microns
  • h2 is, for example, 2.5 microns.
  • the second pole D3 of the driving transistor passes through the third interlayer insulating layer 43 , the second interlayer insulating layer 20 , the first interlayer insulating layer 19 , and the second gate insulating layer. 29 , and the via holes of the first gate insulating layer 28 are electrically connected to the active layer 18 .
  • the second connection pad 40 is electrically connected to the scan line 2 through a via hole penetrating through the second interlayer insulating layer 20 , the first interlayer insulating layer 19 , and the second gate insulating layer 29 .
  • the first interlayer insulating layer 19 and the second gate insulating layer 29 have a second via hole 32; the second electrode D3 of the driving transistor is electrically connected to the active layer 18 In the connected area and the area where the second connection pad 40 is electrically connected to the scan line 2 , the second interlayer insulating layer 20 has a third via hole 34 exposing the first via hole 55 and the second via hole 32 .
  • a patterning process is first performed to remove the second interlayer insulating layer 20 in the area of the third via hole 34, and then , performing a second patterning process to form a second via hole 32 .
  • the size h4 of the first via hole 55 exposing the active layer 18 is, for example, 3 microns.
  • the distance h3 between the edge of the first via hole 55 exposing the active layer 18 and the edge of the second interlayer insulating layer 20 exposing the first interlayer insulating layer 19 is, for example, 1.5 microns.
  • the distance h5 between the edge of the first via hole 55 exposing the active layer 18 and the scanning line is, for example, 2.05 ⁇ m.
  • the size h6 of the second via hole 32 exposing the scan line 2 is, for example, 2.5 microns, and the distance h7 between the edge of the second via hole 32 exposing the scan line 2 and the scan signal input line 7 is, for example, 2.5 microns.
  • the display panel also includes:
  • the opposite substrate is located on the side of the support part away from the common electrode layer, including a light shielding part;
  • the liquid crystal layer is located between the opposite substrate and the common electrode layer.
  • the opposite substrate includes a first light shielding layer, and the first light shielding layer includes a light shielding portion.
  • the display panel is a liquid crystal display panel
  • the sub-pixels arranged in the first direction X have the same color
  • the control circuit is located between adjacent sub-pixel rows, as shown in FIG. 34
  • the light shielding portion may only include a plurality of first light shielding portions 36 extending along the first direction X.
  • the first light shielding portion 36 covers between adjacent sub-pixel rows, that is, the first light shielding portion 36 covers the scanning lines, the fixed potential lines, the scanning signal input lines, and the control circuit.
  • the display panel further includes:
  • a plurality of supporting parts 47 are located on the side of the common electrode layer away from the pixel electrode layer.
  • the orthographic projection of the supporting parts 47 on the first base substrate is located between adjacent sub-pixel rows 6, and the control circuit is located on the side where the supporting parts 47 are provided. between sub-pixel rows.
  • each pixel island 5 includes: a first sub-pixel row 48 , a second sub-pixel row 49 and a third sub-pixel row 50 ;
  • the first sub-pixel row 48 includes a plurality of first-color sub-pixels arranged along the first direction X;
  • the second sub-pixel row 49 includes a plurality of second-color sub-pixels arranged along the first direction X;
  • the third sub-pixel row 50 includes a plurality of third-color sub-pixels arranged along the first direction X;
  • the width of the first light-shielding portion 36 between the first sub-pixel row 48 and the second sub-pixel row 49 and covering the second sub-pixel is smaller than the width of the first light-shielding portion 36 between the first sub-pixel row 48 and the third sub-pixel row 50;
  • the orthographic projection of the support portion 47 on the base substrate is located between the first sub-pixel row 48 and the third sub-pixel row 50 .
  • control circuit is arranged between the first sub-pixel row and the third sub-pixel row.
  • the orthographic projection of the light shielding portion on the first base substrate covers the orthographic projection of the support portion on the first base substrate and the orthographic projection of the control circuit on the first base substrate. Since the supporting part is arranged in the area where the width of the first light shielding part is wider in the second direction Y. Therefore, in the display panel provided by the embodiments of the present disclosure, the control circuit is arranged in the region of the support portion, so as to avoid affecting the aperture ratio of the display panel.
  • the first color sub-pixel is a red sub-pixel R
  • the second color sub-pixel is a green sub-pixel G
  • the third color sub-pixel is a blue sub-pixel B.
  • the region where the first light shielding portion has a wider width in the second direction Y is disposed between the red sub-pixel row and the blue sub-pixel row, which can avoid increasing the first light shielding portion in the second direction Y.
  • the preparation method of the array substrate includes the following steps:
  • S104 deposit gate metal material, etch to form the initial pattern of the scan line, the pattern of the control level of the first transistor, and the pattern of the control level of the second transistor, and perform a semiconductor self-aligned doping process on the active layer forming a conductorized region; wherein each scan line in the initial pattern of scan lines is integrally connected;
  • S112 deposit metal material to form a fourth conductive layer, and etch to form control signal lines, fixed potential lines, input leads, output leads, connection pads, patterns of the first pole and the second pole of the first transistor, and the second transistor The pattern of the first pole and the second pole;
  • forming the pattern of the common electrode further includes the step of forming a protective layer.
  • the supporting part includes a part disposed on one side of the array substrate, a step of forming the supporting part is further included after forming the protective layer.
  • a display device provided by an embodiment of the present disclosure includes:
  • the display panel 51 provided by the embodiment of the present disclosure.
  • the cylindrical lens structure 52 is located on the light emitting side of the display panel 51; the cylindrical lens structure 52 includes a plurality of cylindrical lenses arranged in an array;
  • a controller (not shown), connected to the display panel, is configured to provide a driving signal to the display panel.
  • the drive control circuit provided by the controller can be used to drive the control circuit to input a normal scan signal to the scan line corresponding to the pixel island, and for the area that does not need to be refreshed, it can be passed
  • the driving signal provided by the controller drives the control circuit to input the fixed potential signal transmitted by the fixed potential line to the scanning line corresponding to the pixel island, so as to realize partition driving of the pixel island and save power consumption of the display device.
  • the display device further includes:
  • the light-transmitting spacer layer 53 is located between the display panel 51 and the cylindrical lens structure 52;
  • the flat layer 54 is located on a side of the cylindrical lens structure 52 away from the transparent spacer layer 53 .
  • the display device when the display panel is a liquid crystal display panel, the display device, for example, further includes a backlight module located away from the lenticular structure of the display panel.
  • the display device also includes:
  • the eye-tracking system is used to determine the gaze area of the user's eyes on the display device in real time.
  • high-frequency refreshing may be performed on the fixation area
  • low-frequency refreshment may be performed on the non-fixation area
  • the same resolution as 2D display can be maintained in the three-dimensional image (3D) display mode , combined with eye-tracking, it can realize multi-view display with large viewing angle, and can realize 3D display with higher pixel density (PPI), with larger amount of information, lower color crosstalk between adjacent viewpoints, and lower user
  • PPI pixel density
  • the cylindrical lens array can not only perform pixel mapping on the sub-pixels in the pixel island, but also perform light field modulation on the outgoing light of the pixel island, so that the final outgoing light of the pixel island can form multiple point of view, so as to realize the light field 3D display.
  • the display device is any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.
  • an embodiment of the present disclosure also provides a driving method of a display device, as shown in FIG. 36 , including:
  • the refresh rate of the gazing area is higher than that of the non-gazing area, so that the refresh rate of the display device can be controlled by partition without affecting the user's normal viewing of the display screen, which can The power consumption of the display device is saved.
  • determining the gaze area and non-gazing area of the user on the display device in real time includes:
  • driving the gazing area to display images at a first refresh rate, and driving the non-gazing area to display images at a second refresh rate specifically includes:
  • a and B are positive integers, and A is greater than B.
  • driving each sub-pixel in the gaze area to refresh includes:
  • Control each control signal line to transmit control signals transmit the signal provided by the scanning signal input line to the scanning line corresponding to the gaze area, and transmit the signal provided by the fixed potential line to the scanning line corresponding to the non-gazing area;
  • each control signal line is controlled to transmit control signals, the signal provided by the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the signal provided by the scanning signal input line is transmitted to the non-focus area.
  • control stage of the first transistor and the control stage of the second transistor are electrically connected to the same control signal line;
  • Each control signal line that drives the attention area transmits the first control signal
  • each control signal line that drives the non-annotation area transmits the second control signal, so as to control the first transistor in the attention area to be turned on and the second transistor to be turned off.
  • One transistor is turned off and the second transistor is turned on, and the signal provided by the scanning signal input line is transmitted to the corresponding scanning line in the control area through the first transistors in the control area, and the signal provided by the fixed potential line is passed through the second transistor in the non-watching area.
  • the transistor is passed to the scan line corresponding to the non-focus area;
  • each control signal line is controlled to transmit control signals, the signal provided by the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the signal provided by the scanning signal input line is transmitted to the non-focus area.
  • the scan lines corresponding to the area including:
  • Each control signal line that drives the attention area transmits the second control signal
  • each control signal line that drives the non-annotation area transmits the first control signal, so as to control the first transistor in the attention area to turn off and the second transistor to open, and the first transistor in the non-attention area to turn on.
  • One transistor is turned on and the second transistor is turned off, and the signal provided by the scanning signal input line is transmitted to the corresponding scanning line in the non-control area through the first transistors in the non-control area, and the signal provided by the fixed potential line is passed through the first transistor in the watching area.
  • the two transistors are transmitted to the scan lines corresponding to the gaze area.
  • the first signal when the first transistor is a P-type transistor and the second transistor is an N-type transistor, the first signal is a low-level signal, and the second signal is a high-level signal; when the first transistor is an N-type transistor, When the second transistor is a P-type transistor, the first signal is a high-level signal, and the second signal is a low-level signal.
  • control stage of the first transistor when the control stage of the first transistor is electrically connected to the first control signal line, and the control stage of the second transistor is electrically connected to the second control signal line;
  • Each first control signal line driving the attention area transmits the first control signal
  • each second control signal line transmits the second control signal
  • each first control signal line driving the non-annotation area transmits the third control signal
  • the line transmits the fourth control signal to control the first transistor in the watching area to turn on and the second transistor to turn off, the first transistor in the non-watching area to turn off and the second transistor to turn on, and the signal provided by the scanning signal input line to pass through the control area.
  • Each first transistor is transmitted to the scanning line corresponding to the control area, and at the same time, the signal provided by the fixed potential line is transmitted to the scanning line corresponding to the non-attention area through the second transistor in the non-attention area;
  • each control signal line is controlled to transmit control signals, the signal provided by the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the signal provided by the scanning signal input line is transmitted to the non-focus area.
  • the scan lines corresponding to the area including:
  • Each first control signal line driving the attention area transmits the third control signal
  • each second control signal line transmits the fourth control signal
  • each first control signal line driving the non-annotation area transmits the first control signal and each second control signal
  • the line transmits the second control signal to control the first transistor in the watching area to turn off and the second transistor to turn on, the first transistor in the non-watching area to turn on, and the second transistor to turn off, and the signal provided by the scanning signal input line to pass through the non-controlling area
  • Each of the first transistors in the control area is transmitted to the corresponding scan line of the non-control area, and at the same time, the signal provided by the fixed potential line is transmitted to the scan line corresponding to the attention area through the second transistor of the attention area.
  • the first signal and the fourth signal when both the first transistor and the second transistor are P-type transistors, the first signal and the fourth signal are low-level signals, and the second signal and the third signal are high-level signals.
  • the first transistor and the second transistor are N-type transistors, the first signal and the fourth signal are high level signals, and the second signal and the third signal are low level signals.
  • the first transistor is a P-type transistor and the second transistor is an N-type transistor, the first signal and the second signal are low-level signals, and the third signal and the fourth signal are high-level signals;
  • the P-type transistor and the second transistor are P-type transistors, the first signal and the second signal are high-level signals, and the third and fourth signals are low-level signals.
  • the embodiments of the present disclosure provide a display panel, a display device, and a driving method thereof.
  • the display panel includes a control circuit, and a control signal line, a fixed potential line, and a scanning signal input line electrically connected to the control circuit.
  • the control circuit transmits the signal provided by the scanning signal input line or the signal provided by the fixed potential line to the scanning line. That is to say, during the image display process, for the area that needs to be refreshed, the control circuit can be used to input normal scanning signals to the scanning lines corresponding to the pixel islands, and for the areas that do not need to be refreshed, the control circuit can be used to scan Line input Fixed potential signal transmitted by fixed potential line.
  • the partition driving of the pixel islands can be realized by using the control circuit, the control signal lines, the fixed potential lines, and the scanning signal input lines. Thereby, the power consumption of the display product can be saved.
  • the pixel islands are arranged in an array, and each pixel island is electrically connected to the control circuit, which can also realize partition control of each pixel island in the display panel in the second direction.

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Abstract

本公开实施例提供了一种显示面板、显示装置及其驱动方法。显示面板包括：第一衬底基板；多条扫描线；多条数据线；多个子像素，分别位于多条扫描线和多条数据线划分出的区域内；沿第一方向和第二方向相邻的至少两个子像素构成一个像素岛；多个子像素构成多个像素岛；每一像素岛在第二方向上包括n行子像素行；多条扫描信号输入线，与扫描线一一对应；多条控制信号线；多条固定电位线；多个控制电路，位于相邻的子像素之间；一个像素岛对应连接至少n个控制电路；一个控制电路对应该像素岛中的一行子像素；控制电路被配置为：在控制信号线的控制下，将扫描信号输入线提供的信号或固定电位线提供的信号传递至扫描线。

Description

显示面板、显示装置及其驱动方法 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示装置及其驱动方法。
背景技术
随着显示技术的不断发展，超高分辨率显示已经成为一种可能，目前高达3000像素密度(PPI)的显示已经不再是幻想，然而受限于系统容量及显卡处理速度等因素，超高分辨率显示并不能普及，因此提出了一种分区驱动的智能显示模式，将人眼关注的地方正常显示，其余区域降低分辨率以及刷新频率，既可以应对系统资源不足的问题，又能满足低功耗的需求。但是，现有技术的显示产品仅能实现横向分区驱动的功能，无法实现纵向分区。
发明内容
本公开实施例提供的一种显示面板，显示面板包括：
第一衬底基板；
多条扫描线，位于第一衬底基板一侧，多条扫描线沿第一方向延伸，沿第二方向排列；第一方向和第二方向交叉；
多条数据线，与扫描线位于第一衬底基板的同一侧，多条数据线沿第二方向延伸，沿第一方向排列；
多个子像素，分别位于多条扫描线和多条数据线划分出的区域内；沿第一方向和第二方向相邻的至少两个子像素构成一个像素岛；多个子像素构成多个像素岛；每一像素岛在第二方向上包括n行子像素行；
多条扫描信号输入线，与扫描线一一对应，沿第一方向延伸，沿第二方向排列；
多条控制信号线，沿第二方向延伸，沿第一方向排列；
多条固定电位线；
多个控制电路，位于相邻的子像素之间；一个像素岛对应连接至少n个控制电路；一个控制电路对应该像素岛中的一行子像素；
控制电路被配置为：在控制信号线的控制下，将扫描信号输入线提供的信号或固定电位线提供的信号传递至扫描线。
在一些实施例中，控制电路包括：第一晶体管和第二晶体管；
第一晶体管的控制极与一条控制信号线电连接，第一晶体管的第一极与扫描信号输入线电连接，第一晶体管的第二极与扫描线电连接；
第二晶体管的控制极与一条控制信号线电连接，第二晶体管的第一极与固定电位线电连接，第二晶体管的第二极与扫描线电连接。
在一些实施例中，控制电路位于在第一方向上相邻的两个子像素之间；
多条固定电位线沿第一方向延伸，沿第二方向排列。
在一些实施例中，显示面板具体包括：
第一导电层，包括扫描线、扫描信号输入线、固定电位线、第一晶体管的控制极以及第二晶体管的控制极；
第二导电层，位于第一导电层背离第一衬底基板的一侧，包括数据线以及控制信号线；
第三导电层，位于第二导电层背离第一导电层的一侧，包括第一晶体管的第一极和第二极以及第二晶体管的第一极和第二极。
在一些实施例中，子像素包括驱动晶体管；第一导电层还包括：与扫描线电连接的驱动晶体管的控制级；
第二导电层还包括：驱动晶体管的第一极；
第三导电层还包括：驱动晶体管的第二极。
在一些实施例中，每一控制电路中，第一晶体管和第二晶体管沿第一方向排列成两行。
在一些实施例中，每一控制电路中，第一晶体管的控制极在垂直于第一方向的平面的正投影与第二晶体管的控制极在垂直于第一方向的平面的正投 影互不交叠。
在一些实施例中，第一晶体管的第一极和第二极沿第二方向排列；
第二晶体管的第一极和第二极沿第二方向排列。
在一些实施例中，第三导电层还包括：第一输入引线、第二输入引线、第一输出引线以及第二输出引线；
第一输入引线与第一晶体管的第一极电连接且与扫描信号输入线电连接；
第二输入引线与第二晶体管的第一极电连接且与固定电位线电连接；
第一输出引线与第一晶体管的第二极电连接且与扫描线电连接；
第二输出引线与第二晶体管的第二极电连接且与扫描线电连接；
第一输入引线、第二输入引线、第一输出引线以及第二输出引线均沿第二方向延伸。
在一些实施例中，控制电路位于在第二方向上相邻的两个子像素之间；
多条固定电位线沿第二方向延伸，沿第一方向排列。
在一些实施例中，显示面板具体包括：
第一导电层，包括扫描线、第一晶体管的控制极以及第二晶体管的控制极；
第二导电层，位于第一导电层背离第一衬底基板的一侧，包括扫描信号输入线；
第三导电层，位于第二导电层背离第一导电层的一侧，包括数据线；
第四导电层，位于第三导电层背离第二导电层的一侧，包括控制信号线、固定电位线、第一晶体管的第一极和第二极以及第二晶体管的第一极和第二极；控制信号线固定电位线在第一衬底基板的正投影与数据线在第一衬底基板的正投影的部分区域重叠。
在一些实施例中，第四导电层还包括：沿第二方向延伸的多条第一输出引线和多条第二输出引线；
第一晶体管的第二极通过第一输出引线与扫描线电连接；
第二晶体管的第二极通过第二输出引线与扫描线电连接；
第一输出引线和第二输出引线在第一衬底基板的正投影与数据线在第一衬底基板的正投影的部分区域重叠。
在一些实施例中，子像素包括驱动晶体管；
第一导电层还包括：与扫描线电连接的驱动晶体管的控制级；
第二导电层还包括：驱动晶体管的第一极；
显示面板还包括：
第五导电层，位于第四导电层背离第三导电层的一侧，包括驱动晶体管的第二极。
在一些实施例中，每一所像素岛对应的各控制电路在第一方向上排列成一行。
在一些实施例中，每一第一晶体管中，第一晶体管的第一极、第一晶体管的控制级以及第一晶体管的第二极沿第一方向排列；
每一第二晶体管中，第二晶体管的第一极、第二晶体管的控制级以及第二晶体管的第二极沿第一方向排列。
在一些实施例中，显示面板还包括：位于第一导电层与第一衬底基板之间的有源层；有源层包括第一晶体管的有源层以及第二晶体管的有源层；
第一晶体管的有源层包括沿第一方向延伸的部分；
第二晶体管的有源层包括沿第一方向延伸的部分。
在一些实施例中，第四导电层还包括：沿第二方向延伸的多条第一输出引线和多条第二输出引线；
第一晶体管的第二极通过第一输出引线与扫描线电连接；
第二晶体管的第二极通过第二输出引线与扫描线电连接；
第一输出引线和第二输出引线在第一衬底基板的正投影与数据线在第一衬底基板的正投影的部分区域重叠。
在一些实施例中，显示面板还包括：位于第一导电层和有源层之间的第一栅绝缘层，位于第一导电层和第二导电层之间的第二栅绝缘层，位于第二导电层和第三导电层之间的第一层间绝缘层，位于第三导电层和第四导电层 之间的第二层间绝缘层，以及位于第四导电层和第五导电层之间的第三层间绝缘层；
第四导电层还包括：多个第一连接垫、多个第二连接垫、多个第三连接垫、多个第四连接垫、以及多个第五连接垫；
驱动晶体管的第二极通过贯穿第三层间绝缘层、第二层间绝缘层、第一层间绝缘层、第二栅绝缘层、以及第一栅绝缘层的过孔与有源层电连接；
第一输入引线与第一连接垫电连接，第一连接垫通过贯穿第二层间绝缘层、以及第一层间绝缘层的过孔与扫描信号输入线电连接；
第一输出引线与第二连接垫电连接，且第二连接垫通过贯穿第二层间绝缘层、第一层间绝缘层、以及第二栅绝缘层的过孔与扫描线电连接；
第一控制信号线与第三连接垫电连接，且第三连接垫通过贯穿第二层间绝缘层、第一层间绝缘层、以及第二栅绝缘层的过孔与第一晶体管的控制级电连接；
第二控制信号线与第四连接垫电连接，且第四连接垫通过贯穿第二层间绝缘层第一层间绝缘层、以及第二栅绝缘层的过孔与第二晶体管的控制级电连接；
第二输出引线与第五连接垫电连接，且第五连接垫通过贯穿第二层间绝缘层、第一层间绝缘层、以及第二栅绝缘层的过孔与扫描线电连接；
其中，在驱动晶体管的第二极与有源层电连接的区域，第一层间绝缘层、第二栅绝缘层、以及第一栅绝缘层具有第一过孔；在第二连接垫与扫描线电连接的区域，第一层间绝缘层、以及第二栅绝缘层具有第二过孔；在驱动晶体管的第二极与有源层电连接的区域以及在第二连接垫与扫描线电连接的区域，第二层间绝缘层具有露出第一过孔和第二过孔的第三过孔。
在一些实施例中，显示面板还包括：
像素电极层，位于第五导电层背离第四导电层一侧，包括与子像素一一对应的多个像素电极；像素电极与驱动晶体管的第二极电连接；
公共电极层，位于像素电极层背离第五导电层的一侧；
多个支撑部，位于公共电极层背离像素电极层的一侧，支撑部在第一衬底基板的正投影位于相邻子像素行之间，且控制电路位于设置有支撑部的子像素行之间；
对向基板，位于支撑部背离公共电极层的一侧，包括多个沿第一方向延伸、沿第二方向排列的遮光部；遮光部在第一衬底基板的正投影覆盖支撑部在第一衬底基板的正投影以及控制电路在第一衬底基板的正投影。
在一些实施例中，每一像素岛包括：第一子像素行、第二子像素行以及第三子像素行；
第一子像素行包括沿第一方向排列的多个第一颜色子像素；
第二子像素行包括沿第一方向排列的多个第二颜色子像素；
第三子像素行包括沿第一方向排列的多个第三颜色子像素；
支撑部在衬底基板的正投影位于第一子像素行和第三子像素行之间。
在一些实施例中，第一颜色子像素为红色子像素，第二颜色子像素为绿色子像素，第三颜色子像素为蓝色子像素。
在一些实施例中，第一晶体管的控制极和第二晶体管的控制极与同一条控制信号线电连接；
第一晶体管为N型晶体管，第二晶体管为P型晶体管；或者，第一晶体管为P型晶体管，第二晶体管为N型晶体管。
在一些实施例中，第一晶体管的控制极和第二晶体管的控制极与不同的控制信号线电连接。
在一些实施例中，在第一方向上排列的一行子像素的颜色均相同。
在一些实施例中，多个像素岛分为多个控制区，每一控制区包括至少一个像素岛；
每一扫描线包括：在第一方向上排列且相互断开的多个子扫描线；每一扫描线中，子扫描线的数量与在第一方向排列的一行控制区的数量相同，且每一子扫描线对应一个控制区的一行子像素。
在一些实施例中，在每一控制区中，在第一方向上排列的一行像素岛对 应连接n个控制电路。
本公开实施例提供的一种显示装置，包括：
本公开实施例提供的显示面板；
柱透镜结构，位于显示面板的出光侧；柱透镜结构包括阵列排布的多个柱透镜；
控制器，连接显示面板，被配置为向显示面板提供驱动信号。
本公开实施例提供的一种显示装置的驱动方法，包括：
实时确定用户在显示装置的注视区域和非注视区域；
驱动注视区域以第一刷新率进行图像显示，并驱动非注视区域以第二刷新率进行图像显示；其中，第一刷新率高于第二刷新率。
在一些实施例中，驱动注视区域以第一刷新率进行图像显示，并驱动非注视区域以第二刷新率进行图像显示，具体包括：
驱动注视区域内的各子像素进行A次刷新；
驱动非注视区域内的各子像素进行B次刷新；
其中，A和B为正整数，且A大于B。
在一些实施例中，驱动注视区域内的各子像素进行刷新，具体包括：
驱动注视区域对应的各扫描信号输入线依次传输有效电平信号；
控制各控制信号线传输控制信号，将扫描信号输入线提供的信号传递至注视区域对应的扫描线，将固定电位线提供的信号传递至非注视区域对应的扫描线；
驱动非注视区域内的各子像素进行刷新，包括：
驱动显示面板内的各扫描信号输入线依次传输有效电平信号；
当扫描到注视区域对应的各子像素行时，控制各控制信号线传输控制信号，将固定电位线提供的信号传递至注视区域对应的扫描线，将扫描信号输入线提供的信号传递至非注视区域对应的扫描线。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种显示面板的结构示意图；
图2为本公开实施例提供的另一种显示面板的结构示意图；
图3为本公开实施例提供的又一种显示面板的结构示意图；
图4为本公开实施例提供的一种显示面板中子像素排布的示意图；
图5为本公开实施例提供的又一种显示面板的结构示意图；
图6为本公开实施例提供的一种显示面板中第二遮光层的结构示意图；
图7为本公开实施例提供的一种显示面板中有源层的结构示意图；
图8为本公开实施例提供的一种显示面板中第一导电层的结构示意图；
图9为本公开实施例提供的一种显示面板中第一层间绝缘层的结构示意图；
图10为本公开实施例提供的一种显示面板中第二导电层的结构示意图；
图11为本公开实施例提供的一种显示面板中第二层间绝缘层的结构示意图；
图12为本公开实施例提供的一种显示面板中第三导电层的结构示意图；
图13为本公开实施例提供的一种显示面板中第一平坦化层的结构示意图；
图14为本公开实施例提供的一种显示面板中像素电极层的结构示意图；
图15为本公开实施例提供的一种显示面板中公共电极层的结构示意图；
图16为本公开实施例提供的一种显示面板中第一遮光层的结构示意图；
图17为本公开实施例提供的又一种显示面板的结构示意图；
图18为本公开实施例提供的另一种显示面板中第二遮光层的结构示意图；
图19为本公开实施例提供的另一种显示面板中有源层的结构示意图；
图20为本公开实施例提供的另一种显示面板中第一导电层的结构示意图；
图21为本公开实施例提供的另一种显示面板中第二导电层的结构示意图；
图22为本公开实施例提供的另一种显示面板中第一层间绝缘层的结构示意图；
图23为本公开实施例提供的另一种显示面板中第三导电层的结构示意图；
图24为本公开实施例提供的另一种显示面板中第二层间绝缘层的结构示意图；
图25为本公开实施例提供的另一种显示面板中第二层间绝缘层的结构示意图；
图26为本公开实施例提供的一种显示面板中第四导电层的结构示意图；
图27为本公开实施例提供的一种显示面板中第三层间绝缘层的结构示意图；
图28为本公开实施例提供的一种显示面板中第五导电层的结构示意图；
图29为本公开实施例提供的另一种显示面板中第一钝化层的结构示意图；
图30为本公开实施例提供的另一种显示面板中像素电极层的结构示意图；
图31为本公开实施例提供的另一种显示面板中公共电极层的结构示意图；
图32为本公开实施例提供的沿图17中AA’的截面图；
图33为本公开实施例提供的沿图17中BB’的截面图；
图34为本公开实施例提供的另一种显示面板中第一遮光层的结构示意图；
图35为本公开实施例提供的一种显示装置的结构示意图；
图36为本公开实施例提供的一种显示装置的驱动方法的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所 获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供了一种显示面板，如图1～图3所示，显示面板包括：
第一衬底基板1；
多条扫描线2，位于第一衬底基板1一侧，多条扫描线2沿第一方向X延伸，沿第二方向Y排列；第一方向X和第二方向Y交叉；
多条数据线3，与扫描线2位于第一衬底基板1的同一侧，多条数据线3沿第二方向Y延伸，沿第一方向X排列；
多个子像素4，分别位于多条扫描线2和多条数据线3划分出的区域内；沿第一方向X和第二方向Y相邻的至少两个子像素4构成一个像素岛5；多个子像素4构成多个像素岛5；每一像素岛5在第二方向Y上包括n行子像素行6；
多条扫描信号输入线7，与扫描线2一一对应，沿第一方向X延伸，沿第二方向Y排列；
多条控制信号线8，沿第二方向Y延伸，沿第一方向X排列；
多条固定电位线9；
多个控制电路10，位于相邻的子像素4之间；一个像素岛5对应连接至少n个控制电路10；一个控制电路10对应该像素岛5中的一个子像素行6；
控制电路10被配置为：在控制信号线8的控制下，将扫描信号输入线7提供的信号或固定电位线9提供的信号传递至扫描线2。
本公开实施例提供的显示面板包括控制电路以及与控制电路电连接的控制信号线、固定电位线、扫描信号输入线，从而可以利用控制电路将扫描信号输入线提供的信号或固定电位线提供的信号传递至扫描线。也就是说，在图像显示过程中，对于需要刷新的区域，可以利用控制电路向对应的扫描线输入正常的扫描信号，对于不需要刷新的区域，可以利用控制电路向对应的扫描线输入固定电位线传输的固定电位信号。即可以实现对像素岛的分区驱动，从而可以节省显示产品功耗。并且，像素岛阵列排布，每个像素岛均与控制电路电连接，可以实现在第二方向上对显示面板中的各像素岛分区控制。
在具体实施时，显示面板可以是刚性显示面板，也可以是柔性显示面板，即显示面板可弯曲、可折叠。
在一些实施例中，本公开实施例提供的显示面板为液晶显示面板。其类型可以是扭曲向列(Twisted Nematic，TN)型、垂直取向(Vertical Alignment，VA)型、平面转换(In-Plane Switching，IPS)型或高级超维场转换(AdvancedSuper Dimension Switch，ADS)型等液晶显示面板。
在一些实施例中，液晶显示面板包括：相对设置的阵列基板和对向基板，以及位于阵列基板和对向基板之间的液晶层。图1～图3中的各信号线以及控制电路等例如可以设置于阵列基板。如图1～图3所述，子像素4包括驱动晶体管T3。子像素4还包括与驱动晶体管一一对应电连接的像素电极。对向基板包括第一遮光层以及彩膜。第一遮光层的开口区设置与子像素颜色对应的彩膜。在一些实施例中，液晶显示面板还包括公共电极层，公共电极层可以设置在阵列基板中，也可以设置在对向基板中。
在一些实施例中，本公开实施例提供的显示面板为电致发光显示面板。电致发光显示面板例如可以是有机发光二极管(Organic Light-EmittingDiode，OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板等。在具体实施时，每一子像素例如包括像素驱动电路以及 与像素驱动电路电连接的电致发光器件，像素驱动电路例如包括晶体管、电容等。
在一些实施例中，固定电位线输入低电平信号。
在一些实施例中，显示面板还包括栅极驱动电路，多条扫描信号输入线与所述栅极驱动电路电连接。
从而可以利用栅极驱动电路实现对多行像素岛进行分区控制，即实现横向分区控制。即在第一方向和第二方向上对显示面板中的各像素岛均可分区控制。
在一些实施例中，如图4所示，在第一方向X上排列的一行子像素4的颜色均相同。
需要说明的是图4中仅示出部分子像素。
在一些实施例中，如图1～图3所示，多个像素岛5分为多个控制区56，每一控制区56包括至少一个像素岛5；
每一扫描线2包括：在第一方向X上排列且相互断开的多个子扫描线11；每一扫描线2中，子扫描线11的数量与在第一方向X排列的一行控制区56的数量相同，且每一子扫描线11对应一个控制区56的一行子像素4。
即扫描线在控制区之间断开，从而可以利用控制电路实现对各控制区独立控制。
在一些实施例中，如图1～图3所示，一个像素岛5对应连接n个控制电路。
在一些实施例中，如图1～图3所示，在每一控制区56中，在第一方向X上排列的一行像素岛5对应连接n个控制电路10。
当然，在具体实施时，也可以是每一像素岛均连接n个控制电路。
在一些实施例中，如图1～图3所示，每一像素岛5包括3个子像素行6。即n＝3，每一像素岛5对应连接3个控制电路10。
在一些实施例中，如图1～图3所示，控制电路10包括：第一晶体管T1和第二晶体管T2；
第一晶体管T1的控制极与一条控制信号线8电连接，第一晶体管T1的第一极与扫描信号输入线7电连接，第一晶体管T1的第二极与扫描线2电连接；
第二晶体管T2的控制极与一条控制信号线8电连接，第二晶体管T2的第一极与固定电位线9电连接，第二晶体管T2的第二极与扫描线2电连接。
在具体实施时，对于一个控制区对应的多个控制电路，在控制信号线输入的控制信号的控制下，当第一晶体管打开而第二晶体管关断时，扫描信号输入线输入的信号通过第一晶体管传输至扫描线，以对该控制区的像素岛进行刷新。在控制信号线输入的控制信号的控制下，当第二晶体管打开而第一晶体管关断时，固定电位线输入的低电平信号通过第二晶体管传输至扫描线，即对该控制区的像素岛不需要刷新。
在一些实施例中，一个控制电路中的第一晶体管T1的第二极和第二晶体管T1的第二极与同一条子扫描线电连接。
在一些实施例中，如图1所示，第一晶体管T1的控制极和第二晶体管T1的控制极与同一条控制信号线8电连接；
第一晶体管为N型晶体管，第二晶体管为P型晶体管；或者，第一晶体管为P型晶体管，第二晶体管为N型晶体管。
在一些实施例中，如图2、图3所示，第一晶体管T1的控制极和第二晶体管T2的控制极与不同的控制信号线8电连接。
在一些实施例中，如图2、图3所示，多条控制信号线8包括：多条第一控制信号线12和多条第二控制信号线13；
第一晶体管T1的控制极与第一控制信号线12电连接，第二晶体管T2的控制极与第二控制信号线13电连接。
在具体实施时，当第一晶体管的控制极和第二晶体管的控制极与不同的控制信号线电连接时，第一晶体管可以为N型晶体管，也可以为P型晶体管，第二晶体管可以为N型晶体管，也可以为P型晶体管。
在一些实施例中，如图1、图2所示，控制电路10位于在第一方向X上 相邻的两个子像素4之间；
多条固定电位线9沿第一方向X延伸，沿第二方向Y排列。
即如图1、图2所示，控制电路10位于相邻两列子像素4之间。
接下来以控制电路位于相邻两列子像素之间为例，对显示面板的结构进行举例说明。
在一些实施例中，如图5所示，显示面板具体包括：
第一导电层14，包括扫描线2、扫描信号输入线7、固定电位线9、第一晶体管T1的控制极G1以及第二晶体管T2的控制极G2；
第二导电层15，位于第一导电层14背离第一衬底基板的一侧，包括数据线3以及控制信号线8；
第三导电层17，位于第二导电层15背离第一导电层14的一侧，包括第一晶体管T1的第一极S1和第二极D2、以及第二晶体管T2的第一极S2和第二极D2。
与图5对应的第一导电层14、第二导电层15、第三导电层17的图案分别如图8、图10、图12所示。
在一些实施例中，如图5所示，每一控制电路中，第一晶体管T1和第二晶体管T2沿第一方向排列成两行。
在一些实施例中，如图5、图8所示，每一控制电路中，第一晶体管T1的控制极G1在垂直于第一方向的平面的正投影与第二晶体管T2的控制极G2在垂直于第一方向的平面的正投影互不交叠。即第一晶体管T1的控制极G1以及第二晶体管T2的控制极G2并不是沿与第一方向平行的一条直线排列，这样，即便第一晶体管T1的控制极G1以及第二晶体管T2的控制极G2在第二方向上具有交叠区域，第一晶体管T1的控制极G1以及第二晶体管T2的控制极G2也不会出现短路的问题。相应的，可以减小在第一方向上第一晶体管T1和第二晶体管T2的总宽度，从而最大限度的降低控制电路的设置对开口率造成的影响。
在一些实施例中，如图5、图10所示，在第二方向上，每一第一晶体管 T1中，第一晶体管T1的第一极S1位于第一晶体管T1的第二极D2一侧；在第二方向上，每一第二晶体管T2中，第二晶体管T2的第一极S2位于第二晶体管T2的第二极D2的一侧。即第一晶体管T1的第一极S1和第二极D2沿第二方向排列，第二晶体管T2的第一极S2和第二极D2也沿第二方向排列。这样，可以进一步避免增加在第一方向上第一晶体管T1的宽度以及在第一方向上第二晶体管T2的宽度，从而最大限度的降低控制电路的设置对开口率造成的影响。
在一些实施例中，当显示面板为液晶显示面板时，子像素包括驱动晶体管；第一导电层还包括：与扫描线2电连接的驱动晶体管的控制级；
第二导电层还包括：驱动晶体管的第一极；
第三导电层还包括：驱动晶体管的第二极。
在具体实施时，驱动晶体管的第一极和第二极位于不同导电层，并且控制电路各晶体管的第一极和第二极与控制信号线位于不同导电层，从而可以缩小驱动晶体管的第二极与数据线之间的距离以及缩小控制电路各晶体管的第一极和第二极与控制信号线之间的距离，且不会导致驱动晶体管的第二极与数据线短路，也不会导致控制电路各晶体管的第一极和第二极与控制信号线之间短路，可以减小显示面板版图设计难度。
在一些实施例中，显示面板还包括：位于第三导电层背离第二导电层15一侧的像素电极层，以及像素电极层背离第三导电层一侧的公共电极层。其中像素电极层包括与子像素一一对应的像素电极。公共电极层包括公共电极。需要说明的是，为了便于清楚示意控制电路的结构，图5中并未示出公共电极层和像素电极层的图案。在具体实施时，像素电极层21的图案如图14所示，公共电极层35的图案如图15所示。
在一些实施例中，如图5、图6、图7、图9、图11、图13所示，显示面板还包括第一导电层14和第一衬底基板之间的第二遮光层16，第二遮光层16和第一导电层14之间的有源层18，有源层18和第二遮光层16之间的缓冲层(未示出)，第一导电层14和有源层18之间的栅绝缘层，第一导电层14 和第二导电层15之间的第一层间绝缘层19，第二导电层15和第三导电层17之间的第二层间绝缘层20，第三导电层17和像素电极层之间的第一平坦化层22，以及像素电极层和公共电极层之间的第二平坦化层。其中，图6、图7、图9、图11、图13分别为第二遮光层16、有源层18、第一层间绝缘层19、第二层间绝缘层20、以及第一平坦化层22的图案，图9、图11、图13中虚线区域为第一层间绝缘层19、第二层间绝缘层20、第一平坦化层22的过孔的区域。
在一些实施例中，如图5所示，第三导电层还包括：第一输入引线23、第二输入引线24、第一输出引线25以及第二输出引线26。第一输入引线23与第一晶体管T1的第一极S1电连接，且通过贯穿第二层间绝缘层、以及第一层间绝缘层的过孔与扫描信号输入线7电连接。第二输入引线24与第二晶体管T2的第一极S2电连接且通过第二层间绝缘层、以及第一层间绝缘层的过孔与固定电位线9电连接。第一输出引线25与第一晶体管T1的第二极D2电连接且通过贯穿第二层间绝缘层、以及第一层间绝缘层的过孔与扫描线2电连接，第二输出引线26与第二晶体管T2的第二极D2电连接且通过贯穿第二层间绝缘层、以及第一层间绝缘层的过孔与扫描线2电连接。第一输入引线23、第二输入引线24、第一输出引线25以及第二输出引线26均沿第二方向Y延伸。
在具体实施时，第一输入引线23与第一晶体管T1的第一极S1一体连接。第二输入引线24与第二晶体管T2的第一极S2一体连接。第一输出引线25与第一晶体管T1的第二极D2一体连接。第二输出引线26与第二晶体管T2的第二极D2一体连接。
在一些实施例中，第一控制信号线12通过贯穿第一层间绝缘层的过孔与第一晶体管T1的控制极G1电连接。第二控制信号线13通过贯穿第一层间绝缘层的过孔与第二晶体管T2的控制极G2电连接。第一晶体管T1的第一极S1和第二极D2、以及第二晶体管T2的第一极S2和第二极D2通过贯穿第二层间绝缘层、第一层间绝缘层以及栅绝缘层的过孔与有源层电连接。像素电 极通过贯穿第一平坦化层的过孔与驱动晶体管的第二极电连接。驱动晶体管的第一极通过贯穿第一层间绝缘层以及栅绝缘层的过孔与有源层电连接，驱动晶体管的第二极通过贯穿第二层间绝缘层、第一层间绝缘层以及栅绝缘层的过孔与有源层电连接。
在一些实施例中，控制电路阵列排布，在第二方向上位于同一列的第一晶体管的控制级与同一条第一控制信号线电连接，在第二方向上位于同一列的第二晶体管的控制级与同一条第二控制信号线电连接。在第一方向上位于同一行的第一晶体管的第一极与同一条扫描信号输入线电连接，在第一方向上位于同一行的第二晶体管的第一极与同一条固定电位线电连接。
在一些实施例中，如图16所示，对向基板中的第一遮光层包括沿第一方向X延伸的多个第一遮光部36以及沿第二方向Y延伸的多个第二遮光部37。其中，第一遮光部36覆盖相邻子像素行之间，即第一遮光部36覆盖扫描线、固定电位线以及扫描信号输入线。当在第一方向X上排列的子像素颜色均相同时，第二遮光部37仅覆盖设置有控制电路的子像素列之间，即第二遮光部覆盖控制电路、控制信号线以及各输入引线和输出引线。而未设置控制电路的子像素列之间无需设置第二遮光部，从而可以在实现对控制电路及控制下遮挡的情况下尽可能提高子像素开口率。
或者，在一些实施例中，如图3所示，控制电路10位于在第二方向Y上相邻的两个子像素4之间；
多条固定电位线9沿第二方向Y延伸，沿第一方向X排列。
即控制电路10位于相邻子像素行之间。
在一些实施例中，每一所像素岛对应的各控制电路在第一方向X上排列成一行。
在一些实施例中，在第二方向上排列成一列的第一晶体管的控制极与同一条所述第一控制信号线电连接。在第二方向上排列成一列的第二晶体管的控制极与同一条所述第二控制信号线电连接，在第二方向上排列成一列的第二晶体管的第一极与同一条固定电位线电连接。
接下来以控制电路位于相邻子像素行之间为例，对显示面板的结构进行举例说明。
在一些实施例中，如图17所示，显示面板具体包括：
第一导电层14，包括扫描线2、第一晶体管T1的控制极G1以及第二晶体管T2的控制极G2；
第二导电层15，位于第一导电层14背离第一衬底基板的一侧，包括扫描信号输入线7；
第三导电层17，位于第二导电层15背离第一导电层14的一侧，包括数据线3；
第四导电层38，位于第三导电层17背离第二导电层15的一侧，包括控制信号线8、固定电位线9、第一晶体管T1的第一极S1和第二极D1以及第二晶体管T2的第一极S2和第二极D2；控制信号线8、固定电位线9在第一衬底基板的正投影与数据线3在第一衬底基板的正投影的部分区域重叠。
其中，图20、图21、图23、图26分别示出与图17对应的第一导电层14、第二导电层15、第三导电层17、第四导电层38的图案。
需要说明的是，图17为一个控制区内部分区域的图案，因此并未示出子扫描线之间断开的区域。
在具体实施时，由于控制信号线、固定电位线与数据线位于不同导电层，这样，控制信号线、固定电位线在第一衬底基板的正投影与数据线在第一衬底基板的正投影的部分区域重叠，从而可以避免与控制电路电连接的各信号线对子像素开口率造成影响。
在一些实施例中，子像素包括驱动晶体管；
第一导电层还包括：与扫描线电连接的驱动晶体管的控制级；
第二导电层还包括：驱动晶体管的第一极；
如图17、图28所示，显示面板还包括：
第五导电层42，位于第四导电层38背离第三导电层17的一侧，包括驱动晶体管的第二极D3。
其中，图28为与图17对应的第五导电层42的图案。
在具体实施时，驱动晶体管的第一极和第二极位于不同导电层，从而可以缩小驱动晶体管的第二极与数据线之间的距离，且不会导致驱动晶体管的第二极与数据线短路，从而可以减小显示面板版图设计难度。
在一些实施例中，显示面板还包括：位于第五导电层背离第四导电层一侧的像素电极层，以及像素电极层背离第五导电层一侧的公共电极层。其中像素电极层包括与子像素一一对应的像素电极。公共电极层包括公共电极。需要说明的是，为了便于清楚示意控制电路的结构，图17中并未示出公共电极层和像素电极层的图案。在具体实施时，像素电极层21的图案如图30所示，公共电极层35的图案如图31所示。
需要说明的是，像素电极层和公共电极层可以采用透过率较高的材料。像素电极层和公共电极层例如可以包括氧化铟锡(ITO)。即阵列基板可以设置两层ITO层。第一层ITO作为像素电极层，从而可以减少过孔数量，提升开口率。在一些实施例中，显示面板还包括与公共电极位于同层的金属公共电极线。在具体实施时，例如在第二钝化层上线形成公共电极线，之后再形成与公共电极线电连接的ITO公共电极。
在一些实施例中，如图17、图18、图19、图22、图24、图25、图27、图29、图32、图33所示，显示面板还包括第一导电层14和第一衬底基板之间的第二遮光层16，第二遮光层16和第一导电层14之间的有源层18，有源层18和第二遮光层16之间的缓冲层27，第一导电层14和有源层18之间的第一栅绝缘层28，第一导电层14和第二导电层15之间的第二栅绝缘层29，第二导电层15和第三导电层17之间的第一层间绝缘层19，第三导电层17和第四导电层38之间的第二层间绝缘层20，第四导电层38和第五导电层42之间的第三层间绝缘层43，第五导电层和像素电极层之间的第一钝化层44，以及像素电极层和公共电极层之间的第二钝化层30。其中，图18、图19、图22、图27、图29分别为第二遮光层16、有源层18、第一层间绝缘层19、第三层间绝缘层43、以及第一钝化层44的图案。图32为沿图17中AA’的截面 图，图33为沿图17中BB’的截面图。图22、图27、图29中虚线区域分别为第一层间绝缘层19、第三层间绝缘层43、第一钝化层44的过孔的区域。图24、图25中虚线区域对应形成第二层间绝缘层20之后形成过孔的区域。
在具体实施时，第二层间绝缘层起到平坦化层的作用，形成第二层间绝缘层20之后，先在如图24所示的虚线区域进行第一道图形化工艺形成过孔。之后，在第一道图形化工艺形成的过孔基础上，再在如图25所示的虚线区域进行第二道图形化工艺形成过孔。需要说明的是，在形成第一层间绝缘层之后，未在如图25所示的虚线区域形成过孔，这样，在如图25所示的虚线区域进行第二道图形化工艺，便可以在第一层间绝缘层及其下方的膜层形成相应的过孔，后续第四导电层便可以通过如图25所示的虚线区形成的过孔与有源层或第一导电层电连接。
在一些实施例中，如图17所示，每一控制电路中的第一晶体管T1和第二晶体管T2在第一方向上排列成一行。
在一些实施例中，如图17所示，每一第一晶体管中，第一晶体管T1的第一极S1、第一晶体管T1的控制级G1以及第一晶体管T1的第二极D1沿第一方向排列；
每一第二晶体管T2中，第二晶体管T2的第一极S1、第二晶体管T2的控制级G1以及第二晶体管T的第二极D1沿第一方向排列。
即每一控制电路中的第一晶体管和第二晶体管在第一方向X上排列成一行时，控制电路中各晶体管的第一极、控制极、第二极也在第一方向X上排列成一行，从而可以减小控制电路在第二方向Y上的尺寸，可以进一步避免与控制电路对子像素开口率造成影响。
在一些实施例中，如图17所示，第一晶体管T1的有源层包括沿第一方向延伸的部分；
第二晶体管T2的有源层包括沿第一方向延伸的部分。
在一些实施例中，如图17、图26所示，第四导电层38还包括：沿第二方向Y延伸的多条第一输出引线25和多条第二输出引线26；
第一晶体管T1的第二极D1通过第一输出引线25与扫描线2电连接；
第二晶体管T2的第二极D2通过第二输出引线26与扫描线2电连接；
第一输出引线25和第二输出引线26在第一衬底基板的正投影与数据线3在第一衬底基板的正投影的部分区域重叠。
在具体实施时，由于第一输出引线、第一输入引线以及第二输入引线与数据线位于不同导电层，这样，第一输出引线、第一输入引线以及第二输入引线在第一衬底基板的正投影与数据线在第一衬底基板的正投影的部分区域重叠，从而可以避免与控制电路电连接的各信号线对子像素开口率造成影响。
在一些实施例中，如图17、图26所示，第四导电层38还包括：第一输入引线23，第一晶体管T1的第一极S1通过第一输入引线23与扫描信号输入线7电连接。
在一些实施例中，如图17、图26所示，第四导电层38还包括：多个第一连接垫39、多个第二连接垫40、多个第三连接垫41、多个第四连接垫45、以及多个第五连接垫46。其中，第一输入引线23与第一连接垫39电连接，第一连接垫39通过贯穿第二层间绝缘层、以及第一层间绝缘层的过孔与扫描信号输入线7电连接。如图32所示，第一输出引线25与第二连接垫40电连接，且第二连接垫40通过贯穿第二层间绝缘层20、第一层间绝缘层19、以及第二栅绝缘层29的过孔33与扫描线2电连接。第一控制信号线12与第三连接垫41电连接，且第三连接垫41通过贯穿第二层间绝缘层、第一层间绝缘层、以及第二栅绝缘层的过孔与第一晶体管的控制级电连接。第二控制信号线13与第四连接垫45电连接，且第四连接垫45通过贯穿第二层间绝缘层、第一层间绝缘层、以及第二栅绝缘层的过孔与第二晶体管的控制级电连接。第二输出引线26与第五连接垫46电连接，且第五连接垫46通过贯穿第二层间绝缘层、第一层间绝缘层、以及第二栅绝缘层的过孔与扫描线电连接。
在一些实施例中，如图32所示，第二连接垫40通过贯穿第二层间绝缘层20、第一层间绝缘层19、以及第二栅绝缘层29的第四过孔33与扫描线2电连接的区域。在具体实施时，在形成第二层间绝缘层20之后，第四过孔33 对应的区域，先进行一道图形化工艺在第二层间绝缘层20形成过孔，之后，进行第二道图形化工艺在第一层间绝缘层19、以及第二栅绝缘层29形成过孔，第二层间绝缘层20的过孔尺寸h1大于第二栅绝缘层29的过孔的尺寸，相应的，第二连接垫40在第四过孔33的区域呈阶梯状延伸，第二连接垫40在第二栅绝缘层29的过孔处的平面区域的尺寸为h2。在具体实施时h1例如为4微米，h2例如为2.5微米。
在一些实施例中，如图33所示，驱动晶体管的第二极D3通过贯穿第三层间绝缘层43、第二层间绝缘层20、第一层间绝缘层19、第二栅绝缘层29、以及第一栅绝缘层28的过孔与有源层18电连接。第二连接垫40通过贯穿第二层间绝缘层20、第一层间绝缘层19、以及第二栅绝缘层29的过孔与扫描线2电连接。其中，在驱动晶体管的第二极D3与有源层18电连接的区域，第一层间绝缘层19、第二栅绝缘层29、以及第一栅绝缘层28具有第一过孔55，在第二连接垫40与扫描线2电连接的区域，第一层间绝缘层19、以及第二栅绝缘层29具有第二过孔32；在驱动晶体管的第二极D3与有源层18电连接的区域以及在第二连接垫40与扫描线2电连接的区域，第二层间绝缘层20具有露出第一过孔55和第二过孔32的第三过孔34。在具体实施时，形成第二层间绝缘层20之后需要进行两道图形化工艺形成过孔时，先进行一道图形化工艺在第三过孔34的区域去除第二层间绝缘层20，之后，进行第二道图形化工艺形成第二过孔32。在具体实施时，第一过孔55露出有源层18的尺寸h4例如为3微米。第一过孔55露出有源层18的边缘与第二层间绝缘层20露出第一层间绝缘层19边缘之间的距离h3例如为1.5微米。第一过孔55露出有源层18的边缘与扫描线之间的距离h5例如为2.05微米。第二过孔32露出扫描线2的尺寸h6例如为2.5微米，第二过孔32露出扫描线2的边缘与扫描信号输入线7之间的距离h7例如为2.5微米。
在一些实施例中，显示面板还包括：
对向基板，位于支撑部背离公共电极层的一侧，包括遮光部；
液晶层，位于对向基板和公共电极层之间。
在一些实施例中，对向基板包括第一遮光层，第一遮光层包括遮光部。当显示面板为液晶显示面板，在第一方向X上排列的子像素颜色均相同，且控制电路位于相邻子像素行之间时，如图34所示，对向基板中的第一遮光层的遮光部可以仅包括沿第一方向X延伸的多个第一遮光部36。第一遮光部36覆盖相邻子像素行之间，即第一遮光部36覆盖扫描线、固定电位线、扫描信号输入线、以及控制电路。由于子像素列之间未设置控制电路，且各控制信号线、各固定电位线、各输入子引线以及各输出子引线的正投影与扫描线的部分区域重叠。因此子像素列之间无需设置第二遮光部，从而可以提高子像素开口率。
在一些实施例中，如图34所示，显示面板还包括：
多个支撑部47，位于公共电极层背离像素电极层的一侧，支撑部47在第一衬底基板的正投影位于相邻子像素行6之间，且控制电路位于设置有支撑部47的子像素行之间。
在一些实施例中，如图34所示，每一像素岛5包括：第一子像素行48、第二子像素行49以及第三子像素行50；
第一子像素行48包括沿第一方向X排列的多个第一颜色子像素；
第二子像素行49包括沿第一方向X排列的多个第二颜色子像素；
第三子像素行50包括沿第一方向X排列的多个第三颜色子像素；
在一些实施例中，如图34所示，在第二方向Y上，覆盖第一子像素行48与第二子像素行49之间的第一遮光部36的宽度、以及覆盖第二子像素行49与第三子像素行50之间的第一遮光部36的宽度均小于覆盖第一子像素行48与第三子像素行50之间的第一遮光部36的宽度；
支撑部47在衬底基板的正投影位于第一子像素行48和第三子像素行50之间。
相应的，控制电路设置在第一子像素行和第三子像素行之间。
在具体实施时，遮光部在第一衬底基板的正投影覆盖支撑部在第一衬底基板的正投影以及控制电路在第一衬底基板的正投影。由于支撑部设置在第 一遮光部在第二方向Y上的宽度较宽的区域。因此，本公开实施例提供的显示面板，将控制电路设置于支撑部的区域，从而可以避免影响显示面板开口率。
在一些实施例中，如图34所示，第一颜色子像素为红色子像素R，第二颜色子像素为绿色子像素G，第三颜色子像素为蓝色子像素B。
需要说明的是，相比于红色子像素和蓝色子像素，绿色子像素的发光效率受到开口率影响更大。因此本公开实施例提供的显示面板在第一遮光部在第二方向Y上的宽度较宽的区域设置于红色子像素行和蓝色子像素行之间，可以避免增大第一遮光部在第二方向Y上的宽度对绿色子像素的影响。
接下来，以显示面板为液晶显示面板，且控制电路位于相邻子像素行之间为例，对本公开实施例提供的显示面板的制备进行举例说明，阵列基板的制备方法包括如下步骤：
S101、在第一衬底基板上沉积第二遮光层材料，并采用图形化工艺形成第二遮光层的图案；
S102、沉积缓冲层材料形成缓冲层；
S103、沉积半导体材料，并刻蚀形成有源层的图案；
S103、沉积栅绝缘层材料，形成第一栅绝缘层；
S104、沉积栅极金属材料，并刻蚀形成扫描线的初始图案、第一晶体管的控制级的图案、以及第二晶体管的控制级的图案，并进行半导体自对准掺杂工艺在有源层形成导体化区域；其中，扫描线的初始图案中的每一扫描线一体连接；
S105、对扫描线的初始图案进行刻蚀工艺，每一扫描线形成多条相互断开的子扫描线；
S106、沉积栅绝缘层材料，形成第二栅绝缘层；
S107、沉积金属材料形成第二导电层，并刻蚀形成扫描信号输入线的图案；
S108、沉积第一层间绝缘层材料，并刻蚀形成过孔；
S109、沉积金属材料形成第三导电层，并刻蚀形成数据线以及驱动晶体管第一极的图案；
S110、沉积平坦化层材料，形成第二层间绝缘层，并采用第一道刻蚀工艺形成过孔；
S111、再次采用刻蚀工艺形成过孔；
S112、沉积金属材料形成第四导电层，并刻蚀形成控制信号线、固定电位线、输入引线、输出引线、连接垫、第一晶体管的第一极和第二极的图案、以及第二晶体管的第一极和第二极的图案；
S113、沉积第三层间绝缘层材料，并刻蚀形成过孔；
S114、沉积金属材料形成第五导电层，并刻蚀形成驱动晶体管第二极的图案；
S115、沉积第一钝化层的材料，形成第一钝化层，并采用曝光工艺形成过孔；
S116、沉积ITO形成像素电极层，并刻蚀形成像素电极；
S117、沉积第二钝化层的材料，形成第二钝化层并刻蚀形成周边区域过孔；
S118、沉积金属材料，并刻蚀形成公共电极线的图案；
S119、沉积ITO，并刻蚀形成公共电极的图案。
在一些实施例中，形成公共电极的图案还包括形成保护层的步骤。当支撑部包括设置在阵列基板一侧的部分时，形成保护层之后还包括形成支撑部的步骤。
本公开实施例提供的一种显示装置，如图35所示，包括：
本公开实施例提供的显示面板51；
柱透镜结构52，位于显示面板51的出光侧；柱透镜结构52包括阵列排布的多个柱透镜；
控制器(未示出)，连接显示面板，被配置为向显示面板提供驱动信号。
在具体实施时，在图像显示过程中，对于需要刷新的区域，可以通过控 制器提供的驱动信号驱动控制电路向像素岛对应的扫描线输入正常的扫描信号，对于不需要刷新的区域，可以通过控制器提供的驱动信号驱动控制电路向像素岛对应的扫描线输入固定电位线传输的固定电位信号，从而实现对像素岛的分区驱动，可以节省显示装置功耗。
在一些实施例中，如图6所示，显示装置还包括：
透光隔垫层53，位于显示面板51和柱透镜结构52之间；
平坦层54，位于柱透镜结构52背离透光隔垫层53一侧。
在一些实施例中，当显示面板为液晶显示面板时，显示装置例如还包括位于显示面板背离柱透镜结构的背光模组。
在一些实施例中，显示装置还包括：
人眼追踪系(eye-tracking)，用于实时确定用户眼睛在显示装置的注视区域。
在具体实施时，可以对注视区进行高频刷新，而非注视区进行低频刷新。
在具体实施时，由于是在像素岛(可作为二维图像(2D)显示的一个像素)内进行的子像素细分，在三维图像(3D)显示模式下可以保持与2D显示同样的分辨率，结合eye-tracking能够实现大视角的多视点(view)显示，并且能够实现更高像素密度(PPI)的3D显示，信息量更大，相邻视点间的颜色串扰更低，还可以降低用户观看3D图像时的晕眩感，提升用户体验。当显示装置设置有柱透镜阵列时，柱透镜阵列不仅可以对像素岛中的子像素进行像素映射，还能够对像素岛的出射光线进行光场调制，从而使最终的像素岛的出射光线形成多个视点，从而实现光场3D显示。
本公开实施例提供的显示装置为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
基于同一发明构思，本公开实施例还提供了一种显示装置的驱动方法， 如图36所示，包括：
S201、实时确定用户在显示装置的注视区域和非注视区域；
S202、驱动注视区域以第一刷新率进行图像显示，并驱动非注视区域以第二刷新率进行图像显示；其中，第一刷新率高于第二刷新率。
本公开实施例提供的显示装置的驱动方法，注视区域的刷新频率高于非注视区域的刷新频率，从而可以在不影响用户正常观看显示画面的情况下对显示装置的刷新率进行分区控制，可以节省显示装置功耗。
在一些实施例中，实时确定用户在所述显示装置的注视区域和非注视区域，包括：
利用人眼追踪系统确定用户在显示装置的注视区域；
将显示装置中除注视区域以外的其它区域确定为非注视区域。
在一些实施例中，驱动注视区域以第一刷新率进行图像显示，并驱动非注视区域以第二刷新率进行图像显示，具体包括：
驱动注视区域内的各子像素进行A次刷新；
驱动非注视区域内的各子像素进行B次刷新；
其中，A和B为正整数，且A大于B。
在一些实施例中，驱动注视区域内的各子像素进行刷新，具体包括：
驱动注视区域对应的各扫描信号输入线依次传输有效电平信号；
控制各控制信号线传输控制信号，将扫描信号输入线提供的信号传递至注视区域对应的扫描线，将固定电位线提供的信号传递至非注视区域对应的扫描线；
驱动非注视区域内的各子像素进行刷新，包括：
驱动显示面板内的各扫描信号输入线依次传输有效电平信号；
当扫描到注视区域对应的各子像素行时，控制各控制信号线传输控制信号，将固定电位线提供的信号传递至注视区域对应的扫描线，将扫描信号输入线提供的信号传递至非注视区域对应的扫描线。
在具体实施时，当第一晶体管的控制级、第二晶体管的控制级与同一控 制信号线电连接时；
控制各控制信号线传输控制信号，将扫描信号输入线提供的信号传递至注视区域对应的扫描线，将固定电位线提供的信号传递至非注视区域对应的扫描线，具体包括：
驱动注视区域的各控制信号线传输第一控制信号，驱动非注释区域的各控制信号线传输第二控制信号，以控制注视区域的第一晶体管打开、第二晶体管关断，非注视区的第一晶体管关断、第二晶体管打开，将扫描信号输入线提供的信号通过控制区域的各第一晶体管传递至控制区域对应的扫描线，同时将固定电位线提供的信号通过非注视区域的第二晶体管传递至非注视区域对应的扫描线；
当扫描到注视区域对应的各子像素行时，控制各控制信号线传输控制信号，将固定电位线提供的信号传递至注视区域对应的扫描线，将扫描信号输入线提供的信号传递至非注视区域对应的扫描线，具体包括：
驱动注视区域的各控制信号线传输第二控制信号，驱动非注释区域的各控制信号线传输第一控制信号，以控制注视区域的第一晶体管关断、第二晶体管打开，非注视区的第一晶体管打开、第二晶体管关断，将扫描信号输入线提供的信号通过非控制区域的各第一晶体管传递至非控制区域对应的扫描线，同时将固定电位线提供的信号通过注视区域的第二晶体管传递至注视区域对应的扫描线。
在具体实施时，当第一晶体管为P型晶体管、第二晶体管为N型晶体管时，第一信号为低电平信号，第二信号为高电平信号；当第一晶体管为N型晶体管、第二晶体管为P型晶体管时，第一信号为高电平信号，第二信号为低电平信号。
在具体实施时，当第一晶体管的控制级与第一控制信号线电连接、第二晶体管的控制级第二控制信号线电连接时；
控制各控制信号线传输控制信号，将扫描信号输入线提供的信号传递至注视区域对应的扫描线，将固定电位线提供的信号传递至非注视区域对应的 扫描线，具体包括：
驱动注视区域的各第一控制信号线传输第一控制信号、各第二控制信号线传输第二控制信号，驱动非注释区域的各第一控制信号线传输第三控制信号、各第二控制信号线传输第四控制信号，以控制注视区域的第一晶体管打开、第二晶体管关断，非注视区的第一晶体管关断、第二晶体管打开，将扫描信号输入线提供的信号通过控制区域的各第一晶体管传递至控制区域对应的扫描线，同时将固定电位线提供的信号通过非注视区域的第二晶体管传递至非注视区域对应的扫描线；
当扫描到注视区域对应的各子像素行时，控制各控制信号线传输控制信号，将固定电位线提供的信号传递至注视区域对应的扫描线，将扫描信号输入线提供的信号传递至非注视区域对应的扫描线，具体包括：
驱动注视区域的各第一控制信号线传输第三控制信号、各第二控制信号线传输第四控制信号，驱动非注释区域的各第一控制信号线传输第一控制信号、各第二控制信号线传输第二控制信号，以控制注视区域的第一晶体管关断、第二晶体管打开，非注视区的第一晶体管打开、第二晶体管关断，将扫描信号输入线提供的信号通过非控制区域的各第一晶体管传递至非控制区域对应的扫描线，同时将固定电位线提供的信号通过注视区域的第二晶体管传递至注视区域对应的扫描线。
在一些实施例中，当第一晶体管、第二晶体管均为P型晶体管时，第一信号、第四信号为低电平信号，第二信号、第三信号为高电平信号。当第一晶体管、第二晶体管均为N型晶体管时，第一信号、第四信号为高电平信号，第二信号、第三信号为低电平信号。当第一晶体管为P型晶体管、第二晶体管为N型晶体管时，第一信号、第二信号为低电平信号，第三信号、第四信号为高电平信号；当第一晶体管为N型晶体管、第二晶体管为P型晶体管时，第一信号、第二信号为高电平信号，第三信号、第四信号为低电平信号。
综上所述，本公开实施例提供的显示面板、显示装置及其驱动方法，显示面板包括控制电路，以及与控制电路电连接的控制信号线、固定电位线、 扫描信号输入线，从而可以利用控制电路将扫描信号输入线提供的信号或固定电位线提供的信号传递至扫描线。也就是说，在图像显示过程中，对于需要刷新的区域，可以利用控制电路向像素岛对应的扫描线输入正常的扫描信号，对于不需要刷新的区域，可以利用控制电路向像素岛对应的扫描线输入固定电位线传输的固定电位信号。即可以利用控制电路及控制信号线、固定电位线、扫描信号输入线实现对像素岛的分区驱动。从而可以节省显示产品功耗。并且，像素岛阵列排布，每个像素岛均与控制电路电连接，还可以实现在第二方向上对显示面板中的各像素岛实现分区控制。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (30)

  1. 一种显示面板，其中，所述显示面板包括：
    第一衬底基板；
    多条扫描线，位于所述第一衬底基板一侧，所述多条扫描线沿第一方向延伸，沿第二方向排列；所述第一方向和所述第二方向交叉；
    多条数据线，与所述扫描线位于所述第一衬底基板的同一侧，所述多条数据线沿所述第二方向延伸，沿所述第一方向排列；
    多个子像素，分别位于多条所述扫描线和多条所述数据线划分出的区域内；沿所述第一方向和所述第二方向相邻的至少两个子像素构成一个像素岛；所述多个子像素构成多个所述像素岛；每一所述像素岛在所述第二方向上包括n行子像素行；
    多条扫描信号输入线，与所述扫描线一一对应，沿所述第一方向延伸，沿所述第二方向排列；
    多条控制信号线，沿所述第二方向延伸，沿所述第一方向排列；
    多条固定电位线；
    多个控制电路，位于相邻的所述子像素之间；一个所述像素岛对应连接至少n个所述控制电路；一个所述控制电路对应该像素岛中的一行子像素；
    所述控制电路被配置为：在所述控制信号线的控制下，将所述扫描信号输入线提供的信号或所述固定电位线提供的信号传递至所述扫描线。
  2. 根据权利要求1所述的显示面板，其中，所述控制电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的控制极与一条所述控制信号线电连接，所述第一晶体管的第一极与所述扫描信号输入线电连接，所述第一晶体管的第二极与所述扫描线电连接；
    所述第二晶体管的控制极与一条所述控制信号线电连接，所述第二晶体管的第一极与所述固定电位线电连接，所述第二晶体管的第二极与所述扫描 线电连接。
  3. 根据权利要求2所述的显示面板，其中，所述控制电路位于在所述第一方向上相邻的两个所述子像素之间；
    多条固定电位线沿所述第一方向延伸，沿所述第二方向排列。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板具体包括：
    第一导电层，包括所述扫描线、所述扫描信号输入线、所述固定电位线、所述第一晶体管的控制极以及所述第二晶体管的控制极；
    第二导电层，位于所述第一导电层背离所述第一衬底基板的一侧，包括所述数据线以及所述控制信号线；
    第三导电层，位于所述第二导电层背离所述第一导电层的一侧，包括所述第一晶体管的第一极和第二极以及所述第二晶体管的第一极和第二极。
  5. 根据权利要求4所述的显示面板，其中，所述子像素包括驱动晶体管；所述第一导电层还包括：与所述扫描线电连接的所述驱动晶体管的控制级；
    所述第二导电层还包括：所述驱动晶体管的第一极；
    所述第三导电层还包括：所述驱动晶体管的第二极。
  6. 根据权利要求5所述的显示面板，其中，每一所述控制电路中，所述第一晶体管和所述第二晶体管沿所述第一方向排列成两行。
  7. 根据权利要求6所述的显示面板，其中，每一所述控制电路中，所述第一晶体管的控制极在垂直于所述第一方向的平面的正投影与所述第二晶体管的控制极在垂直于所述第一方向的平面的正投影互不交叠。
  8. 根据权利要求7所述的显示面板，其中，所述第一晶体管的第一极和第二极沿所述第二方向排列；
    所述第二晶体管的第一极和第二极沿所述第二方向排列。
  9. 根据权利要求8所述的显示面板，其中，所述第三导电层还包括：第一输入引线、第二输入引线、第一输出引线以及第二输出引线；
    所述第一输入引线与所述第一晶体管的第一极电连接且与所述扫描信号输入线电连接；
    所述第二输入引线与所述第二晶体管的第一极电连接且与所述固定电位线电连接；
    所述第一输出引线与所述第一晶体管的第二极电连接且与所述扫描线电连接；
    所述第二输出引线与所述第二晶体管的第二极电连接且与所述扫描线电连接；
    所述第一输入引线、所述第二输入引线、所述第一输出引线以及所述第二输出引线均沿所述第二方向延伸。
  10. 根据权利要求2所述的显示面板，其中，所述控制电路位于在所述第二方向上相邻的两个所述子像素之间；
    多条固定电位线沿所述第二方向延伸，沿所述第一方向排列。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板具体包括：
    第一导电层，包括所述扫描线、所述第一晶体管的控制极以及所述第二晶体管的控制极；
    第二导电层，位于所述第一导电层背离所述第一衬底基板的一侧，包括所述扫描信号输入线；
    第三导电层，位于所述第二导电层背离所述第一导电层的一侧，包括所述数据线；
    第四导电层，位于所述第三导电层背离所述第二导电层的一侧，包括所述控制信号线、所述固定电位线、所述第一晶体管的第一极和第二极以及所述第二晶体管的第一极和第二极；所述控制信号线所述固定电位线在所述第一衬底基板的正投影与所述数据线在所述第一衬底基板的正投影的部分区域重叠。
  12. 根据权利要求11所述的显示面板，其中，所述第四导电层还包括：沿所述第二方向延伸的多条第一输出引线和多条第二输出引线；
    所述第一晶体管的第二极通过所述第一输出引线与所述扫描线电连接；
    所述第二晶体管的第二极通过所述第二输出引线与所述扫描线电连接；
    所述第一输出引线和所述第二输出引线在所述第一衬底基板的正投影与所述数据线在所述第一衬底基板的正投影的部分区域重叠。
  13. 根据权利要求11或12所述的显示面板，其中，所述子像素包括驱动晶体管；
    所述第一导电层还包括：与所述扫描线电连接的所述驱动晶体管的控制级；
    所述第二导电层还包括：所述驱动晶体管的第一极；
    所述显示面板还包括：
    第五导电层，位于所述第四导电层背离所述第三导电层的一侧，包括所述驱动晶体管的第二极。
  14. 根据权利要求11～13任一项所述的显示面板，其中，每一所像素岛对应的各所述控制电路在所述第一方向上排列成一行。
  15. 根据权利要求14所述的显示面板，其中，每一所述第一晶体管中，所述第一晶体管的第一极、所述第一晶体管的控制级以及所述第一晶体管的第二极沿所述第一方向排列；
    每一所述第二晶体管中，所述第二晶体管的第一极、所述第二晶体管的控制级以及所述第二晶体管的第二极沿所述第一方向排列。
  16. 根据权利要求15所述的显示面板，其中，所述显示面板还包括：位于所述第一导电层与所述第一衬底基板之间的有源层；所述有源层包括所述第一晶体管的有源层以及所述第二晶体管的有源层；
    所述第一晶体管的有源层包括沿所述第一方向延伸的部分；
    所述第二晶体管的有源层包括沿所述第一方向延伸的部分。
  17. 根据权利要求16所述的显示面板，其中，所述第四导电层还包括：沿所述第二方向延伸的多条第一输出引线和多条第二输出引线；
    所述第一晶体管的第二极通过所述第一输出引线与所述扫描线电连接；
    所述第二晶体管的第二极通过所述第二输出引线与所述扫描线电连接；
    所述第一输出引线和所述第二输出引线在所述第一衬底基板的正投影与 所述数据线在所述第一衬底基板的正投影的部分区域重叠。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板还包括：位于所述第一导电层和所述有源层之间的第一栅绝缘层，位于所述第一导电层和所述第二导电层之间的第二栅绝缘层，位于所述第二导电层和所述第三导电层之间的第一层间绝缘层，位于所述第三导电层和所述第四导电层之间的第二层间绝缘层，以及位于所述第四导电层和所述第五导电层之间的第三层间绝缘层；
    所述第四导电层还包括：多个第一连接垫、多个第二连接垫、多个第三连接垫、多个第四连接垫、以及多个第五连接垫；
    所述驱动晶体管的第二极通过贯穿所述第三层间绝缘层、所述第二层间绝缘层、所述第一层间绝缘层、所述第二栅绝缘层、以及所述第一栅绝缘层的过孔与所述有源层电连接；
    所述第一输入引线与所述第一连接垫电连接，所述第一连接垫通过贯穿所述第二层间绝缘层、以及所述第一层间绝缘层的过孔与所述扫描信号输入线电连接；
    所述第一输出引线与所述第二连接垫电连接，且所述第二连接垫通过贯穿所述第二层间绝缘层、所述第一层间绝缘层、以及所述第二栅绝缘层的过孔与所述扫描线电连接；
    所述第一控制信号线与所述第三连接垫电连接，且所述第三连接垫通过贯穿所述第二层间绝缘层、所述第一层间绝缘层、以及所述第二栅绝缘层的过孔与所述第一晶体管的控制级电连接；
    所述第二控制信号线与所述第四连接垫电连接，且所述第四连接垫通过贯穿所述第二层间绝缘层所述第一层间绝缘层、以及所述第二栅绝缘层的过孔与所述第二晶体管的控制级电连接；
    所述第二输出引线与所述第五连接垫电连接，且所述第五连接垫通过贯穿所述第二层间绝缘层、所述第一层间绝缘层、以及所述第二栅绝缘层的过孔与所述扫描线电连接；
    其中，在所述在驱动晶体管的第二极与所述有源层电连接的区域，所述第一层间绝缘层、所述第二栅绝缘层、以及所述第一栅绝缘层具有第一过孔；在所述第二连接垫与所述扫描线电连接的区域，所述第一层间绝缘层、以及所述第二栅绝缘层具有第二过孔；在所述在驱动晶体管的第二极与所述有源层电连接的区域以及在所述第二连接垫与所述扫描线电连接的区域，所述第二层间绝缘层具有露出所述第一过孔和所述第二过孔的第三过孔。
  19. 根据权利要求14所述的显示面板，其中，所述显示面板还包括：
    像素电极层，位于所述第五导电层背离所述第四导电层一侧，包括与所述子像素一一对应的多个像素电极；所述像素电极与所述驱动晶体管的第二极电连接；
    公共电极层，位于所述像素电极层背离所述第五导电层的一侧；
    多个支撑部，位于所述公共电极层背离所述像素电极层的一侧，所述支撑部在所述第一衬底基板的正投影位于相邻所述子像素行之间，且所述控制电路位于设置有支撑部的所述子像素行之间；
    对向基板，位于所述支撑部背离所述公共电极层的一侧，包括多个沿所述第一方向延伸、沿所述第二方向排列的遮光部；所述遮光部在所述第一衬底基板的正投影覆盖所述支撑部在所述第一衬底基板的正投影以及所述控制电路在所述第一衬底基板的正投影。
  20. 根据权利要求19所述的显示面板，其中，每一所述像素岛包括：第一子像素行、第二子像素行以及第三子像素行；
    所述第一子像素行包括沿所述第一方向排列的多个第一颜色子像素；
    所述第二子像素行包括沿所述第一方向排列的多个第二颜色子像素；
    所述第三子像素行包括沿所述第一方向排列的多个第三颜色子像素；
    所述支撑部在所述衬底基板的正投影位于所述第一子像素行和所述第三子像素行之间。
  21. 根据权利要求20所述的显示面板，其中，所述第一颜色子像素为红色子像素，所述第二颜色子像素为绿色子像素，所述第三颜色子像素为蓝色 子像素。
  22. 根据权利要求1～21任一项所述的显示面板，其中，所述第一晶体管的控制极和所述第二晶体管的控制极与同一条所述控制信号线电连接；
    所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管；或者，所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管。
  23. 根据权利要求1～22任一项所述的显示面板，其中，所述第一晶体管的控制极和所述第二晶体管的控制极与不同的所述控制信号线电连接。
  24. 根据权利要求1～23任一项所述的显示面板，其中，在所述第一方向上排列的一行所述子像素的颜色均相同。
  25. 根据权利要求24所述的显示面板，其中，多个所述像素岛分为多个控制区，每一所述控制区包括至少一个所述像素岛；
    每一所述扫描线包括：在所述第一方向上排列且相互断开的多个子扫描线；每一所述扫描线中，所述子扫描线的数量与在所述第一方向排列的一行所述控制区的数量相同，且每一所述子扫描线对应一个所述控制区的一行所述子像素。
  26. 根据权利要求25所述的显示面板，其中，在每一所述控制区中，在所述第一方向上排列的一行像素岛对应连接n个所述控制电路。
  27. 一种显示装置，其中，包括：
    根据权利要求1～26任一项所述的显示面板；
    柱透镜结构，位于所述显示面板的出光侧；所述柱透镜结构包括阵列排布的多个柱透镜；
    控制器，连接所述显示面板，被配置为向所述显示面板提供驱动信号。
  28. 一种根据权利要求27所述的显示装置的驱动方法，其中，所述方法包括：
    实时确定用户在所述显示装置的注视区域和非注视区域；
    驱动所述注视区域以第一刷新率进行图像显示，并驱动所述非注视区域以第二刷新率进行图像显示；其中，所述第一刷新率高于所述第二刷新率。
  29. 根据权利要求28所述的方法，其中，驱动所述注视区域以第一刷新率进行图像显示，并驱动所述非注视区域以第二刷新率进行图像显示，具体包括：
    驱动所述注视区域内的各子像素进行A次刷新；
    驱动所述非注视区域内的各子像素进行B次刷新；
    其中，A和B为正整数，且A大于B。
  30. 根据权利要求29所述的方法，其中，驱动所述注视区域内的各子像素进行刷新，具体包括：
    驱动所述注视区域对应的各扫描信号输入线依次传输有效电平信号；
    控制各所述控制信号线传输控制信号，将所述扫描信号输入线提供的信号传递至所述注视区域对应的所述扫描线，将所述固定电位线提供的信号传递至所述非注视区域对应的所述扫描线；
    所述驱动所述非注视区域内的各子像素进行刷新，包括：
    驱动所述显示面板内的各扫描信号输入线依次传输有效电平信号；
    当扫描到所述注视区域对应的各子像素行时，控制各所述控制信号线传输控制信号，将所述固定电位线提供的信号传递至所述注视区域对应的所述扫描线，将所述扫描信号输入线提供的信号传递至所述非注视区域对应的所述扫描线。
PCT/CN2021/115138 2021-08-27 2021-08-27 显示面板、显示装置及其驱动方法 WO2023024104A1 (zh)

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