WO2023019659A1 - 一种定位故障晶体管的测试方法、结构 - Google Patents

一种定位故障晶体管的测试方法、结构 Download PDF

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WO2023019659A1
WO2023019659A1 PCT/CN2021/117237 CN2021117237W WO2023019659A1 WO 2023019659 A1 WO2023019659 A1 WO 2023019659A1 CN 2021117237 W CN2021117237 W CN 2021117237W WO 2023019659 A1 WO2023019659 A1 WO 2023019659A1
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transistors
test
faulty device
faulty
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穆克军
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices

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  • the present application relates to but not limited to the technical field of semiconductors, and in particular relates to a testing method and structure for locating faulty transistors.
  • the commonly used method is to use the grinding technology to test each device through the nano probe (nano probe). This method is time-consuming and labor-intensive, and cannot get feedback quickly.
  • WAT wafer acceptance test
  • the purpose of this application is to provide a testing method and structure for locating faulty transistors, which can solve the problem that faulty devices cannot be quickly located in existing transistors that are repeatedly arranged, and significantly reduce the measurement time.
  • the first aspect of the present application provides a test method for locating faulty transistors.
  • the transistors to be tested are divided into Nm groups, and the gates, sources, and substrates of all transistors are connected to a test pad.
  • the drains are respectively connected to Nm test pads to determine the group where the faulty device is located; by analogy, M split tests are performed on the transistor to be tested until it is determined that the number of transistors in the group where the faulty device is located is less than or equal to K.
  • the second aspect of the present application provides a test structure for locating faulty transistors, including multiple sets of transistors to be tested, connecting the gates, sources, and substrates of all transistors to a test pad, and connecting each set of transistors The drains on the battery are connected to a test pad to determine the group where the faulty device is located.
  • the transistors arranged repeatedly are divided into Nm groups, each group contains a certain number of devices, and each group of devices is judged to determine which fault device is located in.
  • the group for the faulty device will continue to be divided into multiple groups, continue to judge each group of devices, conduct M split tests on the transistor to be tested, determine the group where the faulty device is located, and so on, until the faulty device is judged.
  • the number of devices contained in a group is less than or equal to K.
  • FIG. 1 is a schematic diagram of devices repeatedly arranged in the prior related technical solutions
  • Fig. 2 is the flow chart of the forming method of the embodiment of the present application.
  • Fig. 3 is a schematic diagram of the specific division and measurement of the devices repeatedly arranged in the embodiment of the present application;
  • Fig. 4 is a schematic diagram of a metal wire cutting off test pads between the same levels in devices arranged in repeated arrangement according to an embodiment of the present application.
  • This specific embodiment provides a test method for locating faulty transistors, including the following steps:
  • the devices to be tested that are repeatedly arranged are divided into N1 groups according to certain rules, N1 is greater than or equal to 2, and each group contains a certain number of devices.
  • the specific rules include but are not limited to: according to the method of dichotomy and third method, the number of devices between each group is equal, so the division rule can be determined according to the number of devices to be tested set in repeated arrangement, for example, the number of devices to be tested When the number is 12, you can get 2 points, 6 pieces in each group; 3 points, 4 pieces in each group; 4 points, 3 pieces in each group; if the number of devices to be tested is 15, you can get 3 points, 5 pieces in each group ; It can be divided into five points, 3 in each group. There is no limit on how to set the number between multiple groups, and it depends on the number of devices to be tested that are arranged repeatedly.
  • the devices to be tested that are arranged repeatedly can be set as small unit devices, and the small unit devices are arranged repeatedly, and the small unit devices can be composed of the same type or different types of devices.
  • the small unit it is preferred to take the small unit as an example of the composition of the same device, and the small unit device is a transistor.
  • the device to be tested is divided into two groups as an example for illustration.
  • the two groups of devices are compared with each other, and the group with a large electrical deviation is determined as the group where the faulty device is located.
  • determining the group with larger electrical deviation as the group where the faulty device is located specifically includes: connecting the gates, sources, and substrates of all transistors to a test pad, and connecting the two groups of transistors to a test pad.
  • the drains are each connected to a test pad, the operating voltage is applied to the test pad connected to the gate, the test pad connected to the substrate and the source is grounded, and the test pad connected to the drain of each group of devices is applied For the working voltage, by measuring the current between the source and drain test pads and comparing them, find out the group with a large electrical deviation. After finding out the group with a large electrical deviation, do further analysis to accurately locate the faulty device.
  • measure the test pads and determine that the group with larger electrical deviation is the group where the faulty device is located.
  • measure the test pads Specifically include: use Bench test (benchmark test) to measure the test pad voltage connected to the drain of each group of transistors. Compare the electrical properties to find out the group of devices with a large electrical deviation, so as to determine which group of devices the faulty device is located in.
  • the test pad when measuring the conduction current, apply an operating voltage to the test pad connected to the gate and drain, ground the substrate and source, measure the current between the source and drain test pads, and know the average conduction current Ids of the transistor
  • the current value of a group of devices under test is significantly less than the sum of Ids*N0/N1, it can be determined that the faulty device is located in this group of devices under test.
  • the drain test pad when measuring leakage current, apply a working voltage to the drain test pad, ground the gate, substrate, and source, measure the current between the source and drain test pads, and know the average leakage current Ioff of the transistor,
  • the total number of devices under test is N0, if the current value of a group of devices under test is significantly greater than the sum of Ioff*N0/N1, it can be determined that the faulty device is located in this group of devices under test.
  • Nm+1 groups where the faulty devices are located into Nm+1 groups, where Nm+1 is greater than or equal to 2, until the number of devices under test in each group is less than or equal to K .
  • the group device N11 where the faulty device is located continues to be split according to the method of dichotomy, third method, etc., and the number of devices between each group is equal, so the division can be determined according to the number of devices to be tested set in repeated arrangement Rules, for example, when the number of devices to be tested is 12, it can be divided into 2 points, 6 in each group; 3 points, 4 in each group; 4 points, 3 in each group; if the number of devices to be tested is 15, you can Three points, 5 in each group; five points, 3 in each group.
  • accurately locating the faulty device specifically includes: performing nano-probe and PFA analysis on each device in the group of devices to accurately locate the faulty device.
  • step S104 If the number of transistors contained in the group of the faulty device is greater than K, it will enter into step S104 to perform splitting operation again.
  • S104 continue to divide the group where the faulty device is located into Nm groups, continue to measure the Nm group of devices, and determine which group the faulty device is located in, as shown in Figure 2;
  • test pads located on each group of drains at the same level after each division is pre-selected and disconnected.
  • the number of test pads required after M splits of the device to be tested is: 3+N1*N2*...*Nm.
  • test pads of the drain can also be connected together in advance, so that the measurement can be performed from the largest group, reducing the number of test pads used, as follows:
  • the gates and sources of all transistors are respectively connected to a test pad, and the substrate is connected to a test pad.
  • the M-th split will be The group where the faulty device is located is divided into N m groups, and the test pads of the drain of each group can be divided into Nm by the drain pads of the group where the faulty device is located at the time of M-1 splitting, so as to start from the largest group Carry out measurement, and then disconnect step by step after being determined to be divided into N m groups.
  • the step-by-step disconnection is specifically the Nm-1 drain pads of the Nm-1 group, and the conductive wire between each Nm drain pads in the group where the faulty device is located can be disconnected during the M-time split. Nm ⁇ 1*Nm mutually independent drain pads are formed.
  • the conductive wire is a metal material, including AL, W, and CU.
  • test pads on the drains of the two groups of devices after the first split use the Bench test (benchmark test) to measure the electrical properties of the test pads connected to the drains of each group of transistors for comparison, and find out The group of devices with large electrical deviation can be used to determine which group of devices the faulty device is in, and the group of devices where the faulty device is located is recorded as N11.
  • the conduction current when measuring the conduction current, apply the operating voltage to the gate and drain test pads, ground the substrate and source, measure the current between the source and drain test pads, and know the average value of the conduction current Ids of the transistor Next, the total number of devices under test is N0. If the current value of a group of devices under test is significantly smaller than the sum of Ids*N0/N1, it can be determined that the faulty device is located in this group of devices under test.
  • the drain test pad when measuring leakage current, apply a working voltage to the drain test pad, ground the gate, substrate, and source, measure the current between the source and drain test pads, and know the average leakage current Ioff of the transistor,
  • the total number of devices under test is N0, if the current value of a group of devices under test is significantly greater than the sum of Ioff*N0/N1, it can be determined that the faulty device is located in this group of devices under test.
  • the required measurement tests are only 4 times, which are to measure each of the two parts divided into two after the first split, and to measure the number of parts with faults divided into two parts. Then measure each again. At the same time, only seven test pads need to be used, which greatly reduces the measurement time and the number of test pads required for measurement.
  • a test structure for locating faulty transistors including multiple sets of transistors to be tested, connecting the gates and sources of all transistors to a test pad, connecting the substrate to a test pad, connecting the transistors on each group The drain is connected to a test pad to determine the group in which the faulty device is located.
  • the drains on each group of transistors are connected to one test pad, and the drain test pads are connected by conductive wires, wherein the conductive wires are metal materials, including AL, W, and CU.
  • the gate, source, drain, and substrate of the transistor are connected to the test pad, and polysilicon wiring is used for overlapping parts of the wiring.
  • a test method and structure for locating faulty transistors use the split method to split the devices to be tested that are arranged repeatedly into Nm groups, and split again for the group where the faulty device is located, such a After M times of split tests, until it is judged that the number of devices contained in the group where the faulty device is located is less than or equal to K, the drains in each split device are connected to independent test pads, thus On the one hand, it can reduce the number of test pads used; on the other hand, the measurement is performed on the independent test pads connected to each number of devices, which reduces the time required for measurement and improves work efficiency.

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

本申请公开了一种定位故障晶体管的测试方法、结构，其中测试方法包括，将待测试的晶体管分为Nm组，所有晶体管的栅极、源极、衬底各连接到一个测试焊盘，Nm组晶体管的漏极分别连接到Nm个测试焊盘，确定故障器件所在组；以此类推，对待测试晶体管进行M次拆分测试，直到确定故障器件所在组含有晶体管的数量小于等于K个。

Description

一种定位故障晶体管的测试方法、结构
交叉引用
本申请基于申请号为202110937746.5、申请日为2021年8月16日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及但不限于半导体的技术领域，尤其涉及一种定位故障晶体管的测试方法、结构。
背景技术
在半导体芯片的电路布局中，会有大量重复排列晶体管电路设计，如图Fig.1示意图。在整个芯片制造过程中，由于受到各种相关制程的工艺波动，如有源区刻蚀导致的栅极宽度变化、多晶硅栅极刻蚀导致的栅极长度变化、接触栓塞刻蚀导致的接触栓塞大小和深度变化以及热氧化工艺和离子注入工艺的波动等，导致重复器件具有不同的电性，例如阈值电压，导通电流和栅极漏电等。其中，电性偏离比较大的器件会超出芯片电路设计时的可操作范围，影响芯片良率。
为了优化工艺流程提升良率，我们需要在这些重复器件中准确定位故障器件，并做详细的电性量测和物理失效分析(Physical Failure Analysis，PFA)切片来确定是何种工艺带来的影响,从而达到优化工艺、提升良率的目的。
目前常用的方法是利用磨片技术到器件层对每一个器件通过纳米探针(nano probe)进行测试,这种方法耗时耗力，无法快速得到 反馈。
另外一种方法是，在测试设计中，针对每一颗器件做晶圆可接受性测试(wafer acceptance test,WAT)量测。但是这种方法必须给每一个器件至少一个独立的漏极端焊盘(PAD)，栅极、源极和衬底可以分别共用同一个PAD，这样的设计会占据大量的测试空间以及需要大量的量测时间。因此如何快速定位故障器件是提升良率所面临的重大问题。
发明内容
本申请的目的是提供一种定位故障晶体管的测试方法、结构，可以解决现有的重复排列设置的晶体管中无法实现快速定位故障器件的问题，明显减少量测时间。
本申请的第一方面提供了一种定位故障晶体管的测试方法，将待测试的晶体管分为Nm组，所有晶体管的栅极、源极、衬底各连接到一个测试焊盘，Nm组晶体管的漏极分别连接到Nm个测试焊盘，确定故障器件所在组；以此类推，对待测试晶体管进行M次拆分测试，直到确定故障器件所在组含有晶体管的数量小于等于K个。
本申请的第二方面提供了一种定位故障晶体管的测试结构，包括多组设置的待测试晶体管，将所有晶体管的栅极、源极、衬底各连接到一个测试焊盘,将每组晶体管上的漏极共接一个测试焊盘，判断故障器件所在组。
本申请的上述技术方案具有如下有益的技术效果：将重复排列设置的晶体管分为Nm组，每一组内均含有一定数量的器件，对每一组 器件进行判断，判断出故障器件位于哪一组器件内，针对有故障器件的组继续分为多组，继续对每一组器件进行判断，对待测试晶体管进行M次拆分测试，确定故障器件所在组，依次类推，直到判断出故障器件所在组含有器件的数量小于等于K个，通过排查出故障器件位于重复排列设置的晶体管中的位置，依次缩小范围，便可以实现快速定位故障器件，同时针对每组器件做判断，而不是针对单个器件做判断，可以减少检测时间，提高效率。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有相关技术方案中关于重复排列器件的示意图；
图2是本申请实施例的形成方法流程图；
图3是本申请实施例重复排列设置的器件具体的划分和量测示意图；
图4是本申请实施例重复排列设置的器件中切断同级之间测试焊盘的金属丝的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本申请进一步详细说明。应该理解，这些 描述只是示例性的，而并非要限制本申请的范围。
本具体实施方式提供了一种定位故障晶体管的测试方法，包括如下步骤：
S101、将待测试的器件划分为N1组，对N1组器件进行量测，判断故障器件位于哪一组器件内，如图2所示；
具体的为，将重复排列设置的待测试器件按照一定的规则划分为N1组，N1大于等于2,每一组内均包含有一定数量的器件。具体的一定的规则包括但不仅限于：按照二分法、三分法等方式，每组之间的器件数量相等，因此可以按照重复排列设置的待测试器件个数决定划分规则，例如待测试器件个数为12时，可以2分，每组6个；可以三分，每组4个；可以四分，每组三个；如果待测试器件个数为15时，可以三分，每组5个；可以五分，每组3个。具体多组之间的数量如何设置不做限制，视重复排列设置的待测试器件个数决定。
可选的，重复排列设置的待测试器件可设置为小单元器件，将小单元器件重复排列设置，小单元器件可以由同种或不同种器件组成。在本申请文件中优先的以小单元为同种器件组成为例进行说明，且小单元器件为晶体管。
对N1组器件进行量测，判断故障器件位于哪一组器件内，如图2所示；
具体的为，对划分的N1组器件进行一一量测，通过电性比对，判断出故障器件位于哪一组器件内为止，并将故障器件所处的组器件记为N11。
本申请实施例中以将待测试的器件拆分为两组为例进行说明，两组器件互为对照，确定电性偏离较大的组为故障器件所在组。在一个具体的实施例中，确定电性偏离较大的组为故障器件所在组具体包括：将所有晶体管的栅极、源极、衬底各连接到一个测试焊盘，将两组晶体管上的漏极各连接到一个测试焊盘，在栅极连接的测试焊盘上施加工作电压，衬底、源极连接的测试焊盘接地，在每一组器件的漏极连接的测试焊盘上施加工作电压，通过测量源漏测试焊盘之间的电流，进行比对，找出电性偏离较大的组，找出电性偏离较大的组后做进一步分析，准确定位出故障器件。
可选的，对测试焊盘进行量测，确定电性偏离较大的组即为故障器件所在组具体包括：利用Bench test(基准测试)量测每一组晶体管漏极连接的测试焊盘电性进行比对，找出电性偏离较大的组器件，由此判断故障器件位于哪一组器件内。
例如测量导通电流时，在栅极、漏极连接的测试焊盘施加工作电压，衬底、源极接地，测量源、漏测试焊盘之间的电流，已知晶体管的导通电流均值Ids的情况下，待测试器件总数为N0，如果有一组待测器件的电流值明显小于Ids*N0/N1的总和，即可判定故障器件位于这一组待测器件内。
例如测量漏电流时，在漏极测试焊盘施加工作电压，栅极、衬底、源极接地，测量源、漏测试焊盘之间的电流，已知晶体管的漏电流均值Ioff的情况下，待测试器件总数为N0，如果有一组待测器件的电流值明显大于Ioff*N0/N1的总和，即可判定故障器件位于这一组待 测器件内。
S102、判断故障器件所在组含有晶体管的数量是否小于等于K个，如图2所示；
针对重复排列设置的待测试器件较大时，对故障器件所处的组器件继续进行拆分为Nm+1组，其中Nm+1大于等于2，直到每组待测器件的数目小于等于K个。在本申请实施例中以Nm＝2为例进行说明，即每次拆分为两组。
具体的为，将故障器件所处的组器件N11继续按照二分法、三分法等方式进行拆分，每组之间的器件数量相等，因此可以按照重复排列设置的待测试器件个数决定划分规则，例如待测试器件个数为12时，可以2分，每组6个；可以三分，每组4个；可以四分，每组三个；如果待测试器件个数为15时，可以三分，每组5个；可以五分，每组3个。在本申请实施例中以Nm+1＝2为例进行说明，即每次拆分为两组，对两个组器件继续进行量测，直到判断故障器件位于哪一组器件内为止，并将故障器件所处的组数器件记为N21，对故障器件所在组含有晶体管的数量进行判断，判断故障器件所在组含有晶体管的数量是否小于等于K个，其中K为1-4之间。
若故障器件所在组含有晶体管的数量小于K个的话，则进入到下一步步骤S103。
S103、找出电性偏离较大的份数器件后做进一步分析，准确定位出故障器件，如图2所示；
具体的为，准确定位出故障器件具体包括：对所述组器件中的各 个器件做nano-probe和PFA分析，准确定位出故障器件。
若故障器件所在组含有晶体管的数量大于K个的话，则会进入到步骤S104中再次去进行拆分操作。
S104、将故障器件所在组继续分为Nm组，对Nm组器件继续进行量测，判断故障器件位于哪一组内，如图2所示；
具体的为，将故障器件所在组继续按照二分法、三分法等方式进行拆分分为Nm组，再次对Nm组器件继续进行量测，判断出故障器件位于哪一组内后，再重新对故障器件所在组含有晶体管的数量进行判断，判断故障器件所在组含有晶体管的数量是否小于等于K个。如此对待测试晶体管进行M次拆分测试，往复的进行，直到确定故障器件所在组含有器件的数量小于等于K个。
具体的判断故障器件位于哪一组器件内具体操作步骤和S101中的操作步骤一致，在此不再一一赘述。
要说明的是，本实施例中，每次拆分后位于同一级的各组漏极上的测试焊盘是预选断开的之间没有连接关系。则针对此情况下对待测试器件进行M次拆分后所需要的测试焊盘数量为：3+N1*N2*…*Nm个。
在其他实施例中，漏极的多个测试焊盘也可以预先连接在一起，以便可以从最大分组开始进行量测，减少测试焊盘的使用数量，具体如下：
所有晶体管的栅极、源极各连接到一个测试焊盘、衬底连接到一个测试焊盘，对于在第M-1次拆分时处于故障器件所在组下，在第M次拆分时将故障器件所在组分为N m组，每一组的漏极的测试焊盘可以 是由第M-1次拆分时的故障器件所在组的漏极焊盘分成Nm个，以便从最大分组开始进行量测，待确定分N m组后逐级断开。
其中逐级断开具体为Nm-1组的Nm-1个漏极焊盘，在第M次拆分时可以将故障器件所在组的每Nm个漏极焊盘之间的导电线断开，形成Nm-1*Nm个互相独立的漏极焊盘。
可选的，导电线是金属材料，包括AL,W,CU。
如图3、图4所示，为了便于理解，以重复排列设置的器件为十二个为例进行说明：
首先将十二个重复排列设置的晶体管上的栅极、源极、衬底各接一个独立的测试焊盘，如图3中所示，栅极连接PAD1,源极连接PAD2,衬底连接PAD7，随后将十二个重复排列设置的器件按照二等分的规则，将重复排列设置的器件一分为二，每一份内占有六个器件，针对每一份器件再继续平分，由此可以将每次平分在同一小组内的漏极连接一个独立的测试焊盘，各级以及与其上级之间漏极上的测试焊盘预先连接。首先对第一次拆分后的两组器件漏极上的测试焊盘进行量测，利用Bench test(基准测试)量测每一组晶体管漏极连接的测试焊盘电性进行比对，找出电性偏离较大的组器件，由此判断故障器件位于哪一组器件内，并将故障器件所处的组器件记为N11。
例如测量导通电流时，在栅极、漏极测试焊盘施加工作电压，衬底、源极接地，测量源、漏测试焊盘之间的电流，已知晶体管的导通电流均值Ids的情况下，待测试器件总数为N0，如果有一组待测器件的电流值明显小于Ids*N0/N1的总和，即可判定故障器件位于这一 组待测器件内。
例如测量漏电流时，在漏极测试焊盘施加工作电压，栅极、衬底、源极接地，测量源、漏测试焊盘之间的电流，已知晶体管的漏电流均值Ioff的情况下，待测试器件总数为N0，如果有一组待测器件的电流值明显大于Ioff*N0/N1的总和，即可判定故障器件位于这一组待测器件内。
此后，针对判断出故障器件所在的组器件N11继续一分为二，分为两份各自含有三个器件的份数，并切断同级之间测试焊盘的金属丝(参考图4)，继续对测试焊盘进行量测，找出电性偏离较大的一份并将故障器件所处的组器件记为N21，由于每份器件内含有的器件数量为3个，已经小于K个，其中K小于等于4，因此不再进行拆分，在该分法下已经可以针对故障器件所在的组块的所有晶体管进行进一步的nano-probe和PFA分析，准确定位出worse器件。
在该例子中，所需量测的测试仅为4次，分别为第一次拆分后对一分为二的两份器件进行各量测一次，针对有故障的器件份数一分为二后再次各自量测一次。同时需要使用的测试焊盘仅为7个，大大的减少了量测的时间以及量测测试焊盘所需要的数量。
一种定位故障晶体管的测试结构，包括多组设置的待测试晶体管，将所有晶体管的栅极、源极各连接到一个测试焊盘，衬底连接到一个测试焊盘，将每组晶体管上的漏极连接到一个测试焊盘，判断故障器件所在组。
可选的，将每组晶体管上的漏极共接一个测试焊盘，漏极测试焊 盘之间通过导电线连接，其中导电线是金属材料，包括AL,W,CU。
可选的，晶体管的栅极、源极、漏极、衬底连接到测试焊盘，连线重叠的部分采用多晶硅连线。
本具体实施方式提供的一种定位故障晶体管的测试方法、结构，利用拆分法把重复排列设置的待测试器件进行拆分成Nm组，针对有故障的器件所在组再次进行拆分，如此一来经过M次拆分测试，直到判断出故障器件所在组含有器件的数量小于等于K个为止，针对每次拆分后的份数器件内的漏极都共接独立的测试焊盘，由此一来可以减少测试焊盘的使用数量，另一方面针对每份数器件共接的独立测试焊盘进行量测，减少了量测所需的时间，提高了工作效率。
应当理解的是，本申请的上述具体实施方式仅仅用于示例性说明或解释本申请的原理，而不构成对本申请的限制。因此，在不偏离本申请的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。此外，本申请所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (14)

  1. 一种定位故障晶体管的测试方法，包括，
    将待测试的晶体管分为N m组，所有晶体管的栅极、源极、衬底各连接到一个测试焊盘，N m组晶体管的漏极分别连接到N m个测试焊盘，确定故障器件所在组；
    以此类推，对待测试晶体管进行M次拆分测试，直到确定故障器件所在组含有晶体管的数量小于等于K个。
  2. 根据权利要求1所述的方法，其中，
    将待测试的晶体管分为N m组，N m大于等于2。
  3. 根据权利要求1所述的方法，其中，
    对待测试晶体管进行M次拆分测试，M大于等于1。
  4. 根据权利要求2所述的方法，，其中
    N m＝2,基于二分法将待测试的晶体管分为两组，互为对照，确定电性偏离较大的组为故障器件所在组。
  5. 根据权利要求1-4中任意一项所述的方法，其中，所述K的范围是1到4。
  6. 根据权利要求5所述的方法，其中，对待测试器件进行M次拆分后所需要的测试焊盘数量为：3+N1*N2*…*Nm个。
  7. 根据权利要求6所述的方法，其中，对于在第M-1次拆分时处于故障器件所在组下，在第M次拆分时将故障器件所在组分为N m组，每一组的漏极的测试焊盘可以是由第M-1次拆分时的故障器件所在组的漏极焊盘分成Nm个，以便从最大分组开始进行量测，待确定分N m组 后逐级断开。
  8. 根据权利要求7所述的方法，其特征在于，所述逐级断开具体为Nm-1组的Nm-1个漏极焊盘，在第M次拆分时可以将故障器件所在组的每Nm个漏极焊盘之间的导电线断开，形成Nm-1*Nm个互相独立的漏极焊盘。
  9. 根据权利要求8所述的方法，其中，所述导电线是金属材料，包括AL,W,CU。
  10. 根据权利要求1所述的方法，其中，确定故障器件所在组具体包括：
    在栅极测试焊盘上施加工作电压，衬底、源极测试焊盘接地，在每一组器件的漏极测试焊盘上施加工作电压，通过测量源/漏测试焊盘之间的电流，进行比对，
    找出电性偏离较大的组，找出电性偏离较大的组后做进一步分析，准确定位出故障器件。
  11. 根据权利要求10所述的方法，其中，找出电性偏离较大的组后做进一步分析，准确定位出故障器件具体包括：
    对所述组件中的各个器件做nano-probe和PFA分析，准确定位出故障器件。
  12. 一种定位故障晶体管的测试结构，包括多组设置的待测试晶体管，将所有晶体管的栅极、源极、衬底各连接到一个测试焊盘,将每组晶体管上的漏极共接一个测试焊盘，判断故障器件所在组。
  13. 根据权利要求12所述的测试结构，其中，每组晶体管上的漏极共 接一个测试焊盘，漏极测试焊盘之间通过导电线连接，所述导电线是金属材料，包括AL,W,CU。
  14. 根据权利要求12所述的测试结构，其中，所述晶体管的栅极、源极、漏极、衬底连接到测试焊盘，连线重叠的部分采用多晶硅连线。
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