WO2023019574A1 - 移位寄存器、扫描驱动电路及显示装置 - Google Patents

移位寄存器、扫描驱动电路及显示装置 Download PDF

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Publication number
WO2023019574A1
WO2023019574A1 PCT/CN2021/113852 CN2021113852W WO2023019574A1 WO 2023019574 A1 WO2023019574 A1 WO 2023019574A1 CN 2021113852 W CN2021113852 W CN 2021113852W WO 2023019574 A1 WO2023019574 A1 WO 2023019574A1
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Prior art keywords
electrically connected
transistor
node
signal terminal
pull
Prior art date
Application number
PCT/CN2021/113852
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180002232.9A priority Critical patent/CN116114010A/zh
Priority to PCT/CN2021/113852 priority patent/WO2023019574A1/zh
Publication of WO2023019574A1 publication Critical patent/WO2023019574A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, in particular to a shift register, a scan driving circuit and a display device.
  • the scan driving circuit is an important part of the display device.
  • the scan driving circuit may include multiple stages of cascaded shift registers, and each stage of the shift register may be electrically connected to at least one row in the display device.
  • the scan driving circuit can input scan signals row by row to a plurality of wires (such as gate wires or enable signal wires) in the display device, so that the display device can display images.
  • the scanning driving circuit is provided in the display device, which can effectively reduce the cost and improve the yield rate.
  • a shift register is provided.
  • the shift register is applied to a display device, and the display device includes multiple rows of sub-pixels.
  • the shift register is electrically connected to at least one row of sub-pixels.
  • the shift register includes: a first scanning unit and a black insertion circuit.
  • the first scanning unit includes: a first input circuit and a first output circuit.
  • the first input circuit is electrically connected to a display input signal terminal and a first pull-up node; the first input circuit is configured to, in response to a display input signal received at the display input signal terminal, turn the display The input signal is transmitted to the first pull-up node.
  • the first output circuit is electrically connected to the first pull-up node, the first clock signal terminal and the first scan signal terminal; the first output circuit is configured to connect the display to the first input circuit When the input signal is transmitted to the first pull-up node, the first clock signal received at the first clock signal terminal is transmitted to the first pull-up node under the control of the voltage of the first pull-up node.
  • a scanning signal terminal drives the at least one row of sub-pixels for image display.
  • the black insertion circuit is electrically connected to the first control signal end, the black insertion cascade signal end, the second control signal end, the black insertion input signal end, the first pull-up node and the first voltage signal end;
  • the black circuit is configured such that the first control signal transmitted by the first control signal terminal, the black insertion cascade signal transmitted by the black insertion cascade signal terminal, and the second control signal transmitted by the second control signal terminal Under the control of the second control signal, the black insertion input signal received at the black insertion input signal terminal is transmitted to the first pull-up node.
  • the output circuit is further configured to, when the black insertion circuit transmits the black insertion input signal to the first pull-up node, under the control of the voltage of the first pull-up node, set The first clock signal is transmitted to the first scanning signal terminal to drive the at least one row of sub-pixels to display a black screen.
  • the shift register further includes: a second scanning unit.
  • the second scanning unit includes: a second input circuit and a second output circuit.
  • the second input circuit is electrically connected to the display input signal terminal and the second pull-up node; the second input circuit is configured to, in response to the display input signal, transmit the display input signal to the the second pull-up node.
  • the second output circuit is electrically connected to the second pull-up node, the second clock signal terminal and the second scan signal terminal; the second output circuit is configured to connect the display to the second input circuit When the input signal is transmitted to the second pull-up node, the second clock signal received at the second clock signal terminal is transmitted to the first pull-up node under the control of the voltage of the second pull-up node.
  • the second scanning signal end drives the at least one row of sub-pixels to display images.
  • the black insertion circuit is also electrically connected to the second pull-up node; the black insertion circuit is also configured to, while transmitting the black insertion input signal to the first pull-up node, transmit the The black input signal is transmitted to the second pull-up node.
  • the output circuit is further configured to, when the black insertion circuit transmits the black insertion input signal to the second pull-up node, under the control of the voltage of the second pull-up node, set The second clock signal is transmitted to the second scanning signal terminal to drive the at least one row of sub-pixels to display a black screen.
  • the black insertion circuit includes: a black insertion control subcircuit, a black insertion input subcircuit and a first black insertion transmission subcircuit.
  • the black insertion control subcircuit is electrically connected to the first control signal terminal, the black insertion cascade signal terminal, the first voltage signal terminal and the first black insertion node; the black insertion control subcircuit is configured For, under the control of the first control signal, transmit the black insertion cascade signal to the first black insertion node.
  • the black insertion input subcircuit is electrically connected to the first black insertion node, the black insertion input signal terminal and the second black insertion node; the black insertion input subcircuit is configured to Under the control of the voltage of the node, the black insertion input signal is transmitted to the second black insertion node.
  • the first black insertion transmission sub-circuit is electrically connected to the second control signal terminal, the second black insertion node and the first pull-up node; the first black insertion transmission sub-circuit is configured to, Under the control of the second control signal, the black insertion input signal from the second black insertion node is transmitted to the first pull-up node.
  • the black insertion circuit further includes: a second black insertion transmission sub-circuit.
  • the second black insertion transmission sub-circuit is electrically connected to the second control signal terminal, the second black insertion node and the second pull-up node; the second black insertion transmission sub-circuit is configured to, Under the control of the second control signal, the black insertion input signal from the second black insertion node is transmitted to the second pull-up node.
  • the first input circuit includes: a first transistor.
  • the control electrode of the first transistor is electrically connected to the display input signal end, the first electrode of the first transistor is electrically connected to the display input signal end, and the second electrode of the first transistor is electrically connected to the first display input signal end.
  • a pull-up node is electrically connected.
  • the first output circuit includes: a second transistor and a first capacitor. The control electrode of the second transistor is electrically connected to the first pull-up node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the first pull-up node.
  • the first scan signal end is electrically connected.
  • a first end of the first capacitor is electrically connected to the first pull-up node, and a second end of the first capacitor is electrically connected to the first scan signal end.
  • the second input circuit includes: a third transistor.
  • the control electrode of the third transistor is electrically connected to the display input signal end, the first electrode of the third transistor is electrically connected to the display input signal end, and the second electrode of the third transistor is electrically connected to the first display input signal end.
  • the two pull-up nodes are electrically connected.
  • the second output circuit includes: a fourth transistor and a second capacitor.
  • the control electrode of the fourth transistor is electrically connected to the second pull-up node, the first electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the second pull-up node.
  • the second scanning signal terminal is electrically connected.
  • a first end of the second capacitor is electrically connected to the second pull-up node, and a second end of the second capacitor is electrically connected to the second scan signal end.
  • the black insertion control subcircuit includes: a fifth transistor and a third capacitor.
  • the control pole of the fifth transistor is electrically connected to the first control signal terminal, the first pole of the fifth transistor is electrically connected to the black insertion cascade signal terminal, and the second pole of the fifth transistor is electrically connected to the
  • the first plug-in black node is electrically connected.
  • a first end of the third capacitor is electrically connected to the first black insertion node, and a second end of the third capacitor is electrically connected to the first voltage signal end.
  • the black input sub-circuit includes: a sixth transistor.
  • the control pole of the sixth transistor is electrically connected to the first black insertion node, the first pole of the sixth transistor is electrically connected to the black insertion input signal terminal, and the second pole of the sixth transistor is electrically connected to the black insertion terminal.
  • the second plug-in black node is electrically connected.
  • the first black insertion and transmission sub-circuit includes: a seventh transistor.
  • the control pole of the seventh transistor is electrically connected to the second control signal terminal, the first pole of the seventh transistor is electrically connected to the second black node, and the second pole of the seventh transistor is electrically connected to the second black node.
  • the first pull-up node is electrically connected.
  • the second black insertion transmission sub-circuit includes: an eighth transistor.
  • the control pole of the eighth transistor is electrically connected to the second control signal terminal, the first pole of the eighth transistor is electrically connected to the second black node, and the second pole of the eighth transistor is electrically connected to the second black node.
  • the second pull-up node is electrically connected.
  • the first output circuit is also electrically connected to the third clock signal terminal and the first sensing signal terminal.
  • the first output circuit is further configured to, under the control of the voltage of the first pull-up node, when the first input circuit transmits the display input signal to the first pull-up node , transmitting the third clock signal received at the third clock signal terminal to the first sensing signal terminal, driving the at least one row of sub-pixels to reset;
  • the black input signal is transmitted to the first pull-up node, under the control of the voltage of the first pull-up node, the third clock signal is transmitted to the first sensing signal terminal to drive the The at least one row of sub-pixels performs black screen display.
  • the second output circuit is also electrically connected to the fourth clock signal terminal and the second sensing signal terminal.
  • the second output circuit is further configured to, under the control of the voltage of the second pull-up node, in case the second input circuit transmits the display input signal to the second pull-up node , transmitting the fourth clock signal received at the fourth clock signal terminal to the second sensing signal terminal, driving the at least one row of sub-pixels to reset;
  • the black input signal is transmitted to the second pull-up node, under the control of the voltage of the second pull-up node, the fourth clock signal is transmitted to the second sensing signal terminal to drive the The at least one row of sub-pixels performs black screen display.
  • the first output circuit further includes: a ninth transistor and a fourth capacitor.
  • the control electrode of the ninth transistor is electrically connected to the first pull-up node
  • the first electrode of the ninth transistor is electrically connected to the third clock signal terminal
  • the second electrode of the ninth transistor is electrically connected to the The first sensing signal end is electrically connected.
  • a first end of the fourth capacitor is electrically connected to the first pull-up node
  • a second end of the fourth capacitor is electrically connected to the first sensing signal end.
  • the second output circuit further includes: a tenth transistor and a fifth capacitor.
  • the control electrode of the tenth transistor is electrically connected to the second pull-up node, the first electrode of the tenth transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the The second sensing signal end is electrically connected.
  • a first end of the fifth capacitor is electrically connected to the second pull-up node, and a second end of the fifth capacitor is electrically connected to the second sensing signal end.
  • the first output circuit is also electrically connected to the fifth clock signal terminal and the first shift signal terminal.
  • the first output circuit is further configured to transmit a fifth clock signal received at the fifth clock signal terminal to the first shift signal under the control of the voltage of the first pull-up node end.
  • the first output circuit further includes: an eleventh transistor.
  • the control electrode of the eleventh transistor is electrically connected to the first pull-up node, the first electrode of the eleventh transistor is electrically connected to the fifth clock signal terminal, and the second The pole is electrically connected to the first shift signal terminal.
  • the second output circuit is further electrically connected to the sixth clock signal terminal and the second shift signal terminal.
  • the second output circuit is further configured to transmit a sixth clock signal received at the sixth clock signal terminal to the second shift signal under the control of the voltage of the second pull-up node end.
  • the second output circuit further includes: a twelfth transistor.
  • the control electrode of the twelfth transistor is electrically connected to the second pull-up node
  • the first electrode of the twelfth transistor is electrically connected to the sixth clock signal terminal
  • the second The pole is electrically connected to the second shift signal terminal.
  • the first scanning unit further includes: a first reset circuit and a second reset circuit.
  • the first reset circuit is electrically connected to the first reset signal terminal, the first pull-up node, and the first voltage signal terminal; the first reset circuit is configured to be connected to the first reset signal terminal Under the control of the transmitted first reset signal, the first voltage signal received at the first voltage signal terminal is transmitted to the first pull-up node.
  • the second reset circuit is connected to the second reset signal terminal, the first black insertion node, the first pull-up node, and the first voltage The signal terminal is electrically connected; the second reset circuit is configured to, under the control of the voltage of the first plug-in black node and the second reset signal transmitted by the second reset signal terminal, set the first voltage to The signal is transmitted to the first pull-up node.
  • the shift register further includes a second scanning unit
  • the second scanning unit further includes: a third reset circuit and a fourth reset circuit.
  • the third reset circuit is electrically connected to the first reset signal terminal, the second pull-up node, and the first voltage signal terminal; the third reset circuit is configured to, when the first reset signal Under the control of , transmit the first voltage signal to the second pull-up node.
  • the fourth reset circuit is electrically connected to the second reset signal terminal, the first plug-in black node, the second pull-up node, and the first voltage signal terminal; the fourth reset circuit is configured to , under the control of the voltage of the first black insertion node and the second reset signal, transmitting the first voltage signal to the second pull-up node.
  • the first reset circuit includes: a thirteenth transistor.
  • the control electrode of the thirteenth transistor is electrically connected to the first reset signal terminal, the first electrode of the thirteenth transistor is electrically connected to the first pull-up node, and the second The pole is electrically connected to the first voltage signal terminal.
  • the second reset circuit includes: a fourteenth transistor and a fifteenth transistor.
  • the control pole of the fourteenth transistor is electrically connected to the first plug-in black node, the first pole of the fourteenth transistor is electrically connected to the first pull-up node, and the second pole of the fourteenth transistor is electrically connected to the first pull-up node.
  • the pole is electrically connected to the first pole of the fifteenth transistor.
  • the control electrode of the fifteenth transistor is electrically connected to the second reset signal end, and the second electrode of the fifteenth transistor is electrically connected to the first voltage signal end.
  • the third reset circuit includes: a sixteenth transistor. The control electrode of the sixteenth transistor is electrically connected to the first reset signal terminal, the first electrode of the sixteenth transistor is electrically connected to the second pull-up node, and the second pull-up node of the sixteenth transistor The pole is electrically connected to the first voltage signal terminal.
  • the fourth reset circuit includes: a seventeenth transistor and an eighteenth transistor.
  • the control electrode of the seventeenth transistor is electrically connected to the first plug-in black node, the first electrode of the seventeenth transistor is electrically connected to the second pull-up node, and the second pull-up node of the seventeenth transistor
  • the pole is electrically connected to the first pole of the eighteenth transistor.
  • the control electrode of the eighteenth transistor is electrically connected to the second reset signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the first voltage signal terminal.
  • the first scanning unit further includes: a first control circuit electrically connected to the first pull-up node, the first pull-down node, the first voltage signal terminal and the second voltage signal terminal the first control circuit is configured to transmit the second voltage signal to the first pull-down node in response to the second voltage signal received at the second voltage signal terminal, and, at the Under the control of the voltage of the first pull-up node, the first voltage signal received at the first voltage signal terminal is transmitted to the first pull-down node.
  • a first control circuit electrically connected to the first pull-up node, the first pull-down node, the first voltage signal terminal and the second voltage signal terminal the first control circuit is configured to transmit the second voltage signal to the first pull-down node in response to the second voltage signal received at the second voltage signal terminal, and, at the Under the control of the voltage of the first pull-up node, the first voltage signal received at the first voltage signal terminal is transmitted to the first pull-down node.
  • the second scanning unit further includes: a second control circuit, connected to the second pull-up node, the second pull-down node, the first voltage signal terminal and a third voltage signal terminal are electrically connected; the second control circuit is configured to, in response to a third voltage signal received at the third voltage signal terminal, transmit the third voltage signal to the first two pull-down nodes, and, under the control of the voltage of the second pull-up node, transmit the first voltage signal to the second pull-down node.
  • the first control circuit includes: a nineteenth transistor, a twentieth transistor, a twenty-first transistor and a twenty-second transistor.
  • the control pole of the nineteenth transistor is electrically connected to the second voltage signal terminal
  • the first pole of the nineteenth transistor is electrically connected to the second voltage signal terminal
  • the second The electrode is electrically connected to the control electrode of the twentieth transistor and the first electrode of the twenty-first transistor.
  • a first pole of the twentieth transistor is electrically connected to the second voltage signal terminal
  • a second pole of the twentieth transistor is electrically connected to the first pull-down node.
  • the control electrode of the twenty-first transistor is electrically connected to the first pull-up node
  • the second electrode of the twenty-first transistor is electrically connected to the first voltage signal terminal.
  • the control pole of the twenty-second transistor is electrically connected to the first pull-up node, the first pole of the twenty-second transistor is electrically connected to the first pull-down node, and the twenty-second transistor The second pole is electrically connected to the first voltage signal terminal.
  • the second control circuit includes: a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor and a twenty-sixth transistor.
  • the control pole of the twenty-third transistor is electrically connected to the third voltage signal terminal, the first pole of the twenty-third transistor is electrically connected to the third voltage signal terminal, and the twenty-third transistor
  • the second pole of the transistor is electrically connected to the control pole of the twenty-fourth transistor and the first pole of the twenty-fifth transistor.
  • a first pole of the twenty-fourth transistor is electrically connected to the third voltage signal terminal, and a second pole of the twenty-fourth transistor is electrically connected to the second pull-down node.
  • the control electrode of the twenty-fifth transistor is electrically connected to the second pull-up node, and the second electrode of the twenty-fifth transistor is electrically connected to the first voltage signal terminal.
  • the control pole of the twenty-sixth transistor is electrically connected to the second pull-up node, the first pole of the twenty-sixth transistor is electrically connected to the second pull-down node, and the twenty-sixth transistor The second pole is electrically connected to the first voltage signal terminal.
  • the first scanning unit further includes: a fifth reset circuit, a sixth reset circuit and a seventh reset circuit.
  • the fifth reset circuit is electrically connected to the first pull-down node, the first pull-up node, and the first voltage signal terminal; the fifth reset circuit is configured to, in the first pull-down Under the control of the voltage of the node, the first voltage signal is transmitted to the first pull-up node.
  • the sixth reset circuit is electrically connected to the first pull-down node, the first scan signal terminal, and the fourth voltage signal terminal; the sixth reset circuit is configured to, at the first pull-down node Under voltage control, the fourth voltage signal received at the fourth voltage signal terminal is transmitted to the first scan signal terminal.
  • the sixth reset circuit is also electrically connected to the first sensing signal terminal; the sixth The reset circuit is further configured to transmit the fourth voltage signal to the first sensing signal terminal under the control of the voltage of the first pull-down node.
  • the sixth reset circuit is also connected to the first shift signal terminal and the first voltage signal terminal. Terminals are electrically connected; the sixth reset circuit is further configured to, under the control of the voltage of the first pull-down node, transmit the first voltage signal to the first shift signal terminal.
  • the seventh reset circuit is connected to the first black insertion node, the second control signal terminal, the first pull-down node, and the first pull-down node.
  • a voltage signal terminal is electrically connected; the seventh reset circuit is configured to, under the control of the voltage of the first plug-in black node and the second control signal, transmit the first voltage signal to the second Pull down the node once.
  • the second scanning unit further includes: an eighth reset circuit, a ninth reset circuit and a tenth reset circuit.
  • the eighth reset circuit is electrically connected to the second pull-down node, the second pull-up node, and the first voltage signal terminal; the eighth reset circuit is configured to, at the second pull-down node Under the control of the voltage, the first voltage signal is transmitted to the second pull-up node.
  • the ninth reset circuit is electrically connected to the second pull-down node, the second scan signal terminal, and the fourth voltage signal terminal; the ninth reset circuit is configured to, at the second pull-down node Under the control of the voltage, the fourth voltage signal is transmitted to the second scanning signal terminal.
  • the ninth reset circuit is also electrically connected to the second sensing signal end; the ninth reset circuit is also electrically connected to the second sensing signal end; The reset circuit is further configured to transmit the fourth voltage signal to the second sensing signal terminal under the control of the voltage of the second pull-down node.
  • the ninth reset circuit is also connected to the second shift signal terminal and the first voltage signal terminal. Terminals are electrically connected; the ninth reset circuit is further configured to transmit the first voltage signal to the second shift signal terminal under the control of the voltage of the second pull-down node.
  • the tenth reset circuit is electrically connected to the first black insertion node, the second control signal terminal, the second pull-down node, and the first voltage signal terminal; the tenth reset circuit is configured as, Under the control of the voltage of the first black insertion node and the second control signal, the first voltage signal is transmitted to the second pull-down node.
  • the fifth reset circuit includes: a twenty-seventh transistor.
  • the control pole of the twenty-seventh transistor is electrically connected to the first pull-down node
  • the first pole of the twenty-seventh transistor is electrically connected to the first pull-up node
  • the twenty-seventh transistor The second pole is electrically connected to the first voltage signal terminal.
  • the sixth reset circuit includes: a twenty-eighth transistor, a twenty-ninth transistor and a thirtieth transistor.
  • the control electrode of the twenty-eighth transistor is electrically connected to the first pull-down node, the first electrode of the twenty-eighth transistor is electrically connected to the first scan signal terminal, and the twenty-eighth transistor The second pole of the second pole is electrically connected to the fourth voltage signal terminal.
  • the control electrode of the twenty-ninth transistor is electrically connected to the first pull-down node, the first electrode of the twenty-ninth transistor is electrically connected to the first sensing signal terminal, and the twenty-ninth transistor The second pole of the transistor is electrically connected to the fourth voltage signal terminal.
  • the control electrode of the thirtieth transistor is electrically connected to the first pull-down node, the first electrode of the thirtieth transistor is electrically connected to the first shift signal terminal, and the first electrode of the thirtieth transistor is electrically connected to the first shift signal terminal.
  • the two poles are electrically connected to the first voltage signal terminal.
  • the seventh reset circuit includes: a thirty-first transistor and a thirty-second transistor.
  • the control pole of the thirty-first transistor is electrically connected to the first black plug-in node, the first pole of the thirty-first transistor is electrically connected to the first pull-down node, and the thirty-first transistor
  • the second pole of the transistor is electrically connected to the first pole of the thirty-second transistor.
  • the control electrode of the thirty-second transistor is electrically connected to the second control signal terminal, and the second electrode of the thirty-second transistor is electrically connected to the first voltage signal terminal.
  • the eighth reset circuit includes: a thirty-third transistor. The control pole of the thirty-third transistor is electrically connected to the second pull-down node, the first pole of the thirty-third transistor is electrically connected to the second pull-up node, and the thirty-third transistor The second pole is electrically connected to the first voltage signal terminal.
  • the ninth reset circuit includes: a thirty-fourth transistor, a thirty-fifth transistor and a thirty-sixth transistor.
  • the control electrode of the thirty-fourth transistor is electrically connected to the second pull-down node, the first electrode of the thirty-fourth transistor is electrically connected to the second scan signal terminal, and the thirty-fourth transistor The second pole is electrically connected to the fourth voltage signal terminal.
  • the control electrode of the thirty-fifth transistor is electrically connected to the second pull-down node, the first electrode of the thirty-fifth transistor is electrically connected to the second sensing signal terminal, and the thirty-fifth transistor The second pole of the second pole is electrically connected to the fourth voltage signal terminal.
  • the control electrode of the thirty-sixth transistor is electrically connected to the second pull-down node, the first electrode of the thirty-sixth transistor is electrically connected to the second shift signal terminal, and the thirty-sixth transistor
  • the second pole is electrically connected to the first voltage signal terminal.
  • the tenth reset circuit includes: a thirty-seventh transistor and a thirty-eighth transistor.
  • the control pole of the thirty-seventh transistor is electrically connected to the first plug-in black node, the first pole of the thirty-seventh transistor is electrically connected to the second pull-down node, and the thirty-seventh transistor’s
  • the second pole is electrically connected to the first pole of the thirty-eighth transistor.
  • the control electrode of the thirty-eighth transistor is electrically connected to the second control signal terminal, and the second electrode of the thirty-eighth transistor is electrically connected to the first voltage signal terminal.
  • the fifth reset circuit is also electrically connected to the second pull-down node; the fifth reset circuit is further configured to, under the control of the voltage of the second pull-down node, set the The first voltage signal is transmitted to the first pull-up node.
  • the sixth reset circuit is also electrically connected to the second pull-down node; the sixth reset circuit is also configured to, under the control of the voltage of the second pull-down node, transmit the fourth voltage signal to The first scan signal terminal transmits the fourth voltage signal to the first sensing signal terminal, and transmits the first voltage signal to the first shift signal terminal.
  • the eighth reset circuit is also electrically connected to the first pull-down node; the eighth reset circuit is also configured to, under the control of the voltage of the first pull-down node, set the first voltage signal to transmitted to the second pull-up node.
  • the ninth reset circuit is also electrically connected to the first pull-down node; the ninth reset circuit is also configured to, under the control of the voltage of the first pull-down node, set the fourth voltage signal to transmit to the second scan signal terminal, transmit the fourth voltage signal to the second sensing signal terminal, and transmit the first voltage signal to the second shift signal terminal.
  • the fifth reset circuit further includes: a thirty-ninth transistor.
  • the control pole of the thirty-ninth transistor is electrically connected to the second pull-down node
  • the first pole of the thirty-ninth transistor is electrically connected to the first pull-up node
  • the thirty-ninth transistor's The second pole is electrically connected to the first voltage signal terminal.
  • the sixth reset circuit further includes: a fortieth transistor, a forty-first transistor and a forty-second transistor.
  • the control electrode of the fortieth transistor is electrically connected to the second pull-down node, the first electrode of the fortieth transistor is electrically connected to the first scan signal terminal, and the second electrode of the fortieth transistor It is electrically connected with the fourth voltage signal terminal.
  • the control electrode of the forty-first transistor is electrically connected to the second pull-down node, the first electrode of the forty-first transistor is electrically connected to the first sensing signal terminal, and the forty-first transistor
  • the second pole of the second pole is electrically connected to the fourth voltage signal terminal.
  • the control electrode of the forty-second transistor is electrically connected to the second pull-down node, the first electrode of the forty-second transistor is electrically connected to the first shift signal terminal, and the forty-second transistor The second pole is electrically connected to the first voltage signal terminal.
  • the eighth reset circuit further includes: a forty-third transistor. The control electrode of the forty-third transistor is electrically connected to the first pull-down node, the first electrode of the forty-third transistor is electrically connected to the second pull-up node, and the forty-third transistor The second pole is electrically connected to the first voltage signal terminal.
  • the ninth reset circuit further includes: a forty-fourth transistor, a forty-fifth transistor and a forty-sixth transistor.
  • the control electrode of the forty-fourth transistor is electrically connected to the first pull-down node, the first electrode of the forty-fourth transistor is electrically connected to the second scan signal terminal, and the forty-fourth transistor The second pole of the second pole is electrically connected to the fourth voltage signal terminal.
  • the control electrode of the forty-fifth transistor is electrically connected to the first pull-down node, the first electrode of the forty-fifth transistor is electrically connected to the second sensing signal terminal, and the forty-fifth The second pole of the transistor is electrically connected to the fourth voltage signal terminal.
  • the control electrode of the forty-sixth transistor is electrically connected to the first pull-down node
  • the first electrode of the forty-sixth transistor is electrically connected to the second shift signal terminal
  • the forty-sixth transistor is electrically connected to the second shift signal terminal.
  • the second pole of the transistor is electrically connected to the first voltage signal terminal.
  • the shift register further includes: a blanking circuit.
  • the blanking circuit is electrically connected to the third control signal terminal, the display input signal terminal, the seventh clock signal terminal, the first pull-up node and the first voltage signal terminal.
  • the blanking circuit is configured to, under the control of the third control signal transmitted by the third control signal terminal, the display input signal and the seventh clock signal transmitted by the seventh clock signal terminal, The seventh clock signal is transmitted to the first pull-up node.
  • the shift register further includes a second scanning unit
  • the blanking circuit is also electrically connected to the second pull-up node; the blanking circuit is also configured to transfer the seventh clock signal to transmitted to the second pull-up node.
  • the blanking circuit includes: a selection control subcircuit, a blanking input subcircuit, a first blanking transmission subcircuit, and a second blanking transmission subcircuit.
  • the selection control subcircuit is electrically connected to the third control signal terminal, the display input signal terminal, the first blanking node and the first voltage signal terminal; the selection control subcircuit is configured to, at the Under the control of the third control signal, the display input signal is transmitted to the first blanking node.
  • the blanking transmission subcircuit is electrically connected to the first blanking node, the seventh clock signal terminal, and the second blanking node; the blanking transmission subcircuit is configured to, in the first blanking The seventh clock signal is transmitted to the second blanking node under the control of the voltage of the node.
  • the first blanking transmission subcircuit is electrically connected to the seventh clock signal terminal, the second blanking node, and the first pull-up node; the first blanking transmission subcircuit is configured to, Under the control of the seventh clock signal, the seventh clock signal from the second blanking node is transmitted to the first pull-up node.
  • the second blanking transmission subcircuit is electrically connected to the seventh clock signal terminal, the second blanking node, and the second pull-up node; the second blanking transmission subcircuit is configured to, Under the control of the seventh clock signal, the seventh clock signal from the second blanking node is transmitted to the second pull-up node.
  • the selection control subcircuit includes: a forty-seventh transistor and a sixth capacitor.
  • the control pole of the forty-seventh transistor is electrically connected to the third control signal end, the first pole of the forty-seventh transistor is electrically connected to the display input signal end, and the forty-seventh transistor's
  • the second pole is electrically connected to the first blanking node.
  • a first end of the sixth capacitor is electrically connected to the first blanking node, and a second end of the sixth capacitor is electrically connected to the first voltage signal end.
  • the blanking input sub-circuit includes: a forty-eighth transistor.
  • the control electrode of the forty-eighth transistor is electrically connected to the first blanking node, the first electrode of the forty-eighth transistor is electrically connected to the seventh clock signal terminal, and the forty-eighth transistor The second pole of is electrically connected to the second blanking node.
  • the first blanking transmission sub-circuit includes: a forty-ninth transistor.
  • the control electrode of the forty-ninth transistor is electrically connected to the seventh clock signal terminal, the first electrode of the forty-ninth transistor is electrically connected to the second blanking node, and the forty-ninth transistor
  • the second pole of is electrically connected to the first pull-up node.
  • the second blanking transmission sub-circuit includes: a fiftieth transistor.
  • the control electrode of the fiftieth transistor is electrically connected to the seventh clock signal terminal, the first electrode of the fiftieth transistor is electrically connected to the second blanking node, and the second pole is electrically connected to the second pull-up node.
  • the first scanning unit further includes: an eleventh reset circuit, a twelfth reset circuit and a thirteenth reset circuit.
  • the eleventh reset circuit is electrically connected to the global reset signal terminal, the first pull-up node, and the first voltage signal terminal; the eleventh reset circuit is configured to be connected to the global reset signal terminal Under the control of the transmitted global reset signal, the first voltage signal is transmitted to the first pull-up node.
  • the twelfth reset circuit is electrically connected to the display input signal end, the first pull-down node, and the first voltage signal end; the twelfth reset circuit is configured to, when the display input signal Under the control of , transmit the first voltage signal to the first pull-down node.
  • the thirteenth reset circuit is connected to the first blanking node, the seventh clock signal terminal, the first pull-down node, and the first A voltage signal terminal is electrically connected; the thirteenth reset circuit is configured to, under the control of the voltage of the first blanking node and the seventh clock signal, transmit the first voltage signal to the First drop down node.
  • the second scanning unit further includes: a fourteenth reset circuit, a fifteenth reset circuit and a sixteenth reset circuit.
  • the fourteenth reset circuit is electrically connected to the global reset signal terminal, the second pull-up node, and the first voltage signal terminal; the fourteenth reset circuit is configured to, when the global reset signal Under the control of , transmit the first voltage signal to the second pull-up node.
  • the fifteenth reset circuit is electrically connected to the display input signal end, the second pull-down node, and the first voltage signal end; the fifteenth reset circuit is configured to, at the display input signal Under control, the first voltage signal is transmitted to the second pull-down node.
  • the sixteenth reset circuit is electrically connected to the first blanking node, the seventh clock signal terminal, the second pull-down node, and the first voltage signal terminal; the sixteenth reset circuit is configured for transmitting the first voltage signal to the second pull-down node under the control of the voltage of the first blanking node and the seventh clock signal.
  • the eleventh reset circuit includes: a fifty-first transistor.
  • the control electrode of the fifty-first transistor is electrically connected to the global reset signal terminal, the first electrode of the fifty-first transistor is electrically connected to the first pull-up node, and the fifty-first transistor The second pole is electrically connected to the first voltage signal terminal.
  • the twelfth reset circuit includes: a fifty-second transistor. The control electrode of the fifty-second transistor is electrically connected to the display input signal terminal, the first electrode of the fifty-second transistor is electrically connected to the first pull-down node, and the fifty-second transistor The second pole is electrically connected to the first voltage signal terminal.
  • the thirteenth reset circuit includes: a fifty-third transistor and a fifty-fourth transistor.
  • the control electrode of the fifty-third transistor is electrically connected to the first blanking node, the first electrode of the fifty-third transistor is electrically connected to the first pull-down node, and the fifty-third transistor
  • the second pole of the transistor is electrically connected to the first pole of the fifty-fourth transistor.
  • the control electrode of the fifty-fourth transistor is electrically connected to the seventh clock signal terminal, and the second electrode of the fifty-fourth transistor is electrically connected to the first voltage signal terminal.
  • the fourteenth reset circuit includes: a fifty-fifth transistor.
  • the control pole of the fifty-fifth transistor is electrically connected to the global reset signal terminal, the first pole of the fifty-fifth transistor is electrically connected to the second pull-up node, and the fifty-fifth transistor The second pole is electrically connected to the first voltage signal terminal.
  • the fifteenth reset circuit includes: a fifty-sixth transistor. The control electrode of the fifty-sixth transistor is electrically connected to the display input signal terminal, the first electrode of the fifty-sixth transistor is electrically connected to the second pull-down node, and the first electrode of the fifty-sixth transistor The two poles are electrically connected to the first voltage signal terminal.
  • the sixteenth reset circuit includes: a fifty-seventh transistor and a fifty-eighth transistor.
  • the control electrode of the fifty-seventh transistor is electrically connected to the first blanking node, the first electrode of the fifty-seventh transistor is electrically connected to the second pull-down node, and the fifty-seventh transistor
  • the second pole is electrically connected to the first pole of the fifty-eighth transistor.
  • the control electrode of the fifty-eighth transistor is electrically connected to the seventh clock signal terminal, and the second electrode of the fifty-eighth transistor is electrically connected to the first voltage signal end.
  • the shift register further includes: a first leakage prevention circuit.
  • the first anti-leakage circuit is electrically connected to the first blanking node, the fifth voltage signal terminal and the first anti-leakage node; the first anti-leakage circuit is configured to, at the first blanking node Under voltage control, the fifth voltage signal received at the fifth voltage signal terminal is transmitted to the first anti-leakage node.
  • the selection control sub-circuit is also electrically connected to the first anti-leakage node.
  • the first anti-leakage circuit includes: a fifty-ninth transistor.
  • the control electrode of the fifty-ninth transistor is electrically connected to the first blanking node, the first electrode of the fifty-ninth transistor is electrically connected to the fifth voltage signal terminal, and the fifty-ninth transistor
  • the second pole of is electrically connected to the first anti-leakage node.
  • the selection control sub-circuit further includes: a sixtieth transistor.
  • the control pole of the sixtieth transistor is electrically connected to the third control signal terminal, the first pole of the sixtieth transistor is electrically connected to the display input signal terminal, and the second pole of the sixtieth transistor It is electrically connected with the first anti-leakage node.
  • the first pole of the forty-seventh transistor of the selection control sub-circuit is electrically connected to the first anti-leakage node, and is electrically connected to the display input signal terminal through the sixtieth transistor.
  • the shift register further includes: a second anti-leakage circuit.
  • the second anti-leakage circuit is electrically connected to the first pull-up node, the fifth voltage signal terminal, and the second anti-leakage node; the second anti-leakage circuit is configured to, on the first pull-up node Under voltage control, the fifth voltage signal received at the fifth voltage signal terminal is transmitted to the second anti-leakage node.
  • the first input circuit is also electrically connected to the second anti-leakage node.
  • the shift register further includes a second scanning unit
  • the second input circuit is also electrically connected to the second anti-leakage node.
  • the black insertion circuit is also electrically connected to the second anti-leakage node.
  • the first scanning unit further includes a first reset circuit and a second reset circuit
  • the second scanning unit further includes a third reset circuit and a fourth reset circuit
  • the first reset circuit, the second reset circuit The second reset circuit, the third reset circuit and the fourth reset circuit are all electrically connected to the second anti-leakage node.
  • the first scanning unit further includes a fifth reset circuit
  • the second scanning unit further includes an eighth reset circuit
  • the fifth reset circuit and the eighth reset circuit are both connected to the first reset circuit.
  • Two anti-leakage nodes are electrically connected.
  • the shift register further includes a blanking circuit
  • the blanking circuit is also electrically connected to the second anti-leakage node.
  • the eleventh reset circuit and the fourteenth reset circuit also each It is electrically connected with the second anti-leakage node.
  • the second leakage prevention circuit includes: a sixty-first transistor.
  • the control electrode of the sixty-first transistor is electrically connected to the first pull-up node, the first electrode of the sixty-first transistor is electrically connected to the fifth voltage signal terminal, and the sixty-first transistor The second pole of is electrically connected to the second anti-leakage node.
  • the first input circuit further includes: a sixty-second transistor.
  • the control electrode of the sixty-second transistor is electrically connected to the display input signal end, the first electrode of the sixty-second transistor is electrically connected to the display input signal end, and the first electrode of the sixty-second transistor The two poles are electrically connected to the second anti-leakage node.
  • the first electrode of the first transistor is electrically connected to the second anti-leakage node, and is electrically connected to the display input signal terminal through the sixty-second transistor.
  • the first pole of the third transistor in the second input circuit is electrically connected to the second anti-leakage node, and is electrically connected to the display input signal terminal through the sixty-second transistor.
  • the black insertion circuit includes a first black insertion transmission sub-circuit
  • the first black insertion transmission sub-circuit further includes: a sixty-third transistor.
  • the control electrode of the sixty-third transistor is electrically connected to the second control signal terminal
  • the first electrode of the sixty-third transistor is electrically connected to the second plug-in black node
  • the sixty-third transistor The second pole of is electrically connected to the second anti-leakage node.
  • the first pole of the seventh transistor in the first black insertion transmission sub-circuit is electrically connected to the second anti-leakage node, and is electrically connected to the second black insertion node through the sixty-third transistor.
  • the first pole of the eighth transistor in the second black insertion transmission sub-circuit is electrically connected to the second anti-leakage node, and is electrically connected to the second black insertion node through the sixty-third transistor.
  • the first reset circuit further includes: a sixty-fourth transistor.
  • the control electrode of the sixty-fourth transistor is electrically connected to the first reset signal terminal, the first electrode of the sixty-fourth transistor is electrically connected to the second anti-leakage node, and the sixty-fourth transistor
  • the second pole is electrically connected to the first voltage signal terminal.
  • the second pole of the thirteenth transistor in the first reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-fourth transistor.
  • the second pole of the sixteenth transistor in the third reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-fourth transistor.
  • the second reset circuit further includes: a sixty-fifth transistor.
  • the control electrode of the sixty-fifth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixty-fifth transistor is electrically connected to the second anti-leakage node, and the sixty-fifth transistor
  • the second pole is electrically connected to the first voltage signal terminal.
  • the second pole of the fifteenth transistor in the second reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-fifth transistor.
  • the second pole of the eighteenth transistor in the fourth reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-fifth transistor.
  • the fifth reset circuit further includes: a sixty-sixth transistor.
  • the control electrode of the sixty-sixth transistor is electrically connected to the first pull-down node, the first electrode of the sixty-sixth transistor is electrically connected to the second anti-leakage node, and the sixty-sixth transistor
  • the second pole is electrically connected to the first voltage signal terminal.
  • the second pole of the twenty-seventh transistor in the fifth reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-sixth transistor.
  • the second pole of the thirty-third transistor in the eighth reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-sixth transistor.
  • the fifth reset circuit further includes: a sixty-seventh transistor.
  • the control electrode of the sixty-seventh transistor is electrically connected to the second pull-down node
  • the first electrode of the sixty-seventh transistor is electrically connected to the second anti-leakage node
  • the sixty-seventh transistor's The second pole is electrically connected to the first voltage signal terminal.
  • the second pole of the thirty-ninth transistor in the fifth reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-seventh transistor.
  • the second pole of the forty-third transistor in the eighth reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-seventh transistor.
  • the eleventh reset circuit further includes: a sixty-eighth transistor.
  • the control pole of the sixty-eighth transistor is electrically connected to the global reset signal terminal
  • the first pole of the sixty-eighth transistor is electrically connected to the second anti-leakage node
  • the sixty-eighth transistor's The second pole is electrically connected to the first voltage signal terminal.
  • the second pole of the fifty-first transistor in the eleventh reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-eighth transistor.
  • the second pole of the fifty-fifth transistor in the fourteenth reset circuit is electrically connected to the second anti-leakage node, and is electrically connected to the first voltage signal terminal through the sixty-eighth transistor.
  • the first blanking transmission subcircuit further includes: a sixty-ninth transistor.
  • the control electrode of the sixty-ninth transistor is electrically connected to the seventh clock signal terminal, the first electrode of the sixty-ninth transistor is electrically connected to the second blanking node, and the sixty-ninth transistor
  • the second pole of is electrically connected to the second anti-leakage node.
  • the first electrode of the forty-ninth transistor in the first blanking transmission sub-circuit is electrically connected to the second anti-leakage node, and is electrically connected to the second blanking node through the sixty-ninth transistor .
  • the first pole of the fiftieth transistor in the second blanking transmission sub-circuit is electrically connected to the second anti-leakage node, and is electrically connected to the second blanking node through the sixty-ninth transistor.
  • the shift register further includes: a third anti-leakage circuit.
  • the third anti-leakage circuit is electrically connected to the first black insertion node, the fifth voltage signal terminal, and the third anti-leakage node; the third anti-leakage circuit is configured to, at the first black insertion node Under voltage control, the fifth voltage signal received at the fifth voltage signal terminal is transmitted to the third anti-leakage node.
  • the black insertion control sub-circuit is also electrically connected to the third anti-leakage node.
  • the third anti-leakage circuit includes: a seventieth transistor.
  • the control electrode of the seventieth transistor is electrically connected to the first black node
  • the first electrode of the seventieth transistor is electrically connected to the fifth voltage signal terminal
  • the second electrode of the seventieth transistor is electrically connected to the fifth voltage signal terminal.
  • the pole is electrically connected to the third anti-leakage node.
  • the black insertion control sub-circuit further includes: a seventy-first transistor.
  • the control electrode of the seventy-first transistor is electrically connected to the first control signal terminal, the first electrode of the seventy-first transistor is electrically connected to the black insertion cascade signal terminal, and the seventy-first
  • the second pole of the transistor is electrically connected to the third anti-leakage node.
  • the first pole of the fifth transistor in the black insertion control sub-circuit is electrically connected to the third anti-leakage node, and is electrically connected to the black insertion cascade signal terminal through the seventy-first transistor.
  • a scan driving circuit in another aspect, includes: a multi-stage cascaded shift register as described in any one of the above embodiments.
  • the multi-stage shift register includes a plurality of first shift register groups and a plurality of second shift register groups; the first shift register groups and the second shift register groups are arranged alternately.
  • the shift register includes a first scanning unit and a second scanning unit
  • the first shift register group includes a 2N-stage shift register
  • the second shift register group includes a 2N-stage shift register; where N is positive integer.
  • the scanning driving circuit further includes: a first control signal line group, including a first sub-control signal line and a second sub-control signal line; The first control signal end of the bit register is electrically connected, and the second sub-control signal line is electrically connected to the first control signal end of each shift register in the second shift register group; and, the first clock signal line group , including 8N first sub-clock signal lines; the 8N first sub-clock signal lines are respectively connected to the first clock signal end and the second clock signal end of each shift register in the first shift register group, the The first clock signal terminal and the second clock signal terminal of each shift register in the second shift register group are electrically connected.
  • the scan driving circuit further includes: a second clock signal line group.
  • the second clock signal line group includes 4N second sub-clock signal lines; the 4N second sub-clock signal lines are respectively connected to the third clock signal terminals of the shift registers in the first shift register group and the fourth clock signal end, and are respectively electrically connected to the third clock signal end and the fourth clock signal end of each shift register in the second shift register group.
  • the second clock signal line group includes 8N second sub-clock signal lines; the 8N second sub-clock signal lines are connected with the third clock of each shift register in the first shift register group respectively.
  • the signal terminal and the fourth clock signal terminal are electrically connected to the third clock signal terminal and the fourth clock signal terminal of each shift register in the second shift register group.
  • the scan driving circuit further includes: a third clock signal line group.
  • the third clock signal line group includes 4N third sub-clock signal lines; the 4N third sub-clock signal lines are respectively connected to the fifth clock signal terminals of each shift register in the first shift register group and the sixth clock signal terminal, and are respectively electrically connected to the fifth clock signal terminal and the sixth clock signal terminal of each shift register in the second shift register group; or, the 4N third sub-clocks
  • the 2N third sub-clock signal lines in the signal lines are respectively electrically connected to the fifth clock signal terminals of the shift registers in the first shift register group, and the other 2N third sub-clock signal lines are respectively connected to the fifth clock signal terminals of the first shift register group.
  • the fifth clock signal end of each shift register in the two shift register groups is electrically connected; or, the third clock signal line group includes 8N third sub-clock signal lines; the 8N third sub-clock signal lines Respectively with the fifth clock signal end and the sixth clock signal end of each shift register in the first shift register group, the fifth clock signal end and the sixth clock signal end of each shift register in the second shift register group
  • the clock signal terminal is electrically connected.
  • the scan driving circuit further includes: a second control signal line group.
  • the second control signal line group includes: a third sub-control signal line and a fourth sub-control signal line.
  • the third sub-control signal line is electrically connected to the second control signal end of each shift register in the first shift register group; the fourth sub-control signal line is electrically connected to the second control signal end of each shift register in the second shift register group.
  • the second control signal end of the shift register is electrically connected.
  • the third sub-control signal line is also electrically connected to the black input signal terminal of each shift register in the first shift register group.
  • the fourth sub-control signal line is also electrically connected to the black input signal terminal of each shift register in the second shift register group.
  • the display input signal terminals of the other stages of shift registers are connected to the first shift signal in the previous shift registers. Terminals are electrically connected; except for at least the first two stages of shift registers, the black-inserted cascaded signal terminals of the other stages of shift registers are electrically connected to the second shift signal terminals of the previous shift registers; or, in said In the case where the shift register also includes a second anti-leakage circuit, except for at least the first two stages of shift registers, the black plug-in cascade signal terminals of the other stages of shift registers are connected to the second anti-leakage node of the previous shift register. electrical connection.
  • the display input signal terminals of the other stages of shift registers are connected to the second shift signal in the previous shift registers Terminals are electrically connected; except for at least the first two stages of shift registers, the plug-and-black cascade signal terminals of the other stages of shift registers are electrically connected to the first shift signal terminals of the preceding shift registers.
  • At least two stages of shift registers share a black insertion circuit.
  • at least two stages of shift registers share a black insertion circuit.
  • a display device in yet another aspect, includes: multiple rows of sub-pixels; and the scanning driving circuit as described in any one of the above-mentioned embodiments.
  • the one-stage shift register in the scanning driving circuit is electrically connected to at least one row of sub-pixels.
  • FIG. 1 is a structural diagram of a display device according to some embodiments of the present disclosure
  • Fig. 2 is a structural diagram of another display device according to some embodiments of the present disclosure.
  • Fig. 3 is a structural diagram of another display device according to some embodiments of the present disclosure.
  • FIG. 4 is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure.
  • FIG. 5 is a timing diagram corresponding to the sub-pixel shown in FIG. 4 according to the related art
  • FIG. 6 is a timing diagram corresponding to the sub-pixel shown in FIG. 4 according to some embodiments of the present disclosure
  • FIG. 7 is another timing diagram corresponding to the sub-pixel shown in FIG. 4 according to some embodiments of the present disclosure.
  • Fig. 8 is a structural diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 9 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 10 is a circuit diagram of a shift register according to some embodiments of the present disclosure.
  • Fig. 11 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 12 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 13 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 14 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 15 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 16 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 17 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 18 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 19 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 20 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 21 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 22 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 23 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 24 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 25 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 26 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 27 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 28 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 29 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 30 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 31 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 32 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 33 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 34 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 35 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 36 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 37 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 38 is a structural diagram of a scan driving circuit according to some embodiments of the present disclosure.
  • FIG. 39 is a structural diagram of another scan driving circuit according to some embodiments of the present disclosure.
  • FIG. 40 is a structural diagram of another scan driving circuit according to some embodiments of the present disclosure.
  • Fig. 41 is a structural diagram of another scan driving circuit according to some embodiments of the present disclosure.
  • Fig. 42 is a structural diagram of another scan driving circuit according to some embodiments of the present disclosure.
  • Fig. 43 is a circuit diagram of a black insertion circuit in a first shift register group or a second shift register group according to some embodiments of the present disclosure
  • Fig. 44 is a circuit diagram of another black insertion circuit in the first shift register group or the second shift register group according to some embodiments of the present disclosure.
  • FIG. 45 is a structural diagram of another scan driving circuit according to some embodiments of the present disclosure.
  • Fig. 46 is a timing control diagram corresponding to the scanning driving circuit shown in Fig. 38 according to some embodiments of the present disclosure
  • FIG. 47 is another timing control diagram corresponding to the scan driving circuit shown in FIG. 38 according to some embodiments of the present disclosure.
  • Fig. 48 is a structural diagram of another scan driving circuit according to some embodiments of the present disclosure.
  • FIG. 49 is a timing control diagram corresponding to the scan driving circuit shown in FIG. 39 according to some embodiments of the present disclosure.
  • FIG. 50 is a structural diagram of another scan driving circuit according to some embodiments of the present disclosure.
  • FIG. 51 is a timing control diagram corresponding to the scan driving circuit shown in FIG. 40 according to some embodiments of the present disclosure.
  • FIG. 52 is a structural diagram of another scan driving circuit according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • connection When describing some embodiments, the expression “connected” and its derivatives may be used. For example, the term “connected” may be used in describing some embodiments to indicate that two or more elements are in physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited by the context herein.
  • electrical connection may be expressed as a direct electrical connection or as an indirect electrical connection.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that " or “if [the stated condition or event] is detected” are optionally construed to mean “when determining ! or “in response to determining ! depending on the context Or “upon detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the transistors used in the circuits provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors (such as oxide thin film transistors) or other switching devices with the same characteristics.
  • thin film transistors are used as examples for illustration. .
  • the control pole of each transistor used in the shift register is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor.
  • the source and the drain of the transistor may be symmetrical in structure, there may be no structural difference between the source and the drain, that is to say, the first and second electrodes of the transistor in the embodiments of the present disclosure
  • the two poles may be structurally indistinguishable.
  • the transistor is a P-type transistor
  • the first pole of the transistor is the source
  • the second pole is the drain
  • the second pole is the source.
  • nodes such as pull-up nodes and pull-down nodes do not represent actual components, but represent confluence points of related electrical connections in the circuit diagram. Nodes are equivalent to connected junctions.
  • the term "pull-up” refers to charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode rises, thereby realizing the operation of the corresponding transistor (eg conduction).
  • the term “pull-down” means to discharge a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is lowered, thereby realizing the operation (eg, turning off) of the corresponding transistor.
  • the transistors are all N-type transistors as an example for description.
  • Some embodiments of the present disclosure provide a shift register 100 , a scan driving circuit 1000 and a display device 2000 .
  • the shift register 100 , the scan driving circuit 1000 and the display device 2000 will be introduced respectively below.
  • the display device 2000 may be any device that displays images, whether moving (for example, video) or fixed (for example, still images), and whether text or text. More specifically, it is contemplated that the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or Laptop Computers, GPS Receivers/Navigators, Cameras, MP4 Video Players, Camcorders, Game Consoles, Watches, Clocks, Calculators, Television Monitors, Flat Panel Displays, Computer Monitors, Automotive Displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, displays for camera views (e.g., displays for rear-view cameras in vehicles), electronic photographs, electronic billboards or signage, projectors, building structures, packaging and aesthetic structures (for example, for a display of an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Cameras GPS Receivers/Navigators
  • Cameras Motion
  • the display device 2000 may include a frame, a display panel disposed in the frame, a circuit board, a display driver IC (Integrated Circuit, integrated circuit), and other electronic accessories.
  • a display driver IC Integrated Circuit, integrated circuit
  • the above-mentioned display panel may be: an organic light emitting diode (Organic Light Emitting Diode, referred to as OLED) display panel, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, referred to as QLED) display panel, a micro light emitting diode (Micro Light Emitting Diodes , Micro LED for short) display panels, etc., which are not specifically limited in this disclosure.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED for short Micro Light Emitting Diodes
  • Some embodiments of the present disclosure will be schematically described below by taking the aforementioned display panel as an OLED display panel (that is, the display device 2000 is an OLED display device) as an example.
  • the above-mentioned display device 2000 has a display area A and a frame area B disposed beside the display area A.
  • side refers to one side, two sides, three sides or surrounding sides of the display area A, that is, the border area B can be located on one side, two sides or three sides of the display area A, or the border Area B may be arranged around display area A.
  • the above-mentioned display device 2000 may include: a substrate 200 , a plurality of sub-pixels P, and a scan driving circuit 1000 .
  • the substrate 200 is used to carry the plurality of sub-pixels and the scan driving circuit 1000 .
  • the scan driving circuit 1000 may be located in the frame area B. As shown in FIG. Certainly, the scan driving circuit 1000 may also be disposed at other positions, which is not limited in the present disclosure.
  • the scan driving circuit 1000 may be, for example, a light emission control circuit, or may be a gate driving circuit. Wherein, the present disclosure takes the scan driving circuit 1000 as a gate driving circuit as an example for schematic illustration.
  • the substrate 200 may be a rigid substrate.
  • the rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl methacrylate, polymethyl methacrylate) substrate or the like.
  • the substrate 200 may be a flexible substrate.
  • the flexible substrate can be, for example, a PET (Polyethylene terephthalate, polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate or a PI (Polyimide , polyimide) substrates, etc.
  • the display device 2000 may be a flexible display panel.
  • the above-mentioned plurality of sub-pixels P may be located in the display area A.
  • the plurality of sub-pixels P may be arranged in multiple rows along the first direction X, and arranged in multiple columns along the second direction Y.
  • each row of sub-pixels P may include a plurality of sub-pixels P
  • each column of sub-pixels P may include a plurality of sub-pixels P.
  • first direction X and the second direction Y cross each other.
  • the included angle between the first direction X and the second direction Y can be selected and set according to actual needs.
  • the included angle between the first direction X and the second direction Y may be 85°, 89° or 90° and so on.
  • the display device 2000 may further include: a plurality of gate lines GL and a plurality of data lines DL disposed on one side of the substrate 200 and located in the display area A.
  • the plurality of gate lines GL extend along the first direction X
  • the plurality of data lines DL extend along the second direction Y.
  • the sub-pixels P arranged in a row along the first direction X may be referred to as sub-pixels P in the same row, and the sub-pixels P arranged in a column along the second direction Y may be referred to as sub-pixels P in the same column.
  • the sub-pixels P in the same row may be electrically connected to at least one gate line GL, and the sub-pixels P in the same column may be electrically connected to one data line DL.
  • each sub-pixel P may include a pixel driving circuit P1 and a light emitting device P2 electrically connected to the pixel driving circuit P1 .
  • the light emitting device may be an OLED.
  • one gate line GL may be electrically connected to multiple pixel driving circuits P1 in the same row of sub-pixels P
  • one data line DL may be electrically connected to multiple pixel driving circuits P2 in the same column of sub-pixels P.
  • the structure of the pixel driving circuit P1 may include structures such as "3T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C”.
  • T represents a transistor
  • the number before “T” represents the number of transistors
  • C represents a storage capacitor
  • the number before “C” represents the number of storage capacitors.
  • the stability of the transistor in the pixel driving circuit P1 and the light emitting device P2 may decrease (for example, the threshold voltage drift of the driving transistor), which affects the display effect of the display device 2000, so that it is necessary to The sub-pixel P is compensated.
  • a pixel compensation circuit may be provided in the sub-pixel P, so that the sub-pixel P may be internally compensated by the pixel compensation circuit.
  • the transistor inside the sub-pixel P can sense the driving transistor or the light emitting device, and transmit the sensed data to an external sensing circuit, so that the external sensing circuit can be used to calculate the driving voltage value to be compensated and provide feedback , so as to realize the external compensation of the sub-pixel P.
  • the structure and working process of the sub-pixel P are schematically described by taking the external compensation method (sensing the driving transistor) and the pixel driving circuit adopting a “3T1C” structure as an example.
  • the pixel driving circuit P1 may include: a switching transistor T1 , a driving transistor T2 , a sensing transistor T3 and a storage capacitor Cst.
  • the control electrode of the switching transistor T1 is electrically connected to the first gate signal terminal G1
  • the first electrode of the switching transistor T1 is electrically connected to the data signal terminal Data
  • the second electrode of the switching transistor T1 is electrically connected to the first gate signal terminal G1.
  • Node G is electrically connected.
  • the switch transistor T1 is configured to transmit the data signal received at the data signal terminal Data to the first node G in response to the first scan signal received at the first gate signal terminal G1 .
  • the data signal includes, for example, a detection data signal and a display data signal.
  • the detection data signal is used in the blanking period
  • the display data signal is used in the display period.
  • the display period and the blanking period reference may be made to the descriptions in some embodiments below, and details are not repeated here.
  • the control electrode of the driving transistor T2 is electrically connected to the first node G
  • the first electrode of the driving transistor T2 is electrically connected to the sixth voltage signal terminal ELVDD
  • the second electrode of the driving transistor T2 is electrically connected to the second node G. S electrical connection.
  • the driving transistor T2 is configured to be turned on under the control of the voltage of the first node G, and generate a driving signal according to the voltage of the first node G and the sixth voltage signal received at the sixth voltage signal terminal ELVDD , and transmit the driving signal to the second node S.
  • a first end of the storage capacitor Cst is electrically connected to the first node G, and a second end of the storage capacitor Cst is electrically connected to the second node S.
  • the switching transistor T1 charges the storage capacitor Cst at the same time.
  • the anode of the light emitting device P2 is electrically connected to the second node S, and the cathode of the light emitting device P2 is electrically connected to the seventh voltage signal terminal ELVSS.
  • the light emitting device P2 is configured to emit light under the drive of the driving signal.
  • the control electrode of the sensing transistor T3 is electrically connected to the second gate signal terminal G2
  • the first electrode of the sensing transistor T3 is electrically connected to the second node S
  • the second electrode of the sensing transistor T3 It is electrically connected with the sensing signal terminal Sense.
  • the sensing transistor T3 is configured to, in response to the second scan signal received at the second gate signal terminal G2 , detect the electrical characteristics of the driving transistor T2 to achieve external compensation.
  • the electrical characteristics include, for example, the threshold voltage and/or carrier mobility of the drive transistor T2.
  • the sensing signal terminal Sense can provide a reset signal or acquire a sensing signal, wherein the reset signal is used to reset the second node S during the display period, and the acquired sensing signal is used to acquire the voltage of the driving transistor T2 during the blanking period.
  • the reset signal is used to reset the second node S during the display period
  • the acquired sensing signal is used to acquire the voltage of the driving transistor T2 during the blanking period.
  • threshold voltage and/or carrier mobility can be used to acquire the voltage of the driving transistor T2 during the blanking period.
  • multiple pixel driving circuits P1 in the same row of sub-pixels P may be electrically connected to two gate lines GL (namely the first gate line and the second gate line).
  • each first gate signal terminal G1 can be electrically connected to the first gate line and receive the first scanning signal transmitted by the first gate line;
  • each second gate signal terminal G2 can be electrically connected to the second gate line and receive The second scanning signal transmitted by the second gate line.
  • the display period of one frame may include, for example, a display period and a blanking period in sequence.
  • the working process of the sub-pixel P may include, for example: a reset period t1 , a data writing period t2 and a light emitting period t3 .
  • the level of the first scanning signal is high level
  • the level of the data signal terminal is, for example, low level
  • the level of the second scanning signal is high level
  • the sensing signal terminal Sense provides the reset signal. level is low.
  • the switch transistor T1 is turned on under the control of the first scan signal, receives a data signal, and transmits the data signal to the first node G, and resets the first node G.
  • the sensing transistor T3 is turned on under the control of the second scan signal, receives a reset signal, and transmits the reset signal to the second node S, and resets the second node S.
  • the level of the first scan signal is high level, and the level of the data signal (that is, the display data signal) is high level.
  • the switch transistor T1 is kept in a conductive state under the control of the first scan signal, receives the display data signal, and transmits the display data signal to the first node G, and charges the storage capacitor Cst at the same time.
  • the level of the first scanning signal is low level
  • the level of the second scanning signal is low level
  • the level of the sixth voltage signal is high level.
  • the switch transistor T1 is turned off under the control of the first scan signal
  • the sensing transistor T3 is turned off under the control of the second scan signal.
  • the storage capacitor Cst starts discharging so that the voltage of the first node G remains at a high level.
  • the driving transistor T2 is turned on under the control of the voltage of the first node G, receives the sixth voltage signal, generates a driving signal, transmits the driving signal to the second node S, and drives the light emitting device P2 to emit light.
  • the working process of the sub-pixel P may include, for example: a first stage and a second stage.
  • the levels of the first scanning signal and the second scanning signal are both high level, and the level of the data signal (that is, the detection data signal) is high level.
  • the switch transistor T1 is turned on under the control of the first scanning signal, receives the detection data signal, and transmits the detection data signal to the first node G, to charge the first node G.
  • the sensing transistor T3 is turned on under the control of the second scan signal, receives a reset signal provided by the sensing signal terminal Sense, and transmits the reset signal to the second node S.
  • the sensing signal terminal Sense is in a suspended state.
  • the driving transistor T2 is turned on under the control of the voltage of the first node G, receives the sixth voltage signal, and transmits the sixth voltage signal to the second node S to charge the second node S, so that the second node S The voltage rises until the drive transistor T2 is turned off. At this time, the voltage difference Vgs between the first node G and the second node S is equal to the threshold voltage Vth of the driving transistor T2.
  • the sensing transistor T3 Since the sensing transistor T3 is in the conducting state and the sensing signal terminal Sense is in the floating state, when the driving transistor T2 charges the second node S, the sensing signal terminal Sense is also charged at the same time.
  • the threshold voltage Vth of the driving transistor T2 can be calculated according to the relationship between the voltage of the sensing signal terminal Sense and the level of the detection data signal .
  • the threshold voltage Vth of the driving transistor T2 After the threshold voltage Vth of the driving transistor T2 is calculated, the threshold voltage Vth can be compensated into the display data signal of the display period in the display period of the next frame to complete the external compensation of the sub-pixel P.
  • the scan driving circuit 1000 and the plurality of sub-pixels P are located on the same side of the substrate 200 .
  • the scan driving circuit 1000 may include a multi-stage cascaded shift register 100 .
  • the one-stage shift register 100 may be electrically connected to at least one row of sub-pixels P (that is, multiple pixel driving circuits P1 in the sub-pixel P).
  • each shift register 100 in the scan driving circuit 1000 can be electrically connected to the first gate signal terminal G1 through the first gate line, and the first scan is transmitted to the first gate signal terminal G1 through the first gate line.
  • the second gate signal is electrically connected to the second gate signal terminal G2 through the second gate line, and the second scan signal is transmitted to the second scan signal terminal G2 through the second gate line.
  • multiple pixel driving circuits P1 in the same row of sub-pixels P may also be electrically connected to the same gate line GL.
  • the above-mentioned first scan signal and the second scan signal are the same.
  • Each shift register 1 in the scanning driving circuit 1000 can be electrically connected to the first gate signal terminal G1 and the second gate signal terminal G2 through the corresponding gate line GL, and can send signals to the first gate signal terminal through the gate line GL.
  • the terminal G1 and the second gate signal terminal G2 transmit scan signals.
  • image smear phenomenon will occur during the dynamic picture switching process, that is, when the display device 2000 switches from one frame of picture to another frame of picture, the viewer will feel The image smear to the previous frame (also known as dynamic image smear), which will affect the image display effect.
  • the scan driving circuit 1000 includes a multi-stage cascaded shift register 100 .
  • the shift register 100 is applied in the above-mentioned display device 2000 , and each stage of the shift register 100 is electrically connected to at least one row of sub-pixels P.
  • the number of rows of sub-pixels P electrically connected to each shift register 100 may be determined according to the structure of the shift register 100 .
  • the shift register 100 includes: a first scanning unit 1 and a black insertion circuit 2 .
  • the first scanning unit 1 includes a first input circuit 11 and a first output circuit 12 .
  • the first input circuit 11 is electrically connected to the display input signal terminal Iput and the first pull-up node Q ⁇ 1>. Wherein, the first input circuit 11 is configured to transmit the display input signal to the first pull-up node Q ⁇ 1> in response to the display input signal received at the display input signal terminal Iput.
  • the first input circuit 11 can be turned on under the action of the display input signal, and receive and transmit the display input signal to the first pull-up node Q ⁇ 1 >, charge the first pull-up node Q ⁇ 1>, so that the voltage of the first pull-up node Q ⁇ 1> increases.
  • the first output circuit 12 is electrically connected to Oput1 ⁇ N> with the first pull-up node Q ⁇ 1>, the first clock signal terminal CLKE1 and the first scan signal terminal.
  • the first output circuit 12 is configured to control the voltage of the first pull-up node Q ⁇ 1> when the first input circuit 11 transmits the display input signal to the first pull-up node Q ⁇ 1>
  • the first clock signal received at the first clock signal terminal CLKE1 is transmitted to the first scanning signal terminal Oput1 ⁇ N> to drive the at least one row of sub-pixels P for image display.
  • the first output circuit 12 may be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, and will be The first clock signal received at the first clock signal terminal CLKE1 is transmitted to the first scan signal terminal Oput1 ⁇ N>, and the first clock signal is output from the first scan signal terminal Oput1 ⁇ N> as the first scan signal.
  • a plurality of pixel driving circuits P1 in the same row of sub-pixels P may be electrically connected to the same gate line GL.
  • the first scanning signal terminal Oput1 ⁇ N> of a shift register 100 can communicate with the first gate signal terminal G1 and the second gate signal terminal G1 and the second gate signal terminal of a plurality of pixel driving circuits P1 in the corresponding row of sub-pixels P through the gate line GL.
  • G2 is electrically connected.
  • the first scan signal output by the first scan signal terminal Oput1 ⁇ N> can also be transmitted to the first gate signal terminal G1 and the second gate signal terminal G2 of the plurality of pixel driving circuits P1 through the gate line GL.
  • the pull-up node Q ⁇ 1> is electrically connected to the first voltage signal terminal V1.
  • the black insertion circuit 2 is configured as, the first control signal transmitted by the first control signal terminal BCS1, the black insertion cascade signal transmitted by the black insertion cascade signal terminal BCR and the second control signal terminal BCS2 transmitted Under the control of the second control signal, the black insertion input signal received at the black insertion input signal terminal BI is transmitted to the first pull-up node Q ⁇ 1>.
  • the black insertion circuit 2 can It is turned on under the control of the first control signal, the black insertion cascade signal and the second control signal, receives the black insertion input signal, and transmits the black insertion input signal to the first pull-up node Q ⁇ 1>, for the first The pull-up node Q ⁇ 1> is charged, so that the voltage of the first pull-up node Q ⁇ 1> increases.
  • the first voltage signal terminal V1 is configured, for example, to transmit a DC low-level signal (eg, lower than or equal to the low-level part of the clock signal).
  • a DC low-level signal eg, lower than or equal to the low-level part of the clock signal.
  • the first voltage terminal V1 is grounded.
  • the output circuit 12 is further configured to, when the black insertion circuit 2 transmits the black insertion input signal to the first pull-up node Q ⁇ 1>, at the voltage of the first pull-up node Q ⁇ 1> Under control, the first clock signal is transmitted to the first scanning signal terminal Oput1 ⁇ N> to drive the at least one row of sub-pixels P to display a black screen.
  • the first output circuit 12 may be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, and will be in the first
  • the first clock signal received at the clock signal terminal CLKE1 is transmitted to the first scan signal terminal Oput1 ⁇ N>, and the first clock signal is output from the first scan signal terminal Oput1 ⁇ N> as the first scan signal.
  • the first input circuit 11 and the black insertion circuit 2 are turned on at different times.
  • the first gate signal terminal G1 and the second gate signal terminal G2 of multiple pixel driving circuits P1 in the same row of sub-pixels P are electrically connected to the same gate line GL as an example.
  • the first scan signal output by the first scan signal terminal Oput1 ⁇ N> corresponds to the scan signal received by the first gate signal terminal G1 and the second gate signal terminal G2 .
  • the voltage of the first pull-up node Q ⁇ 1> is first raised by the first input circuit 11 .
  • the first output circuit 12 can be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, and the first clock The signal is used as the first scanning signal and output from the first scanning signal terminal Oput1 ⁇ N>. As shown in FIG.
  • the first input circuit 11 is turned off, the voltage of the first pull-up node Q ⁇ 1> remains at a high level, and the first output circuit 12 is A pull-up node Q ⁇ 1> maintains the conduction state under the action of the voltage. Since the level of the first clock signal is high level, the level of the first scan signal output by the first output circuit 12 is high level.
  • the voltage of the first pull-up node Q ⁇ 1> is low level, the first output circuit 12 is turned off, and the level of the first scanning signal is low level; the drive transistor T2 is at the first node G Under the control of the voltage (the storage capacitor Cst is discharged), the light-emitting device P2 is driven to emit light.
  • the light-emitting device P2 is driven to emit light.
  • at least one row of sub-pixels P corresponding to the shift register 100 performs image display.
  • the black insertion circuit 2 is turned on and the first pull-up node Q ⁇ 1 > charging, the first output circuit 12 can be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>.
  • the first clock signal can be output from the first scanning signal terminal Oput1 ⁇ N> as a black insertion signal, and transmitted to the first gate signal terminal G1 and the second gate signal terminal G2 of the pixel driving circuit P1 of the corresponding row.
  • the switching transistor T1 can be turned on under the control of the black insertion signal to transmit the low level or lower level data signal (also called the black insertion data signal) To the first node G; the sensing transistor T3 can also be turned on under the control of the black insertion signal, and transmit a low-level reset signal to the second node S.
  • Vgs that is, the voltage difference between the first node G and the second node S
  • Vth that is, the threshold voltage of the driving transistor T2
  • a black picture can be inserted during the process of the sub-pixel P emitting light for normal image display, shortening the time period for the sub-pixel P to emit light normally. time to shorten the time for the display device 2000 to normally display a picture.
  • the MPRT Motion Picture Response Time, dynamic image response time
  • the MPRT Motion Picture Response Time, dynamic image response time
  • the ratio of the duration of the normal light emission of the sub-pixel P to the duration of maintaining a black screen can be controlled, which is convenient for adjusting the MPRT, and furthermore It is beneficial to improve the smear phenomenon of dynamic images and improve the effect of image display.
  • the first output circuit 12 may also be electrically connected to the third clock signal terminal CLKF1 and the first sensing signal terminal Oput2 ⁇ N>.
  • the first output circuit 12 is further configured to, when the first input circuit 11 transmits the display input signal to the first pull-up node Q ⁇ 1>, at the voltage of the first pull-up node Q ⁇ 1> Under control, the third clock signal received at the third clock signal terminal CLKF1 is transmitted to the first sensing signal terminal Oput2 ⁇ N> to drive the at least one row of sub-pixels P to reset.
  • the black insertion circuit 2 transmits the black insertion input signal to the first pull-up node Q ⁇ 1>, under the control of the voltage of the first pull-up node Q ⁇ 1>, the third clock signal is transmitted to The first sensing signal terminal Oput2 ⁇ N> drives the at least one row of sub-pixels P to display a black screen.
  • the first output circuit 12 may be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, and will be The third clock signal received at the third clock signal terminal CLKF1 is transmitted to the first sensing signal terminal Oput2 ⁇ N>, and the third clock signal is used as the first sensing signal, from the first sensing signal terminal Oput1 ⁇ N> output.
  • a plurality of pixel driving circuits in the same row of sub-pixels P are electrically connected to two gate lines GL.
  • the first scanning signal terminal Oput1 ⁇ N> of a shift register 100 can be electrically connected to the first gate signal terminal G1 of a plurality of pixel driving circuits P in the corresponding row of sub-pixels P through one of the gate lines GL, and the first scanning signal
  • the first scan signal output from the terminal Oput1 ⁇ N> can be transmitted to the first gate signal terminal G1 of the plurality of pixel driving circuits P1 through the gate line GL.
  • the first sensing signal terminal Oput2 ⁇ N> of the shift register 100 can be electrically connected to the second gate signal terminal G2 of a plurality of pixel driving circuits P1 in the corresponding row of sub-pixels P through another gate line GL.
  • the first sensing signal output by the sensing signal terminal Oput2 ⁇ N> can be used as the second scanning signal and transmitted to the second gate signal terminal G2 of the plurality of pixel driving circuits P1 through the gate line GL.
  • the first input circuit 11 is turned on, and the voltage of the first pull-up node Q ⁇ 1> remains is at a high level, the first output circuit 12 remains in an on state under the effect of the voltage of the first pull-up node Q ⁇ 1>. Since the levels of the first clock signal and the third clock signal are both at high level, the levels of the first scanning signal and the first sensing signal output by the first output circuit 12 are both at high level.
  • the switch transistor T1 is turned on under the control of the first scan signal (from the first scan signal terminal Oput1 ⁇ N>), and receives and transmits the data signal to the first node G; the sensing transistor T3 is controlled by the second scan signal (from the first scan signal terminal Oput1 ⁇ N>).
  • the sensing signal terminal Oput2 ⁇ N>) is turned on, receives and transmits a reset signal to the second node S, and resets the second node S. In this way, preparations can be made for the subsequent lighting phase t3 (ie image display).
  • the black insertion circuit 2 is turned on and the first pull-up node Q ⁇ 1 > charging, the first output circuit 12 can be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>.
  • the first clock signal can be output from the first scanning signal terminal Oput1 ⁇ N> as the first black insertion signal, and transmitted to the first gate signal terminal G1 of the pixel driving circuit P1 of the corresponding row, and the third clock signal can be used as
  • the second black insertion signal is output from the first sensing signal terminal Oput2 ⁇ N>, and transmitted to the second gate signal terminal G2 of the pixel driving circuit P1 of the corresponding row, so that the subsequent sub-pixels P display black images.
  • the plug-in black circuit 2 conducting and charging the first pull-up node Q ⁇ 1>, the first scan signal output from the first scan signal terminal Oput1 ⁇ N>
  • the level of the scanning signal (that is, the first black insertion signal) can be high level
  • the level of the first sensing signal (that is, the second black insertion signal) output from the first sensing signal terminal Oput2 ⁇ N> Can be low level.
  • the sensing transistor T3 can be turned off under the control of the second black insertion signal; the switching transistor T1 can be turned on under the control of the first black insertion signal, and the low-level or lower-level data signal (It can also be referred to as a black insertion data signal) is transmitted to the first node G, so that Vgs is smaller than Vth, and then the driving transistor T2 is turned off, so that the sub-pixel P stops emitting light and switches to a black screen.
  • the low-level or lower-level data signal It can also be referred to as a black insertion data signal
  • the first scanning signal output by the first scanning signal terminal Oput1 ⁇ N> (that is, The level of the first black insertion signal) can be a low level
  • the level of the first sensing signal (that is, the second black insertion signal) output from the first sensing signal terminal Oput2 ⁇ N> can be a high level
  • the switching transistor T1 can be turned off under the control of the first black insertion signal; the sensing transistor T3 is turned on under the control of the second black insertion signal, and the high level or higher level sensing signal (It can also be referred to as the black insertion sensing signal) is transmitted to the second node S, so that Vgs is smaller than Vth, and then the driving transistor T2 is turned off, so that the sub-pixel P stops emitting light and switches to a black screen.
  • the high level or higher level sensing signal It can also be referred to as the black insertion sensing signal
  • the time period when the input circuit 11 is turned on may be called a display sub-time period
  • the time period when the black insertion circuit 2 is turned on may be called a black insertion sub-time period.
  • the display sub-period and the sunspot insertion sub-period are performed sequentially.
  • the shift register 100 further includes: a second scanning unit 3 .
  • the second scanning unit 3 includes: a second input circuit 31 and a second output circuit 32 .
  • the second input circuit 31 is electrically connected to the display input signal terminal Iput and the second pull-up node Q ⁇ 2>. Wherein, the second input circuit 31 is configured to transmit the display input signal to the second pull-up node Q ⁇ 2> in response to the display input signal Iput.
  • the second input circuit 31 can be turned on under the effect of the display input signal, and receive and transmit the display input signal to the second pull-up node Q ⁇ 2 >, charge the second pull-up node Q ⁇ 2>, so that the voltage of the second pull-up node Q ⁇ 2> increases.
  • the second output circuit 32 is electrically connected to the second pull-up node Q ⁇ 2>, the second clock signal terminal CLKE2 and the second scanning signal terminal Oput1 ⁇ N+1> .
  • the second output circuit 32 is configured to control the voltage of the second pull-up node Q ⁇ 2> when the second input circuit 31 transmits the display input signal to the second pull-up node Q ⁇ 2>
  • the second clock signal received at the second clock signal terminal CLKE2 is transmitted to the second scanning signal terminal Oput1 ⁇ N+1> to drive the at least one row of sub-pixels P for image display.
  • the second output circuit 32 may be turned on under the control of the voltage of the second pull-up node Q ⁇ 2>, and will be
  • the second clock signal received at the second clock signal terminal CLKE2 is transmitted to the second scanning signal terminal Oput1 ⁇ N+1>, and the second clock signal is used as the second scanning signal, from the second scanning signal terminal Oput1 ⁇ N+1 > output.
  • the first input circuit 11 and the second input circuit 31 are electrically connected to the display input signal terminal Iput, therefore, when the level of the display input signal is a high level, the first input circuit 11 and the second input circuit 31 It can be turned on at the same time, and the first pull-up node Q ⁇ 1> and the second pull-up node Q ⁇ 2> can be charged at the same time, so that the first output circuit 12 and the second output circuit 32 can be turned on at the same time.
  • the first scan signal output by the first output circuit 12 and the second scan signal output by the second output circuit 32 may be different, for example. In this way, it is convenient to drive the sub-pixels P of different rows to perform row-by-row scanning and image display row-by-row.
  • the black insertion circuit 2 is also electrically connected to the second pull-up node Q ⁇ 2>.
  • the black insertion circuit 2 is further configured to transmit the black insertion input signal to the second pull-up node Q ⁇ 2> while transmitting the black insertion input signal to the first pull-up node Q ⁇ 1>.
  • the output circuit 32 is further configured to, when the black insertion circuit 2 transmits the black insertion input signal to the second pull-up node Q ⁇ 2>, under the control of the voltage of the second pull-up node Q ⁇ 2>,
  • the second clock signal is transmitted to the second scanning signal terminal Oput1 ⁇ N+1> to drive the at least one row of sub-pixels P to display a black screen.
  • the black insertion circuit 2 can It is turned on under the control of the first control signal, the black insertion cascade signal and the second control signal, receives the black insertion input signal, and transmits the black insertion input signal to the second pull-up node Q ⁇ 2>, for the second The pull-up node Q ⁇ 2> is charged, so that the voltage of the second pull-up node Q ⁇ 2> increases.
  • the second output circuit 32 can be turned on under the control of the voltage of the second pull-up node Q ⁇ 2>, and transmit the second clock signal received at the second clock signal terminal CLKE2 to the second scan signal terminal Oput1 ⁇ N+ 1>, and take the second clock signal as the second scanning signal, and output it from the second scanning signal terminal Oput1 ⁇ N+1>.
  • the black insertion circuit 2 is not only electrically connected to the first pull-up node Q ⁇ 1>, but also electrically connected to the second pull-up node Q ⁇ 2>, it means that the black insertion circuit 2 is simultaneously connected to the first scanning unit 1 and The second scanning unit 3 is electrically connected. In this way, when the black insertion circuit 2 is turned on, the high-level black insertion input signal can be transmitted to the first pull-up node Q ⁇ 1> and the second pull-up node Q ⁇ 2> at the same time, so that the first The output circuit 12 and the second output circuit 32 are turned on at the same time, and in the process that the first output circuit 12 outputs the first clock signal as the first scan signal, the second output circuit 32 outputs the second clock signal as the first scan signal .
  • the first scanning signal output by the first output circuit 12 and the second scanning signal output by the second output circuit 32 may be the same, for example.
  • the corresponding row of sub-pixels P electrically connected to the first scanning signal terminal Oput1 ⁇ N> and the corresponding row of sub-pixels P electrically connected to the second scanning signal terminal Oput1 ⁇ N+1> can be driven to display a black picture at the same time.
  • each shift register 100 can be electrically connected to at least one row of sub-pixels P, and then the multiple shift registers 100 can be used to control the pixels included in the display device 2000. Multiple rows of sub-pixels P perform progressive scanning or display black images progressively.
  • each shift register 100 can be electrically connected to at least two rows of sub-pixels P, wherein at least one row connected to the first scanning unit 1
  • the sub-pixel P is different from at least one row of sub-pixels P connected to the second scanning unit 3 .
  • at least two rows of sub-pixels P electrically connected to the shift register 100 can be driven to display a black screen at the same time, which is beneficial to reduce the time required for inserting a black screen, improve the phenomenon of moving image smear, and improve the effect of image display.
  • the above-mentioned second output circuit 32 may also be electrically connected to the fourth clock signal terminal CLKF2 and the second sensing signal terminal Oput2 ⁇ N+1>.
  • the second output circuit 32 is further configured to, when the second input circuit 31 transmits the display input signal to the second pull-up node Q ⁇ 2>, at the voltage of the second pull-up node Q ⁇ 2> Under control, the fourth clock signal received at the fourth clock signal terminal CLKF2 is transmitted to the second sensing signal terminal Oput2 ⁇ N+1> to drive at least one row of sub-pixels P to reset; or, in the black insertion circuit 2
  • the fourth clock signal is transmitted to the second sensing signal terminal Oput2 ⁇ N+1>, driving the at least one row of sub-pixels P to display a black screen.
  • the second output circuit 32 may be turned on under the control of the voltage of the second pull-up node Q ⁇ 2>, and will be The fourth clock signal received at the fourth clock signal terminal CLKF2 is transmitted to the second sensing signal terminal Oput2 ⁇ N+1>, and the fourth clock signal is used as the second sensing signal, from the second sensing signal terminal Oput1 ⁇ N+1> output.
  • the number of scanning units included in the shift register 100 provided in the present disclosure is not limited to two.
  • the structure of the black insertion circuit 2 will be schematically described below in conjunction with the accompanying drawings. Of course, the structure of the black insertion circuit 2 in the present disclosure is not limited thereto.
  • the black insertion circuit 2 includes: a black insertion control subcircuit 21 , a black insertion input subcircuit 22 and a first black insertion transmission subcircuit 23 .
  • the black insertion circuit 2 may further include: a second black insertion transmission sub-circuit 24 .
  • the black insertion control subcircuit 21 is electrically connected to the first control signal terminal BCS1, the black insertion cascade signal terminal BCR, the first voltage signal terminal V1, and the first black insertion node M. connect. Wherein, the black insertion control sub-circuit 21 is configured to transmit the black insertion cascade signal to the first black insertion node M under the control of the first control signal.
  • the black insertion control subcircuit 21 can be turned on under the control of the first control signal, and receive and transmit the black insertion cascade signal to the first insertion
  • the black node M charges the first inserted black node M, so that the voltage of the first inserted black node M increases.
  • the black insertion input sub-circuit 22 is electrically connected to the first black insertion node M, the black insertion input signal terminal BI and the second black insertion node K. Wherein, the black insertion input sub-circuit 22 is configured to transmit the black insertion input signal to the second black insertion node K under the control of the voltage of the first black insertion node M.
  • the black insertion input subcircuit 22 may be turned on under the control of the voltage of the first black insertion node M, and receive and transmit the black insertion input signal To the second inserted black node K, the second inserted black node K is charged, so that the voltage of the second inserted black node K increases.
  • the first black insertion transmission sub-circuit 23 is electrically connected to the second control signal terminal BCS2 , the second black insertion node K, and the first pull-up node Q ⁇ 1>. Wherein, the first black insertion transmission sub-circuit 23 is configured to transmit the black insertion input signal from the second black insertion node K to the first pull-up node Q ⁇ 1> under the control of the second control signal.
  • the first black insertion transmission sub-circuit 23 can be turned on under the control of the second control signal, and receive and transmit the black insertion input signal to the first
  • the pull-up node Q ⁇ 1> charges the first pull-up node Q ⁇ 1>, so that the voltage of the first pull-up node Q ⁇ 1> increases.
  • the second black insertion transmission sub-circuit 24 is electrically connected to the second control signal terminal BCS2 , the second black insertion node K, and the second pull-up node Q ⁇ 2>.
  • the second black insertion transmission sub-circuit 24 is configured to transmit the black insertion input signal from the second black insertion node K to the second pull-up node Q ⁇ 2> under the control of the second control signal.
  • the second black insertion transmission sub-circuit 24 can be turned on under the control of the second control signal, and receive and transmit the black insertion input signal to the second
  • the pull-up node Q ⁇ 2> charges the second pull-up node Q ⁇ 2>, so that the voltage of the second pull-up node Q ⁇ 2> increases.
  • the second control signal terminal BCS2 and the black input signal terminal BI are the same signal terminal. That is, the second control signal terminal BCS2 and the black input signal terminal BI receive the same signal and transmit the same signal. That is to say, the timing of the second control signal is the same as that of the black insertion input signal.
  • both the second control signal and the black insertion input signal are clock signals; or, both the second control signal and the black insertion input signal are certain shift signals.
  • the second control signal terminal BCS2 and the black input signal terminal BI are different signal terminals.
  • the second control signal transmitted by the second control signal terminal BCS2 may be a timing signal
  • the black insertion input signal transmitted by the black insertion input signal terminal BI may be a DC high level signal
  • the DC high-level signal may be, for example, a fifth voltage signal.
  • the fifth voltage signal reference may be made to the description below, and details will not be repeated here.
  • the black insertion control subcircuit 21 includes: a fifth transistor M5 and a third capacitor C3.
  • control electrode of the fifth transistor M5 is electrically connected to the first control signal terminal BCS1, and the first electrode of the fifth transistor M5 is connected to the plug black
  • the cascade signal terminal BCR is electrically connected, and the second pole of the fifth transistor M5 is electrically connected to the first black node M.
  • the fifth transistor M5 can be turned on under the control of the first control signal, and the black insertion level received at the black insertion cascade signal terminal BCR The connection signal is transmitted to the first black node M, and the first black node M is charged, so that the voltage of the first black node M increases.
  • the first end of the third capacitor C3 is electrically connected to the first black node M, and the second end of the third capacitor C3 is electrically connected to the first A voltage signal terminal V1 is electrically connected.
  • the third capacitor C3 will also be charged. After the fifth transistor M5 is turned off, the third capacitor C3 can be discharged, so that the voltage of the first black insertion node M remains at a high level.
  • the black insertion input sub-circuit 22 includes: a sixth transistor M6.
  • control electrode of the sixth transistor M6 is electrically connected to the first black node M, and the first electrode of the sixth transistor M6 is connected to the black node M.
  • the input signal terminal BI is electrically connected, and the second pole of the sixth transistor M6 is electrically connected to the second plug-in black node K.
  • the sixth transistor M6 can be at the voltage of the first black node M. It is turned on under the control of and receives and transmits the black insertion input signal to the second black insertion node K.
  • the first black insertion transmission sub-circuit 23 includes: a seventh transistor M7.
  • control electrode of the seventh transistor M7 is electrically connected to the second control signal terminal BCS2, and the first electrode of the seventh transistor M7 is connected to the second The plug-in black node K is electrically connected, and the second pole of the seventh transistor M7 is electrically connected to the first pull-up node Q ⁇ 1>.
  • the seventh transistor M7 may be turned on under the control of the second control signal, and transmit the black insertion input signal from the second black insertion node K to the second black insertion node K.
  • a pull-up node Q ⁇ 1> charges the first pull-up node Q ⁇ 1>, so that the voltage of the first pull-up node Q ⁇ 1> increases.
  • the second black insertion transmission sub-circuit 24 includes: an eighth transistor M8.
  • control electrode of the eighth transistor M8 is electrically connected to the second control signal terminal BCS2
  • first electrode of the eighth transistor M8 is electrically connected to the second black insertion node K
  • second pole of the eighth transistor M8 is electrically connected to the second pull-up node Q ⁇ 2>.
  • the eighth transistor M8 can be turned on under the control of the second control signal, and transmit the black insertion input signal from the second black insertion node K to the second black insertion node K.
  • the second pull-up node Q ⁇ 2> charges the second pull-up node Q ⁇ 2>, so that the voltage of the second pull-up node Q ⁇ 2> increases.
  • the first input circuit 11 includes: a first transistor M1 .
  • the control electrode of the first transistor M1 is electrically connected to the display input signal terminal Iput, and the first electrode of the first transistor M1 is connected to the display input signal terminal Iput.
  • the terminal Iput is electrically connected, and the second pole of the first transistor M1 is electrically connected to the first pull-up node Q ⁇ 1>.
  • the first transistor M1 may be turned on under the action of the display input signal, receive the display input signal, and transmit the display input signal to the first pull-up node Q ⁇ 1>, charging the first pull-up node Q ⁇ 1>, so that the voltage of the first pull-up node Q ⁇ 1> increases.
  • the first output circuit 12 includes: a second transistor M2 and a first capacitor C1 .
  • control electrode of the second transistor M2 is electrically connected to the first pull-up node Q ⁇ 1>, and the first electrode of the second transistor M2 It is electrically connected to the first clock signal terminal CLKE1 , and the second pole of the second transistor M2 is electrically connected to the first scanning signal terminal Oput1 ⁇ N>.
  • the second transistor M2 may be turned on under the control of the first pull-up node Q ⁇ 1>, and the signal from the first clock signal terminal
  • the first clock signal received at CLKE1 is output from the first scanning signal terminal Oput1 ⁇ N>.
  • the first scanning signal outputted from the first scanning signal terminal Oput1 ⁇ N> has different functions when it is turned on in different time periods. For details, reference may be made to the descriptions in some of the above examples, which will not be repeated here.
  • the first end of the first capacitor C1 is electrically connected to the first pull-up node Q ⁇ 1>, and the second end of the first capacitor C1 terminal is electrically connected to the first scanning signal terminal Oput1 ⁇ N>.
  • the first capacitor C1 when the first transistor M1 in the first input circuit 12 is turned on and charges the first pull-up node Q ⁇ 1>, the first capacitor C1 will also be charged. After the first transistor M1 is turned off, the first capacitor C1 can be discharged, so that the voltage of the first pull-up node Q ⁇ 1> remains at a high level.
  • the first capacitor C1 will also be charged. After the black insertion circuit 2 is turned off, the first capacitor C1 can be discharged, so that the voltage of the first pull-up node Q ⁇ 1> remains at a high level.
  • the first output circuit 12 when the first output circuit 12 is also electrically connected to the third clock signal terminal CLKF1 and the first sensing signal terminal Oput2 ⁇ N>, the first The output circuit 12 further includes: a ninth transistor M9 and a fourth capacitor C4.
  • the control electrode of the ninth transistor M9 is electrically connected to the first pull-up node Q ⁇ 1>, and the first electrode of the ninth transistor M9 is connected to the third clock signal terminal CLKF1 is electrically connected, and the second pole of the ninth transistor M9 is electrically connected to the first sensing signal terminal Oput2 ⁇ N>.
  • the ninth transistor M9 may be turned on under the control of the first pull-up node Q ⁇ 1>, and the signal from the third clock signal terminal
  • the third clock signal received at CLKF1 is output from the first sensing signal terminal Oput2 ⁇ N>.
  • the first sensing signal output from the first sensing signal terminal Oput2 ⁇ N> has different functions when it is turned on at different time periods. For details, reference may be made to the descriptions in some of the above examples, which will not be repeated here.
  • the first end of the fourth capacitor C4 is electrically connected to the first pull-up node Q ⁇ 1>, and the second end of the fourth capacitor C4 is electrically connected to the first sensing
  • the signal terminal Oput2 ⁇ N> is electrically connected.
  • the fourth capacitor C4 is also charged. After the first transistor M1 is turned off, the fourth capacitor C4 can be discharged, so that the voltage of the first pull-up node Q ⁇ 1> remains at a high level.
  • the fourth capacitor C4 will also be charged. After the black insertion circuit 2 is turned off, the fourth capacitor C4 can be discharged, so that the voltage of the first pull-up node Q ⁇ 1> remains at a high level.
  • the second input circuit 31 includes: a third transistor M3.
  • the control electrode of the third transistor M3 is electrically connected to the display input signal terminal Iput
  • the first electrode of the third transistor M3 is electrically connected to the display input signal terminal Iput
  • the third transistor M3 is electrically connected to the display input signal terminal Iput.
  • the second pole of the three-transistor M3 is electrically connected to the second pull-up node Q ⁇ 2>.
  • the third transistor M3 may be turned on under the effect of the display input signal, receive the display input signal, and transmit the display input signal to the second pull-up node Q ⁇ 2>, charging the second pull-up node Q ⁇ 2>, so that the voltage of the second pull-up node Q ⁇ 2> increases.
  • the second output circuit 32 includes: a fourth transistor M4 and a second capacitor C2 .
  • control electrode of the fourth transistor M4 is electrically connected to the second pull-up node Q ⁇ 2>, and the first electrode of the fourth transistor M4 is connected to the second clock signal terminal CLKE2 is electrically connected, and the second pole of the fourth transistor M4 is electrically connected to the second scan signal terminal Oput1 ⁇ N+1>.
  • the fourth transistor M4 may be turned on under the control of the second pull-up node Q ⁇ 2>, and the second clock signal terminal
  • the second clock signal received at CLKE2 is output from the second scanning signal terminal Oput1 ⁇ N+1>.
  • the second scanning signal outputted from the second scanning signal terminal Oput1 ⁇ N+1> has different functions during different periods of conduction, for details, reference may be made to the descriptions in some of the above examples, which will not be repeated here.
  • the first terminal of the second capacitor C2 is electrically connected to the second pull-up node Q ⁇ 2>, and the second terminal of the second capacitor C2 is connected to the second scan signal Terminals Oput1 ⁇ N+1> are electrically connected.
  • the second capacitor C2 when the third transistor M3 in the second input circuit 12 is turned on and charges the second pull-up node Q ⁇ 2>, the second capacitor C2 will also be charged. After the third transistor M3 is turned off, the second capacitor C2 can be discharged, so that the voltage of the second pull-up node Q ⁇ 2> remains at a high level.
  • the second capacitor C2 will also be charged. After the black insertion circuit 2 is turned off, the second capacitor C2 can be discharged, so that the voltage of the second pull-up node Q ⁇ 2> remains at a high level.
  • the second output circuit 32 when the second output circuit 32 is also electrically connected to the fourth clock signal terminal CLKF2 and the second sensing signal terminal Oput2 ⁇ N+1>, the second output circuit 32 is also It includes: a tenth transistor M10 and a fifth capacitor C5.
  • the control electrode of the tenth transistor M10 is electrically connected to the second pull-up node Q ⁇ 2>
  • the first electrode of the tenth transistor M10 is electrically connected to the fourth clock signal terminal CLKF2
  • the tenth transistor M10 is electrically connected to the fourth clock signal terminal CLKF2.
  • the second pole of the transistor M10 is electrically connected to the second sensing signal terminal Oput2 ⁇ N+1>.
  • the tenth transistor M10 may be turned on under the control of the second pull-up node Q ⁇ 2>, and the fourth clock signal terminal
  • the fourth clock signal received at CLKF2 is output from the second sensing signal terminal Oput2 ⁇ N+1>.
  • the second sensing signal outputted from the second sensing signal terminal Oput2 ⁇ N+1> has different effects when it is turned on in different time periods. For details, reference may be made to the descriptions in some of the above examples, which will not be repeated here.
  • the first terminal of the fifth capacitor C5 is electrically connected to the second pull-up node Q ⁇ 2>, and the second terminal of the fifth capacitor C5 is connected to the second sensing signal terminal Oput2 ⁇ N+ 1> Electrical connection.
  • the fifth capacitor C5 when the third transistor M3 in the second input circuit 12 is turned on and charges the second pull-up node Q ⁇ 2>, the fifth capacitor C5 will also be charged. After the third transistor M3 is turned off, the fifth capacitor C5 can be discharged, so that the voltage of the second pull-up node Q ⁇ 2> remains at a high level.
  • the fifth capacitor C5 will also be charged. After the black insertion circuit 2 is turned off, the fifth capacitor C5 can be discharged, so that the voltage of the second pull-up node Q ⁇ 2> remains at a high level.
  • the first output circuit 12 is also electrically connected to the fifth clock signal terminal CLKD1 and the first shift signal terminal CR ⁇ N>. Wherein, the first output circuit 12 is further configured to transmit the fifth clock signal received at the fifth clock signal terminal CLKD1 to the first shift signal under the control of the voltage of the first pull-up node Q ⁇ 1> Terminal CR ⁇ N>.
  • the first output circuit 12 may be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, and will be
  • the fifth clock signal received at the fifth clock signal terminal CLKD1 is used as the first shift signal and output from the first shift signal terminal CR ⁇ N>.
  • the structure of the first output circuit 12 will be schematically described below with reference to the accompanying drawings.
  • the first output circuit 12 further includes: an eleventh transistor M11.
  • control electrode of the eleventh transistor M11 is electrically connected to the first pull-up node Q ⁇ 1>, and the first electrode of the eleventh transistor M11 is electrically connected to the fifth clock signal terminal CLKD1,
  • the second pole of the eleventh transistor M11 is electrically connected to the first shift signal terminal CR ⁇ N>.
  • the eleventh transistor M11 may be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, and the voltage from the fifth The fifth clock signal received at the clock signal terminal CLKD1 is output as the first shift signal from the first shift signal terminal CR ⁇ N>.
  • the second output circuit 32 is also connected to the sixth clock signal terminal CLKD2 and the second shift signal Terminal CR2 ⁇ N+1> is electrically connected.
  • the second output circuit 32 is further configured to transmit the sixth clock signal received at the sixth clock signal terminal CLKD2 to the second shift signal under the control of the voltage of the second pull-up node Q ⁇ 2> Terminal CR2 ⁇ N+1>.
  • the second output circuit 32 may be turned on under the control of the voltage of the second pull-up node Q ⁇ 2>, and will be
  • the sixth clock signal received at the sixth clock signal terminal CLKD2 is used as the second shift signal and output from the second shift signal terminal CR2 ⁇ N+1>.
  • the second output circuit 32 further includes: a twelfth transistor M12.
  • control electrode of the twelfth transistor M12 is electrically connected to the second pull-up node Q ⁇ 2>, and the first electrode of the twelfth transistor M12 is electrically connected to the sixth clock signal terminal CLKD2, The second pole of the twelfth transistor M12 is electrically connected to the second shift signal terminal CR2 ⁇ N+1>.
  • the twelfth transistor M12 may be turned on under the control of the voltage of the second pull-up node Q ⁇ 2>, and the voltage from the sixth The sixth clock signal received at the clock signal terminal CLKD2 is output from the second shift signal terminal CR2 ⁇ N+1> as the second shift signal.
  • first shift signal terminal CR ⁇ N> and the second shift signal terminal CR2 ⁇ N+1> are both used for cascade connection, so as to simplify the structure of the scan driving circuit 1000 and reduce the size of the scan driving circuit. 1000 Occupied area in frame area B. That is to say, in the case of cascading using the shift signal terminal, the first output circuit 12 or the second output circuit 32 can be electrically connected to the corresponding shift signal terminal, and in the case of cascading without using the shift signal terminal In some cases, the first output circuit 12 or the second output circuit 32 may not be electrically connected to the corresponding shift signal terminal (that is, not include the corresponding transistor).
  • the shift signal terminal electrically connected to the two belong to different scanning units respectively. This can avoid the situation that the first input circuit 11, the second input circuit 31 and the black insertion circuit 2 of the same shift register 100 are simultaneously turned on due to being connected to the same shift signal terminal, thereby avoiding the process of normal image display and A case where the process of inserting a black screen conflicts.
  • the shift register 100 can also include other circuit structures, which can be selected and set according to actual needs.
  • the shift register 100 may further include: a third anti-leakage circuit 6 .
  • the third anti-leakage circuit 6 is electrically connected to the first black insertion node M, the fifth voltage signal terminal V5 and the third anti-leakage node OFF3.
  • the third anti-leakage circuit 6 is configured to transmit the fifth voltage signal received at the fifth voltage signal terminal V5 to the third anti-leakage node OFF3 under the control of the voltage of the first black insertion node M.
  • the fifth voltage signal terminal V5 can be configured, for example, to transmit a DC high-level signal (for example, higher than or equal to the high-level part of the clock signal).
  • the third anti-leakage circuit 6 may be turned on under the control of the voltage of the first inserted black node M, and receive and transmit the fifth voltage signal To the third anti-leakage node OFF3, the third anti-leakage node OFF3 is charged, so that the voltage of the third anti-leakage node OFF3 increases.
  • the black insertion control subcircuit 21 is also electrically connected to the third anti-leakage node OFF3 .
  • the fifth transistor M5 in the black insertion control sub-circuit 21 When the fifth transistor M5 in the black insertion control sub-circuit 21 is turned off and the third capacitor C3 is discharged so that the voltage of the first black insertion node M remains at a high level, by connecting the black insertion control sub-circuit 21 with The third anti-leakage node OFF3 is electrically connected, which can reduce the voltage difference between the third anti-leakage node OFF3 and the first black insertion node M, and prevent the first black insertion node M from leaking through the black insertion control sub-circuit 21, thereby enabling The first black insertion node M can be maintained at a relatively high and relatively stable voltage, so as to avoid affecting the conduction state of the black insertion input sub-circuit 22 .
  • the third anti-leakage circuit 6 includes: a seventieth transistor M70.
  • the control electrode of the seventieth transistor M70 is electrically connected to the first black node M
  • the first electrode of the seventieth transistor M70 is electrically connected to the fifth voltage signal terminal V5
  • the seventieth transistor M70 is electrically connected to the fifth voltage signal terminal V5.
  • the second pole of the transistor M70 is electrically connected to the third anti-leakage node OFF3.
  • the seventieth transistor M70 can be turned on under the control of the voltage of the first black node M, receives the fifth voltage signal, and turns the fifth The voltage signal is transmitted to the third anti-leakage node OFF3 to charge the third anti-leakage node OFF3 so that the voltage of the third anti-leakage node OFF3 increases.
  • the black insertion control subcircuit 21 further includes: a seventy-first transistor M71.
  • the control electrode of the seventy-first transistor M71 is electrically connected to the first control signal terminal BCS1, and the first electrode of the seventy-first transistor M71 is electrically connected to the black insertion cascade signal terminal BCR,
  • the second pole of the seventy-first transistor M71 is electrically connected to the third anti-leakage node OFF3.
  • the first pole of the fifth transistor M5 in the black insertion control sub-circuit 21 is electrically connected to the third anti-leakage node OFF3, and is electrically connected to the black insertion cascade signal terminal BCR through the seventy-first transistor M71.
  • the fifth transistor M5 and the seventy-first transistor M71 may be turned on simultaneously under the action of the first control signal.
  • the seventy-first transistor M71 can receive and transmit the black insertion cascade signal to the third anti-leakage node OFF3, the fifth transistor M5 can receive and transmit the black insertion cascade signal to the first black insertion node M, and the first black insertion node M M to charge.
  • the fifth transistor M5 and the seventy-first transistor M71 can be turned off simultaneously under the action of the first control signal.
  • the third capacitor C3 in the black insertion control sub-circuit 21 starts to discharge, so that the voltage of the first black insertion node M remains at a high level.
  • the seventieth transistor M70 in the third anti-leakage circuit 6 can transmit the fifth voltage signal to the third anti-leakage node OFF3 to charge the third anti-leakage node OFF3, reducing the voltage of the third anti-leakage node OFF3.
  • the voltage difference between OFF3 and the first black node M makes the voltage difference between the control electrode and the first electrode of the fifth transistor M5 less than zero, ensuring that the fifth transistor M5 is completely or relatively completely turned off. This can prevent the first black insertion node M from leaking electricity through the black insertion control sub-circuit 21, so that the first black insertion node M can be maintained at a higher and more stable voltage.
  • the shift register 100 can also include other circuit structures, which can be selected and set according to actual needs.
  • the first scanning unit 1 in the shift register 100 may further include: a first reset circuit 13 and a second reset circuit 14 .
  • the first reset circuit 13 is electrically connected to the first reset signal terminal STD, the first pull-up node Q ⁇ 1> and the first voltage signal terminal V1 .
  • the first reset circuit 13 is configured to, under the control of the first reset signal transmitted by the first reset signal terminal STD, transmit the first voltage signal received at the first voltage signal terminal V1 to the first pull-up Node Q ⁇ 1>.
  • the first reset circuit 13 can be turned on under the control of the first reset signal, and the first voltage signal received at the first voltage signal terminal V1 It is transmitted to the first pull-up node Q ⁇ 1>, and the pull-down reset is performed on the first pull-up node Q ⁇ 1>.
  • the first reset signal terminal STD of the other shift registers 100 at all levels can be electrically connected with the first shift signal terminal CR ⁇ N> of a shift register 100 of a subsequent stage, and then the first shift signal output by the shift register 100 The signal can be used as the first reset signal of the corresponding shift register 100 .
  • the first reset signal terminal STD of the partial shift register 100 may be electrically connected to the display reset signal line, so as to receive the display reset signal transmitted by the display reset signal line as the first reset signal.
  • the part of the shift registers 100 may be, for example, the last two stages of shift registers 100 in the scan driving circuit 1000 . This enables a cascaded reset.
  • the second reset circuit 14 is connected to the second reset signal terminal BTRST, the first black insertion node M, the second A pull-up node Q ⁇ 1> is electrically connected to the first voltage signal terminal V1.
  • the second reset circuit 14 is configured to transmit the first voltage signal to the first pull-up node under the control of the voltage of the first black insertion node M and the second reset signal transmitted by the second reset signal terminal BTRST Q ⁇ 1>.
  • the second reset circuit 14 can operate between the voltage of the first black node M and the second reset signal. Conducting under the control of the reset signal, the first voltage signal received at the first voltage signal terminal V1 is transmitted to the first pull-up node Q ⁇ 1>, and the pull-down reset is performed on the first pull-up node Q ⁇ 1>.
  • the second reset circuit 14 can, for example, reset the first pull-up node Q ⁇ 1> after the black insertion sub-period (that is, after a black picture is displayed).
  • the second scanning unit 3 may further include: a third reset circuit 33 and a fourth reset circuit 34 .
  • the third reset circuit 33 is electrically connected to the first reset signal terminal STD, the second pull-up node Q ⁇ 2> and the first voltage signal terminal V1 .
  • the third reset circuit 33 is configured to transmit the first voltage signal to the second pull-up node Q ⁇ 2> under the control of the first reset signal.
  • the third reset circuit 33 can be turned on under the control of the first reset signal, and the first voltage signal received at the first voltage signal terminal V1
  • the second pull-up node Q ⁇ 2> is transmitted to the second pull-up node Q ⁇ 2>, and the second pull-up node Q ⁇ 2> is pulled down to reset.
  • both the third reset circuit 33 and the first reset circuit 13 are electrically connected to the first reset signal terminal STD, therefore, when the level of the first reset signal is a high level, the third reset circuit 33 and the first reset The circuit 13 can both be turned on, and perform a pull-down reset on the first pull-up node Q ⁇ 1> and the second pull-up node Q ⁇ 2> at the same time.
  • the fourth reset circuit 34 is connected to the second reset signal terminal BTRST, the first plug-in black node M, the second pull-up node Q ⁇ 2> and the first voltage signal terminal V1 electrical connection.
  • the fourth reset circuit 34 is configured to transmit the first voltage signal to the second pull-up node Q ⁇ 2> under the control of the voltage of the first black insertion node M and the second reset signal.
  • the fourth reset circuit 34 can operate between the voltage of the first black node M and the second reset signal. Conducting under the control of the reset signal, the first voltage signal received at the first voltage signal terminal V1 is transmitted to the second pull-up node Q ⁇ 2>, and the pull-down reset is performed on the second pull-up node Q ⁇ 2>.
  • both the fourth reset circuit 34 and the second reset circuit 14 can be turned on, so that the first pull-up node Q ⁇ 1> and the second Pull up node Q ⁇ 2> for pull-down reset.
  • first reset circuit 13 The structures of the first reset circuit 13 , the second reset circuit 14 , the third reset circuit 33 and the fourth reset circuit 44 will be schematically described below in conjunction with the accompanying drawings.
  • the first reset circuit 13 includes: a thirteenth transistor M13.
  • control electrode of the thirteenth transistor M13 is electrically connected to the first reset signal terminal STD, and the first electrode of the thirteenth transistor M13 is connected to the first pull-up node Q ⁇ 1> Electrically connected, the second pole of the thirteenth transistor M13 is electrically connected to the first voltage signal terminal V1.
  • the thirteenth transistor M13 may be turned on under the control of the first reset signal, and receive and transmit the first voltage signal to the first pull-up node Q ⁇ 1>, perform a pull-down reset on the first pull-up node Q ⁇ 1>.
  • the second reset circuit 14 includes: a fourteenth transistor M14 and a fifteenth transistor M15 .
  • the control electrode of the fourteenth transistor M14 is electrically connected to the first black insertion node M, and the first electrode of the fourteenth transistor M14 is connected to the first pull-up node Q ⁇ 1> Electrically connected, the second pole of the fourteenth transistor M14 is electrically connected to the first pole of the fifteenth transistor M15.
  • the control electrode of the fifteenth transistor M15 is electrically connected to the second reset signal terminal BTRST, and the second electrode of the fifteenth transistor M15 is electrically connected to the first voltage signal terminal V1.
  • the fourteenth transistor M14 can be controlled by the voltage of the first black node M. turn on, the fifteenth transistor M15 can be turned on under the control of the second reset signal, the fifteenth transistor M15 can receive and transmit the first voltage signal to the second pole of the fourteenth transistor M14, and then the fourteenth transistor M14
  • the first voltage signal can be transmitted to the first pull-up node Q ⁇ 1>, and pull-down reset is performed on the first pull-up node Q ⁇ 1>.
  • the third reset circuit 33 includes: a sixteenth transistor M16.
  • control electrode of the sixteenth transistor M16 is electrically connected to the first reset signal terminal STD, and the first electrode of the sixteenth transistor M16 is electrically connected to the second pull-up node Q ⁇ 2>, The second pole of the sixteenth transistor M16 is electrically connected to the first voltage signal terminal V1.
  • the sixteenth transistor M16 may be turned on under the control of the first reset signal, and receive and transmit the first voltage signal to the second pull-up node Q ⁇ 2>, perform a pull-down reset on the second pull-up node Q ⁇ 2>.
  • the fourth reset circuit 34 includes: a seventeenth transistor M17 and an eighteenth transistor M18 .
  • the control electrode of the seventeenth transistor M17 is electrically connected to the first black insertion node M, and the first electrode of the seventeenth transistor M17 is electrically connected to the second pull-up node Q ⁇ 2>.
  • the second pole of the seventeenth transistor M17 is electrically connected to the first pole of the eighteenth transistor M18.
  • the control electrode of the eighteenth transistor M18 is electrically connected to the second reset signal terminal BTRST, and the second electrode of the eighteenth transistor M18 is electrically connected to the first voltage signal terminal V1.
  • the seventeenth transistor M17 can be controlled by the voltage of the first black node M. turn on, the eighteenth transistor M18 can be turned on under the control of the second reset signal, the eighteenth transistor M18 can receive and transmit the first voltage signal to the second pole of the seventeenth transistor M17, and then the seventeenth transistor M17
  • the first voltage signal can be transmitted to the second pull-up node Q ⁇ 2>, and pull-down reset is performed on the second pull-up node Q ⁇ 2>.
  • the shift register 100 can also include other circuit structures, which can be selected and set according to actual needs.
  • the first scanning unit 1 in the shift register 100 may further include: a first control circuit 15 .
  • the first control circuit 15 is electrically connected to the first pull-up node Q ⁇ 1>, the first pull-down node QB_A, the first voltage signal terminal V1, and the second voltage signal terminal V2. connect.
  • the first control circuit 15 is configured to transmit the second voltage signal to the first pull-down node QB_A in response to the second voltage signal received at the second voltage signal terminal V2, and, at the first pull-up node Under the control of the voltage of Q ⁇ 1>, the first voltage signal received at the first voltage signal terminal V1 is transmitted to the first pull-down node QB_A.
  • the first control circuit 15 can receive and transmit the second voltage signal to the first pull-down node QB_A under the control of the second voltage signal.
  • the first control circuit 15 can receive and transmit the first voltage signal under the control of the voltage of the first pull-up node Q ⁇ 1> To the first pull-down node QB_A, perform pull-down reset on the first pull-down node QB_A.
  • the second scanning unit 3 may further include: a second control circuit 35 .
  • the second control circuit 35 is electrically connected to the second pull-up node Q ⁇ 2>, the second pull-down node QB_B, the first voltage signal terminal V1, and the third voltage signal terminal V3 .
  • the second control circuit 35 is configured to transmit the third voltage signal to the second pull-down node QB_B in response to the third voltage signal received at the third voltage signal terminal V3, and, at the second pull-up node QB_B Under the control of the voltage of ⁇ 2>, the first voltage signal is transmitted to the second pull-down node QB_B.
  • the second control circuit 35 can receive and transmit the third voltage signal to the second pull-down node QB_B under the control of the third voltage signal.
  • the second control circuit 35 can receive and transmit the first voltage signal under the control of the voltage of the second pull-up node Q ⁇ 2> To the second pull-down node QB_B, perform pull-down reset on the second pull-down node QB_B.
  • the second voltage signal terminal V2 can be configured, for example, to transmit a DC high-level signal (for example, higher than or equal to the high-level part of the clock signal).
  • the third voltage signal terminal V3 may be configured to transmit a DC high-level signal (for example, higher than or equal to the high-level part of the clock signal).
  • the "high level” and “low level” mentioned in this article are relative terms.
  • the voltage value of the second voltage signal is greater than the voltage value of the first voltage signal.
  • the second voltage signal terminal V2 can also be configured, for example, to transmit a DC high-level signal (eg higher than or equal to the high-level portion of the clock signal) in a display phase of one frame.
  • the third voltage signal terminal V3 may be configured to transmit a DC high-level signal (for example, higher than or equal to the high-level part of the clock signal) in a display phase of one frame.
  • the second voltage signal and the third voltage signal are mutually inverse signals.
  • the first control circuit 15 includes: a nineteenth transistor M19 , a twentieth transistor M20 , a twenty-first transistor M21 and a twenty-second transistor M22 .
  • the control electrode of the nineteenth transistor M19 is electrically connected to the second voltage signal terminal V2, and the first electrode of the nineteenth transistor M19 is electrically connected to the second voltage signal terminal V2,
  • the second electrode of the nineteenth transistor M19 is electrically connected to the control electrode of the twentieth transistor M20 and the first electrode of the twenty-first transistor M21.
  • a first pole of the twentieth transistor M20 is electrically connected to the second voltage signal terminal V2, and a second pole of the twentieth transistor M20 is electrically connected to the first pull-down node QB_A.
  • the nineteenth transistor M19 may be turned on under the control of the second voltage signal, and receive and transmit the second voltage signal to the gate of the twentieth transistor M20.
  • the twentieth transistor M20 can be turned on under the control of the second voltage signal, receive and transmit the second voltage signal to the first pull-down node QB_A, and charge the first pull-down node QB_A, so that the first pull-down node QB_A voltage rise.
  • control electrode of the twenty-first transistor M21 is electrically connected to the first pull-up node Q ⁇ 1>, and the second electrode of the twenty-first transistor M21 is connected to the first voltage signal Terminal V1 is electrically connected.
  • the twenty-first transistor M21 may be turned on under the control of the first pull-up node Q ⁇ 1> to receive and transmit the first
  • the voltage signal is sent to the control electrode of the twentieth transistor M20.
  • the twentieth transistor M20 may be turned off under the control of the first voltage signal.
  • control electrode of the twenty-second transistor M22 is electrically connected to the first pull-up node Q ⁇ 1>, and the first electrode of the twenty-second transistor M22 is connected to the first pull-down node Q ⁇ 1>.
  • the node QB_A is electrically connected, and the second pole of the twenty-second transistor M22 is electrically connected to the first voltage signal terminal V1.
  • the twenty-second transistor M22 may be turned on under the control of the first pull-up node Q ⁇ 1> to receive and transmit the first The voltage signal is sent to the first pull-down node QB_A to perform a pull-down reset on the first pull-down node QB_A.
  • the second control circuit 35 includes: a twenty-third transistor M23 , a twenty-fourth transistor M24 , a twenty-fifth transistor M25 and a twenty-sixth transistor M26 .
  • the control electrode of the twenty-third transistor M23 is electrically connected to the third voltage signal terminal V3, and the first electrode of the twenty-third transistor M23 is electrically connected to the third voltage signal terminal V3.
  • the second pole of the twenty-third transistor M23 is electrically connected to the control pole of the twenty-fourth transistor M24 and the first pole of the twenty-fifth transistor M25.
  • a first pole of the twenty-fourth transistor M24 is electrically connected to the third voltage signal terminal V3, and a second pole of the twenty-fourth transistor M24 is electrically connected to the second pull-down node QB_B.
  • the twenty-third transistor M23 may be turned on under the control of the third voltage signal, and receive and transmit the third voltage signal to the control electrode of the twenty-fourth transistor M24.
  • the twenty-fourth transistor M24 can be turned on under the control of the third voltage signal, receives and transmits the third voltage signal to the second pull-down node QB_B, and charges the second pull-down node QB_B, so that the voltage of the second pull-down node QB_B uplift.
  • control electrode of the twenty-fifth transistor M25 is electrically connected to the second pull-up node Q ⁇ 2>, and the second electrode of the twenty-fifth transistor M25 is connected to the first voltage signal Terminal V1 is electrically connected.
  • the twenty-fifth transistor M25 may be turned on under the control of the second pull-up node Q ⁇ 2> to receive and transmit the first
  • the voltage signal is sent to the control electrode of the twenty-fourth transistor M24.
  • the twenty-fourth transistor M24 can be turned off under the control of the first voltage signal.
  • control electrode of the twenty-sixth transistor M26 is electrically connected to the second pull-up node Q ⁇ 2>, and the first electrode of the twenty-sixth transistor M26 is connected to the second pull-down node Q ⁇ 2>.
  • QB_B is electrically connected, and the second pole of the twenty-sixth transistor M26 is electrically connected to the first voltage signal terminal V1.
  • the twenty-sixth transistor M26 may be turned on under the control of the second pull-up node Q ⁇ 2> to receive and transmit the first The voltage signal is sent to the second pull-down node QB_B to perform pull-down reset on the second pull-down node QB_B.
  • the shift register 100 can also include other circuit structures, which can be selected and set according to actual needs.
  • the first scanning unit 1 further includes: a fifth reset circuit 16 , a sixth reset circuit 17 and a seventh reset circuit 18 .
  • the fifth reset circuit 16 is electrically connected to the first pull-down node QB_A, the first pull-up node Q ⁇ 1> and the first voltage signal terminal V1.
  • the fifth reset circuit 16 is configured to transmit the first voltage signal to the first pull-up node Q ⁇ 1> under the control of the voltage of the first pull-down node QB_A.
  • the fifth reset circuit 16 may be turned on under the control of the voltage of the first pull-down node QB_A, and will receive The first voltage signal of the first pull-up node Q ⁇ 1> is transmitted to the first pull-up node Q ⁇ 1>, and pull-down reset is performed on the first pull-up node Q ⁇ 1>.
  • the sixth reset circuit 17 is electrically connected to the first pull-down node QB_A, the first scan signal terminal Oput1 ⁇ N> and the fourth voltage signal terminal V4 .
  • the sixth reset circuit 17 is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal V4 to the first scan signal terminal Oput1 ⁇ N> under the control of the voltage of the first pull-down node QB_A .
  • the sixth reset circuit 17 may be turned on under the control of the voltage of the first pull-down node QB_A, and will receive The fourth voltage signal is transmitted to the first scanning signal terminal Oput1 ⁇ N>, and the first scanning signal terminal Oput1 ⁇ N> is pulled down to reset.
  • the fourth voltage signal terminal V4 may be configured, for example, to transmit a DC low-level signal (eg, lower than or equal to the low-level part of the clock signal).
  • a DC low-level signal eg, lower than or equal to the low-level part of the clock signal.
  • the fourth voltage signal terminal V4 is grounded.
  • the voltage value of the first voltage signal and the voltage value of the fourth voltage signal may be equal or unequal.
  • the sixth reset circuit 17 when the first output circuit 12 is also electrically connected to the third clock signal terminal CLKF1 and the first sensing signal terminal Oput2 ⁇ N>, the sixth reset circuit 17 also It is electrically connected with the first sensing signal terminal Oput2 ⁇ N>. Wherein, the sixth reset circuit 17 is further configured to transmit the fourth voltage signal to the first sensing signal terminal Oput2 ⁇ N> under the control of the voltage of the first pull-down node QB_A.
  • the sixth reset circuit 17 may be turned on under the control of the voltage of the first pull-down node QB_A, and will receive The fourth voltage signal of the first sensing signal terminal Oput2 ⁇ N> is transmitted to the first sensing signal terminal Oput2 ⁇ N>, and pull-down reset is performed on the first sensing signal terminal Oput2 ⁇ N>.
  • the sixth reset circuit 17 when the first output circuit 12 is still electrically connected to the fifth clock signal terminal CLKD1 and the first shift signal terminal CR ⁇ N>, the sixth reset circuit 17 also It is electrically connected with the first shift signal terminal CR ⁇ N> and the first voltage signal terminal V1. Wherein, the sixth reset circuit 17 is further configured to transmit the first voltage signal to the first shift signal terminal CR ⁇ N> under the control of the voltage of the first pull-down node QB_A.
  • the sixth reset circuit 17 may be turned on under the control of the voltage of the first pull-down node QB_A, and will receive The first voltage signal of the first shift signal terminal CR ⁇ N> is transmitted to the first shift signal terminal CR ⁇ N>, and pull-down reset is performed on the first shift signal terminal CR ⁇ N>.
  • the seventh reset circuit 18 is connected to the first black insertion node M, the second control signal terminal BCS2, the second The pull-down node QB_A is electrically connected to the first voltage signal terminal V1.
  • the seventh reset circuit 18 is configured to transmit the first voltage signal to the first pull-down node QB_A under the control of the voltage of the first black insertion node M and the second control signal.
  • the seventh reset circuit 18 can be set between the voltage of the first black insertion node M and the second control signal. Conducting under the control of the control signal, the first voltage signal received at the first voltage signal terminal V1 is transmitted to the first pull-down node QB_A, and the pull-down reset is performed on the first pull-down node QB_A.
  • the second scanning unit 3 further includes: an eighth reset circuit 36 , a ninth reset circuit 37 and a tenth reset circuit 38 .
  • the eighth reset circuit 36 is electrically connected to the second pull-down node QB_B, the second pull-up node Q ⁇ 2> and the first voltage signal terminal V1.
  • the eighth reset circuit 36 is configured to transmit the first voltage signal to the second pull-up node Q ⁇ 2> under the control of the voltage of the second pull-down node QB_B.
  • the eighth reset circuit 36 may be turned on under the control of the voltage of the second pull-down node QB_B, and the eighth reset circuit 36 received at the first voltage signal terminal V1 A voltage signal is transmitted to the second pull-up node Q ⁇ 2> to perform a pull-down reset on the second pull-up node Q ⁇ 2>.
  • the ninth reset circuit 37 is electrically connected to the second pull-down node QB_B, the second scan signal terminal Oput1 ⁇ N+1> and the fourth voltage signal terminal V4 .
  • the ninth reset circuit 37 is configured to transmit the fourth voltage signal to the second scan signal terminal Oput1 ⁇ N+1> under the control of the voltage of the second pull-down node QB_B.
  • the ninth reset circuit 37 may be turned on under the control of the voltage of the second pull-down node QB_B, and the ninth reset circuit 37 received at the fourth voltage signal terminal V4
  • the four-voltage signal is transmitted to the second scanning signal terminal Oput1 ⁇ N+1>, and the second scanning signal terminal Oput1 ⁇ N+1> is pulled down to reset.
  • the ninth reset circuit 37 is also electrically connected to the second sensing signal terminal Oput2 ⁇ N+1>.
  • the ninth reset circuit 37 is further configured to transmit the fourth voltage signal to the second sensing signal terminal Oput2 ⁇ N+1> under the control of the voltage of the second pull-down node QB_B.
  • the ninth reset circuit 37 may be turned on under the control of the voltage of the second pull-down node QB_B, and the ninth reset circuit 37 received at the fourth voltage signal terminal V4
  • the four-voltage signal is transmitted to the second sensing signal terminal Oput2 ⁇ N+1>, and pull-down reset is performed on the second sensing signal terminal Oput2 ⁇ N+1>.
  • the ninth reset circuit 37 is also electrically connected to the second shift signal terminal CR2 ⁇ N+1> and the first voltage signal terminal V1.
  • the ninth reset circuit 37 is further configured to transmit the first voltage signal to the second shift signal terminal CR2 ⁇ N+1> under the control of the voltage of the second pull-down node QB_B.
  • the ninth reset circuit 37 may be turned on under the control of the voltage of the second pull-down node QB_B, and the ninth reset circuit 37 received at the first voltage signal terminal V1 A voltage signal is transmitted to the second shift signal terminal CR2 ⁇ N+1>, and pull-down reset is performed on the second shift signal terminal CR2 ⁇ N+1>.
  • the tenth reset circuit 38 is electrically connected to the first black insertion node M, the second control signal terminal BCS2 , the second pull-down node QB_B and the first voltage signal terminal V1 .
  • the tenth reset circuit 38 is configured to transmit the first voltage signal to the second pull-down node QB_B under the control of the voltage of the first black insertion node M and the second control signal.
  • the tenth reset circuit 38 can be set between the voltage of the first black insertion node M and the second control signal. Conducting under the control of the control signal, the first voltage signal received at the first voltage signal terminal V1 is transmitted to the second pull-down node QB_B, and the pull-down reset is performed on the second pull-down node QB_B.
  • the fifth reset circuit 16 includes: a twenty-seventh transistor M27.
  • control electrode of the twenty-seventh transistor M27 is electrically connected to the first pull-down node QB_A, and the first electrode of the twenty-seventh transistor M27 is connected to the first pull-up node Q ⁇ 1> Electrical connection, the second pole of the twenty-seventh transistor M27 is electrically connected to the first voltage signal terminal V1.
  • the twenty-seventh transistor M27 can be turned on under the control of the voltage of the first pull-down node QB_A, and receives and transmits the first voltage signal to the second A pull-up node Q ⁇ 1> is pulled down to reset the first pull-up node Q ⁇ 1>.
  • the sixth reset circuit 17 includes: a twenty-eighth transistor M28 , a twenty-ninth transistor M29 and a thirtieth transistor M30 .
  • control electrode of the twenty-eighth transistor M28 is electrically connected to the first pull-down node QB_A, and the first electrode of the twenty-eighth transistor M28 is connected to the first scan signal terminal Oput1 ⁇ N> is electrically connected, and the second pole of the twenty-eighth transistor M28 is electrically connected to the fourth voltage signal terminal V4.
  • the twenty-eighth transistor M28 can be turned on under the control of the voltage of the first pull-down node QB_A, and receives and transmits the fourth voltage signal to the second A scan signal terminal Oput1 ⁇ N> is used to pull down and reset the first scan signal terminal Oput1 ⁇ N>.
  • control electrode of the twenty-ninth transistor M29 is electrically connected to the first pull-down node QB_A, and the first electrode of the twenty-ninth transistor M29 is connected to the first sensing signal terminal Oput2 ⁇ N> is electrically connected, and the second pole of the twenty-ninth transistor M29 is electrically connected to the fourth voltage signal terminal V4.
  • the twenty-ninth transistor M29 can be turned on under the control of the voltage of the first pull-down node QB_A, and receives and transmits the fourth voltage signal to the second A sensing signal terminal Oput2 ⁇ N>, which pulls down and resets the first sensing signal terminal Oput2 ⁇ N>.
  • control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB_A, and the first electrode of the thirtieth transistor M30 is connected to the first shift signal terminal CR ⁇ N > Electrical connection, the second pole of the thirtieth transistor M30 is electrically connected to the first voltage signal terminal V1.
  • the thirtieth transistor M30 may be turned on under the control of the voltage of the first pull-down node QB_A to receive and transmit the first voltage signal to the first
  • the shift signal terminal CR ⁇ N> performs a pull-down reset on the first shift signal terminal CR ⁇ N>.
  • the seventh reset circuit 18 includes: a thirty-first transistor M31 and a thirty-second transistor M32 .
  • the control electrode of the thirty-first transistor M31 is electrically connected to the first black insertion node M, and the first electrode of the thirty-first transistor M31 is electrically connected to the first pull-down node QB_A. connected, the second pole of the thirty-first transistor M31 is electrically connected to the first pole of the thirty-second transistor M32.
  • the control electrode of the thirty-second transistor M32 is electrically connected to the second control signal terminal BCS2, and the second electrode of the thirty-second transistor M32 is electrically connected to the first voltage signal terminal V1.
  • the thirty-first transistor M31 can control the voltage of the first black node M. is turned on, the thirty-second transistor M32 can be turned on under the control of the second control signal.
  • the thirty-second transistor M32 can receive and transmit the first voltage signal to the second pole of the thirty-first transistor M31, and the thirty-first transistor M31 can transmit the first voltage signal to the first pull-down node QB_A, for the first Pull down node QB_A for pull down reset.
  • the eighth reset circuit 36 includes: a thirty-third transistor M33.
  • control electrode of the thirty-third transistor M33 is electrically connected to the second pull-down node QB_B, and the first electrode of the thirty-third transistor M33 is connected to the second pull-up node Q ⁇ 2 > Electrically connected, the second pole of the thirty-third transistor M33 is electrically connected to the first voltage signal terminal V1.
  • the thirty-third transistor M33 may be turned on under the control of the voltage of the second pull-down node QB_B to receive and transmit the first voltage signal to the second upper pull node Q ⁇ 2>, and perform pull-down reset on the second pull-up node Q ⁇ 2>.
  • the ninth reset circuit 37 includes: a thirty-fourth transistor M34 , a thirty-fifth transistor M35 and a thirty-sixth transistor M36 .
  • control electrode of the thirty-fourth transistor M34 is electrically connected to the second pull-down node QB_B, and the first electrode of the thirty-fourth transistor M34 is connected to the second scanning signal terminal Oput1 ⁇ N +1>electrically connected, the second pole of the thirty-fourth transistor M34 is electrically connected to the fourth voltage signal terminal V4.
  • the thirty-fourth transistor M34 may be turned on under the control of the voltage of the second pull-down node QB_B to receive and transmit the fourth voltage signal to the second scan
  • the signal terminal Oput1 ⁇ N+1> performs a pull-down reset on the second scanning signal terminal Oput1 ⁇ N+1>.
  • control electrode of the thirty-fifth transistor M35 is electrically connected to the second pull-down node QB_B, and the first electrode of the thirty-fifth transistor M35 is connected to the second sensing signal terminal Oput2 ⁇ N+1> is electrically connected, and the second pole of the thirty-fifth transistor M35 is electrically connected to the fourth voltage signal terminal V4.
  • the thirty-fifth transistor M35 may be turned on under the control of the voltage of the second pull-down node QB_B, and receive and transmit the fourth voltage signal to the second inductor.
  • the detection signal terminal Oput2 ⁇ N+1> is pulled down to reset the second sensing signal terminal Oput2 ⁇ N+1>.
  • control electrode of the thirty-sixth transistor M36 is electrically connected to the second pull-down node QB_B, and the first electrode of the thirty-sixth transistor M36 is connected to the second shift signal terminal CR2 ⁇ N+1> is electrically connected, and the second pole of the thirty-sixth transistor M36 is electrically connected to the first voltage signal terminal V1.
  • the thirty-sixth transistor M36 may be turned on under the control of the voltage of the second pull-down node QB_B, and receive and transmit the first voltage signal to the second shifter.
  • the bit signal terminal CR2 ⁇ N+1> performs a pull-down reset on the second shift signal terminal CR2 ⁇ N+1>.
  • the tenth reset circuit 38 includes: a thirty-seventh transistor M37 and a thirty-eighth transistor M38 .
  • the control electrode of the thirty-seventh transistor M37 is electrically connected to the first black insertion node M, and the first electrode of the thirty-seventh transistor M37 is electrically connected to the second pull-down node QB_B , the second pole of the thirty-seventh transistor M37 is electrically connected to the first pole of the thirty-eighth transistor M38.
  • the control electrode of the thirty-eighth transistor M38 is electrically connected to the second control signal terminal BCS2, and the second electrode of the thirty-eighth transistor M38 is electrically connected to the first voltage signal terminal V1.
  • the thirty-seventh transistor M37 can control the voltage of the first black node M. is turned on, the thirty-eighth transistor M38 can be turned on under the control of the second control signal.
  • the thirty-eighth transistor M38 can receive and transmit the first voltage signal to the second pole of the thirty-seventh transistor M37, and the thirty-seventh transistor M37 can transmit the first voltage signal to the second pull-down node QB_B for the second pull-down Node QB_B performs a pull-down reset.
  • the shift register 100 can also include other circuit structures, which can be selected and set according to actual needs.
  • the fifth reset circuit 16 is also electrically connected to the second pull-down node QB_B. Wherein, the fifth reset circuit 16 is further configured to transmit the first voltage signal to the first pull-up node Q ⁇ 1> under the control of the voltage of the second pull-down node QB_B.
  • the fifth reset circuit 16 may be turned on under the control of the voltage of the second pull-down node QB_B, and the fifth reset circuit 16 received at the first voltage signal terminal V1 A voltage signal is transmitted to the first pull-up node Q ⁇ 1> to perform a pull-down reset on the first pull-up node Q ⁇ 1>.
  • the sixth reset circuit 17 is also electrically connected to the second pull-down node QB_B. Wherein, the sixth reset circuit 17 is further configured to, under the control of the voltage of the second pull-down node QB_B, transmit the fourth voltage signal to the first scanning signal terminal Oput1 ⁇ N>, and transmit the fourth voltage signal to the first scanning signal terminal Oput1 ⁇ N>.
  • the sensing signal terminal Oput2 ⁇ N> transmits the first voltage signal to the first shift signal terminal CR ⁇ N>.
  • the sixth reset circuit 17 may be turned on under the control of the voltage of the second pull-down node QB_B, and receive and transmit the fourth voltage signal to the first scan signal Terminal Oput1 ⁇ N>, pull down and reset the first scanning signal terminal Oput1 ⁇ N>; receive and transmit the fourth voltage signal to the first sensing signal terminal Oput2 ⁇ N>, and reset the first sensing signal terminal Oput2 ⁇ N> Perform pull-down reset; receive and transmit the first voltage signal to the first shift signal terminal CR ⁇ N>, and perform pull-down reset on the first shift signal terminal CR ⁇ N>.
  • the eighth reset circuit 36 is also electrically connected to the first pull-down node QB_A. Wherein, the eighth reset circuit 36 is further configured to transmit the first voltage signal to the second pull-up node Q ⁇ 2> under the control of the voltage of the first pull-down node QB_A.
  • the eighth reset circuit 36 may be turned on under the control of the voltage of the first pull-down node QB_A, and will receive The first voltage signal of the second pull-up node Q ⁇ 2> is transmitted to the second pull-up node Q ⁇ 2>, and pull-down reset is performed on the second pull-up node Q ⁇ 2>.
  • the ninth reset circuit 37 is also electrically connected to the first pull-down node QB_A. Wherein, the ninth reset circuit 37 is further configured to, under the control of the voltage of the first pull-down node QB_A, transmit the fourth voltage signal to the second scanning signal terminal Oput1 ⁇ N+1>, and transmit the fourth voltage signal to to the second sensing signal terminal Oput2 ⁇ N+1>, and transmit the first voltage signal to the second shift signal terminal CR2 ⁇ N+1>.
  • the ninth reset circuit 37 may be turned on under the control of the voltage of the first pull-down node QB_A, and receive and transmit the fourth voltage signal to the second
  • the scanning signal terminal Oput1 ⁇ N+1> pulls down and resets the second scanning signal terminal Oput1 ⁇ N+1>; receives and transmits the fourth voltage signal to the second sensing signal terminal Oput2 ⁇ N+1>, and resets the second scanning signal terminal Oput2 ⁇ N+1>.
  • the sensing signal terminal Oput2 ⁇ N+1> performs pull-down reset; receives and transmits the first voltage signal to the second shift signal terminal CR2 ⁇ N+1>, and pulls down the second shift signal terminal CR2 ⁇ N+1> reset.
  • the second voltage signal and the third voltage signal may be mutually inverse signals, for example.
  • different structures in different reset circuits can be used to reset the first pull-down node QB_A or the second pull-down node QB_B, reducing the working hours of the corresponding structures, and improving the efficiency of the shift register 100 and the scan driving circuit 1000. service life.
  • the fifth reset circuit 16 further includes: a thirty-ninth transistor M39.
  • control electrode of the thirty-ninth transistor M39 is electrically connected to the second pull-down node QB_B, and the first electrode of the thirty-ninth transistor M39 is electrically connected to the first pull-up node Q ⁇ 1> , the second pole of the thirty-ninth transistor M39 is electrically connected to the first voltage signal terminal V1.
  • the thirty-ninth transistor M39 may be turned on under the control of the voltage of the second pull-down node QB_B to receive and transmit the first voltage signal to the first upper Pull the node Q ⁇ 1>, and perform a pull-down reset on the first pull-up node Q ⁇ 1>.
  • the sixth reset circuit 17 further includes: a fortieth transistor M40 , a forty-first transistor M41 and a forty-second transistor M42 .
  • control electrode of the fortieth transistor M40 is electrically connected to the second pull-down node QB_B, the first electrode of the fortieth transistor M40 is electrically connected to the first scan signal terminal Oput1 ⁇ N>, and the first electrode of the fortieth transistor M40 is electrically connected to the first scanning signal terminal Oput1 ⁇ N>.
  • the second pole of the forty transistor M40 is electrically connected to the fourth voltage signal terminal V4.
  • the fortieth transistor M40 may be turned on under the control of the voltage of the second pull-down node QB_B to receive and transmit the fourth voltage signal to the first scan signal
  • the terminal Oput1 ⁇ N> performs a pull-down reset on the first scanning signal terminal Oput1 ⁇ N>.
  • control electrode of the forty-first transistor M41 is electrically connected to the second pull-down node QB_B, and the first electrode of the forty-first transistor M41 is electrically connected to the first sensing signal terminal Oput2 ⁇ N>. connected, the second pole of the forty-first transistor M41 is electrically connected to the fourth voltage signal terminal V4.
  • the forty-first transistor M41 may be turned on under the control of the voltage of the second pull-down node QB_B, and receive and transmit the fourth voltage signal to the first inductor.
  • the detection signal terminal Oput2 ⁇ N> is pulled down to reset the first sensing signal terminal Oput2 ⁇ N>.
  • control electrode of the forty-second transistor M42 is electrically connected to the second pull-down node QB_B, and the first electrode of the forty-second transistor M42 is electrically connected to the first shift signal terminal CR ⁇ N>. connected, the second pole of the forty-second transistor M42 is electrically connected to the first voltage signal terminal V1.
  • the forty-second transistor M42 may be turned on under the control of the voltage of the second pull-down node QB_B, and receive and transmit the first voltage signal to the first shifter.
  • the bit signal terminal CR ⁇ N> performs a pull-down reset on the first shift signal terminal CR ⁇ N>.
  • the eighth reset circuit 36 further includes: a forty-third transistor M43.
  • control electrode of the forty-third transistor M43 is electrically connected to the first pull-down node QB_A, and the first electrode of the forty-third transistor M43 is electrically connected to the second pull-up node Q ⁇ 2>. connected, the second pole of the forty-third transistor M43 is electrically connected to the first voltage signal terminal V1.
  • the forty-third transistor M43 may be turned on under the control of the voltage of the first pull-down node QB_A, and receive and transmit the first voltage signal to the second The second pull-up node Q ⁇ 2> is pulled down to reset the second pull-up node Q ⁇ 2>.
  • the ninth reset circuit 37 further includes: a forty-fourth transistor M44 , a forty-fifth transistor M45 and a forty-sixth transistor M46 .
  • control electrode of the forty-fourth transistor M44 is electrically connected to the first pull-down node QB_A, and the first electrode of the forty-fourth transistor M44 is connected to the second scanning signal terminal Oput1 ⁇ N+1 > Electrical connection, the second pole of the forty-fourth transistor M44 is electrically connected to the fourth voltage signal terminal V4.
  • the forty-fourth transistor M44 may be turned on under the control of the voltage of the first pull-down node QB_A to receive and transmit the fourth voltage signal to the first
  • the second scanning signal terminal Oput1 ⁇ N+1> is pulled down to reset the second scanning signal terminal Oput1 ⁇ N+1>.
  • control electrode of the forty-fifth transistor M45 is electrically connected to the first pull-down node QB_A, and the first electrode of the forty-fifth transistor M45 is connected to the second sensing signal terminal Oput2 ⁇ N+ 1> electrical connection, the second pole of the forty-fifth transistor M45 is electrically connected to the fourth voltage signal terminal V4.
  • the forty-fifth transistor M45 may be turned on under the control of the voltage of the first pull-down node QB_A, and receive and transmit the fourth voltage signal to the first The second sensing signal terminal Oput2 ⁇ N+1> is pulled down to reset the second sensing signal terminal Oput2 ⁇ N+1>.
  • control electrode of the forty-sixth transistor M46 is electrically connected to the first pull-down node QB_A, and the first electrode of the forty-sixth transistor M46 is connected to the second shift signal terminal CR2 ⁇ N+ 1> electrical connection, the second pole of the forty-sixth transistor M46 is electrically connected to the first voltage signal terminal V1.
  • the forty-sixth transistor M46 may be turned on under the control of the voltage of the first pull-down node QB_A, and receive and transmit the first voltage signal to the second
  • the second shift signal terminal CR2 ⁇ N+1> performs a pull-down reset on the second shift signal terminal CR2 ⁇ N+1>.
  • the display phase of one frame may include, for example, a display period and a blanking period that are performed sequentially.
  • the shift register 100 can drive the corresponding sub-pixels P in the display device 2000 for image display; during the blanking period, the shift register 100 can drive the corresponding sub-pixels P in the display device 2000 for external compensation.
  • the shift register 100 may further include: a blanking circuit 4 .
  • the blanking circuit 4 is connected to the third control signal terminal OE, the display input signal terminal Iput, the seventh clock signal terminal CLKA, the first pull-up node Q ⁇ 1> and the first pull-up node Q ⁇ 1>.
  • a voltage signal terminal V1 is electrically connected.
  • the blanking circuit 4 is configured to, under the control of the third control signal transmitted by the third control signal terminal OE, the display input signal and the seventh clock signal transmitted by the seventh clock signal terminal The signal is transmitted to the first pull-up node Q ⁇ 1>.
  • the blanking circuit 4 is also electrically connected to the second pull-up node Q ⁇ 2>.
  • the blanking circuit 4 is further configured to transmit the seventh clock signal to the second pull-up node Q ⁇ 2>.
  • the blanking circuit 4 can be turned on under the control of the third control signal, the display input signal and the seventh clock signal, and transmit the seventh clock signal received at the seventh clock signal terminal CLKA to the first pull-up node Q ⁇ 1> and the second pull-up node Q ⁇ 2> charge the first pull-up node Q ⁇ 1> and the second pull-up node Q ⁇ 2>.
  • the first output circuit 12 can be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>. If the first output circuit 12 is not electrically connected to the first sensing signal terminal Oput2 ⁇ N>, the first output circuit 12 can simultaneously use the second clock signal received at the first clock signal terminal CLKE1 as the first scanning signal and The first sensing driving signal is output from the first scanning signal terminal Oput1 ⁇ N>. If the first output circuit 12 is electrically connected to the first sensing signal terminal Oput2 ⁇ N>, the first output circuit 12 can use the third clock signal received at the third clock signal terminal CLKF1 as the first sensing signal, from The first sensing signal terminal Oput2 ⁇ N> is output. The first sensing signal can be used to drive the corresponding sub-pixel P for external compensation.
  • the second output circuit 32 can be turned on under the control of the voltage of the second pull-up node Q ⁇ 2>. If the second output circuit 32 is not electrically connected to the second sensing signal terminal Oput2 ⁇ N+1>, the second output circuit 32 can simultaneously use the second clock signal received at the second clock signal terminal CLKE2 as the second scanning signal and the second sensing driving signal are output from the second scanning signal terminal Oput1 ⁇ N+1>.
  • the second output circuit 32 can use the fourth clock signal received at the fourth clock signal terminal CLKF2 as the second sensing signal , output from the second sensing signal terminal Oput2 ⁇ N+1>.
  • the second sensing signal can be used to drive the corresponding sub-pixel P for external compensation.
  • the shift register 100 when the shift register 100 includes the second scanning unit 3 , the first scanning unit 1 and the second scanning unit 3 can share the blanking circuit 4 . This is beneficial to simplify the structures of the shift register 100 and the scan driving circuit 1000 , and improve the yield of the shift register 100 and the scan driving circuit 1000 .
  • the blanking circuit 4 may also include other blanking transmission sub-circuits, so that multiple scanning units can share the blanking circuit 4 .
  • the blanking circuit 4 includes: a selection control subcircuit 41, a blanking input subcircuit 42, a first blanking transmission subcircuit 43 and a second blanking transmission subcircuit 44.
  • the selection control subcircuit 41 is electrically connected to the third control signal terminal OE, the display input signal terminal Iput, the first blanking node H and the first voltage signal terminal V1. Wherein, the selection control subcircuit 41 is configured to transmit the display input signal to the first blanking node H under the control of the third control signal.
  • the selection control subcircuit 41 can be turned on under the control of the third control signal, and transmit the received display input signal to the first
  • the blanking node H charges the first blanking node H, so that the voltage of the first blanking node H increases.
  • the waveform timing of the third control signal can be made the same as the waveform timing of the display input signal, and then the selection control sub-circuit 41 can be turned on.
  • the blanking transmission sub-circuit 42 is electrically connected to the first blanking node H, the seventh clock signal terminal CLKA and the second blanking node N. Wherein, the blanking transmission sub-circuit 42 is configured to transmit the seventh clock signal to the second blanking node N under the control of the voltage of the first blanking node H.
  • the blanking transmission subcircuit 42 may be turned on under the control of the voltage of the first blanking node H, receiving The seventh clock signal transmitted by the seventh clock signal terminal CLKA, and transmit the seventh clock signal to the second blanking node N.
  • the first blanking transmission sub-circuit 43 is electrically connected to the seventh clock signal terminal CLKA, the second blanking node N, and the first pull-up node Q ⁇ 1>.
  • the first blanking transmission sub-circuit 43 is configured to transmit the seventh clock signal from the second blanking node N to the first pull-up node Q ⁇ 1> under the control of the seventh clock signal.
  • the first blanking transmission sub-circuit 43 may be turned on under the control of the seventh clock signal, and transmit from the second blanking node N Receive the seventh clock signal, transmit the received seventh clock signal to the first pull-up node Q ⁇ 1>, and charge the first pull-up node Q ⁇ 1>, so that the first pull-up node Q ⁇ 1> The voltage rises.
  • the second blanking transmission sub-circuit 44 is electrically connected to the seventh clock signal terminal CLKA, the second blanking node N, and the second pull-up node Q ⁇ 2>.
  • the second blanking transmission sub-circuit 44 is configured to transmit the seventh clock signal from the second blanking node N to the second pull-up node Q ⁇ 2> under the control of the seventh clock signal.
  • the second blanking transmission sub-circuit 44 may be turned on under the control of the seventh clock signal, and transmit Receive the seventh clock signal, transmit the received seventh clock signal to the second pull-up node Q ⁇ 2>, and charge the second pull-up node Q ⁇ 2>, so that the second pull-up node Q ⁇ 2> The voltage rises.
  • the structure of the selection control subcircuit 41, the blanking input subcircuit 42, the first blanking transmission subcircuit 43 and the second blanking transmission subcircuit 44 included in the blanking circuit 4 will be schematically described below in conjunction with the accompanying drawings.
  • the selection control subcircuit 41 includes: a forty-seventh transistor M47 and a sixth capacitor C6.
  • control pole of the forty-seventh transistor M47 is electrically connected to the third control signal terminal OE, and the first pole of the forty-seventh transistor M47 is electrically connected to the Iput display input signal terminal. , the second pole of the forty-seventh transistor M47 is electrically connected to the first blanking node H.
  • the forty-seventh transistor M47 can be turned on under the action of the selection control signal to receive and transmit the display input signal to the first A blanking node H charges the first blanking node H, so that the voltage of the first blanking node H increases.
  • the first terminal of the sixth capacitor C6 is electrically connected to the first blanking node H, and the second terminal of the sixth capacitor C6 is electrically connected to the first voltage signal terminal V1 .
  • the sixth capacitor C6 when the forty-seventh transistor M47 is turned on and charges the first blanking node H, the sixth capacitor C6 will also be charged. In this way, when the forty-seventh transistor M47 is turned off, the sixth capacitor C6 can be used to discharge, so that the first blanking node H remains at a high level.
  • the blanking input subcircuit 42 includes a forty-eighth transistor M48 .
  • control electrode of the forty-eighth transistor M48 is electrically connected to the first blanking node H, and the first electrode of the forty-eighth transistor M48 is electrically connected to the seventh clock signal terminal CLKA.
  • the second electrode of the forty-eighth transistor M48 is electrically connected to the second blanking node N.
  • the forty-eighth transistor M48 may be turned on under the control of the voltage of the first blanking node H, and will be at the seventh clock signal terminal CLKA The received seventh clock signal is transmitted to the second blanking node N.
  • the first blanking transmission sub-circuit 43 includes: a forty-ninth transistor M49.
  • the control electrode of the forty-ninth transistor M49 is electrically connected to the seventh clock signal terminal CLKA, and the first electrode of the forty-ninth transistor M49 is electrically connected to the second blanking node N. connected, the second pole of the forty-ninth transistor M49 is electrically connected to the first pull-up node Q ⁇ 1>.
  • the forty-ninth transistor M49 may be turned on under the action of the seventh clock signal to receive and transmit Second, blank the seventh clock signal of the node N to the first pull-up node Q ⁇ 1> to charge the first pull-up node Q ⁇ 1>.
  • the second blanking transmission sub-circuit 44 includes: a fiftieth transistor M50 .
  • the control electrode of the fiftieth transistor M50 is electrically connected to the seventh clock signal terminal CLKA, and the first electrode of the fiftieth transistor M50 is electrically connected to the second blanking node N, The second pole of the fiftieth transistor M50 is electrically connected to the second pull-up node Q ⁇ 2>.
  • the fiftieth transistor M50 may be turned on under the action of the seventh clock signal to receive and transmit the seventh clock signal from the second blanking node N to the second pull-up node Q ⁇ 2>, and charge the second pull-up node Q ⁇ 2>.
  • the first scanning unit 1 further includes: an eleventh reset circuit 19, a twelfth reset circuit 110, and a thirteenth reset circuit 111
  • the second scanning unit 3 further includes: a fourteenth reset circuit 39 , a fifteenth reset circuit 310 and a sixteenth reset circuit 311 .
  • the eleventh reset circuit 19 is electrically connected to the global reset signal terminal TRST, the first pull-up node Q ⁇ 1> and the first voltage signal terminal V1. Wherein, the eleventh reset circuit 19 is configured to transmit the first voltage signal to the first pull-up node Q ⁇ 1> under the control of the global reset signal transmitted by the global reset signal terminal TRST.
  • the eleventh reset circuit 19 can be turned on under the effect of the global reset signal, and the first voltage signal transmitted by the first voltage signal terminal V1 It is transmitted to the first pull-up node Q ⁇ 1>, and the pull-down reset is performed on the first pull-up node Q ⁇ 1>.
  • the twelfth reset circuit 110 is electrically connected to the display input signal terminal Iput, the first pull-down node QB_A and the first voltage signal terminal V1. Wherein, the twelfth reset circuit 110 is configured to transmit the first voltage signal to the first pull-down node QB_A under the control of the display input signal.
  • the twelfth reset circuit 110 may be turned on under the action of the input signal, and transmit the first voltage signal to the first pull-down node QB_A.
  • the first pull-down node QB_A performs a pull-down reset.
  • the thirteenth reset circuit 111 is connected to the first blanking node H, the seventh clock signal terminal CLKA, The first pull-down node QB_A is electrically connected to the first voltage signal terminal V1.
  • the thirteenth reset circuit 111 is configured to transmit the first voltage signal to the first pull-down node QB_A under the control of the voltage of the first blanking node H and the seventh clock signal.
  • the thirteenth reset circuit 111 may and the seventh clock signal are turned on, the first voltage signal is transmitted to the first pull-down node QB_A, and the pull-down reset is performed on the first pull-down node QB_A.
  • the fourteenth reset circuit 39 is connected to the global reset signal terminal TRST, the second pull-up node Q ⁇ 2> and the first voltage signal terminal V1. Wherein, the fourteenth reset circuit 39 is configured to transmit the first voltage signal to the second pull-up node Q ⁇ 2> under the control of the global reset signal.
  • the fourteenth reset circuit 39 can be turned on under the effect of the global reset signal, and the first voltage signal transmitted by the first voltage signal terminal V1
  • the second pull-up node Q ⁇ 2> is transmitted to the second pull-up node Q ⁇ 2>, and the second pull-up node Q ⁇ 2> is pulled down to reset.
  • the fifteenth reset circuit 310 is electrically connected to the display input signal terminal Iput, the second pull-down node QB_B and the first voltage signal terminal V1. Wherein, the fifteenth reset circuit 310 is configured to transmit the first voltage signal to the second pull-down node QB_B under the control of the display input signal.
  • the fifteenth reset circuit 310 may be turned on under the action of the input signal, and transmit the first voltage signal to the first pull-down node QB_A.
  • the first pull-down node QB_A performs a pull-down reset.
  • the sixteenth reset circuit 311 is electrically connected to the first blanking node H, the seventh clock signal terminal CLKA, the second pull-down node QB_B and the first voltage signal terminal V1. Wherein, the sixteenth reset circuit 311 is configured to transmit the first voltage signal to the second pull-down node QB_B under the control of the voltage of the first blanking node H and the seventh clock signal.
  • the sixteenth reset circuit 311 can set the voltage of the first blanking node H to and the seventh clock signal are turned on, the first voltage signal is transmitted to the second pull-down node QB_B, and the pull-down reset is performed on the second pull-down node QB_B.
  • the eleventh reset circuit 19 includes: a fifty-first transistor M51.
  • control electrode of the fifty-first transistor M51 is electrically connected to the global reset signal terminal TRST, and the first electrode of the fifty-first transistor M51 is connected to the first pull-up node Q ⁇ 1 > Electrically connected, the second pole of the fifty-first transistor M51 is electrically connected to the first voltage signal terminal V1.
  • the fifty-first transistor M51 may be turned on under the effect of the global reset signal, and transmit the first voltage signal transmitted by the first voltage signal terminal V1 to The first pull-up node Q ⁇ 1> resets the first pull-up node Q ⁇ 1>.
  • the twelfth reset circuit 110 includes: a fifty-second transistor M52.
  • the control electrode of the fifty-second transistor M52 is electrically connected to the display input signal terminal Iput, and the first electrode of the fifty-second transistor M52 is electrically connected to the first pull-down node QB_A. , the second pole of the fifty-second transistor M52 is electrically connected to the first voltage signal terminal V1.
  • the fifty-second transistor M52 may be turned on under the action of the input signal, and transmit the first voltage signal to the first pull-down node QB_A.
  • the first pull-down node QB_A performs a pull-down reset.
  • the thirteenth reset circuit 111 includes: a fifty-third transistor M53 and a fifty-fourth transistor M54 .
  • the control electrode of the fifty-third transistor M53 is electrically connected to the first blanking node H, and the first electrode of the fifty-third transistor M53 is electrically connected to the first pull-down node QB_A. connected, the second pole of the fifty-third transistor M53 is electrically connected to the first pole of the fifty-fourth transistor M54.
  • the control electrode of the fifty-fourth transistor M54 is electrically connected to the seventh clock signal terminal CLKA, and the second electrode of the fifty-fourth transistor M54 is electrically connected to the first voltage signal terminal V1.
  • the fifty-third transistor M53 may function under the voltage of the first blanking node H is turned on, the fifty-fourth transistor M54 can be turned on under the action of the seventh clock signal.
  • the fifty-fourth transistor M54 can receive and transmit the first voltage signal to the second pole of the fifty-third transistor M53.
  • the fifty-third transistor M53 can receive and transmit the first voltage signal to the first pull-down node QB_A, and perform a pull-down reset on the first pull-down node QB_A.
  • the fourteenth reset circuit 39 includes: a fifty-fifth transistor M55.
  • control electrode of the fifty-fifth transistor M55 is electrically connected to the global reset signal terminal TRST, and the first electrode of the fifty-fifth transistor M55 is connected to the second pull-up node Q ⁇ 2 > Electrically connected, the second pole of the fifty-fifth transistor M55 is electrically connected to the first voltage signal terminal V1.
  • the fifty-fifth transistor M55 may be turned on under the action of the global reset signal, and transmit the first voltage signal transmitted by the first voltage signal terminal V1 to The second pull-up node Q ⁇ 2> resets the second pull-up node Q ⁇ 2>.
  • the fifteenth reset circuit 310 includes: a fifty-sixth transistor M56.
  • control electrode of the fifty-sixth transistor M56 is electrically connected to the display input signal terminal Iput, and the first electrode of the fifty-sixth transistor M56 is electrically connected to the second pull-down node QB_B, The second pole of the fifty-sixth transistor M56 is electrically connected to the first voltage signal terminal V1.
  • the fifty-sixth transistor M56 may be turned on under the action of the input signal, and transmit the first voltage signal to the first pull-down node QB_A.
  • the first pull-down node QB_A performs a pull-down reset.
  • the sixteenth reset circuit 311 includes: a fifty-seventh transistor M57 and a fifty-eighth transistor M58 .
  • the control electrode of the fifty-seventh transistor M57 is electrically connected to the first blanking node H, and the first electrode of the fifty-seventh transistor M57 is electrically connected to the second pull-down node QB_B , the second pole of the fifty-seventh transistor M57 is electrically connected to the first pole of the fifty-eighth transistor M58.
  • the control electrode of the fifty-eighth transistor M58 is electrically connected to the seventh clock signal terminal CLKA, and the second electrode of the fifty-eighth transistor M58 is electrically connected to the first voltage signal terminal V1.
  • the fifty-seventh transistor M57 can be activated by the voltage of the first blanking node H. is turned on, the fifty-eighth transistor M58 can be turned on under the action of the seventh clock signal.
  • the fifty-eighth transistor M58 can receive and transmit the first voltage signal to the second electrode of the fifty-seventh transistor M57.
  • the fifty-seventh transistor M57 can receive and transmit the first voltage signal to the second pull-down node QB_B, and perform a pull-down reset on the second pull-down node QB_B.
  • the shift register 100 further includes: a first anti-leakage circuit 5 .
  • the first anti-leakage circuit 5 is electrically connected to the first blanking node H, the fifth voltage signal terminal V5 and the first anti-leakage node OFF1. Wherein, the first anti-leakage circuit 5 is configured to transmit the fifth voltage signal received at the fifth voltage signal terminal V5 to the first anti-leakage node OFF1 under the control of the voltage of the first blanking node H.
  • the first anti-leakage circuit 5 may be turned on under the control of the voltage of the first blanking node H, and receive and transmit the fifth voltage signal To the first anti-leakage node OFF1, the first anti-leakage node OFF1 is charged, so that the voltage of the first anti-leakage node OFF1 increases.
  • the selection control subcircuit 41 is also electrically connected to the first anti-leakage node OFF1 .
  • the first anti-leakage circuit 5 includes: a fifty-ninth transistor M59.
  • control electrode of the fifty-ninth transistor M59 is electrically connected to the first blanking node H, and the first electrode of the fifty-ninth transistor M59 is electrically connected to the fifth voltage signal terminal V5.
  • the second pole of the fifty-ninth transistor M59 is electrically connected to the first anti-leakage node OFF1.
  • the fifty-ninth transistor M59 may be turned on under the control of the voltage of the first blanking node H, receive the fifth voltage signal, and turn on the fifth voltage signal.
  • the five-voltage signal is transmitted to the first anti-leakage node OFF1 to charge the first anti-leakage node OFF1 so that the voltage of the first anti-leakage node OFF1 increases.
  • the selection control subcircuit 41 may further include: a sixtieth transistor M60.
  • the control electrode of the sixtieth transistor M60 is electrically connected to the third control signal terminal OE
  • the first electrode of the sixtieth transistor M60 is electrically connected to the display input signal terminal Iput
  • the sixtieth transistor M60 is electrically connected to the display input signal terminal Iput.
  • the second pole of M60 is electrically connected to the first anti-leakage node OFF1.
  • the first electrode of the forty-seventh transistor M47 in the selection control sub-circuit 41 is electrically connected to the first anti-leakage node OFF1, and is electrically connected to the display input signal terminal Iput through the above-mentioned sixtieth transistor M60.
  • the forty-seventh transistor M47 and the sixtieth transistor M60 may be turned on simultaneously under the action of the third control signal.
  • the sixtieth transistor M60 can receive and transmit the display input signal to the first anti-leakage node OFF1
  • the forty-seventh transistor M47 can receive and transmit the display input signal to the first blanking node H, and charge the first blanking node H .
  • the forty-seventh transistor M47 and the sixtieth transistor M60 can be turned off simultaneously under the action of the third control signal.
  • the sixth capacitor C6 in the selection control sub-circuit 41 starts to discharge, so that the voltage of the first blanking node H remains at a high level.
  • the fifty-ninth transistor M59 in the first anti-leakage circuit 5 can transmit the fifth voltage signal to the first anti-leakage node OFF1 to charge the first anti-leakage node OFF1 to reduce the first anti-leakage node OFF1 and the first blanking node H, and make the voltage difference between the control electrode of the forty-seventh transistor M47 and the first electrode less than zero, to ensure that the forty-seventh transistor M47 is completely or relatively completely cut off. This can prevent the first blanking node H from leaking electricity through the selection control sub-circuit 41, so that the first blanking node H can be kept at a higher and more stable voltage.
  • the shift register 100 can also include other circuit structures, which can be selected and set according to actual needs.
  • the shift register 100 further includes: a second anti-leakage circuit 7 .
  • the second anti-leakage circuit 7 is connected to the first pull-up node Q ⁇ 1>, the fifth voltage signal terminal V5 and the second anti-leakage node OFF2 electrical connection.
  • the second anti-leakage circuit 7 is configured to transmit the fifth voltage signal received at the fifth voltage signal terminal V5 to the second anti-leakage node under the control of the voltage of the first pull-up node Q ⁇ 1> OFF2.
  • the second anti-leakage circuit 7 may be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, receiving And transmit the fifth voltage signal to the second anti-leakage node OFF2 to charge the second anti-leakage node OFF2 so that the voltage of the second anti-leakage node OFF2 increases.
  • the second anti-leakage circuit 7 includes: a sixty-first transistor M61.
  • the control electrode of the sixty-first transistor M61 is electrically connected to the first pull-up node Q ⁇ 1>, and the first pull-up node of the sixty-first transistor M61
  • the pole is electrically connected to the fifth voltage signal terminal V5, and the second pole of the sixty-first transistor M61 is electrically connected to the second anti-leakage node OFF2.
  • the sixty-first transistor M61 may be turned on under the control of the voltage of the first pull-up node Q ⁇ 1>, receiving the fifth voltage signal, and transmit the fifth voltage signal to the second anti-leakage node OFF2 to charge the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 increases.
  • circuits included in the shift register 100 may also be electrically connected to the second anti-leakage node OFF2.
  • the first input circuit 11 may also be electrically connected to the second anti-leakage node OFF2 .
  • the first input circuit 11 When the first input circuit 11 is turned off and the first capacitor C1 in the first output circuit 12 is discharged so that the voltage of the first pull-up node Q ⁇ 1> remains at a high level, the first input circuit 11 is electrically connected to the second anti-leakage node OFF2, which can reduce the voltage difference between the second anti-leakage node OFF2 and the first pull-up node Q ⁇ 1>, and prevent the first pull-up node Q ⁇ 1> from passing through the first input
  • the electric leakage of the circuit 11 can further keep the first pull-up node Q ⁇ 1> at a higher and more stable voltage, so as to avoid affecting the conduction state of the first output circuit 12 .
  • the first input circuit 11 further includes: a sixty-second transistor M62.
  • the control pole of the sixty-second transistor M62 is electrically connected to the display input signal terminal Iput, and the first pole of the sixty-second transistor M62 is connected to the display input signal terminal Iput.
  • the signal terminal Iput is electrically connected, and the second pole of the sixty-second transistor M62 is electrically connected to the second anti-leakage node OFF2.
  • the first pole of the first transistor M1 is electrically connected to the second anti-leakage node OFF2, and is electrically connected to the display input signal terminal Iput through the sixty-second transistor M62.
  • the first transistor M1 and the sixty-second transistor M62 may be turned on simultaneously under the effect of the display input signal.
  • the sixty-second transistor M62 can receive and transmit the display input signal to the second anti-leakage node OFF2, the first transistor M1 can receive and transmit the display input signal to the first pull-up node Q ⁇ 1>, and the first pull-up node Q ⁇ 1> ⁇ 1> to charge.
  • the first transistor M1 and the sixty-second transistor M62 can be turned off simultaneously under the effect of the display input signal.
  • the first capacitor C1 in the first output circuit 12 starts to discharge, so that the voltage of the first pull-up node Q ⁇ 1> remains at a high level.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2 to charge the second anti-leakage node OFF2 to reduce the second anti-leakage voltage.
  • the shift register 100 when the shift register 100 also includes a second scanning unit 3 , the second input circuit 31 is also connected to the second anti-leakage node OFF2 electrical connection.
  • the second input circuit 31 When the second input circuit 31 is turned off and the second capacitor C2 in the second output circuit 32 is discharged so that the voltage of the second pull-up node Q ⁇ 2> is kept at a high level, by setting the second input circuit 31 is electrically connected to the second anti-leakage node OFF2, which can reduce the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and prevent the second pull-up node Q ⁇ 2> from passing through the second input
  • the electric leakage of the circuit 31 can further keep the second pull-up node Q ⁇ 2> at a higher and more stable voltage, so as to avoid affecting the conduction state of the second output circuit 32 .
  • the first pole of the third transistor M3 in the second input circuit 31 is electrically connected to the second leakage prevention node OFF2, and passes The sixty-second transistor M62 is electrically connected to the display input signal terminal Iput.
  • the third transistor M3 and the sixty-second transistor M62 may be turned on simultaneously under the effect of the display input signal.
  • the sixty-second transistor M62 can receive and transmit the display input signal to the second anti-leakage node OFF2, the third transistor M3 can receive and transmit the display input signal to the second pull-up node Q ⁇ 2>, and the second pull-up node Q ⁇ 2> ⁇ 2> to charge.
  • the third transistor M3 and the sixty-second transistor M62 can be turned off simultaneously under the action of the display input signal.
  • the second capacitor C2 in the second output circuit 32 starts to discharge, so that the voltage of the second pull-up node Q ⁇ 2> remains at a high level.
  • the voltage of the first pull-up node Q ⁇ 1> remains at a high level state, and the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, charge the second anti-leakage node OFF2, reduce the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and make the control electrode of the third transistor M3 and the first electrode The voltage difference between them is less than zero, ensuring that the third transistor M3 is completely or relatively completely turned off. This can prevent the second pull-up node Q ⁇ 2 > from leaking electricity through the second input circuit 31 , so that the second pull-up node Q ⁇ 2 > can maintain a higher and more stable voltage.
  • the second input circuit 31 shares the sixty-second transistor M62 in the first input circuit 11 , which is beneficial to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100 .
  • the black insertion circuit 2 is also electrically connected to the second anti-leakage node OFF2 .
  • the black insertion circuit 2 when the black insertion circuit 2 includes the first black insertion transmission sub-circuit 23, the first black insertion transmission sub-circuit 23 also Including: the sixty-third transistor M63.
  • the control electrode of the sixty-third transistor M63 is electrically connected to the second control signal terminal BCS2, and the first electrode of the sixty-third transistor M63 is electrically connected to the second control signal terminal BCS2.
  • the two-plug black node K is electrically connected, and the second pole of the sixty-third transistor M63 is electrically connected to the second anti-leakage node OFF2.
  • the first pole of the seventh transistor M7 in the first black insertion transmission sub-circuit 23 is electrically connected to the second anti-leakage node OFF2, and is electrically connected to the second black insertion node K through the sixty-third transistor M63.
  • the seventh transistor M7 and the sixty-third transistor M63 may be turned on simultaneously under the action of the second control signal.
  • the sixty-third transistor M63 can receive the black insertion input signal from the second black insertion node K, and send the black insertion input signal to the second anti-leakage node OFF2, and the seventh transistor M7 can receive and transmit the black insertion input signal to the second A pull-up node Q ⁇ 1> charges the first pull-up node Q ⁇ 1>.
  • the seventh transistor M7 and the sixty-third transistor M63 can be turned off simultaneously under the action of the second control signal.
  • the first capacitor C1 in the first output circuit 12 starts to discharge, so that the voltage of the first pull-up node Q ⁇ 1> remains at a high level.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2 to charge the second anti-leakage node OFF2 to reduce the second anti-leakage voltage.
  • This can prevent the first pull-up node Q ⁇ 1> from leaking electricity through the first black insertion transmission sub-circuit 23, so that the first pull-up node Q ⁇ 1> can maintain a higher and more stable voltage.
  • the first pole of the eighth transistor M8 in the second black insertion transmission sub-circuit 24 is electrically connected to the second anti-leakage node OFF2, and passes through The sixty-third transistor M63 is electrically connected to the second plugged black node OFF2.
  • the eighth transistor M8 and the sixty-third transistor M63 may be turned on simultaneously under the action of the second control signal.
  • the sixty-third transistor M63 can receive the black insertion input signal from the second black insertion node K, and send the black insertion input signal to the second anti-leakage node OFF2, and the eighth transistor M8 can receive and transmit the black insertion input signal to the second black insertion node.
  • the second pull-up node Q ⁇ 2> charges the second pull-up node Q ⁇ 2>.
  • the eighth transistor M8 and the sixty-third transistor M63 can be turned off simultaneously under the action of the second control signal.
  • the second capacitor C2 in the second output circuit 22 starts to discharge, so that the voltage of the second pull-up node Q ⁇ 2> remains at a high level.
  • the voltage of the first pull-up node Q ⁇ 1> remains at a high level state, and the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, charge the second anti-leakage node OFF2, reduce the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and make the control electrode of the seventh transistor M7 and the first electrode The voltage difference between them is less than zero, ensuring that the eighth transistor M8 is completely or relatively completely turned off. This can prevent the second pull-up node Q ⁇ 2> from leaking electricity through the second black insertion transmission sub-circuit 24, so that the second pull-up node Q ⁇ 2> can maintain a higher and more stable voltage.
  • the second black insertion transmission sub-circuit 24 shares the sixty-third transistor M63 in the first black insertion transmission sub-circuit 23 , which is beneficial to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100 .
  • the first scanning unit 1 further includes a first reset circuit 13
  • the first reset circuit 13 is also connected to the second anti-leakage node OFF2 is electrically connected.
  • the second anti-leakage node OFF2 When the first pull-up node Q ⁇ 1> is at a high level and the first reset circuit 13 is not working, by electrically connecting the first reset circuit 13 to the second anti-leakage node OFF2, the second anti-leakage The voltage difference between the leakage node OFF2 and the first pull-up node Q ⁇ 1> prevents the first pull-up node Q ⁇ 1> from leaking through the first reset circuit 13, thereby enabling the first pull-up node Q ⁇ 1> to Keep it at a relatively high and relatively stable voltage to avoid affecting the conduction state of the first output circuit 12 .
  • the first reset circuit 13 further includes: a sixty-fourth transistor M64.
  • the control electrode of the sixty-fourth transistor M64 is electrically connected to the first reset signal terminal STD, and the first electrode of the sixty-fourth transistor M64 is connected to the first reset signal terminal STD.
  • the two anti-leakage nodes OFF2 are electrically connected, and the second pole of the sixty-fourth transistor M64 is electrically connected to the first voltage signal terminal V1.
  • the second pole of the thirteenth transistor M13 in the first reset circuit 13 is electrically connected to the second anti-leakage node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-fourth transistor M64.
  • the thirteenth transistor M13 and the sixty-fourth transistor M64 may be turned on simultaneously under the action of the first reset signal.
  • the sixty-fourth transistor M64 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the thirteenth transistor M13 can transmit the first voltage signal to the first pull-up node Q ⁇ 1>. Pull node Q ⁇ 1> for pull-down reset.
  • the thirteenth transistor M13 and the sixty-fourth transistor M64 can be turned off simultaneously under the action of the first reset signal.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, Charge the second anti-leakage node OFF2, reduce the voltage difference between the second anti-leakage node OFF2 and the first pull-up node Q ⁇ 1>, and make the control electrode and the second electrode of the thirteenth transistor M13 The voltage difference is less than zero, ensuring that the thirteenth transistor M13 is completely or relatively completely turned off. This can prevent the first pull-up node Q ⁇ 1> from leaking through the first reset circuit 13, so that the first pull-up node Q ⁇ 1> can be kept at a higher and more stable voltage.
  • the third reset circuit 33 is also connected to the second anti-leakage node OFF2 is electrically connected.
  • the second pull-up node Q ⁇ 2> When the first pull-up node Q ⁇ 1> is at high level, the second pull-up node Q ⁇ 2> is at high level and the third reset circuit 33 is not working, by connecting the third reset circuit 13 with the second The anti-leakage node OFF2 is electrically connected, which can reduce the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and prevent the second pull-up node Q ⁇ 2> from leaking through the third reset circuit 33, Furthermore, the second pull-up node Q ⁇ 2> can be maintained at a higher and more stable voltage, so as to avoid affecting the conduction state of the second output circuit 32 .
  • the second pole of the sixteenth transistor M16 in the third reset circuit 33 is electrically connected to the second anti-leakage node OFF2, and It is electrically connected to the first voltage signal terminal V1 through the sixty-fourth transistor M64.
  • the sixteenth transistor M16 and the sixty-fourth transistor M64 may be turned on simultaneously under the action of the first reset signal.
  • the sixty-fourth transistor M64 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the sixteenth transistor M16 can transmit the first voltage signal to the second pull-up node Q ⁇ 2>. Pull node Q ⁇ 2> for a pull-down reset.
  • the sixteenth transistor M16 and the sixty-fourth transistor M64 can be turned off simultaneously under the action of the first reset signal.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can convert the first The five-voltage signal is transmitted to the second anti-leakage node OFF2 to charge the second anti-leakage node OFF2, reducing the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and making the tenth
  • the voltage difference between the control electrode and the second electrode of the sixth transistor M16 is less than zero, ensuring that the sixteenth transistor M16 is completely or relatively completely turned off. This can prevent the second pull-up node Q ⁇ 2 > from leaking electricity through the third reset circuit 33 , so that the second pull-up node Q ⁇ 2 > can be kept at a
  • the third reset circuit 33 shares the sixty-fourth transistor M64 in the first reset circuit 13 , which is beneficial to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100 .
  • the second reset circuit 14 when the first scanning unit 1 further includes a second reset circuit 14, the second reset circuit 14 is also connected to the second anti-leakage node OFF2 is electrically connected.
  • the second anti-leakage node OFF2 When the first pull-up node Q ⁇ 1> is at a high level and the second reset circuit 14 is not working, by electrically connecting the second reset circuit 14 to the second anti-leakage node OFF2, the second anti-leakage The voltage difference between the leakage node OFF2 and the first pull-up node Q ⁇ 1> prevents the first pull-up node Q ⁇ 1> from leaking through the second reset circuit 14, thereby enabling the first pull-up node Q ⁇ 1> to Keep it at a relatively high and relatively stable voltage to avoid affecting the conduction state of the first output circuit 12 .
  • the second reset circuit 14 further includes: a sixty-fifth transistor M65.
  • the control electrode of the sixty-fifth transistor M65 is electrically connected to the second reset signal terminal BTRST, and the first electrode of the sixty-fifth transistor M65 is connected to the second reset signal terminal BTRST.
  • the anti-leakage node OFF2 is electrically connected, and the second pole of the sixty-fifth transistor M65 is electrically connected to the first voltage signal terminal V1.
  • the second pole of the fifteenth transistor M15 in the second reset circuit 14 is electrically connected to the second anti-leakage node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-fifth transistor M65.
  • the fourteenth transistor M14 can be powered by the voltage of the first black node M turned on, the fifteenth transistor M15 and the sixty-fifth transistor M65 can be turned on simultaneously under the action of the second reset signal.
  • the sixty-fifth transistor M65 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the fifteenth transistor M15 and the fourteenth transistor M14 can transmit the first voltage signal to the first pull-up node Q ⁇ 1 >, perform a pull-down reset on the first pull-up node Q ⁇ 1>.
  • the fourteenth transistor M14, the fifteenth transistor M15 and the sixty-fifth transistor M65 may be turned off. broken.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, Charge the second anti-leakage node OFF2, reduce the voltage difference between the second anti-leakage node OFF2 and the first pull-up node Q ⁇ 1>, and make the gap between the control electrode and the second electrode of the fifteenth transistor M15
  • the voltage difference of is less than zero, ensuring that the fifteenth transistor M15 is completely or relatively completely turned off. This can prevent the first pull-up node Q ⁇ 1> from leaking electricity through the second reset circuit 14, so that the first pull-up node Q ⁇ 1> can be kept at a higher and more stable voltage.
  • the fourth reset circuit 34 when the second scanning unit 3 further includes a fourth reset circuit 34, the fourth reset circuit 34 is also connected to the second anti-leakage node OFF2 is electrically connected.
  • the second pull-up node Q ⁇ 2> When the first pull-up node Q ⁇ 1> is at high level, the second pull-up node Q ⁇ 2> is at high level and the fourth reset circuit 34 is not working, by combining the fourth reset circuit 34 with the second
  • the anti-leakage node OFF2 is electrically connected, which can reduce the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and prevent the second pull-up node Q ⁇ 2> from leaking through the fourth reset circuit 34, Furthermore, the second pull-up node Q ⁇ 2> can be maintained at a higher and more stable voltage, so as to avoid affecting the conduction state of the second output circuit 32 .
  • the second pole of the eighteenth transistor M18 in the fourth reset circuit 34 is electrically connected to the second anti-leakage node OFF2, and It is electrically connected to the first voltage signal terminal V1 through the sixty-fifth transistor M65.
  • the seventeenth transistor M17 can be powered by the voltage of the first black node M turned on, the eighteenth transistor M18 and the sixty-fifth transistor M65 can be turned on simultaneously under the action of the second reset signal.
  • the sixty-fifth transistor M65 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the eighteenth transistor M18 and the seventeenth transistor M17 can transmit the first voltage signal to the second pull-up node Q ⁇ 2 >, perform a pull-down reset on the second pull-up node Q ⁇ 2>.
  • the seventeenth transistor M17, the eighteenth transistor M18 and the sixty-fifth transistor M65 can be turned off. broken.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, Charge the second anti-leakage node OFF2, reduce the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and make the control electrode and the second electrode of the eighteenth transistor M18
  • the voltage difference of is less than zero, ensuring that the eighteenth transistor M18 is completely or relatively completely turned off. This can prevent the second pull-up node Q ⁇ 2> from leaking electricity through the fourth reset circuit 34, so that the second pull-up node Q ⁇ 2> can be kept at a higher and more stable voltage.
  • the fourth reset circuit 34 shares the sixty-fifth transistor M65 in the second reset circuit 14 , which is beneficial to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100 .
  • the fifth reset circuit 16 when the first scanning unit 1 further includes a fifth reset circuit 16, the fifth reset circuit 16 is also connected to the second anti-leakage node OFF2 is electrically connected.
  • the fifth reset circuit 16 further includes: a sixty-sixth transistor M66.
  • the control electrode of the sixty-sixth transistor M66 is electrically connected to the first pull-down node QB_A, and the first electrode of the sixty-sixth transistor M66 is electrically connected to the first pull-down node QB_A.
  • the two anti-leakage nodes OFF2 are electrically connected, and the second pole of the sixty-sixth transistor M66 is electrically connected to the first voltage signal terminal V1.
  • the second pole of the twenty-seventh transistor M27 in the fifth reset circuit 16 is electrically connected to the second anti-leakage node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-sixth transistor M66.
  • the twenty-seventh transistor M27 and the sixty-sixth transistor M66 may be turned on simultaneously under the action of the voltage of the first pull-down node QB_A.
  • the sixty-sixth transistor M66 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the twenty-seventh transistor M27 can transmit the first voltage signal to the first pull-up node Q ⁇ 1>, for the first Pull up node Q ⁇ 1> for pull-down reset.
  • the voltage of the first pull-down node QB_A When the voltage of the first pull-down node QB_A is at a low level, the voltage of the first pull-up node Q ⁇ 1> is at a high level.
  • the twenty-seventh transistor M27 and the sixty-sixth transistor M66 may be turned off.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, charge the second anti-leakage node OFF2, and reduce the second anti-leakage node OFF2 and the first anti-leakage node OFF2.
  • the fifth reset circuit 16 when the fifth reset circuit 16 is also electrically connected to the second pull-down node QB_B, the fifth reset circuit 16 further includes: sixtieth Seven transistors M67.
  • the control electrode of the sixty-seventh transistor M67 is electrically connected to the second pull-down node QB_B, and the first electrode of the sixty-seventh transistor M67 is connected to the second pull-down node QB_B.
  • the anti-leakage node OFF2 is electrically connected, and the second pole of the sixty-seventh transistor M67 is electrically connected to the first voltage signal terminal V1.
  • the second pole of the thirty-ninth transistor M39 in the fifth reset circuit 16 is electrically connected to the second anti-leakage node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-seventh transistor M67.
  • the thirty-ninth transistor M39 and the sixty-seventh transistor M67 may be turned on simultaneously under the action of the voltage of the second pull-down node QB_B.
  • the sixty-seventh transistor M67 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the thirty-ninth transistor M39 can transmit the first voltage signal to the first pull-up node Q ⁇ 1>, for the first Pull up node Q ⁇ 1> for pull-down reset.
  • the voltage of the second pull-down node QB_B When the voltage of the second pull-down node QB_B is at a low level, the voltage of the first pull-up node Q ⁇ 1> is at a high level.
  • the thirty-ninth transistor M39 and the sixty-seventh transistor M67 may be turned off.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, charge the second anti-leakage node OFF2, and reduce the second anti-leakage node OFF2 and the first anti-leakage node OFF2.
  • the eighth reset circuit 36 when the second scanning unit 3 further includes an eighth reset circuit 36, the eighth reset circuit 36 is also connected to the second anti-leakage node OFF2 is electrically connected.
  • the eighth reset circuit 36 is not working, by combining the eighth reset circuit 36 with the The two anti-leakage nodes OFF2 are electrically connected, which can reduce the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and prevent the second pull-up node Q ⁇ 2> from leaking through the eighth reset circuit 36 , so that the second pull-up node Q ⁇ 2> can be maintained at a higher and more stable voltage, so as to avoid affecting the conduction state of the second output circuit 32 .
  • the second pole of the thirty-third transistor M33 in the eighth reset circuit 36 is electrically connected to the second anti-leakage node OFF2, And it is electrically connected to the first voltage signal terminal V1 through the sixty-sixth transistor M66.
  • the voltage of the first pull-down node QB_A is at a high level.
  • the thirty-third transistor M33 may be turned on by the voltage of the second pull-down node QB_B, and the sixty-sixth transistor M66 may be turned on by the voltage of the first pull-down node QB_A.
  • the sixty-sixth transistor M66 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the thirty-third transistor M33 can transmit the first voltage signal to the second pull-up node Q ⁇ 2>, for the second Pull up node Q ⁇ 2> for pull-down reset.
  • the thirty-third transistor M33 and the sixty-sixth transistor M66 may be turned off.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, charge the second anti-leakage node OFF2, and reduce the second anti-leakage node OFF2 and the first anti-leakage node OFF2.
  • the eighth reset circuit 36 when the eighth reset circuit 36 is also electrically connected to the first pull-down node QB_A, the second of the forty-third transistor M43 in the eighth reset circuit 36 The electrode is electrically connected to the second anti-leakage node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-seventh transistor M67.
  • the voltage of the first pull-down node QB_A is at a high level.
  • the forty-third transistor M43 and the sixty-seventh transistor M67 may be turned on.
  • the sixty-seventh transistor M67 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the forty-third transistor M43 can transmit the first voltage signal to the second pull-up node Q ⁇ 2>, for the second Pull up node Q ⁇ 2> for pull-down reset.
  • the forty-third transistor M43 and the sixty-seventh transistor M67 may be turned off.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, charge the second anti-leakage node OFF2, and reduce the second anti-leakage node OFF2 and the first anti-leakage node OFF2.
  • the eighth reset circuit 36 shares the sixty-sixth transistor M66 and the sixty-seventh transistor M67 of the fifth reset circuit 16 , which is beneficial to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100 .
  • the eleventh reset circuit 19 is also electrically connected to the second anti-leakage node OFF2 .
  • the eleventh reset circuit 19 When the first pull-up node Q ⁇ 1> is at a high level and the eleventh reset circuit 19 is not working, by electrically connecting the eleventh reset circuit 19 to the second anti-leakage node OFF2, the first The voltage difference between the second anti-leakage node OFF2 and the first pull-up node Q ⁇ 1> prevents the first pull-up node Q ⁇ 1> from leaking through the eleventh reset circuit 19, thereby making the first pull-up node Q ⁇ 1> 1> It can be kept at a relatively high and relatively stable voltage, so as to avoid affecting the conduction state of the first output circuit 12 .
  • the eleventh reset circuit 19 further includes: a sixty-eighth transistor M68.
  • the control electrode of the sixty-eighth transistor M68 is electrically connected to the global reset signal terminal TRST, and the first electrode of the sixty-eighth transistor M68 is electrically connected to the second anti-leakage node OFF2 , the second pole of the sixty-eighth transistor M68 is electrically connected to the first voltage signal terminal V1.
  • the second pole of the fifty-first transistor M51 in the eleventh reset circuit 19 is electrically connected to the second anti-leakage node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-eighth transistor M68.
  • the fifty-first transistor M51 and the sixty-eighth transistor M68 may be turned on simultaneously under the action of the global reset signal.
  • the sixty-eighth transistor M68 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the fifty-first transistor M51 can transmit the first voltage signal to the first pull-up node Q ⁇ 1>, for the first Pull up node Q ⁇ 1> for pull-down reset.
  • the fifty-first transistor M51 and the sixty-eighth transistor M68 can be turned off simultaneously under the action of the global reset signal.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, Charge the second anti-leakage node OFF2, reduce the voltage difference between the second anti-leakage node OFF2 and the first pull-up node Q ⁇ 1>, and make the control electrode of the fifty-first transistor M51 and the second electrode The voltage difference between them is less than zero, ensuring that the fifty-first transistor M51 is completely or relatively completely turned off. This can prevent the first pull-up node Q ⁇ 1> from leaking electricity through the eleventh reset circuit 19, so that the first pull-up node Q ⁇ 1> can be kept at a higher and more stable voltage.
  • the fourteenth reset circuit 39 is also electrically connected to the second anti-leakage node OFF2 .
  • the fourteenth reset circuit 39 When the first pull-up node Q ⁇ 1> is at a high level, the second pull-up node Q ⁇ 2> is at a high level and the fourteenth reset circuit 39 is not working, by combining the fourteenth reset circuit 39 with The second anti-leakage node OFF2 is electrically connected, which can reduce the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and prevent the second pull-up node Q ⁇ 2> from passing through the fourteenth reset circuit 39 leaks electricity, thereby enabling the second pull-up node Q ⁇ 2> to maintain a relatively high and relatively stable voltage, so as to avoid affecting the conduction state of the second output circuit 32 .
  • the second pole of the fifty-fifth transistor M55 in the fourteenth reset circuit 39 is electrically connected to the second anti-leakage node OFF2, and is connected through the sixtieth
  • the eight transistors M68 are electrically connected to the first voltage signal terminal V1.
  • the fifty-fifth transistor M55 and the sixty-eighth transistor M68 may be turned on simultaneously under the action of the global reset signal.
  • the sixty-eighth transistor M68 can receive and transmit the first voltage signal to the second anti-leakage node OFF2, and the fifty-fifth transistor M55 can transmit the first voltage signal to the second pull-up node Q ⁇ 2>, for the second Pull up node Q ⁇ 2> for pull-down reset.
  • the fifty-fifth transistor M55 and the sixty-eighth transistor M68 can be turned off simultaneously under the action of the global reset signal.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can convert the first The five-voltage signal is transmitted to the second anti-leakage node OFF2 to charge the second anti-leakage node OFF2, reducing the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q ⁇ 2>, and making the fifth The voltage difference between the control electrode and the second electrode of the fifteenth transistor M55 is less than zero, ensuring that the fifty-fifth transistor M55 is completely or relatively completely turned off. This can prevent the second pull-up node Q ⁇ 2 > from leaking electricity through the fourteenth reset circuit 39 , so that the second pull-up node Q ⁇ 2
  • the fourteenth reset circuit 39 shares the sixty-eighth transistor M68 in the eleventh reset circuit 19 , which is beneficial to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100 .
  • the blanking circuit 4 is also electrically connected to the second anti-leakage node OFF2 .
  • the first blanking transmission subcircuit 43 when the blanking circuit 4 includes a first blanking transmission subcircuit 43, the first blanking transmission subcircuit 43 further includes: sixty-ninth Transistor M69.
  • the control electrode of the sixty-ninth transistor M69 is electrically connected to the seventh clock signal terminal CLKA, and the first electrode of the sixty-ninth transistor M69 is electrically connected to the second blanking node N. connected, the second pole of the sixty-ninth transistor M69 is electrically connected to the second anti-leakage node OFF2.
  • the first electrode of the forty-ninth transistor M49 in the first blanking transmission sub-circuit 43 is electrically connected to the second anti-leakage node OFF2, and is electrically connected to the second blanking node N through the sixty-ninth transistor M69.
  • the forty-ninth transistor M49 and the sixty-ninth transistor M69 may be turned on simultaneously under the effect of the seventh clock signal.
  • the sixty-ninth transistor M69 can receive the seventh clock signal from the second blanking node N, and send the seventh clock signal to the second anti-leakage node OFF2, and the forty-ninth transistor M49 can receive and transmit the seventh clock signal to the first pull-up node Q ⁇ 1>, and charge the first pull-up node Q ⁇ 1>.
  • the forty-ninth transistor M49 and the sixty-ninth transistor M69 can be turned off simultaneously under the action of the seventh clock signal.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, Charge the second anti-leakage node OFF2, reduce the voltage difference between the second anti-leakage node OFF2 and the first pull-up node Q ⁇ 1>, and make the control electrode of the forty-ninth transistor M49 and the first electrode The voltage difference between them is less than zero, ensuring that the forty-ninth transistor M49 is completely or relatively completely turned off. This can prevent the first pull-up node Q ⁇ 1> from leaking electricity through the first blanking transmission sub-circuit 43, so that the first pull-up node Q ⁇ 1> can be maintained at a higher and more stable voltage.
  • the first pole of the fiftieth transistor M50 in the second blanking transmission sub-circuit 44 is electrically connected to the second anti-leakage node OFF2, and is connected through the sixty-ninth transistor M69 is electrically connected to the second blanking node N.
  • the fiftieth transistor M50 and the sixty-ninth transistor M69 may be turned on simultaneously under the action of the seventh clock signal.
  • the sixty-ninth transistor M69 can receive the seventh clock signal from the second blanking node N, and transmit the seventh clock signal to the second anti-leakage node OFF2, and the fiftieth transistor M50 can receive and transmit the seventh clock signal to The second pull-up node Q ⁇ 2> charges the second pull-up node Q ⁇ 2>.
  • the fiftieth transistor M50 and the sixty-ninth transistor M69 can be turned off simultaneously under the action of the seventh clock signal.
  • the sixty-first transistor M61 in the second anti-leakage circuit 7 can transmit the fifth voltage signal to the second anti-leakage node OFF2, Charge the second anti-leakage node OFF2, reduce the voltage difference between the second anti-leakage node OFF2 and the first pull-up node Q ⁇ 1>, and make the gap between the control electrode and the first electrode of the fiftieth transistor M50 The voltage difference is less than zero, ensuring that the fiftieth transistor M50 is completely or relatively completely turned off. This can prevent the second pull-up node Q ⁇ 2> from leaking electricity through the second blanking transmission sub-circuit 44, so that the second pull-up node Q ⁇ 2> can maintain a relatively high and stable voltage.
  • the multi-stage cascaded shift register 100 included in the scan driving circuit 1000 includes multiple first shift register groups C and a plurality of second shift register groups D.
  • the first shift register group C and the second shift register group D are alternately arranged.
  • the shift register 100 of the above-mentioned stages may include a first scanning unit 1 .
  • the above-mentioned shift registers 100 at each stage may include a first scanning unit 1 and a second scanning unit 3 .
  • the structure of the scanning driving circuit 1000 will be schematically described below by taking the shift register 100 of each stage including the first scanning unit 1 and the second scanning unit 3 as an example.
  • the first shift register group C may include 2N stages of shift registers 100
  • the second shift register group includes 2N stages of shift registers 100 ; wherein, N is a positive integer. That is, the number of shift registers 100 included in each shift register group is the same.
  • the first shift register group C may include 4-stage shift registers 100
  • the second shift register group includes 4-stage shift registers 100
  • each stage of the shift register 100 includes a first scanning unit 1 and a second scanning unit 3
  • each shift register group may have eight scanning signal terminals, for example, may be electrically connected to eight rows of sub-pixels P respectively.
  • the first shift register group C may include 8-stage shift registers 100
  • the second shift register group includes 8-stage shift registers 100
  • each stage of the shift register 100 includes a first scanning unit 1 and a second scanning unit 3
  • each shift register group may have sixteen scanning signal terminals, for example, may be electrically connected to sixteen rows of sub-pixels P, respectively.
  • the first shift register group C at least two stages of shift registers 100 share the black insertion circuit 2 .
  • the second shift register group D at least two stages of shift registers 100 share the black insertion circuit 2 .
  • N 2 as an example.
  • every two stages of shift registers 100 may share the black insertion circuit 2 .
  • each shift register group the four-stage shift register 100 may share the black insertion circuit 2 .
  • each shift register group may only have a black insertion circuit 2 .
  • one black insertion circuit 2 can be used to transmit the black insertion input signal to the first pull-up node Q ⁇ 1> and the second pull-up node Q ⁇ 2> of the corresponding at least two-stage shift register 100, so as to realize the At least two stages of shift register 100 are controlled, which is beneficial to improve signal transmission efficiency and simplify the structure of scan driving circuit 1000 .
  • the scan driving circuit 1000 may include multiple signal lines.
  • the scan driving circuit 1000 further includes: a first control signal line group.
  • the first control signal line group may include a first sub-control signal line BCK1 and a second sub-control signal line BCK2 .
  • the first sub-control signal line BCK1 is electrically connected to the first control signal terminal BCS1 of each shift register 100 in the first shift register group C
  • the second sub-control signal line BCK2 is connected to each of the second shift register group D.
  • the first control signal terminal BCS1 of the shift register 100 is electrically connected.
  • the first control signal line group includes only one first sub-control signal line BCK1 and one second sub-control signal line BCK2.
  • the first control signal can be transmitted to the first control signal terminal BCS1 in each first shift register group C through the first sub-control signal line BCK1 to control each first shift register group C.
  • the black insertion control subcircuit 21 in the black insertion circuit 2 in the bit register group C is turned on, and the received black insertion cascade signal is stored; it can be sent to each second shift register through the second sub-control signal line BCK2
  • the first control signal terminal BCS1 in the group D transmits the first control signal, controls the black insertion control sub-circuit 21 in the black insertion circuit 2 in each second shift register group D to conduct, and controls the received black insertion level Linked signals are stored.
  • the corresponding black insertion input sub-circuit 22 may be in a conduction state, and transmit the black insertion input signal to the second black insertion node K.
  • the corresponding black insertion input sub-circuit 22 may be in an off state.
  • the scan driving circuit 1000 further includes: a second control signal line group.
  • the second control signal line group 300 may include a third sub-control signal line BCK3 and a fourth sub-control signal line BCK4 .
  • the third sub-control signal line BCK3 is electrically connected to the second control signal terminal BCS2 of each shift register 100 in the first shift register group C
  • the fourth sub-control signal line BCK4 is electrically connected to each of the second shift register group D.
  • the second control signal terminal BCS2 of the shift register 100 is electrically connected.
  • the second control signal line group includes only one third sub-control signal line BCK3 and three second sub-control signal lines BCK4.
  • the second control signal terminal BCS2 of each shift register 100 can receive the second control signal at the same time;
  • the second control signal terminal BCS2 can receive the second control signal at the same time.
  • the third sub-control signal line BCK3 It is also electrically connected with the black input signal terminal BI of each shift register 100 in the first shift register group C, and the fourth sub-control signal line BCK4 is also connected with the black insertion terminal BI of each shift register 100 in the second shift register group D.
  • the input signal terminal BI is electrically connected.
  • each first shift register group C the second control signal terminal BCS2 and the black input signal terminal BI of each shift register 100 can receive signals from the same third sub-control signal line BCK3, and each second In the shift register group D, the second control signal terminal BCS2 and the black input signal terminal BI of each shift register 100 can receive signals from the same fourth sub-control signal line BCK4. This is beneficial to reduce the number of signal lines and simplify the structure of the scan driving circuit 1000 .
  • the same signal can be transmitted to the second control signal terminal BCS2 and the black input signal terminal BI in each first shift register group C through the third sub-control signal line BCK3 to control The conduction state of the first black insertion transmission sub-circuit 23 and the second black insertion transmission sub-circuit 24 of the black insertion circuit 2 in each first shift register group C.
  • the level of the third sub-control signal transmitted by the third sub-control signal line BCK3 is high level, the above-mentioned first black insertion transmission sub-circuit 23 can be turned on, and the third sub-control signal of high level can be turned on.
  • the signal is transmitted to the first pull-up node Q ⁇ 1>, and the voltage of the first pull-up node Q ⁇ 1> is raised, the above-mentioned second plug-in black transmission sub-circuit 24 can be turned on, and the third sub-circuit of high level is controlled
  • the signal is transmitted to the second pull-up node Q ⁇ 2> to increase the voltage of the second pull-up node Q ⁇ 2>.
  • the first clock signal transmitted by the first clock signal terminal CLKE1 and the second clock signal transmitted by the second clock signal terminal CLKE2 can be used to control multiple rows of sub-pixels P corresponding to the first shift register group C to simultaneously A black screen is displayed.
  • the black input signal terminal BI of each shift register 100 may be connected to a line for transmitting a DC high level signal, for example. .
  • the multiple rows of sub-pixels P corresponding to the second shift register group D display images.
  • the black input signal terminals BI of each shift register 100 can be electrically connected to the first shift signal terminal CR ⁇ N> of a certain shift register 100, which can make The black insertion circuit 2 realizes the black insertion function, so that the display device 2000 only needs to insert a black picture.
  • the above-mentioned first shift signal terminal CR ⁇ N> may be the shift signal terminal of the 1099th row, that is, the first shift signal terminal CR ⁇ N> in the shift register 100 of the 545th stage.
  • the setting of the second control signal line group can be avoided, which is beneficial to reducing the number of signal lines included in the scan driving circuit 1000 and simplifying the structure of the scan driving circuit 1000 .
  • the scan driving circuit 1000 further includes: a first clock signal line group.
  • the first clock signal line group may include 8N first sub-clock signal lines CKE.
  • the 8N first sub-clock signal lines CKE are respectively connected with the first clock signal terminal CLKE1 and the second clock signal terminal CLKE2 of each shift register 100 in the first shift register group C, and the second clock signal terminal CLKE2 in the second shift register group D.
  • the first clock signal terminal CLKE1 and the second clock signal terminal CLKE2 of each shift register 100 are electrically connected.
  • the number of the first sub-clock signal lines CKE included in the first clock signal line group may be the sum of the number of scanning signal terminals included in a first shift register group C and a second shift register group D same.
  • One first sub-clock signal line CKE may correspond to one scan signal terminal.
  • first sub-clock signal lines CKE electrically connected to the first shift register groups C are the same, and the first sub-clock signal lines CKE electrically connected to the second shift register groups D are the same.
  • the first clock signal line group may include 16 first sub clock signal lines CKE.
  • the 16 first sub-clock signal lines CKE may include: respectively electrically connected to the first clock signal terminal CLKE1 and the second clock signal terminal CLKE2 of the first-stage shift register 100 in each first shift register group C
  • Nine CKE_9 of the first sub-clock signal line and ten CKE_10 of the first sub-clock signal line respectively connected with the first clock signal terminal CLKE1 and the second clock signal of the second-stage shift register 100 in each first shift register group C
  • the thirteen CKE_13 of the first sub-clock signal line and the fourteen CKE_14 of the first sub-clock signal line electrically connected to the terminal CLKE1 and the second clock signal terminal CLKE2;
  • Fifteen CKE_15 of the first sub-clock signal lines and sixteen CKE_16 of the first sub-clock signal lines electrically connected to the first clock signal terminal CLKE1 and the second clock signal terminal CLKE2 of the register
  • connection sequence of the first sub-clock signal line CKE can be changed, and is not limited to the above connection method.
  • the first output circuit 21 of the shift register 100 is also electrically connected to the third clock signal terminal CLKF1 and the first sensing signal terminal Oput2 ⁇ N>, and the second output circuit 32 is also connected to the fourth clock signal terminal When CLKF2 is electrically connected to the second sensing signal terminal Oput2 ⁇ N+1>, the scan driving circuit 1000 further includes: a second clock signal line group.
  • the second clock signal line group 500 includes 4N second sub-clock signal lines CKF.
  • the 4N second sub-clock signal lines CKF are respectively electrically connected to the third clock signal terminal CLKF1 and the fourth clock signal terminal CLKF2 of each shift register 100 in the first shift register group C, and are respectively connected to the second shift register terminal CLKF2.
  • the third clock signal terminal CLKF1 and the fourth clock signal terminal CLKF2 of each shift register 100 in the bit register group D are electrically connected.
  • the number of the second sub-clock signal lines CKF included in the second clock signal line group 500 can be compared with the number of sensing signal terminals included in a first shift register group C or a second shift register group D. same.
  • One second sub-clock signal line CKF may correspond to one sensing signal terminal.
  • the second sub-clock signal line CKF electrically connected to each shift register group is the same.
  • the second clock signal line group may include 8 second sub clock signal lines CKF.
  • the 8 second sub-clock signal lines CKF may include: the third clock signal terminal CLKF1 of the first-stage shift register 100 in each first shift register group C and the third clock signal terminal CLKF1 in each second shift register group C.
  • the third clock signal terminal CLKF1 of the shift register 100 and the third clock signal terminal CLKF1 of the second stage shift register 100 in each second shift register group C are electrically connected to the second sub-clock signal line three CKF_3;
  • the second clock signal line group 500 includes 8N second sub-clock signal lines CKF.
  • the 8N second sub-clock signal lines CKF are respectively connected with the third clock signal terminal CLKF1 and the fourth clock signal terminal CLKF2 of each shift register 100 in the first shift register group C, and the second clock signal terminal CLKF2 in the second shift register group D.
  • the third clock signal terminal CLKF1 and the fourth clock signal terminal CLKF2 of each shift register 100 are electrically connected.
  • the number of the second sub-clock signal lines CKF included in the second clock signal line group 500 can be compared with the number of sensing signal terminals included in one first shift register group C and one second shift register group D. and the same.
  • One second sub-clock signal line CKF may correspond to one sensing signal terminal.
  • the second sub-clock signal lines CKF electrically connected to the first shift register groups C are the same, and the second sub-clock signal lines CKF electrically connected to the second shift register groups D are the same.
  • the second clock signal line group 500 may include 16 second sub clock signal lines CKF.
  • the 16 second sub-clock signal lines CKF may include: respectively electrically connected to the third clock signal terminal CLKF1 and the fourth clock signal terminal CLKF2 of the first-stage shift register 100 in each first shift register group C
  • Nine CKF_9 of the second sub-clock signal line and ten CKF_10 of the second sub-clock signal line respectively connected with the third clock signal terminal CLKF1 and the fourth clock signal of the second-stage shift register 100 in each first shift register group C
  • the 13th CKF_13 of the second sub-clock signal line and the 14th CKF_14 of the second sub-clock signal line electrically connected to the terminal CLKF1 and the fourth clock signal terminal CLKF2
  • connection sequence of the second sub-clock signal line CKF can be changed, and is not limited to the above connection method.
  • the scanning driving circuit 1000 may not set the second clock signal line group 500, but connect the third clock signal terminal CLKF1 with the first scanning unit 1 to which it belongs.
  • a clock signal terminal CLKE1 is connected to the same first sub-clock signal line CKE
  • the fourth clock signal terminal CLKF2 and the second clock signal terminal CLKE2 of the second scanning unit 3 to which it belongs are connected to the same first sub-clock signal line CKE.
  • the first output circuit 12 of the shift register 100 is also electrically connected to the fifth clock signal terminal CLKD1 and the first shift signal terminal CR ⁇ N>, and the second output circuit 32 is also connected to the sixth clock signal terminal CLKD2 and the second shift signal terminal CR2 ⁇ N+1> are electrically connected.
  • the display input signal terminal Iput of the remaining stage shift register 100 is the same as the first shift register 100 in the previous shift register 100.
  • the bit signal terminal CR ⁇ N> is electrically connected. Except for at least two stages of shift registers 100 in the first stage, the black-inserted cascaded signal terminals BCR of the other stages of shift registers 100 are electrically connected to the second shift signal terminal CR2 ⁇ N+1> in the previous shift register 100 .
  • the shift signals transmitted by the shift signal terminals of odd rows are used as display cascade signals, and the shift signals transmitted by the shift signal terminals of even rows are used as black insertion cascade signals.
  • N 2 as an example. Except for the first two stages of shift registers 100 , the display input signal terminals Iput of the other stages of shift registers 100 are electrically connected to the first shift signal terminals CR ⁇ N> of the first two stages of shift registers 100 . Except the first four stages of shift registers 100 , the black insertion cascade signal terminals BCR of the other stages of shift registers 100 are electrically connected to the second shift signal terminal CR2 ⁇ N+1> in the first four stages of shift registers 100 .
  • the first output circuit 12 of the shift register 100 is also electrically connected to the fifth clock signal terminal CLKD1 and the first shift signal terminal CR ⁇ N>, and the second output circuit 32 is also It is electrically connected with the sixth clock signal terminal CLKD2 and the second shift signal terminal CR2 ⁇ N+1>.
  • the display input signal terminal Iput of the other stages of shift registers is the same as the second shift register in the previous shift register 100.
  • the signal terminal CR2 ⁇ N+1> is electrically connected.
  • the black-insertion cascaded signal terminals BCR of the other shift registers 100 are electrically connected to the first shift signal terminal CR ⁇ N> in the previous shift register 100 .
  • the shift signal transmitted by the shift signal terminals of odd rows is used as a black insertion cascade signal
  • the shift signal transmitted by the shift signal terminals of even rows is used as a display cascade signal.
  • N 2 as an example. Except the first two stages of shift registers 100 , the display input signal terminals Iput of the other stages of shift registers 100 are electrically connected to the second shift signal terminals CR2 ⁇ N+1> in the first two stages of shift registers 100 . Except for the first four stages of shift registers 100 , the black plugging cascade signal terminals BCR of the other stages of shift registers 100 are electrically connected to the first shift signal terminals CR ⁇ N> of the first four stages of shift registers 100 .
  • the first output circuit 12 of the shift register 100 is also electrically connected to the fifth clock signal terminal CLKD1 and the first shift signal terminal CR ⁇ N>, and the shift register 100 also includes The second anti-leakage circuit 7.
  • the display input signal terminal Iput of the remaining stage shift register 100 is the same as the first shift register 100 in the previous shift register 100.
  • the bit signal terminal CR ⁇ N> is electrically connected. Except for at least two stages of shift registers 100 in the first stage, the black plug-in cascade signal terminal BCR of the shift registers 100 in other stages is electrically connected to the second anti-leakage node OFF2 of the previous shift register 100 .
  • the shift signal transmitted by the shift signal terminal of the odd row is used as the display cascade signal
  • the fifth voltage signal transmitted by the second anti-leakage node OFF2 of the even row is used as the display cascade signal.
  • the second anti-leakage node OFF2 of the even rows can also be called the second anti-leakage node OFF2 of the odd rows. Node OFF2.
  • N 2 as an example. Except for the first two stages of shift registers 100 , the display input signal terminals Iput of the other stages of shift registers 100 are electrically connected to the first shift signal terminals CR ⁇ N> of the first two stages of shift registers 100 . Except for the first four stages of shift registers 100 , the black plug cascade signal terminals BCR of the other stages of shift registers 100 are electrically connected to the second anti-leakage node OFF2 in the first four stages of shift registers 100 .
  • the second output circuit 32 in the second scanning unit 3 may not be provided with the twelfth transistor M12, and may not be electrically connected to the sixth clock signal terminal CLKD2, so that the ninth reset in the second scanning unit 3
  • the circuit 37 may not be provided with corresponding transistors.
  • the scan driving circuit 1000 may further include: a third clock signal line group.
  • the first output circuit 12 of the shift register 100 is also electrically connected to the fifth clock signal terminal CLKD1 and the first shift signal terminal CR ⁇ N>, and the second output circuit 32 is also connected to the sixth clock signal terminal
  • the third clock signal line group 600 may include 8N third sub-clock signal lines CKD.
  • the 8N third sub-clock signal lines CKD are respectively connected with the fifth clock signal terminal CLKD1 and the sixth clock signal terminal CLKD2 of each shift register 100 in the first shift register group C, and the second clock signal terminal CLKD2 in the second shift register group D.
  • the fifth clock signal terminal CLKD1 and the sixth clock signal terminal CLKD2 of each shift register 100 are electrically connected.
  • the third sub-clock signal lines CKD electrically connected to the first shift register groups C are the same, and the third sub-clock signal lines CKD electrically connected to the second shift register groups D are the same.
  • the third clock signal line group 600 may include 16 third sub clock signal lines CKD.
  • the 16 third sub-clock signal lines CKD may include: respectively electrically connected to the fifth clock signal terminal CLKD1 and the sixth clock signal terminal CLKD2 of the first-stage shift register 100 in each first shift register group C
  • Nine CKD_9 of the third sub-clock signal line and ten CKD_10 of the third sub-clock signal line respectively connected with the fifth clock signal terminal CLKD1 and the sixth clock signal of the second-stage shift register 100 in each first shift register group C
  • the thirteen CKD_13 of the third sub-clock signal line and the fourteen CKD_14 of the third sub-clock signal line electrically connected to the terminal CLKD1 and the sixth clock signal terminal CLKD2
  • connection sequence of the third sub-clock signal line CKD can be changed, and is not limited to the above connection method.
  • the third clock signal line group 600 may include 4N third sub-clock signal lines CKD.
  • the 4N third sub-clock signal lines CKD are respectively electrically connected to the fifth clock signal terminal CLKD1 and the sixth clock signal terminal CLKD2 of each shift register 100 in the first shift register group C, and are respectively connected to the second shift register group C.
  • the fifth clock signal terminal CLKD1 and the sixth clock signal terminal CLKD2 of each shift register 100 in the bit register group D are electrically connected.
  • the number of the third sub-clock signal lines CKD included in the third clock signal line group 600 can be compared with the number of shift signal terminals included in a first shift register group C or a second shift register group D. same.
  • One third sub-clock signal line CKD may correspond to one shift signal terminal.
  • the third sub-clock signal line CKD electrically connected to each shift register group is the same.
  • the third clock signal line group 600 may include 8 third sub clock signal lines CKD.
  • the eight third sub-clock signal lines CKD may include: the fifth clock signal terminal CLKD1 of the first-stage shift register 100 in each first shift register group C and the fifth clock signal terminal CLKD1 in each second shift register group C.
  • the second CKD_2 of the third sub-clock signal line electrically connected to the sixth clock signal terminal CLKD2 of the first stage shift register 100 in each second shift register group C; and the second stage in each first shift register group C
  • the fifth clock signal terminal CLKD1 of the shift register 100 and the third sub-clock signal line CKD_3 of the fifth clock signal terminal CLKD1 of the second stage shift register 100 in each second shift register group C are electrically connected;
  • the timing of the fifth clock signal transmitted by the signal terminal CLKD1 may be the same.
  • the timings of CKD_1 and CKD_9 shown in FIG. 46 can be combined as the timing of CKD_1 in this example.
  • the timing of the sixth clock signal may be the same.
  • the timings of CKD_2 and CKD_10 shown in FIG. 46 can be combined as the timing of CKD_2 in this example.
  • the fifth clock signal end CLKD1 of the second-stage shift register 100 in each first shift register group C and the fifth clock signal end CLKD1 of the second-stage shift register 100 in each second shift register group C are transmitted
  • the timing of the fifth clock signal may be the same.
  • the timing of CKD_3 and CKD_11 shown in FIG. 46 can be combined as the timing of CKD_3 in this example.
  • the sixth clock signal end CLKD2 of the second-stage shift register 100 in each first shift register group C and the sixth clock signal end CLKD2 of the second-stage shift register 100 in each second shift register group C are transmitted
  • the timing of the sixth clock signal may be the same.
  • the timing of CKD_4 and CKD_12 shown in FIG. 46 can be combined as the timing of CKD_4 in this example.
  • the timing of the fifth clock signal may be the same.
  • the timings of CKD_5 and CKD_13 shown in FIG. 46 can be combined as the timing of CKD_5 in this example.
  • the timing of the sixth clock signal may be the same.
  • the timings of CKD_6 and CKD_14 shown in FIG. 46 can be combined as the timing of CKD_6 in this example.
  • the timing of the fifth clock signal may be the same.
  • the timings of CKD_7 and CKD_15 shown in FIG. 46 can be combined as the timing of CKD_7 in this example.
  • the timing of the sixth clock signal may be the same.
  • the timings of CKD_8 and CKD_16 shown in FIG. 46 can be combined as the timing of CKD_8 in this example.
  • the working process of the scan driving circuit 1000 in this example is basically unchanged from the working process of the scanning driving circuit 1000 in the example using 2N third sub-clock signal lines CKD. This is beneficial to reduce the number of signal lines included in the scan driving circuit 1000 and simplify the structure of the scan driving circuit 1000 .
  • the sub-pixel P in the display device 2000 can display a black screen and increase the MPRT
  • other ways can also be used to combine the third sub-clock signal line CKD, which is not limited in this disclosure. .
  • the timings of CKD_1 , CKD_3 , CKD_5 and CKD_7 in this example can be the same, and then CKD_1 , CKD_3 , CKD_5 and CKD_7 can be combined into CKD_1 , so that the scan driving circuit 1000 only includes five third sub-clock signal lines CKD. This is beneficial to further reducing the number of signal lines included in the scan driving circuit 1000 and further simplifying the structure of the scan driving circuit 1000 .
  • the third clock signal The line group 600 may include 4N third sub clock signal lines CKD.
  • 4N third sub-clock signal lines CKD 2N third sub-clock signal lines CKD are respectively electrically connected to the fifth clock signal terminal CLKD1 of each shift register 100 in the first shift register group C, and the other 2N
  • Each of the third sub-clock signal lines CKD is electrically connected to the fifth clock signal terminal CLKD1 of each shift register 100 in the second shift register group D, respectively.
  • the second output circuit 32 is not electrically connected to the sixth clock signal terminal CLKD2 , corresponding signal lines can be avoided, thereby reducing the number of signal lines included in the scan driving circuit 1000 and simplifying the structure of the scan driving circuit 1000 .
  • the scan driving circuit 1000 may further include: a fourth sub-clock signal line electrically connected to the second reset signal terminal BTRST of each shift register 100 CLK is electrically connected, and the start signal line BSTV is electrically connected to the black plug-in cascade signal terminal BCR of the first at least two stages of shift registers 100 .
  • the scan driving circuit 1000 may also include signal lines electrically connected to other signal terminals (such as the global reset signal terminal TRST or various voltage signal terminals, etc.), which will not be repeated here.
  • C ⁇ 1-8>, D ⁇ 9-16>, C ⁇ 17-24>, D ⁇ 25-32>...C ⁇ 1081- 1088>, D ⁇ 1089-1096> represent each shift register group (that is, the first shift register group C or the second shift register group D) and the four-stage shift register 100 in each shift register group, wherein each stage shifts
  • the bit register 100 includes a first scanning unit 1 and a second scanning unit 3 .
  • one scan signal terminal is electrically connected to a row of sub-pixels P.
  • the level of the start signal transmitted by the start signal line BSTV and the level of the first control signal transmitted by the first sub-control signal line BCK1 are both at high level.
  • the black insertion control subcircuit 21 of each shift register 100 is turned on, wherein the fifth transistor M5 in the black insertion control subcircuit 21 can receive and transmit the start signal to
  • the first inserted black node M charges the first inserted black node M so that the voltage of the first inserted black node M ⁇ 1/3/5/7> is at a high level.
  • the 1081st to 1084th output circuits are turned on, and sequentially transmit high-level clock signals to the sub-pixels P in the 1081st to 1084th rows, so that the subpixels P in the 1081st to 1084th rows Display operations are performed sequentially.
  • the black insertion circuit 2 in the 136th shift register group that is, the first shift register group C
  • the first black insertion node M ⁇ 1081 /1083/1085/1087> for charging raising the voltage of the first black node M ⁇ 1081/1083/1085/1087> in the 136th shift register group C.
  • the level of the second control signal transmitted by the third sub-control signal line BCK2 becomes high level.
  • the first black insertion subcircuit 23 and the second black insertion transmission subcircuit 24 of each shift register 100 are turned on, wherein the first black insertion transmission subcircuit 23
  • the seventh transistor M7 can transmit the high-level black insertion input signal to the first pull-up node Q ⁇ 1>
  • the eighth transistor M8 in the second black insertion transmission sub-circuit 24 can transmit the high-level black insertion input signal Transmitted to the second pull-up node Q ⁇ 2>. Therefore, the voltage of the pull-up node Q ⁇ 1-8> in the first shift register group C can be increased.
  • the levels of the clock signals transmitted by CKE_9 ⁇ CKE_16 become high level
  • the level of the second clock signal transmitted by CKD_10/12/14/16 becomes high level
  • the second The level of the first control signal transmitted by the control signal line BCK2 becomes high level.
  • the scanning signals output by each output circuit are all high level.
  • the level of the data signal is at a low level, so that the driving transistor T2 of the corresponding sub-pixel P is turned off, and then the sub-pixels P in the 1st to 8th rows display a black picture, realizing black insertion.
  • each second shift signal terminal CR2 ⁇ 2/4/6/8> in the first first shift register group C outputs a high-level second clock signal.
  • the black insertion control subcircuit 21 of each shift register 100 can be turned on under the control of the first control signal, and receive the above-mentioned second shift signal terminals CR2 ⁇ 2/4
  • the high-level second clock signal output by /6/8> charges each first black insertion node M ⁇ 9/11/13/15>, and makes M ⁇ 9/11/13/15> The high level remains until the next stage of black insertion.
  • the level of the second reset signal transmitted by the fourth sub-clock signal line CLK is high level, and the voltage of the first black insertion node M ⁇ 1/3/5/7> is high level .
  • each second reset circuit 14 and each fourth reset circuit 34 control the voltage of the second reset signal and the first black node M ⁇ 1/3/5/7> Down conduction, the first voltage signal is transmitted to each pull-up node Q ⁇ 1-8>, and pull-down reset is performed on each pull-up node Q ⁇ 1-8>.
  • the voltage of M ⁇ 1081-1088> is at low level, the voltage of Q ⁇ 1081-1088> can remain at high level.
  • the level of the first control signal transmitted by the first sub-control signal line BCK1 is high level.
  • the black insertion control subcircuit 21 of each shift register 100 is turned on, and a low-level start signal is transmitted to each first black insertion node M for charging, so that each second black insertion node M is charged.
  • the voltage of the one-plug black node M ⁇ 1/3/5/7> is low level.
  • the 1085th-1088th output circuits are turned on, and sequentially transmit high-level clock signals to the sub-pixels P in the 1085th-1088th row, so that the sub-pixels P in the 1085th-1088th row perform display operations in sequence.
  • the first stage T1 to the tenth stage T10 mentioned above can be continuously cycled to realize the combination of display and black insertion.
  • the black insertion of sub-pixels P in rows 1-8 is only an implementation solution, and any first shift register group C and second shift register group C can also be set.
  • the sub-pixel P corresponding to the shift register group D performs display and black insertion.
  • the sixth stage T6 and the fifth stage T5 can be performed synchronously, and the tenth stage T10 and the eighth stage T8 can also be performed synchronously.
  • the working timing diagram of the scanning driving circuit 1000 can be shown in FIG. 47 . This helps to reduce the time required to display a black screen and improve display efficiency.
  • one scan signal terminal is electrically connected to a row of sub-pixels P.
  • the scan signal terminals of the first two stages of shift registers 100 can be suspended.
  • the scanning signal terminals ie, the first scanning signal terminal and the second scanning signal terminal
  • the scanning signal terminals ie, the first scanning signal terminal and the second scanning signal terminal
  • the driving method of the scanning driving circuit 1000 are not suspended as an example, so as to describe the driving method of the scanning driving circuit 1000 .
  • the level of the start signal transmitted by the start signal line BSTV is high level.
  • the black insertion control subcircuit 21 of each shift register 100 is turned on.
  • the level of the first control signal transmitted by the first sub-control signal line BCK1 is high level.
  • each black insertion control subcircuit 21 can receive and transmit a start signal to the first black insertion node M, and charge the first black insertion node M, so that the first black insertion node M
  • the voltage of M ⁇ 1/3/5/7> is high level.
  • the level of the second reset signal transmitted by the fourth sub-clock signal line CLK is high level.
  • the pull-up nodes of the scanning units whose voltage at the first black node M is at a high level can be pulled down to reset.
  • the 25th to 28th output circuits are turned on, and sequentially transmit high-level clock signals to the sub-pixels P in the 25th to 28th rows, so that the subpixels P in the 25th to 28th rows perform display operations in sequence.
  • the black insertion circuit 2 in the fourth shift register group that is, the second shift register group D
  • the voltages of the pull-up nodes Q ⁇ 25/27/29/31> in the fourth shift register group are also elevated to a high level.
  • the level of the second control signal transmitted by the third sub-control signal line BCK3 is high level.
  • the first black insertion subcircuit 23 and the second black insertion transmission subcircuit 24 of each shift register 100 are turned on, wherein the first black insertion transmission subcircuit 23
  • the seventh transistor M7 can transmit the high-level black insertion input signal to the first pull-up node Q ⁇ 1>
  • the eighth transistor M8 in the second black insertion transmission sub-circuit 24 can transmit the high-level black insertion input signal Transmitted to the second pull-up node Q ⁇ 2>. Therefore, the voltage of the pull-up node Q ⁇ 1-8> in the first shift register group C can be increased.
  • the levels of the clock signals transmitted by CKE_9 ⁇ CKE_16 become high level
  • the level of the second clock signal transmitted by CKD_10/12/14/16 becomes high level
  • the second The level of the first control signal transmitted by the control signal line BCK2 becomes high level.
  • the scanning signals output by each output circuit are all high level.
  • the level of the data signal is at a low level, so that the driving transistor T2 of the corresponding sub-pixel P is turned off, and then the sub-pixels P in the 1st to 8th rows display a black picture, realizing black insertion.
  • each second shift signal terminal CR2 ⁇ 2/4/6/8> in the first first shift register group C outputs a high-level second clock signal.
  • the black insertion control subcircuit 21 of each shift register 100 can be turned on under the control of the first control signal, and receive the above-mentioned second shift signal terminals CR2 ⁇ 2/4
  • the high-level second clock signal output by /6/8> charges each first black insertion node M ⁇ 9/11/13/15>, and makes M ⁇ 9/11/13/15> The high level remains until the next stage of black insertion.
  • the voltage of the pull-up node Q ⁇ 25-32> is high level, and the second shift signal terminal CR2 ⁇ 28/30/32/34> of the corresponding output circuit will output the second shift signal,
  • the level of the first control signal received by the black insertion control sub-circuit 21 in the fifth shift register group that is, C ⁇ 33-40>
  • the level of the first control signal received by the black insertion control sub-circuit 21 in the fifth shift register group that is, C ⁇ 33-40>
  • the level of the second reset signal transmitted by the fourth sub-clock signal line CLK is high level.
  • each second reset circuit 14 and each fourth reset circuit 34 Since the voltage of the first black insertion node M ⁇ 1/3/5/7> is high level, in the first first shift register group C, each second reset circuit 14 and each fourth reset circuit 34 The second reset signal and the voltage of the first plug-in black node M ⁇ 1/3/5/7> are turned on, and the first voltage signal is transmitted to each pull-up node Q ⁇ 1-8>, and each pull-up node Q ⁇ 1-8> perform pull-down reset.
  • the voltage of the pull-up node Q ⁇ 24-32> remains at a high level.
  • the level of the first control signal transmitted by the first sub-control signal line BCK1 is high level.
  • the black insertion control subcircuit 21 of each shift register 100 is turned on, and a low-level start signal is transmitted to each first black insertion node M for charging, so that each second black insertion node M is charged.
  • the voltage of the one-plug black node M ⁇ 1/3/5/7> is low level.
  • the 29th to 32nd output circuits are turned on, and sequentially transmit high-level clock signals to the sub-pixels P in the 29th to 32nd rows, so that the subpixels P in the 29th to 32nd rows perform display operations in sequence.
  • This continuous cycle can realize the combination of display and black insertion.
  • the black insertion of the sub-pixels P in the 1st-8th row is only an implementation solution, and any first shift register group C and second shift register group C can also be set.
  • the sub-pixel P corresponding to the shift register group D performs display and black insertion.
  • one scan signal terminal is electrically connected to a row of sub-pixels P.
  • the second shift signal is used as the display input signal
  • the first shift signal is used as the black insertion cascade signal.
  • the black insertion output stage can be combined To the CKE_5 and output stage of the third stage T3, since the CKE_5 output of this stage is the pulse width of two lines, the pulse width of the previous line does not write the display data, so that the black CKE can be used to write the black data
  • the pull-up node Q of the row where the voltage of the first black insertion node M is at a high level can be reset immediately after the black insertion data is written. In this way, compared with the shift register without the black insertion function, only the time of the pre-charge stage of CKE_5 is increased, and the output of the shift register at a high refresh rate will not be affected.

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Abstract

一种移位寄存器（100），与至少一行子像素电连接。移位寄存器（100）包括：第一扫描单元（1）和插黑电路（2）。第一扫描单元（1）包括：第一输入电路（11）和第一输出电路（12）。第一输入电路（11）被配置为，将显示输入信号传输至第一上拉节点。第一输出电路（12）被配置为，在第一输入电路（11）将显示输入信号传输至第一上拉节点的情况下，将在第一时钟信号端处接收的第一时钟信号传输至第一扫描信号端，驱动至少一行子像素进行图像显示。插黑电路（2）被配置为，将插黑输入信号传输至第一上拉节点。第一输出电路（12）还被配置为，在插黑电路（2）将插黑输入信号传输至第一上拉节点的情况下，在第一上拉节点的电压的控制下，将第一时钟信号传输至第一扫描信号端，驱动至少一行子像素进行黑画面显示。

Description

移位寄存器、扫描驱动电路及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器、扫描驱动电路及显示装置。
背景技术
扫描驱动电路为显示装置中的重要组成部分。扫描驱动电路可以包括多级级联的移位寄存器，每一级移位寄存器可以与显示装置中的至少一行走线电连接电连接。扫描驱动电路可以向显示装置中的多条走线(例如栅线或使能信号线等)中逐行输入扫描信号，以使得显示装置能够进行画面显示。
在显示装置中设置扫描驱动电路，能够有效降低成本、提高良率。
发明内容
一方面，提供一种移位寄存器。所述移位寄存器，应用于显示装置，所述显示装置包括多行子像素。所述移位寄存器与至少一行子像素电连接。所述移位寄存器包括：第一扫描单元和插黑电路。所述第一扫描单元包括：第一输入电路和第一输出电路。所述第一输入电路与显示输入信号端及第一上拉节点电连接；所述第一输入电路被配置为，响应于在所述显示输入信号端处接收的显示输入信号，将所述显示输入信号传输至所述第一上拉节点。所述第一输出电路与所述第一上拉节点、第一时钟信号端及第一扫描信号端电连接；所述第一输出电路被配置为，在所述第一输入电路将所述显示输入信号传输至所述第一上拉节点的情况下，在所述第一上拉节点的电压的控制下，将在所述第一时钟信号端处接收的第一时钟信号传输至所述第一扫描信号端，驱动所述至少一行子像素进行图像显示。所述插黑电路与第一控制信号端、插黑级联信号端、第二控制信号端、插黑输入信号端、所述第一上拉节点及第一电压信号端电连接；所述插黑电路被配置为，在所述第一控制信号端所传输的第一控制信号、所述插黑级联信号端所传输的插黑级联信号及所述第二控制信号端所传输的第二控制信号的控制下，将在所述插黑输入信号端处接收的插黑输入信号传输至所述第一上拉节点。所述输出电路还被配置为，在所述插黑电路将所述插黑输入信号传输至所述第一上拉节点的情况下，在所述第一上拉节点的电压的控制下，将所述第一时钟信号传输至所述第一扫描信号端，驱动所述至少一行子像素进行黑画面显示。
在一些实施例中，所述移位寄存器，还包括：第二扫描单元。所述第二扫描单元包括：第二输入电路和第二输出电路。所述第二输入电路与所述显示输入信号端及第二上拉节点电连接；所述第二输入电路被配置为，响应于在所述显示输入信号，将所述显示输入信号传输至所述第二上拉节点。所述第二输出电路与所述第二上拉节点、第二时钟信号端及第二扫描信号端电连接；所述第二输出电路被配置为，在所述第二输入电路将所述显示输入信号传输至所述第二上拉节点的情况下，在所述第二上拉节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述第二扫描信号端，驱动所述至少一行子像素进行图像显示。所述插黑电路还与所述第二上拉节点电连接；所述插黑电路还被配置为，在将所述插黑输入信号传输至所述第一上拉节点的同时，将所述插黑输入信号传输至所述第二上拉节点。所述输出电路还被配置为，在所述插黑电路将所述插黑输入信号传输至所述第二上拉节点的情况下，在所述第二上拉节点的电压的控制下，将所述第二时钟信号传输至所述第二扫描信号端，驱动所述至少一行子像素进行黑画面显示。
在一些实施例中，所述插黑电路包括：插黑控制子电路、插黑输入子电路和第一插黑 传输子电路。所述插黑控制子电路与所述第一控制信号端、所述插黑级联信号端、所述第一电压信号端及第一插黑节点电连接；所述插黑控制子电路被配置为，在所述第一控制信号的控制下，将所述插黑级联信号传输至所述第一插黑节点。所述插黑输入子电路与所述第一插黑节点、所述插黑输入信号端及第二插黑节点电连接；所述插黑输入子电路被配置为，在所述第一插黑节点的电压的控制下，将所述插黑输入信号传输至所述第二插黑节点。所述第一插黑传输子电路与所述第二控制信号端、所述第二插黑节点及所述第一上拉节点电连接；所述第一插黑传输子电路被配置为，在所述第二控制信号的控制下，将来自所述第二插黑节点的插黑输入信号传输至所述第一上拉节点。在所述移位寄存器还包括第二扫描单元的情况下，所述插黑电路还包括：第二插黑传输子电路。所述第二插黑传输子电路与所述第二控制信号端、所述第二插黑节点及所述第二上拉节点电连接；所述第二插黑传输子电路被配置为，在所述第二控制信号的控制下，将来自所述第二插黑节点的插黑输入信号传输至所述第二上拉节点。
在一些实施例中，所述第一输入电路包括：第一晶体管。所述第一晶体管的控制极与所述显示输入信号端电连接，所述第一晶体管的第一极与所述显示输入信号端电连接，所述第一晶体管的第二极与所述第一上拉节点电连接。所述第一输出电路包括：第二晶体管和第一电容器。所述第二晶体管的控制极与所述第一上拉节点电连接，所述第二晶体管的第一极与所述第一时钟信号端电连接，所述第二晶体管的第二极与所述第一扫描信号端电连接。所述第一电容器的第一端与所述第一上拉节点电连接，所述第一电容器的第二端与所述第一扫描信号端电连接。在所述移位寄存器还包括第二扫描单元的情况下，所述第二输入电路包括：第三晶体管。所述第三晶体管的控制极与所述显示输入信号端电连接，所述第三晶体管的第一极与所述显示输入信号端电连接，所述第三晶体管的第二极与所述第二上拉节点电连接。所述第二输出电路包括：第四晶体管和第二电容器。所述第四晶体管的控制极与所述第二上拉节点电连接，所述第四晶体管的第一极与所述第二时钟信号端电连接，所述第四晶体管的第二极与所述第二扫描信号端电连接。所述第二电容器的第一端与所述第二上拉节点电连接，所述第二电容器的第二端与所述第二扫描信号端电连接。在所述插黑电路包括插黑控制子电路、插黑输入子电路、第一插黑传输子电路及第二插黑传输子电路的情况下，所述插黑控制子电路包括：第五晶体管和第三电容器。所述第五晶体管的控制极与所述第一控制信号端电连接，所述第五晶体管的第一极与所述插黑级联信号端电连接，所述第五晶体管的第二极与所述第一插黑节点电连接。所述第三电容器的第一端与所述第一插黑节点电连接，所述第三电容器的第二端与所述第一电压信号端电连接。所述插黑输入子电路包括：第六晶体管。所述第六晶体管的控制极与所述第一插黑节点电连接，所述第六晶体管的第一极与所述插黑输入信号端电连接，所述第六晶体管的第二极与所述第二插黑节点电连接。所述第一插黑传输子电路包括：第七晶体管。所述第七晶体管的控制极与所述第二控制信号端电连接，所述第七晶体管的第一极与所述第二插黑节点电连接，所述第七晶体管的第二极与所述第一上拉节点电连接。所述第二插黑传输子电路包括：第八晶体管。所述第八晶体管的控制极与所述第二控制信号端电连接，所述第八晶体管的第一极与所述第二插黑节点电连接，所述第八晶体管的第二极与所述第二上拉节点电连接。
在一些实施例中，所述第一输出电路还与第三时钟信号端及第一感测信号端电连接。所述第一输出电路还被配置为，在所述第一输入电路将所述显示输入信号传输至所述第一 上拉节点的情况下，在所述第一上拉节点的电压的控制下，将在所述第三时钟信号端处接收的第三时钟信号传输至所述第一感测信号端，驱动所述至少一行子像素进行复位；或，在所述插黑电路将所述插黑输入信号传输至所述第一上拉节点的情况下，在所述第一上拉节点的电压的控制下，将所述第三时钟信号传输至所述第一感测信号端，驱动所述至少一行子像素进行黑画面显示。在所述移位寄存器还包括第二扫描单元的情况下，所述第二输出电路还与第四时钟信号端及第二感测信号端电连接。所述第二输出电路还被配置为，在所述第二输入电路将所述显示输入信号传输至所述第二上拉节点的情况下，在所述第二上拉节点的电压的控制下，将在所述第四时钟信号端处接收的第四时钟信号传输至所述第二感测信号端，驱动所述至少一行子像素进行复位；或，在所述插黑电路将所述插黑输入信号传输至所述第二上拉节点的情况下，在所述第二上拉节点的电压的控制下，将所述第四时钟信号传输至所述第二感测信号端，驱动所述至少一行子像素进行黑画面显示。
在一些实施例中，所述第一输出电路还包括：第九晶体管和第四电容器。所述第九晶体管的控制极与所述第一上拉节点电连接，所述第九晶体管的第一极与所述第三时钟信号端电连接，所述第九晶体管的第二极与所述第一感测信号端电连接。所述第四电容器的第一端与所述第一上拉节点电连接，所述第四电容器的第二端与所述第一感测信号端电连接。所述第二输出电路还包括：第十晶体管和第五电容器。所述第十晶体管的控制极与所述第二上拉节点电连接，所述第十晶体管的第一极与所述第四时钟信号端电连接，所述第十晶体管的第二极与所述第二感测信号端电连接。所述第五电容器的第一端与所述第二上拉节点电连接，所述第五电容器的第二端与所述第二感测信号端电连接。
在一些实施例中，所述第一输出电路还与第五时钟信号端及第一移位信号端电连接。所述第一输出电路还被配置为，在所述第一上拉节点的电压的控制下，将在所述第五时钟信号端处接收的第五时钟信号传输至所述第一移位信号端。
在一些实施例中，所述第一输出电路还包括：第十一晶体管。所述第十一晶体管的控制极与所述第一上拉节点电连接，所述第十一晶体管的第一极与所述第五时钟信号端电连接，所述第十一晶体管的第二极与所述第一移位信号端电连接。
在一些实施例中，在所述移位寄存器还包括第二扫描单元的情况下，所述第二输出电路还与第六时钟信号端及第二移位信号端电连接。所述第二输出电路还被配置为，在所述第二上拉节点的电压的控制下，将在所述第六时钟信号端处接收的第六时钟信号传输至所述第二移位信号端。
在一些实施例中，所述第二输出电路还包括：第十二晶体管。所述第十二晶体管的控制极与所述第二上拉节点电连接，所述第十二晶体管的第一极与所述第六时钟信号端电连接，所述第十二晶体管的第二极与所述第二移位信号端电连接。
在一些实施例中，所述第一扫描单元还包括：第一复位电路和第二复位电路。所述第一复位电路与第一复位信号端、所述第一上拉节点及所述第一电压信号端电连接；所述第一复位电路被配置为，在所述第一复位信号端所传输的第一复位信号的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述第一上拉节点。在所述插黑电路包括插黑控制子电路的情况下，所述第二复位电路与第二复位信号端、所述第一插黑节点、所述第一上拉节点及所述第一电压信号端电连接；所述第二复位电路被配置为，在所述第一插黑节点的电压及所述第二复位信号端所传输的第二复位信号的控制下，将所述第一电压信号传输至所述第一上拉节点。在所述移位寄存器还包括第二扫描单元的情况下，所述第二 扫描单元还包括：第三复位电路和第四复位电路。所述第三复位电路与所述第一复位信号端、所述第二上拉节点及所述第一电压信号端电连接；所述第三复位电路被配置为，在所述第一复位信号的控制下，将所述第一电压信号传输至所述第二上拉节点。所述第四复位电路与所述第二复位信号端、所述第一插黑节点、所述第二上拉节点及所述第一电压信号端电连接；所述第四复位电路被配置为，在所述第一插黑节点的电压及所述第二复位信号的控制下，将所述第一电压信号传输至所述第二上拉节点。
在一些实施例中，所述第一复位电路包括：第十三晶体管。所述第十三晶体管的控制极与所述第一复位信号端电连接，所述第十三晶体管的第一极与所述第一上拉节点电连接，所述第十三晶体管的第二极与所述第一电压信号端电连接。所述第二复位电路包括：第十四晶体管和第十五晶体管。所述第十四晶体管的控制极与所述第一插黑节点电连接，所述第十四晶体管的第一极与所述第一上拉节点电连接，所述第十四晶体管的第二极与所述第十五晶体管的第一极电连接。所述第十五晶体管的控制极与所述第二复位信号端电连接，所述第十五晶体管的第二极与所述第一电压信号端电连接。所述第三复位电路包括：第十六晶体管。所述第十六晶体管的控制极与所述第一复位信号端电连接，所述第十六晶体管的第一极与所述第二上拉节点电连接，所述第十六晶体管的第二极与所述第一电压信号端电连接。所述第四复位电路包括：第十七晶体管和第十八晶体管。所述第十七晶体管的控制极与所述第一插黑节点电连接，所述第十七晶体管的第一极与所述第二上拉节点电连接，所述第十七晶体管的第二极与所述第十八晶体管的第一极电连接。所述第十八晶体管的控制极与所述第二复位信号端电连接，所述第十八晶体管的第二极与所述第一电压信号端电连接。
在一些实施例中，所述第一扫描单元还包括：第一控制电路，与所述第一上拉节点、第一下拉节点、所述第一电压信号端及第二电压信号端电连接；所述第一控制电路被配置为，响应于在所述第二电压信号端处接收的第二电压信号，将所述第二电压信号传输至所述第一下拉节点，并且，在所述第一上拉节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述第一下拉节点。在所述移位寄存器还包括第二扫描单元的情况下，所述第二扫描单元还包括：第二控制电路，与所述第二上拉节点、第二下拉节点、所述第一电压信号端及第三电压信号端电连接；所述第二控制电路被配置为，响应于在所述第三电压信号端处接收的第三电压信号，将所述第三电压信号传输至所述第二下拉节点，并且，在所述第二上拉节点的电压的控制下，将所述第一电压信号传输至所述第二下拉节点。
在一些实施例中，所述第一控制电路包括：第十九晶体管、第二十晶体管、第二十一晶体管和第二十二晶体管。所述第十九晶体管的控制极与所述第二电压信号端电连接，所述第十九晶体管的第一极与所述第二电压信号端电连接，所述第十九晶体管的第二极与所述第二十晶体管的控制极及所述第二十一晶体管的第一极电连接。所述第二十晶体管的第一极与所述第二电压信号端电连接，所述第二十晶体管的第二极与所述第一下拉节点电连接。所述第二十一晶体管的控制极与所述第一上拉节点电连接，所述第二十一晶体管的第二极与所述第一电压信号端电连接。所述第二十二晶体管的控制极与所述第一上拉节点电连接，所述第二十二晶体管的第一极与所述第一下拉节点电连接，所述第二十二晶体管的第二极与所述第一电压信号端电连接。所述第二控制电路包括：第二十三晶体管、第二十四晶体管、第二十五晶体管和第二十六晶体管。所述第二十三晶体管的控制极与所述第三 电压信号端电连接，所述第二十三晶体管的第一极与所述第三电压信号端电连接，所述第二十三晶体管的第二极与所述第二十四晶体管的控制极及所述第二十五晶体管的第一极电连接。所述第二十四晶体管的第一极与所述第三电压信号端电连接，所述第二十四晶体管的第二极与所述第二下拉节点电连接。所述第二十五晶体管的控制极与所述第二上拉节点电连接，所述第二十五晶体管的第二极与所述第一电压信号端电连接。所述第二十六晶体管的控制极与所述第二上拉节点电连接，所述第二十六晶体管的第一极与所述第二下拉节点电连接，所述第二十六晶体管的第二极与所述第一电压信号端电连接。
在一些实施例中，所述第一扫描单元还包括：第五复位电路、第六复位电路和第七复位电路。所述第五复位电路与所述第一下拉节点、所述第一上拉节点及所述第一电压信号端电连接；所述第五复位电路被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压信号传输至所述第一上拉节点。所述第六复位电路与所述第一下拉节点、所述第一扫描信号端及第四电压信号端电连接；所述第六复位电路被配置为，在所述第一下拉节点的电压的控制下，将在所述第四电压信号端处接收的第四电压信号传输至所述第一扫描信号端。在所述第一输出电路还与第三时钟信号端及第一感测信号端电连接的情况下，所述第六复位电路还与所述第一感测信号端电连接；所述第六复位电路还被配置为，在所述第一下拉节点的电压的控制下，将所述第四电压信号传输至所述第一感测信号端。在所述第一输出电路还与第五时钟信号端及第一移位信号端电连接的情况下，所述第六复位电路还与所述第一移位信号端及所述第一电压信号端电连接；所述第六复位电路还被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压信号传输至所述第一移位信号端。在所述插黑电路包括插黑控制子电路的情况下，所述第七复位电路与所述第一插黑节点、所述第二控制信号端、所述第一下拉节点及所述第一电压信号端电连接；所述第七复位电路被配置为，在所述第一插黑节点的电压及所述第二控制信号的控制下，将所述第一电压信号传输至所述第一下拉节点。所述第二扫描单元还包括：第八复位电路、第九复位电路和第十复位电路。所述第八复位电路与所述第二下拉节点、所述第二上拉节点及所述第一电压信号端电连接；所述第八复位电路被配置为，在所述第二下拉节点的电压的控制下，将所述第一电压信号传输至所述第二上拉节点。所述第九复位电路与所述第二下拉节点、所述第二扫描信号端及所述第四电压信号端电连接；所述第九复位电路被配置为，在所述第二下拉节点的电压的控制下，将所述第四电压信号传输至所述第二扫描信号端。在所述第二输出电路还与第四时钟信号端及第二感测信号端电连接的情况下，所述第九复位电路还与所述第二感测信号端电连接；所述第九复位电路还被配置为，在所述第二下拉节点的电压的控制下，将所述第四电压信号传输至所述第二感测信号端。在所述第二输出电路还与第六时钟信号端及第二移位信号端电连接的情况下，所述第九复位电路还与所述第二移位信号端及所述第一电压信号端电连接；所述第九复位电路还被配置为，在所述第二下拉节点的电压的控制下，将所述第一电压信号传输至所述第二移位信号端。所述第十复位电路与所述第一插黑节点、所述第二控制信号端、所述第二下拉节点及所述第一电压信号端电连接；所述第十复位电路被配置为，在所述第一插黑节点的电压及所述第二控制信号的控制下，将所述第一电压信号传输至所述第二下拉节点。
在一些实施例中，所述第五复位电路包括：第二十七晶体管。所述第二十七晶体管的控制极与所述第一下拉节点电连接，所述第二十七晶体管的第一极与所述第一上拉节点电连接，所述第二十七晶体管的第二极与所述第一电压信号端电连接。所述第六复位电路包 括：第二十八晶体管、第二十九晶体管和第三十晶体管。所述第二十八晶体管的控制极与所述第一下拉节点电连接，所述第二十八晶体管的第一极与所述第一扫描信号端电连接，所述第二十八晶体管的第二极与所述第四电压信号端电连接。所述第二十九晶体管的控制极与所述第一下拉节点电连接，所述第二十九晶体管的第一极与所述第一感测信号端电连接，所述第二十九晶体管的第二极与所述第四电压信号端电连接。所述第三十晶体管的控制极与所述第一下拉节点电连接，所述第三十晶体管的第一极与所述第一移位信号端电连接，所述第三十晶体管的第二极与所述第一电压信号端电连接。所述第七复位电路包括：第三十一晶体管和第三十二晶体管。所述第三十一晶体管的控制极与所述第一插黑节点电连接，所述第三十一晶体管的第一极与所述第一下拉节点电连接，所述第三十一晶体管的第二极与所述第三十二晶体管的第一极电连接。所述第三十二晶体管的控制极与所述第二控制信号端电连接，所述第三十二晶体管的第二极与所述第一电压信号端电连接。所述第八复位电路包括：第三十三晶体管。所述第三十三晶体管的控制极与所述第二下拉节点电连接，所述第三十三晶体管的第一极与所述第二上拉节点电连接，所述第三十三晶体管的第二极与所述第一电压信号端电连接。所述第九复位电路包括：第三十四晶体管、第三十五晶体管和第三十六晶体管。所述第三十四晶体管的控制极与所述第二下拉节点电连接，所述第三十四晶体管的第一极与所述第二扫描信号端电连接，所述第三十四晶体管的第二极与所述第四电压信号端电连接。所述第三十五晶体管的控制极与所述第二下拉节点电连接，所述第三十五晶体管的第一极与所述第二感测信号端电连接，所述第三十五晶体管的第二极与所述第四电压信号端电连接。所述第三十六晶体管的控制极与所述第二下拉节点电连接，所述第三十六晶体管的第一极与所述第二移位信号端电连接，所述第三十六晶体管的第二极与所述第一电压信号端电连接。所述第十复位电路包括：第三十七晶体管和第三十八晶体管。所述第三十七晶体管的控制极与所述第一插黑节点电连接，所述第三十七晶体管的第一极与所述第二下拉节点电连接，所述第三十七晶体管的第二极与所述第三十八晶体管的第一极电连接。所述第三十八晶体管的控制极与所述第二控制信号端电连接，所述第三十八晶体管的第二极与所述第一电压信号端电连接。
在一些实施例中，所述第五复位电路还与所述第二下拉节点电连接；所述第五复位电路还被配置为，在所述第二下拉节点的电压的控制下，将所述第一电压信号传输至所述第一上拉节点。所述第六复位电路还与所述第二下拉节点电连接；所述第六复位电路还被配置为，在所述第二下拉节点的电压的控制下，将所述第四电压信号传输至所述第一扫描信号端，将所述第四电压信号传输至所述第一感测信号端，将所述第一电压信号传输至所述第一移位信号端。所述第八复位电路还与所述第一下拉节点电连接；所述第八复位电路还被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压信号传输至所述第二上拉节点。所述第九复位电路还与所述第一下拉节点电连接；所述第九复位电路还被配置为，在所述第一下拉节点的电压的控制下，将所述第四电压信号传输至所述第二扫描信号端，将所述第四电压信号传输至所述第二感测信号端，将所述第一电压信号传输至所述第二移位信号端。
在一些实施例中，所述第五复位电路还包括：第三十九晶体管。所述第三十九晶体管的控制极与所述第二下拉节点电连接，所述第三十九晶体管的第一极与所述第一上拉节点电连接，所述第三十九晶体管的第二极与所述第一电压信号端电连接。所述第六复位电路还包括：第四十晶体管、第四十一晶体管和第四十二晶体管。所述第四十晶体管的控制极 与所述第二下拉节点电连接，所述第四十晶体管的第一极与所述第一扫描信号端电连接，所述第四十晶体管的第二极与所述第四电压信号端电连接。所述第四十一晶体管的控制极与所述第二下拉节点电连接，所述第四十一晶体管的第一极与所述第一感测信号端电连接，所述第四十一晶体管的第二极与所述第四电压信号端电连接。所述第四十二晶体管的控制极与所述第二下拉节点电连接，所述第四十二晶体管的第一极与所述第一移位信号端电连接，所述第四十二晶体管的第二极与所述第一电压信号端电连接。所述第八复位电路还包括：第四十三晶体管。所述第四十三晶体管的控制极与所述第一下拉节点电连接，所述第四十三晶体管的第一极与所述第二上拉节点电连接，所述第四十三晶体管的第二极与所述第一电压信号端电连接。所述第九复位电路还包括：第四十四晶体管、第四十五晶体管和第四十六晶体管。所述第四十四晶体管的控制极与所述第一下拉节点电连接，所述第四十四晶体管的第一极与所述第二扫描信号端电连接，所述第四十四晶体管的第二极与所述第四电压信号端电连接。所述第四十五晶体管的控制极与所述第一下拉节点电连接，所述第四十五晶体管的第一极与所述第二感测信号端电连接，所述第四十五晶体管的第二极与所述第四电压信号端电连接。所述第四十六晶体管的控制极与所述第一下拉节点电连接，所述第四十六晶体管的第一极与所述第二移位信号端电连接，所述第四十六晶体管的第二极与所述第一电压信号端电连接。
在一些实施例中，所述移位寄存器，还包括：消隐电路。所述消隐电路与第三控制信号端、所述显示输入信号端、第七时钟信号端、所述第一上拉节点及所述第一电压信号端电连接。所述消隐电路被配置为，在所述第三控制信号端所传输的第三控制信号、所述显示输入信号及所述第七时钟信号端所传输的第七时钟信号的控制下，将所述第七时钟信号传输至所述第一上拉节点。在所述移位寄存器还包括第二扫描单元的情况下，所述消隐电路还与所述第二上拉节点电连接；所述消隐电路还被配置为，将所述第七时钟信号传输至所述第二上拉节点。
在一些实施例中，所述消隐电路包括：选择控制子电路、消隐输入子电路、第一消隐传输子电路和第二消隐传输子电路。所述选择控制子电路与所述第三控制信号端、所述显示输入信号端、第一消隐节点及所述第一电压信号端电连接；所述选择控制子电路被配置为，在所述第三控制信号的控制下，将所述显示输入信号传输至所述第一消隐节点。所述消隐传输子电路与所述第一消隐节点、所述第七时钟信号端及第二消隐节点电连接；所述消隐传输子电路被配置为，在所述第一消隐节点的电压的控制下，将所述第七时钟信号传输至所述第二消隐节点。所述第一消隐传输子电路与所述第七时钟信号端、所述第二消隐节点及所述第一上拉节点电连接；所述第一消隐传输子电路被配置为，在所述第七时钟信号的控制下，将来自所述第二消隐节点的第七时钟信号传输至所述第一上拉节点。所述第二消隐传输子电路与所述第七时钟信号端、所述第二消隐节点及所述第二上拉节点电连接；所述第二消隐传输子电路被配置为，在所述第七时钟信号的控制下，将来自所述第二消隐节点的第七时钟信号传输至所述第二上拉节点。
在一些实施例中，所述选择控制子电路包括：第四十七晶体管和第六电容器。所述第四十七晶体管的控制极与所述第三控制信号端电连接，所述第四十七晶体管的第一极与所述显示输入信号端电连接，所述第四十七晶体管的第二极与所述第一消隐节点电连接。所述第六电容器的第一端与所述第一消隐节点电连接，所述第六电容器的第二端与所述第一电压信号端电连接。所述消隐输入子电路包括：第四十八晶体管。所述第四十八晶体管的 控制极与所述第一消隐节点电连接，所述第四十八晶体管的第一极与所述第七时钟信号端电连接，所述第四十八晶体管的第二极与所述第二消隐节点电连接。所述第一消隐传输子电路包括：第四十九晶体管。所述第四十九晶体管的控制极与所述第七时钟信号端电连接，所述第四十九晶体管的第一极与所述第二消隐节点电连接，所述第四十九晶体管的第二极与所述第一上拉节点电连接。所述第二消隐传输子电路包括：第五十晶体管。所述第五十晶体管的控制极与所述第七时钟信号端电连接，所述第五十晶体管的第一极与所述第二消隐节点电连接，所述第五十晶体管的第二极与所述第二上拉节点电连接。
在一些实施例中，所述第一扫描单元还包括：第十一复位电路、第十二复位电路及第十三复位电路。所述第十一复位电路与全局复位信号端、所述第一上拉节点及所述第一电压信号端电连接；所述第十一复位电路被配置为，在所述全局复位信号端所传输的全局复位信号的控制下，将所述第一电压信号传输至所述第一上拉节点。所述第十二复位电路与所述显示输入信号端、所述第一下拉节点及所述第一电压信号端电连接；所述第十二复位电路被配置为，在所述显示输入信号的控制下，将所述第一电压信号传输至所述第一下拉节点。在所述消隐电路包括选择控制子电路的情况下，所述第十三复位电路与所述第一消隐节点、所述第七时钟信号端、所述第一下拉节点及所述第一电压信号端电连接；所述第十三复位电路被配置为，在所述第一消隐节点的电压和所述第七时钟信号的控制下，将所述第一电压信号传输至所述第一下拉节点。所述第二扫描单元还包括：第十四复位电路、第十五复位电路及第十六复位电路。所述第十四复位电路与所述全局复位信号端、所述第二上拉节点及所述第一电压信号端电连接；所述第十四复位电路被配置为，在所述全局复位信号的控制下，将所述第一电压信号传输至所述第二上拉节点。所述第十五复位电路与所述显示输入信号端、所述第二下拉节点及所述第一电压信号端电连接；所述第十五复位电路被配置为，在所述显示输入信号的控制下，将所述第一电压信号传输至所述第二下拉节点。所述第十六复位电路与所述第一消隐节点、所述第七时钟信号端、所述第二下拉节点及所述第一电压信号端电连接；所述第十六复位电路被配置为，在所述第一消隐节点的电压和所述第七时钟信号的控制下，将所述第一电压信号传输至所述第二下拉节点。
在一些实施例中，所述第十一复位电路包括：第五十一晶体管。所述第五十一晶体管的控制极与所述全局复位信号端电连接，所述第五十一晶体管的第一极与所述第一上拉节点电连接，所述第五十一晶体管的第二极与所述第一电压信号端电连接。所述第十二复位电路包括：第五十二晶体管。所述第五十二晶体管的控制极与所述显示输入信号端电连接，所述第五十二晶体管的第一极与所述第一下拉节点电连接，所述第五十二晶体管的第二极与所述第一电压信号端电连接。所述第十三复位电路包括：第五十三晶体管和第五十四晶体管。所述第五十三晶体管的控制极与所述第一消隐节点电连接，所述第五十三晶体管的第一极与所述第一下拉节点电连接，所述第五十三晶体管的第二极与所述第五十四晶体管的第一极电连接。所述第五十四晶体管的控制极与所述第七时钟信号端电连接，所述第五十四晶体管的第二极与所述第一电压信号端电连接。所述第十四复位电路包括：第五十五晶体管。所述第五十五晶体管的控制极与所述全局复位信号端电连接，所述第五十五晶体管的第一极与所述第二上拉节点电连接，所述第五十五晶体管的第二极与所述第一电压信号端电连接。所述第十五复位电路包括：第五十六晶体管。所述第五十六晶体管的控制极与所述显示输入信号端电连接，所述第五十六晶体管的第一极与所述第二下拉节点电连接，所述第五十六晶体管的第二极与所述第一电压信号端电连接。所述第十六复位电路包 括：第五十七晶体管和第五十八晶体管。所述第五十七晶体管的控制极与所述第一消隐节点电连接，所述第五十七晶体管的第一极与所述第二下拉节点电连接，所述第五十七晶体管的第二极与所述第五十八晶体管的第一极电连接。所述第五十八晶体管的控制极与所述第七时钟信号端电连接，所述第五十八晶体管的第二极与所述第一电压信号端电连接。
在一些实施例中，所述移位寄存器，还包括：第一防漏电电路。所述第一防漏电电路与所述第一消隐节点、第五电压信号端及第一防漏电节点电连接；所述第一防漏电电路被配置为，在所述第一消隐节点的电压的控制下，将在所述第五电压信号端处接收的第五电压信号传输至所述第一防漏电节点。其中，所述选择控制子电路还与所述第一防漏电节点电连接。
在一些实施例中，所述第一防漏电电路包括：第五十九晶体管。所述第五十九晶体管的控制极与所述第一消隐节点电连接，所述第五十九晶体管的第一极与所述第五电压信号端电连接，所述第五十九晶体管的第二极与所述第一防漏电节点电连接。所述选择控制子电路还包括：第六十晶体管。所述第六十晶体管的控制极与所述第三控制信号端电连接，所述第六十晶体管的第一极与所述显示输入信号端电连接，所述第六十晶体管的第二极与所述第一防漏电节点电连接。所述选择控制子电路的第四十七晶体管的第一极与所述第一防漏电节点电连接，并通过所述第六十晶体管与所述显示输入信号端电连接。
在一些实施例中，所述移位寄存器，还包括：第二防漏电电路。所述第二防漏电电路与所述第一上拉节点、第五电压信号端及第二防漏电节点电连接；所述第二防漏电电路被配置为，在所述第一上拉节点的电压的控制下，将在所述第五电压信号端处接收的第五电压信号传输至所述第二防漏电节点。其中，所述第一输入电路还与所述第二防漏电节点电连接。在所述移位寄存器还包括第二扫描单元的情况下，所述第二输入电路还与所述第二防漏电节点电连接。所述插黑电路还与所述第二防漏电节点电连接。在所述第一扫描单元还包括第一复位电路和第二复位电路、所述第二扫描单元还包括第三复位电路和第四复位电路的情况下，所述第一复位电路、所述第二复位电路、所述第三复位电路和所述第四复位电路，还均与所述第二防漏电节点电连接。在所第一扫描单元还包括第五复位电路、所述第二扫描单元还包括及第八复位电路的情况下，所述第五复位电路和所述第八复位电路，还均与所述第二防漏电节点电连接。在所述移位寄存器还包括消隐电路的情况下，所述消隐电路还与第二防漏电节点电连接。在所第一扫描单元还包括第十一复位电路、所述第二扫描单元还包括及第十四复位电路的情况下，所述第十一复位电路和所述第十四复位电路，还均与所述第二防漏电节点电连接。
在一些实施例中，所述第二防漏电电路包括：第六十一晶体管。所述第六十一晶体管的控制极与所述第一上拉节点电连接，所述第六十一晶体管的第一极与所述第五电压信号端电连接，所述第六十一晶体管的第二极与所述第二防漏电节点电连接。所述第一输入电路还包括：第六十二晶体管。所述第六十二晶体管的控制极与所述显示输入信号端电连接，所述第六十二晶体管的第一极与所述显示输入信号端电连接，所述第六十二晶体管的第二极与所述第二防漏电节点电连接。所述第一晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十二晶体管与所述显示输入信号端电连接。所述第二输入电路中的第三晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十二晶体管与所述显示输入信号端电连接。在所述插黑电路包括第一插黑传输子电路的情况下，所述第一插黑传输子电路还包括：第六十三晶体管。所述第六十三晶体管的控制极与所述第二控制信号端 电连接，所述第六十三晶体管的第一极与所述第二插黑节点电连接，所述第六十三晶体管的第二极与所述第二防漏电节点电连接。所述第一插黑传输子电路中的第七晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十三晶体管与所述第二插黑节点电连接。所述第二插黑传输子电路中的第八晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十三晶体管与所述第二插黑节点电连接。所述第一复位电路还包括：第六十四晶体管。所述第六十四晶体管的控制极与所述第一复位信号端电连接，所述第六十四晶体管的第一极与所述第二防漏电节点电连接，所述第六十四晶体管的第二极与所述第一电压信号端电连接。所述第一复位电路中的第十三晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十四晶体管与所述第一电压信号端电连接。所述第三复位电路中的第十六晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十四晶体管与所述第一电压信号端电连接。所述第二复位电路还包括：第六十五晶体管。所述六十五晶体管的控制极与所述第二复位信号端电连接，所述第六十五晶体管的第一极与所述第二防漏电节点电连接，所述第六十五晶体管的第二极与所述第一电压信号端电连接。所述第二复位电路中的第十五晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十五晶体管与所述第一电压信号端电连接。所述第四复位电路中的第十八晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十五晶体管与所述第一电压信号端电连接。所述第五复位电路还包括：第六十六晶体管。所述第六十六晶体管的控制极与所述第一下拉节点电连接，所述第六十六晶体管的第一极与所述第二防漏电节点电连接，所述第六十六晶体管的第二极与所述第一电压信号端电连接。所述第五复位电路中的第二十七晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十六晶体管与所述第一电压信号端电连接。所述第八复位电路中的第三十三晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十六晶体管与所述第一电压信号端电连接。在所述第五复位电路还与所述第二下拉节点电连接的情况下，所述第五复位电路还包括：第六十七晶体管。所述第六十七晶体管的控制极与所述第二下拉节点电连接，所述第六十七晶体管的第一极与所述第二防漏电节点电连接，所述第六十七晶体管的第二极与所述第一电压信号端电连接。所述第五复位电路中的第三十九晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十七晶体管与所述第一电压信号端电连接。所述第八复位电路中的第四十三晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十七晶体管与所述第一电压信号端电连接。在所述第一扫描单元还包括第十一复位电路的情况下，所述第十一复位电路还包括：第六十八晶体管。所述第六十八晶体管的控制极与所述全局复位信号端电连接，所述第六十八晶体管的第一极与所述第二防漏电节点电连接，所述第六十八晶体管的第二极与所述第一电压信号端电连接。所述第十一复位电路中的第五十一晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十八晶体管与所述第一电压信号端电连接。所述第十四复位电路中的第五十五晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十八晶体管与所述第一电压信号端电连接。在所述消隐电路包括第一消隐传输子电路的情况下，所述第一消隐传输子电路还包括：第六十九晶体管。所述第六十九晶体管的控制极与所述第七时钟信号端电连接，所述第六十九晶体管的第一极与所述第二消隐节点电连接，所述第六十九晶体管的第二极与所述第二防漏电节点电连接。所述第一消隐传输子电路中的第四十九晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十九晶体管与所述第二消隐节点电连接。所述第二消隐传输子电路中的第五十晶体管的第一极与所述第二防 漏电节点电连接，并通过所述第六十九晶体管与所述第二消隐节点电连接。
在一些实施例中，所述移位寄存器，还包括：第三防漏电电路。所述第三防漏电电路与所述第一插黑节点、第五电压信号端及第三防漏电节点电连接；所述第三防漏电电路被配置为，在所述第一插黑节点的电压的控制下，将在所述第五电压信号端处接收的第五电压信号传输至所述第三防漏电节点。其中，所述插黑控制子电路还与所述第三防漏电节点电连接。
在一些实施例中，所述第三防漏电电路包括：第七十晶体管。所述第七十晶体管的控制极与所述第一插黑节点电连接，所述第七十晶体管的第一极与所述第五电压信号端电连接，所述第七十晶体管的第二极与所述第三防漏电节点电连接。所述插黑控制子电路还包括：第七十一晶体管。所述第七十一晶体管的控制极与所述第一控制信号端电连接，所述第七十一晶体管的第一极与所述插黑级联信号端电连接，所述第七十一晶体管的第二极所述第三防漏电节点电连接。所述插黑控制子电路中的第五晶体管的第一极与所述第三防漏电节点电连接，并通过所述第七十一晶体管与所述插黑级联信号端电连接。
另一方面，提供一种扫描驱动电路。所述扫描驱动电路包括：多级级联的如上述任一实施例所述的移位寄存器。
在一些实施例中，多级所述移位寄存器包括多个第一移位寄存器组和多个第二移位寄存器组；第一移位寄存器组和第二移位寄存器组交替排列。在所述移位寄存器包括第一扫描单元和第二扫描单元的情况下，第一移位寄存器组包括2N级移位寄存器，第二移位寄存器组包括2N级移位寄存器；其中，N为正整数。所述扫描驱动电路还包括：第一控制信号线组，包括第一子控制信号线和第二子控制信号线；所述第一子控制信号线与所述第一移位寄存器组中各移位寄存器的第一控制信号端电连接，所述第二子控制信号线与所述第二移位寄存器组中各移位寄存器的第一控制信号端电连接；以及，第一时钟信号线组，包括8N个第一子时钟信号线；所述8N个第一子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第一时钟信号端及第二时钟信号端、所述第二移位寄存器组中各移位寄存器的第一时钟信号端及第二时钟信号端电连接。在所述移位寄存器的第一输出电路还与第三时钟信号端及第一感测信号端电连接、第二输出电路还与第四时钟信号端及第二感测信号端电连接的情况下，所述扫描驱动电路还包括：第二时钟信号线组。所述第二时钟信号线组，包括4N个第二子时钟信号线；所述4N个第二子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第三时钟信号端及第四时钟信号端电连接，并分别与所述第二移位寄存器组中各移位寄存器的第三时钟信号端及第四时钟信号端电连接。或者，所述第二时钟信号线组，包括8N个第二子时钟信号线；所述8N个第二子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第三时钟信号端及第四时钟信号端、所述第二移位寄存器组中各移位寄存器的第三时钟信号端及第四时钟信号端电连接。在所述移位寄存器的第一输出电路还与第五时钟信号端及第一移位信号端电连接、第二输出电路还与第六时钟信号端及第二移位信号端电连接的情况下，所述扫描驱动电路还包括：第三时钟信号线组。所述第三时钟信号线组，包括4N个第三子时钟信号线；所述4N个第三子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第五时钟信号端及第六时钟信号端电连接，并分别与所述第二移位寄存器组中各移位寄存器的第五时钟信号端及第六时钟信号端电连接；或，所述4N个第三子时钟信号线中的2N个第三子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第五时钟信号端电连接，另外2N个第三子时钟信号线分别与所 述第二移位寄存器组中各移位寄存器的第五时钟信号端电连接；或者，所述第三时钟信号线组，包括8N个第三子时钟信号线；所述8N个第三子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第五时钟信号端及第六时钟信号端、所述第二移位寄存器组中各移位寄存器的第五时钟信号端及第六时钟信号端电连接。
在一些实施例中，所述扫描驱动电路，还包括：第二控制信号线组。所述第二控制信号线组包括：第三子控制信号线和第四子控制信号线。所述第三子控制信号线与所述第一移位寄存器组中各移位寄存器的第二控制信号端电连接；所述第四子控制信号线与所述第二移位寄存器组中各移位寄存器的第二控制信号端电连接。
在一些实施例中，所述第三子控制信号线还与所述第一移位寄存器组中各移位寄存器的插黑输入信号端电连接。所述第四子控制信号线还与所述第二移位寄存器组中各移位寄存器的插黑输入信号端电连接。
在一些实施例中，多级所述移位寄存器中，除前至少一级移位寄存器外，其余级移位寄存器的显示输入信号端，与在前的移位寄存器中的第一移位信号端电连接；除前至少两级移位寄存器外，其余级移位寄存器的插黑级联信号端，与在前的移位寄存器中的第二移位信号端电连接；或者，在所述移位寄存器还包括第二防漏电电路的情况下，除前至少两级移位寄存器外，其余级移位寄存器的插黑级联信号端，与在前的移位寄存器的第二防漏电节点电连接。
在一些实施例中，多级所述移位寄存器中，除前至少一级移位寄存器外，其余级移位寄存器的显示输入信号端，与在前的移位寄存器中的第二移位信号端电连接；除前至少两级移位寄存器外，其余级移位寄存器的插黑级联信号端，与在前的移位寄存器中的第一移位信号端电连接。
在一些实施例中，所述第一移位寄存器组中，至少两级移位寄存器共用插黑电路。所述第二移位寄存器组中，至少两级移位寄存器共用插黑电路。
又一方面，提供一种显示装置。所示显示装置包括：多行子像素；以及，如上述任一实施例所述的扫描驱动电路。其中，所述扫描驱动电路中的一级移位寄存器与至少一行子像素电连接。
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为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开一些实施例中的一种显示装置的结构图；
图2为根据本公开一些实施例中的另一种显示装置的结构图；
图3为根据本公开一些实施例中的又一种显示装置的结构图；
图4为根据本公开一些实施例中的一种子像素的电路图；
图5为根据相关技术中的一种对应于图4所示子像素的时序图；
图6为根据本公开一些实施例中的一种对应于图4所示子像素的时序图；
图7为根据本公开一些实施例中的另一种对应于图4所示子像素的时序图；
图8为根据本公开一些实施例中的一种移位寄存器的结构图；
图9为根据本公开一些实施例中的另一种移位寄存器的结构图；
图10为根据本公开一些实施例中的一种移位寄存器的电路图；
图11为根据本公开一些实施例中的又一种移位寄存器的结构图；
图12为根据本公开一些实施例中的另一种移位寄存器的电路图；
图13为根据本公开一些实施例中的又一种移位寄存器的结构图；
图14为根据本公开一些实施例中的又一种移位寄存器的电路图；
图15为根据本公开一些实施例中的又一种移位寄存器的结构图；
图16为根据本公开一些实施例中的又一种移位寄存器的电路图；
图17为根据本公开一些实施例中的又一种移位寄存器的结构图；
图18为根据本公开一些实施例中的又一种移位寄存器的电路图；
图19为根据本公开一些实施例中的又一种移位寄存器的结构图；
图20为根据本公开一些实施例中的又一种移位寄存器的电路图；
图21为根据本公开一些实施例中的又一种移位寄存器的结构图；
图22为根据本公开一些实施例中的又一种移位寄存器的电路图；
图23为根据本公开一些实施例中的又一种移位寄存器的结构图；
图24为根据本公开一些实施例中的又一种移位寄存器的电路图；
图25为根据本公开一些实施例中的又一种移位寄存器的电路图；
图26为根据本公开一些实施例中的又一种移位寄存器的结构图；
图27为根据本公开一些实施例中的又一种移位寄存器的电路图；
图28为根据本公开一些实施例中的又一种移位寄存器的电路图；
图29为根据本公开一些实施例中的又一种移位寄存器的结构图；
图30为根据本公开一些实施例中的又一种移位寄存器的电路图；
图31为根据本公开一些实施例中的又一种移位寄存器的结构图；
图32为根据本公开一些实施例中的又一种移位寄存器的电路图；
图33为根据本公开一些实施例中的又一种移位寄存器的电路图；
图34为根据本公开一些实施例中的又一种移位寄存器的电路图；
图35为根据本公开一些实施例中的又一种移位寄存器的电路图；
图36为根据本公开一些实施例中的又一种移位寄存器的电路图；
图37为根据本公开一些实施例中的又一种移位寄存器的电路图；
图38为根据本公开一些实施例中的一种扫描驱动电路的结构图；
图39为根据本公开一些实施例中的另一种扫描驱动电路的结构图；
图40为根据本公开一些实施例中的又一种扫描驱动电路的结构图；
图41为根据本公开一些实施例中的又一种扫描驱动电路的结构图；
图42为根据本公开一些实施例中的又一种扫描驱动电路的结构图；
图43为根据本公开一些实施例中的一种第一移位寄存器组或第二移位寄存器组中插黑电路的电路图；
图44为根据本公开一些实施例中的另一种第一移位寄存器组或第二移位寄存器组中插黑电路的电路图；
图45为根据本公开一些实施例中的又一种扫描驱动电路的结构图；
图46为根据本公开一些实施例中的一种对应于图38所示的扫描驱动电路的时 序控制图；
图47为根据本公开一些实施例中的另一种对应于图38所示的扫描驱动电路的时序控制图；
图48为根据本公开一些实施例中的又一种扫描驱动电路的结构图；
图49为根据本公开一些实施例中的一种对应于图39所示的扫描驱动电路的时序控制图；
图50为根据本公开一些实施例中的又一种扫描驱动电路的结构图；
图51为根据本公开一些实施例中的一种对应于图40所示的扫描驱动电路的时序控制图；
图52为根据本公开一些实施例中的又一种扫描驱动电路的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
另外，在一些实施例中，“电连接”可以表示为直接电连接，也可以表示为间接电连接。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述 的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管(例如氧化物薄膜晶体管)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在一些实施例中，移位寄存器所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的电路中，上拉节点和下拉节点等节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
在本公开的实施例中，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)。术语“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
下面，在本公开的实施例提供的电路中，以晶体管均以N型晶体管为例进行说明。
本公开的一些实施例提供了一种移位寄存器100、扫描驱动电路1000及显示装置2000。以下对移位寄存器100、扫描驱动电路1000及显示装置2000分别进行介绍。
本公开的一些实施例提供一种显示装置2000，如图1所示。该显示装置2000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后 视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些示例中，上述显示装置2000可以包括框架、设置于框架内的显示面板、电路板、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。
上述显示面板的类型包括多种，可以根据实际需要选择设置。
示例性的，上述显示面板可以为：有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板、微发光二极管(Micro Light Emitting Diodes，简称Micro LED)显示面板等，本公开对此不做具体限定。
下面以上述显示面板为OLED显示面板(也即显示装置2000为OLED显示装置)为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，如图2和图3所示，上述显示装置2000具有显示区A，以及设置在显示区A旁侧的边框区B。其中，“旁侧”指的是显示区A的一侧、两侧、三侧或者周侧等，也即，边框区B可以位于显示区A的一侧、两侧或三侧，或者，边框区B可以围绕显示区A设置。
在一些实施例中，如图2和图3所示，上述显示装置2000可以包括：衬底200、多个子像素P及扫描驱动电路1000。该衬底200用于承载该多个子像素和扫描驱动电路1000。
示例性的，如图2和图3所示，扫描驱动电路1000可以位于边框区B。当然，扫描驱动电路1000也可以设置在其他位置，本公开对此不做限定。
此处，扫描驱动电路1000例如可以为发光控制电路，也可以为栅极驱动电路。其中，本公开以扫描驱动电路1000为栅极驱动电路为例进行示意性说明。
上述衬底200的类型包括多种，可以根据实际需要选择设置。
示例性的，衬底200可以为刚性衬底。该刚性衬底例如可以为玻璃衬底或PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底等。
示例性的，衬底200可以为柔性衬底。该柔性衬底例如可以为PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)衬底、PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)衬底或PI(Polyimide，聚酰亚胺)衬底等。此时，显示装置2000可以为柔性显示面板。
示例性的，如图2和图3所示，上述多个子像素P可以位于显示区A内。其中，该多个子像素P例如可以沿第一方向X排列为多行，沿第二方向Y排列为多列。其中，每行子像素P可以包括多个子像素P，每列子像素P可以包括多个子像素P。
此处，第一方向X和第二方向Y相互交叉。第一方向X和第二方向Y之间的夹角可以根据实际需要选择设置。示例性的，第一方向X和第二方向Y之间的夹角可以为85°、89°或90°等。
在一些示例中，如图2和图3所示，上述显示装置2000还可以包括：设置在衬底200的一侧、且位于显示区A的多条栅线GL以及多条数据线DL。其中，该多条栅线GL沿第一方向X延伸，该多条数据线DL沿第二方向Y延伸。
示例性的，可以将沿第一方向X排列成一行的子像素P称为同一行子像素P，将沿第二方向Y排列成一列的子像素P称为同一列子像素P。同一行子像素P可以与至少一条栅线GL电连接，同一列子像素P可以与一条数据线DL电连接。
在一些示例中，如图4所示，上述多个子像素P中，每个子像素P可以包括像素驱动电路P1及与该像素驱动电路P1电连接的发光器件P2。该发光器件可以为OLED。
示例性的，一条栅线GL可以与同一行子像素P中的多个像素驱动电路P1电连接，一条数据线DL可以与同一列子像素P中的多个像素驱动电路P2电连接。
上述像素驱动电路P1的结构包括多种，可以根据实际需要选择设置。例如，像素驱动电路P1的结构可以包括“3T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。其中，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
此处，在显示装置2000使用的过程中，像素驱动电路P1中的晶体管及发光器件P2的稳定性可能会下降(例如驱动晶体管的阈值电压漂移)，影响显示装置2000的显示效果，这样便需要对子像素P进行补偿。
对子像素P进行补偿的方式可以包括多种，可以根据实际需要选择设置。例如，可以在子像素P中设置像素补偿电路，以利用该像素补偿电路对子像素P进行内部补偿。又如，可以通过子像素P内部的晶体管对驱动晶体管或发光器件进行感测，并将感测到的数据传输到外部感应电路，以利用该外部感应电路计算需要补偿的驱动电压值并进行反馈，从而实现对子像素P的外部补偿。
本公开以采用外部补偿的方式(对驱动晶体管进行感测)，且像素驱动电路采用“3T1C”的结构为例，对子像素P的结构及工作过程进行示意性说明。
示例性的，如图4所示，像素驱动电路P1可以包括：开关晶体管T1、驱动晶体管T2、感测晶体管T3和存储电容器Cst。
例如，如图4所示，开关晶体管T1的控制极与第一栅极信号端G1电连接，开关晶体管T1的第一极与数据信号端Data电连接，开关晶体管T1的第二极与第一节点G电连接。其中，开关晶体管T1被配置为，响应于在第一栅极信号端G1处接收的第一扫描信号，将在数据信号端Data处接收的数据信号传输至第一节点G。
此处，数据信号例如包括检测数据信号和显示数据信号。其中，检测数据信号用在消隐时段，显示数据信号用在显示时段。关于显示时段和消隐时段，可以参照下面一些实施例中的说明，此处不再赘述。
例如，如图4所示，驱动晶体管T2的控制极与第一节点G电连接，驱动晶体管T2的第一极与第六电压信号端ELVDD电连接，驱动晶体管T2的第二极与第二节点S电连接。其中，驱动晶体管T2被配置为，在第一节点G的电压的控制下导通，根据所述第一节点G的电压及在第六电压信号端ELVDD处接收的第六电压信号，生成驱动信号，并将所述驱动信号传输至第二节点S。
例如，如图4所示，存储电容器Cst的第一端与第一节点G电连接，存储电容器Cst的第二端与第二节点S电连接。其中，开关晶体管T1在对第一节点G进行充电的过程中，同时对存储电容器Cst进行充电。
例如，如图4所示，发光器件P2的阳极与第二节点S电连接，发光器件P2的阴极与第七电压信号端ELVSS电连接。发光器件P2被配置为，在所述驱动信号的驱动下，进行发光。
例如，如图4所示，感测晶体管T3的控制极与第二栅极信号端G2电连接，感测晶体管T3的第一极与第二节点S电连接，感测晶体管T3的第二极与感测信号端Sense电连接。 其中，感测晶体管T3被配置为，响应于在第二栅极信号端G2处接收的第二扫描信号，检测驱动晶体管T2的电特性以实现外部补偿。该电特性例如包括驱动晶体管T2的阈值电压和/或载流子迁移率。
此处，感测信号端Sense可以提供复位信号或获取感测信号，其中，复位信号用于在显示时段对第二节点S进行复位，获取感测信号用于在消隐时段获取驱动晶体管T2的阈值电压和/或载流子迁移率。
基于像素驱动电路P1的结构，如图2所示，同一行子像素P中的多个像素驱动电路P1可以与两条栅线GL(也即第一栅线和第二栅线)电连接。例如，各第一栅极信号端G1可以与第一栅线电连接并接收第一栅线传输的第一扫描信号；各第二栅极信号端G2可以与第二栅线电连接，并接收第二栅线传输的第二扫描信号。
需要说明的是，一帧的显示阶段例如可以包括依次进行的显示时段和消隐时段。
在一帧显示阶段中的显示时段，如图5所示，子像素P的工作过程例如可以包括：复位阶段t1、数据写入阶段t2和发光阶段t3。
在复位阶段t1中，第一扫描信号的电平为高电平，数据信号端的电平例如为低电平，第二扫描信号的电平为高电平，感测信号端Sense提供复位信号的电平为低电平。开关晶体管T1在第一扫描信号的控制下导通，接收数据信号，并将该数据信号传输至第一节点G，对第一节点G进行复位。感测晶体管T3在第二扫描信号的控制下导通，接收复位信号，并将该复位信号传输至第二节点S，对第二节点S进行复位。
在数据写入阶段t2中，第一扫描信号的电平为高电平，数据信号(也即显示数据信号)的电平为高电平。开关晶体管T1在第一扫描信号的控制下保持导通状态，接收显示数据信号，并将该显示数据信号传输至第一节点G，同时对存储电容器Cst进行充电。
在发光阶段t3中，第一扫描信号的电平为低电平，第二扫描信号的电平为低电平，第六电压信号的电平为高电平。开关晶体管T1在第一扫描信号的控制下关断，感测晶体管T3在第二扫描信号的控制下关断。存储电容器Cst开始放电，使得第一节点G的电压保持为高电平。驱动晶体管T2在第一节点G的电压的控制下导通，接收第六电压信号，并生成驱动信号，将该驱动信号传输至第二节点S，驱动发光器件P2进行发光。
在一帧显示阶段中的消隐时段，子像素P的工作过程例如可以包括：第一阶段和第二阶段。
在第一阶段中，第一扫描信号的电平和第二扫描信号的电平均为高电平，数据信号(也即检测数据信号)的电平为高电平。开关晶体管T1在第一扫描信号的控制下导通，接收检测数据信号，并将该检测数据信号传输至第一节点G，对第一节点G进行充电。感测晶体管T3在第二扫描信号的控制下导通，接收感测信号端Sense提供复位信号，并将该复位信号传输至第二节点S。
在第二阶段中，感测信号端Sense处于悬浮状态。驱动晶体管T2在第一节点G的电压的控制下导通，接收第六电压信号，并将该第六电压信号传输至第二节点S，对第二节点S进行充电，使得第二节点S的电压升高，直至驱动晶体管T2截止。此时，第一节点G和第二节点S之间的电压差Vgs等于驱动晶体管T2的阈值电压Vth。
由于感测晶体管T3处于导通状态、且感测信号端Sense处于悬浮状态，因此，在驱动晶体管T2对第二节点S进行充电的过程中，同时还会对感测信号端Sense进行充电。通过对感测信号端Sense进行电压取样(也即获取感测信号)，便可以根据感测信号端Sense 的电压和检测数据信号的电平之间的关系，计算得到驱动晶体管T2的阈值电压Vth。
在计算得到驱动晶体管T2的阈值电压Vth之后，便可以将该阈值电压Vth补偿进下一帧显示阶段中显示时段的显示数据信号中，完成对子像素P的外部补偿。
在一些示例中，上述扫描驱动电路1000与上述多个子像素P位于衬底200的同一侧。该扫描驱动电路1000可以包括多级级联的移位寄存器100。一级移位寄存器100例如可以与至少一行子像素P(也即子像素P中的多个像素驱动电路P1)电连接。
需要说明的是，在一帧的显示阶段中，第一栅极信号端G1所传输的第一扫描信号和第二栅极信号端G2所传输的第二扫描信号均由扫描驱动电路1000提供。也即，扫描驱动电路1000中的每个移位寄存器100可以通过第一栅线与第一栅极信号端G1电连接，通过该第一栅线向第一栅极信号端G1传输第一扫描信号，并通过第二栅线与第二栅极信号端G2电连接，通过该第二栅线向第二扫描信号端G2传输第二扫描信号。
当然，如图3所示，同一行子像素P中的多个像素驱动电路P1也可以与同一条栅线GL电连接。在此情况下，上述第一扫描信号和第二扫描信号相同。扫描驱动电路1000中的每个移位寄存器1可以通过相应的栅线GL与第一栅极信号端G1及第二栅极信号端G2电连接，并通过该栅线GL向第一栅极信号端G1及第二栅极信号端G2传输扫描信号。
相关技术中，在显示装置2000进行显示的过程中，动态画面切换的过程中会产生图像拖影现象，也即，当显示装置2000从一帧画面切换到另一帧画面时，观看者会感受到上一帧的画面拖影(也成动态图像拖影)，从而会影响图像显示效果。
基于此，如图39～图42所示，本公开的一些实施例提供了一种扫描驱动电路1000。该扫描驱动电路1000包括多级级联的移位寄存器100。其中，该移位寄存器100应用于上述显示装置2000中，每级移位寄存器100与至少一行子像素P电连接。
此处，每级移位寄存器100所电连接的子像素P的行数，可以根据移位寄存器100的结构而定。
在一些实施例中，如图8～图10所示，移位寄存器100包括：第一扫描单元1和插黑电路2。其中，第一扫描单元1包括第一输入电路11和第一输出电路12。
在一些示例中，如图8～图10所示，第一输入电路11与显示输入信号端Iput及第一上拉节点Q<1>电连接。其中，第一输入电路11被配置为，响应于在显示输入信号端Iput处接收的显示输入信号，将显示输入信号传输至第一上拉节点Q<1>。
示例性的，在显示输入信号的电平为高电平的情况下，第一输入电路11可以在显示输入信号的作用下导通，接收并传输显示输入信号至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电，使得第一上拉节点Q<1>的电压升高。
在一些示例中，如图8～图10所示，第一输出电路12与第一上拉节点Q<1>、第一时钟信号端CLKE1及第一扫描信号端电连接Oput1<N>。其中，第一输出电路12被配置为，在第一输入电路11将显示输入信号传输至第一上拉节点Q<1>的情况下，在第一上拉节点Q<1>的电压的控制下，将在第一时钟信号端CLKE1处接收的第一时钟信号传输至第一扫描信号端Oput1<N>，驱动上述至少一行子像素P进行图像显示。
示例性的，在第一上拉节点Q<1>的电压为高电平的情况下，第一输出电路12可以在第一上拉节点Q<1>的电压的控制下导通，将在第一时钟信号端CLKE1处接收的第一时钟信号传输至第一扫描信号端Oput1<N>，并将第一时钟信号作为第一扫描信号，从第一扫描信号端Oput1<N>输出。
在此情况下，相同行子像素P中的多个像素驱动电路P1可以与同一条栅线GL电连接。一个移位寄存器100的第一扫描信号端Oput1<N>则可以通过该栅线GL与相应行子像素P中多个像素驱动电路P1的第一栅极信号端G1和第二栅极信号端G2电连接。第一扫描信号端Oput1<N>所输出的第一扫描信号也便可以经该栅线GL传输至该多个像素驱动电路P1的第一栅极信号端G1和第二栅极信号端G2。
在一些示例中，如图8～图10所示，插黑电路2与第一控制信号端BCS1、插黑级联信号端BCR、第二控制信号端BCS2、插黑输入信号端BI、第一上拉节点Q<1>及第一电压信号端V1电连接。其中，插黑电路2被配置为，在第一控制信号端BCS1所传输的第一控制信号、插黑级联信号端BCR所传输的插黑级联信号及第二控制信号端BCS2所传输的第二控制信号的控制下，将在插黑输入信号端BI处接收的插黑输入信号传输至第一上拉节点Q<1>。
示例性的，在第一控制信号的电平为高电平、插黑级联信号的电平为高电平且第二控制信号的电平为高电平的情况下，插黑电路2可以在第一控制信号、插黑级联信号及第二控制信号的控制下导通，接收插黑输入信号，并将该插黑输入信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电，使得第一上拉节点Q<1>的电压升高。
此处，第一电压信号端V1例如被配置为传输直流低电平信号(例如低于或等于时钟信号的低电平部分)。示例性的，该第一电压端V1接地。
示例性的，输出电路12还被配置为，在插黑电路2将插黑输入信号传输至第一上拉节点Q<1>的情况下，在第一上拉节点Q<1>的电压的控制下，将第一时钟信号传输至第一扫描信号端Oput1<N>，驱动上述至少一行子像素P进行黑画面显示。
例如，在第一上拉节点Q<1>的电压为高电平的情况下，第一输出电路12可以在第一上拉节点Q<1>的电压的控制下导通，将在第一时钟信号端CLKE1处接收的第一时钟信号传输至第一扫描信号端Oput1<N>，并将第一时钟信号作为第一扫描信号，从第一扫描信号端Oput1<N>输出。
需要说明的是，在本公开的实施例中，在一帧显示阶段中的显示时段内，第一输入电路11和插黑电路2分别在不同的时间导通。
如图3所示，以同一行子像素P中多个像素驱动电路P1的第一栅极信号端G1和第二栅极信号端G2，与同一条栅线GL电连接为例。第一扫描信号端Oput1<N>输出的第一扫描信号，对应为第一栅极信号端G1和第二栅极信号端G2所接收的扫描信号。
在一帧显示阶段中的显示时段中，第一上拉节点Q<1>的电压首先是由第一输入电路11抬升的。第一输入电路11导通并对第一上拉节点Q<1>进行充电后，第一输出电路12可以在第一上拉节点Q<1>的电压的控制下导通，将第一时钟信号作为第一扫描信号，从第一扫描信号端Oput1<N>输出。如图6所示，在复位阶段t1和数据写入阶段t2中，第一输入电路11关断，第一上拉节点Q<1>的电压保持为高电平，第一输出电路12在第一上拉节点Q<1>的电压的作用下保持导通状态。由于第一时钟信号的电平为高电平，因此，第一输出电路12输出的第一扫描信号的电平为高电平。在发光阶段t3中，第一上拉节点Q<1>的电压为低电平，第一输出电路12关断，第一扫描信号的电平为低电平；驱动晶体管T2在第一节点G的电压(存储电容器Cst进行放电)的控制下导通，驱动发光器件P2发光。相对应的，与移位寄存器100相对应的至少一行子像素P进行图像显示。
在发光器件P2发光过程中的某一时刻(也即图6所示中发光阶段t3和插黑写入阶段 t4交替的时刻)，插黑电路2导通并对第一上拉节点Q<1>进行充电，第一输出电路12可以在第一上拉节点Q<1>的电压的控制下导通。此时，第一时钟信号可以作为插黑信号从第一扫描信号端Oput1<N>输出，并传输至相应行像素驱动电路P1的第一栅极信号端G1和第二栅极信号端G2。由于插黑信号的电平为高电平，开关晶体管T1可以在该插黑信号的控制下导通，将低电平或较低电平的数据信号(也可以称为插黑数据信号)传输至第一节点G；感测晶体管T3也可以在插黑信号的控制下导通，将低电平的复位信号传输至第二节点S。此时Vgs(也即第一节点G和第二节点S之间的压差)小于Vth(也即驱动晶体管T2的阈值电压)，使得子像素P停止发光，切换为黑画面。在插黑保持阶段t5中，子像素P持续显示为黑画面。
由此，本公开的一些实施例所提供的移位寄存器100，通过设置插黑电路2，可以在子像素P发光以进行正常图像显示的过程中，插入黑画面，缩短子像素P发光正常发光的时间，缩短显示装置2000正常显示画面的时间。这样可以在不增加刷新频率的基础上，增大MPRT(Motion Picture Response Time，动态图像响应时间)，改善动态图像拖影的现象，提高图像显示的效果。
此外，通过控制插黑电路2在发光阶段t3和插黑写入阶段t4的交替时刻，便可以控制子像素P正常发光的时长与保持为黑画面的时长之比，这样便于调整MPRT，进而有利于改善动态图像拖影的现象，提高图像显示的效果。
需要说明的是，对子像素P的发光过程进行控制，以插入黑画面的方式包括多种，具体可以根据实际需要选择设置，本公开对此不作限定。
在一些实施例中，如图13和图14所示，第一输出电路12还可以与第三时钟信号端CLKF1及第一感测信号端Oput2<N>电连接。其中，第一输出电路12还被配置为，在第一输入电路11将显示输入信号传输至第一上拉节点Q<1>的情况下，在第一上拉节点Q<1>的电压的控制下，将在第三时钟信号端CLKF1处接收的第三时钟信号传输至第一感测信号端Oput2<N>，驱动上述至少一行子像素P进行复位。或，在插黑电路2将插黑输入信号传输至第一上拉节点Q<1>的情况下，在第一上拉节点Q<1>的电压的控制下，将第三时钟信号传输至第一感测信号端Oput2<N>，驱动上述至少一行子像素P进行黑画面显示。
示例性的，在第一上拉节点Q<1>的电压为高电平的情况下，第一输出电路12可以在第一上拉节点Q<1>的电压的控制下导通，将在第三时钟信号端CLKF1处接收的第三时钟信号传输至第一感测信号端Oput2<N>，并将第三时钟信号作为第一感测信号，从第一感测信号端Oput1<N>输出。
在此情况下，同一行子像素P中的多个像素驱动电路与两条栅线GL电连接。一个移位寄存器100的第一扫描信号端Oput1<N>可以通过其中一条栅线GL与相应行子像素P中多个像素驱动电路P的第一栅极信号端G1电连接，第一扫描信号端Oput1<N>所输出的第一扫描信号可以经该栅线GL传输至该多个像素驱动电路P1的第一栅极信号端G1。该移位寄存器100的第一感测信号端Oput2<N>可以通过另一条栅线GL与相应行子像素P中多个像素驱动电路P1的第二栅极信号端G2电连接，第一感测信号端Oput2<N>所输出的第一感测信号可以作为第二扫描信号经该栅线GL传输至该多个像素驱动电路P1的第二栅极信号端G2。
例如，在一帧显示阶段中的显示时段中，如图6所示，在复位阶段t1和数据写入阶段t2中，第一输入电路11开启，第一上拉节点Q<1>的电压保持为高电平，第一输出电路12 在第一上拉节点Q<1>的电压的作用下保持导通状态。由于第一时钟信号的电平和第三时钟信号的电平均为高电平，因此，第一输出电路12输出的第一扫描信号的电平和第一感测信号的电平均为高电平。开关晶体管T1在第一扫描信号(来自第一扫描信号端Oput1<N>)的控制下导通，接收并传输数据信号至第一节点G；感测晶体管T3在第二扫描信号(来自第一感测信号端Oput2<N>)的控制下导通，接收并传输复位信号至第二节点S，对第二节点S进行复位。这样可以对后续的发光阶段t3(也即图像显示)做准备。
在发光器件P2发光过程中的某一时刻(也即图6所示中发光阶段t3和插黑写入阶段t4交替的时刻)，插黑电路2导通并对第一上拉节点Q<1>进行充电，第一输出电路12可以在第一上拉节点Q<1>的电压的控制下导通。此时，第一时钟信号可以作为第一插黑信号从第一扫描信号端Oput1<N>输出，并传输至相应行像素驱动电路P1的第一栅极信号端G1，第三时钟信号可以作为第二插黑信号从第一感测信号端Oput2<N>输出，并传输至相应行像素驱动电路P1的第二栅极信号端G2，以便于后续子像素P显示黑画面。
以同一行子像素P中多个像素驱动电路的第一扫描信号端G1和第二扫描信号端G2，分别与一条栅线GL电连接为例，对插入黑画面的方式进行示意性说明。
例如，如图7所示，在发光器件P2发光、插黑电路2导通并对第一上拉节点Q<1>进行充电的过程中，第一扫描信号端Oput1<N>输出的第一扫描信号(也即第一插黑信号)的电平可以为高电平，而第一感测信号端Oput2<N>输出的第一感测信号(也即第二插黑信号)的电平可以为低电平。基于此，感测晶体管T3可以在第二插黑信号的控制下关断；开关晶体管T1则可以在第一插黑信号的控制下导通，并将低电平或较低电平的数据信号(也可以称为插黑数据信号)传输至第一节点G，使得Vgs小于Vth，进而使得驱动晶体管T2关断，使得子像素P停止发光，切换为黑画面。
又如，在发光器件P2发光、插黑电路2导通并对第一上拉节点Q<1>进行充电的过程中，第一扫描信号端Oput1<N>输出的第一扫描信号(也即第一插黑信号)的电平可以为低电平，而第一感测信号端Oput2<N>输出的第一感测信号(也即第二插黑信号)的电平可以为高电平。基于此，开关晶体管T1可以在第一插黑信号的控制下关断；感测晶体管T3则在第二插黑信号的控制下导通，并将高电平或较高电平的感测信号(也可以称为插黑感测信号)传输至第二节点S，使得Vgs小于Vth，进而使得驱动晶体管T2关断，使得子像素P停止发光，切换为黑画面。
示例性的，输入电路11导通的时间段可以称为显示子时段，插黑电路2导通的时间段可以称为插黑子时段。其中，显示子时段和插黑子时段依次进行。
在一些实施例中，如图11～图12所示，移位寄存器100还包括：第二扫描单元3。其中，第二扫描单元3包括：第二输入电路31和第二输出电路32。
在一些示例中，如图11～图12所示，第二输入电路31与显示输入信号端Iput及第二上拉节点Q<2>电连接。其中，第二输入电路31被配置为，响应于在显示输入信号Iput，将显示输入信号传输至第二上拉节点Q<2>。
示例性的，在显示输入信号的电平为高电平的情况下，第二输入电路31可以在显示输入信号的作用下导通，接收并传输显示输入信号至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电，使得第二上拉节点Q<2>的电压升高。
在一些示例中，如图11～图12所示，第二输出电路32与第二上拉节点Q<2>、第二时钟信号端CLKE2及第二扫描信号端Oput1<N+1>电连接。其中，第二输出电路32被配置 为，在第二输入电路31将显示输入信号传输至第二上拉节点Q<2>的情况下，在第二上拉节点Q<2>的电压的控制下，将在第二时钟信号端CLKE2处接收的第二时钟信号传输至第二扫描信号端Oput1<N+1>，驱动上述至少一行子像素P进行图像显示。
示例性的，在第二上拉节点Q<2>的电压为高电平的情况下，第二输出电路32可以在第二上拉节点Q<2>的电压的控制下导通，将在第二时钟信号端CLKE2处接收的第二时钟信号传输至第二扫描信号端Oput1<N+1>，并将第二时钟信号作为第二扫描信号，从第二扫描信号端Oput1<N+1>输出。
由于第一输入电路11和第二输入电路31均与显示输入信号端Iput电连接，因此，在显示输入信号的电平为高电平的情况下，第一输入电路11和第二输入电路31可以同时导通，并同时对第一上拉节点Q<1>和第二上拉节点Q<2>进行充电，进而可以使得第一输出电路12和第二输出电路32同时导通。
其中，在显示时段中的显示子时段，第一输出电路12输出的第一扫描信号和第二输出电路32输出的第二扫描信号，例如可以不同。这样便于驱动不同行子像素P进行逐行扫描及逐行进行图像显示。
在一些示例中，如图11～图12所示，插黑电路2还与第二上拉节点Q<2>电连接。其中，插黑电路2还被配置为，在将插黑输入信号传输至第一上拉节点Q<1>的同时，将插黑输入信号传输至第二上拉节点Q<2>。输出电路32还被配置为，在插黑电路2将插黑输入信号传输至第二上拉节点Q<2>的情况下，在第二上拉节点Q<2>的电压的控制下，将第二时钟信号传输至第二扫描信号端Oput1<N+1>，驱动上述至少一行子像素P进行黑画面显示。
示例性的，在第一控制信号的电平为高电平、插黑级联信号的电平为高电平且第二控制信号的电平为高电平的情况下，插黑电路2可以在第一控制信号、插黑级联信号及第二控制信号的控制下导通，接收插黑输入信号，并将该插黑输入信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电，使得第二上拉节点Q<2>的电压升高。第二输出电路32可以在第二上拉节点Q<2>的电压的控制下导通，将在第二时钟信号端CLKE2处接收的第二时钟信号传输至第二扫描信号端Oput1<N+1>，并将第二时钟信号作为第二扫描信号，从第二扫描信号端Oput1<N+1>输出。
由于插黑电路2不仅与第一上拉节点Q<1>电连接，还与第二上拉节点Q<2>电连接，也就意味着，插黑电路2同时与第一扫描单元1和第二扫描单元3电连接。这样在插黑电路2导通的情况下，可以将高电平的插黑输入信号，同时传输至第一上拉节点Q<1>和第二上拉节点Q<2>，进而使得第一输出电路12和第二输出电路32同时导通，在第一输出电路12将第一时钟信号作为第一扫描信号输出的过程中，第二输出电路32将第而时钟信号作为第一扫描信号输出。
其中，在显示时段中的插黑子时段，第一输出电路12输出的第一扫描信号和第二输出电路32输出的第二扫描信号，例如可以相同。这样可以驱动与第一扫描信号端Oput1<N>电连接的相应行子像素P及与第二扫描信号端Oput1<N+1>电连接的相应行子像素P，同时显示黑画面。
此处，在移位寄存器100包括第一扫描单元1的情况下，每个移位寄存器100可以与至少一行子像素P电连接，进而可以通过多个移位寄存器100对显示装置2000所包括的多行子像素P进行逐行扫描或逐行显示黑画面。
在移位寄存器100包括第一扫描单元1和第二扫描单元3的情况下，每个移位寄存器100可以与至少两行子像素P电连接，其中，第一扫描单元1所连接的至少一行子像素P与第二扫描单元3所连接的至少一行子像素P不同。这样可以驱动与移位寄存器100所电连接的至少两行子像素P，同时进行黑画面显示，有利于减少插入黑画面所需的时间，改善动态图像拖影的现象，提高图像显示的效果。
在一些示例中，如图15～18所示，上述第二输出电路32还可以与第四时钟信号端CLKF2及第二感测信号端Oput2<N+1>电连接。其中，第二输出电路32还被配置为，在第二输入电路31将显示输入信号传输至第二上拉节点Q<2>的情况下，在第二上拉节点Q<2>的电压的控制下，将在第四时钟信号端CLKF2处接收的第四时钟信号传输至第二感测信号端Oput2<N+1>，驱动上至少一行子像素P进行复位；或，在插黑电路2将插黑输入信号传输至第二上拉节点Q<2>的情况下，在第二上拉节点Q<2>的电压的控制下，将第四时钟信号传输至第二感测信号端Oput2<N+1>，驱动上述至少一行子像素P进行黑画面显示。
示例性的，在第二上拉节点Q<2>的电压为高电平的情况下，第二输出电路32可以在第二上拉节点Q<2>的电压的控制下导通，将在第四时钟信号端CLKF2处接收的第四时钟信号传输至第二感测信号端Oput2<N+1>，并将第四时钟信号作为第二感测信号，从第二感测信号端Oput1<N+1>输出。
需要说明的是，利用第二扫描单元3驱动相应行子像素P进行图像显示或黑画面显示的过程，与利用第一扫描单元3驱动相应行子像素P进行图像显示或黑画面显示的过程相同，具体可以参照上述一些实施例中的说明，此处不再赘述。
此处，本公开提供的移位寄存器100所包括的扫描单元的数量，并不局限于两个。
下面结合附图对插黑电路2的结构进行示意性说明，当然，本公开中的插黑电路2的结构并不局限于此。
在一些实施例中，如图9～图18所示，插黑电路2包括：插黑控制子电路21、插黑输入子电路22和第一插黑传输子电路23。其中，在移位寄存器100还包括第二扫描单元3的情况下，插黑电路2还可以包括：第二插黑传输子电路24。
在一些示例中，如图9～图18所示，插黑控制子电路21与第一控制信号端BCS1、插黑级联信号端BCR、第一电压信号端V1及第一插黑节点M电连接。其中，插黑控制子电路21被配置为，在第一控制信号的控制下，将插黑级联信号传输至第一插黑节点M。
示例性的，在第一控制信号的电平为高电平的情况下，插黑控制子电路21可以在第一控制信号的控制下导通，接收并传输插黑级联信号至第一插黑节点M，对第一插黑节点M进行充电，使得第一插黑节点M的电压升高。
在一些示例中，如图9～图18所示，插黑输入子电路22与第一插黑节点M、插黑输入信号端BI及第二插黑节点K电连接。其中，插黑输入子电路22被配置为，在第一插黑节点M的电压的控制下，将插黑输入信号传输至第二插黑节点K。
示例性的，在第一插黑节点M的电压为高电平的情况下，插黑输入子电路22可以在第一插黑节点M的电压的控制下导通，接收并传输插黑输入信号至第二插黑节点K，对第二插黑节点K进行充电，使得第二插黑节点K的电压升高。
在一些示例中，如图9～图18所示，第一插黑传输子电路23与第二控制信号端BCS2、第二插黑节点K及第一上拉节点Q<1>电连接。其中，第一插黑传输子电路23被配置为，在第二控制信号的控制下，将来自第二插黑节点K的插黑输入信号传输至第一上拉节点 Q<1>。
示例性的，在第二控制信号的电平为高电平的情况下，第一插黑传输子电路23可以在第二控制信号的控制下导通，接收并传输插黑输入信号至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电，使得第一上拉节点Q<1>的电压升高。
在一些示例中，如图15～图18所示，第二插黑传输子电路24与第二控制信号端BCS2、第二插黑节点K及第二上拉节点Q<2>电连接。其中，第二插黑传输子电路24被配置为，在第二控制信号的控制下，将来自第二插黑节点K的插黑输入信号传输至第二上拉节点Q<2>。
示例性的，在第二控制信号的电平为高电平的情况下，第二插黑传输子电路24可以在第二控制信号的控制下导通，接收并传输插黑输入信号至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电，使得第二上拉节点Q<2>的电压升高。
在一些示例中，第二控制信号端BCS2和插黑输入信号端BI为相同信号端。也即，第二控制信号端BCS2和插黑输入信号端BI接收相同的信号，并传输相同的信号。也就是说，第二控制信号和插黑输入信号的时序相同。
示例性的，第二控制信号和插黑输入信号均为时钟信号；或者，第二控制信号和插黑输入信号均为某个移位信号。
在另一些示例中，第二控制信号端BCS2和插黑输入信号端BI为不同的信号端。
示例性的，第二控制信号端BCS2所传输的第二控制信号可以为时序信号，插黑输入信号端BI所传输的插黑输入信号可以为直流高电平信号。其中，该直流高电平信号例如可以为第五电压信号。关于第五电压信号，可以参见下文中的说明，此处不再赘述。
这样有利于简化移位寄存器100和扫描驱动电路1000的结构，有利于提高移位寄存器100和扫描驱动电路1000的良率。
下面结合附图对第一扫描单元1、插黑电路2和第二扫描单元3的结构进行示意性说明，
在一些示例中，如图10、图12、图14、图16和图18所示，插黑控制子电路21包括：第五晶体管M5和第三电容器C3。
示例性的，如图10、图12、图14、图16和图18所示，第五晶体管M5的控制极与第一控制信号端BCS1电连接，第五晶体管M5的第一极与插黑级联信号端BCR电连接，第五晶体管M5的第二极与第一插黑节点M电连接。
例如，在第一控制信号的电平为高电平的情况下，第五晶体管M5可以在该第一控制信号的控制下导通，将在插黑级联信号端BCR处接收的插黑级联信号传输至第一插黑节点M，对第一插黑节点M进行充电，使得第一插黑节点M的电压升高。
示例性的，如图10、图12、图14、图16和图18所示，第三电容器C3的第一端与第一插黑节点M电连接，第三电容器C3的第二端与第一电压信号端V1电连接。
例如，在第五晶体管M5导通、并对第一插黑节点M进行充电的过程中，还会对第三电容器C3进行充电。在第五晶体管M5关断后，第三电容器C3可以进行放电，使得第一插黑节点M的电压保持为高电平。
在一些示例中，如图10、图12、图14、图16和图18所示，插黑输入子电路22包括：第六晶体管M6。
示例性的，如图10、图12、图14、图16和图18所示，第六晶体管M6的控制极与 第一插黑节点M电连接，第六晶体管M6的第一极与插黑输入信号端BI电连接，第六晶体管M6的第二极与第二插黑节点K电连接。
例如，在第五晶体管M5导通、并对第一插黑节点M进行充电，使得第一插黑节点M的电压升高的情况下，第六晶体管M6可以在第一插黑节点M的电压的控制下导通，接收并传输插黑输入信号至第二插黑节点K。
在一些示例中，如图10、图12、图14、图16和图18所示，第一插黑传输子电路23包括：第七晶体管M7。
示例性的，如图10、图12、图14、图16和图18所示，第七晶体管M7的控制极与第二控制信号端BCS2电连接，第七晶体管M7的第一极与第二插黑节点K电连接，第七晶体管M7的第二极与第一上拉节点Q<1>电连接。
例如，在第二控制信号的电平为高电平的情况下，第七晶体管M7可以在第二控制信号的控制下导通，将来自第二插黑节点K的插黑输入信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电，使得第一上拉节点Q<1>的电压升高。
在一些示例中，如图12、图16和图18所示，第二插黑传输子电路24包括：第八晶体管M8。
示例性的，如图12、图16和图18所示，第八晶体管M8的控制极与第二控制信号端BCS2电连接，第八晶体管M8的第一极与第二插黑节点K电连接，第八晶体管M8的第二极与第二上拉节点Q<2>电连接。
例如，在第二控制信号的电平为高电平的情况下，第八晶体管M8可以在第二控制信号的控制下导通，将来自第二插黑节点K的插黑输入信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电，使得第二上拉节点Q<2>的电压升高。
在一些示例中，如图10、图12、图14、图16和图18所示，第一输入电路11包括：第一晶体管M1。
示例性的，如图10、图12、图14、图16和图18所示，第一晶体管M1的控制极与显示输入信号端Iput电连接，第一晶体管M1的第一极与显示输入信号端Iput电连接，第一晶体管M1的第二极与第一上拉节点Q<1>电连接。
例如，在显示输入信号的电平为高电平的情况下，第一晶体管M1可以在显示输入信号的作用下导通，接收显示输入信号，并将显示输入信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电，使得第一上拉节点Q<1>的电压升高。
在一些示例中，如图10、图12、图14、图16和图18所示，第一输出电路12包括：第二晶体管M2和第一电容器C1。
示例性的，如图10、图12、图14、图16和图18所示，第二晶体管M2的控制极与第一上拉节点Q<1>电连接，第二晶体管M2的第一极与第一时钟信号端CLKE1电连接，第二晶体管M2的第二极与第一扫描信号端Oput1<N>电连接。
例如，在第一上拉节点Q<1>的电压为高电平的情况下，第二晶体管M2可以在第一上拉节点Q<1>的控制下导通，将从第一时钟信号端CLKE1处接收的第一时钟信号从第一扫描信号端Oput1<N>输出。其中，在不同的时段导通，第一扫描信号端Oput1<N>输出的第一扫描信号的作用不同，具体可以参照上述一些示例中的说明，此处不再赘述。
示例性的，如图10、图12、图14、图16和图18所示，第一电容器C1的第一端与第一上拉节点Q<1>电连接，第一电容器C1的第二端与第一扫描信号端Oput1<N>电连接。
例如，在第一输入电路12中的第一晶体管M1导通、并对第一上拉节点Q<1>进行充电的过程中，还会对第一电容器C1进行充电。在第一晶体管M1关断后，第一电容器C1可以进行放电，使得第一上拉节点Q<1>的电压保持为高电平。
又如，在插黑电路2导通、并对第一上拉节点Q<1>进行充电的过程中，还会对第一电容器C1进行充电。在插黑电路2关断后，第一电容器C1可以进行放电，使得第一上拉节点Q<1>的电压保持为高电平。
在一些示例中，如图14、图16和图18所示，在第一输出电路12还与第三时钟信号端CLKF1及第一感测信号端Oput2<N>电连接的情况下，第一输出电路12还包括：第九晶体管M9和第四电容器C4。
示例性的，如图14、图16和图18所示，第九晶体管M9的控制极与第一上拉节点Q<1>电连接，第九晶体管M9的第一极与第三时钟信号端CLKF1电连接，第九晶体管M9的第二极与第一感测信号端Oput2<N>电连接。
例如，在第一上拉节点Q<1>的电压为高电平的情况下，第九晶体管M9可以在第一上拉节点Q<1>的控制下导通，将从第三时钟信号端CLKF1处接收的第三时钟信号从第一感测信号端Oput2<N>输出。其中，在不同的时段导通，第一感测信号端Oput2<N>输出的第一感测信号的作用不同，具体可以参照上述一些示例中的说明，此处不再赘述。
示例性的，如图14、图16和图18所示，第四电容器C4的第一端与第一上拉节点Q<1>电连接，第四电容器C4的第二端与第一感测信号端Oput2<N>电连接。
例如，在第一输入电路12中的第一晶体管M1导通、并对第一上拉节点Q<1>进行充电的过程中，还会对第四电容器C4进行充电。在第一晶体管M1关断后，第四电容器C4可以进行放电，使得第一上拉节点Q<1>的电压保持为高电平。
又如，在插黑电路2导通、并对第一上拉节点Q<1>进行充电的过程中，还会对第四电容器C4进行充电。在插黑电路2关断后，第四电容器C4可以进行放电，使得第一上拉节点Q<1>的电压保持为高电平。
在一些示例中，如图12、图16和图18所示，第二输入电路31包括：第三晶体管M3。
示例性的，如图12、图16和图18所示，第三晶体管M3的控制极与显示输入信号端Iput电连接，第三晶体管M3的第一极与显示输入信号端Iput电连接，第三晶体管M3的第二极与第二上拉节点Q<2>电连接。
例如，在显示输入信号的电平为高电平的情况下，第三晶体管M3可以在显示输入信号的作用下导通，接收显示输入信号，并将显示输入信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电，使得第二上拉节点Q<2>的电压升高。
在一些示例中，如图12、图16和图18所示，第二输出电路32包括：第四晶体管M4和第二电容器C2。
示例性的，如图12、图16和图18所示，第四晶体管M4的控制极与第二上拉节点Q<2>电连接，第四晶体管M4的第一极与第二时钟信号端CLKE2电连接，第四晶体管M4的第二极与第二扫描信号端Oput1<N+1>电连接。
例如，在第二上拉节点Q<2>的电压为高电平的情况下，第四晶体管M4可以在第二上拉节点Q<2>的控制下导通，将从第二时钟信号端CLKE2处接收的第二时钟信号从第二扫描信号端Oput1<N+1>输出。其中，在不同的时段导通，第二扫描信号端Oput1<N+1>输出的第二扫描信号的作用不同，具体可以参照上述一些示例中的说明，此处不再赘述。
示例性的，如图12、图16和图18所示，第二电容器C2的第一端与第二上拉节点Q<2>电连接，第二电容器C2的第二端与第二扫描信号端Oput1<N+1>电连接。
例如，在第二输入电路12中的第三晶体管M3导通、并对第二上拉节点Q<2>进行充电的过程中，还会对第二电容器C2进行充电。在第三晶体管M3关断后，第二电容器C2可以进行放电，使得第二上拉节点Q<2>的电压保持为高电平。
又如，在插黑电路2导通、并对第二上拉节点Q<2>进行充电的过程中，还会对第二电容器C2进行充电。在插黑电路2关断后，第二电容器C2可以进行放电，使得第二上拉节点Q<2>的电压保持为高电平。
在一些示例中，如图16所示，在第二输出电路32还与第四时钟信号端CLKF2及第二感测信号端Oput2<N+1>电连接的情况下，第二输出电路32还包括：第十晶体管M10和第五电容器C5。
示例性的，如图16所示，第十晶体管M10的控制极与第二上拉节点Q<2>电连接，第十晶体管M10的第一极与第四时钟信号端CLKF2电连接，第十晶体管M10的第二极与第二感测信号端Oput2<N+1>电连接。
例如，在第二上拉节点Q<2>的电压为高电平的情况下，第十晶体管M10可以在第二上拉节点Q<2>的控制下导通，将从第四时钟信号端CLKF2处接收的第四时钟信号从第二感测信号端Oput2<N+1>输出。其中，在不同的时段导通，第二感测信号端Oput2<N+1>输出的第二感测信号的作用不同，具体可以参照上述一些示例中的说明，此处不再赘述。
示例性的，如图16所示，第五电容器C5的第一端与第二上拉节点Q<2>电连接，第五电容器C5的第二端与第二感测信号端Oput2<N+1>电连接。
例如，在第二输入电路12中的第三晶体管M3导通、并对第二上拉节点Q<2>进行充电的过程中，还会对第五电容器C5进行充电。在第三晶体管M3关断后，第五电容器C5可以进行放电，使得第二上拉节点Q<2>的电压保持为高电平。
又如，在插黑电路2导通、并对第二上拉节点Q<2>进行充电的过程中，还会对第五电容器C5进行充电。在插黑电路2关断后，第五电容器C5可以进行放电，使得第二上拉节点Q<2>的电压保持为高电平。
在一些实施例中，如图13和图14所示，第一输出电路12还与第五时钟信号端CLKD1及第一移位信号端CR<N>电连接。其中，第一输出电路12还被配置为，在第一上拉节点Q<1>的电压的控制下，将在第五时钟信号端CLKD1处接收的第五时钟信号传输至第一移位信号端CR<N>。
示例性的，在第一上拉节点Q<1>的电压为高电平的情况下，第一输出电路12可以在第一上拉节点Q<1>的电压的控制下导通，将在第五时钟信号端CLKD1处接收的第五时钟信号作为第一移位信号，从第一移位信号端CR<N>输出。
下面结合附图对第一输出电路12的结构进行示意性说明。
在一些示例中，如图14所示，第一输出电路12还包括：第十一晶体管M11。
示例性的，如图14所示，第十一晶体管M11的控制极与第一上拉节点Q<1>电连接，第十一晶体管M11的第一极与第五时钟信号端CLKD1电连接，第十一晶体管M11的第二极与第一移位信号端CR<N>电连接。
例如，在第一上拉节点Q<1>的电压为高电平的情况下，第十一晶体管M11可以在第一上拉节点Q<1>的电压的控制下导通，将从第五时钟信号端CLKD1处接收的第五时钟信 号作为第一移位信号从第一移位信号端CR<N>输出。
在一些实施例中，如图17～图18所示，在移位寄存器100还包括第二扫描单元3的情况下，第二输出电路32还与第六时钟信号端CLKD2及第二移位信号端CR2<N+1>电连接。其中，第二输出电路32还被配置为，在第二上拉节点Q<2>的电压的控制下，将在第六时钟信号端CLKD2处接收的第六时钟信号传输至第二移位信号端CR2<N+1>。
示例性的，在第二上拉节点Q<2>的电压为高电平的情况下，第二输出电路32可以在第二上拉节点Q<2>的电压的控制下导通，将在第六时钟信号端CLKD2处接收的第六时钟信号作为第二移位信号，从第二移位信号端CR2<N+1>输出。
下面结合附图对第二输出电路32的结构进行示意性说明。
在一些示例中，如图18所示，第二输出电路32还包括：第十二晶体管M12。
示例性的，如图18所示，第十二晶体管M12的控制极与第二上拉节点Q<2>电连接，第十二晶体管M12的第一极与第六时钟信号端CLKD2电连接，第十二晶体管M12的第二极与第二移位信号端CR2<N+1>电连接。
例如，在第二上拉节点Q<2>的电压为高电平的情况下，第十二晶体管M12可以在第二上拉节点Q<2>的电压的控制下导通，将从第六时钟信号端CLKD2处接收的第六时钟信号作为第二移位信号从第二移位信号端CR2<N+1>输出。
需要说明的是，上述第一移位信号端CR<N>及第二移位信号端CR2<N+1>均用于级联，以便于简化扫描驱动电路1000的结构，减小扫描驱动电路1000在边框区B的占据面积。也就是说，在采用移位信号端进行级联的情况下，第一输出电路12或第二输出电路32可以与相应的移位信号端电连接，在不采用移位信号端进行级联的情况下，第一输出电路12或第二输出电路32可以不与相应的移位信号端电连接(也即不包括相应的晶体管)。
在本公开中，级联的方式包括多种，可以参见下面一些实施例中的说明，此处不再赘述。
其中，在显示输入信号端Iput与某一移位信号端电连接、且插黑级联信号端BCR与某一移位信号端电连接的情况下，两者所电连接的移位信号端，分别属于不同的扫描单元。这样可以避免出现同一移位寄存器100的第一输入电路11、第二输入电路31及插黑电路2因连接同一移位信号端而同时导通的情况，进而可以避免出现图像正常显示的过程和插入黑画面的过程相冲突的情况。
在一些实施例中，移位寄存器100还可以包括其他的电路结构，具体可以根据实际需要选择设置。
在一些示例中，如图29～图30所示，移位寄存器100还可以包括：第三防漏电电路6。该第三防漏电电路6与第一插黑节点M、第五电压信号端V5及第三防漏电节点OFF3电连接。其中，第三防漏电电路6被配置为，在第一插黑节点M的电压的控制下，将在第五电压信号端V5处接收的第五电压信号传输至第三防漏电节点OFF3。
此处，第五电压信号端V5例如可以被配置为传输直流高电平信号(例如高于或等于时钟信号的高电平部分)。
示例性的，在第一插黑节点M的电压为高电平的情况下，第三防漏电电路6可以在第一插黑节点M的电压的控制下导通，接收并传输第五电压信号至第三防漏电节点OFF3，对第三防漏电节点OFF3进行充电，使得第三防漏电节点OFF3的电压升高。
在一些示例中，如图29～图30所示，插黑控制子电路21还与第三防漏电节点OFF3 电连接。
在插黑控制子电路21中的第五晶体管M5关断、第三电容器C3进行放电以使得第一插黑节点M的电压保持为高电平的情况下，通过将插黑控制子电路21与第三防漏电节点OFF3电连接，可以减小第三防漏电节点OFF3和第一插黑节点M之间的压差，避免第一插黑节点M通过插黑控制子电路21漏电，进而可以使得第一插黑节点M能够保持在一个较高的、较为稳定的电压，避免影响插黑输入子电路22的导通状态。
下面结合附图对第三防漏电电路6和插黑控制子电路21的结构进行示意性说明。
在一些示例中，如图30所示，第三防漏电电路6包括：第七十晶体管M70。
示例性的，如图30所示，第七十晶体管M70的控制极与第一插黑节点M电连接，第七十晶体管M70的第一极与第五电压信号端V5电连接，第七十晶体管M70的第二极与第三防漏电节点OFF3电连接。
例如，在第一插黑节点M的电压为高电平的情况下，第七十晶体管M70可以在第一插黑节点M的电压的控制下导通，接收第五电压信号，并将第五电压信号传输至第三防漏电节点OFF3，对第三防漏电节点OFF3进行充电，使得第三防漏电节点OFF3的电压升高。
基于此，在一些示例中，如图30所示，插黑控制子电路21还包括：第七十一晶体管M71。
示例性的，如图30所示，第七十一晶体管M71的控制极与第一控制信号端BCS1电连接，第七十一晶体管M71的第一极与插黑级联信号端BCR电连接，第七十一晶体管M71的第二极第三防漏电节点OFF3电连接。其中，插黑控制子电路21中的第五晶体管M5的第一极与第三防漏电节点OFF3电连接，并通过第七十一晶体管M71与插黑级联信号端BCR电连接。
例如，在第一控制信号的电平为高电平的情况下，第五晶体管M5和第七十一晶体管M71可以在第一控制信号的作用下同时导通。第七十一晶体管M71可以接收并传输插黑级联信号至第三防漏电节点OFF3，第五晶体管M5可以接收并传输插黑级联信号至第一插黑节点M，对第一插黑节点M进行充电。
在第一控制信号的电平为低电平的情况下，第五晶体管M5和第七十一晶体管M71可以在第一控制信号的作用下同时关断。插黑控制子电路21中的第三电容器C3开始放电，使得第一插黑节点M的电压保持为高电平。在此过程中，第三防漏电电路6中的第七十晶体管M70可以将第五电压信号传输至第三防漏电节点OFF3，对第三防漏电节点OFF3进行充电，减小第三防漏电节点OFF3和第一插黑节点M之间的压差，并使得第五晶体管M5的控制极与第一极之间的压差小于零，确保第五晶体管M5被完全或较为完全地截止。这样可以避免第一插黑节点M通过插黑控制子电路21漏电，使得第一插黑节点M能够保持在一个较高的、较为稳定的电压。
在一些实施例中，移位寄存器100还可以包括其他的电路结构，具体可以根据实际需要选择设置。
在一些示例中，如图19～图22所示，移位寄存器100中的第一扫描单元1还可以包括：第一复位电路13和第二复位电路14。
示例性的，如图19～图22所示，第一复位电路13与第一复位信号端STD、第一上拉节点Q<1>及第一电压信号端V1电连接。其中，第一复位电路13被配置为，在第一复位信号端STD所传输的第一复位信号的控制下，将在第一电压信号端V1处接收的第一电压 信号传输至第一上拉节点Q<1>。
例如，在第一复位信号的电平为高电平的情况下，第一复位电路13可以在第一复位信号的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
需要说明的是，在将多个移位寄存器100级联构成扫描驱动电路1000后，除了前几级移位寄存器100(例如第一级移位寄存器100和第二级移位寄存器100等)外，其余各级移位寄存器100的第一复位信号端STD可以与其后某级移位寄存器100的第一移位信号端CR<N>电连接，进而该移位寄存器100输出的第一移位信号，可以作为相应移位寄存器100的第一复位信号。
相应的，部分移位寄存器100的第一复位信号端STD可以与显示复位信号线电连接，从而接收该显示复位信号线所传输的显示复位信号作为第一复位信号。其中，该部分移位寄存器100例如可以为扫描驱动电路1000中的最后两级移位寄存器100等。这样便可以实现级联复位。
示例性的，如图19～图22所示，在插黑电路2包括插黑控制子电路21的情况下，第二复位电路14与第二复位信号端BTRST、第一插黑节点M、第一上拉节点Q<1>及第一电压信号端V1电连接。其中，第二复位电路14被配置为，在第一插黑节点M的电压及第二复位信号端BTRST所传输的第二复位信号的控制下，将第一电压信号传输至第一上拉节点Q<1>。
例如，在第一插黑节点M的电压为高电平、且第二复位信号的电平为高电平的情况下，第二复位电路14可以在第一插黑节点M的电压及第二复位信号的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
此处，第二复位电路14例如可以在插黑子时段后(也即显示黑画面后)，对第一上拉节点Q<1>进行复位。
在一些示例中，如图21～图22所示，在移位寄存器100还包括第二扫描单元3的情况下，第二扫描单元3还可以包括：第三复位电路33和第四复位电路34。
示例性的，如图21～图22所示，第三复位电路33与第一复位信号端STD、第二上拉节点Q<2>及第一电压信号端V1电连接。其中，第三复位电路33被配置为，在第一复位信号的控制下，将第一电压信号传输至第二上拉节点Q<2>。
例如，在第一复位信号的电平为高电平的情况下，第三复位电路33可以在第一复位信号的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
由于第三复位电路33和第一复位电路13均与第一复位信号端STD电连接，因此，在第一复位信号的电平为高电平的情况下，第三复位电路33和第一复位电路13可以均导通，同时对第一上拉节点Q<1>和第二上拉节点Q<2>进行下拉复位。
示例性的，如图21～图22所示，第四复位电路34与第二复位信号端BTRST、第一插黑节点M、第二上拉节点点Q<2>及第一电压信号端V1电连接。其中，第四复位电路34被配置为，在第一插黑节点M的电压及第二复位信号的控制下，将第一电压信号传输至第二上拉节点Q<2>。
例如，在第一插黑节点M的电压为高电平、且第二复位信号的电平为高电平的情况下， 第四复位电路34可以在第一插黑节点M的电压及第二复位信号的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
由于第四复位电路34和第二复位电路14均与第一插黑节点M及第二复位信号端BTRST电连接，因此，在第一插黑节点M的电压为高电平、且第二复位信号的电平为高电平的情况下，第四复位电路34和第二复位电路14可以均导通，进而可以在插黑子时段后，同时对第一上拉节点Q<1>和第二上拉节点Q<2>进行下拉复位。
下面结合附图对第一复位电路13、第二复位电路14、第三复位电路33及第四复位电路44的结构进行示意性说明。
在一些示例中，如图20和图22所示，第一复位电路13包括：第十三晶体管M13。
示例性的，如图20和图22所示，第十三晶体管M13的控制极与第一复位信号端STD电连接，第十三晶体管M13的第一极与第一上拉节点Q<1>电连接，第十三晶体管M13的第二极与第一电压信号端V1电连接。
例如，在第一复位信号的电平为高电平的情况下，第十三晶体管M13可以在第一复位信号的控制下导通，接收并传输第一电压信号至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在一些示例中，如图20和图22所示，第二复位电路14包括：第十四晶体管M14和第十五晶体管M15。
示例性的，如图20和图22所示，第十四晶体管M14的控制极与第一插黑节点M电连接，第十四晶体管M14的第一极与第一上拉节点Q<1>电连接，第十四晶体管M14的第二极与第十五晶体管M15的第一极电连接。第十五晶体管M15的控制极与第二复位信号端BTRST电连接，第十五晶体管M15的第二极与第一电压信号端V1电连接。
例如，在第一插黑节点M的电压为高电平、且第二复位信号的电平为高电平的情况下，第十四晶体管M14可以在第一插黑节点M的电压的控制下导通，第十五晶体管M15可以在第二复位信号的控制下导通，第十五晶体管M15可以接收并传输第一电压信号至第十四晶体管M14的第二极，然后第十四晶体管M14可以将该第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在一些示例中，如图22所示，第三复位电路33包括：第十六晶体管M16。
示例性的，如图22所示，第十六晶体管M16的控制极与第一复位信号端STD电连接，第十六晶体管M16的第一极与第二上拉节点Q<2>电连接，第十六晶体管M16的第二极与第一电压信号端V1电连接。
例如，在第一复位信号的电平为高电平的情况下，第十六晶体管M16可以在第一复位信号的控制下导通，接收并传输第一电压信号至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在一些示例中，如图22所示，第四复位电路34包括：第十七晶体管M17和第十八晶体管M18。
示例性的，如图22所示，第十七晶体管M17的控制极与所述第一插黑节点M电连接，第十七晶体管M17的第一极与第二上拉节点Q<2>电连接，第十七晶体管M17的第二极与第十八晶体管M18的第一极电连接。第十八晶体管M18的控制极与第二复位信号端BTRST电连接，第十八晶体管M18的第二极与第一电压信号端V1电连接。
例如，在第一插黑节点M的电压为高电平、且第二复位信号的电平为高电平的情况下，第十七晶体管M17可以在第一插黑节点M的电压的控制下导通，第十八晶体管M18可以在第二复位信号的控制下导通，第十八晶体管M18可以接收并传输第一电压信号至第十七晶体管M17的第二极，然后第十七晶体管M17可以将该第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在一些实施例中，移位寄存器100还可以包括其他的电路结构，具体可以根据实际需要选择设置。
在一些示例中，如图23～图25所示，移位寄存器100中的第一扫描单元1还可以包括：第一控制电路15。
示例性的，如图23～图25所示，第一控制电路15与第一上拉节点Q<1>、第一下拉节点QB_A、第一电压信号端V1及第二电压信号端V2电连接。其中，第一控制电路15被配置为，响应于在第二电压信号端V2处接收的第二电压信号，将第二电压信号传输至第一下拉节点QB_A，并且，在第一上拉节点Q<1>的电压的控制下，将在第一电压信号端V1处接收的第一电压信号传输至第一下拉节点QB_A。
例如，第一控制电路15可以在第二电压信号的控制下，接收并传输第二电压信号至第一下拉节点QB_A。在第一上拉节点Q<1>的电压为高电平的情况下，第一控制电路15可以在第一上拉节点Q<1>的电压的控制下，接收并传输第一电压信号传输至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图23～图25所示，在移位寄存器100还包括第二扫描单元3的情况下，第二扫描单元3还可以包括：第二控制电路35。
示例性的，如图23～图25所示，第二控制电路35与第二上拉节点Q<2>、第二下拉节点QB_B、第一电压信号端V1及第三电压信号端V3电连接。其中，第二控制电路35被配置为，响应于在第三电压信号端V3处接收的第三电压信号，将第三电压信号传输至第二下拉节点QB_B，并且，在第二上拉节点Q<2>的电压的控制下，将第一电压信号传输至第二下拉节点QB_B。
例如，第二控制电路35可以在第三电压信号的控制下，接收并传输第三电压信号至第二下拉节点QB_B。在第二上拉节点Q<2>的电压为高电平的情况下，第二控制电路35可以在第二上拉节点Q<2>的电压的控制下，接收并传输第一电压信号传输至第二下拉节点QB_B，对第二下拉节点QB_B进行下拉复位。
此处，第二电压信号端V2例如可以被配置为传输直流高电平信号(例如高于或等于时钟信号的高电平部分)。第三电压信号端V3例如可以被配置为传输直流高电平信号(例如高于或等于时钟信号的高电平部分)。本文中提及的“高电平”和“低电平”是相对而言的。示例性的，第二电压信号的电压值大于第一电压信号的电压值。
此外，第二电压信号端V2例如还可以被配置为，在一帧的显示阶段中传输直流高电平信号(例如高于或等于时钟信号的高电平部分)。第三电压信号端V3例如可以被配置为，在一帧的显示阶段中传输直流高电平信号(例如高于或等于时钟信号的高电平部分)。其中，第二电压信号和第三电压信号互为反相信号。
下面结合附图对第一控制电路15和第二控制电路35的结构进行示意性说明。
在一些示例中，如图24和图25所示，第一控制电路15包括：第十九晶体管M19、第二十晶体管M20、第二十一晶体管M21和第二十二晶体管M22。
示例性的，如图24和图25所示，第十九晶体管M19的控制极与第二电压信号端V2电连接，第十九晶体管M19的第一极与第二电压信号端V2电连接，第十九晶体管M19的第二极与第二十晶体管M20的控制极及第二十一晶体管M21的第一极电连接。第二十晶体管M20的第一极与第二电压信号端V2电连接，第二十晶体管M20的第二极与第一下拉节点QB_A电连接。
例如，第十九晶体管M19可以在第二电压信号的控制下导通，接收并传输第二电压信号至第二十晶体管M20的控制极。第二十晶体管M20可以在该第二电压信号的控制下导通，接收并传输第二电压信号至第一下拉节点QB_A，对第一下拉节点QB_A进行充电，使得第一下拉节点QB_A的电压抬升。
示例性的，如图24和图25所示，第二十一晶体管M21的控制极与第一上拉节点Q<1>电连接，第二十一晶体管M21的第二极与第一电压信号端V1电连接。
例如，在第一上拉节点Q<1>的电压为高电平的情况下，第二十一晶体管M21可以在第一上拉节点Q<1>的控制下导通，接收并传输第一电压信号至第二十晶体管M20的控制极。第二十晶体管M20可以在第一电压信号的控制下关断。
示例性的，如图24和图25所示，第二十二晶体管M22的控制极与第一上拉节点Q<1>电连接，第二十二晶体管M22的第一极与第一下拉节点QB_A电连接，第二十二晶体管M22的第二极与第一电压信号端V1电连接。
例如，在第一上拉节点Q<1>的电压为高电平的情况下，第二十二晶体管M22可以在第一上拉节点Q<1>的控制下导通，接收并传输第一电压信号至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图24和图25所示，第二控制电路35包括：第二十三晶体管M23、第二十四晶体管M24、第二十五晶体管M25和第二十六晶体管M26。
示例性的，如图24和图25所示，第二十三晶体管M23的控制极与第三电压信号端V3电连接，第二十三晶体管M23的第一极与第三电压信号端V3电连接，第二十三晶体管M23的第二极与第二十四晶体管M24的控制极及第二十五晶体管M25的第一极电连接。第二十四晶体管M24的第一极与第三电压信号端V3电连接，第二十四晶体管M24的第二极与第二下拉节点QB_B电连接。
例如，第二十三晶体管M23可以在第三电压信号的控制下导通，接收并传输第三电压信号至第二十四晶体管M24的控制极。第二十四晶体管M24可以在该第三电压信号的控制下导通，接收并传输第三电压信号至第二下拉节点QB_B，对第二下拉节点QB_B进行充电，使得第二下拉节点QB_B的电压抬升。
示例性的，如图24和图25所示，第二十五晶体管M25的控制极与第二上拉节点Q<2>电连接，第二十五晶体管M25的第二极与第一电压信号端V1电连接。
例如，在第二上拉节点Q<2>的电压为高电平的情况下，第二十五晶体管M25可以在第二上拉节点Q<2>的控制下导通，接收并传输第一电压信号至第二十四晶体管M24的控制极。第二十四晶体管M24可以在第一电压信号的控制下关断。
示例性的，如图24和图25所示，第二十六晶体管M26的控制极与第二上拉节点Q<2>电连接，第二十六晶体管M26的第一极与第二下拉节点QB_B电连接，第二十六晶体管M26的第二极与第一电压信号端V1电连接。
例如，在第二上拉节点Q<2>的电压为高电平的情况下，第二十六晶体管M26可以在 第二上拉节点Q<2>的控制下导通，接收并传输第一电压信号至第二下拉节点QB_B，对第二下拉节点QB_B进行下拉复位。
在一些实施例中，移位寄存器100还可以包括其他的电路结构，具体可以根据实际需要选择设置。
在一些示例中，如图26～图28所示，第一扫描单元1还包括：第五复位电路16、第六复位电路17和第七复位电路18。
示例性的，如图26～图28所示，第五复位电路16与第一下拉节点QB_A、第一上拉节点Q<1>及第一电压信号端V1电连接。其中，第五复位电路16被配置为，在第一下拉节点QB_A的电压的控制下，将第一电压信号传输至第一上拉节点Q<1>。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第五复位电路16可以在第一下拉节点QB_A的电压的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
示例性的，如图26～图28所示，第六复位电路17与第一下拉节点QB_A、第一扫描信号端Oput1<N>及第四电压信号端V4电连接。其中，第六复位电路17被配置为，在第一下拉节点QB_A的电压的控制下，将在第四电压信号端V4处接收的第四电压信号传输至第一扫描信号端Oput1<N>。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第六复位电路17可以在第一下拉节点QB_A的电压的控制下导通，将在第四电压信号端V4处接收的第四电压信号传输至第一扫描信号端Oput1<N>，对第一扫描信号端Oput1<N>进行下拉复位。
此处，第四电压信号端V4例如可以被配置为传输直流低电平信号(例如低于或等于时钟信号的低电平部分)。示例性的，该第四电压信号端V4接地。其中，第一电压信号的电压值和第四电压信号的电压值可以相等，也可以不相等。
示例性的，如图26～图28所示，在第一输出电路12还与第三时钟信号端CLKF1及第一感测信号端Oput2<N>电连接的情况下，第六复位电路17还与第一感测信号端Oput2<N>电连接。其中，第六复位电路17还被配置为，在第一下拉节点QB_A的电压的控制下，将第四电压信号传输至第一感测信号端Oput2<N>。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第六复位电路17可以在第一下拉节点QB_A的电压的控制下导通，将在第四电压信号端V4处接收的第四电压信号传输至第一感测信号端Oput2<N>，对第一感测信号端Oput2<N>进行下拉复位。
示例性的，如图26～图28所示，在第一输出电路12还与第五时钟信号端CLKD1及第一移位信号端CR<N>电连接的情况下，第六复位电路17还与第一移位信号端CR<N>及第一电压信号端V1电连接。其中，第六复位电路17还被配置为，在第一下拉节点QB_A的电压的控制下，将第一电压信号传输至第一移位信号端CR<N>。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第六复位电路17可以在第一下拉节点QB_A的电压的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第一移位信号端CR<N>，对第一移位信号端CR<N>进行下拉复位。
示例性的，如图26～图28所示，在插黑电路2包括插黑控制子电路21的情况下，第七复位电路18与第一插黑节点M、第二控制信号端BCS2、第一下拉节点QB_A及第一电压信号端V1电连接。其中，第七复位电路18被配置为，在第一插黑节点M的电压及第二控制信号的控制下，将第一电压信号传输至第一下拉节点QB_A。
例如，在第一插黑节点M的电压为高电平、且第二控制信号的电平为高电平的情况下，第七复位电路18可以在第一插黑节点M的电压及第二控制信号的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图26～图28所示，第二扫描单元3还包括：第八复位电路36、第九复位电路37和第十复位电路38。
示例性的，如图26～图28所示，第八复位电路36与第二下拉节点QB_B、第二上拉节点Q<2>及第一电压信号端V1电连接。其中，第八复位电路36被配置为，在第二下拉节点QB_B的电压的控制下，将第一电压信号传输至第二上拉节点Q<2>。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第八复位电路36可以在第二下拉节点QB_B的电压的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
示例性的，如图26～图28所示，第九复位电路37与第二下拉节点QB_B、第二扫描信号端Oput1<N+1>及第四电压信号端V4电连接。其中，第九复位电路37被配置为，在第二下拉节点QB_B的电压的控制下，将第四电压信号传输至第二扫描信号端Oput1<N+1>。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第九复位电路37可以在第二下拉节点QB_B的电压的控制下导通，将在第四电压信号端V4处接收的第四电压信号传输至第二扫描信号端Oput1<N+1>，对第二扫描信号端Oput1<N+1>进行下拉复位。
示例性的，如图26～图28所示，在第二输出电路32还与第四时钟信号端CLKF2及第二感测信号端Oput2<N+1>电连接的情况下，第九复位电路37还与第二感测信号端Oput2<N+1>电连接。其中，第九复位电路37还被配置为，在第二下拉节点QB_B的电压的控制下，将第四电压信号传输至第二感测信号端Oput2<N+1>。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第九复位电路37可以在第二下拉节点QB_B的电压的控制下导通，将在第四电压信号端V4处接收的第四电压信号传输至第二感测信号端Oput2<N+1>，对第二感测信号端Oput2<N+1>进行下拉复位。
示例性的，如图26～图28所示，在第二输出电路32还与第六时钟信号端CLKD2及第二移位信号端CR2<N+1>电连接的情况下，第九复位电路37还与第二移位信号端CR2<N+1>及第一电压信号端V1电连接。其中，第九复位电路37还被配置为，在第二下拉节点QB_B的电压的控制下，将第一电压信号传输至第二移位信号端CR2<N+1>。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第九复位电路37可以在第二下拉节点QB_B的电压的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第二移位信号端CR2<N+1>，对第二移位信号端CR2<N+1>进行下拉复位。
示例性的，如图26～图28所示，第十复位电路38与第一插黑节点M、第二控制信号端BCS2、第二下拉节点QB_B及第一电压信号端V1电连接。其中，第十复位电路38被配置为，在第一插黑节点M的电压及第二控制信号的控制下，将第一电压信号传输至第二下拉节点QB_B。
例如，在第一插黑节点M的电压为高电平、且第二控制信号的电平为高电平的情况下，第十复位电路38可以在第一插黑节点M的电压及第二控制信号的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第二下拉节点QB_B，对第二下拉节点QB_B 进行下拉复位。
下面结合附图对第五复位电路16、第六复位电路17、第七复位电路18、第八复位电路36、第九复位电路37和第十复位电路38的结构进行示意性说明。
在一些示例中，如图27和图28所示，第五复位电路16包括：第二十七晶体管M27。
示例性的，如图27和图28所示，第二十七晶体管M27的控制极与第一下拉节点QB_A电连接，第二十七晶体管M27的第一极与第一上拉节点Q<1>电连接，第二十七晶体管M27的第二极与第一电压信号端V1电连接。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第二十七晶体管M27可以在第一下拉节点QB_A的电压的控制下导通，接收并传输第一电压信号至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在一些示例中，如图27和图28所示，第六复位电路17包括：第二十八晶体管M28、第二十九晶体管M29和第三十晶体管M30。
示例性的，如图27和图28所示，第二十八晶体管M28的控制极与第一下拉节点QB_A电连接，第二十八晶体管M28的第一极与第一扫描信号端Oput1<N>电连接，第二十八晶体管M28的第二极与第四电压信号端V4电连接。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第二十八晶体管M28可以在第一下拉节点QB_A的电压的控制下导通，接收并传输第四电压信号至第一扫描信号端Oput1<N>，对第一扫描信号端Oput1<N>进行下拉复位。
示例性的，如图27和图28所示，第二十九晶体管M29的控制极与第一下拉节点QB_A电连接，第二十九晶体管M29的第一极与第一感测信号端Oput2<N>电连接，第二十九晶体管M29的第二极与第四电压信号端V4电连接。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第二十九晶体管M29可以在第一下拉节点QB_A的电压的控制下导通，接收并传输第四电压信号至第一感测信号端Oput2<N>，对第一感测信号端Oput2<N>进行下拉复位。
示例性的，如图27和图28所示，第三十晶体管M30的控制极与第一下拉节点QB_A电连接，第三十晶体管M30的第一极与第一移位信号端CR<N>电连接，第三十晶体管M30的第二极与第一电压信号端V1电连接。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第三十晶体管M30可以在第一下拉节点QB_A的电压的控制下导通，接收并传输第一电压信号至第一移位信号端CR<N>，对第一移位信号端CR<N>进行下拉复位。
在一些示例中，如图27和图28所示，第七复位电路18包括：第三十一晶体管M31和第三十二晶体管M32。
示例性的，如图27和图28所示，第三十一晶体管M31的控制极与第一插黑节点M电连接，第三十一晶体管M31的第一极与第一下拉节点QB_A电连接，第三十一晶体管M31的第二极与第三十二晶体管M32的第一极电连接。第三十二晶体管M32的控制极与第二控制信号端BCS2电连接，第三十二晶体管M32的第二极与第一电压信号端V1电连接。
例如，在第一插黑节点M的电压为高电平、且第二控制信号的电平为高电平的情况下，第三十一晶体管M31可以在第一插黑节点M的电压的控制下导通，第三十二晶体管M32可以在第二控制信号的控制下导通。第三十二晶体管M32可以接收并传输第一电压信号至 第三十一晶体管M31的第二极，第三十一晶体管M31可以将第一电压信号传输至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图27和图28所示，第八复位电路36包括：第三十三晶体管M33。
示例性的，如图27和图28所示，第三十三晶体管M33的控制极与第二下拉节点QB_B电连接，第三十三晶体管M33的第一极与第二上拉节点Q<2>电连接，第三十三晶体管M33的第二极与第一电压信号端V1电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第三十三晶体管M33可以在第二下拉节点QB_B的电压的控制下导通，接收并传输第一电压信号至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在一些示例中，如图27和图28所示，第九复位电路37包括：第三十四晶体管M34、第三十五晶体管M35和第三十六晶体管M36。
示例性的，如图27和图28所示，第三十四晶体管M34的控制极与第二下拉节点QB_B电连接，第三十四晶体管M34的第一极与第二扫描信号端Oput1<N+1>电连接，第三十四晶体管M34的第二极与第四电压信号端V4电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第三十四晶体管M34可以在第二下拉节点QB_B的电压的控制下导通，接收并传输第四电压信号至第二扫描信号端Oput1<N+1>，对第二扫描信号端Oput1<N+1>进行下拉复位。
示例性的，如图27和图28所示，第三十五晶体管M35的控制极与第二下拉节点QB_B电连接，第三十五晶体管M35的第一极与第二感测信号端Oput2<N+1>电连接，第三十五晶体管M35的第二极与第四电压信号端V4电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第三十五晶体管M35可以在第二下拉节点QB_B的电压的控制下导通，接收并传输第四电压信号至第二感测信号端Oput2<N+1>，对第二感测信号端Oput2<N+1>进行下拉复位。
示例性的，如图27和图28所示，第三十六晶体管M36的控制极与第二下拉节点QB_B电连接，第三十六晶体管M36的第一极与第二移位信号端CR2<N+1>电连接，第三十六晶体管M36的第二极与第一电压信号端V1电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第三十六晶体管M36可以在第二下拉节点QB_B的电压的控制下导通，接收并传输第一电压信号至第二移位信号端CR2<N+1>，对第二移位信号端CR2<N+1>进行下拉复位。
在一些示例中，如图27和图28所示，第十复位电路38包括：第三十七晶体管M37和第三十八晶体管M38。
示例性的，如图27和图28所示，第三十七晶体管M37的控制极与第一插黑节点M电连接，第三十七晶体管M37的第一极与第二下拉节点QB_B电连接，第三十七晶体管M37的第二极与第三十八晶体管M38的第一极电连接。第三十八晶体管M38的控制极与第二控制信号端BCS2电连接，第三十八晶体管M38的第二极与第一电压信号端V1电连接。
例如，在第一插黑节点M的电压为高电平、且第二控制信号的电平为高电平的情况下，第三十七晶体管M37可以在第一插黑节点M的电压的控制下导通，第三十八晶体管M38可以在第二控制信号的控制下导通。第三十八晶体管M38可以接收并传输第一电压信号至第三十七晶体管M37的第二极，第三十七晶体管M37可以将第一电压信号传输至第二下 拉节点QB_B，对第二下拉节点QB_B进行下拉复位。
在一些实施例中，移位寄存器100还可以包括其他的电路结构，具体可以根据实际需要选择设置。
在一些示例中，如图28所示，第五复位电路16还与第二下拉节点QB_B电连接。其中，第五复位电路16还被配置为，在第二下拉节点QB_B的电压的控制下，将第一电压信号传输至第一上拉节点Q<1>。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第五复位电路16可以在第二下拉节点QB_B的电压的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在一些示例中，如图28所示，第六复位电路17还与第二下拉节点QB_B电连接。其中，第六复位电路17还被配置为，在第二下拉节点QB_B的电压的控制下，将第四电压信号传输至第一扫描信号端Oput1<N>，将第四电压信号传输至第一感测信号端Oput2<N>，将第一电压信号传输至第一移位信号端CR<N>。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第六复位电路17可以在第二下拉节点QB_B的电压的控制下导通，接收并传输第四电压信号至第一扫描信号端Oput1<N>，对第一扫描信号端Oput1<N>进行下拉复位；接收并传输第四电压信号至第一感测信号端Oput2<N>，对第一感测信号端Oput2<N>进行下拉复位；接收并传输第一电压信号至第一移位信号端CR<N>，对第一移位信号端CR<N>进行下拉复位。
在一些示例中，如图28所示，第八复位电路36还与第一下拉节点QB_A电连接。其中，第八复位电路36还被配置为，在第一下拉节点QB_A的电压的控制下，将第一电压信号传输至第二上拉节点Q<2>。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第八复位电路36可以在第一下拉节点QB_A的电压的控制下导通，将在第一电压信号端V1处接收的第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在一些示例中，如图28所示，第九复位电路37还与第一下拉节点QB_A电连接。其中，第九复位电路37还被配置为，在第一下拉节点QB_A的电压的控制下，将第四电压信号传输至第二扫描信号端Oput1<N+1>，将第四电压信号传输至所述第二感测信号端Oput2<N+1>，将第一电压信号传输至第二移位信号端CR2<N+1>。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第九复位电路37可以在第一下拉节点QB_A的电压的控制下导通，接收并传输第四电压信号至第二扫描信号端Oput1<N+1>，对第二扫描信号端Oput1<N+1>进行下拉复位；接收并传输第四电压信号至第二感测信号端Oput2<N+1>，对第二感测信号端Oput2<N+1>进行下拉复位；接收并传输第一电压信号至第二移位信号端CR2<N+1>，对第二移位信号端CR2<N+1>进行下拉复位。
在上述示例中，第二电压信号和第三电压信号例如可以互为反相信号。这样可以在不同的显示时段，采用不同的复位电路中的不同结构对第一下拉节点QB_A或第二下拉节点QB_B进行复位，减少相应结构的工作时长，提高移位寄存器100及扫描驱动电路1000的使用寿命。
下面结合附图对第五复位电路16、第六复位电路17、第八复位电路36和第九复位电路37的结构进行示意性说明。
在一些示例中，如图28所示，第五复位电路16还包括：第三十九晶体管M39。
示例性的，如图28所示，第三十九晶体管M39的控制极与第二下拉节点QB_B电连接，第三十九晶体管M39的第一极与第一上拉节点Q<1>电连接，第三十九晶体管M39的第二极与第一电压信号端V1电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第三十九晶体管M39可以在第二下拉节点QB_B的电压的控制下导通，接收并传输第一电压信号至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在一些示例中，如图28所示，第六复位电路17还包括：第四十晶体管M40、第四十一晶体管M41和第四十二晶体管M42。
示例性的，如图28所示，第四十晶体管M40的控制极与第二下拉节点QB_B电连接，第四十晶体管M40的第一极与第一扫描信号端Oput1<N>电连接，第四十晶体管M40的第二极与第四电压信号端V4电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第四十晶体管M40可以在第二下拉节点QB_B的电压的控制下导通，接收并传输第四电压信号至第一扫描信号端Oput1<N>，对第一扫描信号端Oput1<N>进行下拉复位。
示例性的，如图28所示，第四十一晶体管M41的控制极与第二下拉节点QB_B电连接，第四十一晶体管M41的第一极与第一感测信号端Oput2<N>电连接，第四十一晶体管M41的第二极与第四电压信号端V4电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第四十一晶体管M41可以在第二下拉节点QB_B的电压的控制下导通，接收并传输第四电压信号至第一感测信号端Oput2<N>，对第一感测信号端Oput2<N>进行下拉复位。
示例性的，如图28所示，第四十二晶体管M42的控制极与第二下拉节点QB_B电连接，第四十二晶体管M42的第一极与第一移位信号端CR<N>电连接，第四十二晶体管M42的第二极与第一电压信号端V1电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第四十二晶体管M42可以在第二下拉节点QB_B的电压的控制下导通，接收并传输第一电压信号至第一移位信号端CR<N>，对第一移位信号端CR<N>进行下拉复位。
在一些示例中，如图28所示，第八复位电路36还包括：第四十三晶体管M43。
示例性的，如图28所示，第四十三晶体管M43的控制极与第一下拉节点QB_A电连接，第四十三晶体管M43的第一极与第二上拉节点Q<2>电连接，第四十三晶体管M43的第二极与第一电压信号端V1电连接。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第四十三晶体管M43可以在第一下拉节点QB_A的电压的控制下导通，接收并传输第一电压信号至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在一些示例中，如图28所示，第九复位电路37还包括：第四十四晶体管M44、第四十五晶体管M45和第四十六晶体管M46。
示例性的，如图28所示，第四十四晶体管M44的控制极与第一下拉节点QB_A电连接，第四十四晶体管M44的第一极与第二扫描信号端Oput1<N+1>电连接，第四十四晶体管M44的第二极与第四电压信号端V4电连接。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第四十四晶体管M44可以在第一下拉节点QB_A的电压的控制下导通，接收并传输第四电压信号至第二扫描信号端 Oput1<N+1>，对第二扫描信号端Oput1<N+1>进行下拉复位。
示例性的，如图28所示，第四十五晶体管M45的控制极与第一下拉节点QB_A电连接，第四十五晶体管M45的第一极与第二感测信号端Oput2<N+1>电连接，第四十五晶体管M45的第二极与第四电压信号端V4电连接。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第四十五晶体管M45可以在第一下拉节点QB_A的电压的控制下导通，接收并传输第四电压信号至第二感测信号端Oput2<N+1>，对第二感测信号端Oput2<N+1>进行下拉复位。
示例性的，如图28所示，第四十六晶体管M46的控制极与第一下拉节点QB_A电连接，第四十六晶体管M46的第一极与第二移位信号端CR2<N+1>电连接，第四十六晶体管M46的第二极与第一电压信号端V1电连接。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第四十六晶体管M46可以在第一下拉节点QB_A的电压的控制下导通，接收并传输第一电压信号至第二移位信号端CR2<N+1>，对第二移位信号端CR2<N+1>进行下拉复位。
由前述，一帧的显示阶段例如可以包括依次进行的显示时段和消隐时段。在显示时段，移位寄存器100可以驱动显示装置2000中相应的子像素P进行图像显示；在消隐时段，移位寄存器100可以驱动显示装置2000中相应的子像素P进行外部补偿。
基于此，在一些实施例中，如图34和图35所示，移位寄存器100还可以包括：消隐电路4。
在一些示例中，如图34和图35所示，消隐电路4与第三控制信号端OE、显示输入信号端Iput、第七时钟信号端CLKA、第一上拉节点Q<1>及第一电压信号端V1电连接。其中，消隐电路4被配置为，在第三控制信号端OE所传输的第三控制信号、显示输入信号及第七时钟信号端CLKA所传输的第七时钟信号的控制下，将第七时钟信号传输至第一上拉节点Q<1>。
此外，如图34和图35所示，在移位寄存器100还包括第二扫描单元3的情况下，消隐电路4还与第二上拉节点Q<2>电连接。其中，消隐电路4还被配置为，将第七时钟信号传输至第二上拉节点Q<2>。
例如，在一帧的显示阶段中的消隐时段，在选择控制信号的电平为高电平、显示输入信号的电平为高电平且第七时钟信号的电平为高电平的情况下，消隐电路4可以在第三控制信号、显示输入信号及第七时钟信号的控制下导通，将在第七时钟信号端CLKA处接收的第七时钟信号传输至第一上拉节点Q<1>和第二上拉节点Q<2>，对第一上拉节点Q<1>和第二上拉节点Q<2>进行充电。
在第一上拉节点Q<1>的电压升高后，第一输出电路12可以在第一上拉节点Q<1>的电压的控制下导通。如果第一输出电路12未与第一感测信号端Oput2<N>电连接，则第一输出电路12可以将在第一时钟信号端CLKE1处接收的第二时钟信号同时作为第一扫描信号和第一感测驱动信号，从第一扫描信号端Oput1<N>输出。如果第一输出电路12与第一感测信号端Oput2<N>电连接，则第一输出电路12可以将在第三时钟信号端CLKF1处接收的第三时钟信号作为第一感测信号，从第一感测信号端Oput2<N>输出。利用第一感测信号可以驱动相应的子像素P进行外部补偿。
在第二上拉节点Q<2>的电压升高后，第二输出电路32可以在第二上拉节点Q<2>的电压的控制下导通。如果第二输出电路32未与第二感测信号端Oput2<N+1>电连接，则第 二输出电路32可以将在第二时钟信号端CLKE2处接收的第二时钟信号同时作为第二扫描信号和第二感测驱动信号，从第二扫描信号端Oput1<N+1>输出。如果第二输出电路32与第二感测信号端Oput2<N+1>电连接，则第二输出电路32可以将在第四时钟信号端CLKF2处接收的第四时钟信号作为第二感测信号，从第二感测信号端Oput2<N+1>输出。利用第二感测信号可以驱动相应的子像素P进行外部补偿。
由上，在移位寄存器100包括第二扫描单元3的情况下，第一扫描单元1和第二扫描单元3可以共用消隐电路4。这样有利于简化移位寄存器100及扫描驱动电路1000的结构，提高移位寄存器100及扫描驱动电路1000的良率。
此外，在移位寄存器100还包括其他扫描单元的情况下，消隐电路4还可以包括其他的消隐传输子电路，以使得多个扫描单元能够共用消隐电路4。
在一些实施例中，如图34和图35所示，消隐电路4包括：选择控制子电路41、消隐输入子电路42、第一消隐传输子电路43和第二消隐传输子电路44。
在一些示例中，如图34和图35所示，选择控制子电路41与第三控制信号端OE、显示输入信号端Iput、第一消隐节点H及第一电压信号端V1电连接。其中，选择控制子电路41被配置为，在第三控制信号的控制下，将显示输入信号传输至第一消隐节点H。
示例性的，在第三控制信号的电平为高电平的情况下，选择控制子电路41可以在该第三控制信号的控制下导通，并将所接收的显示输入信号传输至第一消隐节点H，对第一消隐节点H进行充电，使得第一消隐节点H的电压升高。
例如，在移位寄存器100需要输出感测信号时，可以使得第三控制信号的波形时序和显示输入信号的波形时序相同，进而使得选择控制子电路41导通。
在一些示例中，如图34和图35所示，消隐传输子电路42与第一消隐节点H、第七时钟信号端CLKA及第二消隐节点N电连接。其中，消隐传输子电路42被配置为，在第一消隐节点H的电压的控制下，将第七时钟信号传输至第二消隐节点N。
示例性的，在选择控制子电路41导通使得第一消隐节点H的电压升高的情况下，消隐传输子电路42可以在第一消隐节点H的电压的控制下导通，接收第七时钟信号端CLKA所传输的第七时钟信号，并将该第七时钟信号传输至第二消隐节点N。
在一些示例中，如图34和图35所示，第一消隐传输子电路43与第七时钟信号端CLKA、第二消隐节点N及第一上拉节点Q<1>电连接。其中，第一消隐传输子电路43被配置为，在第七时钟信号的控制下，将来自第二消隐节点N的第七时钟信号传输至第一上拉节点Q<1>。
示例性的，在第七时钟信号的电平为高电平的情况下，第一消隐传输子电路43可以在该第七时钟信号的控制下导通，并从第二消隐节点N处接收第七时钟信号，将所接收的第七时钟信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电，使得第一上拉节点Q<1>的电压升高。
在一些示例中，如图34和图35所示，第二消隐传输子电路44与第七时钟信号端CLKA、第二消隐节点N及第二上拉节点Q<2>电连接。其中，第二消隐传输子电路44被配置为，在第七时钟信号的控制下，将来自第二消隐节点N的第七时钟信号传输至第二上拉节点Q<2>。
示例性的，在第七时钟信号的电平为高电平的情况下，第二消隐传输子电路44可以在该第七时钟信号的控制下导通，并从第二消隐节点N处接收第七时钟信号，将所接收的 第七时钟信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电，使得第二上拉节点Q<2>的电压升高。
下面结合附图对消隐电路4所包括的选择控制子电路41、消隐输入子电路42、第一消隐传输子电路43和第二消隐传输子电路44的结构进行示意性说明。
在一些示例中，如图34和图35所示，选择控制子电路41包括：第四十七晶体管M47和第六电容器C6。
示例性的，如图34和图35所示，第四十七晶体管M47的控制极与第三控制信号端OE电连接，第四十七晶体管M47的第一极与Iput显示输入信号端电连接，第四十七晶体管M47的第二极与第一消隐节点H电连接。
例如，在选择控制信号端OE所传输的选择控制信号的电平为高电平的情况下，第四十七晶体管M47可以在选择控制信号的作用下导通，接收并传输显示输入信号至第一消隐节点H，对第一消隐节点H进行充电，使得第一消隐节点H的电压升高。
示例性的，如图34和图35所示，第六电容器C6的第一端与第一消隐节点H电连接，第六电容器C6的第二端与第一电压信号端V1电连接。
例如，在第四十七晶体管M47导通、并对第一消隐节点H进行充电的过程中，还会对第六电容器C6进行充电。这样可以在第四十七晶体管M47关断的情况下，利用第六电容器C6放电，使得第一消隐节点H保持高电平。
在一些示例中，如图34和图35所示，消隐输入子电路42包括：第四十八晶体管M48。
示例性的，如图34和图35所示，第四十八晶体管M48的控制极与第一消隐节点H电连接，第四十八晶体管M48的第一极与第七时钟信号端CLKA电连接，第四十八晶体管M48的第二极与第二消隐节点N电连接。
例如，在第一消隐节点H的电压为高电平的情况下，第四十八晶体管M48可以在第一消隐节点H的电压的控制下导通，将在第七时钟信号端CLKA处接收的第七时钟信号传输至第二消隐节点N。
在一些示例中，如图34和图35所示，第一消隐传输子电路43包括：第四十九晶体管M49。
示例性的，如图34和图35所示，第四十九晶体管M49的控制极与第七时钟信号端CLKA电连接，第四十九晶体管M49的第一极与第二消隐节点N电连接，第四十九晶体管M49的第二极与第一上拉节点Q<1>电连接。
例如，在第七时钟信号端CLKA所传输的第七时钟信号的电平为高电平的情况下，第四十九晶体管M49可以在第七时钟信号的作用下导通，接收并传输来自第二消隐节点N的第七时钟信号至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电。
在一些示例中，如图34和图35所示，第二消隐传输子电路44包括：第五十晶体管M50。
示例性的，如图34和图35所示，第五十晶体管M50的控制极与第七时钟信号端CLKA电连接，第五十晶体管M50的第一极与第二消隐节点N电连接，第五十晶体管M50的第二极与第二上拉节点Q<2>电连接。
例如，在第七时钟信号的电平为高电平的情况下，第五十晶体管M50可以在第七时钟信号的作用下导通，接收并传输来自第二消隐节点N的第七时钟信号至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电。
在一些实施例中，如图34和图35所示，移位寄存器100中，第一扫描单元1还包括：第十一复位电路19、第十二复位电路110及第十三复位电路111，第二扫描单元3还包括：第十四复位电路39、第十五复位电路310及第十六复位电路311。
在一些示例中，如图34和图35所示，第十一复位电路19与全局复位信号端TRST、第一上拉节点Q<1>及第一电压信号端V1电连接。其中，第十一复位电路19被配置为，在全局复位信号端TRST所传输的全局复位信号的控制下，将第一电压信号传输至第一上拉节点Q<1>。
示例性的，在全局复位信号的电平为高电平的情况下，第十一复位电路19可以在全局复位信号的作用下导通，将第一电压信号端V1所传输的第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在一些示例中，如图34和图35所示，第十二复位电路110与显示输入信号端Iput、第一下拉节点QB_A及第一电压信号端V1电连接。其中，第十二复位电路110被配置为，在显示输入信号的控制下，将第一电压信号传输至第一下拉节点QB_A。
示例性的，在显示输入信号的电平为高电平的情况下，第十二复位电路110可以在输入信号的作用下导通，将第一电压信号传输至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图34和图35所示，在消隐电路4包括选择控制子电路41的情况下，第十三复位电路111与第一消隐节点H、第七时钟信号端CLKA、第一下拉节点QB_A及第一电压信号端V1电连接。其中，第十三复位电路111被配置为，在第一消隐节点H的电压和第七时钟信号的控制下，将第一电压信号传输至第一下拉节点QB_A。
示例性的，在第一消隐节点H的电压为高电平、且第七时钟信号的电平为高电平的情况下，第十三复位电路111可以在第一消隐节点H的电压和第七时钟信号的作用下导通，将第一电压信号传输至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图34和图35所示，第十四复位电路39与全局复位信号端TRST、第二上拉节点Q<2>及第一电压信号端电V1连接。其中，第十四复位电路39被配置为，在全局复位信号的控制下，将第一电压信号传输至第二上拉节点Q<2>。
示例性的，在全局复位信号的电平为高电平的情况下，第十四复位电路39可以在全局复位信号的作用下导通，将第一电压信号端V1所传输的第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在一些示例中，如图34和图35所示，第十五复位电路310与显示输入信号端Iput、第二下拉节点QB_B及第一电压信号端V1电连接。其中，第十五复位电路310被配置为，在显示输入信号的控制下，将第一电压信号传输至第二下拉节点QB_B。
示例性的，在显示输入信号的电平为高电平的情况下，第十五复位电路310可以在输入信号的作用下导通，将第一电压信号传输至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图34和图35所示，第十六复位电路311与第一消隐节点H、第七时钟信号端CLKA、第二下拉节点QB_B及第一电压信号端V1电连接。其中，第十六复位电路311被配置为，在第一消隐节点H的电压和第七时钟信号的控制下，将第一电压信号传输至第二下拉节点QB_B。
示例性的，在第一消隐节点H的电压为高电平、且第七时钟信号的电平为高电平的情 况下，第十六复位电路311可以在第一消隐节点H的电压和第七时钟信号的作用下导通，将第一电压信号传输至第二下拉节点QB_B，对第二下拉节点QB_B进行下拉复位。
下面结合附图对第十一复位电路19、第十二复位电路110、第十三复位电路111、第十四复位电路39、第十五复位电路310及第十六复位电路311的结构进行示意性说明。
在一些示例中，如图34和图35所示，第十一复位电路19包括：第五十一晶体管M51。
示例性的，如图34和图35所示，第五十一晶体管M51的控制极与全局复位信号端TRST电连接，第五十一晶体管M51的第一极与第一上拉节点Q<1>电连接，第五十一晶体管M51的第二极与第一电压信号端V1电连接。
例如，在全局复位信号的电平为高电平的情况下，第五十一晶体管M51可以在全局复位信号的作用下导通，将第一电压信号端V1所传输的第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行复位。
在一些示例中，如图34和图35所示，第十二复位电路110包括：第五十二晶体管M52。
示例性的，如图34和图35所示，第五十二晶体管M52的控制极与显示输入信号端Iput电连接，第五十二晶体管M52的第一极与第一下拉节点QB_A电连接，第五十二晶体管M52的第二极与第一电压信号端V1电连接。
示例性的，在显示输入信号的电平为高电平的情况下，第五十二晶体管M52可以在输入信号的作用下导通，将第一电压信号传输至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图34和图35所示，第十三复位电路111包括：第五十三晶体管M53和第五十四晶体管M54。
示例性的，如图34和图35所示，第五十三晶体管M53的控制极与第一消隐节点H电连接，第五十三晶体管M53的第一极与第一下拉节点QB_A电连接，第五十三晶体管M53的第二极与第五十四晶体管M54的第一极电连接。第五十四晶体管M54的控制极与第七时钟信号端CLKA电连接，第五十四晶体管M54的第二极与第一电压信号端V1电连接。
例如，在第一消隐节点H的电压为高电平、且第七时钟信号的电平为高电平的情况下，第五十三晶体管M53可以在第一消隐节点H的电压的作用下导通，第五十四晶体管M54可以在第七时钟信号的作用下导通。第五十四晶体管M54可以接收并传输第一电压信号至第五十三晶体管M53的第二极。第五十三晶体管M53可以接收并传输第一电压信号至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图34和图35所示，第十四复位电路39包括：第五十五晶体管M55。
示例性的，如图34和图35所示，第五十五晶体管M55的控制极与全局复位信号端TRST电连接，第五十五晶体管M55的第一极与第二上拉节点Q<2>电连接，第五十五晶体管M55的第二极与第一电压信号端V1电连接。
例如，在全局复位信号的电平为高电平的情况下，第五十五晶体管M55可以在全局复位信号的作用下导通，将第一电压信号端V1所传输的第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行复位。
在一些示例中，如图34和图35所示，第十五复位电路310包括：第五十六晶体管M56。
示例性的，如图34和图35所示，第五十六晶体管M56的控制极与显示输入信号端Iput电连接，第五十六晶体管M56的第一极与第二下拉节点QB_B电连接，第五十六晶体管M56的第二极与第一电压信号端V1电连接。
示例性的，在显示输入信号的电平为高电平的情况下，第五十六晶体管M56可以在输入信号的作用下导通，将第一电压信号传输至第一下拉节点QB_A，对第一下拉节点QB_A进行下拉复位。
在一些示例中，如图34和图35所示，第十六复位电路311包括：第五十七晶体管M57和第五十八晶体管M58。
示例性的，如图34和图35所示，第五十七晶体管M57的控制极与第一消隐节点H电连接，第五十七晶体管M57的第一极与第二下拉节点QB_B电连接，第五十七晶体管M57的第二极与第五十八晶体管M58的第一极电连接。第五十八晶体管M58的控制极与第七时钟信号端CLKA电连接，第五十八晶体管M58的第二极与第一电压信号端V1电连接。
例如，在第一消隐节点H的电压为高电平、且第七时钟信号的电平为高电平的情况下，第五十七晶体管M57可以在第一消隐节点H的电压的作用下导通，第五十八晶体管M58可以在第七时钟信号的作用下导通。第五十八晶体管M58可以接收并传输第一电压信号至第五十七晶体管M57的第二极。第五十七晶体管M57可以接收并传输第一电压信号至第二下拉节点QB_B，对第二下拉节点QB_B进行下拉复位。
在一些实施例中，如图37所示，移位寄存器100还包括：第一防漏电电路5。
在一些示例中，如图37所示，第一防漏电电路5与第一消隐节点H、第五电压信号端V5及第一防漏电节点OFF1电连接。其中，第一防漏电电路5被配置为，在第一消隐节点H的电压的控制下，将在第五电压信号端V5处接收的第五电压信号传输至第一防漏电节点OFF1。
示例性的，在第一消隐节点H的电压为高电平的情况下，第一防漏电电路5可以在第一消隐节点H的电压的控制下导通，接收并传输第五电压信号至第一防漏电节点OFF1，对第一防漏电节点OFF1进行充电，使得第一防漏电节点OFF1的电压升高。
在一些示例中，如图37所示，选择控制子电路41还与第一防漏电节点OFF1电连接。
在选择控制子电路41中的第四十七晶体管M47关断、第六电容器C6进行放电以使得第一消隐节点H的电压保持为高电平的情况下，通过将选择控制子电路41与第一防漏电节点OFF1电连接，可以减小第一防漏电节点OFF1和第一消隐节点H之间的压差，避免第一消隐节点H通过选择控制子电路41漏电，进而可以使得第一消隐节点H能够保持在一个较高的、较为稳定的电压，避免影响消隐输入子电路42的导通状态。
下面结合附图对第一防漏电电路5和选择控制子电路41的结构进行示意性说明。
在一些示例中，如图37所示，第一防漏电电路5包括：第五十九晶体管M59。
示例性的，如图37所示，第五十九晶体管M59的控制极与第一消隐节点H电连接，第五十九晶体管M59的第一极与第五电压信号端V5电连接，第五十九晶体管M59的第二极与第一防漏电节点OFF1电连接。
例如，在第一消隐节点H的电压为高电平的情况下，第五十九晶体管M59可以在第一消隐节点H的电压的控制下导通，接收第五电压信号，并将第五电压信号传输至第一防漏电节点OFF1，对第一防漏电节点OFF1进行充电，使得第一防漏电节点OFF1的电压升 高。
基于此，在一些示例中，如图37所示，选择控制子电路41还可以包括：第六十晶体管M60。
示例性的，如图37所示，第六十晶体管M60的控制极与第三控制信号端OE电连接，第六十晶体管M60的第一极与显示输入信号端Iput电连接，第六十晶体管M60的第二极与第一防漏电节点OFF1电连接。其中，选择控制子电路41中的第四十七晶体管M47的第一极与第一防漏电节点OFF1电连接，并通过上述第六十晶体管M60与显示输入信号端Iput电连接。
例如，在第三控制信号的电平为高电平的情况下，第四十七晶体管M47和第六十晶体管M60可以在第三控制信号的作用下同时导通。第六十晶体管M60可以接收并传输显示输入信号至第一防漏电节点OFF1，第四十七晶体管M47可以接收并传输显示输入信号至第一消隐节点H，对第一消隐节点H进行充电。
在第三控制信号的电平为低电平的情况下，第四十七晶体管M47和第六十晶体管M60可以在第三控制信号的作用下同时关断。选择控制子电路41中的第六电容器C6开始放电，使得第一消隐节点H的电压保持为高电平。在此过程中，第一防漏电电路5中的第五十九晶体管M59可以将第五电压信号传输至第一防漏电节点OFF1，对第一防漏电节点OFF1进行充电，减小第一防漏电节点OFF1和第一消隐节点H之间的压差，并使得第四十七晶体管M47的控制极与第一极之间的压差小于零，确保第四十七晶体管M47被完全或较为完全地截止。这样可以避免第一消隐节点H通过选择控制子电路41漏电，使得第一消隐节点H能够保持在一个较高的、较为稳定的电压。
移位寄存器100还可以包括其他的电路结构，具体可以根据实际需要选择设置。
在一些实施例中，如图31～图33、图36和图37所示，移位寄存器100还与包括：第二防漏电电路7。
在一些示例中，如图31～图33、图36和图37所示，第二防漏电电路7与第一上拉节点Q<1>、第五电压信号端V5及第二防漏电节点OFF2电连接。其中，第二防漏电电路7被配置为，在第一上拉节点Q<1>的电压的控制下，将在第五电压信号端V5处接收的第五电压信号传输至第二防漏电节点OFF2。
示例性的，在第一上拉节点Q<1>的电压为高电平的情况下，第二防漏电电路7可以在第一上拉节点Q<1>的电压的控制下导通，接收并传输第五电压信号至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，使得第二防漏电节点OFF2的电压升高。
下面结合附图对第二防漏电电路7的结构进行示意性说明。
在一些示例中，如图32、图33、图36和图37所示，第二防漏电电路7包括：第六十一晶体管M61。
示例性的，如图32、图33、图36和图37所示，第六十一晶体管M61的控制极与第一上拉节点Q<1>电连接，第六十一晶体管M61的第一极与第五电压信号端V5电连接，第六十一晶体管M61的第二极与第二防漏电节点OFF2电连接。
例如，在第一上拉节点Q<1>的电压为高电平的情况下，第六十一晶体管M61可以在第一上拉节点Q<1>的电压的控制下导通，接收第五电压信号，并将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，使得第二防漏电节点OFF2的电压升高。
需要说明的是，移位寄存器100中所包括的其他电路也可以与第二防漏电节点OFF2电连接。
在一些实施例中，如图32、图33、图36和图37所示，第一输入电路11还可以与第二防漏电节点OFF2电连接。
在第一输入电路11关断、第一输出电路12中的第一电容器C1进行放电以使得第一上拉节点Q<1>的电压保持为高电平的情况下，通过将第一输入电路11与第二防漏电节点OFF2电连接，可以减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，避免第一上拉节点Q<1>通过第一输入电路11漏电，进而可以使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压，避免影响第一输出电路12的导通状态。
基于此，在一些示例中，如图32、图33、图36和图37所示，第一输入电路11还包括：第六十二晶体管M62。
示例性的，如图32、图33、图36和图37所示，第六十二晶体管M62的控制极与显示输入信号端Iput电连接，第六十二晶体管M62的第一极与显示输入信号端Iput电连接，第六十二晶体管M62的第二极与第二防漏电节点OFF2电连接。第一晶体管M1的第一极与第二防漏电节点OFF2电连接，并通过第六十二晶体管M62与显示输入信号端Iput电连接。
例如，在显示输入信号的电平为高电平的情况下，第一晶体管M1和第六十二晶体管M62可以在显示输入信号的作用下同时导通。第六十二晶体管M62可以接收并传输显示输入信号至第二防漏电节点OFF2，第一晶体管M1可以接收并传输显示输入信号至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电。
在显示输入信号的电平为低电平的情况下，第一晶体管M1和第六十二晶体管M62可以在显示输入信号的作用下同时关断。第一输出电路12中的第一电容器C1开始放电，使得第一上拉节点Q<1>的电压保持为高电平。在此过程中，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第一晶体管M1的控制极与第一极之间的压差小于零，确保第一晶体管M1被完全或较为完全地截止。这样可以避免第一上拉节点Q<1>通过第一输入电路11漏电，使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压。
在一些实施例中，如图32、图33、图36和图37所示，在移位寄存器100还包括第二扫描单元3的情况下，第二输入电路31还与第二防漏电节点OFF2电连接。
在第二输入电路31关断、第二输出电路32中的第二电容器C2进行放电以使得第二上拉节点Q<2>的电压保持为高电平的情况下，通过将第二输入电路31与第二防漏电节点OFF2电连接，可以减小第二防漏电节点OFF2和第二上拉节点Q<2>之间的压差，避免第二上拉节点Q<2>通过第二输入电路31漏电，进而可以使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压，避免影响第二输出电路32的导通状态。
基于此，在一些示例中，如图32、图33、图36和图37所示，第二输入电路31中的第三晶体管M3的第一极与第二防漏电节点OFF2电连接，并通过第六十二晶体管M62与显示输入信号端Iput电连接。
例如，在显示输入信号的电平为高电平的情况下，第三晶体管M3和第六十二晶体管M62可以在显示输入信号的作用下同时导通。第六十二晶体管M62可以接收并传输显示 输入信号至第二防漏电节点OFF2，第三晶体管M3可以接收并传输显示输入信号至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电。
在显示输入信号的电平为低电平的情况下，第三晶体管M3和第六十二晶体管M62可以在显示输入信号的作用下同时关断。第二输出电路32中的第二电容器C2开始放电，使得第二上拉节点Q<2>的电压保持为高电平。在此过程中，第一上拉节点Q<1>的电压保持为高电平状态，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第二上拉节点Q<2>之间的压差，并使得第三晶体管M3的控制极与第一极之间的压差小于零，确保第三晶体管M3被完全或较为完全地截止。这样可以避免第二上拉节点Q<2>通过第二输入电路31漏电，使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压。
此外，第二输入电路31共用第一输入电路11中的第六十二晶体管M62，有利于简化移位寄存器100的结构，减小移位寄存器100所占据的面积。
在一些实施例中，如图32、图33、图36和图37所示，插黑电路2还与第二防漏电节点OFF2电连接。
基于此，在一些示例中，如图32、图33、图36和图37所示，在插黑电路2包括第一插黑传输子电路23的情况下，第一插黑传输子电路23还包括：第六十三晶体管M63。
示例性的，如图32、图33、图36和图37所示，第六十三晶体管M63的控制极与第二控制信号端BCS2电连接，第六十三晶体管M63的第一极与第二插黑节点K电连接，第六十三晶体管M63的第二极与第二防漏电节点OFF2电连接。第一插黑传输子电路23中的第七晶体管M7的第一极与第二防漏电节点OFF2电连接，并通过第六十三晶体管M63与第二插黑节点K电连接。
例如，在第二控制信号的电平为高电平的情况下，第七晶体管M7和第六十三晶体管M63可以在第二控制信号的作用下同时导通。第六十三晶体管M63可以接收来自第二插黑节点K的插黑输入信号，并将该插黑输入信号至第二防漏电节点OFF2，第七晶体管M7可以接收并传输插黑输入信号至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电。
在第二控制信号的电平为低电平的情况下，第七晶体管M7和第六十三晶体管M63可以在第二控制信号的作用下同时关断。第一输出电路12中的第一电容器C1开始放电，使得第一上拉节点Q<1>的电压保持为高电平。在此过程中，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第七晶体管M7的控制极与第一极之间的压差小于零，确保第七晶体管M7被完全或较为完全地截止。这样可以避免第一上拉节点Q<1>通过第一插黑传输子电路23漏电，使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压。
在一些示例中，如图32、图33、图36和图37所示，第二插黑传输子电路24中的第八晶体管M8的第一极与第二防漏电节点OFF2电连接，并通过第六十三晶体管M63与第二插黑节点OFF2电连接。
例如，在第二控制信号的电平为高电平的情况下，第八晶体管M8和第六十三晶体管M63可以在第二控制信号的作用下同时导通。第六十三晶体管M63可以接收来自第二插黑节点K的插黑输入信号，并将该插黑输入信号至第二防漏电节点OFF2，第八晶体管M8 可以接收并传输插黑输入信号至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电。
在第二控制信号的电平为低电平的情况下，第八晶体管M8和第六十三晶体管M63可以在第二控制信号的作用下同时关断。第二输出电路22中的第二电容器C2开始放电，使得第二上拉节点Q<2>的电压保持为高电平。在此过程中，第一上拉节点Q<1>的电压保持为高电平状态，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第二上拉节点Q<2>之间的压差，并使得第七晶体管M7的控制极与第一极之间的压差小于零，确保第八晶体管M8被完全或较为完全地截止。这样可以避免第二上拉节点Q<2>通过第二插黑传输子电路24漏电，使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压。
此外，第二插黑传输子电路24共用第一插黑传输子电路23中的第六十三晶体管M63，有利于简化移位寄存器100的结构，减小移位寄存器100所占据的面积。
在一些实施例中，如图32、图33、图36和图37所示，在第一扫描单元1还包括第一复位电路13的情况下，第一复位电路13还与第二防漏电节点OFF2电连接。
在第一上拉节点Q<1>为高电平、且第一复位电路13未工作的情况下，通过将第一复位电路13与第二防漏电节点OFF2电连接，可以减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，避免第一上拉节点Q<1>通过第一复位电路13漏电，进而可以使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压，避免影响第一输出电路12的导通状态。
基于此，在一些示例中，如图32、图33、图36和图37所示，第一复位电路13还包括：第六十四晶体管M64。
示例性的，如图32、图33、图36和图37所示，第六十四晶体管M64的控制极与第一复位信号端STD电连接，第六十四晶体管M64的第一极与第二防漏电节点OFF2电连接，第六十四晶体管M64的第二极与第一电压信号端V1电连接。第一复位电路13中的第十三晶体管M13的第二极与第二防漏电节点OFF2电连接，并通过第六十四晶体管M64与第一电压信号端V1电连接。
例如，在第一复位信号的电平为高电平的情况下，第十三晶体管M13和第六十四晶体管M64可以在第一复位信号的作用下同时导通。第六十四晶体管M64可以接收并传输第一电压信号至第二防漏电节点OFF2，第十三晶体管M13可以将该第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在第一复位信号的电平为低电平的情况下，第十三晶体管M13和第六十四晶体管M64可以在第一复位信号的作用下同时关断。在第一上拉节点Q<1>的电压保持为高电平的情况下，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第十三晶体管M13的控制极与第二极之间的压差小于零，确保第十三晶体管M13被完全或较为完全地截止。这样可以避免第一上拉节点Q<1>通过第一复位电路13漏电，使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压。
在一些实施例中，如图32、图33、图36和图37所示，在第二扫描单元3还包括第三复位电路33的情况下，第三复位电路33还与第二防漏电节点OFF2电连接。
在第一上拉节点Q<1>为高电平、第二上拉节点Q<2>为高电平且第三复位电路33未 工作的情况下，通过将第三复位电路13与第二防漏电节点OFF2电连接，可以减小第二防漏电节点OFF2和第二上拉节点Q<2>之间的压差，避免第二上拉节点Q<2>通过第三复位电路33漏电，进而可以使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压，避免影响第二输出电路32的导通状态。
基于此，在一些示例中，如图32、图33、图36和图37所示，第三复位电路33中的第十六晶体管M16的第二极与第二防漏电节点OFF2电连接，并通过第六十四晶体管M64与第一电压信号端V1电连接。
例如，在第一复位信号的电平为高电平的情况下，第十六晶体管M16和第六十四晶体管M64可以在第一复位信号的作用下同时导通。第六十四晶体管M64可以接收并传输第一电压信号至第二防漏电节点OFF2，第十六晶体管M16可以将该第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在第一复位信号的电平为低电平的情况下，第十六晶体管M16和第六十四晶体管M64可以在第一复位信号的作用下同时关断。在第一上拉节点Q<1>的电压及第二上拉节点Q<2>的电压保持为高电平的情况下，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第二上拉节点Q<2>之间的压差，并使得第十六晶体管M16的控制极与第二极之间的压差小于零，确保第十六晶体管M16被完全或较为完全地截止。这样可以避免第二上拉节点Q<2>通过第三复位电路33漏电，使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压。
此外，第三复位电路33共用第一复位电路13中的第六十四晶体管M64，有利于简化移位寄存器100的结构，减小移位寄存器100所占据的面积。
在一些实施例中，如图32、图33、图36和图37所示，在第一扫描单元1还包括第二复位电路14的情况下，第二复位电路14还与第二防漏电节点OFF2电连接。
在第一上拉节点Q<1>为高电平、且第二复位电路14未工作的情况下，通过将第二复位电路14与第二防漏电节点OFF2电连接，可以减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，避免第一上拉节点Q<1>通过第二复位电路14漏电，进而可以使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压，避免影响第一输出电路12的导通状态。
基于此，在一些示例中，如图32、图33、图36和图37所示，第二复位电路14还包括：第六十五晶体管M65。
示例性的，如图32、图33、图36和图37所示，六十五晶体管M65的控制极与第二复位信号端BTRST电连接，第六十五晶体管M65的第一极与第二防漏电节点OFF2电连接，第六十五晶体管M65的第二极与第一电压信号端V1电连接。第二复位电路14中的第十五晶体管M15的第二极与第二防漏电节点OFF2电连接，并通过第六十五晶体管M65与第一电压信号端V1电连接。
例如，在第二复位信号的电平为高电平、且第一插黑节点M的电压为高电平的情况下，第十四晶体管M14可以在第一插黑节点M的电压的作用下导通，第十五晶体管M15和第六十五晶体管M65可以在第二复位信号的作用下同时导通。第六十五晶体管M65可以接收并传输第一电压信号至第二防漏电节点OFF2，第十五晶体管M15和第十四晶体管M14可以将该第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在第二复位信号的电平为低电平、且第一插黑节点M的电压为低电平的情况下，第十四晶体管M14、第十五晶体管M15和第六十五晶体管M65可以关断。在第一上拉节点Q<1>的电压保持为高电平的情况下，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第十五晶体管M15的控制极与第二极之间的压差小于零，确保第十五晶体管M15被完全或较为完全地截止。这样可以避免第一上拉节点Q<1>通过第二复位电路14漏电，使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压。
在一些实施例中，如图32、图33、图36和图37所示，在第二扫描单元3还包括第四复位电路34的情况下，第四复位电路34还与第二防漏电节点OFF2电连接。
在第一上拉节点Q<1>为高电平、第二上拉节点Q<2>为高电平且第四复位电路34未工作的情况下，通过将第四复位电路34与第二防漏电节点OFF2电连接，可以减小第二防漏电节点OFF2和第二上拉节点Q<2>之间的压差，避免第二上拉节点Q<2>通过第四复位电路34漏电，进而可以使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压，避免影响第二输出电路32的导通状态。
基于此，在一些示例中，如图32、图33、图36和图37所示，第四复位电路34中的第十八晶体管M18的第二极与第二防漏电节点OFF2电连接，并通过第六十五晶体管M65与第一电压信号端V1电连接。
例如，在第二复位信号的电平为高电平、且第一插黑节点M的电压为高电平的情况下，第十七晶体管M17可以在第一插黑节点M的电压的作用下导通，第十八晶体管M18和第六十五晶体管M65可以在第二复位信号的作用下同时导通。第六十五晶体管M65可以接收并传输第一电压信号至第二防漏电节点OFF2，第十八晶体管M18和第十七晶体管M17可以将该第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在第二复位信号的电平为低电平、且第一插黑节点M的电压为低电平的情况下，第十七晶体管M17、第十八晶体管M18和第六十五晶体管M65可以关断。在第一上拉节点Q<1>的电压保持为高电平的情况下，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第二上拉节点Q<2>之间的压差，并使得第十八晶体管M18的控制极与第二极之间的压差小于零，确保第十八晶体管M18被完全或较为完全地截止。这样可以避免第二上拉节点Q<2>通过第四复位电路34漏电，使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压。
此外，第四复位电路34共用第二复位电路14中的第六十五晶体管M65，有利于简化移位寄存器100的结构，减小移位寄存器100所占据的面积。
在一些实施例中，如图32、图33、图36和图37所示，在第一扫描单元1还包括第五复位电路16的情况下，第五复位电路16还与第二防漏电节点OFF2电连接。
在第一上拉节点Q<1>为高电平、且第五复位电路16未工作的情况下，通过将第五复位电路16与第二防漏电节点OFF2电连接，可以减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，避免第一上拉节点Q<1>通过第五复位电路16漏电，进而可以使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压，避免影响第一输出电路12的导通状态。
基于此，在一些示例中，如图32、图33、图36和图37所示，第五复位电路16还包括：第六十六晶体管M66。
示例性的，如图32、图33、图36和图37所示，第六十六晶体管M66的控制极与第一下拉节点QB_A电连接，第六十六晶体管M66的第一极与第二防漏电节点OFF2电连接，第六十六晶体管M66的第二极与第一电压信号端V1电连接。第五复位电路16中的第二十七晶体管M27的第二极与第二防漏电节点OFF2电连接，并通过第六十六晶体管M66与第一电压信号端V1电连接。
例如，在第一下拉节点QB_A的电压为高电平的情况下，第二十七晶体管M27和第六十六晶体管M66可以在第一下拉节点QB_A的电压的作用下同时导通。第六十六晶体管M66可以接收并传输第一电压信号至第二防漏电节点OFF2，第二十七晶体管M27可以将该第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在第一下拉节点QB_A的电压为低电平的情况下，第一上拉节点Q<1>的电压为高电平。第二十七晶体管M27和第六十六晶体管M66可以关断。第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第二十七晶体管M27的控制极与第二极之间的压差小于零，确保第二十七晶体管M27被完全或较为完全地截止。这样可以避免第一上拉节点Q<1>通过第五复位电路16漏电，使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压。
需要说明的是，如图32、图33、图36和图37所示，在第五复位电路16还与第二下拉节点QB_B电连接的情况下，第五复位电路16还包括：第六十七晶体管M67。
示例性的，如图32、图33、图36和图37所示，第六十七晶体管M67的控制极与第二下拉节点QB_B电连接，第六十七晶体管M67的第一极与第二防漏电节点OFF2电连接，第六十七晶体管M67的第二极与第一电压信号端V1电连接。第五复位电路16中的第三十九晶体管M39的第二极与第二防漏电节点OFF2电连接，并通过第六十七晶体管M67与第一电压信号端V1电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第三十九晶体管M39和第六十七晶体管M67可以在第二下拉节点QB_B的电压的作用下同时导通。第六十七晶体管M67可以接收并传输第一电压信号至第二防漏电节点OFF2，第三十九晶体管M39可以将该第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在第二下拉节点QB_B的电压为低电平的情况下，第一上拉节点Q<1>的电压为高电平。第三十九晶体管M39和第六十七晶体管M67可以关断。第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第三十九晶体管M39的控制极与第二极之间的压差小于零，确保第三十九晶体管M39被完全或较为完全地截止。这样可以避免第一上拉节点Q<1>通过第五复位电路16漏电，使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压。
在一些实施例中，如图32、图33、图36和图37所示，在第二扫描单元3还包括第八复位电路36的情况下，第八复位电路36还与第二防漏电节点OFF2电连接。
在第一上拉节点Q<1>为高电平、第二上拉节点Q<2>为高电平、且第八复位电路36未工作的情况下，通过将第八复位电路36与第二防漏电节点OFF2电连接，可以减小第二 防漏电节点OFF2和第二上拉节点Q<2>之间的压差，避免第二上拉节点Q<2>通过第八复位电路36漏电，进而可以使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压，避免影响第二输出电路32的导通状态。
基于此，在一些示例中，如图32、图33、图36和图37所示，第八复位电路36中的第三十三晶体管M33的第二极与第二防漏电节点OFF2电连接，并通过第六十六晶体管M66与第一电压信号端V1电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第一下拉节点QB_A的电压为高电平。第三十三晶体管M33可以在第二下拉节点QB_B的电压的作用下导通，第六十六晶体管M66可以在第一下拉节点QB_A的电压的作用下导通。第六十六晶体管M66可以接收并传输第一电压信号至第二防漏电节点OFF2，第三十三晶体管M33可以将该第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在第二下拉节点QB_B的电压为低电平的情况下，第一下拉节点QB_A的电压为低电平，第一上拉节点Q<1>的电压为高电平。第三十三晶体管M33和第六十六晶体管M66可以关断。第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第三十三晶体管M33的控制极与第二极之间的压差小于零，确保第三十三晶体管M33被完全或较为完全地截止。这样可以避免第二上拉节点Q<2>通过第八复位电路36漏电，使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压。
需要说明的是，如图36和图37所示，在第八复位电路36还与第一下拉节点QB_A电连接的情况下，第八复位电路36中的第四十三晶体管M43的第二极与第二防漏电节点OFF2电连接，并通过第六十七晶体管M67与第一电压信号端V1电连接。
例如，在第二下拉节点QB_B的电压为高电平的情况下，第一下拉节点QB_A的电压为高电平。第四十三晶体管M43和第六十七晶体管M67可以导通。第六十七晶体管M67可以接收并传输第一电压信号至第二防漏电节点OFF2，第四十三晶体管M43可以将该第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在第二下拉节点QB_B的电压为低电平的情况下，第一下拉节点QB_A的电压为低电平，第一上拉节点Q<1>的电压为高电平。第四十三晶体管M43和第六十七晶体管M67可以关断。第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第四十三晶体管M43的控制极与第二极之间的压差小于零，确保第四十三晶体管M43被完全或较为完全地截止。这样可以避免第二上拉节点Q<2>通过第八复位电路36漏电，使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压。
此外，第八复位电路36共用第五复位电路16中的第六十六晶体管M66和第六十七晶体管M67，有利于简化移位寄存器100的结构，减小移位寄存器100所占据的面积。
在一些实施例中，如图36和图37所示，在第一扫描单元1还包括第十一复位电路19的情况下，第十一复位电路19还与第二防漏电节点OFF2电连接。
在第一上拉节点Q<1>为高电平、且第十一复位电路19未工作的情况下，通过将第十一复位电路19与第二防漏电节点OFF2电连接，可以减小第二防漏电节点OFF2和第一上 拉节点Q<1>之间的压差，避免第一上拉节点Q<1>通过第十一复位电路19漏电，进而可以使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压，避免影响第一输出电路12的导通状态。
基于此，在一些示例中，如图36和图37所示，第十一复位电路19还包括：第六十八晶体管M68。
示例性的，如图36和图37所示，第六十八晶体管M68的控制极与全局复位信号端TRST电连接，第六十八晶体管M68的第一极与第二防漏电节点OFF2电连接，第六十八晶体管M68的第二极与第一电压信号端V1电连接。第十一复位电路19中的第五十一晶体管M51的第二极与第二防漏电节点OFF2电连接，并通过第六十八晶体管M68与第一电压信号端V1电连接。
例如，在全局复位信号的电平为高电平的情况下，第五十一晶体管M51和第六十八晶体管M68可以在全局复位信号的作用下同时导通。第六十八晶体管M68可以接收并传输第一电压信号至第二防漏电节点OFF2，第五十一晶体管M51可以将该第一电压信号传输至第一上拉节点Q<1>，对第一上拉节点Q<1>进行下拉复位。
在全局复位信号的电平为低电平的情况下，第五十一晶体管M51和第六十八晶体管M68可以在全局复位信号的作用下同时关断。在第一上拉节点Q<1>的电压保持为高电平的情况下，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第五十一晶体管M51的控制极与第二极之间的压差小于零，确保第五十一晶体管M51被完全或较为完全地截止。这样可以避免第一上拉节点Q<1>通过第十一复位电路19漏电，使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压。
在一些实施例中，如图36和图37所示，在第二扫描单元3还包括第十四复位电路39的情况下，第十四复位电路39还与第二防漏电节点OFF2电连接。
在第一上拉节点Q<1>为高电平、第二上拉节点Q<2>为高电平且第十四复位电路39未工作的情况下，通过将第十四复位电路39与第二防漏电节点OFF2电连接，可以减小第二防漏电节点OFF2和第二上拉节点Q<2>之间的压差，避免第二上拉节点Q<2>通过第十四复位电路39漏电，进而可以使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压，避免影响第二输出电路32的导通状态。
基于此，在一些示例中，如图36和图37所示，第十四复位电路39中的第五十五晶体管M55的第二极与第二防漏电节点OFF2电连接，并通过第六十八晶体管M68与第一电压信号端V1电连接。
例如，在全局复位信号的电平为高电平的情况下，第五十五晶体管M55和第六十八晶体管M68可以在全局复位信号的作用下同时导通。第六十八晶体管M68可以接收并传输第一电压信号至第二防漏电节点OFF2，第五十五晶体管M55可以将该第一电压信号传输至第二上拉节点Q<2>，对第二上拉节点Q<2>进行下拉复位。
在全局复位信号的电平为低电平的情况下，第五十五晶体管M55和第六十八晶体管M68可以在全局复位信号的作用下同时关断。在第一上拉节点Q<1>的电压及第二上拉节点Q<2>的电压保持为高电平的情况下，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第 二防漏电节点OFF2和第二上拉节点Q<2>之间的压差，并使得第五十五晶体管M55的控制极与第二极之间的压差小于零，确保第五十五晶体管M55被完全或较为完全地截止。这样可以避免第二上拉节点Q<2>通过第十四复位电路39漏电，使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压。
此外，第十四复位电路39共用第十一复位电路19中的第六十八晶体管M68，有利于简化移位寄存器100的结构，减小移位寄存器100所占据的面积。
在一些实施例中，如图36和图37所示，在移位寄存器100还包括消隐电路4的情况下，消隐电路4还与第二防漏电节点OFF2电连接。
基于此，在一些示例中，如图36和图37所示，在消隐电路4包括第一消隐传输子电路43的情况下，第一消隐传输子电路43还包括：第六十九晶体管M69。
示例性的，如图36和图37所示，第六十九晶体管M69的控制极与第七时钟信号端CLKA电连接，第六十九晶体管M69的第一极与第二消隐节点N电连接，第六十九晶体管M69的第二极与第二防漏电节点OFF2电连接。第一消隐传输子电路43中的第四十九晶体管M49的第一极与第二防漏电节点OFF2电连接，并通过第六十九晶体管M69与第二消隐节点N电连接。
例如，在第七时钟信号的电平为高电平的情况下，第四十九晶体管M49和第六十九晶体管M69可以在第七时钟信号的作用下同时导通。第六十九晶体管M69可以接收来自第二消隐节点N的第七时钟信号，并将该第七时钟信号至第二防漏电节点OFF2，第四十九晶体管M49可以接收并传输第七时钟信号至第一上拉节点Q<1>，对第一上拉节点Q<1>进行充电。
在第七时钟信号的电平为低电平的情况下，第四十九晶体管M49和第六十九晶体管M69可以在第七时钟信号的作用下同时关断。在第一上拉节点Q<1>的电压保持为高电平的情况下，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节点Q<1>之间的压差，并使得第四十九晶体管M49的控制极与第一极之间的压差小于零，确保第四十九晶体管M49被完全或较为完全地截止。这样可以避免第一上拉节点Q<1>通过第一消隐传输子电路43漏电，使得第一上拉节点Q<1>能够保持在一个较高的、较为稳定的电压。
在一些示例中，如图36和图37所示，第二消隐传输子电路44中的第五十晶体管M50的第一极与第二防漏电节点OFF2电连接，并通过第六十九晶体管M69与第二消隐节点N电连接。
例如，在第七时钟信号的电平为高电平的情况下，第五十晶体管M50和第六十九晶体管M69可以在第七时钟信号的作用下同时导通。第六十九晶体管M69可以接收来自第二消隐节点N的第七时钟信号，并将该第七时钟信号至第二防漏电节点OFF2，第五十晶体管M50可以接收并传输第七时钟信号至第二上拉节点Q<2>，对第二上拉节点Q<2>进行充电。
在第七时钟信号的电平为低电平的情况下，第五十晶体管M50和第六十九晶体管M69可以在第七时钟信号的作用下同时关断。在第一上拉节点Q<1>的电压保持为高电平的情况下，第二防漏电电路7中的第六十一晶体管M61可以将第五电压信号传输至第二防漏电节点OFF2，对第二防漏电节点OFF2进行充电，减小第二防漏电节点OFF2和第一上拉节 点Q<1>之间的压差，并使得第五十晶体管M50的控制极与第一极之间的压差小于零，确保第五十晶体管M50被完全或较为完全地截止。这样可以避免第二上拉节点Q<2>通过第二消隐传输子电路44漏电，使得第二上拉节点Q<2>能够保持在一个较高的、较为稳定的电压。
本公开的一些实施例提供的扫描驱动电路1000中，如图38～图42所示，该扫描驱动电路1000所包括的多级级联的移位寄存器100，包括多个第一移位寄存器组C和多个第二移位寄存器组D。第一移位寄存器组C和第二移位寄存器组D交替排列。
在一些示例中，上述各级移位寄存器100可以包括第一扫描单元1。
在另一些示例中，如图38～图42所示，上述各级移位寄存器100可以包括第一扫描单元1和第二扫描单元3。
下面以各级移位寄存器100包括第一扫描单元1和第二扫描单元3为例，对扫描驱动电路1000的结构进行示意性说明。
在一些示例中，第一移位寄存器组C可以包括2N级移位寄存器100，第二移位寄存器组包括2N级移位寄存器100；其中，N为正整数。也即，各移位寄存器组所包括的移位寄存器100的数量相同。
示例性的，在N＝2的情况下，第一移位寄存器组C可以包括4级移位寄存器100，第二移位寄存器组包括4级移位寄存器100。其中，每级移位寄存器100包括第一扫描单元1和第二扫描单元3。相应的，每个移位寄存器组可以有八个扫描信号端，例如可以与八行子像素P分别电连接。
示例性的，在N＝4的情况下，第一移位寄存器组C可以包括8级移位寄存器100，第二移位寄存器组包括8级移位寄存器100。其中，每级移位寄存器100包括第一扫描单元1和第二扫描单元3。相应的，每个移位寄存器组可以有十六个扫描信号端，例如可以与十六行子像素P分别电连接。
在一些示例中，如图43和图44所示，第一移位寄存器组C中，至少两级移位寄存器100共用插黑电路2。第二移位寄存器组D中，至少两级移位寄存器100共用插黑电路2。
示例性的，以N＝2为例。
例如，各移位寄存器组中，每两级移位寄存器100可以共用插黑电路2。此时，每个移位寄存器组中可以仅具有两个插黑电路2。
又如，各移位寄存器组中，4级移位寄存器100可以共用插黑电路2。此时，每个移位寄存器组中可以仅具有以个插黑电路2。
采用上述设置方式，可以利用一个插黑电路2向相应的至少两级移位寄存器100的第一上拉节点Q<1>和第二上拉节点Q<2>传输插黑输入信号，实现对至少两级移位寄存器100的控制，这样有利于提高信号传输效率，简化扫描驱动电路1000的结构。
需要说明的是，基于移位寄存器100具有多个信号端，扫描驱动电路1000可以包括多条信号线。
在一些示例中，扫描驱动电路1000还包括：第一控制信号线组。
示例性的，如图38～图41、图45、图48、图50和图52所示，第一控制信号线组可以包括第一子控制信号线BCK1和第二子控制信号线BCK2。其中，第一子控制信号线BCK1与第一移位寄存器组C中各移位寄存器100的第一控制信号端BCS1电连接，第二子控制信号线BCK2与第二移位寄存器组D中各移位寄存器100的第一控制信号端BCS1 电连接。
例如，第一控制信号线组仅包括一条第一子控制信号线BCK1和一条第二子控制信号线BCK2。
这样在扫描驱动电路1000进行工作的过程中，可以通过第一子控制信号线BCK1向向各第一移位寄存器组C中的第一控制信号端BCS1传输第一控制信号，控制各第一移位寄存器组C中的插黑电路2中的插黑控制子电路21导通，并对所接收的插黑级联信号进行存储；可以通过第二子控制信号线BCK2向各第二移位寄存器组D中的第一控制信号端BCS1传输第一控制信号，控制各第二移位寄存器组D中的插黑电路2中的插黑控制子电路21导通，并对所接收的插黑级联信号进行存储。
此处，在插黑级联信号的电平为高电平的情况下，则可以使得相应的插黑输入子电路22包括导通状态，将插黑输入信号传输至第二插黑节点K。在插黑级联信号的电平为低电平的情况下，则可以使得相应的插黑输入子电路22包括关断状态。
在一些示例中，扫描驱动电路1000还包括：第二控制信号线组。
示例性的，如图38～图41、图45、图48、图50和图52所示，第二控制信号线组300可以包括第三子控制信号线BCK3和第四子控制信号线BCK4。其中，第三子控制信号线BCK3与第一移位寄存器组C中各移位寄存器100的第二控制信号端BCS2电连接，第四子控制信号线BCK4与第二移位寄存器组D中各移位寄存器100的第二控制信号端BCS2电连接。
例如，第二控制信号线组仅包括一条第三子控制信号线BCK3和三条第二子控制信号线BCK4。
此时，各第一移位寄存器组C中，各移位寄存器100的第二控制信号端BCS2，可以同时接收第二控制信号；各第二移位寄存器组D中各移位寄存器100的第二控制信号端BCS2，可以同时接收第二控制信号。
此处，可选的，如图45、图48、图50和图52所示，在第二控制信号端BCS2和插黑输入信号端BI为相同信号端的情况下，第三子控制信号线BCK3还与第一移位寄存器组C中各移位寄存器100的插黑输入信号端BI电连接，第四子控制信号线BCK4还与第二移位寄存器组D中各移位寄存器100的插黑输入信号端BI电连接。
此时，各第一移位寄存器组C中，各移位寄存器100的第二控制信号端BCS2和插黑输入信号端BI可以接收来自同一条第三子控制信号线BCK3的信号，各第二移位寄存器组D中，各移位寄存器100的第二控制信号端BCS2和插黑输入信号端BI可以接收来自同一条第四子控制信号线BCK4的信号。这样有利于减少信号线的数量，简化扫描驱动电路1000的结构。
在扫描驱动电路1000进行工作的过程中，可以通过第三子控制信号线BCK3向各第一移位寄存器组C中的第二控制信号端BCS2及插黑输入信号端BI传输相同的信号，控制各第一移位寄存器组C中的插黑电路2的第一插黑传输子电路23和第二插黑传输子电路24的导通状态。在第三子控制信号线BCK3所传输的第三子控制信号的电平为高电平的情况下，上述第一插黑传输子电路23可以导通，并将高电平的第三子控制信号传输至第一上拉节点Q<1>，抬高第一上拉节点Q<1>的电压，上述第二插黑传输子电路24可以导通，并将高电平的第三子控制信号传输至第二上拉节点Q<2>，抬高第二上拉节点Q<2>的电压。之后便可以通过第一时钟信号端CLKE1所传输的第一时钟信号及第二时钟信号 端CLKE2所传输的第二时钟信号，控制与第一移位寄存器组C相对应的多行子像素P同时显示黑画面。
同理，对于第二移位寄存器组D的工作过程参照上述说明，此处不再赘述。
可选的，在第二控制信号端BCS2和插黑输入信号端BI为不同信号端的情况下，各移位寄存器100的插黑输入信号端BI例如可以与传输直流高电平信号的线电连接。
在此情况下，对于第一移位寄存器组C、第二移位寄存器组D的工作过程参照上述说明，此处不再赘述。
需要说明的是，在第一移位寄存器组C相对应的多行子像素P显示黑画面的过程中，第二移位寄存器组D相对应的多行子像素P进行图像显示。
另外，在一些示例中，如图42所示，各移位寄存器100的插黑输入信号端BI可以均与某一移位寄存器100的第一移位信号端CR<N>电连接，能够使得插黑电路2实现插黑功能、使得显示装置2000插入黑画面即可。
示例性的，上述第一移位信号端CR<N>可以为第1099行的移位信号端，也即，第545级移位寄存器100中的第一移位信号端CR<N>。
这样可以避免设置第二控制信号线组，有利于减少扫描驱动电路1000所包括的信号线的数量，简化扫描驱动电路1000的结构。
在一些示例中，扫描驱动电路1000还包括：第一时钟信号线组。
示例性的，如图38～图42、图45、图48、图50和图52所示，第一时钟信号线组可以包括8N个第一子时钟信号线CKE。其中，该8N个第一子时钟信号线CKE分别与第一移位寄存器组C中各移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2、第二移位寄存器组D中各移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2电连接。
也即，第一时钟信号线组所包括的第一子时钟信号线CKE的数量，可以与一个第一移位寄存器组C和一个第二移位寄存器组D所包括的扫描信号端的数量之和相同。一条第一子时钟信号线CKE可以与一个扫描信号端相对应。
例如，各第一移位寄存器组C所电连接的第一子时钟信号线CKE相同，各第二移位寄存器组D所电连接的第一子时钟信号线CKE相同。
示例性的，如图38～图42、图45、图48、图50和图52所示，以N＝2为例。第一时钟信号线组可以包括16条第一子时钟信号线CKE。
其中，该16条第一子时钟信号线CKE可以包括：分别与各第一移位寄存器组C中第一级移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2电连接的第一子时钟信号线之九CKE_9和第一子时钟信号线之十CKE_10；分别与各第一移位寄存器组C中第二级移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2电连接的第一子时钟信号线之十一CKE_11和第一子时钟信号线之十二CKE_12；分别与各第一移位寄存器组C中第三级移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2电连接的第一子时钟信号线之十三CKE_13和第一子时钟信号线之十四CKE_14；分别与各第一移位寄存器组C中第四级移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2电连接的第一子时钟信号线之十五CKE_15和第一子时钟信号线之十六CKE_16；分别与各第二移位寄存器组D中第一级移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2电连接的第一子时钟信号线之一CKE_1和第一子时钟信号线之 二CKE_2；分别与各第二移位寄存器组D中第二级移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2电连接的第一子时钟信号线之三CKE_3和第一子时钟信号线之四CKE_4；分别与各第二移位寄存器组D中第三级移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2电连接的第一子时钟信号线之五CKE_5和第一子时钟信号线之六CKE_6；分别与各第二移位寄存器组D中第四级移位寄存器100的第一时钟信号端CLKE1及第二时钟信号端CLKE2电连接的第一子时钟信号线之七CKE_7和第一子时钟信号线之八CKE_8。
当然，上述第一子时钟信号线CKE的连接顺序可以调换，并不局限于上述连接方式。
在一些示例中，在移位寄存器100的第一输出电路21还与第三时钟信号端CLKF1及第一感测信号端Oput2<N>电连接、第二输出电路32还与第四时钟信号端CLKF2及第二感测信号端Oput2<N+1>电连接的情况下，扫描驱动电路1000还包括：第二时钟信号线组。
上述第二时钟信号线组的设置方式及与移位寄存器100的连接方式包括多种，可以根据实际需要选择设置。
可选的，如图39、图48和图52所示，第二时钟信号线组500包括4N个第二子时钟信号线CKF。其中，该4N个第二子时钟信号线CKF分别与第一移位寄存器组C中各移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接，并分别与第二移位寄存器组D中各移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接。
也即，第二时钟信号线组500所包括的第二子时钟信号线CKF的数量，可以与一个第一移位寄存器组C或一个第二移位寄存器组D所包括的感测信号端的数量相同。一条第二子时钟信号线CKF可以与一个感测信号端相对应。各移位寄存器组所电连接的第二子时钟信号线CKF相同。
示例性的，如图39、图48和图52所示，以N＝2为例。第二时钟信号线组可以包括8条第二子时钟信号线CKF。
其中，该8条第二子时钟信号线CKF可以包括：与各第一移位寄存器组C中第一级移位寄存器100的第三时钟信号端CLKF1及各第二移位寄存器组C中第一级移位寄存器100的第三时钟信号端CLKF1电连接的第二子时钟信号线之一CKF_1；与各第一移位寄存器组C中第一级移位寄存器100的第四时钟信号端CLKF2及各第二移位寄存器组C中第一级移位寄存器100的第四时钟信号端CLKF2电连接的第二子时钟信号线之二CKF_2；与各第一移位寄存器组C中第二级移位寄存器100的第三时钟信号端CLKF1及各第二移位寄存器组C中第二级移位寄存器100的第三时钟信号端CLKF1电连接的第二子时钟信号线之三CKF_3；与各第一移位寄存器组C中第二级移位寄存器100的第四时钟信号端CLKF2及各第二移位寄存器组C中第二级移位寄存器100的第四时钟信号端CLKF2电连接的第二子时钟信号线之四CKF_4；与各第一移位寄存器组C中第三级移位寄存器100的第三时钟信号端CLKF1及各第二移位寄存器组C中第三级移位寄存器100的第三时钟信号端CLKF1电连接的第二子时钟信号线之五CKF_5；与各第一移位寄存器组C中第三级移位寄存器100的第四时钟信号端CLKF2及各第二移位寄存器组C中第三级移位寄存器100的第四时钟信号端CLKF2电连接的第二子时钟信号线之六CKF_6；与各第一移位寄存器组C中第四级移位寄存器100的第三时钟信号端CLKF1及各第二移位寄存器组C中第四级移位寄存器100的第三时钟信号端CLKF1电连接的第二子时钟信号线之七 CKF_7；与各第一移位寄存器组C中第四级移位寄存器100的第四时钟信号端CLKF2及各第二移位寄存器组C中第四级移位寄存器100的第四时钟信号端CLKF2电连接的第二子时钟信号线之八CKF_8。
可选的，如图38、图41和图45所示，第二时钟信号线组500包括8N个第二子时钟信号线CKF。其中，该8N个第二子时钟信号线CKF分别与第一移位寄存器组C中各移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2、第二移位寄存器组D中各移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接。
也即，第二时钟信号线组500所包括的第二子时钟信号线CKF的数量，可以与一个第一移位寄存器组C和一个第二移位寄存器组D所包括的感测信号端的数量之和相同。一条第二子时钟信号线CKF可以与一个感测信号端相对应。
例如，各第一移位寄存器组C所电连接的第二子时钟信号线CKF相同，各第二移位寄存器组D所电连接的第二子时钟信号线CKF相同。
示例性的，如图38、图41和图45所示，以N＝2为例。第二时钟信号线组500可以包括16条第二子时钟信号线CKF。
其中，该16条第二子时钟信号线CKF可以包括：分别与各第一移位寄存器组C中第一级移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接的第二子时钟信号线之九CKF_9和第二子时钟信号线之十CKF_10；分别与各第一移位寄存器组C中第二级移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接的第二子时钟信号线之十一CKF_11和第二子时钟信号线之十二CKF_12；分别与各第一移位寄存器组C中第三级移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接的第二子时钟信号线之十三CKF_13和第二子时钟信号线之十四CKF_14；分别与各第一移位寄存器组C中第四级移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接的第二子时钟信号线之十五CKF_15和第二子时钟信号线之十六CKF_16；分别与各第二移位寄存器组D中第一级移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接的第二子时钟信号线之一CKF_1和第二子时钟信号线之二CKF_2；分别与各第二移位寄存器组D中第二级移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接的第二子时钟信号线之三CKF_3和第二子时钟信号线之四CKF_4；分别与各第二移位寄存器组D中第三级移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接的第二子时钟信号线之五CKF_5和第二子时钟信号线之六CKF_6；分别与各第二移位寄存器组D中第四级移位寄存器100的第三时钟信号端CLKF1及第四时钟信号端CLKF2电连接的第二子时钟信号线之七CKF_7和第二子时钟信号线之八CKF_8。
当然，上述第二子时钟信号线CKF的连接顺序可以调换，并不局限于上述连接方式。
此外，由于扫描信号和感测信号的时序可以相同，因此，扫描驱动电路1000中也可以不设置第二时钟信号线组500，而将第三时钟信号端CLKF1与其所属第一扫描单元1的第一时钟信号端CLKE1连接相同的第一子时钟信号线CKE，将第四时钟信号端CLKF2与其所属第二扫描单元3的第二时钟信号端CLKE2连接相同的第一子时钟信号线CKE。
需要说明的是，扫描驱动电路1000中，多级移位寄存器100的级联方式包括多种，可以根据实际需要选择设置。
在一些示例中，移位寄存器100的第一输出电路12还与第五时钟信号端CLKD1及第 一移位信号端CR<N>电连接，第二输出电路32还与第六时钟信号端CLKD2及第二移位信号端CR2<N+1>电连接。
在此情况下，多级移位寄存器100中，除前至少一级移位寄存器100外，其余级移位寄存器100的显示输入信号端Iput，与在前的移位寄存器100中的第一移位信号端CR<N>电连接。除前至少两级移位寄存器100外，其余级移位寄存器100的插黑级联信号端BCR，与在前的移位寄存器100中的第二移位信号端CR2<N+1>电连接。
也即，奇数行的移位信号端所传输的移位信号作为显示级联信号，偶数行的移位信号端所传输的移位信号作为插黑级联信号。
示例性的，如图38和图39所示，以N＝2为例。除前两级移位寄存器100外，其余级移位寄存器100的显示输入信号端Iput，与前两级移位寄存器100中的第一移位信号端CR<N>电连接。除前四级移位寄存器100外，其余级移位寄存器100的插黑级联信号端BCR，与前四级移位寄存器100中的第二移位信号端CR2<N+1>电连接。
在另一些示例中，如图40所示，移位寄存器100的第一输出电路12还与第五时钟信号端CLKD1及第一移位信号端CR<N>电连接，第二输出电路32还与第六时钟信号端CLKD2及第二移位信号端CR2<N+1>电连接。
在此情况下，多级移位寄存器100中，除前至少一级移位寄存器100外，其余级移位寄存器的显示输入信号端Iput，与在前的移位寄存器100中的第二移位信号端CR2<N+1>电连接。除前至少两级移位寄存器100外，其余级移位寄存器100的插黑级联信号端BCR，与在前的移位寄存器100中的第一移位信号端CR<N>电连接。
也即，奇数行的移位信号端所传输的移位信号作为插黑级联信号，偶数行的移位信号端所传输的移位信号作为显示级联信号。
示例性的，以N＝2为例。除前两级移位寄存器100外，其余级移位寄存器100的显示输入信号端Iput，与前两级移位寄存器100中的第二移位信号端CR2<N+1>电连接。除前四级移位寄存器100外，其余级移位寄存器100的插黑级联信号端BCR，与前四级移位寄存器100中的第一移位信号端CR<N>电连接。
在又一些示例中，如图41所示，移位寄存器100的第一输出电路12还与第五时钟信号端CLKD1及第一移位信号端CR<N>电连接，移位寄存器100还包括第二防漏电电路7。
在此情况下，多级移位寄存器100中，除前至少一级移位寄存器100外，其余级移位寄存器100的显示输入信号端Iput，与在前的移位寄存器100中的第一移位信号端CR<N>电连接。除前至少两级移位寄存器100外，其余级移位寄存器100的插黑级联信号端BCR，与在前的移位寄存器100的第二防漏电节点OFF2电连接。
也即，奇数行的移位信号端所传输的移位信号作为显示级联信号，偶数行的第二防漏电节点OFF2所传输的第五电压信号作为显示级联信号。此处，由于移位寄存器100中第一扫描单元1和第二扫描单元3共用第二防漏电电路7，因此，偶数行的第二防漏电节点OFF2也可以称为奇数行的第二防漏电节点OFF2。
示例性的，如图41所示，以N＝2为例。除前两级移位寄存器100外，其余级移位寄存器100的显示输入信号端Iput，与前两级移位寄存器100中的第一移位信号端CR<N>电连接。除前四级移位寄存器100外，其余级移位寄存器100的插黑级联信号端BCR，与前四级移位寄存器100中的第二防漏电节点OFF2电连接。
在本示例中，第二扫描单元3中的第二输出电路32可以不设置第十二晶体管M12， 进而可以不与第六时钟信号端CLKD2电连接，进而第二扫描单元3中的第九复位电路37可以不设置相应的晶体管。
这样有利于简化移位寄存器100和扫描驱动电路1000的结构，进而有利于减小移位寄存器100和扫描驱动电路1000的占据面积，提高移位寄存器100和扫描驱动电路1000的良率。
基于上述示例，扫描驱动电路1000还可以包括：第三时钟信号线组。
可选的，在移位寄存器100的第一输出电路12还与第五时钟信号端CLKD1及第一移位信号端CR<N>电连接，且第二输出电路32还与第六时钟信号端CLKD2及第二移位信号端CR2<N+1>电连接的情况下，第三时钟信号线组600可以包括8N个第三子时钟信号线CKD。其中，该8N个第三子时钟信号线CKD分别与第一移位寄存器组C中各移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2、第二移位寄存器组D中各移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接。
例如，各第一移位寄存器组C所电连接的第三子时钟信号线CKD相同，各第二移位寄存器组D所电连接的第三子时钟信号线CKD相同。
示例性的，如图38和图45所示，以N＝2为例。第三时钟信号线组600可以包括16条第三子时钟信号线CKD。
其中，该16条第三子时钟信号线CKD可以包括：分别与各第一移位寄存器组C中第一级移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接的第三子时钟信号线之九CKD_9和第三子时钟信号线之十CKD_10；分别与各第一移位寄存器组C中第二级移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接的第三子时钟信号线之十一CKD_11和第三子时钟信号线之十二CKD_12；分别与各第一移位寄存器组C中第三级移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接的第三子时钟信号线之十三CKD_13和第三子时钟信号线之十四CKD_14；分别与各第一移位寄存器组C中第四级移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接的第三子时钟信号线之十五CKD_15和第三子时钟信号线之十六CKD_16；分别与各第二移位寄存器组D中第一级移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接的第三子时钟信号线之一CKD_1和第三子时钟信号线之二CKD_2；分别与各第二移位寄存器组D中第二级移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接的第三子时钟信号线之三CKD_3和第三子时钟信号线之四CKD_4；分别与各第二移位寄存器组D中第三级移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接的第三子时钟信号线之五CKD_5和第三子时钟信号线之六CKD_6；分别与各第二移位寄存器组D中第四级移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接的第三子时钟信号线之七CKD_7和第三子时钟信号线之八CKD_8。
当然，上述第三子时钟信号线CKD的连接顺序可以调换，并不局限于上述连接方式。
可选的，如图39和图48所示，在移位寄存器100的第一输出电路12还与第五时钟信号端CLKD1及第一移位信号端CR<N>电连接，且第二输出电路32还与第六时钟信号端CLKD2及第二移位信号端CR2<N+1>电连接的情况下，第三时钟信号线组600可以包括4N个第三子时钟信号线CKD。其中，该4N个第三子时钟信号线CKD分别与第一移位寄存器组C中各移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电 连接，并分别与第二移位寄存器组D中各移位寄存器100的第五时钟信号端CLKD1及第六时钟信号端CLKD2电连接。
也即，第三时钟信号线组600所包括的第三子时钟信号线CKD的数量，可以与一个第一移位寄存器组C或一个第二移位寄存器组D所包括的移位信号端的数量相同。一条第三子时钟信号线CKD可以与一个移位信号端相对应。各移位寄存器组所电连接的第三子时钟信号线CKD相同。
示例性的，如图39和图48所示，以N＝2为例。第三时钟信号线组600可以包括8条第三子时钟信号线CKD。
其中，该8条第三子时钟信号线CKD可以包括：与各第一移位寄存器组C中第一级移位寄存器100的第五时钟信号端CLKD1及各第二移位寄存器组C中第一级移位寄存器100的第五时钟信号端CLKD1电连接的第三子时钟信号线之一CKD_1；与各第一移位寄存器组C中第一级移位寄存器100的第六时钟信号端CLKD2及各第二移位寄存器组C中第一级移位寄存器100的第六时钟信号端CLKD2电连接的第三子时钟信号线之二CKD_2；与各第一移位寄存器组C中第二级移位寄存器100的第五时钟信号端CLKD1及各第二移位寄存器组C中第二级移位寄存器100的第五时钟信号端CLKD1电连接的第三子时钟信号线之三CKD_3；与各第一移位寄存器组C中第二级移位寄存器100的第六时钟信号端CLKD2及各第二移位寄存器组C中第二级移位寄存器100的第六时钟信号端CLKD2电连接的第三子时钟信号线之四CKD_4；与各第一移位寄存器组C中第三级移位寄存器100的第五时钟信号端CLKD1及各第二移位寄存器组C中第三级移位寄存器100的第五时钟信号端CLKD1电连接的第三子时钟信号线之五CKD_5；与各第一移位寄存器组C中第三级移位寄存器100的第六时钟信号端CLKD2及各第二移位寄存器组C中第三级移位寄存器100的第六时钟信号端CLKD2电连接的第三子时钟信号线之六CKD_6；与各第一移位寄存器组C中第四级移位寄存器100的第五时钟信号端CLKD1及各第二移位寄存器组C中第四级移位寄存器100的第五时钟信号端CLKD1电连接的第三子时钟信号线之七CKD_7；与各第一移位寄存器组C中第四级移位寄存器100的第六时钟信号端CLKD2及各第二移位寄存器组C中第四级移位寄存器100的第六时钟信号端CLKD2电连接的第三子时钟信号线之八CKD_8。
这也就意味着，各第一移位寄存器组C中第一级移位寄存器100的第五时钟信号端CLKD1及各第二移位寄存器组C中第一级移位寄存器100的第五时钟信号端CLKD1所传输的第五时钟信号的时序可以是相同的。例如，可以将图46中所示的CKD_1和CKD_9的时序合并，作为本示例中CKD_1的时序。
各第一移位寄存器组C中第一级移位寄存器100的第六时钟信号端CLKD2及各第二移位寄存器组C中第一级移位寄存器100的第六时钟信号端CLKD2所传输的第六时钟信号的时序可以是相同的。例如，可以将图46中所示的CKD_2和CKD_10的时序合并，作为本示例中CKD_2的时序。
各第一移位寄存器组C中第二级移位寄存器100的第五时钟信号端CLKD1及各第二移位寄存器组C中第二级移位寄存器100的第五时钟信号端CLKD1所传输的第五时钟信号的时序可以是相同的。例如，可以将图46中所示的CKD_3和CKD_11的时序合并，作为本示例中CKD_3的时序。
各第一移位寄存器组C中第二级移位寄存器100的第六时钟信号端CLKD2及各第二 移位寄存器组C中第二级移位寄存器100的第六时钟信号端CLKD2所传输的第六时钟信号的时序可以是相同的。例如，可以将图46中所示的CKD_4和CKD_12的时序合并，作为本示例中CKD_4的时序。
各第一移位寄存器组C中第三级移位寄存器100的第五时钟信号端CLKD1及各第二移位寄存器组C中第三级移位寄存器100的第五时钟信号端CLKD1所传输的第五时钟信号的时序可以是相同的。例如，可以将图46中所示的CKD_5和CKD_13的时序合并，作为本示例中CKD_5的时序。
各第一移位寄存器组C中第三级移位寄存器100的第六时钟信号端CLKD2及各第二移位寄存器组C中第三级移位寄存器100的第六时钟信号端CLKD2所传输的第六时钟信号的时序可以是相同的。例如，可以将图46中所示的CKD_6和CKD_14的时序合并，作为本示例中CKD_6的时序。
各第一移位寄存器组C中第四级移位寄存器100的第五时钟信号端CLKD1及各第二移位寄存器组C中第四级移位寄存器100的第五时钟信号端CLKD1所传输的第五时钟信号的时序可以是相同的。例如，可以将图46中所示的CKD_7和CKD_15的时序合并，作为本示例中CKD_7的时序。
各第一移位寄存器组C中第四级移位寄存器100的第六时钟信号端CLKD2及各第二移位寄存器组C中第四级移位寄存器100的第六时钟信号端CLKD2所传输的第六时钟信号的时序可以是相同的。例如，可以将图46中所示的CKD_8和CKD_16的时序合并，作为本示例中CKD_8的时序。
本示例中扫描驱动电路1000的工作过程，相比于采用2N条第三子时钟信号线CKD的示例中扫描驱动电路1000的工作过程，基本无变化。这样有利于减少扫描驱动电路1000所包括的信号线的数量，简化扫描驱动电路1000的结构。
此外，在能够使得显示装置2000中的子像素P显示黑画面、并增大MPRT的情况下，还可以采用其他得方式对第三子时钟信号线CKD进行合并，本公开对此并不做限定。
例如，如图52所示，在采用奇数行的移位信号端所传输的移位信号作为插黑级联信号，偶数行的移位信号端所传输的移位信号作为显示级联信号的情况下，本示例中的CKD_1、CKD_3、CKD_5及CKD_7的时序可以相同，进而可以将CKD_1、CKD_3、CKD_5及CKD_7合并为CKD_1，使得扫描驱动电路1000仅包括5条第三子时钟信号线CKD。这样有利于进一步减少扫描驱动电路1000所包括的信号线的数量，进一步简化扫描驱动电路1000的结构。
可选的，如图41所示，在移位寄存器100的第一输出电路12还与第五时钟信号端CLKD1及第一移位信号端CR<N>电连接的情况下，第三时钟信号线组600可以包括4N个第三子时钟信号线CKD。其中，该4N个第三子时钟信号线CKD中的2N个第三子时钟信号线CKD分别与第一移位寄存器组C中各移位寄存器100的第五时钟信号端CLKD1电连接，另外2N个第三子时钟信号线CKD分别与第二移位寄存器组D中各移位寄存器100的第五时钟信号端CLKD1电连接。
由于第二输出电路32未与第六时钟信号端CLKD2电连接，因此可以避免设置相应的信号线，进而有利于减少扫描驱动电路1000所包括的信号线的数量，简化扫描驱动电路1000的结构。
此外，需要说明的是，如图45、48、50和图52所示，扫描驱动电路1000还可以包 括：与各移位寄存器100的第二复位信号端BTRST电连接的第四子时钟信号线CLK电连接，以及，与前至少两级移位寄存器100的插黑级联信号端BCR电连接的起始信号线BSTV。
当然，扫描驱动电路1000还可以包括与其他信号端(例如全局复位信号端TRST或各电压信号端等)电连接的信号线，此处不再赘述。
需要说明的是，在图45、48、50和图52中，C<1-8>、D<9-16>、C<17-24>、D<25-32>……C<1081-1088>、D<1089-1096>分别表示各移位寄存器组(也即第一移位寄存器组C或第二移位寄存器组D)和中的四级移位寄存器100，其中，每级移位寄存器100包括第一扫描单元1和第二扫描单元3。
下面结合图45和图46，对图38所示的扫描驱动电路1000的驱动方法进行示意性说明。其中，一个扫描信号端与一行子像素P电连接。
在第一阶段T1中，起始信号线BSTV所传输的起始信号的电平及第一子控制信号线BCK1所传输的第一控制信号的电平，均为高电平。
第一个第一移位寄存器组C中，各移位寄存器100的插黑控制子电路21导通，其中，插黑控制子电路21中的第五晶体管M5，可以接收并传输起始信号至第一插黑节点M，对第一插黑节点M进行充电，使得第一插黑节点M<1/3/5/7>的电压为高电平。
在第二阶段T2～第五阶段T5中，第1081～1084个输出电路导通，并依次传输高电平的时钟信号至第1081～1084行子像素P，使得第1081～1084行子像素P依次进行显示操作。在，第1084行子像素P写入数据后，第136个移位寄存器组(也即第一移位寄存器组C)中的插黑电路2导通，并对第一插黑节点M<1081/1083/1085/1087>进行充电，抬高第136个移位寄存器组C中第一插黑节点M<1081/1083/1085/1087>的电压。
在第六阶段T6中，第三子控制信号线BCK2所传输的第二控制信号的电平，变为高电平。第一个第一移位寄存器组C中，各移位寄存器100的第一插黑传输子电路23和第二插黑传输子电路24导通，其中，第一插黑传输子电路23中的第七晶体管M7可以将高电平的插黑输入信号传输至第一上拉节点Q<1>，第二插黑传输子电路24中的第八晶体管M8可以将高电平的插黑输入信号传输至第二上拉节点Q<2>。从而，可以抬高第一个第一移位寄存器组C中上拉节点Q<1-8>的电压。
在第七阶段T7中，CKE_9～CKE_16所传输的时钟信号的电平变为高电平，CKD_10/12/14/16所传输的第二时钟信号的电平变为高电平，第二子控制信号线BCK2所传输的第一控制信号的电平变为高电平。
第一个第一移位寄存器组C中，各输出电路输出的扫描信号均为高电平。此时，数据信号的电平为低电平，使得相应子像素P的驱动晶体管T2关断，进而使得第1～8行子像素P显示黑画面，实现插黑。
在此阶段，第一个第一移位寄存器组C中的各第二移位信号端CR2<2/4/6/8>将高电平的第二时钟信号输出。
第二个第一移位寄存器组D中，各移位寄存器100的插黑控制子电路21可以在第一控制信号的控制下导通，接收上述各第二移位信号端CR2<2/4/6/8>所输出的高电平的第二时钟信号，对各第一插黑节点M<9/11/13/15>进行充电，并使得M<9/11/13/15>的高电平保持到下一个插黑阶段。
在第八阶段T8中，第四子时钟信号线CLK所传输的第二复位信号的电平为高电平， 第一插黑节点M<1/3/5/7>的电压为高电平。
第一个第一移位寄存器组C中，各第二复位电路14和各第四复位电路34在第二复位信号及第一插黑节点M<1/3/5/7>的电压的控制下导通，将第一电压信号传输至各上拉节点Q<1-8>，对各上拉节点Q<1-8>进行下拉复位。
由于M<1081-1088>的电压为低电平，因此，Q<1081-1088>的电压可以保持为高电平。
在第九阶段T9中，第一子控制信号线BCK1所传输的第一控制信号的电平为高电平。
第一个第一移位寄存器组C中，各移位寄存器100的插黑控制子电路21导通，将低电平的起始信号传输至各第一插黑节点M进行充电，使得各第一插黑节点M<1/3/5/7>的电压为低电平。
在第十阶段T10中，第1085～1088个输出电路导通，并依次传输高电平的时钟信号至第1085～1088行子像素P，使得第1085～1088行子像素P依次进行显示操作。
上述第一阶段T1～第十阶段T10，可以不断的进行循环，即可实现显示和插黑的结合。当然本方案设置第1081～1088行子像素P进行显示的中间过程中，第1-8行子像素P进行插黑只是一种实施方案，也可以设置任意第一移位寄存器组C和第二移位寄存器组D所对应的子像素P进行显示和插黑方式。
在一些示例中，上述第六阶段T6和第五阶段T5可以同步进行，上述第十阶段T10和第八阶段T8也可以同步进行。其中，将第六阶段T6和第五阶段T5合并、并将第十阶段T10和第八阶段T8合并后，扫描驱动电路1000的工作时序图可以如图47所示。这样有利于减少显示黑画面所需的时间，提高显示效率。
下面结合图48和图49，对图39所示的扫描驱动电路1000的驱动方法进行示意性说明。其中，一个扫描信号端与一行子像素P电连接。
示例性的，在图39所示的扫描驱动电路1000中，前两级移位寄存器100的扫描信号端可以悬浮设置。
此处，以上述前两级移位寄存器100的扫描信号端(也即第一扫描信号端及第二扫描信号端)未悬浮设置为例，以便于对扫描驱动电路1000的驱动方法进行描述。
在第一阶段T1中，起始信号线BSTV所传输的起始信号的电平为高电平。
第一个第一移位寄存器组C中，各移位寄存器100的插黑控制子电路21导通。
在第二阶段T2中，第一子控制信号线BCK1所传输的第一控制信号的电平为高电平。
第一个第一移位寄存器组C中，各插黑控制子电路21可以接收并传输起始信号至第一插黑节点M，对第一插黑节点M进行充电，使得第一插黑节点M<1/3/5/7>的电压为高电平。
在第三阶段T3中，第四子时钟信号线CLK所传输的第二复位信号的电平为高电平。
此时，可以将第一插黑节点M的电压为高电平的各扫描单元的上拉节点，进行下拉复位。
在第四阶段T4中，第25～28个输出电路导通，并依次传输高电平的时钟信号至第25～28行子像素P，使得第25～28行子像素P依次进行显示操作。在第28行子像素P写入数据后，第4个移位寄存器组(也即第二移位寄存器组D)中的插黑电路2导通，并对个第一插黑节点M<25/27/29/31>进行充电。
在此阶段中，第4个移位寄存器组(也即第二移位寄存器组D)中的各上拉节点Q<25/27/29/31>的电压也抬高为高电平。
在第五阶段T5中，第三子控制信号线BCK3所传输的第二控制信号的电平为高电平。
第一个第一移位寄存器组C中，各移位寄存器100的第一插黑传输子电路23和第二插黑传输子电路24导通，其中，第一插黑传输子电路23中的第七晶体管M7可以将高电平的插黑输入信号传输至第一上拉节点Q<1>，第二插黑传输子电路24中的第八晶体管M8可以将高电平的插黑输入信号传输至第二上拉节点Q<2>。从而，可以抬高第一个第一移位寄存器组C中上拉节点Q<1-8>的电压。
在第六阶段T6中，CKE_9～CKE_16所传输的时钟信号的电平变为高电平，CKD_10/12/14/16所传输的第二时钟信号的电平变为高电平，第二子控制信号线BCK2所传输的第一控制信号的电平变为高电平。
第一个第一移位寄存器组C中，各输出电路输出的扫描信号均为高电平。此时，数据信号的电平为低电平，使得相应子像素P的驱动晶体管T2关断，进而使得第1～8行子像素P显示黑画面，实现插黑。
在此阶段，第一个第一移位寄存器组C中的各第二移位信号端CR2<2/4/6/8>将高电平的第二时钟信号输出。
第二个第一移位寄存器组D中，各移位寄存器100的插黑控制子电路21可以在第一控制信号的控制下导通，接收上述各第二移位信号端CR2<2/4/6/8>所输出的高电平的第二时钟信号，对各第一插黑节点M<9/11/13/15>进行充电，并使得M<9/11/13/15>的高电平保持到下一个插黑阶段。
在此过程中，上拉节点Q<25-32>的电压为高电平，相应的输出电路的第二移位信号端CR2<28/30/32/34>会输出第二移位信号，但是由于第五个移位寄存器组(也即C<33-40>)中插黑控制子电路21所接收的第一控制信号的电平为低电平，因此并不会影响显示行。
在第七阶段T7中，第四子时钟信号线CLK所传输的第二复位信号的电平为高电平。
由于第一插黑节点M<1/3/5/7>的电压为高电平，第一个第一移位寄存器组C中，各第二复位电路14和各第四复位电路34在第二复位信号及第一插黑节点M<1/3/5/7>的电压的控制下导通，将第一电压信号传输至各上拉节点Q<1-8>，对各上拉节点Q<1-8>进行下拉复位。
由于第一插黑节点M<25/27/29/31>的电压为低电平，因此，上拉节点Q<24-32>的电压保持为高电平。
在第八阶段T8中，第一子控制信号线BCK1所传输的第一控制信号的电平为高电平。
第一个第一移位寄存器组C中，各移位寄存器100的插黑控制子电路21导通，将低电平的起始信号传输至各第一插黑节点M进行充电，使得各第一插黑节点M<1/3/5/7>的电压为低电平。
同时，第29～32个输出电路导通，并依次传输高电平的时钟信号至第29～32行子像素P，使得第29～32行子像素P依次进行显示操作。
这样不断的进行循环，即可实现显示和插黑的结合。当然本方案设置第24～32行子像素P进行显示的中间过程中，第1-8行子像素P进行插黑只是一种实施方案，也可以设置任意第一移位寄存器组C和第二移位寄存器组D所对应的子像素P进行显示和插黑方式。
下面结合图50和图51，对图40所示的扫描驱动电路1000的驱动方法进行示意性说明。其中，一个扫描信号端与一行子像素P电连接。
在本示例中，扫描驱动电路1000的驱动方法，可以参照对图48和图49所对应的驱 动方法，此处不再赘述。
需要说明的是，本示例采用第二移位信号作为显示输入信号，将第一移位信号作为插黑级联信号，可以在图15所示的第一阶段T1中，插黑输出阶段可以合并到第三阶段T3的CKE_5与输出阶段，由于该阶段的CKE_5输出为两行的脉宽，前一行的脉宽是不写显示数据的，这样可以被插黑的CKE用来写插黑的数据，图15所示的第二阶段T2可以在写入插黑数据后紧接着对第一插黑节点M的电压为高电平的行的上拉节点Q进行复位。这样相比于无插黑功能的移位寄存器，仅多了CKE_5的预充阶段的时间，不会影响高刷新频率下的移位寄存器的输出。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (37)

  1. 一种移位寄存器，应用于显示装置，所述显示装置包括多行子像素；所述移位寄存器与至少一行子像素电连接；所述移位寄存器包括：第一扫描单元和插黑电路；
    所述第一扫描单元包括：第一输入电路和第一输出电路；
    所述第一输入电路与显示输入信号端及第一上拉节点电连接；所述第一输入电路被配置为，响应于在所述显示输入信号端处接收的显示输入信号，将所述显示输入信号传输至所述第一上拉节点；
    所述第一输出电路与所述第一上拉节点、第一时钟信号端及第一扫描信号端电连接；所述第一输出电路被配置为，在所述第一输入电路将所述显示输入信号传输至所述第一上拉节点的情况下，在所述第一上拉节点的电压的控制下，将在所述第一时钟信号端处接收的第一时钟信号传输至所述第一扫描信号端，驱动所述至少一行子像素进行图像显示；
    所述插黑电路与第一控制信号端、插黑级联信号端、第二控制信号端、插黑输入信号端、所述第一上拉节点及第一电压信号端电连接；所述插黑电路被配置为，在所述第一控制信号端所传输的第一控制信号、所述插黑级联信号端所传输的插黑级联信号及所述第二控制信号端所传输的第二控制信号的控制下，将在所述插黑输入信号端处接收的插黑输入信号传输至所述第一上拉节点；
    所述输出电路还被配置为，在所述插黑电路将所述插黑输入信号传输至所述第一上拉节点的情况下，在所述第一上拉节点的电压的控制下，将所述第一时钟信号传输至所述第一扫描信号端，驱动所述至少一行子像素进行黑画面显示。
  2. 根据权利要求1所述的移位寄存器，还包括：第二扫描单元；
    所述第二扫描单元包括：第二输入电路和第二输出电路；
    所述第二输入电路与所述显示输入信号端及第二上拉节点电连接；所述第二输入电路被配置为，响应于在所述显示输入信号，将所述显示输入信号传输至所述第二上拉节点；
    所述第二输出电路与所述第二上拉节点、第二时钟信号端及第二扫描信号端电连接；所述第二输出电路被配置为，在所述第二输入电路将所述显示输入信号传输至所述第二上拉节点的情况下，在所述第二上拉节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述第二扫描信号端，驱动所述至少一行子像素进行图像显示；
    所述插黑电路还与所述第二上拉节点电连接；所述插黑电路还被配置为，在将所述插黑输入信号传输至所述第一上拉节点的同时，将所述插黑输入信号传输至所述第二上拉节点；
    所述输出电路还被配置为，在所述插黑电路将所述插黑输入信号传输至所述第二上拉节点的情况下，在所述第二上拉节点的电压的控制下，将所述第二时钟信号传输至所述第二扫描信号端，驱动所述至少一行子像素进行黑画面显示。
  3. 根据权利要求1或2所述的移位寄存器，其中，
    所述插黑电路包括：插黑控制子电路、插黑输入子电路和第一插黑传输子电路；
    所述插黑控制子电路与所述第一控制信号端、所述插黑级联信号端、所述第一电压信号端及第一插黑节点电连接；所述插黑控制子电路被配置为，在所述第一控制信号的控制下，将所述插黑级联信号传输至所述第一插黑节点；
    所述插黑输入子电路与所述第一插黑节点、所述插黑输入信号端及第二插黑节点电连接；所述插黑输入子电路被配置为，在所述第一插黑节点的电压的控制下，将所述插黑输入信号传输至所述第二插黑节点；
    所述第一插黑传输子电路与所述第二控制信号端、所述第二插黑节点及所述第一上拉节点电连接；所述第一插黑传输子电路被配置为，在所述第二控制信号的控制下，将来自所述第二插黑节点的插黑输入信号传输至所述第一上拉节点；
    在所述移位寄存器还包括第二扫描单元的情况下，
    所述插黑电路还包括：第二插黑传输子电路；
    所述第二插黑传输子电路与所述第二控制信号端、所述第二插黑节点及所述第二上拉节点电连接；所述第二插黑传输子电路被配置为，在所述第二控制信号的控制下，将来自所述第二插黑节点的插黑输入信号传输至所述第二上拉节点。
  4. 根据权利要求1～3中任一项所述的移位寄存器，其中，
    所述第一输入电路包括：第一晶体管；
    所述第一晶体管的控制极与所述显示输入信号端电连接，所述第一晶体管的第一极与所述显示输入信号端电连接，所述第一晶体管的第二极与所述第一上拉节点电连接；
    所述第一输出电路包括：第二晶体管和第一电容器；
    所述第二晶体管的控制极与所述第一上拉节点电连接，所述第二晶体管的第一极与所述第一时钟信号端电连接，所述第二晶体管的第二极与所述第一扫描信号端电连接；
    所述第一电容器的第一端与所述第一上拉节点电连接，所述第一电容器的第二端与所述第一扫描信号端电连接；
    在所述移位寄存器还包括第二扫描单元的情况下，
    所述第二输入电路包括：第三晶体管；
    所述第三晶体管的控制极与所述显示输入信号端电连接，所述第三晶体管的第一极与所述显示输入信号端电连接，所述第三晶体管的第二极与所述第二上拉节点电连接；
    所述第二输出电路包括：第四晶体管和第二电容器；
    所述第四晶体管的控制极与所述第二上拉节点电连接，所述第四晶体管的第一极与所述第二时钟信号端电连接，所述第四晶体管的第二极与所述第二扫描信号端电连接；
    所述第二电容器的第一端与所述第二上拉节点电连接，所述第二电容器的第二端与所述第二扫描信号端电连接；
    在所述插黑电路包括插黑控制子电路、插黑输入子电路、第一插黑传输子电路及第二插黑传输子电路的情况下，
    所述插黑控制子电路包括：第五晶体管和第三电容器；
    所述第五晶体管的控制极与所述第一控制信号端电连接，所述第五晶体管的第一极与所述插黑级联信号端电连接，所述第五晶体管的第二极与所述第一插黑节点电连接；
    所述第三电容器的第一端与所述第一插黑节点电连接，所述第三电容器的第二端与所述第一电压信号端电连接；
    所述插黑输入子电路包括：第六晶体管；
    所述第六晶体管的控制极与所述第一插黑节点电连接，所述第六晶体管的第一极与所述插黑输入信号端电连接，所述第六晶体管的第二极与所述第二插黑节点电连接；
    所述第一插黑传输子电路包括：第七晶体管；
    所述第七晶体管的控制极与所述第二控制信号端电连接，所述第七晶体管的第一极与所述第二插黑节点电连接，所述第七晶体管的第二极与所述第一上拉节点电连接；
    所述第二插黑传输子电路包括：第八晶体管；
    所述第八晶体管的控制极与所述第二控制信号端电连接，所述第八晶体管的第一极与所述第二插黑节点电连接，所述第八晶体管的第二极与所述第二上拉节点电连接。
  5. 根据权利要求1～4中任一项所述的移位寄存器，其中，所述第一输出电路还与第三时钟信号端及第一感测信号端电连接；
    所述第一输出电路还被配置为，在所述第一输入电路将所述显示输入信号传输至所述第一上拉节点的情况下，在所述第一上拉节点的电压的控制下，将在所述第三时钟信号端处接收的第三时钟信号传输至所述第一感测信号端，驱动所述至少一行子像素进行复位；或，在所述插黑电路将所述插黑输入信号传输至所述第一上拉节点的情况下，在所述第一上拉节点的电压的控制下，将所述第三时钟信号传输至所述第一感测信号端，驱动所述至少一行子像素进行黑画面显示；
    在所述移位寄存器还包括第二扫描单元的情况下，
    所述第二输出电路还与第四时钟信号端及第二感测信号端电连接；
    所述第二输出电路还被配置为，在所述第二输入电路将所述显示输入信号传输至所述第二上拉节点的情况下，在所述第二上拉节点的电压的控制下，将在所述第四时钟信号端处接收的第四时钟信号传输至所述第二感测信号端，驱动所述至少一行子像素进行复位；或，在所述插黑电路将所述插黑输入信号传输至所述第二上拉节点的情况下，在所述第二上拉节点的电压的控制下，将所述第四时钟信号传输至所述第二感测信号端，驱动所述至少一行子像素进行黑画面显示。
  6. 根据权利要求5所述的移位寄存器，其中，所述第一输出电路还包括：第九晶体管和第四电容器；
    所述第九晶体管的控制极与所述第一上拉节点电连接，所述第九晶体管的第一极与所述第三时钟信号端电连接，所述第九晶体管的第二极与所述第一感测信号端电连接；
    所述第四电容器的第一端与所述第一上拉节点电连接，所述第四电容器的第二端与所述第一感测信号端电连接；
    所述第二输出电路还包括：第十晶体管和第五电容器；
    所述第十晶体管的控制极与所述第二上拉节点电连接，所述第十晶体管的第一极与所述第四时钟信号端电连接，所述第十晶体管的第二极与所述第二感测信号端电连接；
    所述第五电容器的第一端与所述第二上拉节点电连接，所述第五电容器的第二端与所述第二感测信号端电连接。
  7. 根据权利要求1～6中任一项所述的移位寄存器，其中，所述第一输出电路还与第五时钟信号端及第一移位信号端电连接；
    所述第一输出电路还被配置为，在所述第一上拉节点的电压的控制下，将在所述第五时钟信号端处接收的第五时钟信号传输至所述第一移位信号端。
  8. 根据权利要求7所述的移位寄存器，其中，所述第一输出电路还包括：第十一晶体管；
    所述第十一晶体管的控制极与所述第一上拉节点电连接，所述第十一晶体管的第一极与所述第五时钟信号端电连接，所述第十一晶体管的第二极与所述第一移位信号端电连接。
  9. 根据权利要求7或8所述的移位寄存器，其中，在所述移位寄存器还包括第二扫描单元的情况下，
    所述第二输出电路还与第六时钟信号端及第二移位信号端电连接；
    所述第二输出电路还被配置为，在所述第二上拉节点的电压的控制下，将在所述第六时钟信号端处接收的第六时钟信号传输至所述第二移位信号端。
  10. 根据权利要求9所述的移位寄存器，其中，所述第二输出电路还包括：第十二晶体管；
    所述第十二晶体管的控制极与所述第二上拉节点电连接，所述第十二晶体管的第一极与所述第六时钟信号端电连接，所述第十二晶体管的第二极与所述第二移位信号端电连接。
  11. 根据权利要求1～10中任一项所述的移位寄存器，其中，所述第一扫描单元还包括：第一复位电路和第二复位电路；
    所述第一复位电路与第一复位信号端、所述第一上拉节点及所述第一电压信号端电连接；所述第一复位电路被配置为，在所述第一复位信号端所传输的第一复位信号的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述第一上拉节点；
    在所述插黑电路包括插黑控制子电路的情况下，
    所述第二复位电路与第二复位信号端、所述第一插黑节点、所述第一上拉节点及所述第一电压信号端电连接；所述第二复位电路被配置为，在所述第一插黑节点的电压及所述第二复位信号端所传输的第二复位信号的控制下，将所述第一电压信号传输至所述第一上拉节点；
    在所述移位寄存器还包括第二扫描单元的情况下，
    所述第二扫描单元还包括：第三复位电路和第四复位电路；
    所述第三复位电路与所述第一复位信号端、所述第二上拉节点及所述第一电压信号端电连接；所述第三复位电路被配置为，在所述第一复位信号的控制下，将所述第一电压信号传输至所述第二上拉节点；
    所述第四复位电路与所述第二复位信号端、所述第一插黑节点、所述第二上拉节点及所述第一电压信号端电连接；所述第四复位电路被配置为，在所述第一插黑节点的电压及所述第二复位信号的控制下，将所述第一电压信号传输至所述第二上拉节点。
  12. 根据权利要求11所述的移位寄存器，其中，
    所述第一复位电路包括：第十三晶体管；
    所述第十三晶体管的控制极与所述第一复位信号端电连接，所述第十三晶体管的第一极与所述第一上拉节点电连接，所述第十三晶体管的第二极与所述第一电压信号端电连接；
    所述第二复位电路包括：第十四晶体管和第十五晶体管；
    所述第十四晶体管的控制极与所述第一插黑节点电连接，所述第十四晶体管的第一极与所述第一上拉节点电连接，所述第十四晶体管的第二极与所述第十五晶体管的第一极电连接；
    所述第十五晶体管的控制极与所述第二复位信号端电连接，所述第十五晶体管的第二极与所述第一电压信号端电连接；
    所述第三复位电路包括：第十六晶体管；
    所述第十六晶体管的控制极与所述第一复位信号端电连接，所述第十六晶体管的第一极与所述第二上拉节点电连接，所述第十六晶体管的第二极与所述第一电压信号端电连 接；
    所述第四复位电路包括：第十七晶体管和第十八晶体管；
    所述第十七晶体管的控制极与所述第一插黑节点电连接，所述第十七晶体管的第一极与所述第二上拉节点电连接，所述第十七晶体管的第二极与所述第十八晶体管的第一极电连接；
    所述第十八晶体管的控制极与所述第二复位信号端电连接，所述第十八晶体管的第二极与所述第一电压信号端电连接。
  13. 根据权利要求1～12中任一项所述的移位寄存器，其中，所述第一扫描单元还包括：
    第一控制电路，与所述第一上拉节点、第一下拉节点、所述第一电压信号端及第二电压信号端电连接；所述第一控制电路被配置为，响应于在所述第二电压信号端处接收的第二电压信号，将所述第二电压信号传输至所述第一下拉节点，并且，在所述第一上拉节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述第一下拉节点；
    在所述移位寄存器还包括第二扫描单元的情况下，
    所述第二扫描单元还包括：
    第二控制电路，与所述第二上拉节点、第二下拉节点、所述第一电压信号端及第三电压信号端电连接；所述第二控制电路被配置为，响应于在所述第三电压信号端处接收的第三电压信号，将所述第三电压信号传输至所述第二下拉节点，并且，在所述第二上拉节点的电压的控制下，将所述第一电压信号传输至所述第二下拉节点。
  14. 根据权利要求13所述的移位寄存器，其中，所述第一控制电路包括：第十九晶体管、第二十晶体管、第二十一晶体管和第二十二晶体管；
    所述第十九晶体管的控制极与所述第二电压信号端电连接，所述第十九晶体管的第一极与所述第二电压信号端电连接，所述第十九晶体管的第二极与所述第二十晶体管的控制极及所述第二十一晶体管的第一极电连接；
    所述第二十晶体管的第一极与所述第二电压信号端电连接，所述第二十晶体管的第二极与所述第一下拉节点电连接；
    所述第二十一晶体管的控制极与所述第一上拉节点电连接，所述第二十一晶体管的第二极与所述第一电压信号端电连接；
    所述第二十二晶体管的控制极与所述第一上拉节点电连接，所述第二十二晶体管的第一极与所述第一下拉节点电连接，所述第二十二晶体管的第二极与所述第一电压信号端电连接；
    所述第二控制电路包括：第二十三晶体管、第二十四晶体管、第二十五晶体管和第二十六晶体管；
    所述第二十三晶体管的控制极与所述第三电压信号端电连接，所述第二十三晶体管的第一极与所述第三电压信号端电连接，所述第二十三晶体管的第二极与所述第二十四晶体管的控制极及所述第二十五晶体管的第一极电连接；
    所述第二十四晶体管的第一极与所述第三电压信号端电连接，所述第二十四晶体管的第二极与所述第二下拉节点电连接；
    所述第二十五晶体管的控制极与所述第二上拉节点电连接，所述第二十五晶体管的第 二极与所述第一电压信号端电连接；
    所述第二十六晶体管的控制极与所述第二上拉节点电连接，所述第二十六晶体管的第一极与所述第二下拉节点电连接，所述第二十六晶体管的第二极与所述第一电压信号端电连接。
  15. 根据权利要求13或14所述的移位寄存器，其中，
    所述第一扫描单元还包括：第五复位电路、第六复位电路和第七复位电路；
    所述第五复位电路与所述第一下拉节点、所述第一上拉节点及所述第一电压信号端电连接；所述第五复位电路被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压信号传输至所述第一上拉节点；
    所述第六复位电路与所述第一下拉节点、所述第一扫描信号端及第四电压信号端电连接；所述第六复位电路被配置为，在所述第一下拉节点的电压的控制下，将在所述第四电压信号端处接收的第四电压信号传输至所述第一扫描信号端；
    在所述第一输出电路还与第三时钟信号端及第一感测信号端电连接的情况下，
    所述第六复位电路还与所述第一感测信号端电连接；所述第六复位电路还被配置为，在所述第一下拉节点的电压的控制下，将所述第四电压信号传输至所述第一感测信号端；
    在所述第一输出电路还与第五时钟信号端及第一移位信号端电连接的情况下，
    所述第六复位电路还与所述第一移位信号端及所述第一电压信号端电连接；所述第六复位电路还被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压信号传输至所述第一移位信号端；
    在所述插黑电路包括插黑控制子电路的情况下，
    所述第七复位电路与所述第一插黑节点、所述第二控制信号端、所述第一下拉节点及所述第一电压信号端电连接；所述第七复位电路被配置为，在所述第一插黑节点的电压及所述第二控制信号的控制下，将所述第一电压信号传输至所述第一下拉节点；
    所述第二扫描单元还包括：第八复位电路、第九复位电路和第十复位电路；
    所述第八复位电路与所述第二下拉节点、所述第二上拉节点及所述第一电压信号端电连接；所述第八复位电路被配置为，在所述第二下拉节点的电压的控制下，将所述第一电压信号传输至所述第二上拉节点；
    所述第九复位电路与所述第二下拉节点、所述第二扫描信号端及所述第四电压信号端电连接；所述第九复位电路被配置为，在所述第二下拉节点的电压的控制下，将所述第四电压信号传输至所述第二扫描信号端；
    在所述第二输出电路还与第四时钟信号端及第二感测信号端电连接的情况下，
    所述第九复位电路还与所述第二感测信号端电连接；所述第九复位电路还被配置为，在所述第二下拉节点的电压的控制下，将所述第四电压信号传输至所述第二感测信号端；
    在所述第二输出电路还与第六时钟信号端及第二移位信号端电连接的情况下，
    所述第九复位电路还与所述第二移位信号端及所述第一电压信号端电连接；所述第九复位电路还被配置为，在所述第二下拉节点的电压的控制下，将所述第一电压信号传输至所述第二移位信号端；
    所述第十复位电路与所述第一插黑节点、所述第二控制信号端、所述第二下拉节点及所述第一电压信号端电连接；所述第十复位电路被配置为，在所述第一插黑节点的电压及所述第二控制信号的控制下，将所述第一电压信号传输至所述第二下拉节点。
  16. 根据权利要求15所述的移位寄存器，其中，
    所述第五复位电路包括：第二十七晶体管；
    所述第二十七晶体管的控制极与所述第一下拉节点电连接，所述第二十七晶体管的第一极与所述第一上拉节点电连接，所述第二十七晶体管的第二极与所述第一电压信号端电连接；
    所述第六复位电路包括：第二十八晶体管、第二十九晶体管和第三十晶体管；
    所述第二十八晶体管的控制极与所述第一下拉节点电连接，所述第二十八晶体管的第一极与所述第一扫描信号端电连接，所述第二十八晶体管的第二极与所述第四电压信号端电连接；
    所述第二十九晶体管的控制极与所述第一下拉节点电连接，所述第二十九晶体管的第一极与所述第一感测信号端电连接，所述第二十九晶体管的第二极与所述第四电压信号端电连接；
    所述第三十晶体管的控制极与所述第一下拉节点电连接，所述第三十晶体管的第一极与所述第一移位信号端电连接，所述第三十晶体管的第二极与所述第一电压信号端电连接；
    所述第七复位电路包括：第三十一晶体管和第三十二晶体管；
    所述第三十一晶体管的控制极与所述第一插黑节点电连接，所述第三十一晶体管的第一极与所述第一下拉节点电连接，所述第三十一晶体管的第二极与所述第三十二晶体管的第一极电连接；
    所述第三十二晶体管的控制极与所述第二控制信号端电连接，所述第三十二晶体管的第二极与所述第一电压信号端电连接；
    所述第八复位电路包括：第三十三晶体管；
    所述第三十三晶体管的控制极与所述第二下拉节点电连接，所述第三十三晶体管的第一极与所述第二上拉节点电连接，所述第三十三晶体管的第二极与所述第一电压信号端电连接；
    所述第九复位电路包括：第三十四晶体管、第三十五晶体管和第三十六晶体管；
    所述第三十四晶体管的控制极与所述第二下拉节点电连接，所述第三十四晶体管的第一极与所述第二扫描信号端电连接，所述第三十四晶体管的第二极与所述第四电压信号端电连接；
    所述第三十五晶体管的控制极与所述第二下拉节点电连接，所述第三十五晶体管的第一极与所述第二感测信号端电连接，所述第三十五晶体管的第二极与所述第四电压信号端电连接；
    所述第三十六晶体管的控制极与所述第二下拉节点电连接，所述第三十六晶体管的第一极与所述第二移位信号端电连接，所述第三十六晶体管的第二极与所述第一电压信号端电连接；
    所述第十复位电路包括：第三十七晶体管和第三十八晶体管；
    所述第三十七晶体管的控制极与所述第一插黑节点电连接，所述第三十七晶体管的第一极与所述第二下拉节点电连接，所述第三十七晶体管的第二极与所述第三十八晶体管的第一极电连接；
    所述第三十八晶体管的控制极与所述第二控制信号端电连接，所述第三十八晶体管的 第二极与所述第一电压信号端电连接。
  17. 根据权利要求15或16所述的移位寄存器，其中，
    所述第五复位电路还与所述第二下拉节点电连接；所述第五复位电路还被配置为，在所述第二下拉节点的电压的控制下，将所述第一电压信号传输至所述第一上拉节点；
    所述第六复位电路还与所述第二下拉节点电连接；所述第六复位电路还被配置为，在所述第二下拉节点的电压的控制下，将所述第四电压信号传输至所述第一扫描信号端，将所述第四电压信号传输至所述第一感测信号端，将所述第一电压信号传输至所述第一移位信号端；
    所述第八复位电路还与所述第一下拉节点电连接；所述第八复位电路还被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压信号传输至所述第二上拉节点；
    所述第九复位电路还与所述第一下拉节点电连接；所述第九复位电路还被配置为，在所述第一下拉节点的电压的控制下，将所述第四电压信号传输至所述第二扫描信号端，将所述第四电压信号传输至所述第二感测信号端，将所述第一电压信号传输至所述第二移位信号端。
  18. 根据权利要求17所述的移位寄存器，其中，
    所述第五复位电路还包括：第三十九晶体管；
    所述第三十九晶体管的控制极与所述第二下拉节点电连接，所述第三十九晶体管的第一极与所述第一上拉节点电连接，所述第三十九晶体管的第二极与所述第一电压信号端电连接；
    所述第六复位电路还包括：第四十晶体管、第四十一晶体管和第四十二晶体管；
    所述第四十晶体管的控制极与所述第二下拉节点电连接，所述第四十晶体管的第一极与所述第一扫描信号端电连接，所述第四十晶体管的第二极与所述第四电压信号端电连接；
    所述第四十一晶体管的控制极与所述第二下拉节点电连接，所述第四十一晶体管的第一极与所述第一感测信号端电连接，所述第四十一晶体管的第二极与所述第四电压信号端电连接；
    所述第四十二晶体管的控制极与所述第二下拉节点电连接，所述第四十二晶体管的第一极与所述第一移位信号端电连接，所述第四十二晶体管的第二极与所述第一电压信号端电连接；
    所述第八复位电路还包括：第四十三晶体管；
    所述第四十三晶体管的控制极与所述第一下拉节点电连接，所述第四十三晶体管的第一极与所述第二上拉节点电连接，所述第四十三晶体管的第二极与所述第一电压信号端电连接；
    所述第九复位电路还包括：第四十四晶体管、第四十五晶体管和第四十六晶体管；
    所述第四十四晶体管的控制极与所述第一下拉节点电连接，所述第四十四晶体管的第一极与所述第二扫描信号端电连接，所述第四十四晶体管的第二极与所述第四电压信号端电连接；
    所述第四十五晶体管的控制极与所述第一下拉节点电连接，所述第四十五晶体管的第一极与所述第二感测信号端电连接，所述第四十五晶体管的第二极与所述第四电压信号端电连接；
    所述第四十六晶体管的控制极与所述第一下拉节点电连接，所述第四十六晶体管的第一极与所述第二移位信号端电连接，所述第四十六晶体管的第二极与所述第一电压信号端电连接。
  19. 根据权利要求13～18中任一项所述的移位寄存器，还包括：消隐电路；
    所述消隐电路与第三控制信号端、所述显示输入信号端、第七时钟信号端、所述第一上拉节点及所述第一电压信号端电连接；
    所述消隐电路被配置为，在所述第三控制信号端所传输的第三控制信号、所述显示输入信号及所述第七时钟信号端所传输的第七时钟信号的控制下，将所述第七时钟信号传输至所述第一上拉节点；
    在所述移位寄存器还包括第二扫描单元的情况下，
    所述消隐电路还与所述第二上拉节点电连接；所述消隐电路还被配置为，将所述第七时钟信号传输至所述第二上拉节点。
  20. 根据权利要求19所述的移位寄存器，其中，所述消隐电路包括：选择控制子电路、消隐输入子电路、第一消隐传输子电路和第二消隐传输子电路；
    所述选择控制子电路与所述第三控制信号端、所述显示输入信号端、第一消隐节点及所述第一电压信号端电连接；所述选择控制子电路被配置为，在所述第三控制信号的控制下，将所述显示输入信号传输至所述第一消隐节点；
    所述消隐传输子电路与所述第一消隐节点、所述第七时钟信号端及第二消隐节点电连接；所述消隐传输子电路被配置为，在所述第一消隐节点的电压的控制下，将所述第七时钟信号传输至所述第二消隐节点；
    所述第一消隐传输子电路与所述第七时钟信号端、所述第二消隐节点及所述第一上拉节点电连接；所述第一消隐传输子电路被配置为，在所述第七时钟信号的控制下，将来自所述第二消隐节点的第七时钟信号传输至所述第一上拉节点；
    所述第二消隐传输子电路与所述第七时钟信号端、所述第二消隐节点及所述第二上拉节点电连接；所述第二消隐传输子电路被配置为，在所述第七时钟信号的控制下，将来自所述第二消隐节点的第七时钟信号传输至所述第二上拉节点。
  21. 根据权利要求20所述的移位寄存器，其中，
    所述选择控制子电路包括：第四十七晶体管和第六电容器；
    所述第四十七晶体管的控制极与所述第三控制信号端电连接，所述第四十七晶体管的第一极与所述显示输入信号端电连接，所述第四十七晶体管的第二极与所述第一消隐节点电连接；
    所述第六电容器的第一端与所述第一消隐节点电连接，所述第六电容器的第二端与所述第一电压信号端电连接；
    所述消隐输入子电路包括：第四十八晶体管；
    所述第四十八晶体管的控制极与所述第一消隐节点电连接，所述第四十八晶体管的第一极与所述第七时钟信号端电连接，所述第四十八晶体管的第二极与所述第二消隐节点电连接；
    所述第一消隐传输子电路包括：第四十九晶体管；
    所述第四十九晶体管的控制极与所述第七时钟信号端电连接，所述第四十九晶体管的第一极与所述第二消隐节点电连接，所述第四十九晶体管的第二极与所述第一上拉节点电 连接；
    所述第二消隐传输子电路包括：第五十晶体管；
    所述第五十晶体管的控制极与所述第七时钟信号端电连接，所述第五十晶体管的第一极与所述第二消隐节点电连接，所述第五十晶体管的第二极与所述第二上拉节点电连接。
  22. 根据权利要求19～21中任一项所述的移位寄存器，所述第一扫描单元还包括：第十一复位电路、第十二复位电路及第十三复位电路；
    所述第十一复位电路与全局复位信号端、所述第一上拉节点及所述第一电压信号端电连接；所述第十一复位电路被配置为，在所述全局复位信号端所传输的全局复位信号的控制下，将所述第一电压信号传输至所述第一上拉节点；
    所述第十二复位电路与所述显示输入信号端、所述第一下拉节点及所述第一电压信号端电连接；所述第十二复位电路被配置为，在所述显示输入信号的控制下，将所述第一电压信号传输至所述第一下拉节点；
    在所述消隐电路包括选择控制子电路的情况下，
    所述第十三复位电路与所述第一消隐节点、所述第七时钟信号端、所述第一下拉节点及所述第一电压信号端电连接；所述第十三复位电路被配置为，在所述第一消隐节点的电压和所述第七时钟信号的控制下，将所述第一电压信号传输至所述第一下拉节点；
    所述第二扫描单元还包括：第十四复位电路、第十五复位电路及第十六复位电路；
    所述第十四复位电路与所述全局复位信号端、所述第二上拉节点及所述第一电压信号端电连接；所述第十四复位电路被配置为，在所述全局复位信号的控制下，将所述第一电压信号传输至所述第二上拉节点；
    所述第十五复位电路与所述显示输入信号端、所述第二下拉节点及所述第一电压信号端电连接；所述第十五复位电路被配置为，在所述显示输入信号的控制下，将所述第一电压信号传输至所述第二下拉节点；
    所述第十六复位电路与所述第一消隐节点、所述第七时钟信号端、所述第二下拉节点及所述第一电压信号端电连接；所述第十六复位电路被配置为，在所述第一消隐节点的电压和所述第七时钟信号的控制下，将所述第一电压信号传输至所述第二下拉节点。
  23. 根据权利要求22所述的移位寄存器，其中，所述第十一复位电路包括：第五十一晶体管；
    所述第五十一晶体管的控制极与所述全局复位信号端电连接，所述第五十一晶体管的第一极与所述第一上拉节点电连接，所述第五十一晶体管的第二极与所述第一电压信号端电连接；
    所述第十二复位电路包括：第五十二晶体管；
    所述第五十二晶体管的控制极与所述显示输入信号端电连接，所述第五十二晶体管的第一极与所述第一下拉节点电连接，所述第五十二晶体管的第二极与所述第一电压信号端电连接；
    所述第十三复位电路包括：第五十三晶体管和第五十四晶体管；
    所述第五十三晶体管的控制极与所述第一消隐节点电连接，所述第五十三晶体管的第一极与所述第一下拉节点电连接，所述第五十三晶体管的第二极与所述第五十四晶体管的第一极电连接；
    所述第五十四晶体管的控制极与所述第七时钟信号端电连接，所述第五十四晶体管的 第二极与所述第一电压信号端电连接；
    所述第十四复位电路包括：第五十五晶体管；
    所述第五十五晶体管的控制极与所述全局复位信号端电连接，所述第五十五晶体管的第一极与所述第二上拉节点电连接，所述第五十五晶体管的第二极与所述第一电压信号端电连接；
    所述第十五复位电路包括：第五十六晶体管；
    所述第五十六晶体管的控制极与所述显示输入信号端电连接，所述第五十六晶体管的第一极与所述第二下拉节点电连接，所述第五十六晶体管的第二极与所述第一电压信号端电连接；
    所述第十六复位电路包括：第五十七晶体管和第五十八晶体管；
    所述第五十七晶体管的控制极与所述第一消隐节点电连接，所述第五十七晶体管的第一极与所述第二下拉节点电连接，所述第五十七晶体管的第二极与所述第五十八晶体管的第一极电连接；
    所述第五十八晶体管的控制极与所述第七时钟信号端电连接，所述第五十八晶体管的第二极与所述第一电压信号端电连接。
  24. 根据权利要求20～23中任一项所述的移位寄存器，还包括：第一防漏电电路；
    所述第一防漏电电路与所述第一消隐节点、第五电压信号端及第一防漏电节点电连接；所述第一防漏电电路被配置为，在所述第一消隐节点的电压的控制下，将在所述第五电压信号端处接收的第五电压信号传输至所述第一防漏电节点；
    其中，所述选择控制子电路还与所述第一防漏电节点电连接。
  25. 根据权利要求24所述的移位寄存器，其中，
    所述第一防漏电电路包括：第五十九晶体管；
    所述第五十九晶体管的控制极与所述第一消隐节点电连接，所述第五十九晶体管的第一极与所述第五电压信号端电连接，所述第五十九晶体管的第二极与所述第一防漏电节点电连接；
    所述选择控制子电路还包括：第六十晶体管；
    所述第六十晶体管的控制极与所述第三控制信号端电连接，所述第六十晶体管的第一极与所述显示输入信号端电连接，所述第六十晶体管的第二极与所述第一防漏电节点电连接；
    所述选择控制子电路的第四十七晶体管的第一极与所述第一防漏电节点电连接，并通过所述第六十晶体管与所述显示输入信号端电连接。
  26. 根据权利要求1～25中任一项所述的移位寄存器，还包括：第二防漏电电路；
    所述第二防漏电电路与所述第一上拉节点、第五电压信号端及第二防漏电节点电连接；所述第二防漏电电路被配置为，在所述第一上拉节点的电压的控制下，将在所述第五电压信号端处接收的第五电压信号传输至所述第二防漏电节点；
    其中，所述第一输入电路还与所述第二防漏电节点电连接；
    在所述移位寄存器还包括第二扫描单元的情况下，所述第二输入电路还与所述第二防漏电节点电连接；
    所述插黑电路还与所述第二防漏电节点电连接；
    在所述第一扫描单元还包括第一复位电路和第二复位电路、所述第二扫描单元还包括 第三复位电路和第四复位电路的情况下，所述第一复位电路、所述第二复位电路、所述第三复位电路和所述第四复位电路，还均与所述第二防漏电节点电连接；
    在所第一扫描单元还包括第五复位电路、所述第二扫描单元还包括及第八复位电路的情况下，所述第五复位电路和所述第八复位电路，还均与所述第二防漏电节点电连接；
    在所述移位寄存器还包括消隐电路的情况下，所述消隐电路还与第二防漏电节点电连接；
    在所第一扫描单元还包括第十一复位电路、所述第二扫描单元还包括及第十四复位电路的情况下，所述第十一复位电路和所述第十四复位电路，还均与所述第二防漏电节点电连接。
  27. 根据权利要求26所述的移位寄存器，其中，
    所述第二防漏电电路包括：第六十一晶体管；
    所述第六十一晶体管的控制极与所述第一上拉节点电连接，所述第六十一晶体管的第一极与所述第五电压信号端电连接，所述第六十一晶体管的第二极与所述第二防漏电节点电连接；
    所述第一输入电路还包括：第六十二晶体管；
    所述第六十二晶体管的控制极与所述显示输入信号端电连接，所述第六十二晶体管的第一极与所述显示输入信号端电连接，所述第六十二晶体管的第二极与所述第二防漏电节点电连接；
    所述第一晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十二晶体管与所述显示输入信号端电连接；
    所述第二输入电路中的第三晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十二晶体管与所述显示输入信号端电连接；
    在所述插黑电路包括第一插黑传输子电路的情况下，
    所述第一插黑传输子电路还包括：第六十三晶体管；
    所述第六十三晶体管的控制极与所述第二控制信号端电连接，所述第六十三晶体管的第一极与所述第二插黑节点电连接，所述第六十三晶体管的第二极与所述第二防漏电节点电连接；
    所述第一插黑传输子电路中的第七晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十三晶体管与所述第二插黑节点电连接；
    所述第二插黑传输子电路中的第八晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十三晶体管与所述第二插黑节点电连接；
    所述第一复位电路还包括：第六十四晶体管；
    所述第六十四晶体管的控制极与所述第一复位信号端电连接，所述第六十四晶体管的第一极与所述第二防漏电节点电连接，所述第六十四晶体管的第二极与所述第一电压信号端电连接；
    所述第一复位电路中的第十三晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十四晶体管与所述第一电压信号端电连接；
    所述第三复位电路中的第十六晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十四晶体管与所述第一电压信号端电连接；
    所述第二复位电路还包括：第六十五晶体管；
    所述六十五晶体管的控制极与所述第二复位信号端电连接，所述第六十五晶体管的第一极与所述第二防漏电节点电连接，所述第六十五晶体管的第二极与所述第一电压信号端电连接；
    所述第二复位电路中的第十五晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十五晶体管与所述第一电压信号端电连接；
    所述第四复位电路中的第十八晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十五晶体管与所述第一电压信号端电连接；
    所述第五复位电路还包括：第六十六晶体管；
    所述第六十六晶体管的控制极与所述第一下拉节点电连接，所述第六十六晶体管的第一极与所述第二防漏电节点电连接，所述第六十六晶体管的第二极与所述第一电压信号端电连接；
    所述第五复位电路中的第二十七晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十六晶体管与所述第一电压信号端电连接；
    所述第八复位电路中的第三十三晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十六晶体管与所述第一电压信号端电连接；
    在所述第五复位电路还与所述第二下拉节点电连接的情况下，所述第五复位电路还包括：第六十七晶体管；
    所述第六十七晶体管的控制极与所述第二下拉节点电连接，所述第六十七晶体管的第一极与所述第二防漏电节点电连接，所述第六十七晶体管的第二极与所述第一电压信号端电连接；
    所述第五复位电路中的第三十九晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十七晶体管与所述第一电压信号端电连接；
    所述第八复位电路中的第四十三晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十七晶体管与所述第一电压信号端电连接；
    在所述第一扫描单元还包括第十一复位电路的情况下，
    所述第十一复位电路还包括：第六十八晶体管；
    所述第六十八晶体管的控制极与所述全局复位信号端电连接，所述第六十八晶体管的第一极与所述第二防漏电节点电连接，所述第六十八晶体管的第二极与所述第一电压信号端电连接；
    所述第十一复位电路中的第五十一晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十八晶体管与所述第一电压信号端电连接；
    所述第十四复位电路中的第五十五晶体管的第二极与所述第二防漏电节点电连接，并通过所述第六十八晶体管与所述第一电压信号端电连接；
    在所述消隐电路包括第一消隐传输子电路的情况下，
    所述第一消隐传输子电路还包括：第六十九晶体管；
    所述第六十九晶体管的控制极与所述第七时钟信号端电连接，所述第六十九晶体管的第一极与所述第二消隐节点电连接，所述第六十九晶体管的第二极与所述第二防漏电节点电连接；
    所述第一消隐传输子电路中的第四十九晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十九晶体管与所述第二消隐节点电连接；
    所述第二消隐传输子电路中的第五十晶体管的第一极与所述第二防漏电节点电连接，并通过所述第六十九晶体管与所述第二消隐节点电连接。
  28. 根据权利要求3～27中任一项所述的移位寄存器，还包括：第三防漏电电路；
    所述第三防漏电电路与所述第一插黑节点、第五电压信号端及第三防漏电节点电连接；所述第三防漏电电路被配置为，在所述第一插黑节点的电压的控制下，将在所述第五电压信号端处接收的第五电压信号传输至所述第三防漏电节点；
    其中，所述插黑控制子电路还与所述第三防漏电节点电连接。
  29. 根据权利要求28所述的移位寄存器，其中，
    所述第三防漏电电路包括：第七十晶体管；
    所述第七十晶体管的控制极与所述第一插黑节点电连接，所述第七十晶体管的第一极与所述第五电压信号端电连接，所述第七十晶体管的第二极与所述第三防漏电节点电连接；
    所述插黑控制子电路还包括：第七十一晶体管；
    所述第七十一晶体管的控制极与所述第一控制信号端电连接，所述第七十一晶体管的第一极与所述插黑级联信号端电连接，所述第七十一晶体管的第二极所述第三防漏电节点电连接；
    所述插黑控制子电路中的第五晶体管的第一极与所述第三防漏电节点电连接，并通过所述第七十一晶体管与所述插黑级联信号端电连接。
  30. 一种扫描驱动电路，包括：多级级联的如权利要求1～29中任一项所述的移位寄存器。
  31. 根据权利要求30所述的扫描驱动电路，其中，多级所述移位寄存器包括多个第一移位寄存器组和多个第二移位寄存器组；第一移位寄存器组和第二移位寄存器组交替排列；
    在所述移位寄存器包括第一扫描单元和第二扫描单元的情况下，
    第一移位寄存器组包括2N级移位寄存器，第二移位寄存器组包括2N级移位寄存器；其中，N为正整数；
    所述扫描驱动电路还包括：
    第一控制信号线组，包括第一子控制信号线和第二子控制信号线；所述第一子控制信号线与所述第一移位寄存器组中各移位寄存器的第一控制信号端电连接，所述第二子控制信号线与所述第二移位寄存器组中各移位寄存器的第一控制信号端电连接；以及，
    第一时钟信号线组，包括8N个第一子时钟信号线；所述8N个第一子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第一时钟信号端及第二时钟信号端、所述第二移位寄存器组中各移位寄存器的第一时钟信号端及第二时钟信号端电连接；
    在所述移位寄存器的第一输出电路还与第三时钟信号端及第一感测信号端电连接、第二输出电路还与第四时钟信号端及第二感测信号端电连接的情况下，
    所述扫描驱动电路还包括：第二时钟信号线组；
    所述第二时钟信号线组，包括4N个第二子时钟信号线；所述4N个第二子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第三时钟信号端及第四时钟信号端电连接，并分别与所述第二移位寄存器组中各移位寄存器的第三时钟信号端及第四时钟信号端电连接；
    或者，所述第二时钟信号线组，包括8N个第二子时钟信号线；所述8N个第二子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第三时钟信号端及第四时钟信号端、所述第二移位寄存器组中各移位寄存器的第三时钟信号端及第四时钟信号端电连接；
    在所述移位寄存器的第一输出电路还与第五时钟信号端及第一移位信号端电连接、第二输出电路还与第六时钟信号端及第二移位信号端电连接的情况下，
    所述扫描驱动电路还包括：第三时钟信号线组；
    所述第三时钟信号线组，包括4N个第三子时钟信号线；所述4N个第三子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第五时钟信号端及第六时钟信号端电连接，并分别与所述第二移位寄存器组中各移位寄存器的第五时钟信号端及第六时钟信号端电连接；或，所述4N个第三子时钟信号线中的2N个第三子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第五时钟信号端电连接，另外2N个第三子时钟信号线分别与所述第二移位寄存器组中各移位寄存器的第五时钟信号端电连接；
    或者，所述第三时钟信号线组，包括8N个第三子时钟信号线；所述8N个第三子时钟信号线分别与所述第一移位寄存器组中各移位寄存器的第五时钟信号端及第六时钟信号端、所述第二移位寄存器组中各移位寄存器的第五时钟信号端及第六时钟信号端电连接。
  32. 根据权利要求31所述的扫描驱动电路，还包括：第二控制信号线组；
    所述第二控制信号线组包括：第三子控制信号线和第四子控制信号线；
    所述第三子控制信号线与所述第一移位寄存器组中各移位寄存器的第二控制信号端电连接；所述第四子控制信号线与所述第二移位寄存器组中各移位寄存器的第二控制信号端电连接。
  33. 根据权利要求32所述的扫描驱动电路，其中，所述第三子控制信号线还与所述第一移位寄存器组中各移位寄存器的插黑输入信号端电连接；
    所述第四子控制信号线还与所述第二移位寄存器组中各移位寄存器的插黑输入信号端电连接。
  34. 根据权利要求31～33中任一项所述的扫描驱动电路，其中，多级所述移位寄存器中，
    除前至少一级移位寄存器外，其余级移位寄存器的显示输入信号端，与在前的移位寄存器中的第一移位信号端电连接；
    除前至少两级移位寄存器外，其余级移位寄存器的插黑级联信号端，与在前的移位寄存器中的第二移位信号端电连接；或者，在所述移位寄存器还包括第二防漏电电路的情况下，除前至少两级移位寄存器外，其余级移位寄存器的插黑级联信号端，与在前的移位寄存器的第二防漏电节点电连接。
  35. 根据权利要求31～33中任一项所述的扫描驱动电路，其中，多级所述移位寄存器中，
    除前至少一级移位寄存器外，其余级移位寄存器的显示输入信号端，与在前的移位寄存器中的第二移位信号端电连接；
    除前至少两级移位寄存器外，其余级移位寄存器的插黑级联信号端，与在前的移位寄存器中的第一移位信号端电连接。
  36. 根据权利要求31～35中任一项所述的扫描驱动电路，其中，
    所述第一移位寄存器组中，至少两级移位寄存器共用插黑电路；
    所述第二移位寄存器组中，至少两级移位寄存器共用插黑电路。
  37. 一种显示装置，包括：
    多行子像素；以及，
    如权利要求30～35中任一项所述的扫描驱动电路；
    其中，所述扫描驱动电路中的一级移位寄存器与至少一行子像素电连接。
PCT/CN2021/113852 2021-08-20 2021-08-20 移位寄存器、扫描驱动电路及显示装置 WO2023019574A1 (zh)

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