WO2023019529A1 - 显示装置、显示面板及其制造方法 - Google Patents

显示装置、显示面板及其制造方法 Download PDF

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Publication number
WO2023019529A1
WO2023019529A1 PCT/CN2021/113636 CN2021113636W WO2023019529A1 WO 2023019529 A1 WO2023019529 A1 WO 2023019529A1 CN 2021113636 W CN2021113636 W CN 2021113636W WO 2023019529 A1 WO2023019529 A1 WO 2023019529A1
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WIPO (PCT)
Prior art keywords
layer
electrode
groove
display panel
substrate
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PCT/CN2021/113636
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English (en)
French (fr)
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WO2023019529A9 (zh
Inventor
杨盛际
董学
王辉
陈小川
卢鹏程
黄冠达
张大成
Original Assignee
京东方科技集团股份有限公司
云南创视界光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 云南创视界光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to GB2312642.8A priority Critical patent/GB2618290A/en
Priority to CN202180002209.XA priority patent/CN115997247A/zh
Priority to PCT/CN2021/113636 priority patent/WO2023019529A1/zh
Publication of WO2023019529A1 publication Critical patent/WO2023019529A1/zh
Publication of WO2023019529A9 publication Critical patent/WO2023019529A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/19—Tandem OLEDs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display device, a display panel, and a method for manufacturing the display panel.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the purpose of the disclosure is to provide a display device, a display panel and a method for manufacturing the display panel.
  • a display panel comprising:
  • the driving backplane includes a substrate, at least one wiring layer and a flat layer, the wiring layer is arranged on one side of the substrate; the flat layer covers the wiring layer, and the flat layer is provided with a concave groove;
  • the first electrode layer is arranged on the surface of the flat layer facing away from the substrate, and includes a plurality of first electrodes distributed at intervals; the orthographic projection of the groove on the flat layer is located outside the first electrodes ;
  • a pixel definition layer disposed on the surface of the flat layer away from the substrate, and exposing each of the first electrodes; the pixel definition layer forms a separation groove at the groove;
  • a conductive shielding layer at least partially disposed in the groove and insulated from the first electrode
  • a light emitting layer covering the pixel definition layer, the first electrode and the conductive shielding layer, the light emitting layer is recessed at the separation groove and directly contacts at least part of the conductive shielding layer;
  • the second electrode covers the light emitting layer.
  • the pixel definition layer covers the bottom surface of the groove, and the pixel definition layer covering the bottom surface of the groove is the bottom surface of the separation groove; the conductive The shielding layer is at least partially stacked on the bottom surface of the separation groove.
  • the conductive shielding layer is disposed on the bottom surface of the groove; the pixel definition layer exposes at least a part of the conductive shielding layer.
  • the conductive shielding layer is connected to the second electrode.
  • the separation groove includes at least one annular groove body, and the groove body surrounds a first electrode
  • the conductive shielding layer includes at least one shielding ring, and a shielding ring is provided in one of the tanks;
  • any one of the tanks and the shielding ring inside surround the same first electrode.
  • the number of the grooves is the same as the number of the first electrodes, and each of the first electrodes is surrounded by a groove, and each of the grooves Each body is provided with a shielding ring.
  • each of the grooves is connected to form an integrated structure
  • each of the shielding rings is connected to form an integrated structure
  • each of the shielding rings is connected to the second electrode.
  • the driving backplane includes a pixel area and a peripheral area outside the pixel area; the orthographic projection of the first electrode on the driving backplane is located at the pixel In the area; the orthographic projection of the edge of the second electrode on the driving backplane is located in the peripheral area;
  • the conductive shielding layer further includes a connecting body connected to the shielding ring, and the orthographic projection of the connecting body on the driving backplane extends from the pixel area to the peripheral area;
  • the second electrode is connected to the shielding ring through the connecting body.
  • At least a part of the shielding ring is connected to the second electrode through a first via hole penetrating through the light-emitting layer, at least one of the first via holes is in the planar layer
  • the orthographic projection of is located between two adjacent first electrodes.
  • At least one of the wiring layers includes a connection portion connected to the second electrode, and the shielding ring is connected to the second via hole penetrating into the planar layer.
  • the connecting part is connected.
  • the surface of the shielding ring facing away from the substrate is provided with ribs extending in the circumferential direction.
  • the surface of the shielding ring facing away from the substrate is provided with pits extending in the circumferential direction, and the ribs and the pits are arranged along the radial direction of the shielding ring. distributed.
  • the thickness of the conductive shielding layer is smaller than the depth of the groove.
  • the ratio of the width of the shielding ring to the width of the groove is less than 4:5.
  • the thickness of the conductive shielding layer is greater than the thickness of the pixel definition layer.
  • the conductive shielding layer is located on a side of the first electrode close to the substrate.
  • the bottom surface of the separation groove includes a middle region and an edge region outside the middle region, and the orthographic projection of the conductive shielding layer on the bottom surface of the separation groove is the same as the The middle regions overlap; at least a part of the edge region is located on a side of the middle region facing away from the substrate.
  • the conductive shielding layer includes a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked in a direction away from the substrate.
  • the materials of the first conductive layer and the third conductive layer are metal titanium, and the material of the second conductive layer is metal aluminum.
  • the depth of the separation groove is 800 ⁇ m-1000 ⁇ m.
  • the light emitting layer includes multiple light emitting sublayers connected in series, at least one light emitting sublayer is connected in series with an adjacent light emitting sublayer through a charge generation layer.
  • the second electrode is recessed at the separation groove to form a recessed area, and the bottom of the recessed area corresponds to the area of the conductive shielding layer facing away from the conductive shielding layer.
  • the direction is convex.
  • a method of manufacturing a display panel including:
  • the driving backplane includes a substrate, at least one wiring layer and a flat layer, the wiring layer is arranged on one side of the substrate; the flat layer covers the wiring layer;
  • a first electrode layer is formed on the surface of the flat layer away from the substrate, the first electrode layer includes a plurality of first electrodes distributed at intervals; the orthographic projection of the groove on the flat layer is located at the other than the first electrode;
  • a pixel definition layer exposing each of the first electrodes is formed on the surface of the planar layer away from the substrate, and the pixel definition layer forms a separation groove at the groove;
  • the light emitting layer is recessed at the separation groove, and is in direct contact with at least a partial area of the conductive shielding layer;
  • a second electrode covering the light emitting layer is formed.
  • a method of manufacturing a display panel including:
  • the driving backplane includes a substrate, at least one wiring layer and a flat layer, the wiring layer is arranged on one side of the substrate; the flat layer covers the wiring layer;
  • a first electrode layer is formed on the surface of the flat layer away from the substrate, the first electrode layer includes a plurality of first electrodes distributed at intervals; the orthographic projection of the groove on the flat layer is located at the other than the first electrode;
  • a pixel definition layer exposing each of the first electrodes and the conductive shielding layer is formed on the surface of the flat layer away from the substrate, and the pixel definition layer forms a separation groove at the groove;
  • the light emitting layer is recessed at the separation groove, and is in direct contact with at least a partial area of the conductive shielding layer;
  • a second electrode covering the light emitting layer is formed.
  • a display device including the display panel described in any one of the above.
  • FIG. 1 is a circuit schematic diagram of a leakage current of a light emitting unit in the related art.
  • FIG. 2 is a schematic diagram of the structure and principle of leakage of light-emitting units in the related art.
  • Fig. 3 is a spectrum diagram of a light-emitting unit in the related art.
  • FIG. 4 is a schematic diagram of an embodiment of the display panel of the present disclosure.
  • FIG. 5 is a top view of the driving backplane in an embodiment of the display panel of the present disclosure.
  • FIG. 6 is a top view of a pixel definition layer and a conductive shielding layer in an embodiment of the display panel of the present disclosure.
  • FIG. 7 is a schematic diagram of a light-emitting layer in an embodiment of the display panel of the present disclosure.
  • FIG. 8 is a schematic diagram of another embodiment of the display panel of the present disclosure.
  • FIG. 9 is a schematic diagram of another embodiment of the display panel of the present disclosure.
  • FIG. 10 is a schematic diagram of another embodiment of the display panel of the present disclosure.
  • FIG. 11 is a schematic diagram of the middle area and the edge area of the separation groove in an embodiment of the display panel of the present disclosure.
  • FIG. 12 is a schematic diagram of the middle area and the edge area of the separation groove in another embodiment of the display panel of the present disclosure.
  • FIG. 13 is a schematic diagram of ribs of the shielding ring in an embodiment of the display panel of the present disclosure.
  • FIG. 14 is a schematic diagram of convex ribs and recesses of the shielding ring in an embodiment of the display panel of the present disclosure.
  • FIG. 15 is a schematic diagram of a circuit for preventing leakage of the display panel of the present disclosure.
  • FIG. 16 is a spectrum diagram of an embodiment of the display panel of the present disclosure.
  • FIG. 17 is a schematic diagram of voltage-brightness of an embodiment of the display panel of the present disclosure.
  • FIG. 18 is a schematic diagram of the voltage-color coordinates of the red sub-pixel in an embodiment of the display panel of the present disclosure.
  • FIG. 19 is a schematic diagram of the voltage-color coordinates of the blue sub-pixel in an embodiment of the display panel of the present disclosure.
  • FIG. 20 is a schematic diagram of the voltage-color coordinates of the green sub-pixel in an embodiment of the display panel of the present disclosure.
  • 21-25 are structural schematic diagrams of some steps in an embodiment of the manufacturing method of the display panel of the present disclosure.
  • FIG. 26 is a schematic structural diagram of step S230 in another embodiment of the manufacturing method of the display panel of the present disclosure.
  • Pixel definition layer 31. Opening; 32. Separation groove; 321. Groove body; 322. Middle area; 323. Edge area;
  • Conductive shielding layer 401, first conductive layer; 402, second conductive layer; 403, third conductive layer; 41, shielding ring; 42, connecting body; 4011, convex rib; 4012, pit;
  • Light-emitting layer 51. Light-emitting sublayer; 52. Charge generation layer; 001. Light-emitting unit; 0011. Light-emitting device;
  • H1 the first via hole
  • H2 the second via hole
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • a Micro OLED (Micro Organic Light-Emitting Diode, micro organic light-emitting diode) display panel is a display panel developed in recent years, and the Micro OLED light-emitting device it contains usually has a size smaller than 100 ⁇ m.
  • the silicon-based OLED display panel is a relatively common one.
  • the silicon-based OLED can not only realize the active addressing of the pixels, but also can realize the preparation on the silicon substrate through the semiconductor manufacturing process, including pixel circuits, timing control (TCON) circuits, CMOS circuits such as over-current protection (OCP) circuits help reduce system size and weight.
  • TCON timing control
  • CMOS circuits such as over-current protection (OCP) circuits help reduce system size and weight.
  • a silicon-based OLED display panel may include a driving backplane and a light-emitting layer, wherein: the light-emitting functional layer is provided on one side of the driving backplane, and includes a plurality of light-emitting devices, and the light-emitting unit may include one or more series-connected OLED light-emitting devices, each light-emitting device includes a first electrode (anode), a light-emitting layer, and a second electrode (cathode) that are sequentially stacked in a direction away from the driving backplane, and by applying electrical signals to the first electrode and the second electrode,
  • the light-emitting layer can be driven to emit light, and the specific light-emitting principle of the OLED light-emitting device will not be described in detail here.
  • each light-emitting device can be formed by direct evaporation through a fine mask (FMM).
  • FMM fine mask
  • the light-emitting layers of each light-emitting device are distributed at intervals and emit light independently to achieve color display.
  • PPI pixel density
  • color display can also be realized by combining monochromatic light or white light with color film, that is, each light-emitting device shares the same continuous light-emitting layer, and the light-emitting layer can emit white light or other monochromatic light.
  • the color film layer has multiple light-emitting units one by one
  • the corresponding filter area, a filter area and the corresponding light-emitting unit can form a sub-pixel, and a plurality of sub-pixels form a pixel, and the colors of light that can pass through different filter areas can be different, so that different sub-pixels emit light
  • the colors may be different, and the same pixel includes multiple sub-pixels of different colors.
  • a pixel may include three sub-pixels whose emission colors are red (R), green (G), and blue (B). Thereby, color display can be realized by a plurality of pixels.
  • each light emitting unit may include two light emitting devices connected in series, the two light emitting devices share the first electrode 2a and the second electrode 3a, and there are two layers between the first electrode 2a and the second electrode 3a
  • the light-emitting sub-layer 1a, the two light-emitting sub-layers 1a are connected in series through the charge generation layer 4a to form a light-emitting layer.
  • Figure 3 shows the spectral diagrams of red (R), green (G), and blue (B) sub-pixels in the same pixel being lit simultaneously (shown in a in Figure 3) and respectively lit
  • the spectrograms shown in b-c in Figure 3.
  • the wavelength it can be seen that when the three sub-pixels are respectively lit, light of different colors escapes from the adjacent sub-pixels.
  • the R sub-pixel when the R sub-pixel emits red light, it corresponds to At the wavelength of blue light and green light, there are peaks, which are emitted by blue light and green light. This results in a reduction in the color gamut of the entire display panel.
  • the color gamut indicator (NTSC) of the display panel is only 30%.
  • the embodiment of the present disclosure provides a display panel, as shown in FIG. 4-FIG.
  • the driving backplane 1 includes a substrate 101, at least one wiring layer 103 and a flat layer 104, the wiring layer 103 is arranged on one side of the substrate 101; the flat layer 104 covers the wiring layer 103, and the flat layer 104 is provided with a groove 1041 .
  • the first electrode layer 2 is disposed on the surface of the planar layer 104 facing away from the substrate 101 , and includes a plurality of first electrodes 21 distributed at intervals, and the orthographic projection of the groove 1041 on the planar layer 104 is located outside the first electrodes 21 .
  • the pixel definition layer 3 is disposed on the surface of the planar layer 104 away from the substrate 101 and exposes each first electrode 21 ; the pixel definition layer 3 forms a separation groove 32 at the groove 1041 .
  • the conductive shielding layer 4 is at least partially disposed in the groove 1041 .
  • the light emitting layer 5 covers the pixel definition layer 3 , the first electrode 21 and the conductive shielding layer 4 , and the light emitting layer 5 is recessed at the separation groove 32 and is in direct contact with at least part of the conductive shielding layer 4 .
  • the second electrode 6 covers the light emitting layer 5 .
  • any first electrode 21 and its corresponding light emitting layer 5 and second electrode 6 can constitute a light emitting unit 001. Since the conductive shielding layer 4 is located in the groove 1041 and is insulated from the first electrode 21, at the same time, the conductive shielding layer 4 is in direct contact with the light emitting layer 5, and the orthographic projection of the groove 1041 on the flat layer 104 is located on the first electrode 21. In addition, the conductive shielding layer 4 can absorb the carriers (such as holes) generated in the light-emitting layer 5 and move along the distribution direction of the first electrode 21 to prevent mutual leakage between the light-emitting units 001, thereby improving cross-color.
  • carriers such as holes
  • the groove 1041 makes the pixel definition layer 3 have a separation groove 32, and the separation groove 32 can separate each light-emitting unit 001, and the light-emitting layer 5 is recessed at the separation groove 32, which is beneficial to make the light-emitting layer 5 in the separation groove 32. Thinning or even disconnection can also prevent electric leakage between adjacent light-emitting units 001 and improve cross-color.
  • the driving backplane 1 may include a pixel area 110 and a peripheral area 120 .
  • the peripheral area 120 is located outside the pixel area 110 and may be arranged around the pixel area 110 .
  • the driving backplane 1 is used to form a driving circuit for driving the light emitting unit 001 to emit light, and the driving circuit may include a pixel circuit and a peripheral circuit, wherein:
  • the pixel circuits can be 2T1C, 4T2C, 6T1C or 7T1C pixel circuits, as long as they can drive the light emitting unit 001 to emit light.
  • the number of pixel circuits is the same as the number of the first electrodes 21 , and they are connected to the first electrodes 21 in a one-to-one correspondence, so as to respectively control each light emitting unit 001 to emit light.
  • nTmC indicates that a pixel circuit includes n transistors (indicated by the letter "T”) and m capacitors (indicated by the letter "C").
  • the peripheral circuit is located in the peripheral area 120 and connected to the pixel circuit.
  • the peripheral circuit may include at least one of a light emission control circuit, a gate 102 drive circuit, a source drive circuit, and a power supply circuit, and of course other circuits, as long as the pixel circuit can drive the light emitting unit 001 to emit light.
  • the peripheral circuit It may also include a power supply circuit connected to the second electrode 6 for inputting a power supply signal to the second electrode 6 .
  • the peripheral circuit can input a driving signal to the first electrode 21 and a power signal to the second electrode 6 through the pixel circuit, so that the light emitting unit 001 can emit light.
  • the driving backplane 1 may include a substrate 101, which may be a silicon base, and the above-mentioned driving circuit may be formed on the silicon base through a semiconductor process
  • both the pixel circuit and the peripheral circuit may include a plurality of transistors
  • a well region 1011 may be formed in the silicon substrate through a doping process, and the well region 1011 has two doped regions 1012 distributed at intervals.
  • the gate 102 is provided on one side of the driving backplane 1 , that is, the orthographic projection of the gate 102 on the driving backplane 1 is located between the two doped regions 1012 .
  • the driving backplane 1 can also include at least one wiring layer 103 and a flat layer 104, the wiring layer 103 is arranged on one side of the substrate 101, the flat layer 104 covers the wiring layer 103, and each doped area of at least one wiring layer 103 1012 , and includes a source 1031S and a drain 1031D connected to the two doped regions 1012 of the same well region 1011 .
  • the wiring layer 103 has two layers and is located in the flat layer 104.
  • the wiring layer 103 includes a first wiring layer 1031 and a second wiring layer 1032, and the first wiring layer 1031 is located on One side of the substrate 101, and a part of the flat layer 104 is arranged between the substrate 101;
  • the first wiring layer 1031 includes a source 1031S and a drain 1031D, and the source 1031S and the drain 1031D of the same transistor are connected to the same well region
  • the two doped regions 1012 of 1011 are respectively connected to form a transistor through a well region 1011 and its corresponding gate 102 , source 1031S and drain 1031D.
  • the second wiring layer 1032 is arranged on the side of the first wiring layer 1031 away from the substrate 101, and is separated from the first wiring layer 1031 by a part of the planar layer 104, and at least part of the second wiring layer 1032 The region is connected to the first wiring layer 1031; the transistors are connected through each wiring layer 103 to form a driving circuit.
  • the specific connection lines and wiring patterns depend on the circuit structure, and are not specifically limited here.
  • Each wiring layer 103 can be formed by a sputtering process.
  • the material of the planar layer 104 can be silicon oxide, silicon oxynitride or silicon nitride, and is formed layer by layer through multiple deposition and polishing processes, that is, the planar layer 104 can be formed by stacking multiple insulating film layers.
  • each light emitting unit 001 of the display panel is distributed in an array on one side of the driving backplane 1 , for example, each light emitting unit 001 is disposed on the surface of the flat layer 104 away from the substrate 101 .
  • Each light-emitting unit 001 can include a first electrode 21, a second electrode 6, and a light-emitting layer 5 between the first electrode 21 and the second electrode 6, and the first electrode 21 and the second electrode 6 can be connected with the wiring layer 103 connection, by driving the backplane 1 to apply a driving signal to the first electrode 21 and applying a power signal to the second electrode 6, thereby driving the light-emitting layer 5 to emit light.
  • each light-emitting unit 001 can emit light of the same color, cooperate with the color filter layer 7 on the side of the second electrode 6 away from the driving backplane 1 to realize color display.
  • the scheme shown is described as an example.
  • each light emitting unit 001 can also be made to emit light independently, and the light emitting colors of different light emitting units 001 can be different.
  • a plurality of light emitting units 001 can be formed by the first electrode layer 2, the pixel definition layer 3, the light emitting layer 5 and the second electrode 6, wherein:
  • the first electrode layer 2 is disposed on one side of the driving backplane 1 , for example, the first electrode layer 2 is disposed on the surface of the planar layer 104 away from the substrate 101 .
  • the first electrode layer 2 may include a plurality of first electrodes 21 distributed at intervals, and the orthographic projection of each first electrode 21 on the driving backplane 1 is located in the pixel area 110, and is connected to the pixel circuit, and one first electrode 21 is connected to one The pixel circuit, for example, the first electrode 21 can be connected to the second wiring layer 1032 .
  • the first electrode layer 2 can be a single-layer or multi-layer structure, and its material is not particularly limited here.
  • the first electrode layer 2 may include a first layer 201, a second layer 202, a third layer 203 and a fourth layer 204 stacked in sequence in a direction away from the driving backplane 1, wherein the first layer 201 and the second layer
  • the three layers 203 can adopt the same metal material, such as titanium; the fourth layer 204 can adopt transparent conductive materials such as ITO (indium tin oxide); 204 are different metal materials, and the resistivity is lower than that of the first layer 201 and the third layer 203, for example, the material of the second layer 202 can be aluminum.
  • the pixel definition layer 3 and the first electrode layer 2 are arranged on the same surface of the driving backplane 1, that is, the flat layer 104 is away from the surface of the substrate 101, and the pixel definition layer 3 exposes each first electrode. 21.
  • the pixel definition layer 3 is provided with an opening 31 exposing the first electrode 21 , and the range of each light emitting unit 001 can be defined by the pixel definition layer 3 and the opening 31 .
  • the material of the pixel definition layer 3 may be insulating materials such as silicon oxide and silicon nitride, which are not specifically limited here.
  • any opening 31 on the driving backplane 1 is located within the exposed first electrode 21, that is, the opening 31 is not larger than the exposed first electrode 21.
  • the shape of the opening 31 may be a polygon such as rectangle, pentagon, or hexagon, but not necessarily a regular polygon.
  • the shape of the opening 31 may also be other shapes such as an ellipse, which are not specifically limited here.
  • the light emitting layer 5 covers the pixel definition layer 3 and the first electrode 21, and the area where the light emitting layer 5 is located in an opening 31 and overlaps with the first electrode layer 2 is used to form a light emitting unit 001, that is, In other words, each light emitting unit 001 can share the same light emitting layer 5 , that is, the parts of the light emitting layer 5 located in different openings 31 belong to different light emitting units 001 . In addition, since each light-emitting unit 001 shares the light-emitting layer 5 , different light-emitting units 001 emit the same color.
  • the light emitting unit 001 may include a plurality of light emitting devices 0011, and each light emitting device 0011 includes a first electrode 21, a second electrode 6, and the first electrode 21 and the second electrode. Multiple light-emitting sub-layers 51 between the electrodes 6, each light-emitting device 0011 of the same light-emitting unit 001 can share the same first electrode 21 and the same second electrode 6, that is, the same light-emitting unit 001 can have only one first electrode 21 and a second electrode 6.
  • the luminescent layer 5 may include multiple luminescent sublayers 51 connected in series along the direction away from the driving backplane 1, at least one luminescent sublayer 51 communicates with an adjacent luminescent sublayer 51 through a charge generation layer 52.
  • the sublayers 51 are connected in series. When an electrical signal is applied to the first electrode 21 and the second electrode 6 , each luminescent sublayer 51 can emit light, and different luminescent sublayers 51 can be used to emit light of different colors.
  • any luminescent sublayer 51 may include a hole injection layer (HIL), a hole transport layer (HTL), a luminescent material layer (EL), Electron transport layer (ETL) and electron injection layer (EIL), the specific luminescent principle will not be described in detail here, wherein, the number of hole injection layer, hole transport layer, electron transport layer and electron injection layer is not special here defined, and each luminescent sublayer 51 can share one or more of the hole injection layer, the hole transport layer, the electron transport layer and the electron injection layer.
  • a charge generation layer 52 may be provided between at least two adjacent luminescent sublayers 51 , so that the two luminescent sublayers 51 are connected in series.
  • the luminescent layer 5 may include three luminescent sublayers 51 of different colors, that is, the first luminescent sublayer 51 that emits red light, the second luminescent sublayer 51 that emits green light.
  • the layer 51 and the third luminescent sublayer 51 emitting blue light
  • the first luminescent sublayer 51 , the second luminescent sublayer 51 and the third luminescent sublayer 51 emit light simultaneously
  • the luminescent layer 5 can emit white light.
  • the first luminescent sublayer 51 and the second luminescent sublayer 51 share a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer, and the luminescent material layer of the second luminescent sublayer 51 is arranged on the first luminescent sublayer 51.
  • the luminescent material layer of the sublayer 51 is away from the surface of the driving backplane 1 , so that the first luminescent sublayer 51 and the second luminescent sublayer 51 are directly connected in series.
  • a charge generation layer 52 may be provided on the surface of the second luminescent sublayer 51 away from the driving backplane 1 .
  • the third luminescent sublayer 51 shares an electron injection layer with the first luminescent sublayer 51 and the second luminescent sublayer 51, and the hole injection layer of the third luminescent sublayer 51 is disposed on the surface of the charge generation layer 52 away from the driving backplane 1, Thus, the third luminescent sublayer 51 and the second luminescent sublayer 51 can be connected in series.
  • the second electrode 6 covers the light emitting layer 5 , and the orthographic projection of the second electrode 6 on the driving backplane 1 can cover the pixel area 110 and extend into the peripheral area 120 .
  • Each light emitting unit 001 can share the same second electrode 6 .
  • the voltage difference between the second electrode 6 and the first electrode 21 reaches the voltage difference that enables the light-emitting layer 5 to emit light, the light-emitting layer 5 can be made to emit light. Therefore, by controlling the power signal input to the second electrode 6 and the signal input to the The voltage of the driving signal of the first electrode 21 is used to control the light emitting layer 5 to emit light.
  • the color filter layer 7 is arranged on the side of the second electrode 6 away from the driving backplane 1, and includes a plurality of filter parts 71, and each first electrode 21 is perpendicular to each filter part 71. They are arranged opposite to each other in the direction of the substrate 101 , that is, the orthographic projection of a filter portion 71 on the flat layer 104 at least partially overlaps with a first electrode 21 .
  • Each filter portion 71 includes at least three color filter portions 71 , for example, a filter portion 71 that can transmit red light, a filter portion 71 that can transmit green light, and a filter portion 71 that can transmit blue light.
  • each light-emitting unit 001 After the light emitted by each light-emitting unit 001 is filtered by the filter part 71, monochromatic light of different colors can be obtained, thereby realizing color display, wherein a filter part 71 and its corresponding light-emitting unit 001 can form a sub-pixel
  • the color of light emitted by any sub-pixel is the color of the light transmitted by the filter portion 71
  • a plurality of sub-pixels can constitute a pixel, and the colors of light emitted by each sub-pixel of the same pixel are different.
  • the shape of the orthographic projection of the filter portion 71 on the flat layer 104 can be the same as the shape of the opening 31 of the pixel definition layer 3, and the orthographic projection of each opening 31 on the flat layer 104 is located in a one-to-one correspondence between each filter portion 71. Within the orthographic projection on the flat layer 104 .
  • the color filter layer 7 may further include a light-shielding portion 72 separating the filter portion 71 , the light-shielding portion 72 is opaque and shields the area between the two light-emitting units 001 .
  • the filter part 71 can be directly spaced from the filter part 71 by using a light-shielding material; or, in some embodiments of the present disclosure, adjacent filter parts 71 can be placed in the area corresponding to the area between two adjacent light-emitting units 001 They are stacked, and the colors of light transmitted by the two are different, so that the stacked area is opaque.
  • the color filter layer 7 may further include a transparent part.
  • a transparent part In the direction perpendicular to the substrate 101, a transparent part may It is arranged opposite to a light-emitting unit 001, so that the color filter layer 7 can also pass through white light, and the brightness can be increased through white light.
  • the light extraction layer 11 can be covered on the side of the second electrode 6 away from the driving backplane 1 to improve brightness. Further, the light extraction layer 11 can directly cover the surface of the second electrode 6 away from the driving backplane 1 .
  • the first electrode layer 2 further includes an adapter ring, and the orthographic projection of the adapter ring on the driving backplane 1 is located in the peripheral area 120, and the transfer ring
  • the connecting ring can be connected with peripheral circuits and surround the pixel area 110 .
  • the second electrode 6 can be connected with the adapter ring, so that the second electrode 6 can be connected with the peripheral circuit through the adapter ring, so that the driving signal can be applied to the second electrode 6 by the peripheral circuit.
  • the pattern of the adapter ring can be the same as that of the first electrode 21 in the pixel area 110 , so as to improve the uniformity of the pattern of the first electrode layer 2 .
  • the display panel of the present disclosure may further include a first encapsulation layer 8 , which may be disposed on the side of the second electrode 6 away from the driving backplane 1 , and Located between the color filter layer 7 and the second electrode 6, it is used to block the erosion of external water and oxygen.
  • the first encapsulation layer 8 may be a single-layer or multi-layer structure.
  • the first encapsulation layer 8 may include a first encapsulation sublayer 81, a second encapsulation sublayer 82, and a third Encapsulation sublayer 83, wherein, the material of the first encapsulation sublayer 81 and the second encapsulation sublayer 82 can be inorganic insulating materials such as silicon nitride, silicon oxide, and the second encapsulation sublayer 82 can adopt ALD (Atomic layer deposition, Atomic layer deposition) process; the material of the third encapsulation sub-layer 83 can be an organic material, which can be formed by MLD (Molecular Layer Deposition, molecular layer deposition) process.
  • ALD Atomic layer deposition, Atomic layer deposition
  • MLD Molecular Layer Deposition, molecular layer deposition
  • the display panel of the present disclosure may further include a transparent cover 10, which may cover the side of the color filter layer 7 away from the driving backplane 1, and the transparent cover 10 may be a single layer or
  • the material of the multi-layer structure is not particularly limited here.
  • the display panel of the present disclosure may further include a second encapsulation layer 9, which may cover the surface of the color filter layer 7 away from the driving backplane 1, so as to achieve flattening and facilitate covering the transparent cover 10 , and can improve the encapsulation effect and further block water and oxygen.
  • the second encapsulation layer 9 may be a single-layer or multi-layer structure, and may include inorganic materials such as silicon nitride and silicon oxide, or organic materials, and the structure of the second encapsulation layer 9 is not specifically limited here.
  • each light-emitting unit 001 shares the light-emitting layer 5
  • the carriers (such as holes) of one light-emitting unit 001 may move to other light-emitting units 001 through the film layers such as the charge generation layer 52, especially It is to move to the adjacent light-emitting unit 001, that is, leakage occurs, which affects the purity of light emission.
  • a conductive shielding layer 4 can be disposed between the flat layer 104 and the light emitting layer 5 and between two adjacent light emitting units 001, and the conductive shielding layer 4 is connected to the first Electrode 21 is insulating, but conductive. Carriers can be absorbed by the conductive shielding layer 4 to prevent the carriers from moving between the light emitting units 001 , thereby avoiding color crossover caused by electric leakage.
  • the conductive shielding layer 4 can be a single-layer or multi-layer structure.
  • the conductive shielding layer 4 includes sequentially stacked The first conductive layer 401, the second conductive layer 402 and the third conductive layer 403, the material of the first conductive layer 401 and the third conductive layer 403 can be the same as the second layer 202 and the fourth layer 204 of the first electrode layer 2
  • the materials of the first conductive layer 401 and the third conductive layer 403 are metal titanium
  • the material of the second conductive layer 402 can be the same as that of the third electrode layer of the first electrode layer 2, for example, the second conductive layer
  • the material of 402 is metal aluminum.
  • the pixel definition layer 3 can be made to correspond to the area other than the light-emitting unit 001, that is, the area other than the opening 31, to form a separation groove 32, so that the light-emitting layer 5 is recessed at the separation groove 32, which is beneficial to light emission. Thin, and even cut off the charge generation layer 52 and at least part of the light-emitting sub-layer 51 in the light-emitting layer 5, thereby further preventing leakage.
  • a groove 1041 can be provided on the flat layer 104 of the driving backplane 1, and the orthographic projection of the groove 1041 on the flat layer 104 is located on the first electrode.
  • the pixel definition layer 3 can form a separation groove 32 at the groove 1041 , and the light emitting layer 5 is recessed at the separation groove 32 , and correspondingly, is also recessed at the groove 1041 .
  • At least a part of the conductive shielding layer 4 is located in the groove 1041 and is insulated from the first electrode 21 , for example, the conductive shielding layer 4 is spaced apart from the first electrode 21 without being connected to each other.
  • the conductive shielding layer 4 is at most partly covered by the pixel definition layer 3 , so it can directly contact the light emitting layer 5 recessed into the groove 1041 , so that the carriers of the light emitting layer 5 between the two light emitting units 001 can be derived.
  • the thickness of the conductive shielding layer 4 can be smaller than the depth of the groove 1041, so as to ensure that the light emitting layer 5 can be recessed into the groove 1041, which is conducive to thinning, and even cuts off the charge generation layer 52 and at least part of the light emitting sublayer in the light emitting layer 5. 51, so as to further prevent leakage.
  • the thickness of the pixel definition layer 3 is smaller than the depth of the groove 1041, and the groove 1041 is recessed to form a separation groove 32, and the separation groove 32
  • the bottom surface covers the bottom surface of the groove 1041 , that is, the separation groove 32 does not penetrate the pixel definition layer 3 in the depth direction.
  • each wiring layer 103 can be located on the side of the bottom surface of the groove 1041 close to the substrate 101 and not exposed by the groove 1041 .
  • the conductive shielding layer 4 is located in the separation groove 32, for example, the conductive shielding layer 4 is at least partially stacked on the bottom surface of the separation groove 32, that is, the conductive shielding layer 4 is at least partially disposed on the bottom surface of the separation groove 32 away from the substrate 101 side.
  • the area of the conductive shielding layer 4 on the bottom of the separation groove 32 is smaller than the area of the bottom surface of the separation groove 32 , that is, the conductive shielding layer 4 does not completely cover the bottom surface of the separation groove 32 .
  • the depth L of the separation groove 32 can be 800 ⁇ m-1000 ⁇ m, such as 800 ⁇ m, 900 ⁇ m or 1000 ⁇ m. It should be noted that the bottom surface of the separation groove 32 is not limited to a plane, and may be a curved surface or an irregular surface. The depth of the separation groove 32 refers to the distance between the bottom surface of the separation groove 32 and the closest point to the substrate 101 and the substrate 101. distance between.
  • the pixel definition layer 3 may be recessed along the groove 1041, but expose at least part of the bottom surface of the groove 1041, and may cover the bottom surface of the groove 1041. side wall.
  • the conductive shielding layer 4 is disposed on the bottom surface of the groove 1041 , and at least part of the region is exposed by the pixel definition layer 3 , so that the light emitting layer 5 recessed into the groove 1041 can directly contact the conductive shielding layer 4 . Since the conductive shielding layer 4 and the first electrode layer 21 are both stacked on the planar layer 104 , the conductive shielding layer 4 and the first electrode layer 21 can be formed simultaneously through the same process to simplify the process. Of course, they can also be formed independently.
  • the pixel definition layer 3 may be located outside the boundary of the groove 1041 without extending into the groove 1041, that is, the pixel definition layer 3 does not cover the sidewall and bottom surface of the groove 1041, so that the pixel definition
  • the layer 3 forms a separation groove 32 through the pixel definition layer 3 at the groove 1041 , the sidewall of the separation groove 32 can be flush with the sidewall of the groove 1041 or located outside the sidewall of the groove 1041 , thereby exposing the groove 1041 .
  • the conductive shielding layer 4 can be disposed on the bottom surface of the groove 1041 and not covered by the pixel definition layer 3 , so that the light emitting layer 5 recessed into the groove 1041 can directly contact the conductive shielding layer 4 . Since the conductive shielding layer 4 and the first electrode layer 21 are both stacked on the flat layer 104, the conductive shielding layer 4 and the first electrode layer 21 can be formed simultaneously through the same process to simplify the process. Of course, they can also be formed independently.
  • the light-emitting unit 001 can be surrounded by the conductive shielding layer 4 and the separation groove 32.
  • the separation groove 32 includes at least one annular groove body 321, and a groove body 321 surrounds a first electrode 21; correspondingly, the conductive shielding layer 4 may include at least one shielding ring 41 , a shielding ring 41 is disposed in a tank body 321 , and the shielding ring 41 can be stacked on the bottom surface of the tank body 321 .
  • a first electrode 21 can be surrounded by the slot body 321 and the shielding ring 41 inside the slot body 321 , that is, a light emitting unit 001 can be surrounded.
  • each shielding ring 41 can be connected to the second electrode 6 so as to lead out the carriers absorbed by the conductive shielding layer 4 , making it difficult for the light emitting unit 001 to leak electricity to the adjacent light emitting unit 001 .
  • the ratio of the width of the shielding ring 41 to the width of the groove 1041 is less than 4:5, so that there is a certain distance between the shielding ring 41 and the sidewall of the groove 1041.
  • the ratio of the width can also be larger or more Small
  • the width of the shielding ring 41 is the distance between the inner wall and the outer wall of the shielding ring 41 .
  • the thickness of the conductive shielding layer 4 may be greater than that of the pixel definition layer 3 .
  • the conductive shielding layer 4 can be located on the side of the first electrode 21 close to the substrate 101, that is, the conductive shielding layer 4 does not exceed the groove 1041, that is, the conductive shielding layer 4 is located on the flat layer 104 where the first electrode 21 is disposed. The surface is close to the side of the substrate 101 .
  • the separation groove 32 may include a plurality of slot bodies 321, and the conductive shielding layer 4 may include a plurality of shielding rings 41, and the number of the slot bodies 321 and the shielding rings 41 may be the same as the number of the first electrodes 21.
  • each tank body 321 is provided with a shielding ring 41, and the two can be concentrically arranged in an annular structure.
  • Each slot 321 and the shielding ring 41 inside can surround a first electrode 21 .
  • the shape of the groove 1041 directly limits the shape of the separation groove 32. Therefore, if the separation groove 32 includes the above-mentioned multiple annular groove bodies 321, Then the groove 1041 also includes a plurality of annular grooves.
  • the bottom surface of the separation groove 32 may include a middle region 322 and an edge region 323 outside the middle region 322, and the orthographic projection of the conductive shielding layer 4 on the bottom surface of the separation groove 32 is the same as
  • the middle area 322 overlaps, and the thickness of the middle area 322 is greater than the thickness of the edge area 323, that is to say, in the bottom surface of the separation groove 32, the thickness of the area covered by the conductive shielding layer 4 is greater than that of the area not covered by the conductive shielding layer 4. thickness.
  • the edge region 323 is located on the side of the middle region 322 away from the substrate 101 , that is, the maximum distance between the edge region 323 and the substrate 101 The distance is greater than the maximum distance between the middle region 322 and the substrate 101 , so that the middle region 322 is recessed toward the substrate 101 with respect to the edge region 323 .
  • the shape of the edge region 323 may be a curved surface that is protruding away from the substrate 101 toward the middle region 322 , and is connected between the sidewall of the separation groove 32 and the middle region 322 .
  • the bottom surface of the groove 1041 of the flat layer 104 can form the middle part and the side parts on both sides of the middle part, and the side parts face away from the substrate 101 toward the middle part One side of the groove is raised, so that the middle part is concave relative to the side part.
  • the pixel definition layer 3 When the pixel definition layer 3 is formed, the pixel definition layer 3 covering the bottom surface of the groove 1041 forms a shape matching the bottom surface of the groove 1041, that is, the above-mentioned middle part is formed. zone 322 and edge zone 323.
  • the above-mentioned middle region 322 and edge region 323 can also be formed by controlling the thickness of the pixel definition layer 3 in the groove 1041 .
  • the shielding ring 41 may have an uneven structure, for example:
  • the surface of the shielding ring 41 facing away from the substrate 101 may be provided with ribs 4011 extending in the circumferential direction, and the surface of the shielding ring 41 facing away from the substrate 101 is located on both sides of the ribs 4011.
  • the area of the sides may be flat.
  • the convex rib 4011 and the shielding ring 41 have an integrated structure, which can be formed by the protrusion of the third conductive layer 403.
  • the protrusion of the third conductive layer 403 can be formed by increasing its own thickness, or it can be formed by the first conductive layer 403.
  • Layer 401 and second conductive layer 402 are formed in a raised shape.
  • the surface of the shielding ring 41 facing away from the substrate 101 is provided with the above-mentioned raised rib 4011 , and may also be provided with a circumferentially extending recess 4012 , the raised rib 4011 and
  • the dimples 4012 can be distributed along the radial direction of the shielding ring 41 , that is, distributed from the inner wall to the outer wall of the shielding ring 41 .
  • the number of ribs 4011 and recesses 4012 is not limited thereto, as long as they are distributed radially along the shielding ring 41 .
  • the conductive shielding layer 4 can be connected with peripheral circuits.
  • a power signal can be input to the conductive shielding layer 4, and the voltage difference between the power signal and the power signal input to the second electrode 6 is smaller than the turn-on voltage difference that enables the luminescent layer 5 to emit light, thereby avoiding the contact between the conductive shielding layer 4 and the second electrode 6.
  • the light emitting layer 5 between the electrodes 6 emits light, and only the light emitting layer 5 between the first electrode 21 and the second electrode 6 emits light.
  • the conductive shielding layer 4 can be connected with the second electrode 6, although the light-emitting layer 5 also exists between the conductive shielding layer 4 and the second electrode 6, but because the conductive shielding layer 4 is connected with the second electrode 6, it is connected with the second electrode 6.
  • the potentials of the electrodes 6 are the same, and the voltage difference is zero, so the light-emitting layer 5 will not be driven to emit light.
  • the conductive shielding layer 4 can also be grounded directly through the peripheral circuit, or connected to other signals, as long as the carriers can be derived to avoid leakage between adjacent light-emitting units 001, and the light-emitting layer 5 will not be connected to the ground corresponding to the conductive shielding layer.
  • the area of 4 can be illuminated.
  • the shielding ring 41 can be connected into an integrated structure.
  • the conductive shielding layer 4 can also include a connecting body 42, the orthographic projection of the connecting body 42 on the driving backplane 1 extends from the pixel area 110 to the peripheral area 120, and the connecting body 42 is connected to at least one shielding ring 41, The area corresponding to the peripheral area 120 is connected to the second electrode 6; the number of connecting bodies 42 can be multiple, and distributed around the pixel area 110, each connecting body 42 can be connected to a shielding ring 41, because each shielding ring 41 is connected as Therefore, each connecting body 42 is electrically connected to each shielding ring 41 .
  • the structure of the connecting body 42 may be a wire or the like, and there is no special limitation here, as long as it can function as a conductive connection.
  • the orthographic projection of the light emitting layer 5 on the driving backplane 1 covers the pixel area 110 and extends into the peripheral area 120 , and has a certain distance from the boundary of the peripheral area 120 .
  • the boundary of the orthographic projection of the second electrode 6 on the driving backplane 1 is located outside the boundary of the light emitting layer 5; The regions are in direct contact, so that the second electrode 6 is connected to the shielding ring 41 via the connecting body 42 .
  • At least a part of the shielding ring 41 can be connected to the second electrode 6 through the first via hole H1 penetrating the light emitting layer 5, and at least one first via hole H1 is in the planar layer
  • the orthographic projection of 104 is located between two adjacent first electrodes 21 . If each shielding ring 41 has an integral structure, then at least one shielding ring 41 needs to be connected to the second electrode 6.
  • a plurality of first via holes H1 can be provided to connect the plurality of shielding rings 41 to the second electrode 6. , but can be used to connect each shielding ring 41 to the second electrode 6 , and the orthographic projections of each first via hole H1 on the driving backplane 1 are located in the pixel region 110 .
  • connection portion 1032a may include a connection portion 1032a
  • the second wiring layer 1032 may include a connection portion 1032a.
  • the potential of the connection part 1032a can be the same as that of the second electrode 6.
  • the connection part 1032a can extend to the peripheral area and be connected to the second electrode 6, and the potential and the power input to the second electrode 6 can also be input to the connection part 1032a.
  • a second via hole H2 connected to the connecting portion 1032a can be provided in the flat layer 104, and the second via hole H2 can be connected to the shielding ring 41, thereby connecting the shielding ring 41 to the second electrode 6; or, the shielding ring 41
  • the potential is equal to that of the second electrode 6 , thereby preventing the light emitting layer 5 between the shielding ring 41 and the second electrode 6 from emitting light.
  • the second via hole H2 can penetrate the pixel definition layer 3 . If the conductive shielding layer 4 is disposed on the bottom surface of the groove 1041 , the second via hole H2 does not need to penetrate the pixel definition layer 3 .
  • the second electrode 6 is recessed at the separation groove 32 to form a recessed region 61 , and the depth of the recessed region 61 is not greater than the depth of the separation groove 32 .
  • the bottom surface of the recessed area 61 corresponding to the region of the conductive shielding layer 4 bulges in a direction away from the conductive shielding layer 4, and the height of the protrusion is smaller than the separation groove 32.
  • the depth of groove 32 is provided in the separation groove 32.
  • Figure 15 shows the circuit principle of the conductive shielding layer 4 absorbing carriers, it can be seen that the carriers (holes) between two adjacent light emitting units 001 are absorbed by the conductive shielding layer 4, Electric leakage between two light emitting units 001 is avoided.
  • FIG. 16 shows the spectrum diagrams of three sub-pixels of red (R), green (G) and blue (B) being turned on at the same time and the spectrum diagrams of the three sub-pixels being turned on separately.
  • R red
  • G green
  • B blue
  • FIG. 17 shows the voltage-brightness curves of three sub-pixels of red (R), green (G), and blue (B), wherein, the R, G, and B curves are three sub-pixels in an embodiment of the present disclosure.
  • the curves of sub-pixels, R-071, G-071 and B-071 are the curves of three sub-pixels in the related art.
  • Figures 18-20 respectively show the voltage-color coordinate curves of three sub-pixels of red (R), green (G), and blue (B), wherein, sample-R-x, sample-R-y, sample-G-x, sample-G-y , sample-B-x, and sample-B-y curves are color coordinate curves of three sub-pixels in an embodiment of the present disclosure; R-x, R-y, G-x, G-y, B-x, B-y curves are color coordinate curves of three sub-pixels in the related art.
  • some implementations of the display panel of the present disclosure can prevent electric leakage, thereby avoiding the problem of cross-color.
  • the present disclosure also provides a method for manufacturing a display panel.
  • the display panel may be the display panel in any of the above-mentioned embodiments, as shown in FIG. 4 and FIG. 21-FIG. 25 , the manufacturing method may include step S110-step S170, wherein:
  • Step S110 forming a driving backplane;
  • the driving backplane includes a substrate, at least one wiring layer and a flat layer, the wiring layer is arranged on one side of the substrate; the flat layer covers the wiring layer. As shown in Figure 25.
  • Step S120 opening grooves on the flat layer. As shown in Figure 20 and Figure 21.
  • Step S130 forming a first electrode layer on the surface of the flat layer facing away from the substrate, the first electrode layer including a plurality of first electrodes distributed at intervals; the orthographic projection of the groove on the flat layer outside the first electrode. As shown in Figure 24.
  • Step S140 forming a pixel definition layer exposing each of the first electrodes on the surface of the planar layer away from the substrate, and the pixel definition layer forms a separation groove at the groove. As shown in Figure 22 and Figure 23
  • Step S150 forming a conductive shielding layer at least in the separation groove. As shown in Figure 21.
  • Step S160 forming a light-emitting layer covering the pixel definition layer, the first electrode and the conductive shielding layer, the light-emitting layer is recessed at the separation groove, and is directly connected to at least part of the conductive shielding layer touch. As shown in Figure 4.
  • Step S170 forming a second electrode covering the light emitting layer. As shown in Figure 4.
  • step S110 includes step S1110 and step S1120, wherein:
  • Step S1110 forming a substrate.
  • Step S1120 forming at least one wiring layer and a flat layer covering the wiring layer on one side of the substrate; the first electrode layer is provided on a surface of the flat layer away from the substrate.
  • manufacturing method of the present disclosure may further include step S180:
  • a color filter layer including a plurality of filter parts is formed on the side of the second electrode away from the driving backplane, and each of the first electrodes and each of the filter parts are arranged one by one in a direction perpendicular to the substrate. relative settings. As shown in Figure 4.
  • the present disclosure also provides a method for manufacturing a display panel.
  • the display panel may be the display panel in any of the above-mentioned embodiments.
  • the manufacturing method may include step S210-step S270, wherein:
  • Step S210 forming a driving backplane, the driving backplane includes a substrate, at least one wiring layer and a flat layer, the wiring layer is arranged on one side of the substrate; the flat layer covers the wiring layer;
  • Step S220 opening a groove on the flat layer, the orthographic projection of the groove on the flat layer is located outside the first electrode; as shown in FIG. 26 .
  • Step S230 forming a conductive shielding layer at least in the groove; as shown in FIG. 26 .
  • Step S240 forming a first electrode layer on the surface of the flat layer facing away from the substrate, the first electrode layer including a plurality of first electrodes distributed at intervals; the orthographic projection of the groove on the flat layer located outside the first electrode;
  • Step S250 forming a pixel definition layer exposing each of the first electrodes and the conductive shielding layer on the surface of the planar layer away from the substrate, and the pixel definition layer forms a separation groove at the groove;
  • Step S260 forming a light-emitting layer covering the pixel definition layer, the first electrode and the conductive shielding layer, the light-emitting layer is recessed at the separation groove, and is directly connected to at least part of the conductive shielding layer touch;
  • Step S270 forming a second electrode covering the light emitting layer.
  • manufacturing method of the present disclosure may further include step S280:
  • a color filter layer including a plurality of filter parts is formed on the side of the second electrode away from the driving backplane, and each of the first electrodes and each of the filter parts are arranged one by one in a direction perpendicular to the substrate. relative settings. As shown in Figure 8.
  • Embodiments of the present disclosure further provide a display device, including the display panel in any of the above embodiments.
  • a display device including the display panel in any of the above embodiments.
  • the display device of the present disclosure may be an electronic device with an image display function such as a mobile phone and a tablet computer, which will not be listed here.

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Abstract

一种显示装置、显示面板及其制造方法，该显示面板包括：驱动背板(1)，包括衬底(101)、走线层(103)和平坦层(104)，走线层(103)设于衬底(101)一侧；平坦层(104)覆盖走线层(103)，且设有凹槽(1041)；第一电极层(2)，设于平坦层(104)背离衬底(101)的表面，包括多个第一电极(21)；像素定义层(3)，设于平坦层(104)背离衬底(101)的表面；像素定义层(3)在凹槽(1041)处形成分隔槽(32)；导电屏蔽层(4)，至少部分设于凹槽(1041)内；发光层(5)，覆盖像素定义层(3)和导电屏蔽层(4)；第二电极(6)覆盖发光层(5)；彩膜层(7)设于第二电极(6)背离衬底(101)的一侧，且包括多个滤光部(71)。

Description

显示装置、显示面板及其制造方法 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示装置、显示面板及显示面板的制造方法。
背景技术
随着显示技术的发展，显示面板已经广泛的应用于手机等各种电子设备，用于实现图像显示和触控操作。其中，OLED(OrganicLight-Emitting Diode，有机发光二极管)显示面板是较为常见的一种。但是，现有显示面板的色域仍有待提高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种显示装置、显示面板及显示面板的制造方法。
根据本公开的一个方面，提供一种显示面板，包括：
驱动背板，包括衬底、至少一层走线层和平坦层，所述走线层设于所述衬底一侧；所述平坦层覆盖所述走线层，所述平坦层设有凹槽；
第一电极层，设于所述平坦层背离所述衬底的表面，且包括间隔分布的多个第一电极；所述凹槽在所述平坦层上的正投影位于所述第一电极以外；
像素定义层，设于所述平坦层背离所述衬底的表面，且露出各所述第一电极；所述像素定义层在所述凹槽处形成分隔槽；
导电屏蔽层，至少部分设于所述凹槽内，且与所述第一电极绝缘设置；
发光层，覆盖所述像素定义层、所述第一电极和所述导电屏蔽层，所述发光层在所述分隔槽处凹陷，且与所述导电屏蔽层的至少部分区域直接接触；
第二电极，覆盖所述发光层。
在本公开的一种示例性实施例中，所述像素定义层覆盖所述凹槽的底面，且覆盖所述凹槽的底面的所述像素定义层为所述分隔槽的底面；所述导电屏蔽层至少部分层叠于所述分隔槽的底面。
在本公开的一种示例性实施例中，所述导电屏蔽层设于所述凹槽的底面；所述像素定义层至少露出所述导电屏蔽层的部分区域。
在本公开的一种示例性实施例中，所述导电屏蔽层与所述第二电极连接。
在本公开的一种示例性实施例中，所述分隔槽包括至少一个环形的槽体，一所述槽体围绕于一所述第一电极外；
所述导电屏蔽层包括至少一个屏蔽环，一所述槽体内设有一所述屏蔽环；
任一所述槽体及其内的所述屏蔽环围绕于同一所述第一电极外。
在本公开的一种示例性实施例中，所述槽体的数量与所述第一电极的数量相同，且每个所述第一电极外均围绕一所述槽体，每个所述槽体内均设有一所述屏蔽环。
在本公开的一种示例性实施例中，各所述槽体连通成一体结构，各所述屏蔽环连接成一体结构。
在本公开的一种示例性实施例中，各所述屏蔽环与所述第二电极连接。
在本公开的一种示例性实施例中，所述驱动背板包括像素区和位于所述像素区外的外围区；所述第一电极在所述驱动背板上的正投影位于所述像素区内；所述第二电极的边缘在所述驱动背板上的正投影位于所述外围区；
所述导电屏蔽层还包括与所述屏蔽环连接的连接体，所述连接体在所述驱动背板上的正投影由所述像素区延伸至所述外围区；
所述第二电极通过所述连接体与所述屏蔽环连接。
在本公开的一种示例性实施例中，至少一部分所述屏蔽环通过贯穿所述发光层的第一过孔与所述第二电极连接，至少一所述第一过孔在所述平坦层的正投影位于相邻两所述第一电极之间。
在本公开的一种示例性实施例中，至少一所述走线层包括与所述第二电极连接的连接部，所述屏蔽环通过穿入所述平坦层的第二过孔与所述连接部连接。
在本公开的一种示例性实施例中，所述屏蔽环背离所述衬底的表面设有沿周向延伸的凸棱。
在本公开的一种示例性实施例中，所述屏蔽环背离所述衬底的表面设有沿周向延伸的凹坑，所述凸棱和所述凹坑沿所述屏蔽环的径向分布。
在本公开的一种示例性实施例中，所述导电屏蔽层的厚度小于所述凹槽的深度。
在本公开的一种示例性实施例中，所述屏蔽环的宽度与所述凹槽的宽度之比小于4:5。
在本公开的一种示例性实施例中，所述导电屏蔽层的厚度大于所述像素定义层的厚度。
在本公开的一种示例性实施例中，所述导电屏蔽层位于所述第一电极靠近所述衬底的一侧。
在本公开的一种示例性实施例中，所述分隔槽的底面包括中间区和位于所述中间区外的边缘区，所述导电屏蔽层在所述分隔槽的底面的正投影与所述中间区重合；所述边缘区的至少部分区域位于所述中间区背离所述衬底的一侧。
在本公开的一种示例性实施例中，所述导电屏蔽层包括向背离所述衬底的方向依次层叠的第一导电层、第二导电层和第三导电层。
在本公开的一种示例性实施例中，所述第一导电层和所述第三导电层的材料均为金属钛，所述第二导电层的材料为金属铝。
在本公开的一种示例性实施例中，所述分隔槽的深度为800μm-1000μm。
在本公开的一种示例性实施例中，所述发光层包括串联的多层发光子层，至少一所述发光子层通过电荷生成层与相邻的一所述发光子层串联。
在本公开的一种示例性实施例中，所述第二电极在所述分隔槽处凹陷形成凹陷区，所述凹陷区的底部对应于所述导电屏蔽层的区域向背离所述导电屏蔽层的方向凸起。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
形成驱动背板，所述驱动背板包括衬底、至少一层走线层和平坦层，所述走线层设于所述衬底一侧；所述平坦层覆盖所述走线层；
在所述平坦层开设凹槽；
在所述平坦层背离所述衬底的表面形成第一电极层，所述第一电极层包括间隔分布的多个第一电极；所述凹槽在所述平坦层上的正投影位于所述第一电极以外；
在所述平坦层背离所述衬底的表面形成露出各所述第一电极的像素定义层，所述像素定义层在所述凹槽处形成分隔槽；
至少在所述分隔槽内形成导电屏蔽层；
形成覆盖所述像素定义层、所述第一电极和所述导电屏蔽层的发光层，所述发光层在所述分隔槽处凹陷，且与所述导电屏蔽层的至少部分区域直接接触；
形成覆盖所述发光层的第二电极。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
形成驱动背板，所述驱动背板包括衬底、至少一层走线层和平坦层，所述走线层设于所述衬底一侧；所述平坦层覆盖所述走线层；
在所述平坦层开设凹槽，所述凹槽在所述平坦层上的正投影位于所述第一电极以外；
至少在所述凹槽内形成导电屏蔽层；
在所述平坦层背离所述衬底的表面形成第一电极层，所述第一电极层包括间隔分布的多个第一电极；所述凹槽在所述平坦层上的正投影位于所述第一电极以外；
在所述平坦层背离所述衬底的表面形成露出各所述第一电极和所述导电屏蔽层的像素定义层，所述像素定义层在所述凹槽处形成分隔槽；
形成覆盖所述像素定义层、所述第一电极和所述导电屏蔽层的发光层，所述发光层在所述分隔槽处凹陷，且与所述导电屏蔽层的至少部分区域直接接触；
形成覆盖所述发光层的第二电极。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中发光单元漏电的电路原理图。
图2为相关技术中发光单元漏电的结构原理图。
图3为相关技术中发光单元的光谱图。
图4为本公开显示面板一实施方式的示意图。
图5为本公开显示面板一实施方式中驱动背板的俯视图。
图6为本公开显示面板一实施方式中像素定义层和导电屏蔽层的俯视图。
图7为本公开显示面板一实施方式中发光层的示意图。
图8为本公开显示面板另一实施方式的示意图。
图9为本公开显示面板再一实施方式的示意图。
图10为本公开显示面板又一实施方式的示意图。
图11为本公开显示面板一实施方式中分隔槽的中间区和边缘区的示意图。
图12为本公开显示面板另一实施方式中分隔槽的中间区和边缘区的示意图。
图13为本公开显示面板一实施方式中屏蔽环的凸棱的示意图。
图14为本公开显示面板一实施方式中屏蔽环的凸棱凹坑的示意图。
图15为本公开显示面板防止漏电的电路原理图。
图16为本公开显示面板一实施方式的光谱图。
图17为本公开显示面板一实施方式的电压-亮度示意图。
图18为本公开显示面板一实施方式中红子像素的电压-色坐标示意图。
图19为本公开显示面板一实施方式中蓝子像素的电压-色坐标示意图。
图20为本公开显示面板一实施方式中绿子像素的电压-色坐标示意图。
图21-图25为本公开显示面板的制造方法一实施方式中一些步骤的结构示意图。
图26为本公开显示面板的制造方法另一实施方式中步骤S230的结构示意图。
附图标记说明：
1、驱动背板；110、像素区；120、外围区；101、衬底；1011、阱区；1012、掺杂区；102、栅极；103、走线层；1031、第一走线层；1031S、源极；1031D、漏极；1032、第二走线层；1032a、连接部；104、平坦层；1041、凹槽；
2、第一电极层；21、第一电极；201、第一层；202、第二层；203、第三层；204、第四层；
3、像素定义层；31、开口；32、分隔槽；321、槽体；322、中间区；323、边缘区；
4、导电屏蔽层；401、第一导电层；402、第二导电层；403、第三导电层；41、屏蔽环；42、连接体；4011、凸棱；4012、凹坑；
5、发光层；51、发光子层；52、电荷生成层；001、发光单元；0011、发光器件；
6、第二电极；61、凹陷区；
7、彩膜层；71、滤光部；72、遮光部；
8、第一封装层；81、第一封装子层；82、第二封装子层；83、第三封装子层；
9、第二封装层；
10、透明盖板；
11、光提取层；
H1、第一过孔；H2、第二过孔。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
相关技术中，Micro OLED(Micro Organic Light-Emitting Diode，微型有机发光二极管)显示面板是近年来发展起来的显示面板，其包含的Micro OLED发光器件通常具有小于100μm的尺寸。其中，硅基OLED显示面板是较为常见的一种，硅基OLED不仅可以实现像素的有源寻址，并且可以通过半导体制造工艺实现在硅基底上制备包括像素电路、时序控制(TCON)电路、过电流保护(OCP)电路等CMOS电路，有利于减小系统体积，实现轻量化。
以硅基OLED显示面板为例，其可包括驱动背板和发光层，其中：发光功能层设于驱动背板一侧，且包括多个发光器件，该发光单元可包括一个或多个串联的OLED发光器件，每个发光器件均包括向背离驱动背板的方向依次层叠的第一电极(阳极)、发光层和第二电极(阴极)，通过向第一电极和第二电极施加电信号，可驱动发光层发光，OLED发光器件的具体发光原理在此不再详述。
此外，各个发光器件的发光层，可以通过精细掩膜版(FMM)直接蒸镀形成，各发光器件的发光层间隔分布，独立发光，实现彩色显示。但是由于精细掩膜版制 造工艺的限制，难以实现高PPI(像素密度)。因此，还可通过单色光或白光配合彩膜实现彩色显示，即各发光器件共用同一连续的发光层，发光层可发白光或其它单色光，彩膜层具有多个与发光单元一一对应的滤光区，一滤光区和对应的发光单元可构成一子像素，多个子像素构成一像素，不同的滤光区可透过的光线的颜色可以不同，使得不同的子像素的发光颜色可以不同，同一像素包括多个颜色不同的子像素，例如，一像素可包括发光颜色分别为红(R)、绿(G)、蓝(B)的三种子像素。由此，可通过多个像素实现彩色显示。
但是，若发光层为连续的整层结构，使得一发光单元与周边的发光单元之间容易出现漏电，导致串色，下面结合附图对串色的原因进行分析：
如图1所示，每个发光单元可包括两个串联的发光器件，两个发光器件共用第一电极2a，且共用第二电极3a，第一电极2a和第二电极3a之间具有两层发光子层1a，两层发光子层1a通过电荷生成层4a串联成发光层。从图1和图2可以看出，正电荷(空穴)通过电荷生成层4a在相邻两个发光单元之间转移，而图2可以看出，在对应彩膜层5a中的红色滤光区R的发光单元发光时，由于漏电的影响，会使对应彩膜层5a中的绿色滤光区G的发光单元也发光，导致单个像素发光纯度降低，是整个显示面板的色域降低。
如图3所示，图3示出了同一像素中的红(R)、绿(G)、蓝(B)三种子像素同时点亮的光谱图(图3中a所示)以及分别点亮的光谱图(图3中b-c所示)。根据波长可以看出，当三种子像素分别点亮时，都有不同颜色的光从相邻的子像素逸出，例如，图3中的a所示，R子像素发红光时，对应于蓝光和绿光的波长处，存在波峰，即由蓝光和绿光发出。这导致整个显示面板的色域降低。根据测算，该显示面板色域指标(NTSC)仅为30％。
本公开实施方式提供了一种显示面板，如图4-图8所示，该显示面板可包括驱动背板1、第一电极层2、像素定义层3、导电屏蔽层4、发光层5、第二电极6和彩膜层7，其中：
驱动背板1包括衬底101、至少一层走线层103和平坦层104，走线层103设于衬底101一侧；平坦层104覆盖走线层103，平坦层104设有凹槽1041。
第一电极层2设于平坦层104背离衬底101的表面，且包括间隔分布的多个第一电极21，凹槽1041在平坦层104上的正投影位于第一电极21以外。像素定义层3设于平坦层104背离衬底101的表面，且露出各第一电极21；像素定义层3在凹槽1041处形成分隔槽32。导电屏蔽层4至少部分设于凹槽1041内。发光层5覆盖像素定义层3、第一电极21和导电屏蔽层4，且发光层5在分隔槽32处凹陷，且与导电屏蔽层4的至少部分区域直接接触。第二电极6覆盖发光层5。
本公开实施方式的显示面板，任一第一电极21与其对应的发光层5和第二电极 6可构成一发光单元001。由于导电屏蔽层4位于凹槽1041内，且与第一电极21绝缘设置，同时，导电屏蔽层4与发光层5直接接触，而凹槽1041在平坦层104上的正投影位于第一电极21以外，从而可通过导电屏蔽层4吸收发光层5中产生的沿第一电极21的分布方向移动的载流子(例如空穴)，防止发光单元001之间相互漏电，从而改善串色。同时，凹槽1041使得像素定义层3具有分隔槽32，而分隔槽32可对各发光单元001进行分隔，且发光层5在分隔槽32处凹陷，有利于使发光层5在分隔槽32处减薄甚至断开，也可防止相邻的发光单元001之间相互漏电，改善串色。
下面对本公开显示面板实现显示功能的结构进行详细说明：
如图4、图5和图8所示，驱动背板1可包括像素区110和外围区120，外围区120位于像素区110外，并可围绕像素区110设置。驱动背板1用于形成驱动发光单元001发光的驱动电路，驱动电路可包括像素电路和外围电路，其中：
像素电路和发光单元001的数量均可以是多个，且像素电路位于像素区110内，像素电路可以是2T1C、4T2C、6T1C或7T1C等像素电路，只要能驱动发光单元001发光即可，在此不对其结构做特殊限定。像素电路的数量与第一电极21的数量相同，且一一对应地与第一电极21连接，以便分别控制各个发光单元001发光。其中，nTmC表示一个像素电路包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。
外围电路位于外围区120，且与像素电路连接。外围电路可包括发光控制电路、栅极102驱动电路和源极驱动电路以及电源电路中的至少一个，当然还可以包括其它电路，只要能通过像素电路驱动发光单元001发光即可，同时，外围电路还可包括与第二电极6连接的电源电路，用于向第二电极6输入电源信号。外围电路可通过像素电路向第一电极21输入驱动信号，并向第二电极6输入电源信号，从而使发光单元001发光。
在本公开的一些实施方式中，如图4和图8所示，驱动背板1可包括衬底101，衬底101可为硅基底，上述的驱动电路可通过半导体工艺形成于硅基底上，例如，像素电路和外围电路均可包括多个晶体管，可通过掺杂工艺在硅基底中形成阱区1011，阱区1011具有间隔分布的两个掺杂区1012。同时，以一个阱区1011为例：驱动背板1一侧设有栅极102，即栅极102在驱动背板1上的正投影位于两掺杂区1012之间。驱动背板1还可包括至少一层走线层103和平坦层104，走线层103设于衬底101一侧，平坦层104覆盖走线层103，至少一走线层103各掺杂区1012连接，且包括连接于同一阱区1011的两掺杂区1012的源极1031S和漏极1031D。
举例而言：走线层103的数量为两层，且位于平坦层104内，例如，走线层103包括第一走线层1031和第二走线层1032，第一走线层1031设于衬底101一侧，且与衬底101之间设有平坦层104的一部分；第一走线层1031包括源极1031S和漏极1031D，同一晶体管的源极1031S和漏极1031D与同一阱区1011的两掺杂区 1012分别连接，从而可通过一阱区1011及其对应的栅极102、源极1031S和漏极1031D形成一晶体管。第二走线层1032设于第一走线层1031背离衬底101的一侧，其与第一走线层1031之间被平坦层104的一部分分隔，且第二走线层1032的至少部分区域与第一走线层1031连接；通过各走线层103对晶体管进行连接，可形成驱动电路，具体连接线路和走线图案视电路结构而定，在此不做特殊限定。
各走线层103可通过溅射工艺形成。平坦层104的材料可采用氧化硅、氮氧化硅或氮化硅，通过多次沉积和抛光工艺逐层形成，也就是说，平坦层104可由多个绝缘膜层层叠而成。
如图4和图8所示，显示面板的各发光单元001阵列分布于驱动背板1一侧，例如，各发光单元001设于平坦层104背离衬底101的表面。每个发光单元001可包括第一电极21、第二电极6以及位于第一电极21和第二电极6之间的发光层5，第一电极21和第二电极6均可与走线层103连接，通过驱动背板1向第一电极21施加驱动信号，向第二电极6施加电源信号，从而驱动发光层5发光。
为了实现彩色显示，可以使各发光单元001均发出相同颜色的光线，配合位于第二电极6背离驱动背板1一侧的彩膜层7，实现彩色显示，本公开的实施方式以此种彩色显示的方案为例进行说明。当然，也可以使各个发光单元001分别独立发光，且不同的发光单元001的发光颜色可以不同。
在本公开的一些实施方式中，如图4和图6所示，可通过第一电极层2、像素定义层3、发光层5和第二电极6形成多个发光单元001，其中：
第一电极层2设于驱动背板1一侧面，例如，第一电极层2设于平坦层104背离衬底101的表面。第一电极层2可包括多个间隔分布的第一电极21，且各第一电极21在驱动背板1上的正投影位于像素区110，且与像素电路连接，一个第一电极21连接一个像素电路，举例而言，第一电极21可与第二走线层1032连接。
第一电极层2可为单层或多层结构，其材料在此不做特殊限定。举例而言，第一电极层2可包括向背离驱动背板1的方向依次层叠的第一层201、第二层202、第三层203和第四层204，其中，第一层201和第三层203可采用相同的金属材料，例如钛；第四层204可采用ITO(氧化铟锡)等透明导电材料；第二层202可采用与第一层201、第三层203和第四层204不同的金属材料，且电阻率低于第一层201和第三层203，例如，第二层202的材料可为铝。
如图4和图6所示，像素定义层3与第一电极层2设于驱动背板1的同一表面，即平坦层104背离衬底101的表面，且像素定义层3露出各第一电极21，具体而言，像素定义层3设有露出第一电极21的开口31，通过像素定义层3及其开口31可限定出各个发光单元001的范围。像素定义层3的材料可以是氧化硅、氮化硅等绝缘材料，在此不做特殊限定。
任一开口31在驱动背板1上的正投影位于其露出的第一电极21以内，也就是 说，开口31不大于其露出的第一电极21。如图6所示，开口31的形状可以是矩形、五边形、六边形等多边形，但不一定是正多边形，开口31的形状还可以是椭圆形等其它形状，在此不做特殊限定。
如图4和图7所示，发光层5覆盖像素定义层3和第一电极21，发光层5位于一开口31内且与第一电极层2叠的区域用于形成发光单元001，也就是说，各个发光单元001可共用同一发光层5，也就是说，发光层5位于不同开口31内的部分属于不同的发光单元001。此外，由于各发光单元001共用发光层5，使得不同的发光单元001的发光颜色相同。
在本公开的一些实施方式中，如图7所示，发光单元001可包括多个发光器件0011，每个发光器件0011均包括第一电极21、第二电极6以及第一电极21和第二电极6之间的多个发光子层51，同一发光单元001的各发光器件0011可共用同一第一电极21和同一第二电极6，也就是说，同一发光单元001可以只有一个第一电极21和一个第二电极6。
举例而言：如图7所示，发光层5可包括沿背离驱动背板1的方向依次串联的多层发光子层51，至少一发光子层51通过电荷生成层52与相邻的一发光子层51串联。在向第一电极21和第二电极6施加电信号时，各发光子层51均可发光，且不同的发光子层51可用于发出不同颜色的光线。
进一步的，如图7所示，任一发光子层51可包括沿背离驱动背板1的方向分布的空穴注入层(HIL)、空穴传输层(HTL)、发光材料层(EL)、电子传输层(ETL)和电子注入层(EIL)，具体发光原理在此不再详述，其中，空穴注入层、空穴传输层、电子传输层和电子注入层的数量在此不做特殊限定，且各发光子层51可共用空穴注入层、空穴传输层、电子传输层和电子注入层中的一个或多个。同时，至少有两个相邻的发光子层51之间可设有电荷生成层52，从而将两发光子层51串联。
在本公开的一些实施方式中，如图7所示，发光层5可包括三个颜色不同的发光子层51，即发红光的第一发光子层51、发绿光的第二发光子层51和发蓝光的第三发光子层51，第一发光子层51、第二发光子层51和第三发光子层51同时发光时，发光层5可发白光。其中，第一发光子层51和第二发光子层51共用空穴注入层、空穴传输层、电子传输层和电子注入层，且第二发光子层51的发光材料层设于第一发光子层51的发光材料层背离驱动背板1的表面，从而使第一发光子层51和第二发光子层51直接串联。第二发光子层51背离驱动背板1的表面可设有电荷生成层52。第三发光子层51与第一发光子层51和第二发光子层51共用电子注入层，第三发光子层51的空穴注入层设于电荷生成层52背离驱动背板1的表面，从而可将第三发光子层51与第二发光子层51串联。
如图4和图8所示，第二电极6覆盖发光层5，且第二电极6在驱动背板1上的正投影可覆盖像素区110，并延伸至外围区120内。各个发光单元001可共用同一 第二电极6。第二电极6与第一电极21之间的电压差达到能使发光层5发光的压差时，可使发光层5发光，因此，可通过控制输入至第二电极6的电源信号和输入至第一电极21的驱动信号的电压来控制发光层5发光。
如图4和图8所示，彩膜层7设于第二电极6背离驱动背板1的一侧，且包括多个滤光部71，各第一电极21与各滤光部71在垂直于衬底101的方向上一一相对设置，即一滤光部71在平坦层104上的正投影与一第一电极21至少部分重合。各个滤光部71中至少包括三种颜色的滤光部71，例如，可透红光的滤光部71、可透过绿光的滤光部71和可透过蓝光的滤光部71。各发光单元001发出的光线经过滤光部71的滤光作用后，可得到不同颜色的单色光，从而实现彩色显示，其中，一滤光部71与其对应的发光单元001可构成一子像素，任一子像素发光的颜色即为其滤光部71透过的光线的颜色，多个子像素可构成一像素，同一像素的各子像素的发光颜色不同。
滤光部71在平坦层104上的正投影的形状可与像素定义层3的开口31的形状相同，且各开口31在平坦层104上的正投影一一对应地位于各滤光部71在平坦层104上的正投影以内。
如图4和图8所示，彩膜层7还可包括分隔滤光部71的遮光部72，遮光部72不透光，并遮挡两发光单元001之间的区域。滤光部71可直接采用遮光材料与滤光部71间隔设置；或者，在本公开的一些实施方式中，可以使相邻的滤光部71在对应于相邻两发光单元001之间的区域层叠设置，且二者透光的光线的颜色不同，从而使得层叠区域不透光。
此外，在本公开的一些实施方式中，在发光层5发出白光的基础上，为了提高画面亮度，彩膜层7还可包括透明部，在垂直于衬底101的方向上，一透明部可与一发光单元001相对设置，使得彩膜层7还可透过白光，可通过白光增加亮度。
为了提高出光效率，可在第二电极6背离驱动背板1的一侧覆盖光提取层11，以提高亮度，进一步的，光提取层11可直接覆盖第二电极6背离驱动背板1的表面。
为了便于将第二电极6与驱动电路连接，在本公开的一些实施方式中，第一电极层2还包括转接环，转接环在驱动背板1上的正投影位于外围区120，转接环可与外围电路连接，且围绕于像素区110外。第二电极6可与转接环连接，从而可通过转接环将第二电极6与外围电路连接起来，以便由外围电路向第二电极6施加驱动信号。转接环的图案可与像素区110内的第一电极21的图案相同，以便提高第一电极层2的图案的均一性。
如图4和图8所示，在本公开的一些实施方式中，本公开的显示面板还可包括第一封装层8，其可设于第二电极6背离驱动背板1的一侧，且位于彩膜层7和第二电极6之间，用于阻隔外界水、氧的侵蚀。第一封装层8可为单层或多层结构，例如，第一封装层8可包括向背离驱动背板1的方向依次层叠的第一封装子层81、第 二封装子层82和第三封装子层83，其中，第一封装子层81和第二封装子层82的材料可以是氮化硅、氧化硅等无机绝缘材料，且第二封装子层82可采用ALD(Atomic layer deposition，原子层沉积)工艺形成；第三封装子层83的材料可为有机材料，其可采用MLD(Molecular Layer Deposition，分子层沉积)工艺形成。当然，第一封装层8还可以采用其它结构，在此不对第一封装层8的结构做特殊限定。
此外，在本公开的一些实施方式中，本公开的显示面板还可包括透明盖板10，其可覆盖于彩膜层7背离驱动背板1的一侧，透明盖板10可以是单层或多层结构，其材料在此不做特殊限定。
在本公开的一些实施方式中，本公开的显示面板还可包括第二封装层9，其可覆盖于彩膜层7背离驱动背板1的表面，以便实现平坦化，便于覆盖透明盖板10，且可以提高封装效果，进一步阻隔水、氧。第二封装层9可以是单层或多层结构，且可以包括氮化硅、氧化硅等无机材料，也可以包括有机材料，在此不对第二封装层9的结构做特殊限定。
下面对本公开的显示面板解决串色问题的方案进行详细说明：
结合上文对相关技术的分析，由于各个发光单元001共用发光层5，一发光单元001的载流子(例如空穴)可能会通过电荷生成层52等膜层向其它发光单元001移动，特别是向相邻的发光单元001移动，即发生漏电，影响发光的纯度。为此，如图4和图8所示，可在位于平坦层104和发光层5之间，且位于相邻两发光单元001之间的区域设置导电屏蔽层4，导电屏蔽层4与第一电极21绝缘，但可导电。可通过导电屏蔽层4吸收载流子，防止载流子在发光单元001之间移动，从而避免因漏电而导致的串色。
如图4和图8所示，导电屏蔽层4可为单层或多层结构，举例而言，在本公开的一些实施方式中，导电屏蔽层4包括向背离驱动背板1的方向依次层叠的第一导电层401、第二导电层402和第三导电层403，第一导电层401和第三导电层403的材料可与第一电极层2的第二层202和第四层204相同，例如，第一导电层401和第三导电层403的材料均为金属钛，第二导电层402的材料可与第一电极层2的第三电极层的材料相同，例如，第二导电层402的材料为金属铝。由此，可利用形成第一电极层2的至少部分工艺形成导电屏蔽层4，以便节约成本，同时，可使导电屏蔽层4的导电性能与第一电极层2相似，避免对第一电极21的正常发光造成影响。
如图4和图6所示，可使像素定义层3对应于发光单元001以外的区域，即开口31以外的区域，形成分隔槽32，使发光层5在分隔槽32处凹陷，有利于减薄，甚至截断发光层5中的电荷生成层52和至少部分发光子层51，从而进一步防止漏电。
为了在像素定义层3形成分隔槽32，如图4和图21所示，可在驱动背板1的平 坦层104设置凹槽1041，凹槽1041在平坦层104上的正投影位于第一电极21以外，像素定义层3可在凹槽1041处形成分隔槽32，发光层5在分隔槽32处凹陷，相应的，也在凹槽1041处凹陷。
导电屏蔽层4的至少部分区域位于凹槽1041内，且与第一电极21绝缘设置，例如，导电屏蔽层4与第一电极21间隔分布，而互不连接。同时，导电屏蔽层4至多被像素定义层3覆盖一部分，因而可与凹陷至凹槽1041内的发光层5直接接触，从而可导出两发光单元001之间的发光层5的载流子。此外，导电屏蔽层4的厚度可小于凹槽1041的深度，保证发光层5能向凹槽1041内凹陷，有利于减薄，甚至截断发光层5中的电荷生成层52和至少部分发光子层51，从而进一步防止漏电。
如图4、图20和图21所示，在本公开的一些实施方式中，像素定义层3的厚度小于凹槽1041的深度，且在凹槽1041处凹陷形成分隔槽32，分隔槽32的底面覆盖凹槽1041的底面，即分隔槽32在深度方向上不贯穿像素定义层3。为了避免凹槽1041露出走线层103，可使各个走线层103均位于凹槽1041底面靠近衬底101的一侧，而不被凹槽1041露出。同时，导电屏蔽层4的至少部分区域位于分隔槽32内，例如，导电屏蔽层4至少部分层叠于分隔槽32的底面，即导电屏蔽层4至少部分设于分隔槽32的底面背离衬底101的一侧。此外，位于分隔槽32的底部上的导电屏蔽层4的面积小于分隔槽32的底面的面积，即，导电屏蔽层4不完全遮盖分隔槽32的底面。
如图4和图20所示，为了确保分隔槽32能够使发光层5凹陷，可使分隔槽32的深度L为800μm-1000μm，例如800μm、900μm或1000μm。需要说明的是，分隔槽32的底面并不限定为平面，可以是曲面或不规则的表面，分隔槽32的深度是指分隔槽32的底面距离衬底101距离最近的一点与衬底101之间的距离。
如图8和图25所示，在本公开的另一些实施方式中，像素定义层3可沿凹槽1041内凹陷，但露出凹槽1041的底面的至少部分区域，而可以覆盖凹槽1041的侧壁。导电屏蔽层4设于凹槽1041的底面，且被像素定义层3露出至少部分区域，以使凹陷至凹槽1041内的发光层5能与导电屏蔽层4直接接触。由于导电屏蔽层4和第一电极层21均层叠于平坦层104上，因而导电屏蔽层4和第一电极层21可以通过相同的工艺同时形成，以简化工艺。当然，也可以分别独立形成。
在本公开的其它实施方式中，像素定义层3可位于凹槽1041的边界外，而不延伸至凹槽1041内，即像素定义层3不覆盖凹槽1041的侧壁和底面，使得像素定义层3在凹槽1041处形成贯穿像素定义层3的分隔槽32，分隔槽32的侧壁可与凹槽1041的侧壁平齐或者位于凹槽1041的侧壁外侧，从而露出凹槽1041。导电屏蔽层4可设于凹槽1041的底面，且不被像素定义层3遮盖，以使凹陷至凹槽1041内的发光层5能与导电屏蔽层4直接接触。由于导电屏蔽层4和第一电极层21均层叠于平坦层104上，因而导电屏蔽层4和第一电极层21可以通过相同的工艺同时形成，以 简化工艺。当然，也可以分别独立形成。
为了最大程度的避免漏电，可使发光单元001被导电屏蔽层4和分隔槽32围绕，以上述将导电屏蔽层4层叠于分隔槽32的底面的实施方式为例，如图4和图6所示，在本公开的一些实施方式中，分隔槽32包括至少一个环形的槽体321，一槽体321围绕于一第一电极21外；相应的，导电屏蔽层4可包括至少一个屏蔽环41，一槽体321内设有一屏蔽环41，屏蔽环41可层叠于槽体321的底面。可通过槽体321和槽体321内的屏蔽环41围绕一第一电极21，即围绕一发光单元001。同时，各屏蔽环41可与第二电极6连接，以便导出导电屏蔽层4吸收的载流子，使得该发光单元001难以向相邻的发光单元001漏电。
屏蔽环41的宽度可与凹槽1041的宽度之比小于4:5，使得屏蔽环41与凹槽1041的侧壁之间具有一定的距离，当然，该宽度之比也可以是更大或者更小，屏蔽环41的宽度为屏蔽环41的内壁和外壁之间的距离。同时，导电屏蔽层4的厚度可大于像素定义层3的厚度。此外，可使导电屏蔽层4可位于第一电极21靠近衬底101的一侧，即导电屏蔽层4不超出凹槽1041，也即，导电屏蔽层4位于平坦层104设置第一电极21的表面靠近衬底101的一侧。
进一步的，如图6所示，分隔槽32可包括多个槽体321，导电屏蔽层4可包括多个屏蔽环41，槽体321和屏蔽环41的数量可与第一电极21的数量相同，每个槽体321内设有一个屏蔽环41，且二者可以同心设置的环形结构。每个槽体321及其内的屏蔽环41可围绕于一第一电极21外。
需要说明的是，对于因凹陷至凹槽1041内而形成的分隔槽32，凹槽1041的形状直接限制分隔槽32的形状，因此，若分隔槽32包括上述的多个环形的槽体321，则凹槽1041也包括多个环形的槽体。
如图11所示，在本公开的一些实施方式中，分隔槽32的底面可包括中间区322和位于中间区322外的边缘区323，导电屏蔽层4在分隔槽32的底面的正投影与中间区322重合，中间区322的厚度大于边缘区323的厚度，也就是说，在分隔槽32的底面中，被导电屏蔽层4覆盖的区域的厚度大于未被导电屏蔽层4覆盖的区域的厚度。
如图12所示，在本公开的另一些实施方式中，边缘区323的至少部分区域位于中间区322背离衬底101的一侧，也就是说，边缘区323与衬底101之间的最大距离大于中间区322与衬底101之间的最大距离，使得中间区322对于边缘区323向衬底101凹陷。此外，边缘区323的形状可为向中间区322背离衬底101的因此而凸起的曲面，且连接于分隔槽32的侧壁和中间区322之间。
进一步的，为了形成上述中间区322对于边缘区323向衬底101凹陷的结构，可使平坦层104的凹槽1041的底面形成中部和中部两侧的侧部，侧部向中部背离衬底101的一侧凸起，使得中部相对于侧部凹陷，在形成像素定义层3时，覆盖凹槽 1041底面的像素定义层3形成与凹槽1041的底面相匹配的形貌，即形成上述的中间区322和边缘区323。当然，在凹槽1041的底面为平面或其它形状时，也可通过对凹槽1041内的像素定义层3的厚度的控制，形成上述的中间区322和边缘区323。
在垂直于衬底101的方向上，屏蔽环41可以是凹凸不平的结构，举例而言：
如图13所示，在本公开的一些实施方式中，屏蔽环41背离衬底101的表面可设有沿周向延伸的凸棱4011，屏蔽环41背离衬底101的表面位于凸棱4011两侧的区域可为平面。同时，凸棱4011与屏蔽环41为一体结构，其可以是第三导电层403凸起而形成，第三导电层403凸起可以是其自身厚度增大而形成，也可以是因第一导电层401和第二导电层402凸起二形成。
如图14所示，在本公开的另一些实施方式中，屏蔽环41背离衬底101的表面设有上述的凸棱4011，还可设有沿周向延伸的凹坑4012，凸棱4011和凹坑4012可沿屏蔽环41的径向分布，即由屏蔽环41的内壁相外壁分布。例如，凹坑4012的数量为两个，且同心设置，凸棱4011的数量为一个，且位于两个凹坑4012之间。当然，凸棱4011和凹坑4012的数量并不限于此，只要沿屏蔽环41径向分布即可。
为了便于导出导电屏蔽层4吸收的载流子，可将导电屏蔽层4与外围电路连接。同时，可向导电屏蔽层4输入电源信号，该电源信号与输入至第二电极6的电源信号的电压差小于能使发光层5发光的启亮压差，从而避免导电屏蔽层4与第二电极6之间的发光层5发光，而只有第一电极21与第二电极6之间的发光层5发光。举例而言，导电屏蔽层4可与第二电极6连接，虽然导电屏蔽层4和第二电极6之间也存在发光层5，但由于导电屏蔽层4和第二电极6连接，与第二电极6的电位相同，压差为零，因而不会驱动发光层5发光。当然，导电屏蔽层4也可直接通过外围电路接地，或者接入其它信号，只要能导出载流子，避免相邻发光单元001之间漏电，且不会使发光层5在对应于导电屏蔽层4的区域发光即可。
下面对屏蔽环41与第二电极6连接的方式进行详细说明：
在本公开的一些实施方式中，如图6所示，为了便于将屏蔽环41与第二电极6连接，可将使屏蔽环41连成一体结构，相应的，分隔槽32的各槽体321可连通成一体结构。举例而言，导电屏蔽层4还可包括连接体42，连接体42在驱动背板1上的正投影由像素区110延伸到外围区120，且连接体42与至少一屏蔽环41连接，在对应于外围区120的区域与第二电极6连接；连接体42的数量可为多个，且围绕像素区110分布，每个连接体42可连接一个屏蔽环41，由于各屏蔽环41连为一体，因而每个连接体42都与各屏蔽环41电连接。连接体42的结构可以是导线等，在此不做特殊限定，只要能起到导电连接的作用即可。
进一步的，发光层5在驱动背板1上的正投影覆盖像素区110并延伸至外围区 120内，且与外围区120的边界具有一定的距离。第二电极6在驱动背板1上的正投影的边界位于发光层5的边界以外；连接体42可延伸至发光层5的边界外，并与第二电极6位于发光层5的边界外的区域直接接触，从而使第二电极6通过连接体42与屏蔽环41连接。
如图9所示，在本公开的另一些实施方式中，至少一部分屏蔽环41可通过贯穿发光层5的第一过孔H1与第二电极6连接，至少一第一过孔H1在平坦层104的正投影位于相邻两第一电极21之间。若各个屏蔽环41为一体结构，则至少只要有一个屏蔽环41与第二电极6连接即可，当然，可以设置多个第一过孔H1，将多个屏蔽环41与第二电极6连接，但可以用于将每个屏蔽环41均与第二电极6连接，各个第一过孔H1在驱动背板1上的正投影均位于像素区110内。
如图10所示，在本公开的其它实施方式中，至少一走线层103可包括连接部1032a，例如，第二走线层1032可包括连接部1032a。连接部1032a的电位可与第二电极6相同，例如，连接部1032a可延伸至外围区，并与第二电极6连接，也可以向连接部1032a输入电位与与输入至第二电极6的电源信号的电位相等的信号。同时，平坦层104内可设有与连接部1032a连接第二过孔H2，第二过孔H2可与屏蔽环41连接，从而将屏蔽环41与第二电极6连接；或者，使屏蔽环41与第二电极6的电位相等，从而可防止屏蔽环41与第二电极6之间的发光层5发光。
需要说明的是，若导电屏蔽层4层叠于像素定义层3上，即层叠于分隔槽32的底面上，则第二过孔H2可贯穿像素定义层3。若导电屏蔽层4设于凹槽1041的底面，则第二过孔H2无需贯穿像素定义层3。
进一步的，由于分隔槽32存在，使得第二电极6在分隔槽32处凹陷，形成凹陷区61，凹陷区61的深度不大于分隔槽32的深度。同时，由于分隔槽32内设有导电屏蔽层4的至少部分区域，使得凹陷区61的底面对应于导电屏蔽层4的区域向背离导电屏蔽层4的方向凸起，且凸起的高度小于分隔槽32的深度。
下面对本公开显示面板的效果进行说明：
如图15所示，图15示出了导电屏蔽层4吸收载流子的电路原理，可以看出，相邻两发光单元001之间的载流子(空穴)被导电屏蔽层4吸收，避免了两发光单元001之间漏电。
如图16所示，图16示出了红(R)、绿(G)、蓝(B)三种子像素同时点亮的光谱图以及分别点亮的光谱图。与图3比较的相关技术的光谱图比较，可以看出，在本公开的显示面板中，当三种子像素分别点亮时，不同颜色的光明显减少，使得整个显示面板的色域提升。根据测算，该显示面板的色域指标(NTSC)可达到80％。
如图17所示，图17示出了红(R)、绿(G)、蓝(B)三种子像素的电压-亮度 曲线，其中，R、G和B曲线为本公开一实施方式中三种子像素的曲线，R-071、G-071和B-071是相关技术中三种子像素的曲线。图18-图20分别示出了红(R)、绿(G)、蓝(B)三种子像素的电压-色坐标曲线，其中，样本-R-x、样本-R-y，样本-G-x、样本-G-y、样本-B-x、样本-B-y曲线为本公开一实施方式中三种子像素的色坐标曲线；R-x、R-y，G-x、G-y、B-x、B-y曲线是相关技术中三种子像素的色坐标曲线。
由图18-图20可以看出，相关技术中的显示面板，在低压下(虚线左侧)出现明显的亮度和色坐标变化，且随电压变化伴随跳变和翻转问题，使得低灰阶下Gamma调试困难，较容易出现彩条问题。本公开实施方式的显示面板，各个单色色坐标随电压变化的幅度明显减小，有利于Gamma调试，且曲线的过度平滑，无跳变问题。
综上，可以看出，本公开的显示面板的一些实施方式可以防止漏电，从而避免串色问题。
本公开还提供一种显示面板的制造方法，该显示面板可以是上述任意实施方式的显示面板，如图4以及图21-图25所示，该制造方法可包括步骤S110-步骤S170，其中：
步骤S110、形成驱动背板；所述驱动背板包括衬底、至少一层走线层和平坦层，所述走线层设于所述衬底一侧；所述平坦层覆盖所述走线层。如图25所示。
步骤S120、在所述平坦层开设凹槽。如图20和图21所示。
步骤S130、在所述平坦层背离所述衬底的表面形成第一电极层，所述第一电极层包括间隔分布的多个第一电极；所述凹槽在所述平坦层上的正投影位于所述第一电极以外。如图24所示。
步骤S140、在所述平坦层背离所述衬底的表面形成露出各所述第一电极的像素定义层，所述像素定义层在所述凹槽处形成分隔槽。如图22和图23所示
步骤S150、至少在所述分隔槽内形成导电屏蔽层。如图21所示。
步骤S160、形成覆盖所述像素定义层、所述第一电极和所述导电屏蔽层的发光层，所述发光层在所述分隔槽处凹陷，且与所述导电屏蔽层的至少部分区域直接接触。如图4所示。
步骤S170、形成覆盖所述发光层的第二电极。如图4所示。
本公开实施方式的制造方法的各步骤中的结构已在上文显示面板的实施方式中进行了详细说明，在此不再详述。
在本公开的一些实施方式中，步骤S110，包括步骤S1110和步骤S1120，其中：
步骤S1110、形成一衬底。
步骤S1120、在所述衬底一侧形成至少一层走线层和覆盖所述走线层的平坦层； 所述第一电极层设于所述平坦层背离所述衬底的表面。
此外，本公开的制造方法还可包括步骤S180：
在所述第二电极背离驱动背板的一侧形成包括多个滤光部的彩膜层，各所述第一电极与各所述滤光部在垂直于所述衬底的方向上一一相对设置。如图4所示。
本公开还提供一种显示面板的制造方法，该显示面板可以是上述任意实施方式的显示面板，如图8以及图26所示，该制造方法可包括步骤S210-步骤S270，其中：
步骤S210、形成驱动背板，所述驱动背板包括衬底、至少一层走线层和平坦层，所述走线层设于所述衬底一侧；所述平坦层覆盖所述走线层；
步骤S220、在所述平坦层开设凹槽，所述凹槽在所述平坦层上的正投影位于所述第一电极以外；如图26所示。
步骤S230、至少在所述凹槽内形成导电屏蔽层；如图26所示。
步骤S240、在所述平坦层背离所述衬底的表面形成第一电极层，所述第一电极层包括间隔分布的多个第一电极；所述凹槽在所述平坦层上的正投影位于所述第一电极以外；
步骤S250、在所述平坦层背离所述衬底的表面形成露出各所述第一电极和所述导电屏蔽层的像素定义层，所述像素定义层在所述凹槽处形成分隔槽；
步骤S260、形成覆盖所述像素定义层、所述第一电极和所述导电屏蔽层的发光层，所述发光层在所述分隔槽处凹陷，且与所述导电屏蔽层的至少部分区域直接接触；
步骤S270、形成覆盖所述发光层的第二电极。
此外，本公开的制造方法还可包括步骤S280：
在所述第二电极背离驱动背板的一侧形成包括多个滤光部的彩膜层，各所述第一电极与各所述滤光部在垂直于所述衬底的方向上一一相对设置。如图8所示。
以上制造方法的具体细节已在上文的显示面板的实施方式中进行了详细说明，可以参考显示面板的实施方式，在此不再赘述。
需要说明的是，尽管在附图中以特定顺序描述了本公开中制造方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施方式还提供一种显示装置，包括上述任意实施方式的显示面板，显示面板的结构可参考上文中显示面的实施方式，在此不再赘述。本公开的显示装置可以是手机、平板电脑等具有图像显示功能的电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的 其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (26)

  1. 一种显示面板，其中，包括：
    驱动背板，包括衬底、至少一层走线层和平坦层，所述走线层设于所述衬底一侧；所述平坦层覆盖所述走线层，所述平坦层设有凹槽；
    第一电极层，设于所述平坦层背离所述衬底的表面，且包括间隔分布的多个第一电极；所述凹槽在所述平坦层上的正投影位于所述第一电极以外；
    像素定义层，设于所述平坦层背离所述衬底的表面，且露出各所述第一电极；所述像素定义层在所述凹槽处形成分隔槽；
    导电屏蔽层，至少部分设于所述凹槽内，且与所述第一电极绝缘设置；
    发光层，覆盖所述像素定义层、所述第一电极和所述导电屏蔽层，所述发光层在所述分隔槽处凹陷，且与所述导电屏蔽层的至少部分区域直接接触；
    第二电极，覆盖所述发光层。
  2. 根据权利要求1所述的显示面板，其中，所述像素定义层覆盖所述凹槽的底面，且覆盖所述凹槽的底面的所述像素定义层为所述分隔槽的底面；所述导电屏蔽层至少部分层叠于所述分隔槽的底面。
  3. 根据权利要求1所述的显示面板，其中，所述导电屏蔽层设于所述凹槽的底面；所述像素定义层至少露出所述导电屏蔽层的部分区域。
  4. 根据权利要求1所述的显示面板，其中，所述导电屏蔽层与所述第二电极连接。
  5. 根据权利要求4所述的显示面板，其中，所述分隔槽包括至少一个环形的槽体，一所述槽体围绕于一所述第一电极外；
    所述导电屏蔽层包括至少一个屏蔽环，一所述槽体内设有一所述屏蔽环；
    任一所述槽体及其内的所述屏蔽环围绕于同一所述第一电极外。
  6. 根据权利要求5所述的显示面板，其中，所述槽体的数量与所述第一电极的数量相同，且每个所述第一电极外均围绕一所述槽体，每个所述槽体内均设有一所述屏蔽环。
  7. 根据权利要求6所述的显示面板，其中，各所述槽体连通成一体结构，各所述屏蔽环连接成一体结构。
  8. 根据权利要求7所述的显示面板，其中，各所述屏蔽环与所述第二电极连接。
  9. 根据权利要求8所述的显示面板，其中，所述驱动背板包括像素区和位于所述像素区外的外围区；所述第一电极在所述驱动背板上的正投影位于所述像素区内；所述第二电极的边缘在所述驱动背板上的正投影位于所述外围区；
    所述导电屏蔽层还包括与所述屏蔽环连接的连接体，所述连接体在所述驱动背板上的正投影由所述像素区延伸至所述外围区；
    所述第二电极通过所述连接体与所述屏蔽环连接。
  10. 根据权利要求5所述的显示面板，其中，至少一部分所述屏蔽环通过贯穿所述发光层的第一过孔与所述第二电极连接，至少一所述第一过孔在所述平坦层的正投影位于相邻两所述第一电极之间。
  11. 根据权利要求5所述的显示面板，其中，至少一所述走线层包括与所述第二电极连接的连接部，所述屏蔽环通过穿入所述平坦层的第二过孔与所述连接部连接。
  12. 根据权利要求5所述的显示面板，其中，所述屏蔽环背离所述衬底的表面设有沿周向延伸的凸棱。
  13. 根据权利要求12所述的显示面板，其中，所述屏蔽环背离所述衬底的表面设有沿周向延伸的凹坑，所述凸棱和所述凹坑沿所述屏蔽环的径向分布。
  14. 根据权利要求1所述的显示面板，其中，所述导电屏蔽层的厚度小于所述凹槽的深度。
  15. 根据权利要求5所述的显示面板，其中，所述屏蔽环的宽度与所述凹槽的宽度之比小于4:5。
  16. 根据权利要求2所述的显示面板，其中，所述导电屏蔽层的厚度大于所述像素定义层的厚度。
  17. 根据权利要求1所述的显示面板，其中，所述导电屏蔽层位于所述第一电极靠近所述衬底的一侧。
  18. 根据权利要求2所述的显示面板，其中，所述分隔槽的底面包括中间区和位于所述中间区外的边缘区，所述导电屏蔽层在所述分隔槽的底面的正投影与所述中间区重合；所述边缘区的至少部分区域位于所述中间区背离所述衬底的一侧。
  19. 根据权利要求1所述的显示面板，其中，所述导电屏蔽层包括向背离所述衬底的方向依次层叠的第一导电层、第二导电层和第三导电层。
  20. 根据权利要求19所述的显示面板，其中，所述第一导电层和所述第三导电层的材料均为金属钛，所述第二导电层的材料为金属铝。
  21. 根据权利要求1-20任一项所述的显示面板，其中，所述分隔槽的深度为800μm-1000μm。
  22. 根据权利要求1-20任一项所述的显示面板，其中，所述发光层包括串联的多层发光子层，至少一所述发光子层通过电荷生成层与相邻的一所述发光子层串联。
  23. 根据权利要求1-20任一项所述的显示面板，其中，所述第二电极在所述分隔槽处凹陷形成凹陷区，所述凹陷区的底部对应于所述导电屏蔽层的区域向背离所述导电屏蔽层的方向凸起。
  24. 一种显示面板的制造方法，其中，包括：
    形成驱动背板，所述驱动背板包括衬底、至少一层走线层和平坦层，所述走线层设于所述衬底一侧；所述平坦层覆盖所述走线层；
    在所述平坦层开设凹槽；
    在所述平坦层背离所述衬底的表面形成第一电极层，所述第一电极层包括间隔分布的多个第一电极；所述凹槽在所述平坦层上的正投影位于所述第一电极以外；
    在所述平坦层背离所述衬底的表面形成露出各所述第一电极的像素定义层，所述像素定义层在所述凹槽处形成分隔槽；
    至少在所述分隔槽内形成导电屏蔽层；
    形成覆盖所述像素定义层、所述第一电极和所述导电屏蔽层的发光层，所述发光层在所述分隔槽处凹陷，且与所述导电屏蔽层的至少部分区域直接接触；
    形成覆盖所述发光层的第二电极。
  25. 一种显示面板的制造方法，其中，包括：
    形成驱动背板，所述驱动背板包括衬底、至少一层走线层和平坦层，所述走线层设于所述衬底一侧；所述平坦层覆盖所述走线层；
    在所述平坦层开设凹槽，所述凹槽在所述平坦层上的正投影位于所述第一电极以外；
    至少在所述凹槽内形成导电屏蔽层；
    在所述平坦层背离所述衬底的表面形成第一电极层，所述第一电极层包括间隔分布的多个第一电极；所述凹槽在所述平坦层上的正投影位于所述第一电极以外；
    在所述平坦层背离所述衬底的表面形成露出各所述第一电极和所述导电屏蔽层的像素定义层，所述像素定义层在所述凹槽处形成分隔槽；
    形成覆盖所述像素定义层、所述第一电极和所述导电屏蔽层的发光层，所述发光层在所述分隔槽处凹陷，且与所述导电屏蔽层的至少部分区域直接接触；
    形成覆盖所述发光层的第二电极。
  26. 一种显示装置，其中，包括权利要求1-24任一项所述的显示面板。
PCT/CN2021/113636 2021-08-19 2021-08-19 显示装置、显示面板及其制造方法 WO2023019529A1 (zh)

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