WO2023016282A1 - 一种多晶熔丝型非易失性存储器及其制作方法 - Google Patents

一种多晶熔丝型非易失性存储器及其制作方法 Download PDF

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Publication number
WO2023016282A1
WO2023016282A1 PCT/CN2022/108981 CN2022108981W WO2023016282A1 WO 2023016282 A1 WO2023016282 A1 WO 2023016282A1 CN 2022108981 W CN2022108981 W CN 2022108981W WO 2023016282 A1 WO2023016282 A1 WO 2023016282A1
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Prior art keywords
fuse
polysilicon
layer
polycrystalline
well region
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English (en)
French (fr)
Inventor
王浩
张楠
刘小红
黄勇
郭术明
李侠
龚才
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

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  • the invention belongs to the technical field of semiconductor integrated circuits, and relates to a polycrystalline fuse type nonvolatile memory and a manufacturing method thereof.
  • MTTF AJ -n e -Ea/kT
  • A a constant
  • J the current density
  • T the temperature
  • E a the activation energy of about 0.9eV
  • k the Boltzmann Constant
  • n a model parameter between 1 and 2. It is not difficult to see that the MTTF time is mainly related to the J current density, and the current density is affected by the cross-sectional area of the polycrystalline fuse and the current size, which is proportional to the current size and inversely proportional to the cross-sectional area.
  • FIG. 1 it is a common structure of a polycrystalline fuse type non-volatile memory unit, where fuse represents a polycrystalline fuse, M1 represents the first selection transistor, M2 represents the second selection transistor, and WWL represents the write word line terminal , RWL represents the read word line terminal, BL represents the bit line terminal and PL represents the power line terminal.
  • the structure is divided into two working modes: read mode and write mode.
  • the specific operation method is shown in Table 1. Among them, Program mode represents programming mode, Read mode represents reading mode, VDD represents operating voltage, Floating represents floating, VPP represents programming/erasing voltage, and sense amp represents comparison amplifier.
  • the core programming function unit is composed of the first selection transistor M1 and the polycrystalline fuse fuse.
  • the current will cause irreversible damage to the polycrystalline fuse fuse, and completely destroy the polycrystalline structure of the polycrystalline fuse fuse, making it change from a small resistance (about tens of ohms) to a larger resistance (several More than ten K ohms), a thousand times the resistance change, can be detected by the detection circuit.
  • FIG. 2 it is a layout of a polycrystalline nonvolatile memory cell, including an ion implantation region 101 , a metal extraction region 102 , a polycrystalline region 103 , and a contact region 104 .
  • a traditional fuse unit after trimming occurs close to both ends of the fuse (first end 105 and second end 106)
  • the chemical characteristics of fusing it will show diffusion outward, making the repair
  • the adjusted resistors will be connected together after being opened, causing the resistance to change from large to small, and the resistance value will become hundreds of ohms or several K ohms, resulting in uncontrollable data after adjustment.
  • the study on the working principle of the existing polycrystalline fuse type non-volatile memory unit found that the fusing position of the fuse device is close to the end of the fuse, and some are close to the middle position of the fuse.
  • the randomness of the position brings certain uncertainty to the final adjustment result: sometimes there will be tens of K ohms, sometimes there will be hundreds of K ohms, and sometimes there will be several M ohms, such
  • the distribution will reduce the current "0" and "1" window interval of the bit cell (bitcell), which will increase the difficulty of design and affect the stability of stored data.
  • the existing polycrystalline fuse type non-volatile memory unit has obvious traces of burning, which is not conducive to data protection.
  • the purpose of the present invention is to provide a polycrystalline fuse type non-volatile memory and its manufacturing method, which is used to solve the uncontrollable results caused by the uncertainty of the fuse position in the prior art , there is uncertainty in the resistance value distribution after fusing, resulting in large dispersion of results; fusing traces are obvious, and there is no shielding layer, which is not conducive to data confidentiality and other issues.
  • the present invention provides a polycrystalline fuse type nonvolatile memory, which includes a plurality of memory units, the memory cells include polycrystalline silicon fuses, and the polycrystalline silicon fuses include sequentially connected The first fuse section, the second fuse section and the third fuse section, the materials of the first fuse section and the three fuse sections all include doped polysilicon, and the material of the second fuse section includes Intrinsic polysilicon.
  • the length of the second fuse section is shorter than the length of the first fuse section, and the length of the second fuse section is shorter than the length of the third fuse section.
  • the second fuse segment is located at half of the polysilicon fuse or at the golden section point.
  • the memory unit further includes a conductive cover layer located above the polysilicon fuse, and the vertical projection of the conductive cover layer on the plane where the polysilicon fuse is located blocks the second fuse section;
  • the covering layer is made of conductive metal or polysilicon.
  • the memory unit further includes a first conductive material layer and an insulating medium layer, the first conductive material layer is located on the upper surface of the polysilicon fuse, and the insulating medium layer is located on the first conductive material layer On the upper surface, the conductive covering layer is located on the upper surface of the insulating medium layer.
  • the memory unit further includes a doped polysilicon connection part connected to both ends of the polysilicon fuse and a second conductive material layer electrically connected to the doped polysilicon connection part.
  • the memory unit further includes a substrate and an isolation dielectric layer on the substrate, and the polysilicon fuse is located on the isolation dielectric layer.
  • a first well region and a second well region are provided in the substrate, the first well region is located in the second well region, and the second fuse segment of the polysilicon fuse is in the
  • the vertical projection on the substrate is located in the first well region, the doping type of the first well region is opposite to the doping type of the substrate, and the doping type of the second well region is opposite to the doping type of the second well region
  • the doping type of the above substrate is the same.
  • the present invention also provides a method for manufacturing a polycrystalline fuse type nonvolatile memory, comprising the following steps:
  • the polysilicon fuse comprising a first fuse segment, a second fuse segment and a third fuse segment connected in sequence, the Materials of the first fuse section and the three fuse sections include doped polysilicon, and materials of the second fuse section include intrinsic polysilicon.
  • performing ion implantation on the predetermined region of the intrinsic polysilicon layer includes: using a mask with at least an opening pattern of the first ion implantation region and an opening pattern of the second ion implantation region to perform the ion implantation.
  • the opening of the first ion implantation region exposes the first fuse segment
  • the opening of the second ion implantation region exposes the third fuse segment
  • the second fuse segment is covered by the mask cover.
  • the following steps are also included: forming a first conductive material layer on the upper surface of the intrinsic polysilicon layer, forming an insulating dielectric layer on the upper surface of the first conductive material layer, forming a conductive covering layer on the insulating the upper surface of the dielectric layer.
  • the method further includes the following steps: providing a substrate, forming an isolation dielectric layer on the substrate, and the intrinsic polysilicon layer is formed on the isolation dielectric layer.
  • the following steps are further included: forming a first well region and a second well region in the substrate, the first well region is located in the second well region, and the first well region of the polysilicon fuse is The vertical projection of the two fuse segments on the substrate is located in the first well region, the doping type of the first well region is opposite to the doping type of the substrate, and the doping type of the second well region is The doping type is the same as that of the substrate.
  • the polycrystalline fuse type nonvolatile memory of the present invention and its manufacturing method utilize ion implantation to produce a sandwich polycrystalline region during the polycrystalline doping process, that is, low-resistance polycrystalline region+intrinsic
  • This structure can effectively control the programming position of the memory cell, so that the fusing point does not occur at both ends, and only occurs near the polycrystalline narrow point position, that is, the fusing position It is deterministic and position controllable, which can effectively improve the resistance value distribution of the memory cells after programming, make the discreteness of the cell resistance distribution after programming low, improve the robustness of the design, and improve the cell "0" and "1"
  • the design width of the window interval in the " state can effectively improve the resistance value distribution of the memory cells after programming, make the discreteness of the cell resistance distribution after programming low, improve the robustness of the design, and improve the cell "0" and "1"
  • this structure can also effectively improve the data stability of the memory cells before and after programming, and there will be no data loss caused by disconnection and reconnection.
  • the upper region of the structure cleverly utilizes the metal layer or the polycrystalline layer to shield the data storage part of the storage unit, effectively improving the data security of the storage unit.
  • FIG. 1 shows a polycrystalline fuse type nonvolatile memory cell structure in the prior art.
  • FIG. 2 shows a layout of a polymorphic nonvolatile memory cell in the prior art.
  • FIG. 3 shows a layout of memory cells of the polycrystalline fuse type nonvolatile memory of the present invention.
  • FIG. 4 is a cross-sectional view of a three-dimensional structure of a storage unit of the polycrystalline fuse type nonvolatile memory of the present invention.
  • FIG. 5 is a cross-sectional view of another three-dimensional structure of a storage unit of the polycrystalline fuse type nonvolatile memory of the present invention.
  • FIGS. 1 to 5 are only schematically illustrating the basic ideas of the present invention, and only components related to the present invention are shown in the diagrams rather than according to the present invention.
  • the number, shape and size of the components in the actual implementation can be changed arbitrarily in the type, quantity and proportion of the components in the actual implementation, and the layout of the components may also be more complicated.
  • This embodiment provides a polycrystalline fuse type nonvolatile memory, which includes a plurality of memory units, and the memory units include polycrystalline silicon fuses, and the polycrystalline silicon fuses include sequentially connected first fuse sections, second For the fuse section and the third fuse section, the materials of the first fuse section and the third fuse section both include doped polysilicon, and the material of the second fuse section includes intrinsic polysilicon.
  • one end of the second fuse section of the polysilicon fuse is connected to the first fuse section, and the other end of the second fuse section is connected to the third fuse section.
  • the resistance is low, while the second fuse section uses undoped intrinsic polysilicon, and the resistance is relatively high.
  • the heat will be concentrated on the second fuse segment with higher resistance, so that the programming position of the memory unit can be effectively controlled, so that the fusing point will not occur at the two ends of the polysilicon fuse. end, and only occurs near the position of the second fuse section, that is, the location of the fuse is deterministic and controllable, which can effectively improve the resistance value distribution of the memory cell after programming, and make the discreteness of the cell resistance distribution after programming relatively small. Low, improve the robustness of the design, and increase the window interval design width of the cell "0" and "1" states.
  • the length of the second fuse section is smaller than the length of the first fuse section
  • the length of the second fuse section is smaller than the length of the third fuse section
  • the relatively short second fuse section The length of the wire segment makes the second fuse segment act as a polysilicon pinch, where the polysilicon area has lower conductivity and is more prone to fusing and electromigration.
  • the fusing point can be effectively controlled here Narrow point, thus effectively improving the stability and reliability of the trimming results.
  • the second fuse segment can be located at half of the polysilicon fuse, at the golden section point (0.618 ratio point or 0.382 ratio point) or other suitable positions, so that the second fuse There are sufficient chemical reaction diffusion areas on both sides of the segment, which can avoid the phenomenon of disconnection and reconnection of the fuse device mentioned above, thereby effectively improving the data stability of the memory cell before and after programming, and preventing data loss caused by disconnection and reconnection Phenomenon.
  • FIG. 3 shows a layout of a memory cell of a polycrystalline fuse type nonvolatile memory, including a first ion implantation region 201 and a second ion implantation region 202 arranged at intervals, and includes a polysilicon layer 203 (not shown in FIG. 3, please refer to FIG.
  • the polysilicon layer 203 includes a first doped polysilicon connection part 203a, a polysilicon fuse 203b and a second doped polysilicon connection part 203c connected in sequence, and the first doped polysilicon connection part 203a is located in the first ion Implantation region 201, the second doped polysilicon connection portion 203c is located in the second ion implantation region 202, and the polysilicon fuse 203b includes a first fuse segment 203b1, a second fuse segment and a third fuse segment connected in sequence.
  • a wire segment 203b2 the first fuse segment 203b1 is located in the first ion implantation area 201, and the second fuse segment is located in the area between the first ion implantation area 201 and the second ion implantation area 202
  • the third fuse segment 203b2 is located in the second ion implantation region 202
  • the contact layer includes at least one first contact portion 204a located on the first doped polysilicon connection portion 203a and located on the at least one second contact portion 204b on the second doped polysilicon connection portion 203c
  • the second conductive material layer (205a, 205b) includes the second conductive material layer 205a on the first contact portion 204a and the The second conductive material layer 205b on the second contact portion 204b.
  • the second doped polysilicon connection portion 203c has a gradually changing width section, and the gradually changing width section is connected to the polysilicon fuse 203b and moves away from the polysilicon fuse 203b.
  • the upper width gradually increases.
  • the memory cell further includes a first conductive material layer 211 (not shown in FIG. 3 but shown in FIG. 4 ) on the upper surface of the polysilicon layer 203 to reduce the contact resistance of the polysilicon layer 203.
  • the first The material of the conductive material layer 211 may include metal silicide, polysilicon or other suitable conductive materials.
  • the first conductive material layer 211 is preferably made of metal silicide.
  • the exposed silicon surface of the polysilicon layer 203 forms a metal silicide, that is, the metal silicide material completely covers the polysilicon layer.
  • the memory unit further includes a conductive cover layer 206 located above the polysilicon fuse 203b, and the vertical projection of the conductive cover layer 206 on the plane where the polysilicon fuse 203b is located shields at least Describe the second fuse section.
  • the vertical projection of the conductive covering layer 206 on the plane where the polysilicon fuse 203b is located shields the entire polysilicon fuse 203b and shields the width gradient section of the second doped polysilicon connection portion 203c.
  • the material of the conductive covering layer 206 includes conductive metal or polysilicon, which can effectively shield the data storage part of the storage unit and effectively improve the data security of the storage unit.
  • the memory cell further includes a first well region 207 , and the vertical projection of the second fuse segment of the polysilicon fuse 203 b is located in the first well region 207 .
  • Fig. 4 and Fig. 5 both of which are sectional views of the three-dimensional structure of the storage unit. Compared with the description of the layout, the sectional view of the three-dimensional structure more clearly shows the actual situation of the solution of the present invention, wherein in Fig. 4 , the material of the conductive covering layer 206a is conductive metal, and in FIG. 5 , the material of the conductive covering layer 206b is polysilicon.
  • the memory cell further includes a substrate 208 and an isolation dielectric layer 209, the polysilicon layer 203 is located on the isolation dielectric layer 209, and the polysilicon layer 203 includes a first Doped polycrystalline region 203d, non-doped polycrystalline region 203e and second doped polycrystalline region 203f, wherein the first doped polycrystalline region 203d includes the first doped polycrystalline silicon connection portion 203a and the The first fuse section 203b1 of the polysilicon fuse 203b, the non-doped polycrystalline region 203e is used as the second fuse section of the polysilicon fuse 203b, and the second doped polycrystalline region 203f includes The third fuse section 203b2 of the polysilicon fuse 203b and the second doped polysilicon connection portion 203c.
  • a second well region 210 is provided in the substrate 208, the first well region 207 is located in the second well region 210, and the first well region 207 is opposite to the doping type of the second well region 210 , and the vertical projection of the second fuse segment of the polysilicon fuse 203 b on the substrate 208 is located in the first well region 207 .
  • the doping type of the first well region 207 is opposite to that of the substrate 208
  • the doping type of the second well region 210 is the same as that of the substrate 208 .
  • the memory cell further includes a first conductive material layer 211 and an insulating medium layer 212 , and the first conductive material layer 211 is located on the upper surface of the polysilicon layer 203 .
  • the insulating medium layer 212 at least completely covers the upper surface of the first conductive layer 211, and the second conductive material layer 205a is connected to the first conductive material layer 205a through the first contact portion 204a penetrating through the insulating medium layer 212.
  • the layer 211 is electrically connected, and the second conductive material layer 205 b is electrically connected to the first conductive layer 211 through the second contact portion 204 b penetrating through the insulating medium layer 212 .
  • the upper surface of the insulating medium layer 212 is provided with a conductive covering layer (206a, 206b).
  • the conductive covering layer 206a made of conductive metal extends above the second conductive material layer 205a and passes through the third contact portion 213 penetrating through the insulating medium layer 212 and the first The two conductive material layers 205a are electrically connected; as shown in FIG. 5 , the conductive covering layer 206b made of polysilicon is located between the second conductive material layer 205a and the second conductive material layer 205b in the horizontal direction.
  • the polysilicon fuse includes a first fuse segment, a second fuse segment, and a third fuse segment connected in sequence, and the first fuse segment and the third fuse segment
  • the material of the third fuse section includes doped polysilicon
  • the material of the second fuse section includes intrinsic polysilicon, wherein the second fuse section constitutes an intrinsic polysilicon narrow point, which can control the fusing point At this narrow point, the stability and reliability of the trimming results are effectively improved.
  • this structure can also effectively improve the data stability of the memory cells before and after programming, and there will be no data loss caused by disconnection and reconnection.
  • the upper region of the structure cleverly utilizes a conductive covering layer made of conductive metal or polysilicon to shield the data storage part of the storage unit, effectively improving the data security of the storage unit.
  • a method for fabricating a polycrystalline fuse type non-volatile memory including the following steps:
  • S2 performing ion implantation on a preset region of the intrinsic polysilicon layer to obtain a polysilicon fuse, the polysilicon fuse comprising a first fuse segment, a second fuse segment and a third fuse segment connected in sequence, Both the first fuse section and the third fuse section are made of doped polysilicon, and the second fuse section is made of intrinsic polysilicon.
  • the ion implantation is performed using a mask with at least the opening pattern of the first ion implantation region and the opening pattern of the second ion implantation region, and the opening of the first ion implantation region exposes The opening of the first fuse section and the second ion implantation area exposes the third fuse section, and the second fuse section is covered by the mask plate.
  • the length of the second fuse segment is smaller than the length of the first fuse segment, and the length of the second fuse segment is smaller than the length of the third fuse segment.
  • the second fuse section is located at one-half of the polysilicon fuse, at the golden section point, or at other suitable locations so that both sides of the second fuse section have sufficient chemical reaction diffusion area to avoid disconnection and reconnection, thereby effectively improving the data stability of memory cells before and after programming, and preventing data loss caused by disconnection and reconnection.
  • the method further includes the step of forming a conductive cover layer above the polysilicon fuse, and the vertical projection of the conductive cover layer on the plane where the polysilicon fuse is located shields the second fuse section.
  • the material of the conductive cover layer includes conductive metal or polysilicon, which can effectively cover the data storage part of the storage unit and effectively improve the data security of the storage unit.
  • the following steps are further included: forming a first conductive material layer on the upper surface of the intrinsic polysilicon layer, and forming an insulating medium layer on the upper surface of the first conductive material layer, wherein the conductive covering layer is formed on the upper surface of the insulating medium layer.
  • the first conductive material layer can reduce the contact resistance between the polysilicon and the contact portion.
  • a doped polysilicon connection part connected to both ends of the polysilicon fuse is also obtained, so that the doped polysilicon connection part is connected to the polysilicon An electrical signal is applied across the fuse.
  • the method further includes forming a second conductive material layer electrically connected to the doped polysilicon connection portion.
  • the method further includes the following steps: providing a substrate, forming an isolation dielectric layer on the substrate, and the intrinsic polysilicon layer is formed on the isolation dielectric layer.
  • the following steps are further included: forming a first well region and a second well region in the substrate, the first well region is located in the second well region, and the second well region of the polysilicon fuse
  • the vertical projection of the fuse section on the substrate is located in the first well region, the doping type of the first well region is opposite to the doping type of the substrate, and the doping type of the second well region is The heterotype is the same as the doping type of the substrate.
  • the polycrystalline fuse type nonvolatile memory and its manufacturing method of the present invention utilizes ion implantation to produce a sandwich polycrystalline region during the polycrystalline doping process, that is, a low-resistance polycrystalline region + this
  • the structure of polycrystalline narrow point + low-resistance polycrystalline region, this structure can effectively control the programming position of the memory cell, so that the fusing point does not occur at both ends, and only occurs near the polycrystalline narrow point position, that is, fusing
  • the position is deterministic and controllable, which can effectively improve the resistance value distribution of the memory cell after programming, make the discreteness of the cell resistance distribution after programming low, improve the robustness of the design, and improve the cell "0" and The design width of the window interval in the "1" state.
  • this structure can also effectively improve the data stability of the memory cells before and after programming, and there will be no data loss caused by disconnection and reconnection.
  • the upper region of the structure cleverly utilizes the metal layer or the polycrystalline layer to shield the data storage part of the storage unit, effectively improving the data security of the storage unit. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

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Abstract

本发明提供一种多晶熔丝型非易失性存储器及其制作方法，该存储器包括多个存储器单元，存储器单元包括多晶硅熔丝，多晶硅熔丝包括依次相连的第一、第二及第三熔丝段，第一及第三熔丝段的材质均包括掺杂多晶硅，第二熔丝段的材质包括本征多晶硅。本发明利用离子注入在多晶的掺杂过程中产生了一个三明治的多晶区域，即低阻多晶区+本征多晶狭点+低阻多晶区的结构，此结构可有效控制存储器单元的编程位置，熔断位置具有确定性，位置可控，可有效改善存储器单元编程后的阻值分布。此结构还可有效改善存储器单元编程前后的数据稳定性，避免因断而复连导致的数据丢失现象。此外，此结构上层区域利用导电覆盖层遮挡存储单元的数据存储部分，可提高数据保密性。

Description

一种多晶熔丝型非易失性存储器及其制作方法
相关申请的交叉引用
本申请要求于2021年8月9日提交中国专利局、申请号为202110908421.4、发明名称为“一种多晶熔丝型非易失性存储器及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于半导体集成电路技术领域，涉及一种多晶熔丝型非易失性存储器及其制作方法。
背景技术
利用多晶熔丝修调芯片电参数，是一种常见的降低工艺波动对电路性能参数影响的方法。随着工艺特征尺寸的缩小，多晶熔丝变得更加容易修调，多晶熔丝型非易失性存储器单元修调技术逐渐发展成为一种可以进行封装后修调的技术，其更易于集成，无需特殊器件，无需增加层次，和逻辑工艺完全兼容，在深亚微米制程中得到了极为广泛的应用。在公式MTTF＝AJ -ne -Ea/kT中，MTTF是平均熔断时间，A是一个常数，J是电流密度，T是温度，E a是约0.9eV的活化能量，k是玻尔兹曼常量，n是一个在1到2之间的模型参数。不难看出，MTTF时间主要和J电流密度有关，而电流密度又受多晶熔丝的横截面积以及电流大小影响，与电流大小成正比，与横截面积成反比。
如图1所示，为多晶熔丝型非易失性存储器单元的常见结构，其中，fuse代表多晶熔丝、M1代表第一选择管，M2代表第二选择管，WWL代表写字线端、RWL代表读字线端、BL代表位线端及PL代表电源线端。该结构分为两种工作模式：读模式、写模式。具体操作方式见表1，其中，Program mode代表编程模式，Read mode代表读模式，VDD代表工作电压，Floating代表悬空，VPP代表编程/擦除电压，sense amp代表比较放大器。其中，在编程模式中第一选择管M1会导通，第二选择M2会关断，在读模式中，第一选择管M1会关断，第二选择M2会导通。其中，核心的编程功能单元由第一选择管M1和多晶熔丝fuse组成，当第一选择管M1开启时，编程电流会从多晶熔丝fuse和第一选择管M1上流过，一个恰到好处的电流会对多晶熔丝fuse造成不可恢复的损伤，将多晶熔丝fuse的多晶结构彻底破坏，使之从一个较小的电阻(约几十欧姆)变化成为较大的电阻(几十K欧姆 以上)，一千倍的电阻变化，可以使用检测电路将其检测出来。
  WWL RWL BL PL
Program mode VDD 0 Floating VPP
Read mode 0 VDD sense amp 0
表1
如图2所示，为多晶型非易失性存储器单元的一种版图，包括离子注入区101、金属引出区102、多晶区103，接触区域104。实际研究发现，传统的熔丝单元当修调后的烧毁点发生在接近熔丝两端(第一端105和第二端106)时，由于熔断的化学特性，会往外呈现扩散性，使得修调后的电阻有一定几率会在开路后又连接在一起，导致电阻由大变小，阻值变成几百欧姆或几K欧姆，从而导致修调后的数据不可控。
另外，对已有的多晶熔丝型非易失性存储器单元的工作原理研究发现，熔丝器件的熔断位置，有的接近熔丝的端头，有的接近熔丝的中间位置，具有熔断位置的随机性，这样对最终的修调结果带来一定的不确定性：有时候会有几十K欧姆，有时候会有几百K欧姆，有时候会有几M欧姆不等，这样的分布会带来位单元(bitcell)的电流“0”和“1”窗口区间变小，会增加设计的难度，以及影响存储数据的稳定性。另外，现有的多晶熔丝型非易失性存储器单元，烧断的痕迹比较明显，不利于数据保护。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种多晶熔丝型非易失性存储器及其制作方法，用于解决现有技术中熔断位置存在不确定性导致结果不可控，熔断后的阻值分布存在不确定性导致结果离散性较大；熔断痕迹明显，且无遮挡层，不利于数据的保密等问题。
为实现上述目的及其他相关目的，本发明提供一种多晶熔丝型非易失性存储器，其包括多个存储器单元，所述存储器单元包括多晶硅熔丝，所述多晶硅熔丝包括依次相连的第一熔丝段、第二熔丝段及第三熔丝段，所述第一熔丝段及所述三熔丝段的材质均包括掺杂多晶硅，所述第二熔丝段的材质包括本征多晶硅。
可选地，所述第二熔丝段的长度小于所述第一熔丝段的长度，所述第二熔丝段的长度小于所述第三熔丝段的长度。
可选地，所述第二熔丝段位于所述多晶硅熔丝的二分之一处或黄金分割点处。
可选地，所述存储器单元还包括位于所述多晶硅熔丝上方的导电覆盖层，所述导电覆盖层在所述多晶硅熔丝所在平面的垂直投影遮挡所述第二熔丝段；所述导电覆盖层的材质 包括导电金属或多晶硅。
可选地，所述存储器单元还包括第一导电材料层及绝缘介质层，所述第一导电材料层位于所述多晶硅熔丝的上表面，所述绝缘介质层位于的第一导电材料层的上表面，所述导电覆盖层位于所述绝缘介质层的上表面。
可选地，所述存储器单元还包括连接于所述多晶硅熔丝两端的掺杂多晶硅连接部及与所述掺杂多晶硅连接部电连接的第二导电材料层。
可选地，所述存储器单元还包括衬底及位于所述衬底上的隔离介质层，所述多晶硅熔丝位于所述隔离介质层上。
可选地，所述衬底中设有第一阱区及第二阱区，所述第一阱区位于所述第二阱区中，所述多晶硅熔丝的所述第二熔丝段在所述衬底上的垂直投影位于所述第一阱区内，所述第一阱区的掺杂类型与所述衬底的掺杂类型相反，所述第二阱区的掺杂类型与所述衬底的掺杂类型相同。
本发明还提供一种多晶熔丝型非易失性存储器的制作方法，包括以下步骤：
形成本征多晶硅层；
对所述本征多晶硅层的预设区域进行离子注入，以得到多晶硅熔丝，所述多晶硅熔丝包括依次相连的第一熔丝段、第二熔丝段及第三熔丝段，所述第一熔丝段及所述三熔丝段的材质均包括掺杂多晶硅，所述第二熔丝段的材质包括本征多晶硅。
可选地，所述对所述本征多晶硅层的预设区域进行离子注入包括：利用至少带有第一离子注入区的开口图形和第二离子注入区的开口图形的掩膜版进行所述离子注入，所述第一离子注入区开口露出所述第一熔丝段，所述第二离子注入区开口露出所述第三熔丝段，所述第二熔丝段被所述掩膜版覆盖。
可选地，还包括以下步骤：形成第一导电材料层于所述本征多晶硅层的上表面，形成绝缘介质层于所述第一导电材料层的上表面，形成导电覆盖层于所述绝缘介质层的上表面。
可选地，还包括以下步骤：提供一衬底，形成隔离介质层于所述衬底上，所述本征多晶硅层形成于所述隔离介质层上。
可选地，还包括以下步骤：形成第一阱区及第二阱区于所述衬底中，所述第一阱区位于所述第二阱区中，所述多晶硅熔丝的所述第二熔丝段在所述衬底上的垂直投影位于所述第一阱区内，所述第一阱区的掺杂类型与所述衬底的掺杂类型相反，所述第二阱区的掺杂类型与所述衬底的掺杂类型相同。
如上所述，本发明的多晶熔丝型非易失性存储器及其制作方法利用离子注入在多晶的掺杂过程中产生了一个三明治的多晶区域，即低阻多晶区+本征多晶狭点+低阻多晶区的结 构，此种结构可以有效地控制存储器单元的编程位置，使熔断点不会发生在两端，并且只发生在多晶狭点位置附近，即熔断位置具有确定性，位置可控，从而可以有效改善存储器单元编程后的阻值分布，使编程后单元阻值分布的离散性较低，提高设计的鲁棒性，并提高单元“0”和“1”状态的窗口区间设计宽度。同时，此结构还可以有效改善存储器单元编程前后的数据稳定性，不会存在因断而复连导致的数据丢失现象。此外，此结构的上层区域巧妙利用了金属层或多晶层来遮挡存储单元的数据存储部分，有效提高了存储单元的数据保密性。
附图说明
图1显示为现有技术中一种多晶熔丝型非易失性存储器单元结构。
图2显示为现有技术中多晶型非易失性存储器单元的一种版图。
图3显示为本发明的多晶熔丝型非易失性存储器的存储单元的一种版图。
图4显示为本发明的多晶熔丝型非易失性存储器的存储单元的一种立体结构剖面图。
图5显示为本发明的多晶熔丝型非易失性存储器的存储单元的另一种立体结构剖面图。
元件标号说明
201                    第一离子注入区
202                    第二离子注入区
203                    多晶硅层
203a                   第一掺杂多晶硅连接部
203b                   多晶硅熔丝
203b1                  第一熔丝断
203b2                  第三熔丝断
203c                   第二掺杂多晶硅连接部
203d                   第一掺杂多晶区
203e                   非掺杂多晶区
203f                   第二掺杂多晶区
204a                   第一接触部
204b                   第二接触部
205a、205b             第二导电材料层
206、206a、206b        导电覆盖层
207                    第一阱区
208                    衬底
209                    隔离介质层
210                    第二阱区
211                    第一导电材料层
212                    绝缘介质层
213                    第三接触部
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示(请参阅图1至图5)仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本实施例中提供一种多晶熔丝型非易失性存储器，包括多个存储器单元，所述存储器单元包括多晶硅熔丝，所述多晶硅熔丝包括依次相连的第一熔丝段、第二熔丝段及第三熔丝段，所述第一熔丝段及所述第三熔丝段的材质均包括掺杂多晶硅，所述第二熔丝段的材质包括本征多晶硅。
作为示例，所述多晶硅熔丝的所述第二熔丝段的一端连接所述第一熔丝段，所述第二熔丝段的另一端连接所述第三熔丝段。
具体地，由于所述第一熔丝段及所述第三熔丝段进行了掺杂，电阻较低，而所述第二熔丝段采用未掺杂的本征多晶硅，电阻较高，当对所述多晶硅熔丝进行熔断操作时，发热将集中在电阻较高的第二熔丝段，从而可以有效地控制存储器单元的编程位置，使熔断点不会发生在所述多晶硅熔丝的两端，并且只发生在第二熔丝段的位置附近，即熔断位置具有确定性，位置可控，从而可以有效改善存储器单元编程后的阻值分布，使编程后单元阻值分布的离散性较低，提高设计的鲁棒性，并提高单元“0”和“1”状态的窗口区间设计 宽度。
作为示例，所述第二熔丝段的长度小于所述第一熔丝段的长度，所述第二熔丝段的长度小于所述第三熔丝段的长度，相对较短的第二熔丝段长度使得第二熔丝段作为一个多晶硅狭点，此处多晶区域具有更低的电导率，也更容易发生熔断和电迁移，通过形成特定区域，可以将熔断点有效地控制在此狭点上，从而有效地提高了修调结果的稳定性和可靠性。
作为示例，所述第二熔丝段可位于所述多晶硅熔丝的二分之一处、黄金分割点(0.618比例点或者0.382比例点)处或其它合适的位置，使所述第二熔丝段两侧都有足够的化学反应扩散区，可以避免前述提到的熔丝器件断而复连的现象，从而有效改善存储器单元编程前后的数据稳定性，防止因断而复连导致的数据丢失现象。
作为示例，请参阅图3，显示为多晶熔丝型非易失性存储器的存储单元的一种版图，包括间隔设置的第一离子注入区201与第二离子注入区202，并包括多晶硅层203(图3中未示出，请参见图4)、接触层及第二导电材料层(205a，205b)，其中，所述第一离子注入区201与第二离子注入区202之间形成狭缝；所述多晶硅层203包括依次相连的第一掺杂多晶硅连接部203a、多晶硅熔丝203b及第二掺杂多晶硅连接部203c，所述第一掺杂多晶硅连接部203a位于所述第一离子注入区201，所述第二掺杂多晶硅连接部203c位于所述第二离子注入区202，所述多晶硅熔丝203b包括依次相连的第一熔丝段203b1、第二熔丝段及第三熔丝段203b2，所述第一熔丝段203b1位于所述第一离子注入区201，所述第二熔丝段位于所述第一离子注入区201与所述第二离子注入区202之间的狭缝处，所述第三熔丝段203b2位于所述第二离子注入区202；所述接触层包括位于所述第一掺杂多晶硅连接部203a上的至少一个第一接触部204a及位于所述第二掺杂多晶硅连接部203c上的至少一个第二接触部204b；所述第二导电材料层(205a，205b)包括位于所述第一接触部204a上的第二导电材料层205a及位于所述第二接触部204b上的第二导电材料层205b。
作为示例，如图3所示，所述第二掺杂多晶硅连接部203c具有一宽度渐变段，所述宽度渐变段与所述多晶硅熔丝203b连接，并在远离所述多晶硅熔丝203b的方向上宽度逐渐增加。
作为示例，所述存储单元还包括位于多晶硅层203上表面的第一导电材料层211(图3中未图示，图4有图示)，以降低多晶硅层203的接触电阻，所述第一导电材料层211的材质可包括金属硅化物、多晶硅或其它合适的导电材料。本实施例中，所述第一导电材料层211优选采用金属硅化物，在形成所述金属硅化物的过程中，所述多晶硅层203露出的硅表面均形成金属硅化物，即所述金属硅化物完全覆盖所述多晶硅层。
作为示例，如图3所示，所述存储单元还包括位于所述多晶硅熔丝203b上方的导电 覆盖层206，所述导电覆盖层206在所述多晶硅熔丝203b所在平面的垂直投影至少遮挡所述第二熔丝段。本实施例中，所述导电覆盖层206在所述多晶硅熔丝203b所在平面的垂直投影遮挡整条所述多晶硅熔丝203b，并遮挡所述第二掺杂多晶硅连接部203c的宽度渐变段。所述导电覆盖层206的材质包括导电金属或多晶硅，可有效遮挡住存储单元的数据存储部分，有效提高存储单元的数据保密性。
作为示例，如图3所示，所述存储单元还包括第一阱区207，所述多晶硅熔丝203b的所述第二熔丝段的垂直投影位于所述第一阱区207内。
作为示例，请参阅图4及图5，均显示为所述存储单元的立体结构剖面图，相对于版图的说明，立体结构剖面图更清晰的展示了本发明方案的实际情况，其中图4中，导电覆盖层206a的材质采用导电金属，图5中，导电覆盖层206b的材质采用多晶硅。
具体地，如图4及图5所示，所述存储器单元还包括衬底208及隔离介质层209，所述多晶硅层203位于所述隔离介质层209上，且所述多晶硅层203包括第一掺杂多晶区203d、非掺杂多晶区203e及第二掺杂多晶区203f，其中，所述第一掺杂多晶区203d包括所述第一掺杂多晶硅连接部203a及所述多晶硅熔丝203b的所述第一熔丝段203b1，所述非掺杂多晶区203e作为所述多晶硅熔丝203b的所述第二熔丝段，所述第二掺杂多晶区203f包括所述多晶硅熔丝203b的所述第三熔丝段203b2及所述第二掺杂多晶硅连接部203c。
作为示例，如图4及图5所示，所述衬底208中设有第二阱区210，所述第一阱区207位于所述第二阱区210中，且所述第一阱区207与所述第二阱区210的掺杂类型相反，所述多晶硅熔丝203b的所述第二熔丝段在所述衬底208上的垂直投影位于所述第一阱区207内。所述第一阱区207的掺杂类型与所述衬底208的掺杂类型相反，所述第二阱区210的掺杂类型与所述衬底208的掺杂类型相同。
作为示例，如图4及图5所示，所述存储器单元还包括第一导电材料层211及绝缘介质层212，所述第一导电材料层211位于所述多晶硅层203的上表面。所述绝缘介质层212至少完全覆盖所述第一导电层211的上表面，所述第二导电材料层205a通过贯穿所述绝缘介质层212的所述第一接触部204a与所述第一导电层211电连接，所述第二导电材料层205b通过贯穿所述绝缘介质层212的所述第二接触部204b与所述第一导电层211电连接。所述绝缘介质层212的上表面设有导电覆盖层(206a，206b)。
作为示例，如图4所示，采用导电金属材质的所述导电覆盖层206a延伸至所述第二导电材料层205a上方并通过贯穿所述绝缘介质层212的第三接触部213与所述第二导电材料层205a电连接；如图5所示，采用多晶硅材质的所述导电覆盖层206b在水平方向上位于所述第二导电材料层205a与所述第二导电材料层205b之间。
需要指出的是，版图及立体结构的各种细节设计可以根据需要进行调整，不以图3、图4及图5所示为限。另外，图4及图5中所述绝缘介质层212未图示完整，实际上，接触部之间、不同导电层之间均设有绝缘介质。
本实施例的多晶熔丝型非易失性存储器中，多晶硅熔丝包括依次相连的第一熔丝段、第二熔丝段及第三熔丝段，所述第一熔丝段及所述第三熔丝段的材质均包括掺杂多晶硅，所述第二熔丝段的材质包括本征多晶硅，其中，所述第二熔丝段构成本征多晶狭点，能够将熔断点控制在此狭点上，有效地提高了修调结果的稳定性和可靠性。同时，此结构还可以有效改善存储器单元编程前后的数据稳定性，不会存在因断而复连导致的数据丢失现象。此外，此结构的上层区域巧妙利用了导电金属材质或多晶硅材质的导电覆盖层来遮挡存储单元的数据存储部分，有效提高了存储单元的数据保密性。
实施例二
本实施例中提供一种多晶熔丝型非易失性存储器的制作方法，包括以下步骤：
S1：形成本征多晶硅层；
S2：对所述本征多晶硅层的预设区域进行离子注入，以得到多晶硅熔丝，所述多晶硅熔丝包括依次相连的第一熔丝段、第二熔丝段及第三熔丝段，所述第一熔丝段及所述第三熔丝段的材质均包括掺杂多晶硅，所述第二熔丝段的材质包括本征多晶硅。
作为示例，在所述步骤S2中，利用至少带有第一离子注入区的开口图形和第二离子注入区的开口图形的掩膜版进行所述离子注入，所述第一离子注入区开口露出所述第一熔丝段，所述第二离子注入区开口露出所述第三熔丝段，所述第二熔丝段被所述掩膜版覆盖。
作为示例，所述第二熔丝段的长度小于所述第一熔丝段的长度，所述第二熔丝段的长度小于所述第三熔丝段的长度。
作为示例，所述第二熔丝段位于所述多晶硅熔丝的二分之一处、黄金分割点处或其它合适的位置以使所述第二熔丝段两侧都有足够的化学反应扩散区，以避免断而复连的现象，从而有效改善存储器单元编程前后的数据稳定性，防止因断而复连导致的数据丢失现象。
作为示例，还包括形成导电覆盖层于所述多晶硅熔丝上方的步骤，所述导电覆盖层在所述多晶硅熔丝所在平面的垂直投影遮挡所述第二熔丝段。所述导电覆盖层的材质包括导电金属或多晶硅，可有效遮挡住存储单元的数据存储部分，有效提高存储单元的数据保密性。
作为示例，还包括以下步骤：形成第一导电材料层于所述本征多晶硅层的上表面，形成绝缘介质层于所述第一导电材料层的上表面，其中，所述导电覆盖层形成于所述绝缘介 质层的上表面。第一导电材料层可以降低多晶硅与接触部之间的接触电阻。
作为示例，在对所述本征多晶硅层的预设区域进行离子注入时，还得到连接于所述多晶硅熔丝两端的掺杂多晶硅连接部，以通过所述掺杂多晶硅连接部在所述多晶硅熔丝两端施加电信号。
作为示例，还包括形成与所述掺杂多晶硅连接部电连接的第二导电材料层。
作为示例，还包括以下步骤：提供一衬底，形成隔离介质层于所述衬底上，所述本征多晶硅层形成于所述隔离介质层上。
作为示例，还包括以下步骤：形成第一阱区及第二阱区于所述衬底中，所述第一阱区位于所述第二阱区中，所述多晶硅熔丝的所述第二熔丝段在所述衬底上的垂直投影位于所述第一阱区内，所述第一阱区的掺杂类型与所述衬底的掺杂类型相反，所述第二阱区的掺杂类型与所述衬底的掺杂类型相同。
综上所述，本发明的多晶熔丝型非易失性存储器及其制作方法利用离子注入在多晶的掺杂过程中产生了一个三明治的多晶区域，即低阻多晶区+本征多晶狭点+低阻多晶区的结构，此种结构可以有效地控制存储器单元的编程位置，使熔断点不会发生在两端，并且只发生在多晶狭点位置附近，即熔断位置具有确定性，位置可控，从而可以有效地改善存储器单元编程后的阻值分布，使编程后单元阻值分布的离散性较低，提高设计的鲁棒性，并提高单元“0”和“1”状态的窗口区间设计宽度。同时，此结构还可以有效改善存储器单元编程前后的数据稳定性，不会存在因断而复连导致的数据丢失现象。此外，此结构的上层区域巧妙利用了金属层或多晶层来遮挡存储单元的数据存储部分，有效提高了存储单元的数据保密性。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. 一种多晶熔丝型非易失性存储器，其特征在于：包括多个存储器单元，所述存储器单元包括多晶硅熔丝，所述多晶硅熔丝包括依次相连的第一熔丝段、第二熔丝段及第三熔丝段，所述第一熔丝段及所述三熔丝段的材质均包括掺杂多晶硅，所述第二熔丝段的材质包括本征多晶硅。
  2. 根据权利要求1所述的多晶熔丝型非易失性存储器，其特征在于：所述第二熔丝段的长度小于所述第一熔丝段的长度，所述第二熔丝段的长度小于所述第三熔丝段的长度。
  3. 根据权利要求1所述的多晶熔丝型非易失性存储器，其特征在于：所述第二熔丝段位于所述多晶硅熔丝的二分之一处或黄金分割点处。
  4. 根据权利要求1所述的多晶熔丝型非易失性存储器，其特征在于：所述存储器单元还包括位于所述多晶硅熔丝上方的导电覆盖层，所述导电覆盖层在所述多晶硅熔丝所在平面的垂直投影遮挡所述第二熔丝段；所述导电覆盖层的材质包括导电金属或多晶硅。
  5. 根据权利要求4所述的多晶熔丝型非易失性存储器，其特征在于：所述存储器单元还包括第一导电材料层及绝缘介质层，所述第一导电材料层位于所述多晶硅熔丝的上表面，所述绝缘介质层位于的第一导电材料层的上表面，所述导电覆盖层位于所述绝缘介质层的上表面。
  6. 根据权利要求4所述的多晶熔丝型非易失性存储器，其特征在于：所述存储器单元还包括连接于所述多晶硅熔丝两端的掺杂多晶硅连接部及与所述掺杂多晶硅连接部电连接的第二导电材料层。
  7. 根据权利要求6所述的多晶熔丝型非易失性存储器，其特征在于：所述导电覆盖层在所述多晶硅熔丝所在平面的垂直投影遮挡整条所述多晶硅熔丝，并遮挡所述掺杂多晶硅连接部的宽度渐变段。
  8. 根据权利要求1所述的多晶熔丝型非易失性存储器，其特征在于：所述存储器单元还包括衬底及位于所述衬底上的隔离介质层，所述多晶硅熔丝位于所述隔离介质层上。
  9. 根据权利要求8所述的多晶熔丝型非易失性存储器，其特征在于：所述衬底中设有第一阱区及第二阱区，所述第一阱区位于所述第二阱区中，所述多晶硅熔丝的所述第二熔丝段在所述衬底上的垂直投影位于所述第一阱区内，所述第一阱区的掺杂类型与所述衬底的掺杂类型相反，所述第二阱区的掺杂类型与所述衬底的掺杂类型相同。
  10. 一种多晶熔丝型非易失性存储器的制作方法，其特征在于，包括以下步骤：
    形成本征多晶硅层；
    对所述本征多晶硅层的预设区域进行离子注入，以得到多晶硅熔丝，所述多晶硅熔丝包括依次相连的第一熔丝段、第二熔丝段及第三熔丝段，所述第一熔丝段及所述三熔丝段的材质均包括掺杂多晶硅，所述第二熔丝段的材质包括本征多晶硅。
  11. 根据权利要求10所述的多晶熔丝型非易失性存储器的制作方法，其特征在于，所述对所述本征多晶硅层的预设区域进行离子注入包括：利用至少带有第一离子注入区的开口图形和第二离子注入区的开口图形的掩膜版进行所述离子注入，所述第一离子注入区开口露出所述第一熔丝段，所述第二离子注入区开口露出所述第三熔丝段，所述第二熔丝段被所述掩膜版覆盖。
  12. 根据权利要求10所述的多晶熔丝型非易失性存储器的制作方法，其特征在于，还包括以下步骤：形成第一导电材料层于所述本征多晶硅层的上表面，形成绝缘介质层于所述第一导电材料层的上表面，形成导电覆盖层于所述绝缘介质层的上表面。
  13. 根据权利要求10所述的多晶熔丝型非易失性存储器的制作方法，其特征在于，还包括以下步骤：提供一衬底，形成隔离介质层于所述衬底上，所述本征多晶硅层形成于所述隔离介质层上。
  14. 根据权利要求13所述的多晶熔丝型非易失性存储器的制作方法，其特征在于，还包括以下步骤：形成第一阱区及第二阱区于所述衬底中，所述第一阱区位于所述第二阱区中，所述多晶硅熔丝的所述第二熔丝段在所述衬底上的垂直投影位于所述第一阱区内，所述第一阱区的掺杂类型与所述衬底的掺杂类型相反，所述第二阱区的掺杂类型与所述衬底的掺杂类型相同。
  15. 根据权利要求10所述的多晶熔丝型非易失性存储器的制作方法，其特征在于，还包括以下步骤：在对所述本征多晶硅层的预设区域进行离子注入时，得到连接于所述多晶硅熔丝两端的掺杂多晶硅连接部；形成与所述掺杂多晶硅连接部电连接的第二导电材料层。
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