WO2023011367A1 - 一种存储芯片及堆叠芯片 - Google Patents

一种存储芯片及堆叠芯片 Download PDF

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Publication number
WO2023011367A1
WO2023011367A1 PCT/CN2022/109157 CN2022109157W WO2023011367A1 WO 2023011367 A1 WO2023011367 A1 WO 2023011367A1 CN 2022109157 W CN2022109157 W CN 2022109157W WO 2023011367 A1 WO2023011367 A1 WO 2023011367A1
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memory
chip
pins
circuit
repair
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PCT/CN2022/109157
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English (en)
French (fr)
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俞冰
段会福
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西安紫光国芯半导体有限公司
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Publication of WO2023011367A1 publication Critical patent/WO2023011367A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Definitions

  • the present application relates to the technical field of memory, and in particular to a memory chip and stacked chips.
  • the clock frequency and data throughput rate of the processor are increasing at an unimaginable speed, but the access speed and data throughput rate of the memory (such as DRAM) are much slower.
  • the large difference between the access speed of the storage module and the calculation speed of the processor greatly limits the overall operating speed of the system, that is, the problem of the storage wall becomes more and more serious, and the speed of calculation, storage, and I/O is increasingly mismatched. Therefore, there is an urgent need to improve the access speed and data throughput of the memory.
  • the embodiments of the present application provide a memory chip and a stacked chip, which can effectively improve the access speed and data width of the memory.
  • the embodiment of the present application provides a memory chip, including:
  • a plurality of memory array modules each of which is independently provided with operation pins leading to the outside of the memory chip;
  • the operation pins include: control pins and data pins, the control pins are used to receive control signals for reading or writing control to the memory cells to be accessed in the corresponding memory array module,
  • the data pin is used to read or write data from the storage unit to be accessed.
  • the storage array module includes: a test circuit, the test circuit is connected to the drive circuit in the storage array module, and when the test circuit receives a test signal, the drive circuit The failure test is performed on the corresponding storage units in the storage array module, and the test result is output.
  • operation pins further include: test pins connected to the test circuit for receiving the test signal sent from outside the memory chip.
  • the storage array module includes: a repairing circuit, the repairing circuit is connected to the driving circuit in the storage array module, and when the repairing circuit receives a repairing signal, the driving circuit The failed storage unit in the storage array module is repaired.
  • the operation pin further includes: a repair pin connected to the repair circuit for receiving the repair signal sent from outside the memory chip.
  • the repair pin includes: a repair enable pin and a repair control pin; the repair enable pin and the repair control pin are connected to the repair circuit; wherein, the repair enable pin Used to control the opening of the repair circuit, the repair control pin is used to receive a repair control signal, and the repair control signal includes the address of the failed memory unit to be repaired.
  • the repair circuit includes an eFuse module.
  • the memory chip further includes: an off-chip power supply pin, which is connected to each of the memory array modules, and is used to connect to a power generation circuit arranged outside the memory chip, so as to utilize The power generation circuit supplies power to the storage array module.
  • the memory chip further includes: a power generation circuit and on-chip power pins, the on-chip power pins are connected to the power generation circuit, and the power generation circuit is connected to the memory array module; On-chip power supply pins are used to input the chip operating voltage and common ground voltage to the power generation circuit; the power generation circuit is used to generate the power supply signal required by the memory array module based on the externally input chip operating voltage and common ground voltage .
  • control pins include control command pins and address pins
  • control signals include control command signals and address signals.
  • the control command pin is used to receive the control command signal of the corresponding memory array module
  • the address pin is used to receive the address signal of the storage unit to be accessed.
  • control command pins include: row operation enable pins, column operation enable pins, read and write control pins, and data bit selection pins.
  • the address pins include row address pins and column address pins.
  • the storage capacity of the storage chip is 1G, and the storage chip includes 16 mutually independent storage array modules, the storage capacity of each storage array module is 64M, and the storage capacity of each storage array module is The data pins include 64-bit data input and output ports.
  • the storage chip is a dynamic random access memory, or a flash memory.
  • the embodiment of the present application also provides a stacked chip, including a logic unit and a storage unit, the logic unit is directly connected to the storage unit;
  • the storage unit includes: a plurality of storage array modules, each of which The memory array modules are all independently provided with operation pins leading to the outside of the memory chip; wherein, the operation pins include: control pins and data pins, and the control pins are used to receive corresponding memory A control signal for reading or writing control of the storage unit to be accessed in the array module, and the data pin is used to read or write data from the storage unit to be accessed.
  • logic chip and the memory chip are packaged together in a 3D stacking manner.
  • the storage array module includes: a test circuit, the test circuit is connected to the drive circuit in the storage array module, and when the test circuit receives a test signal, the drive circuit The failure test is performed on the corresponding storage units in the storage array module, and the test result is output.
  • the storage array module includes: a repairing circuit, the repairing circuit is connected to the driving circuit in the storage array module, and when the repairing circuit receives a repairing signal, the driving circuit The failed storage unit in the storage array module is repaired.
  • the memory chip further includes: an off-chip power supply pin, which is connected to each of the memory array modules, and is used to connect to a power generation circuit arranged outside the memory chip, so as to utilize The power generation circuit supplies power to the storage array module.
  • the memory chip further includes: a power generation circuit and on-chip power pins, the on-chip power pins are connected to the power generation circuit, and the power generation circuit is connected to the memory array module; On-chip power supply pins are used to input the chip operating voltage and common ground voltage to the power generation circuit; the power generation circuit is used to generate the power supply signal required by the memory array module based on the externally input chip operating voltage and common ground voltage .
  • the memory chip and the stacked chip provided by the embodiment of the present application, by independently setting operation pins for each memory array module to the outside of the chip, including control pins and data pins, can make the control involved in the access operation
  • the signal and data signal are directly input or output through their respective operation pins, so as to complete the access operation of each memory array module independently, which effectively simplifies the signal control process in the memory chip and is conducive to improving the data of the memory chip.
  • Access speed and increase the data width that can be read or written at one time.
  • the chip area is also significantly reduced.
  • FIG. 1 shows a schematic diagram of a chip structure of an exemplary dynamic random access memory
  • Fig. 2 shows a schematic structural diagram of a memory chip provided by the first aspect of the embodiment of this specification
  • FIG. 3 shows a schematic structural diagram of a test circuit provided by an embodiment of this specification
  • FIG. 4 shows a schematic structural diagram of a repair circuit provided by an embodiment of this specification
  • FIG. 5 shows a schematic structural diagram of a stacked chip provided by the second aspect of the embodiment of the present specification.
  • FIG. 1 is a schematic diagram of a 1G double data rate (Double Data Rate, DDR3 for short) dynamic random access memory (Dynamic Random Access Memory, DRAM for short) chip structure.
  • the (splitbank) capacity is 64M, and the division of these two sub-storage array modules is externally insensitive and share the same bank address.
  • bank0 includes splitbank0 and splitbank0'
  • bank1 includes splitbank1 and splitbank1'
  • bank7 includes splitbank7 and splitbank7'.
  • bank0-bank7 share the row scanning line
  • four splitbanks share the data line, that is, splitbank0-splitbank3 share the data line
  • splitbank0'-splitbank3' share the data line
  • splitbank4-splitbank7 share the data line
  • splitbank4'-splitbank7' share the data line.
  • the inventor has conducted long-term research on the data access process of the memory chip shown in FIG. 1 and found that the multi-level control circuits in the memory greatly limit the access speed of the memory.
  • the following mainly takes the activation operation (ACTIVE) and read operation as examples for illustration:
  • the external system When performing ACTIVE operation, first, the external system sends the first address information and the first command information to the global control module (Golbal ctrl) in the chip, and the global control module decodes the first address information to generate bank selection information bnksel ⁇ 7:0> and the row address information shared by each memory array module (gradd ⁇ 13:0>), where bnksel ⁇ 7:0> is the activation operation bank address information, which is used to determine the bank targeted for this activation operation.
  • the corresponding memory array module will activate the word line corresponding to the corresponding row address according to the first command information and amplify the data on the word line to wait for the read or write operation.
  • the external system When performing a read operation, the external system sends the second address information and the second command information to the above-mentioned global control module, and the global control module decodes the second address information to generate the read operation bank information cas ⁇ 7:0>, read Write information pawcol and data mask information DM ⁇ 7:0> and column address information gcadd ⁇ 6:0> shared by each bank.
  • cas ⁇ 7:0> is the bank address information of the read operation, which is used to determine the bank targeted by this read operation, pawcol is used to control whether to read data or write data, and the data mask information is used to select the data bits to be written.
  • the corresponding bank will read a total of 128 bits of data, each splitbank will read 64 bits of data, and the read data rwdl ⁇ 63:0> will be sent to the data processing dpcross module through the data lines shared by the four splitbanks.
  • the 128-bit data is divided into 8 pieces of data (16 bits each) by the dpcross module, and then the OCD module is driven by the output data to send each 16-bit data to the external data pin DQ ⁇ 15:0> for output.
  • the DRAM command input needs to be decoded by the global control module to reach the corresponding bank, and the read data also needs to undergo multi-level processing before it can be output to the outside of the chip, resulting in memory access Speed and data throughput are difficult to improve.
  • the embodiment of this specification provides a memory chip and a stacked chip.
  • the control signals and data signals involved in the access operation are Through the direct input or output of their respective operation pins, the access operation of each memory array module is completed independently, which effectively simplifies the signal control process in the memory chip, and is conducive to improving the data access speed of the memory and the data width.
  • the storage chip provided by the embodiment of this specification can be a dynamic random access memory (Dynamic Random Access Memory, DRAM), or it can also be other types of storage chips, such as flash memory such as NAND flash memory, etc. This is not limited.
  • DRAM Dynamic Random Access Memory
  • flash memory such as NAND flash memory
  • the embodiment of this specification provides a memory chip 20 , including: a plurality of memory array modules 200 .
  • Each memory array module 200 is independently provided with operation pins leading out of the memory chip 20 . In this way, the control and data signals involved in the access operation of each storage array module 200 can be directly input or output through the respective operation pins.
  • a memory array module 200 is a bank in the memory chip 20, and the memory chip 20 includes M banks, where M is an integer greater than or equal to 2, and each bank is provided with an operation leading to the outside of the chip. pins, the memory chip 20 includes M groups of operating pins. It should be noted that the specific number of M is determined according to the capacity of the memory chip 20 and the capacity of each bank, and the number of banks shown in FIG. 2 is only for illustration.
  • the memory chip 20 includes 16 mutually independent banks, such as bank0 to bank15 shown in FIG. 2 , and the storage capacity of each bank is 64M.
  • the operation pin that bank0 leads to the outside of the chip is represented as p0
  • the operation pin that bank1 leads to the outside of the chip is represented as p1
  • the operation pin that bank2 leads to the outside of the chip is represented as p2
  • bank15 leads to the outside of the chip
  • the operation pin is denoted as p15.
  • each memory array module 200 includes a memory cell array and driving circuits such as row (Row) circuits and column (column) circuits.
  • the operation pins may include: control pins and data pins. Both the control pins and the data pins are connected to the drive circuit of the corresponding memory array module 200 .
  • the control pin is used to receive a control signal for controlling the reading or writing of the storage unit to be accessed in the corresponding memory array module, and send the control signal to the driving circuit, so as to control the reading or writing of the storage unit to be accessed.
  • the data pin is used to read or write data from the storage unit to be accessed. Wherein, the storage unit to be accessed is the storage unit targeted by the storage or read operation.
  • each memory array module 200 can have its own control signal transmission port and data signal transmission port, and can complete the access operation to each memory array module independently, reducing the signal control circuit in the memory chip 20, and effectively It is beneficial to improve the access speed and data width of the memory.
  • control pin includes a control command pin and an address pin, and correspondingly, the above-mentioned control signal includes a control command signal and an address signal.
  • the control command pin is used to receive the control command signal of the corresponding storage array module 200 ;
  • the address pin is used to receive the address signal of the storage unit to be accessed in the corresponding storage array module 200 .
  • control command pins may include: row operation enable pins, column operation enable pins, read/write control pins, and data bit selection pins.
  • the row operation enable pin can be expressed as bnksel
  • the column operation enable pin can be expressed as cas
  • the read and write control pin can be expressed as pawcol
  • the data bit selection pin can be expressed as dm ⁇ k:0>.
  • bnksel is used to enable row addressing operations
  • cas is used to enable column addressing operations
  • pawcol is used for read and write control
  • dm ⁇ k:0> is used to select the data bits involved in the write operation, through dm ⁇ k: 0> to determine which data bits to write.
  • control command pins can also include more or fewer pins, for example, the number of pins can be reduced by multiplexing some pins. The embodiment does not limit this.
  • the number of address pins is determined according to the number of row and column address lines of each memory array module 200 .
  • the address pins may include independent row address pins and column address pins.
  • the storage capacity of each memory array module 200 is 64M, and each memory array module 200 can be set with 13 row address pins, such as gradd ⁇ 12:0>, and 7 Column address pins, such as gcadd ⁇ 6:0>.
  • the row and column address lines of the same memory array module 200 may also be multiplexed.
  • each memory array module 200 can have its own address, and the row address and column address can be directly input through the address pins, without setting up a global control module to perform bank address selection and decoding, which is conducive to simplifying the signal control process inside the chip and improving Data access speed. At the same time, it is also beneficial to reduce the chip area.
  • the number of data pins is determined according to the data width that each memory array module 200 itself can write or read at most. For example, in an application scenario, each storage array module 200 can write or read 64-bit data at most at one time, then the data pins of each storage array module 200 can include 64-bit data input and output ports, as can be expressed is rwdl ⁇ 63:0>; as another example, in another application scenario, the data pins of each storage array module 200 may include 32-bit data input and output ports. In this way, each storage array module 200 can write or read data signals through its own data pins, without multi-level processing, and output them separately through the data pins shared with other storage array modules 200, which is conducive to improving data storage. Take speed and data width. At the same time, it is also beneficial to further reduce the chip area.
  • the technical solution provided by the embodiment of this specification can complete the access operation of each storage array module independently of each other by directly inputting or outputting the control signals and data signals of each storage array module 200 through their respective operation pins, effectively Simplifying the signal control process inside the chip is conducive to improving the data access speed and increasing the data width that can be read or written at one time.
  • the data width can be increased from the traditional 16 bits to a maximum of 1024 (ie 64*16) bits.
  • the signal control circuit inside the chip is reduced, the chip area can also be reduced.
  • the built-in circuit structure may also include: Test the circuit.
  • the test circuit is connected to the drive circuit, and when the test circuit receives the test signal, the drive circuit performs a failure test on the corresponding memory cells in the memory array module 200 based on the test signal, and outputs the test result.
  • the test circuit receives the test signal, it generates a test instruction based on the test signal, and the driving circuit accesses the corresponding storage unit in the storage array module 200 based on the test instruction to complete the test task.
  • the test command includes a test address signal, a test data signal and a test control signal.
  • the memory array module 200 in the memory chip 20 needs to be tested for failure, it only needs to receive the test signal sent by the external system, trigger the corresponding memory array module 200 to work in the test mode, and test the required test address and test data.
  • Both the test control command and the test control command can be generated by the built-in test circuit provided in the memory array module 200 inside the chip, without external input from the user.
  • the corresponding storage unit can be addressed in the storage array module 200, and the failure test is performed on the corresponding storage unit according to the test data, effectively realizing the self-test of the storage chip 20 .
  • the above-mentioned external system is an external control system of the memory chip 20, such as a processor or an SOC (System on Chip) system integrating the memory chip 20.
  • test rules may also be set in advance for various failure mechanisms in actual application scenarios.
  • the test command generation method is pre-configured in the test circuit. Specifically, it can be configured according to actual application scenarios and experience.
  • the test signal may contain a test task identifier, and the test circuit pre-stores the corresponding relationship between the test task identifier and the test instruction generation method. Based on the test task identifier and the corresponding relationship, the test instruction generation method is determined, thereby generating the test for this test task. instruction.
  • a test rule for a certain failure mechanism needs to perform data reading operations on the same storage unit cyclically at preset time intervals to test whether the data can be read normally.
  • the method of generating the test instruction corresponding to the corresponding test identifier can be as follows: randomly select the address of a storage unit in the storage array module 200 as the test address, and generate control commands involved in the read operation according to a preset time interval, and cycle through the memory unit to read data. Further, the test circuit can detect whether the data can be read normally during the test, and then output the test result.
  • the above-mentioned operation pins may also include: test pins, which are connected to the test circuit for receiving The test signal sent from the outside of the chip 20 is used to perform a failure test on the storage array module 200, that is, to make the storage array module 200 work in a test mode.
  • the test signals can be received through the respective test pins of each memory array module 200, and the self-test of each memory array module 200 can be realized independently, which is beneficial to improve the test efficiency.
  • test pins can be set individually for each storage array module 200, or can be shared by multiple storage array modules 200, and can be specifically set according to actual needs.
  • the test circuit 300 may include a test unit 301 and a selector 302, the input of the test unit 301 is connected to the test pin, and the output of the test unit 301 is connected to the selector.
  • the first input terminal c1 of 302 is connected.
  • the second input terminal c2 of the selector 302 is connected to the control pin and the data pin (ADD&Data&CTRL) of the corresponding storage array module 200 .
  • the output terminal out of the selector 302 is connected to the driving circuit in the storage array module 200 .
  • test unit 301 is configured to generate a test instruction when receiving a test signal, and send the test instruction to the selector 302 .
  • testing unit 301 may be implemented by hardware such as an integrated circuit, or may also be implemented by software codes.
  • the selector 302 is used to control the current working mode of the storage array module 200 by selecting the first input terminal c1 or the second input terminal c2.
  • the address, data and control command signals input to the drive circuit are test address signals, test data signals and test control signals.
  • the memory array module 200 works in the test mode ;
  • the selector 302 strobes the second input terminal the address, data and control command signal input to the drive circuit are the address, data input by the address pin of the memory array module 200, the data pin and the control command pin And the control command signal, at this time, the storage array module 200 works in the non-test mode.
  • the test pin may include a test enable pin test_en and a test control pin test_ctr
  • the test signal includes a test enable signal and a test control signal
  • the test enable signal is used to control the storage array module 200
  • the test control signal may include a test task identifier for generating test instructions.
  • the test enable pin test_en can be set independently, and the test control pin test_ctr can be used as other multiplexable operation pins of the corresponding storage array module 200 . As shown in FIG.
  • test enable pin test_en and the test control pin test_ctr are both connected to the test unit 301 , and the gate control terminal of the selector 302 is connected to the test enable pin test_en.
  • the test pins may also include test result output pins, or other operation pins of the corresponding storage array module 200 other than the test enable pins may be reused as test result output pins. foot.
  • the memory array module 200 may further include: a repair circuit.
  • the repair circuit is connected to the driving circuit in the storage array module 200 .
  • the drive circuit repairs the failed memory cells in the memory array module 200 based on the repairing signal. It can be understood that, during the use of the memory chip 20 , failure of the storage unit may occur. At this time, the failed storage unit needs to be repaired to avoid affecting the use of the memory chip 20 .
  • the memory chip 20 provided in this embodiment can repair failed memory cells by building a repair circuit in each memory array module 200 .
  • the operation pin further includes: a repair pin.
  • the repair pin is connected to the repair circuit and is used for receiving a repair signal sent from outside the memory chip 20 .
  • repair signals can be received through respective repair pins of each memory array module 200, and repairs to each memory array module 200 can be implemented independently, which is beneficial to improving repair efficiency.
  • the repair pin may include a repair enable pin and a repair control pin, and accordingly, as shown in FIG. 4 , the repair signal may include a repair enable signal and a repair control signal. Both the repair enable pin and the repair control pin are connected to the repair circuit 400 .
  • the repair enable pin is used to control the start of the repair circuit, and the repair control pin is used to receive the repair control signal.
  • the repair control signal may include an address signal, that is, the address of the failed memory unit to be repaired.
  • the repair enable pin can be set independently, and the repair control pin can be multiplexed with other multiplexable operation pins of the corresponding storage array module 200 .
  • the repair circuit 400 provided in the embodiment of this specification may adopt an eFuse repair method, that is, the repair circuit 400 may include an eFuse module.
  • eFuse is a fuse that can be used as a one-time programmable memory to record information.
  • the external system finds that a storage unit in a memory array module 200 in the memory chip 20 is wrong, it can record the row address of the wrong storage unit, and then input the row address into the eFuse module of the storage array module 200 .
  • the eFuse module edits a group of eFuses corresponding to a redundant word line of the memory array module 200 according to the row address, and records the row address into the group of eFuses, so that the redundant word line replaces the corresponding row address address line.
  • the redundant word line is a spare word line preset in the memory array module 200 .
  • the memory array module 200 includes 1000 rows of memory cells, 1006 row address lines can be set correspondingly, and the remaining 6 row address lines are redundant word lines, and a group of eFuses can be set corresponding to each redundant word line.
  • the repair enable pin can be denoted as efuse_en.
  • efuse_en 1
  • the system can input the row address of the invalid storage unit through the repair control pin of the corresponding storage array module 200, and the eFuse module edits the efuse information according to the row address to generate efuse repair information , and then the efuse repair information enters the row decoder in the drive circuit of the memory array module 200, and the word line activated corresponding to the row address is changed from the original word line to a replacement redundant word line. In this way, when the system accesses the failed memory cell again, the word line where the failed cell is located has been repaired by the redundant word line.
  • the repairing circuit 400 may also adopt other repairing methods, which are not limited here.
  • the memory chip 20 provided in this embodiment further includes a power supply pin, so as to receive power supply signals required by each memory array module 200 .
  • a power supply pin so as to receive power supply signals required by each memory array module 200 .
  • the memory chip 20 may use an off-chip power supply system, and the power supply pins are off-chip power supply pins, and the specific number of pins is determined according to the type of power supply signal required by the memory array module 200 .
  • the off-chip power supply pins are connected to each storage array module 200 for connecting to a power generation circuit disposed outside the memory chip 20 , so as to supply power to the storage array module 200 by using the peripheral power generation circuit.
  • Using an off-chip power supply system and setting off-chip power supply pins for corresponding power supply signals is beneficial to reducing the area of the memory chip 20 .
  • an on-chip power supply system can also be used, that is, the memory chip 20 is also provided with: a power generation circuit, which is connected to the corresponding storage array module 200, and is used for chip power supply based on external input.
  • the working voltage VDD and the common ground voltage VSS generate power signals required by the corresponding memory array module 200 .
  • the power supply pin is an on-chip power supply pin, and the on-chip power supply pin is connected to the power generation circuit for inputting the working voltage of the chip and the common ground voltage.
  • the internal power required by the memory array module 200 is generated inside the memory chip 20 by the power generation circuit according to the VDD and VSS input from the on-chip power pin.
  • the specific circuit structure of the power generation circuit can refer to the power system of the existing memory chip 20 , and will not be described in detail here.
  • the embodiment of this specification provides a stacked chip 50 including a logic unit 51 and a storage unit 52 .
  • the storage unit may include the storage chip 20 described in the embodiment of the first aspect above.
  • the logic unit 51 and the storage unit 52 are directly connected and packaged together in a 3D stacking manner.
  • the storage unit 52 may be in the form of a chip, a die or a wafer, which is not limited here.
  • the specific structure of the logic unit 51 and the specific type of the stacked chip 50 may be determined according to the actual application scenario of the memory chip 20, which is not limited in this embodiment.
  • the logic unit 51 may include a logic circuit chip, and accordingly, the stacked chip 50 may be a cache memory or a computing memory. That is to say, the above-mentioned memory chip 20 can be used as a cache of a logic circuit chip to implement a stacked chip with a cache or computing memory function.
  • logic circuit chips can be used for AI and applications that require cache memory.
  • the logic unit 51 may also include an interface chip, and accordingly, the stacked chip 50 may be a high-speed memory.
  • the above-mentioned memory chip 20 can also be used as a storage body with different interface chips to form an independent high-speed memory.
  • the interface chip can use SERDES (ie SERializer (serializer)/DESerializer (deserializer)) or GDDR ( Graphics Double Data Rate), etc.
  • each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment refer to each other That's it.

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Abstract

本申请公开了一种存储芯片以及堆叠芯片，该存储芯片包括：多个存储阵列模块，每个所述存储阵列模块均相互独立地设置有引出到存储芯片外部的操作引脚。其中，操作引脚包括：控制引脚和数据引脚，控制引脚用于接收对相应存储阵列模块中待访问存储单元进行读出或写入控制的控制信号，数据引脚用于从待访问存储单元中读出或写入数据。通过相互独立地为每个存储阵列模块均设置引出到芯片外部的操作引脚，能够有效地提高存储器的数据存取速度以及数据宽度。

Description

一种存储芯片及堆叠芯片
相关申请的交叉引用
本申请基于2021年8月3日提交的中国专利申请202110887771.7主张其优先权，此处通过参照引入其全部的记载内容。
【技术领域】
本申请涉及存储器技术领域，尤其涉及一种存储芯片以及堆叠芯片。
【背景技术】
处理器的时钟频率和数据吞吐率以超乎想象的速度增长，但是存储器(如DRAM)的存取速度和数据吞吐率增长却要缓慢得多。存储模块的存取速度和处理器的计算速度的较大差异极大地限制了系统整体的运行速度，即存储墙问题越来越严重，计算、存储、I/O的速度越来越不匹配。因此，亟需提高存储器的存取速度和数据吞吐率。
【发明内容】
有鉴于此，本申请实施例提供了一种存储芯片以及堆叠芯片，能够有效地提高存储器的存取速度以及数据宽度。
第一方面，本申请实施例提供了一种存储芯片，包括：
多个存储阵列模块，每个所述存储阵列模块均相互独立地设置有引出到所述存储芯片外部的操作引脚；
其中，所述操作引脚包括：控制引脚和数据引脚，所述控制引脚用于接收对相应存储阵列模块中待访问存储单元进行读出或写入控制的控制信号，
所述数据引脚用于从所述待访问存储单元中读出或写入数据。
进一步地，所述存储阵列模块包括：测试电路，所述测试电路与所述存储阵列模块中的驱动电路连接，响应于所述测试电路接收到测试信号时，所述驱 动电路基于所述测试信号对所述存储阵列模块中的相应存储单元进行失效测试，并输出测试结果。
进一步地，所述操作引脚还包括：测试引脚，所述测试引脚与所述测试电路连接，用于接收从所述存储芯片外部发送的所述测试信号。
进一步地，所述存储阵列模块包括：修复电路，所述修复电路与所述存储阵列模块中的驱动电路连接，响应于所述修复电路接收到修复信号时，所述驱动电路基于所述修复信号对所述存储阵列模块中的失效存储单元进行修复。
进一步地，所述操作引脚还包括：修复引脚，所述修复引脚与所述修复电路连接，用于接收从所述存储芯片外部发送的所述修复信号。
进一步地，所述修复引脚包括：修复使能引脚和修复控制引脚；所述修复使能引脚和所述修复控制引脚连接所述修复电路；其中，所述修复使能引脚用于控制修复电路的开启，所述修复控制引脚用于接收修复控制信号，所述修复控制信号包括待修复的失效存储单元的地址。
进一步地，所述修复电路包括eFuse模块。
进一步地，所述存储芯片还包括：片外电源引脚，所述片外电源引脚与每个所述存储阵列模块连接，用于连接设置在所述存储芯片外部的电源产生电路，以利用所述电源产生电路对所述存储阵列模块供电。
进一步地，所述存储芯片还包括：电源产生电路和片内电源引脚，所述片内电源引脚与所述电源产生电路连接，所述电源产生电路与所述存储阵列模块连接；所述片内电源引脚用于向所述电源产生电路输入芯片工作电压和公共接地电压；所述电源产生电路用于基于从外部输入的芯片工作电压和公共接地电压产生存储阵列模块所需的电源信号。
进一步地，所述控制引脚包括控制命令引脚和地址引脚，所述控制信号包括控制命令信号和地址信号。所述控制命令引脚用于接收相应存储阵列模块的控制命令信号，所述地址引脚用于接收所述待访问存储单元的地址信号。
进一步地，所述控制命令引脚包括：行操作使能引脚、列操作使能引脚、 读写控制引脚以及数据位选引脚。
进一步地，所述地址引脚包括行地址引脚和列地址引脚。
进一步地，所述存储芯片的存储容量为1G，所述存储芯片包括16个相互独立的存储阵列模块，每个所述存储阵列模块的存储容量为64M，每个所述存储阵列模块的所述数据引脚包括64位数据输入输出口。
进一步地，所述存储芯片为动态随机存取存储器，或者，闪存。
第二方面，本申请实施例还提供了一种堆叠芯片，包括逻辑单元以及存储单元，所述逻辑单元与所述存储单元直连；所述存储单元包括：多个存储阵列模块，每个所述存储阵列模块均相互独立地设置有引出到所述存储芯片外部的操作引脚；其中，所述操作引脚包括：控制引脚和数据引脚，所述控制引脚用于接收对相应存储阵列模块中待访问存储单元进行读出或写入控制的控制信号，所述数据引脚用于从所述待访问存储单元中读出或写入数据。
进一步地，所述逻辑芯片和所述存储芯片采用3D堆叠的方式封装在一起。
进一步地，所述存储阵列模块包括：测试电路，所述测试电路与所述存储阵列模块中的驱动电路连接，响应于所述测试电路接收到测试信号时，所述驱动电路基于所述测试信号对所述存储阵列模块中的相应存储单元进行失效测试，并输出测试结果。
进一步地，所述存储阵列模块包括：修复电路，所述修复电路与所述存储阵列模块中的驱动电路连接，响应于所述修复电路接收到修复信号时，所述驱动电路基于所述修复信号对所述存储阵列模块中的失效存储单元进行修复。
进一步地，所述存储芯片还包括：片外电源引脚，所述片外电源引脚与每个所述存储阵列模块连接，用于连接设置在所述存储芯片外部的电源产生电路，以利用所述电源产生电路对所述存储阵列模块供电。
进一步地，所述存储芯片还包括：电源产生电路和片内电源引脚，所述片内电源引脚与所述电源产生电路连接，所述电源产生电路与所述存储阵列模块连接；所述片内电源引脚用于向所述电源产生电路输入芯片工作电压和公共接 地电压；所述电源产生电路用于基于从外部输入的芯片工作电压和公共接地电压产生存储阵列模块所需的电源信号。
本申请实施例提供的存储芯片以及堆叠芯片，通过相互独立地为每个存储阵列模块均设置引出到芯片外部的操作引脚，包括控制引脚和数据引脚，能够将存取操作涉及的控制信号和数据信号通过各自的操作引脚直接输入或输出，从而相互独立地完成对每个存储阵列模块的存取操作，有效地简化了存储芯片中的信号控制流程，有利于提高存储芯片的数据存取速度，以及增加一次可读取或写入的数据宽度。同时由于减少了芯片内部的控制电路，芯片面积也明显减少。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
【附图说明】
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本申请的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1示出了一种示例性动态随机存取存储器的芯片结构示意图；
图2示出了本说明书实施例第一方面提供的一种存储芯片的结构示意图；
图3示出了本说明书实施例提供的一种测试电路的结构示意图；
图4示出了本说明书实施例提供的一种修复电路的结构示意图；
图5示出了本说明书实施例第二方面提供的一种堆叠芯片的结构示意图。
【具体实施方式】
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了 本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
图1所示为一种1G双倍速率(Double Data Rate，简称DDR3)动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)芯片结构示意图。整个芯片共8个存储阵列模块(bank)，每个(bank)容量为128M，在芯片内部每个存储阵列模块(bank)由两个分存储阵列模块(splitbank)组成，每个分存储阵列模块(splitbank)容量为64M，且这两个分存储阵列模块的划分是外部无感知的，共享同一个bank地址。
如图1所示，bank0包括splitbank0和splitbank0′，bank1包括splitbank1和splitbank1′，以此类推，bank7包括splitbank7和splitbank7′。其中，bank0-bank7共用行扫描线，且四个splitbank共用数据线，即splitbank0-splitbank3共用数据线，splitbank0′-splitbank3′共用数据线，splitbank4-splitbank7共用数据线，splitbank4′-splitbank7′共用数据线。
发明人对图1示出的存储器芯片的数据存取过程进行了长期研究发现，存储器中的多级控制电路极大地限制了存储器的存取速度。下面主要以激活操作(ACTIVE)和读操作为例进行说明：
在进行ACTIVE操作时，首先，外部系统发送第一地址信息和第一命令信息到芯片内的全局控制模块(Golbal ctrl)，由全局控制模块对第一地址信息进行译码，产生bank选择信息bnksel<7:0>和各存储阵列模块共用的行地址信息(gradd<13:0>)，其中，bnksel<7:0>为激活操作bank地址信息，用于确定本次激活操作针对的bank。相应的存储阵列模块会根据第一命令信息激活相应行地址对应的字线并将字线上的数据放大等待读操作或写操作。在进行读操作时，外部系统发送第二地址信息和第二命令信息到上述全局控制模块，由全局控制模块对第二地址信息进行译码，产生读操作bank信息cas<7:0>，读写信息pawcol以及数据mask信息DM<7:0>和各bank共用的列地址信息gcadd<6:0>。其中， cas<7:0>为读操作bank地址信息，用于确定本次读操作针对的bank，pawcol用于控制是读数据还是写入数据，数据mask信息用于选择写入的数据位。相应的bank会读出共128位数据，每个splitbank读出64位数据，通过四个splitbank共用的数据线将读出的数据rwdl<63:0>送至数据处理dpcross模块。由dpcross模块将128位数据划分为8笔数据(每笔16位)，再通过输出数据驱动OCD模块将每笔16位的数据送至外部数据引脚DQ<15:0>输出。
可以看到，不管是ACTIVE操作还是读操作，DRAM命令输入需要经过全局控制模块译码才能到达对应的bank，读取的数据也需要经过多级处理才能输出到芯片外部，从而导致存储器的存取速度以及数据吞吐率难以提高。
有鉴于此，本说明书实施例提供了一种存储芯片以及堆叠芯片，通过相互独立地为每个存储阵列模块均设置引出到芯片外部的操作引脚，将存取操作涉及的控制信号和数据信号通过各自的操作引脚直接输入或输出，从而相互独立地完成对每个存储阵列模块的存取操作，有效地简化了存储芯片中的信号控制流程，有利于提高存储器的数据存取速度以及数据宽度。
下面对本说明书实施例提供的具体实现方案进行详细介绍。需要说明的是，本说明书实施例提供的存储芯片可以是动态随机存储器(Dynamic Random Access Memory，DRAM)，或者，也可以是其他类型的存储芯片，例如闪存如NAND闪存等，本说明书实施例对此不作限制。
第一方面，如图2所示，本说明书实施例提供了一种存储芯片20，包括：多个存储阵列模块200。每个存储阵列模块200均相互独立地设置有引出到存储芯片20外部的操作引脚。这样就可以将对各个存储阵列模块200进行存取操作涉及的控制以及数据信号通过各自的操作引脚直接输入或输出。
需要说明的是，一个存储阵列模块200即为存储芯片20中的一个bank，存储芯片20包括M个bank，M为大于或等于2的整数，则每个bank各自设置有引出到芯片外部的操作引脚，存储芯片20就包括M组操作引脚。需要说明的是，M的具体数量根据存储芯片20的容量以及每个bank的容量确定，图2中示出 的bank数量仅为示意。
举例来讲，存储芯片20的存储容量为1G，则该存储芯片20包括16个相互独立的bank，如图2中示出的bank0至bank15，每个bank的存储容量为64M。其中，bank0引出到芯片外部的操作引脚表示为p0，bank1引出到芯片外部的操作引脚表示为p1，bank2引出到芯片外部的操作引脚表示为p2，以此类推，bank15引出到芯片外部的操作引脚表示为p15。
具体来讲，每个存储阵列模块200包括存储单元阵列以及驱动电路如行(Row)电路和列(column)电路。对于每个存储阵列模块200来讲，操作引脚可以包括：控制引脚和数据引脚。控制引脚和数据引脚均与相应存储阵列模块200的驱动电路连接。控制引脚用于接收对相应存储阵列模块中待访问存储单元进行读出或写入控制的控制信号，并将控制信号发给驱动电路，从而对待访问存储单元进行读出或写入控制。数据引脚用于从上述待访问存储单元中读出或写入数据。其中，待访问存储单元即为存入或读取操作针对的存储单元。
这样，各存储阵列模块200就可以拥有各自的控制信号传输口和数据信号传输口，可以相互独立地完成对每个存储阵列模块的存取操作，减少了存储芯片20中的信号控制电路，有利于提高存储器的存取速度以及数据宽度。
进一步地，控制引脚包括控制命令引脚和地址引脚，相应地，上述控制信号包括控制命令信号和地址信号。控制命令引脚用于接收相应存储阵列模块200的控制命令信号；地址引脚用于接收相应存储阵列模块200中待访问存储单元的地址信号。
举例来讲，控制命令引脚可以包括：行操作使能引脚、列操作使能引脚、读写控制引脚以及数据位选引脚。例如，行操作使能引脚可以表示为bnksel，列操作使能引脚可以表示为cas，读写控制引脚可以表示为pawcol，数据位选引脚可以表示为dm<k:0>。bnksel用于使能行寻址操作，cas用于使能列寻址操作，pawcol用于进行读写控制，dm<k:0>用于选择写入操作涉及的数据位，通过dm<k:0>的值来决定写入哪些数据位。dm<k:0>的每一位mask数据信号中的8 位，k的具体大小根据数据引脚包括的数据位宽决定，如数据位宽为64位，则k为7，数据位宽为32位，则k为3。以dm<7:0>为例，若dm[0]＝1，则数据信号中的0-7位就不能写了。
当然，除了上述四种引脚以外，在本说明书其他实施方式中，控制命令引脚也可以包括更多或更少的引脚，例如，可以通过复用一些引脚来减少引脚数量，本实施例对此不作限制。
本实施例中，地址引脚的数量根据每个存储阵列模块200的行列地址线数量确定。在一种可选的实施方式中，地址引脚可以包括相互独立的行地址引脚和列地址引脚。例如，在一种应用场景中，每个存储阵列模块200的存储容量为64M，每个存储阵列模块200可以设置13个行地址引脚，如可以表示为gradd<12:0>，以及7个列地址引脚，如可以表示为gcadd<6:0>。当然，在一种可选的实施方式中，同一存储阵列模块200的行列地址线也可以复用。这样每个存储阵列模块200就可以有各自的地址，直接通过地址引脚输入行地址和列地址，无需再设置全局控制模块进行bank选址译码，有利于简化芯片内部的信号控制流程，提高数据存取速度。同时，也有利于减少芯片面积。
数据引脚的数量根据每个存储阵列模块200自身最多能够一次写入或读出的数据宽度确定。例如，在一种应用场景中，每个存储阵列模块200最多能够一次写入或读出64位数据，则每个存储阵列模块200的数据引脚可以包括64位数据输入输出口，如可以表示为rwdl<63:0>；又例如，在另一种应用场景中，每个存储阵列模块200的数据引脚可以包括32位数据输入输出口。这样每个存储阵列模块200就可以通过自身的数据引脚写入或读出数据信号，无需经过多级处理后通过与其他存储阵列模块200共用的数据引脚分笔输出，有利于提高数据存取速度和数据宽度。同时，也有利于进一步减少芯片面积。
本说明书实施例提供的技术方案通过将各存储阵列模块200的控制信号和数据信号直接通过各自的操作引脚输入或输出，能够相互独立地完成对每个存储阵列模块的存取操作，有效地简化芯片内部的信号控制流程，有利于提高数 据存取速度，以及增加一次可读取或写入的数据宽度。例如，在上述1G存储芯片20、64位数据引脚的示例中，数据宽度可以由传统的16位增加至最多1024(即64*16)位。同时，由于减少了芯片内部的信号控制电路，还能够减少芯片面积。
为了更方便地对存储芯片20进行测试，在一种可选的实施方式中，对于存储芯片20中的每个存储阵列模块200来讲，内设的电路结构除了驱动电路以外，还可以包括：测试电路。测试电路与驱动电路连接，响应于测试电路接收到测试信号时，驱动电路基于测试信号对该存储阵列模块200中的相应存储单元进行失效测试，并输出测试结果。举例来讲，测试电路接收到测试信号时，会基于测试信号产生测试指令，驱动电路基于测试指令对存储阵列模块200中的相应存储单元进行访问，完成本次测试任务。其中，测试指令包括测试地址信号、测试数据信号及测试控制信号。
也就是说，在需要对存储芯片20中的存储阵列模块200进行失效测试时，只需要接收外部系统发送的测试信号，触发相应存储阵列模块200工作在测试模式，测试需要的测试地址、测试数据以及测试控制命令均可以由芯片内部设置在存储阵列模块200中的内建测试电路产生，无需用户从外部输入。基于内建测试电路产生的测试地址和测试控制命令就可以在存储阵列模块200中寻址相应的存储单元，并根据测试数据对相应存储单元进行失效测试，有效地实现了存储芯片20的自测试。需要说明的是，上述外部系统为存储芯片20的外部控制系统，例如可以是处理器或者是集成该存储芯片20的SOC(System on Chip)系统。
具体实施过程中，也可以预先针对实际应用场景中，多种不同失效机理设置对应的测试规则。针对每种失效机理的测试规则，预先在测试电路中配置测试指令产生方式。具体可以根据实际应用场景以及经验配置。测试信号中可以包含测试任务标识，测试电路中预先存储有测试任务标识与测试指令产生方式的对应关系，基于测试任务标识以及该对应关系，确定测试指令产生方式，从 而产生本次测试任务的测试指令。
例如，某种失效机理的测试规则需要按照预设时间间隔循环对同一个存储单元进行数据读取操作，测试是否能正常读取数据。此时，相应测试标识对应的测试指令产生方式可以为：随机选取存储阵列模块200中的一个存储单元的地址作为测试地址，并按照预设时间间隔生成读操作涉及的控制命令，循环对该存储单元进行数据读取。进一步，测试电路可以检测测试过程中数据是否能正常读取，进而输出测试结果。
在此基础上，为了方便控制各存储阵列模块200是否工作在测试模式，作为一种实施方式，上述操作引脚还可以包括：测试引脚，测试引脚与测试电路连接，用于接收从存储芯片20外部发送的测试信号，以对存储阵列模块200进行失效测试，也就是使得存储阵列模块200工作在测试模式。这样就可以通过各存储阵列模块200各自的测试引脚接收测试信号，相互独立地实现对各存储阵列模块200的自测试，有利于提高测试效率。
需要说明的是，本实施例中，测试引脚可以针对每个存储阵列模块200单独设置，或者，也可以由多个存储阵列模块200共用，具体可以根据实际需要设置。
在一种可选的实施方式中，如图3所示，测试电路300可以包括测试单元301和选择器302，测试单元301的输入端与测试引脚连接，测试单元301的输出端与选择器302的第一输入端c1连接。选择器302的第二输入端c2与相应存储阵列模块200的控制引脚以及数据引脚(ADD&Data&CTRL)连接。选择器302输出端out与存储阵列模块200中的驱动电路连接。
其中，测试单元301用于在接收到测试信号时，产生测试指令，并将测试指令发送到选择器302。需要说明的是，测试单元301可以由硬件例如集成电路实现，或者，也可以由软件代码实现。
选择器302用于通过选通第一输入端c1或第二输入端c2，控制该存储阵列模块200的当前工作模式。当选择器302选通第一输入端c1时，输入到驱动电 路的地址、数据以及控制命令信号为测试地址信号、测试数据信号及测试控制信号，此时，该存储阵列模块200工作在测试模式；当选择器302选通第二输入端时，输入到驱动电路的地址、数据以及控制命令信号为由该存储阵列模块200的地址引脚、数据引脚以及控制命令引脚输入的地址、数据以及控制命令信号，此时，该存储阵列模块200工作在非测试模式。
作为一种实施方式，测试引脚可以包括测试使能引脚test_en以及测试控制引脚test_ctr，相应地，测试信号包括测试使能信号以及测试控制信号，测试使能信号用于控制存储阵列模块200工作在测试模式，测试控制信号可以包括测试任务标识，用于产生测试指令。在一种应用场景中，测试使能引脚test_en可以单独设置，测试控制引脚test_ctr可以复用相应存储阵列模块200的其他能被复用的操作引脚。如图3所示，测试使能引脚test_en以及测试控制引脚test_ctr均与测试单元301连接，选择器302的选通控制端与测试使能引脚test_en连接。进一步地，为了方便输出测试结果，测试引脚还可以包括测试结果输出引脚，或者，也可以复用相应存储阵列模块200的除测试使能引脚以外的其他操作引脚作为测试结果输出引脚。
对某存储阵列模块200进行内建自测试时，即该存储阵列模块200的test_en＝1时，测试单元301根据接收到的测试控制信号产生测试地址、测试数据及测试控制信号，选择器302会选择内建自测试产生的这些信号对该存储阵列模块200进行操作从而达到测试目的。当非测试模式下即该存储阵列模块200的test_en＝0时，选择器302则选择该存储阵列模块200的地址引脚、数据引脚以及控制命令引脚上面的地址、数据及控制命令信号对该存储阵列模块200中的存储单元进行操作。
进一步地，为了提高本说明书实施例提供的存储芯片20的可靠性，在一种可选的实施方式中，存储阵列模块200中还可以包括：修复电路。针对每个存储阵列模块200来讲，修复电路与存储阵列模块200中的驱动电路连接。响应于修复电路接收到修复信号时，驱动电路基于修复信号对存储阵列模块200中 的失效存储单元进行修复。可以理解的是，存储芯片20使用过程中，可能会发生存储单元的失效，此时，需要对失效的存储单元进行修复，以避免影响存储芯片20的使用。本实施例提供的存储芯片20通过在各存储阵列模块200中内建修复电路，能够对失效存储单元进行修复。
在此基础上，在一种可选的实施方式中，上述操作引脚还包括：修复引脚。修复引脚与修复电路连接，用于接收从存储芯片20外部发送的修复信号。这样就可以通过各存储阵列模块200各自的修复引脚接收修复信号，相互独立地实现对各存储阵列模块200的修复，有利于提高修复效率。
作为一种实施方式，修复引脚可以包括修复使能引脚和修复控制引脚，相应地，如图4所示，修复信号可以包括修复使能信号以及修复控制信号。修复使能引脚和修复控制引脚均与修复电路400连接。修复使能引脚用于控制修复电路的开启，修复控制引脚用于接收修复控制信号，例如，修复控制信号可以包括地址信号，即待修复的失效存储单元的地址。在一种应用场景中，修复使能引脚可以单独设置，修复控制引脚可以复用相应存储阵列模块200的其他能被复用的操作引脚。
举例来讲，本说明书实施例提供的修复电路400可以采用eFuse修复方式，即修复电路400可以包括eFuse模块。可以理解的是，eFuse是一种熔丝，能够作为一次性可编程存储器，用来记录信息。外部系统发现存储芯片20内某个存储阵列模块200中的存储单元错误时，可记录错误存储单元的行地址，然后将此行地址输入该存储阵列模块200的eFuse模块。eFuse模块根据此行地址对该存储阵列模块200的一根冗余字线对应的一组eFuse进行编辑，将该行地址记录到这一组eFuse中，使得该冗余字线代替此行地址对应的地址线。其中，冗余字线为存储阵列模块200中预先设置的备用字线。例如，存储阵列模块200包括1000行存储单元，可以对应设置1006根行地址线，剩余的6根行地址线即为冗余字线，可以针对每一根冗余字线对应设置一组eFuse。
例如，修复使能引脚可以表示为efuse_en。如图4所示，当efuse_en＝1即 efuse修复使能时，系统可以通过相应存储阵列模块200的修复控制引脚输入失效存储单元行地址，eFuse模块根据该行地址编辑efuse信息产生efuse修复信息，之后efuse修复信息进入该存储阵列模块200的驱动电路中的行译码器，将该行地址对应启动的字线由原本的字线变更为替换的冗余字线。这样当系统再次访问此失效存储单元时，此失效单元所在的字线已经被冗余字线修复。
当然，在本说明书其他实施例中，除了上述的eFuse修复方式以外，修复电路400也可以采用其他修复方式，此处不做限定。
另外，可以理解的是，本实施例提供的存储芯片20还包括电源引脚，以便接收各存储阵列模块200所需的电源信号。具体实施过程中，根据实际应用场景中，存储芯片20的电源系统设计的不同，即采用片内电源系统或者是片外电源系统，电源引脚的设置有所不同。
在一种可选的实施方式中，存储芯片20可以采用片外电源系统，电源引脚为片外电源引脚，具体引脚数量根据存储阵列模块200所需的电源信号种类确定。片外电源引脚与每个存储阵列模块200连接，用于连接设置在存储芯片20外部的电源产生电路，以利用外设的电源产生电路对存储阵列模块200供电。采用片外电源系统，设置相应电源信号的片外电源引脚，有利于减少存储芯片20的面积。
当然，在本说明书其他实施例中，也可以采用片内电源系统，即存储芯片20内还设置有：电源产生电路，电源产生电路与相应存储阵列模块200连接，用于基于从外部输入的芯片工作电压VDD和公共接地电压VSS产生相应存储阵列模块200所需的电源信号。此时，电源引脚为片内电源引脚，片内电源引脚与电源产生电路连接，用于输入芯片工作电压和公共接地电压。此时，存储阵列模块200所需内部电源在存储芯片20内部由电源产生电路根据从片内电源引脚输入的VDD和VSS产生。
需要说明的是，电源产生电路的具体电路结构可以参见现有存储芯片20的电源系统，此处不做详述。
第二方面，如图5所示，本说明书实施例提供了一种堆叠芯片50，包括逻辑单元51以及存储单元52。其中，存储单元可以包括上述第一方面实施例所述的存储芯片20。逻辑单元51以及存储单元52直连，采用3D堆叠的方式封装在一起。存储芯片20的具体结构以及效果可以参照前述第一方面提供的实施例中相应内容，此处不再赘述。举例来讲，存储单元52可以是芯片(chip)、晶粒(die)或晶圆(wafer)的形式，此处不做限定。
需要说明的是，逻辑单元51的具体结构以及堆叠芯片50的具体类型可以根据上述存储芯片20的实际应用场景确定，本实施例对此不做限定。举例来讲，逻辑单元51可以包括逻辑电路芯片，相应地，堆叠芯片50可以为高速缓存或计算存储器。也就是说，上述存储芯片20可以作为逻辑电路芯片的缓存，实现具有高速缓存或计算存储器功能的堆叠芯片。例如，逻辑电路芯片可以是用于AI及需要高速缓存的应用。又例如，逻辑单元51也可以包括接口芯片，相应地，堆叠芯片50可以为高速存储器。也就是说，上述存储芯片20也可以作为存储主体搭配不同的接口芯片构成独立高速存储器，如搭配的接口芯片可以采用SERDES(即SERializer(串行器)/DESerializer(解串器))或GDDR(Graphics Double Data Rate)等。
由于本说明书实施例所介绍的堆叠芯片50包括的存储芯片20在前述已经进行说明，故而基于本说明书实施例所介绍的存储芯片20，本领域所属人员能够了解该堆叠芯片50的具体结构及效果原理，故而在此不再赘述。凡是包括本说明书实施例的存储芯片20的堆叠芯片50都属于本发明所欲保护的范围。
还需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何 其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。术语“多个”表示两个以上，包括两个或大于两个的情况。
尽管已描述了本说明书的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本说明书范围的所有变更和修改。
显然，本领域的技术人员可以对本说明书进行各种改动和变型而不脱离本说明书的精神和范围。这样，倘若本说明书的这些修改和变型属于本说明书权利要求及其等同技术的范围之内，则本说明书也意图包含这些改动和变型在内。

Claims (20)

  1. 一种存储芯片，其特征在于，包括：
    多个存储阵列模块，每个所述存储阵列模块均相互独立地设置有引出到所述存储芯片外部的操作引脚；
    其中，所述操作引脚包括：控制引脚和数据引脚，所述控制引脚用于接收对相应存储阵列模块中待访问存储单元进行读出或写入控制的控制信号，所述数据引脚用于从所述待访问存储单元中读出或写入数据。
  2. 根据权利要求1所述的存储芯片，其特征在于，所述存储阵列模块包括：测试电路，所述测试电路与所述存储阵列模块中的驱动电路连接，响应于所述测试电路接收到测试信号时，所述驱动电路基于所述测试信号对所述存储阵列模块中的相应存储单元进行失效测试，并输出测试结果。
  3. 根据权利要求2所述的存储芯片，其特征在于，所述操作引脚还包括：测试引脚，所述测试引脚与所述测试电路连接，用于接收所述存储芯片外部发送的所述测试信号。
  4. 根据权利要求1所述的存储芯片，其特征在于，所述存储阵列模块包括：修复电路，所述修复电路与所述存储阵列模块中的驱动电路连接，响应于所述修复电路接收到修复信号时，所述驱动电路基于所述修复信号对所述存储阵列模块中的失效存储单元进行修复。
  5. 根据权利要求4所述的存储芯片，其特征在于，所述操作引脚还包括：修复引脚，所述修复引脚与所述修复电路连接，用于接收从所述存储芯片外部发送的所述修复信号。
  6. 根据权利要求5所述的存储芯片，其特征在于，所述修复引脚包括：修复使能引脚和修复控制引脚；所述修复使能引脚和所述修复控制引脚连接所述修复电路；
    其中，所述修复使能引脚用于控制修复电路的开启，所述修复控制引脚用 于接收修复控制信号，所述修复控制信号包括待修复的失效存储单元的地址。
  7. 根据权利要求4所述的存储芯片，其特征在于，所述修复电路包括eFuse模块。
  8. 根据权利要求1所述的存储芯片，其特征在于，所述存储芯片还包括：片外电源引脚，所述片外电源引脚与每个所述存储阵列模块连接，用于连接设置在所述存储芯片外部的电源产生电路，以利用所述电源产生电路对所述存储阵列模块供电。
  9. 根据权利要求1所述的存储芯片，其特征在于，所述存储芯片还包括：电源产生电路和片内电源引脚，所述片内电源引脚与所述电源产生电路连接，所述电源产生电路与所述存储阵列模块连接；
    所述片内电源引脚用于向所述电源产生电路输入芯片工作电压和公共接地电压；所述电源产生电路用于基于从外部输入的芯片工作电压和公共接地电压产生存储阵列模块所需的电源信号。
  10. 根据权利要求1所述的存储芯片，其特征在于，所述控制引脚包括控制命令引脚和地址引脚，所述控制信号包括控制命令信号和地址信号；
    所述控制命令引脚用于接收相应存储阵列模块的控制命令信号，所述地址引脚用于接收所述待访问存储单元的地址信号。
  11. 根据权利要求10所述的存储芯片，其特征在于，所述控制命令引脚包括：行操作使能引脚、列操作使能引脚、读写控制引脚以及数据位选引脚。
  12. 根据权利要求10所述的存储芯片，其特征在于，所述地址引脚包括行地址引脚和列地址引脚。
  13. 根据权利要求1所述的存储芯片，其特征在于，所述存储芯片的存储容量为1G，所述存储芯片包括16个相互独立的存储阵列模块，每个所述存储阵列模块的存储容量为64M，每个所述存储阵列模块的所述数据引脚包括64位数据输入输出口。
  14. 根据权利要求1所述的存储芯片，其特征在于，所述存储芯片为动态随 机存取存储器，或者，闪存。
  15. 一种堆叠芯片，其特征在于，包括：
    逻辑单元；
    存储单元；所述逻辑单元与所述存储单元直连；
    所述存储单元包括：多个存储阵列模块，每个所述存储阵列模块均相互独立地设置有引出到所述存储芯片外部的操作引脚；
    其中，所述操作引脚包括：控制引脚和数据引脚，所述控制引脚用于接收对相应存储阵列模块中待访问存储单元进行读出或写入控制的控制信号，
    所述数据引脚用于从所述待访问存储单元中读出或写入数据。
  16. 根据权利要求15所述的堆叠芯片，其特征在于，所述逻辑芯片和所述存储芯片采用3D堆叠的方式封装在一起。
  17. 根据权利要求15所述的堆叠芯片，其特征在于，所述存储阵列模块包括：测试电路，所述测试电路与所述存储阵列模块中的驱动电路连接，响应于所述测试电路接收到测试信号时，所述驱动电路基于所述测试信号对所述存储阵列模块中的相应存储单元进行失效测试，并输出测试结果。
  18. 根据权利要求15所述的堆叠芯片，其特征在于，所述存储阵列模块包括：修复电路，所述修复电路与所述存储阵列模块中的驱动电路连接，响应于所述修复电路接收到修复信号时，所述驱动电路基于所述修复信号对所述存储阵列模块中的失效存储单元进行修复。
  19. 根据权利要求15所述的存储芯片，其特征在于，所述存储芯片还包括：片外电源引脚，所述片外电源引脚与每个所述存储阵列模块连接，用于连接设置在所述存储芯片外部的电源产生电路，以利用所述电源产生电路对所述存储阵列模块供电。
  20. 根据权利要求15所述的存储芯片，其特征在于，所述存储芯片还包括：电源产生电路和片内电源引脚，所述片内电源引脚与所述电源产生电路连接，所述电源产生电路与所述存储阵列模块连接；
    所述片内电源引脚用于向所述电源产生电路输入芯片工作电压和公共接地电压；所述电源产生电路用于基于从外部输入的芯片工作电压和公共接地电压产生存储阵列模块所需的电源信号。
PCT/CN2022/109157 2021-08-03 2022-07-29 一种存储芯片及堆叠芯片 WO2023011367A1 (zh)

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