WO2023010648A1 - Dispositif de protection électrostatique et circuit de protection électrostatique - Google Patents

Dispositif de protection électrostatique et circuit de protection électrostatique Download PDF

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Publication number
WO2023010648A1
WO2023010648A1 PCT/CN2021/117226 CN2021117226W WO2023010648A1 WO 2023010648 A1 WO2023010648 A1 WO 2023010648A1 CN 2021117226 W CN2021117226 W CN 2021117226W WO 2023010648 A1 WO2023010648 A1 WO 2023010648A1
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conductivity type
doped region
heavily doped
region
well region
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PCT/CN2021/117226
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English (en)
Chinese (zh)
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许杞安
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长鑫存储技术有限公司
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Publication of WO2023010648A1 publication Critical patent/WO2023010648A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers

Definitions

  • the present application relates to the field of semiconductors, in particular to an electrostatic protection device and an electrostatic protection circuit.
  • the schematic diagram of the existing electrostatic protection circuit uses two diodes to divide the current and prevent excessive voltage from being applied to the protected circuit.
  • the capacitance of the diode will affect the charging and discharging speed of the electrostatic protection circuit, and then affect the response speed of the electrostatic protection circuit. If the capacitance is large and the response speed is slow, the electrostatic protection circuit is not turned on in time, and the devices in the main circuit may be shocked by a large current. worn, damaged.
  • the purpose of this application is to solve the problem that the large capacitance of the diode in the existing electrostatic protection circuit affects the response speed of the electrostatic protection circuit.
  • an embodiment of the present application provides an electrostatic protection device connected to the power supply terminal, including: a substrate of the first conductivity type and a deep well region of the second conductivity type located in the substrate of the first conductivity type ; The doped region of the first conductivity type and the heavily doped region of the second conductivity type located on the surface of the deep well region of the second conductivity type; the doped region of the first conductivity type includes a heavily doped region of the first conductivity type A doped region and at least one of the following: a lightly doped region of the first conductivity type, a well region of the first conductivity type; the heavily doped region of the first conductivity type is located in the lightly doped region of the first conductivity type In or on the surface of the well region of the first conductivity type; the heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type.
  • An embodiment of the present application provides an electrostatic protection device for a ground terminal, including: a substrate of a first conductivity type, a doped region of a second conductivity type located in the substrate of the first conductivity type, and a doped region of the first conductivity type.
  • the heavily doped region; the doped region of the second conductivity type includes a heavily doped region of the second conductivity type and at least one of the following: a lightly doped region of the second conductivity type, a well region of the second conductivity type; The heavily doped region of the second conductivity type is located in the lightly doped region of the second conductivity type or on the surface of the well region of the second conductivity type; the heavily doped region of the second conductivity type is connected to the The heavily doped regions of the first conductivity type are arranged at intervals.
  • An embodiment of the present application provides an electrostatic protection circuit, including a power supply terminal, a ground terminal, an input-output interface terminal located between the power supply terminal and the ground terminal, the above-mentioned electrostatic protection device connected to the power supply terminal, and the above-mentioned electrostatic protection device at the ground terminal
  • the power supply terminal is electrically connected to the heavily doped region of the second conductivity type of the electrostatic protection device connected to the power supply terminal
  • the input and output interface is connected to the heavily doped region of the first conductivity type of the electrostatic protection device connected to the power supply terminal.
  • the heterogeneous area is electrically connected; the ground terminal is electrically connected to the heavily doped region of the first conductivity type of the electrostatic protection device at the ground terminal, and the input and output interface is connected to the second conductivity type of the electrostatic protection device at the ground terminal.
  • the heavily doped regions are electrically connected.
  • the embodiment of the present application can reduce the capacitance of the electrostatic protection device, improve the response speed of the integrated circuit, and maintain the original electrostatic protection capability.
  • Fig. 1 is the schematic diagram of existing electrostatic protection circuit
  • FIGS. 2-4 are schematic diagrams of the planar structure and the corresponding cross-sectional structure of the electrostatic protection device connected to the power supply terminal provided by the embodiment of the present application;
  • FIG. 5-7 are schematic diagrams of the planar structure and the corresponding cross-sectional structure of the electrostatic protection device at the ground terminal provided by the embodiment of the present application.
  • the speed of the existing DRAM is getting faster and faster, which requires the I/O interface not only to have a reliable electrostatic protection capability, but also to have a relatively small capacitance.
  • the application provides an electrostatic protection device and an electrostatic protection circuit with low spot capacitance, which can provide an electrostatic protection solution with a fast response speed.
  • Fig. 1 shows a schematic diagram of an existing electrostatic protection circuit
  • the electrostatic protection circuit includes diodes 101, 102, and the diode 101 and the diode 102 are coupled in series.
  • a diode 101 is connected between the power supply terminal VDD and the input and output interface terminal I/O
  • the cathode of the diode 101 is coupled to the power supply terminal VDD
  • the anode is coupled to the input and output interface terminal I/O
  • a diode 102 is connected between the terminals I/O
  • the cathode of the diode 101 is coupled to the input/output interface terminal I/O
  • the anode is coupled to the power supply terminal VSS.
  • the capacitance of diodes 101 and 102 will affect the charging and discharging speed of the electrostatic protection circuit, and then affect the response speed of the electrostatic protection circuit. If the capacitance is large and the response speed is slow, the electrostatic protection circuit is not turned on in time, and the devices in the main circuit may be damaged by large currents. breakdown, damage.
  • An embodiment of the present application provides an electrostatic protection device connected to a power supply terminal, including: a substrate of the first conductivity type and a deep well region of the second conductivity type located in the substrate of the first conductivity type; and a deep well region located in the second conductivity type A doped region of the first conductivity type and a heavily doped region of the second conductivity type on the surface of the deep well region.
  • the doped region of the first conductivity type includes a heavily doped region of the first conductivity type and at least one of the following: a lightly doped region of the first conductivity type, a well region of the first conductivity type;
  • the heavily doped region of the first conductivity type is located in the lightly doped region of the first conductivity type or on the surface of the well region of the first conductivity type; the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type Miscellaneous interval settings.
  • the above-mentioned doped region of the first conductivity type includes a heavily doped region of the first conductivity type and a lightly doped region of the first conductivity type, then the lightly doped region of the first conductivity type surrounds the region of the first conductivity type Heavily doped region; the above device further includes a first well region and a second well region of the second conductivity type located on the deep well region of the second conductivity type and the substrate of the first conductivity type.
  • the first well region is adjacent to the lightly doped region of the first conductivity type and is at one end away from the heavily doped region of the second conductivity type
  • the second well region is adjacent to the heavily doped region of the second conductivity type and located at one end away from the heavily doped region of the first conductivity type.
  • the device further includes a deep well region of the second conductivity type and a well region of the first conductivity type.
  • the first well region and the second well region are respectively located on both sides of the well region of the first conductivity type, and the heavily doped region of the second conductivity type is located on the surface of the second well region.
  • the above-mentioned doped region of the first conductivity type includes a heavily doped region of the first conductivity type, a lightly doped region of the first conductivity type, and a well region of the first conductivity type
  • the well region of the first conductivity type Located on the surface of the deep well region of the second conductivity type, the lightly doped region of the first conductivity type is located on the surface of the well region of the first conductivity type, and the lightly doped region of the first conductivity type surrounds the heavily doped region of the first conductivity type.
  • the above-mentioned device also includes a first well region and a second well region of the second conductivity type located on the deep well region of the second conductivity type and the substrate surface of the first conductivity type; the first well region and the second well region The well regions are respectively located on both sides of the well region of the first conductivity type, and the heavily doped region of the second conductivity type is located on the surface of the second well region.
  • the above-mentioned heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type.
  • the above-mentioned device further includes a shallow trench isolation structure (Shallow Trench Isolation, STI), and the shallow trench isolation structure is located between the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type.
  • the shallow trench isolation structure is located between the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type, and is also located where the deep well region of the first conductivity type is far away from the deep well region of the second conductivity type. one end, and also located at the end of the deep well region of the second conductivity type away from the deep well region of the first conductivity type.
  • the depth of the shallow trench isolation structure is less than 0.3um.
  • the above-mentioned heavily doped region of the first conductivity type is connected to the input-output interface terminal, and the heavily doped region of the second conductivity type is connected to the power supply terminal.
  • the doping concentration and distribution of the heavily doped region of the first conductivity type of the device can be changed by adding a lightly doped region of the first conductivity type or a well region of the first conductivity type to increase The depletion region of the PN junction, thereby reducing the capacitance of the electrostatic protection device, and realizing the low capacitance requirement of the electrostatic protection device connected to the power supply end of the I/O circuit.
  • the doping concentration of the lightly doped region of the first conductivity type ranges from 10 19 to 10 20 atom/cm 3
  • the doping concentration of the well region of the first conductivity type ranges from 10 17 to 10 18 atom/cm 3.
  • the lightly doped region of the first conductivity type corresponds to a junction depth of 10-20nm, and the well region of the first conductivity type corresponds to a junction depth of 1.5-2um, so as to achieve the purpose of reducing the capacitance of the electrostatic protection device.
  • the doping concentration or energy of the heavily doped region of the first conductivity type remains unchanged.
  • the electrostatic protection device connected to the power supply terminal provided by the embodiment of the present application changes the doping concentration and Distribution to increase the depletion region of the PN junction, thereby reducing the capacitance of the electrostatic protection device, increasing the speed of the integrated circuit, and maintaining the original electrostatic protection capability.
  • the above-mentioned first conductivity type includes P type
  • the second conductivity type includes N type
  • Fig. 2 shows a schematic diagram of the planar structure and the corresponding cross-sectional structure of an electrostatic protection device connected to the power supply terminal provided by the embodiment of the present application, showing a P-type substrate 201 and an N-type deep In the well 202 , a P-type doped region and an N-type heavily doped region 205 are formed on the surface of the N-type deep well 202 .
  • the P-type doped region includes a P-type heavily doped region 203 and a P-type lightly doped region 204
  • the above-mentioned electrostatic protection device also includes a first N-type well across the surface of the N-type deep well 202 and the P-type substrate 201.
  • the well region 207 and the second N-type well region 206 are examples of the P-type doped region.
  • the first N-type well region 207 is adjacent to the P-type lightly doped region 204
  • the second N-type well region 206 is adjacent to the N-type heavily doped region 205 .
  • FIG. 2 also shows that both sides of the P-type lightly doped region 204 and the N-type heavily doped region 205 are provided with shallow trench isolation structures 208 .
  • the P-type heavily doped region 203 is connected to the input/output interface terminal I/O, and the N-type heavily doped region 205 is connected to the power supply terminal VDD.
  • Figure 3 shows a schematic diagram of the planar structure and its corresponding cross-sectional structure of another electrostatic protection device connected to the power supply terminal provided by the embodiment of the present application, showing a P-type substrate 301 and an N-type
  • the deep well 302 has a P-type doped region and an N-type heavily doped region 307 formed on the surface of the N-type deep well 302 .
  • the P-type doped region includes a P-type heavily doped region 303 and a P-type well region 304
  • the electrostatic protection device also includes a first N-type well across the surface of the N-type deep well 302 and the P-type substrate 301 region 306 and the second N-type well region 305 .
  • the first N-type well region 306 and the second N-type well region 305 are respectively located on two sides of the P-type well region 304 , and the N-type heavily doped region 307 is located on the surface of the second N-type well region 305 .
  • FIG. 3 also shows that both sides of the P-type heavily doped region 303 and the N-type heavily doped region 307 are provided with shallow trench isolation structures 308 .
  • the P-type heavily doped region 303 is connected to the input/output interface terminal I/O, and the N-type heavily doped region 307 is connected to the power supply terminal VDD.
  • Figure 4 shows a schematic diagram of the planar structure and its corresponding cross-sectional structure of another electrostatic protection device connected to the power supply terminal provided by the embodiment of the present application, showing a P-type substrate 401 and an N-type
  • the deep well 402 has a P-type doped region and an N-type heavily doped region 403 formed on the surface of the N-type deep well 402 .
  • the P-type doped region includes a P-type heavily doped region 405 , a P-type lightly doped region 404 and a P-type well region 406 .
  • the P-type well region 406 is located on the surface of the N-type deep well 402
  • the P-type lightly doped region 404 is located on the surface of the P-type well region 406
  • the P-type heavily doped region 405 is located in the P-type lightly doped region 404 .
  • the diode also includes a first N-type well region 408 and a second N-type well region 407 across the surface of the N-type deep well 402 and the P-type substrate 401; the first N-type well region 408 and the second N-type well region 407 are respectively located on both sides of the P-type well region 406 , and the N-type heavily doped region is located on the surface of the second N-type well region 407 .
  • the P-type heavily doped region 405 is connected to the input/output interface terminal I/O, and the N-type heavily doped region 403 is connected to the power supply terminal VDD.
  • An embodiment of the present application provides an electrostatic protection device for a ground terminal, including a substrate of the first conductivity type, a doped region of the second conductivity type located in the substrate of the first conductivity type, and a heavily doped region of the second conductivity type district.
  • the doped region of the second conductivity type includes a heavily doped region of the second conductivity type and at least one of the following: a lightly doped region of the second conductivity type and a well region of the second conductivity type.
  • the above-mentioned heavily doped region of the second conductivity type is located in the lightly doped region of the second conductivity type or on the surface of the well region of the second conductivity type; the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type Interval setting.
  • the doped region of the second conductivity type includes a heavily doped region of the second conductivity type and a lightly doped region of the second conductivity type; On the bottom surface, the lightly doped region of the second conductivity type surrounds the heavily doped region of the second conductivity type.
  • the doped region of the second conductivity type includes a heavily doped region of the second conductivity type and a well region of the second conductivity type; then the well region of the second conductivity type is located on the surface of the substrate of the first conductivity type, and the second conductivity type The heavily doped region of the second conductivity type is located on the surface of the well region of the second conductivity type.
  • the doped region of the second conductivity type includes a heavily doped region of the second conductivity type, a lightly doped region of the second conductivity type, and a well region of the second conductivity type; then the well region of the second conductivity type is located The substrate surface of the first conductivity type, the lightly doped region of the second conductivity type is located on the surface of the well region of the second conductivity type, and the lightly doped region of the second conductivity type surrounds the heavily doped region of the second conductivity type.
  • the above-mentioned heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type.
  • the above device further includes a shallow trench isolation structure, and the shallow trench isolation structure is located between the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type.
  • the above-mentioned heavily doped region of the second conductivity type is connected to the input-output interface terminal, and the heavily doped region of the first conductivity type is connected to the ground terminal.
  • the doping concentration and distribution of the heavily doped region of the second conductivity type of the device can be changed by adding a lightly doped region of the second conductivity type or a well region of the second conductivity type to increase The depletion region of the PN junction, thereby reducing the capacitance of the electrostatic protection device, and realizing the low capacitance demand of the electrostatic protection device on the ground terminal of the I/O circuit.
  • the doping concentration of the lightly doped region of the second conductivity type ranges from 10 19 to 10 20 atom/cm 3
  • the doping concentration of the well region of the second conductivity type ranges from 10 17 to 10 18 atom/cm 3
  • the lightly doped region of the second conductivity type corresponds to a junction depth of 10-20nm
  • the well region of the second conductivity type corresponds to a junction depth of 1.5-2um, thereby achieving electrostatic protection purpose of device capacitance reduction.
  • the doping concentration or energy of the heavily doped region of the second conductivity type remains unchanged.
  • the electrostatic protection device at the ground terminal changes the doping concentration and distribution of the heavily doped region of the second conductivity type of the device by adding a lightly doped region of the second conductivity type or a well region of the second conductivity type , to increase the depletion region of the PN junction, thereby reducing the capacitance of the electrostatic protection device and improving the speed of the integrated circuit, and maintaining the original electrostatic protection capability.
  • the above-mentioned first conductivity type includes P type
  • the second conductivity type includes N type.
  • N-type heavily doped region/Pwell electrostatic protection device as an example, specific implementations of various ground terminal electrostatic protection devices provided in the embodiments of the present application will be described in detail.
  • Fig. 5 shows a schematic diagram of the planar structure and its corresponding cross-sectional structure of an electrostatic protection circuit for a ground terminal provided by an embodiment of the present application, showing a P-type substrate 501 and an N-type doped layer located in the P-type substrate 501. region and the P-type heavily doped region 504.
  • the N-type doped region includes an N-type heavily doped region 503 and an N-type lightly doped region 502; the N-type lightly doped region 502 is located on the surface of the N-type substrate 501, and the N-type heavily doped region 503 is located In the doped region 502.
  • FIG. 5 also shows that the N-type heavily doped region 503 is connected to the input/output interface terminal I/O, and the P-type heavily doped region 504 is connected to the ground terminal VSS.
  • FIG. 5 also shows that both sides of the P-type heavily doped region 504 and the N-type lightly doped region 502 are provided with shallow trench isolation structures 505 .
  • Fig. 6 shows a schematic diagram of the planar structure and its corresponding cross-sectional structure of another electrostatic protection circuit for the ground terminal provided by the embodiment of the present application, showing a P-type substrate 601 and an N-type dopant in the P-type substrate 601. impurity region and P-type heavily doped region 604.
  • the N-type doped region includes an N-type heavily doped region 602 and an N-type well region 603; the N-type well region 603 is located on the surface of the N-type substrate 601, and the N-type heavily doped region 703 is located on the surface of the N-type well region 603.
  • FIG. 6 also shows that the N-type heavily doped region 602 is connected to the input/output interface terminal I/O, and the P-type heavily doped region 604 is connected to the ground terminal VSS.
  • FIG. 6 also shows that both sides of the P-type heavily doped region 604 and the N-type heavily doped region 602 are provided with shallow trench isolation structures 605 .
  • Fig. 7 shows a schematic diagram of the plane structure and its corresponding cross-sectional structure of another electrostatic protection circuit for the ground terminal provided by the embodiment of the present application, showing a P-type substrate 701 and an N-type dopant in the P-type substrate 701. impurity region and P-type heavily doped region 705.
  • the N-type doped region includes an N-type heavily doped region 702, an N-type lightly doped region 703, and an N-type well region 704; the N-type well region 704 is located on the surface of the N-type substrate 701, and the N-type lightly doped region 703 Located on the surface of the N-type well region 704 , the N-type heavily doped region 702 is located in the N-type lightly doped region 703 .
  • FIG. 7 also shows that both sides of the P-type heavily doped region 705 and the N-type heavily doped region 703 are provided with shallow trench isolation structures 706 .
  • the embodiment of the present application introduces NMLDD and PMLDD through double diffusion on the basis of the original electrostatic protection circuit, changes the doping concentration and distribution of N+ and P+, reduces the capacitance of the electrostatic protection device, and realizes the improvement of the speed of the integrated circuit. At the same time, the original electrostatic protection ability is maintained.
  • the embodiment of the present application also provides an electrostatic protection circuit, including a power supply terminal, a ground terminal, and an input and output interface terminal between the power supply terminal and the ground terminal, as well as the above-mentioned electrostatic protection device connected to the power supply terminal, and the above-mentioned electrostatic protection device at the ground terminal.
  • the power supply terminal is electrically connected to the heavily doped region of the second conductivity type of the electrostatic protection device connected to the power supply terminal, and the input and output interface is electrically connected to the heavily doped region of the first conductivity type of the electrostatic protection device connected to the power supply terminal; grounding The terminal is electrically connected to the heavily doped region of the first conductivity type of the electrostatic protection device at the grounding terminal, and the input and output interface is electrically connected to the heavily doped region of the second conductivity type of the electrostatic protection device at the grounding terminal.
  • the above-mentioned low-capacitance electrostatic protection circuit provided by the embodiment of the present application has a relatively low capacitance of the electrostatic protection device, improves the speed of the integrated circuit, and maintains the original electrostatic protection capability.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un dispositif de protection électrostatique et un circuit de protection électrostatique. Le dispositif de protection électrostatique comprend : un substrat d'un premier type de conductivité, et une région de puits profond d'un second type de conductivité située à l'intérieur du substrat du premier type de conductivité ; et une région dopée du premier type de conductivité située sur la surface de la région de puits profond du second type de conductivité, et une région fortement dopée du second type de conductivité. La région dopée du premier type de conductivité comprend une région fortement dopée du premier type de conductivité, et au moins une région légèrement dopée du premier type de conductivité et une région de puits du premier type de conductivité. La région fortement dopée du premier type de conductivité est située à l'intérieur de la région légèrement dopée du premier type de conductivité ou sur la surface de la région de puits du premier type de conductivité ; la région fortement dopée du second type de conductivité est espacée de la région fortement dopée du premier type de conductivité.
PCT/CN2021/117226 2021-08-06 2021-09-08 Dispositif de protection électrostatique et circuit de protection électrostatique WO2023010648A1 (fr)

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CN202110901938.0 2021-08-06
CN202110901938.0A CN115706109A (zh) 2021-08-06 2021-08-06 静电保护器件及静电保护电路

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030234405A1 (en) * 2002-06-25 2003-12-25 Macronix International Co., Ltd. Silicon controlled rectifier structure with guard ring controlled circuit
CN105977251A (zh) * 2015-03-13 2016-09-28 台湾积体电路制造股份有限公司 用于差分信号器件的静电放电保护器件
CN106158744A (zh) * 2015-04-16 2016-11-23 上海箩箕技术有限公司 静电保护结构及其制作方法、芯片及其制作方法
CN111524884A (zh) * 2020-04-15 2020-08-11 电子科技大学 一种用于高压esd保护的改进型ldmos-scr器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030234405A1 (en) * 2002-06-25 2003-12-25 Macronix International Co., Ltd. Silicon controlled rectifier structure with guard ring controlled circuit
CN105977251A (zh) * 2015-03-13 2016-09-28 台湾积体电路制造股份有限公司 用于差分信号器件的静电放电保护器件
CN106158744A (zh) * 2015-04-16 2016-11-23 上海箩箕技术有限公司 静电保护结构及其制作方法、芯片及其制作方法
CN111524884A (zh) * 2020-04-15 2020-08-11 电子科技大学 一种用于高压esd保护的改进型ldmos-scr器件

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