WO2023005609A1 - 阵列基板及其制备方法、发光装置和拼接显示装置 - Google Patents
阵列基板及其制备方法、发光装置和拼接显示装置 Download PDFInfo
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- WO2023005609A1 WO2023005609A1 PCT/CN2022/103454 CN2022103454W WO2023005609A1 WO 2023005609 A1 WO2023005609 A1 WO 2023005609A1 CN 2022103454 W CN2022103454 W CN 2022103454W WO 2023005609 A1 WO2023005609 A1 WO 2023005609A1
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Classifications
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/1336—Illuminating devices
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- G02F1/133603—Direct backlight with LEDs
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/1336—Illuminating devices
- G02F1/133602—Direct backlight
- G02F1/133605—Direct backlight including specially adapted reflectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Definitions
- the present application relates to the field of display technology, in particular to an array substrate and a preparation method thereof, a light emitting device and a spliced display device.
- Mini LED Mini Light Emitting Diode, sub-millimeter light-emitting diode
- Micro LED Micro Light Emitting Diode, micro-light-emitting diode
- One of the advantages of Micro/mini LED display products is that it can realize large-area splicing, that is, splicing with multiple array substrates, so as to obtain super-sized display products.
- an array substrate comprising:
- Both the device region and the peripheral region include a substrate and a reflective layer on the substrate;
- the device region also includes an interlayer dielectric layer and a plurality of devices, the interlayer dielectric layer is located at least between the substrate and the reflective layer; the reflective layer has a direction perpendicular to the substrate a plurality of hollowed out areas, the device is located in the hollowed out areas;
- the orthographic projection of the reflective layer on the part of the substrate located in the device region overlaps with the orthographic projection of the interlayer dielectric layer on the substrate, and the reflective layer is located in the peripheral
- the part of the region covers the part of the substrate located in the peripheral region, and the outer contour of the substrate is consistent with the outer contour of the peripheral region of the array substrate;
- the device at least includes a light emitting device.
- the reflective layer includes a first reflective sublayer and a second reflective sublayer, and the second reflective sublayer is located on a side of the first reflective sublayer away from the substrate;
- the orthographic projection of the first reflective sublayer on the substrate is located in the device region and the peripheral region;
- the orthographic projection of the part of the first reflective sublayer located in the device region on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate, and the first The reflective sublayer also covers the portion of the substrate located in the peripheral region;
- the orthographic projection of the second reflective sublayer on the substrate is located within the orthographic projection of the first reflective sublayer on the substrate.
- the orthographic projection of the second reflective sublayer on the substrate is located in the device region
- the orthographic projection of the second reflective sublayer on the substrate does not overlap with the orthographic projection of the part of the first reflective sublayer located in the peripheral region on the substrate.
- the orthographic projection of the second reflective sublayer on the substrate is located in the peripheral region and the device region;
- the orthographic projection of the part of the second reflective sublayer located in the peripheral region on the substrate overlaps with the orthographic projection of the part of the first reflective sublayer located in the peripheral region on the substrate.
- the first reflective sublayer and the second reflective sublayer have the same thickness along a direction perpendicular to the substrate.
- the array substrate further includes an auxiliary reflection part; the auxiliary reflection part is located on the interlayer dielectric layer, and the auxiliary reflection part is connected to the reflection layer.
- the auxiliary reflective part includes a first reflective part and a second reflective part, and the first reflective part and the second reflective part are integrated;
- the hollow area exposes a part of the interlayer dielectric layer, and the first reflective portion
- the orthographic projection on the substrate is located in the hollow area and is in direct contact with the interlayer dielectric layer;
- the second reflective part is in direct contact with the surface of the reflective layer away from the substrate, and the orthographic projection of the second reflective part on the substrate is the same as the orthographic projection of the reflective layer on the substrate overlap.
- the array substrate further includes a plurality of packaging units corresponding to the devices, and the orthographic projection of the packaging units on the substrate covers the area of the device on the substrate. Orthographic projection, and the orthographic projection of the packaging unit on the substrate partly overlaps with the orthographic projection of the reflective layer on the substrate.
- the device region of the array substrate includes a buffer layer and a first conductive layer sequentially disposed on the substrate, and the interlayer dielectric layer is located away from the first conductive layer. one side of the substrate;
- the interlayer dielectric layer includes a first insulating layer and a first planar layer, and the first planar layer is at least located between the first insulating layer and the reflective layer.
- the device region of the array substrate further includes a second conductive layer, a second insulating layer, a second planar layer, and a third insulating layer that are sequentially stacked on the buffer layer,
- the third insulating layer is located on a side of the first conductive layer away from the first insulating layer.
- the first conductive layer includes at least one first pad and at least one second pad
- the interlayer dielectric layer has a plurality of first pads along a direction perpendicular to the substrate. an opening and a plurality of second openings, the first opening exposes the area where the first pad is located, and the second opening exposes the area where the second pad is located;
- the first pad is electrically connected to the first soldering leg of the device through the first opening
- the second soldering pad is electrically connected to the second soldering leg of the device through the second opening
- the array substrate further includes support columns, the support columns are located on the side of the reflective layer away from the substrate, and the orthographic projection of the support columns on the substrate do not overlap with the orthographic projection of the device on the substrate.
- Embodiments of the present application also provide a light emitting device, including the above-mentioned array substrate.
- the light-emitting device further includes a diffusion plate, a quantum dot film, a diffusion sheet, and a composite film that are sequentially stacked;
- the diffusion plate is located on the light emitting side of the array substrate.
- An embodiment of the present application also provides a spliced display device, comprising at least two light emitting devices as described above.
- the embodiment of the present application also provides a method for preparing an array substrate, which is applied to prepare the above-mentioned array substrate, and the method includes:
- the motherboard substrate is divided into at least one device region and a cutting region adjacent to the device region;
- a reflective layer is formed on the device area and the cutting area of the motherboard substrate; wherein, the reflective layer has a plurality of hollowed-out regions along a direction perpendicular to the motherboard substrate; the interlayer The dielectric layer is located at least between the motherboard substrate and the reflective layer; the orthographic projection of the part of the reflective layer located in the device area on the motherboard substrate is the same as that of the interlayer dielectric layer in the The orthographic projections on the motherboard substrate overlap, and the part of the reflective layer located in the cutting region covers the cutting region of the motherboard substrate;
- the method further includes:
- the edge of the array substrate is ground by a vertical grinding process.
- the step of grinding the edge of the array substrate using a vertical grinding process includes:
- the side surfaces of the substrate of the array substrate and the side surfaces of the reflective layer are simultaneously ground; wherein, the side surfaces of the substrate and the side surfaces of the reflective layer are coplanar .
- the step of forming a reflective layer on the device region and the cutting region of the motherboard substrate includes:
- the orthographic projection of the first reflective sublayer on the motherboard substrate is located in the device region and the cutting region;
- the orthographic projection of the first reflective sublayer on the motherboard substrate is located in the device region and the cutting region;
- the orthographic projection of the second reflective sublayer on the motherboard substrate is located within the device region and the cutting region.
- the method further includes:
- An auxiliary reflection part is formed on the interlayer dielectric layer; wherein the auxiliary reflection part is connected to the reflection layer.
- Figures 1a-5 are schematic structural views of nine types of array substrates provided by the embodiments of the present application.
- FIG. 6 is a schematic structural diagram of a light emitting device provided by an embodiment of the present application.
- FIG. 7 is a schematic structural diagram of a spliced display device provided by an embodiment of the present application.
- Fig. 8a is a microscopic interferogram of scratches on the packaging unit of the array substrate and knife marks on the reflective layer in a related art provided by the embodiment of the present application;
- Fig. 8b is a micrograph of knife marks on the reflective layer of an array substrate in a related art provided in the embodiment of the present application;
- Fig. 8c is a schematic structural diagram of a cutting wheel provided in the embodiment of the present application.
- Fig. 8d is a schematic diagram of a cutter wheel front cutting process provided by the embodiment of the present application.
- FIG. 9 is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application.
- FIG. 10 is a schematic structural diagram of a motherboard of an array substrate provided in an embodiment of the present application.
- FIG. 11 is a schematic structural diagram of a motherboard of another array substrate provided by an embodiment of the present application.
- Figure 12a, Figure 13a and Figure 14 are schematic diagrams of three back cutting processes provided by the embodiment of the present application.
- Figure 12b is a schematic diagram of the position of the cutting line corresponding to the cutting process of Figure 12a;
- Figure 13b is a schematic diagram of the position of the cutting line corresponding to the cutting process of Figure 13a;
- Fig. 15a is a schematic diagram of a polishing process of an array substrate in a related art provided by an embodiment of the present application.
- FIG. 15b and FIG. 15c are two structural schematic diagrams of the grinding area of the array substrate prepared by the grinding process of FIG. 15a;
- FIG. 16 is a schematic diagram of a grinding process of an array substrate provided in an embodiment of the present application.
- Fig. 17a is a schematic structural diagram of a splicing display device in a related art provided by an embodiment of the present application.
- Fig. 17b is a schematic structural diagram of a spliced display device provided by an embodiment of the present application.
- Fig. 18 is a schematic structural diagram of a vacuum chuck provided by an embodiment of the present application.
- plural means two or more; the orientation or positional relationship indicated by the term “upper” is based on the orientation or positional relationship shown in the drawings, It is only for the convenience of describing the present application and simplifying the description, but does not indicate or imply that the structures or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
- words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect. Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity.
- Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
- the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
- example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
- the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
- An embodiment of the present application provides an array substrate, as shown in FIG. 1a or FIG. 2a, including:
- both the device region A and the peripheral region B include a substrate 1 and a reflective layer 20 located on the substrate 1;
- the device region A also includes an interlayer dielectric layer 30 and a plurality of devices 12, the interlayer dielectric layer 30 is located at least between the substrate 1 and the reflective layer 20; the reflective layer 20 has a plurality of hollowed out regions along the direction perpendicular to the substrate 1 L, the device 12 is located in the hollow area L;
- the orthographic projection of the part of the reflective layer 20 located in the device region A on the substrate 1 overlaps with the part of the orthographic projection of the interlayer dielectric layer 30 on the substrate 1, and the part of the reflective layer 20 located in the peripheral region B covers the substrate 1
- the part located in the peripheral area B, and the outer contour of the substrate 1 is consistent with the outer contour of the peripheral area B of the array substrate.
- a variety of devices 12 arranged in an array are arranged in the device area A on the array substrate.
- the devices 12 include at least light-emitting devices, and may also include any one of sensor devices, micro-drive chips or other types of devices. It can be understood that , different types of devices have different numbers, or different types of devices have different array arrangement densities.
- the peripheral area B is the area between the device area A and the boundary of the array substrate; in the actual production process, each array substrate is formed by cutting the motherboard, that is, the size of the peripheral area B can be determined according to the actual cutting process.
- the width of the peripheral region B is the distance between the boundary of the array substrate and the device region A, and the width of the peripheral region B ranges from 0.2mm to 2mm; for example, it can be 0.2mm, 1mm, 1.2mm, 1.5 mm or 2mm.
- the area except the peripheral area B is the device area A without considering the bonding area.
- the distance between the geometric center of the orthographic projection of the device 12 located in the upper left corner of the array substrate on the substrate 1 along the X direction to the edge of the array substrate is 4mm, and the outer contour of the device region A
- the distance along the X direction to the outer contour of the peripheral area B is 0.7mm;
- the distance between the outer contour of the device region A and the outer contour of the peripheral region B along the Y direction is 0.7mm. That is, all the devices on the array substrate are located in the area where the device area A is located.
- Substrate 1 can be rigid substrate, and the material of rigid substrate can be any one in glass, quartz, PET, plastics, and the thickness of rigid substrate can be 0.2mm-1mm, example, the thickness of rigid substrate is 0.2mm, 0.4mm, 0.5mm, 0.7mm or 1mm.
- the light emitting device may be a submillimeter light emitting diode (Mini Light Emitting Diode, English abbreviation is Mini LED) or a micro light emitting diode (Micro Light Emitting Diode, English abbreviation is Micro LED), which is not limited here.
- Mini LED Mini Light Emitting Diode
- Micro LED Micro Light Emitting Diode
- the plurality of devices 12 may all be blue-emitting submillimeter light-emitting diodes or miniature light-emitting diodes, or the plurality of devices 12 may simultaneously include three types of light-emitting diodes or micro-light emitting diodes that emit red light, green light, and blue light. diode.
- the reflective layer 20 can reflect the light emitted by the light-emitting device to the light-emitting surface of the array substrate, so as to improve the light utilization efficiency of the light-emitting device.
- the color of the reflective layer 20 is white, so that the reflective layer 20 has a higher reflectivity.
- the reflective layer 20 may be a sheet structure with multiple hollowed out regions L, or the reflective layer 20 may also be fabricated on the array substrate by sputtering, coating, coating and other processes.
- the material of the reflective layer 20 may include white ink, and the components of the white ink include resin (for example, epoxy resin, polytetrafluoroethylene resin), titanium dioxide (chemical formula TiO2) and organic solvent (for example, dipropylene glycol methyl ether )wait.
- resin for example, epoxy resin, polytetrafluoroethylene resin
- titanium dioxide chemical formula TiO2
- organic solvent for example, dipropylene glycol methyl ether
- the material of the reflective layer 20 may also include silicon-based white glue.
- the reflective layer 20 can be formed by printing with a screen printing process, or sprayed with a glue valve spraying process to form the reflective layer 20 .
- the distance T1 between the surface of the reflective layer 20 in contact with the interlayer dielectric layer 30 and the surface away from the interlayer dielectric layer 30 may range from 10 ⁇ m to 300 ⁇ m, for example, the thickness may be 10 ⁇ m, 50 ⁇ m, 55 ⁇ m, 60 ⁇ m, 80 ⁇ m, 155 ⁇ m, 200 ⁇ m or 300 ⁇ m.
- the reflective layer 20 can be formed by one or more screen printing processes.
- the portion of the reflective layer 20 located at the edge of the hollowed-out area L may be stepped.
- the shape of the orthographic projection of the hollow area L on the substrate 1 may be a circle, a triangle, or a rectangle.
- the part of the conductive pattern on the substrate 1 exposed by the hollow area L on the reflective layer 20 is used to connect with the device 12, and the part of the conductive pattern covered by the reflective layer 20 is used to connect with the external signal source circuit so that Electrical signals are received and transmitted to device 12 .
- the interlayer dielectric layer 30 is located at least between the substrate 1 and the reflective layer 20 is: as shown in FIG.
- a part of the interlayer dielectric layer 30 is provided in a part of the region between the conductive patterns (for example, between the conductive pads 71 and 72), and the part of the interlayer dielectric layer 30 is located between the substrate 1 and the substrate 1. between devices 12.
- the interlayer dielectric layer 30 has a plurality of first openings K1 and a plurality of second openings K2 along a direction perpendicular to the substrate 1 .
- the orthographic projection of the first opening K1 and/or the second opening K2 on the substrate 1 is within the range of the orthographic projection of the hollow area L on the substrate 1 .
- the first opening K1 in the interlayer dielectric layer 30 exposes a part of the conductive pattern provided on the substrate 1, and the second opening K2 in the interlayer dielectric layer 30 exposes another part of the conductive pattern provided on the substrate 1, so that The device 12 is connected to the conductive pattern, and the conductive pattern is connected to an external signal source circuit to receive electrical signals.
- both the device area A and the peripheral area B are provided with a reflective layer 20, for example: as shown in FIG. 1a or FIG. 2a, the orthographic projection of the reflective layer 20 on the array substrate does not overlap with the hollow area L .
- the part of the reflective layer 20 disposed in the device region A is located on the side of the interlayer dielectric layer 30 away from the substrate 1, and according to the material and/or manufacturing process of the reflective layer 20, the reflective layer 20 is formed on the substrate There are different overlapping situations between the orthographic projection on the substrate 1 and the orthographic projection of the interlayer dielectric layer 30 on the substrate 1 .
- the boundary of the reflective layer 20 at the hollow area L is stepped, and part of the interlayer dielectric layer 30 located at the hollow area L is not covered by the reflective layer 20 .
- FIG. 3 shows a schematic structural view of an array substrate in which the reflective layer 20 is not disposed in the peripheral area B of the substrate 1.
- the reflective layer 20 covers the device area A of the array substrate except for the hollow area L. Almost all of the area, but does not cover the peripheral area B of the substrate 1.
- the array substrate shown in FIG. 3 emits light, there is no device 12 in the peripheral area B, and no reflective layer 20 reflects light, thus presenting a relatively dark visual effect, that is, the luminous effect is not good.
- the outer contour of the peripheral area B of the array substrate is the outer contour of the substrate 1
- the reflective layer 20 is located in the peripheral area B Covering the peripheral region B of the substrate 1, therefore, the part of the reflective layer 20 located in the peripheral region B can extend to the outer contour of the substrate 1, so that when the array substrate emits light, the reflective layer 20 of the peripheral region B can emit light from the device region A. And the light incident on its surface is reflected, which greatly improves the problem of the large optical brightness difference between the peripheral area B of the array substrate and the device area A, and can increase the brightness of the array substrate along the direction perpendicular to the plane where the substrate 1 is located. The amount of light output on the substrate, thereby improving the light extraction efficiency of the array substrate.
- the reflective layer 20 includes a first reflective sublayer 10 and a second reflective sublayer 11, and the second reflective sublayer 11 is located away from the first reflective sublayer 10.
- One side of the substrate 1; the orthographic projection of the first reflective sublayer 10 on the substrate 1 is located in the device region A and the peripheral region B;
- the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located within the orthographic projection of the first reflective sublayer 10 on the substrate 1 .
- the reflective layer 20 does not need to be arranged, and on the interlayer dielectric layer 30 outside the area where the device 12 is located
- the reflective layer 20 is set so that the orthographic projection of the reflective layer 20 on the substrate 1 partially overlaps the orthographic projection of the interlayer dielectric layer 30 on the substrate 1 .
- the orthographic projection of the part of the first reflective sublayer 10 located in the device region A on the substrate 1 overlaps with the orthographic projection of the interlayer dielectric layer 30 on the substrate 1.
- the first reflective sublayer 10 in the reflective layer 20 may extend toward the direction in which the first reflective sublayer 10 points to the device 12, so that the first reflective sublayer 10 covers as shown in Figure 1a
- the part of the interlayer dielectric layer 30 that is located in the hollow area L and does not overlap with the orthographic projection of the device 12 on the substrate 1 is shown in .
- the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located within the orthographic projection of the first reflective sublayer 10 on the substrate 1 .
- the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located in the device region A and the peripheral region B, and the part of the second reflective sublayer 11 disposed in the device region A is on the substrate 1
- the orthographic projection of the first reflective sublayer 10 on the substrate 1 is located within the orthographic projection of the part of the first reflective sublayer 10 disposed in the device region A, and the orthographic projection of the part of the second reflective sublayer 11 located in the peripheral region B on the substrate 1 is within the same range as the first reflective sublayer 11.
- the orthographic projections of the portion of a reflective sub-layer 10 located in the peripheral region B on the substrate 1 overlap.
- the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located in the device area A and the peripheral area B, and the orthographic projection of the part of the second reflective sublayer 11 disposed in the device area A on the substrate 1 is located in the first reflective sublayer 11.
- the sublayer 10 is arranged within the orthographic projection of the part of the device region A on the substrate 1, and the orthographic projection of the part of the second reflective sublayer 11 arranged on the peripheral region B on the substrate 1 is located within the part of the first reflective sublayer 10.
- the part in the peripheral zone B is within the orthographic projection on the substrate 1 .
- the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located in the device region A, and the second reflective sublayer 11 is not provided in the peripheral region B, and the second reflective sublayer 11 is formed on the substrate 1.
- the orthographic projection on is located within the orthographic projection of the part of the first reflective sublayer 10 disposed on the device region A on the substrate 1 .
- the orthographic projection of the first reflective sublayer 10 on the substrate 1 may be located within the orthographic projection of the second reflective sublayer 11 on the substrate 1 .
- the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located within the orthographic projection of the first reflective sublayer 10 on the substrate 1 as an example.
- the first reflective sublayer 10 covers the edge of the substrate 1, and the second reflective sublayer 11 shrinks toward the device region A; so that the edge of the second reflective sublayer 11 reaches the substrate
- the range of the distance H1 between the edges of 1 is controlled within 0.2-2mm.
- the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 can be 0.2mm, 0.4mm, 0.5mm, 0.8mm, 1mm, 1.5mm, 1.8mm or 2mm, the second reflective
- the specific value of the distance H1 between the edge of the sub-layer 11 and the edge of the substrate 1 may be determined according to the design of the array substrate, the manufacturing process or the cutting process of the array substrate.
- FIG. 2d a top view of an array substrate is shown, wherein FIG. 2a is a cross-sectional view along the M1M2 direction of FIG. 2d .
- a plurality of devices 12 are arranged in an array in the device area A, the reflective layer 20 in the device area A includes the first reflective sublayer 10 and the second reflective sublayer 11, and the reflective layer 20 in the peripheral area B includes The first reflective sublayer 10 .
- the device 12 depicted in Figure 2d is a light emitting device.
- the materials included in the first reflective sublayer 10 and the second reflective sublayer 11 may be different, for example: the material of the first reflective sublayer 10 may include white ink, and the material of the second reflective sublayer 11 may include Silicon-based white glue; or, the material of the first reflective sub-layer 10 may include white ink, and the material of the second reflective sub-layer 11 may include a reflective sheet.
- the first reflective sublayer 10 and the second reflective sublayer 11 may be made of the same material, for example: the materials of the first reflective sublayer 10 and the second reflective sublayer 11 both include white ink.
- the materials of the first reflective sublayer 10 and the second reflective sublayer 11 include white ink or silicon-based white glue
- the first reflective sublayer 10 and the second reflective sublayer 11 can be printed and formed respectively by using a screen printing process.
- the thickness range of the first reflective sublayer 10 along the direction perpendicular to the substrate 1 may be 25 ⁇ m-35 ⁇ m, for example: 25 ⁇ m, 28 ⁇ m, 30 ⁇ m, 32 ⁇ m or 35 ⁇ m.
- the thickness range of the second reflective sublayer 11 along the direction perpendicular to the substrate 1 may be 25 ⁇ m-35 ⁇ m, for example: 25 ⁇ m, 28 ⁇ m, 30 ⁇ m, 32 ⁇ m or 35 ⁇ m.
- the second reflective sublayer 11 is located in the device region A; the orthographic projection of the second reflective sublayer 11 on the substrate 1 does not overlap with the peripheral region B.
- the peripheral area B refers to the area between the device area A and the boundary (cutting line) of the array substrate during the preparation of the array substrate
- the first reflective sublayer is arranged on the substrate 1 in the peripheral area B 10, without setting the second reflective sub-layer 11, on the one hand, it can improve the film peeling (Peeling) problem of the reflective layer 20 caused by the cutting process when the motherboard is cut into an array substrate;
- the first reflective sublayer 10 is set on the substrate 1, and the first reflective sublayer 10 covers the outer contour of the substrate 1, so that when the array substrate emits light, the first reflective sublayer 10 in the peripheral area B can emit light from the array substrate.
- the light reflected from the array substrate improves the large difference in optical brightness between the peripheral area B of the array substrate and the device area A, and largely increases the amount of light output from the array substrate along the direction perpendicular to the plane where the substrate 1 is located, thereby improving The light extraction efficiency of the array substrate.
- the materials of the first reflective sublayer 10 and the second reflective sublayer 11 both include white ink
- the thickness range of the first reflective sublayer 10 and the second reflective sublayer 11 is 25-35 ⁇ m 2a
- the difference in the reflectance value of the reflective layer 20 in the device area A and the reflective layer 20 in the peripheral area B to light is within 5%, which will not cause the difference between the device area A and the peripheral area B. Obvious optical difference.
- the boundaries of the sub-layer 10 and the second reflective sub-layer 11 substantially coincide with the outer contour of the substrate 1, so that when the array substrate emits light, the first reflective sub-layer 10 and the second reflective sub-layer 11 in the peripheral area B can reflect the array substrate The emitted light is reflected, and under the dual effects of the first reflective sublayer 10 and the second reflective sublayer 11, the problem of large optical brightness difference between the peripheral area B of the array substrate and the device area A can be well improved.
- the array substrate further includes a binding area D located on one side thereof, the reflecting layer 20 is not provided in the binding area D, and the binding area D includes a plurality of binding terminal groups 107 One end of the binding terminal group 107 is used to connect with the gold finger structure of an external circuit (circuit board or integrated circuit) to receive electrical signals, and the other end is connected to a conductive pattern on the array substrate, such as a signal line, to transmit electrical signals.
- an external circuit circuit board or integrated circuit
- the first reflective sublayer 10 and the second reflective sublayer 11 have the same thickness along a direction perpendicular to the substrate 1 .
- the thicknesses of the first reflective sublayer 10 and the second reflective sublayer 11 along the direction perpendicular to the substrate 1 are both 25 ⁇ m, or both 30 ⁇ m, or both 35 ⁇ m.
- the array substrate further includes an auxiliary reflective portion 13 ; the auxiliary reflective portion 13 is located on the interlayer dielectric layer 30 , and the auxiliary reflective portion 13 is connected to the reflective layer 20 .
- the orthographic projection of the reflective layer 20 on the substrate 1 covers the part of the interlayer dielectric layer 30 except the hollow region L.
- the orthographic projection of the reflective layer 20 on the substrate 1 falls into the interlayer dielectric layer 30. Therefore, in order to ensure the reflective effect, after the reflective layer 30 is provided, the auxiliary reflective part 13 is provided to enhance the reflective effect.
- the interlayer dielectric layer 30 is located in the part of the hollow area L.
- the auxiliary reflection part 13 can be provided on the part of the interlayer dielectric layer 30 to cover the exposed part of the interlayer dielectric layer 30 on the edge of the hollow area L. Part of the surface, so as to further increase the amount of light output from the array substrate along the direction perpendicular to the plane where the substrate 1 is located, thereby improving the light extraction efficiency of the array substrate.
- the auxiliary reflective part 13 is provided at the sidewall of the hollowed out area L of the reflective layer 20 , which can reduce the radial size of the hollowed out area L and improve the dimensional accuracy of the hollowed out area L.
- the radial dimension of the hollow area L is not reduced for marking.
- the distance T2 between the surface of the auxiliary reflective portion 13 in contact with the interlayer dielectric layer 30 and the surface of the auxiliary reflective portion 13 away from the interlayer dielectric layer 30 is greater than that between the reflective layer 20 and the interlayer dielectric layer 30 .
- the distance T1 between the surface in contact with the dielectric layer 30 and the surface of the reflective layer 20 away from the interlayer dielectric layer 30 is greater than that between the reflective layer 20 and the interlayer dielectric layer 30 .
- the distance T2 between the surface of the auxiliary reflection part 13 in contact with the interlayer dielectric layer 30 and the surface of the auxiliary reflection part 13 away from the interlayer dielectric layer 30 may range from 50 ⁇ m to 80 ⁇ m;
- the distance T1 between the surface in contact with the dielectric layer 30 and the surface of the reflective layer 20 away from the interlayer dielectric layer 30 may range from 30 ⁇ m to 50 ⁇ m.
- auxiliary reflective part 13 can be provided on the edge surrounding the hollow area L through a spraying process.
- the material of the auxiliary reflective part 13 includes silicon-based white glue, and the color of the silicon-based white glue is white, so that the color of the auxiliary reflective part 13 is roughly the same as that of the reflective layer 20, so as to ensure that the auxiliary reflective part 13 is The light reflectance is close to the light reflectance of the reflective layer 20 .
- the auxiliary reflection part 13 includes a first reflection part 132 and a second reflection part 131 , and the first reflection part 132 and the second reflection part 131 are integrally structured.
- the hollow area L in the reflective layer 20 exposes a part of the interlayer dielectric layer 30, the orthographic projection of the first reflective portion 132 on the substrate 1 is located in the hollow area L, and the first reflective portion 132 is directly connected to the interlayer dielectric layer 30.
- Contact; the second reflective portion 131 is in direct contact with the surface of the reflective layer 20 away from the substrate 1 , and the orthographic projection of the second reflective portion 131 on the substrate 1 overlaps with the orthographic projection of the reflective layer 20 on the substrate 1 .
- the second reflective part 131 covers part of the surface of the first reflective sublayer 10 away from the substrate 1, and the second reflective part 131 is in a direction parallel to the plane where the substrate 1 is located. There is a gap Z between the second reflective sub-layer 11 and the second reflective sub-layer 11 .
- the second reflective part 131 covers part of the surface of the first reflective sublayer 10 away from the substrate 1, and the second reflective part 131 is aligned with the second reflective part 131 in a direction parallel to the plane where the substrate 1 is located.
- the sublayers 11 are connected.
- the second reflective part 131 covers part of the surface of the first reflective sublayer 10 away from the substrate 1
- the second reflective part 131 also covers part of the surface of the second reflective sublayer 11 away from the substrate 1 .
- the array substrate further includes a plurality of packaging units 14 corresponding to the device 12, and the orthographic projection of the packaging unit 14 on the substrate 1 covers the device 12 on the substrate. 1 , and the orthographic projection of the packaging unit 14 on the substrate 1 partially overlaps the orthographic projection of the reflective layer 20 on the substrate 1 .
- each packaging unit 14 wraps one device 12 . While encapsulating the device 12, the encapsulation unit 14 can further adjust the output light of the light-emitting device included in the device 12 by designing its surface shape away from the substrate 1, for example, making it have a convex lens-like surface. angle.
- the array substrate may further include an encapsulation layer disposed on a side of the device 12 away from the substrate 1 for protecting the device 12 .
- the encapsulation layer may be an entire layer covering multiple devices 12 .
- FIG. 4 shows a schematic structural view of the device region A of the array substrate.
- the dielectric layer 30 is located on the side of the first conductive layer 7 away from the substrate 1; wherein, the interlayer dielectric layer 30 includes a first insulating layer 8 and a first planar layer 9, and the first planar layer 9 is located at least on the first insulating layer 8 and the first planar layer 9. Between the reflective layer 20.
- the first conductive layer 7 is used to form a conductive pattern.
- the array substrate is provided with a first conductive layer 7 , and the part of the first conductive layer 7 covered by the first insulating layer 8 constitutes a trace 73 in a conductive pattern for transmitting electrical signals. and the part of the first conductive layer 7 not covered by the first insulating layer 8 and away from the surface of the substrate 1 forms a conductive pad, which is used to electrically connect with the device 12, so as to pass the electrical signal transmitted in the wiring 73 to the device 12.
- the array substrate may include only one conductive layer.
- the material of the first conductive layer 7 may include any one of copper, aluminum, nickel, molybdenum and titanium or a combination of several metals arranged in layers.
- the first conductive layer 7 may include a molybdenum-nickel-titanium alloy (MoNiTi) layer, a copper metal layer, and a molybdenum-niobium alloy (MoNb) layer that are sequentially stacked.
- MoNiTi molybdenum-nickel-titanium alloy
- the nucleation density of the molybdenum-niobium alloy layer plays a role in preventing the oxidation of copper metal.
- the thickness range of the molybdenum-nickel-titanium alloy layer in the first conductive layer 7 can be For example, the thickness can be or
- the thickness of the first conductive layer 7 may range from 1.5 ⁇ m to 7 ⁇ m, for example, the thickness may be 1.5 ⁇ m, 2 ⁇ m, 4 ⁇ m, 6.5 ⁇ m or 7 ⁇ m.
- FIG. 5 shows another schematic structural view of the device region A of the array substrate.
- the device region A of the array substrate also includes a second conductive layer 3 and a second insulating layer that are sequentially stacked on the buffer layer 2. 4.
- the second flat layer 5 and the third insulating layer 6 , the third insulating layer 6 is located on the side of the first conductive layer 7 away from the first insulating layer 8 .
- the first conductive layer 7 and the second conductive layer 3 together form a conductive pattern.
- the first conductive layer 7 is arranged farther away from the substrate 1 than the second conductive layer 3, so the part of the surface of the first conductive layer 7 away from the substrate 1 that is not covered by the interlayer dielectric layer 30 constitutes a conductive pad for It is electrically connected with the device 12, and the part of the first conductive layer 7 covered by other film layers and the second conductive layer 3 constitute the signal line and the connecting line in the conductive pattern, which are used to receive and transmit the electrical signal from the external signal source circuit to the device 12.
- the conductive pattern of the second conductive layer 3 is not specifically drawn, and its patterned structure may be determined according to the circuit layout design of the array substrate.
- the material of the second conductive layer 3 may include any one of copper, aluminum, nickel, molybdenum and titanium or a combination of several metals arranged in layers.
- the second conductive layer 3 may include a molybdenum-niobium alloy layer, a copper metal layer and a protective layer stacked in sequence, and the protective layer may include copper-nickel alloy (CuNi), nickel or indium tin oxide (Indium Tin Oxide, ITO for short).
- the molybdenum-niobium alloy layer plays the role of improving the adhesion between the copper metal and the film layer near the substrate
- the protective layer plays the role of preventing the oxidation of the copper metal.
- the thickness range of the second conductive layer 3 may be 0.5-10 ⁇ m, for example, the thickness may be 0.5 ⁇ m, 1 ⁇ m, 1.8 ⁇ m, 2.7 ⁇ m or 10 ⁇ m.
- the exposed part of the surface of the first conductive layer 7 away from the substrate 1 constitutes a conductive pad
- the conductive pad includes at least one first pad 71, for example. and at least one second pad 72
- the interlayer dielectric layer 30 has a plurality of first openings K1 and a plurality of second openings K2 along the direction perpendicular to the substrate 1, and the first opening K1 exposes where the first pad 71 is located. area, the second opening K2 exposes the area where the second pad 72 is located;
- the first pad 71 is electrically connected to the first soldering leg 151 of the device 12 through the first opening K1
- the second soldering pad 72 is electrically connected to the second soldering leg 152 of the device 12 through the second opening K2 .
- the first pad 71 is electrically connected to the first solder pin 151 through a soldering material (such as solder, not shown in the figure) located in the first opening K1, and the second pad 72 and the second The welding legs 152 are electrically connected through the welding material located in the second opening K2 , so as to transmit electrical signals to the device 12 through the first welding 71 and the second welding pad 72 .
- a soldering material such as solder, not shown in the figure
- the solder material can be pre-printed on the first pad 71 and the second pad 72 , or can also be pre-fabricated on the first solder pin 151 and the second solder pin 152 .
- the array substrate further includes a plurality of support pillars 102, and the support pillars 102 are located on the side of the reflective layer 20 away from the substrate 1, and the orthographic projection of the support pillars 102 on the substrate 1 is the same as that of the device 12.
- the orthographic projections on the substrate 1 do not overlap each other.
- the color of the support pillars 102 can be selected according to needs, for example, the color of the support pillars 102 can be white, so that the reflectivity of the support pillars 102 is close to the reflectivity of the reflective layer 20 .
- the support column 102 may be transparent.
- the peripheral region B may further include a buffer layer 2, a second conductive layer 3, a second insulating layer 4, a second flat layer 5, a third insulating layer 6, a first conductive layer 7. At least one or more film layers of the first insulating layer 8 and the first flat layer 9 .
- other film structures that may be included in the peripheral area B may be determined according to actual design, and are not limited here.
- the embodiment of the present application also provides a light emitting device, as shown in FIG. 6 , including the above array substrate 100 .
- the substrate 1 in FIG. 1 a and all film layers between the substrate 1 and the reflective layer 20 constitute the substrate 101 shown in FIG.
- a light emitting device is provided, and the light emitting device includes the array substrate provided by the embodiments of the present application.
- the light emitting device may further include a protective substrate (or cover plate) covering the array substrate.
- the light emitting device can be used as a backlight device, or can also be used as a display device. Specifically, if the plurality of devices 12 in the light-emitting device are all light-emitting devices that emit light of a single color, the above-mentioned light-emitting device can be used as a backlight device; if the plurality of devices 12 in the light-emitting device include light-emitting devices that emit light of different colors , such as three light-emitting devices that emit red light, green light and blue light, then the above-mentioned light-emitting device can be used as a display device.
- the support pillars 102 may not be disposed in the array substrate 100 .
- the light-emitting device further includes a diffusion plate 103, a quantum dot film 104, a diffusion sheet 105, and a composite film 106 that are sequentially stacked; light side.
- a plurality of support columns 102 are used to support a plurality of optical films (including a diffusion plate 103, a quantum dot film 104, a diffusion sheet 105, and a composite film 106), so that there is a mixing between the reflective layer 20 in the array substrate 100 and the optical films.
- the light distance can improve the light shadow produced by the array substrate and improve the display quality of the light emitting device.
- the material of the diffuser plate 103 may include glass, polystyrene (PS), polycarbonate (PC), polyethylene (PE), polypropylene (PP), polyvinyl chloride (PVC), polypara Any of polyethylene phthalate (PET), acrylic (PMMA), and acrylic (MMA).
- PS polystyrene
- PC polycarbonate
- PE polyethylene
- PP polypropylene
- PVC polyvinyl chloride
- PET polypara Any of polyethylene phthalate
- acrylic PMMA
- MMA acrylic
- quantum dot film is a technology that uniformly mixes quantum dot phosphors and polymers to form a film.
- the material of quantum dot film 104 can include perovskite quantum Point material, its thickness is generally about 100um.
- the material of the diffuser sheet 105 may be the same as that of the diffuser plate 103 .
- the composite film 106 is used to improve light efficiency, it is also used as a protective film for the diffuser plate 103, the quantum dot film 104 and the diffuser sheet 105 to protect it from being scratched or damaged. damage.
- the reflective layer 20 located in the peripheral area B covers the outer contour of the substrate 1, so that there is no non-reflective area on the substrate 1 in the peripheral area B, so that when the light-emitting device emits light, the reflective layer 20 in the peripheral area B can reflect
- the light emitted by the light-emitting device is reflected, which greatly improves the problem of the large optical brightness difference between the peripheral area B of the light-emitting device and the device area A, and greatly increases the brightness of the light-emitting device along the direction perpendicular to the plane where the substrate 1 is located. The amount of light output on the surface, thereby improving the light extraction efficiency of the light emitting device.
- An embodiment of the present application also provides a spliced display device, as shown in FIG. 7 , comprising at least two light emitting devices as described above.
- the multiple devices 12 when used as a light-emitting device in a spliced display device, the multiple devices 12 include three types of light-emitting devices that emit red light, green light and blue light.
- the spliced display device may further include a multi-port transponder, a power supply device, a first frame and a second frame.
- each light-emitting device is located on the same plane, and each light-emitting device is fixed to the first frame, the first frame is fixed to the second frame, and the second frame is located far away from the first frame.
- the multi-port transponder and the power supply equipment are fixed to the second frame; the multi-port transponder is electrically connected to the power supply equipment, and the binding terminal group 107 of each light emitting device is electrically connected to the multi-port transponder respectively.
- the spliced display device shown in FIG. 7 is obtained by splicing light emitting devices composed of the array substrate shown in FIG. 2d.
- the peripheral area B used as the light emitting device in the spliced display device is also provided with a reflective layer 20 (in FIG. 7, the first reflector is provided in the peripheral area B Layer 10) can reflect the light emitted by the light-emitting device, which greatly improves the problem of the large optical brightness difference between the peripheral area B of the light-emitting device and the device area A.
- the spliced display device formed by splicing the light-emitting device In the case where the splicing width is sufficiently small and hardly detectable by the human eye, there is no optical dark area in the middle of two adjacent light-emitting devices, thereby greatly improving the display effect of the spliced display device.
- Fig. 8d shows a schematic diagram of a cutter wheel front cutting process.
- the substrate to be cut is located on the cutting machine table 305, and the following conditions must be met to ensure successful cutting by adopting the cutter wheel front cutting process: first, the distance d1 greater than or equal to 0.7 mm, the cutter wheel 302 can directly cut to the surface of the substrate 1 .
- the distance d2 between the clamp 301 of the cutter wheel and the packaging unit 104 is greater than 0 mm, so as to ensure that the clamp 301 of the cutter wheel will not scratch the packaging unit 104 .
- the distance between its axis and the edge of one side of the fixture 301 is about 3mm.
- the embodiment of the present application provides a method for preparing an array substrate, which is applied to prepare the above-mentioned array substrate, as shown in FIG. 9 , the method includes:
- motherboard substrate 400 as shown in FIG. 10 or FIG. 11; the motherboard substrate 400 is divided into at least one device region A and a cutting region C adjacent to the device region A;
- peripheral area B can be obtained by cutting off the area C1 other than the cutting line in the cutting area C.
- the motherboard substrate 400 as shown in FIG. 10 is cut along the cutting line, and at least one substrate 1 can be obtained after removing the C1 region of the motherboard substrate 400 .
- the reflective layer 20 has a plurality of hollow areas L along the direction perpendicular to the motherboard substrate 400; the interlayer dielectric layer 30 is at least located between the motherboard substrate 400 and the reflective layer 20; the reflective layer 20 is located in the device region A Part of the orthographic projection on the motherboard substrate 400 overlaps with the orthographic projection of the interlayer dielectric layer 30 on the motherboard substrate 400, and the part of the reflective layer 20 located in the cutting region C covers the cutting region C of the motherboard substrate 400 .
- Various devices 12 arranged in an array are arranged in the device area A, and the devices 12 include light-emitting devices, and any one of sensor devices, micro-drive chips or other types of devices.
- the interlayer dielectric layer 30 is located at least between the substrate 1 and the reflective layer 20 is: as shown in FIG.
- a part of the interlayer dielectric layer 30 is provided in a part of the region between the conductive patterns (between the conductive pads 71 and 72), and the part of the interlayer dielectric layer 30 is located between the substrate 1 and the device 12 between.
- the interlayer dielectric layer 30 has a plurality of first openings K1 and a plurality of second openings K2 along a direction perpendicular to the motherboard substrate 400 .
- the orthographic projection of the first opening K1 and/or the second opening K2 on the substrate 1 is within the range of the orthographic projection of the hollow area L on the substrate 1 .
- the first opening K1 in the interlayer dielectric layer 30 exposes the conductive pattern 71 provided on the substrate 1
- the second opening K2 in the interlayer dielectric layer 30 exposes the conductive pattern 72 provided on the substrate 1, so that
- the device 12 is connected to the conductive pattern 71 and the conductive pattern 72 respectively, and the conductive pattern is connected to an external signal source circuit to receive electrical signals.
- Both the device area A and the cutting area C are provided with a reflective layer 20.
- a reflective layer 20 For example: as shown in FIG. 10 or FIG. There is a reflective layer 20 .
- At least one film layer in 9 can extend to the cutting area C, which can be determined according to actual design, and is not limited here.
- Fig. 12a shows a schematic diagram of a back cutting process.
- the motherboard of the array substrate when cutting from the back side of the motherboard substrate 400 along the cutting line, the motherboard of the array substrate is located on the cutting machine table 305, and the cutting wheel 302 is arranged on the motherboard substrate 400. The back.
- a roller 306 is also provided on the other side of the motherboard of the array substrate opposite to the cutter wheel 302 to counteract the cutter wheel 302. Cutting pressure generated by the wheel 302 when cutting from the backside of the mother substrate 400 .
- the back side of the motherboard substrate 400 is not provided with the reflective layer 20, it can be cut at any position in the cutting area according to the cutting requirements. In this way, when cutting, it is not necessary to consider the distance between the axis of the cutter wheel 302 and the edge of the reflective layer 20. distance, and there is no need to consider the possible scratches and abrasions of the package unit 14 in the clamp 301 of the cutter wheel 302; There is a problem of cutting failure due to the influence of the reflective layer 20 .
- FIG. 12a, FIG. 13a and FIG. 14a the reflective layer 20, the device 12 and the packaging unit 14 are drawn on the motherboard substrate 400, and other structures included in the motherboard of the array substrate are not shown.
- the array substrate Other structures included in the motherboard are similar to those included in the array substrate. For details, reference may be made to the foregoing description of the structure of the array substrate, and details will not be repeated here.
- Fig. 12b is a schematic diagram showing the position of cutting lines of the motherboard of the array substrate in Fig. 12a.
- the position marked by the dotted line is the position of the cutting line.
- an array substrate can be obtained.
- the reflective layer 20 is also disposed in the region C1 outside the dicing line of the motherboard of the array substrate. However, since the backside dicing process is adopted, the reflective layer 20 will not affect the dicing process.
- FIG. 13a a schematic diagram of another backside cutting process is shown.
- the cutting line is located in the middle of the mother boards of the two array substrates, and the middle of the cutting machine table 305 is hollowed out to leave a space for setting the cutting wheel 302 there.
- FIG. 13b is a schematic diagram showing the position of cutting lines of the mother board of the array substrate in FIG. 13a. Wherein, the area between the two cutting lines is the C1 area to be cut off.
- multiple cutting wheels can be used to cut at the same time.
- a roller 306 is provided on the side of the reflective layer 20 away from the motherboard substrate 400 to balance the cutting time of the cutting wheel 302 resulting cutting pressure.
- the embodiment of the present application provides a vacuum chuck 500 as shown in FIG. 18
- the vacuum chuck 500 is a soft nozzle chuck, which has a good adsorption effect on array substrates with non-flat surfaces, and is used for handling and handling during cutting. Move the motherboard of the array substrate or the array substrate.
- the edge of the array substrate can be ground to reduce the probability of damage to the edge of the array substrate due to possible protrusions, gaps or microcracks, and improve the reliability of the array substrate.
- the array substrate is placed on the grinding machine table 307, and the grinding knife wheel 308 rotates counterclockwise, so that the grinding knife wheel 308 first grinds to the reflective layer 20, and then grinds to the substrate 1, avoiding When the substrate 1 is polished, the reflective layer 20 is partially peeled off due to pulling.
- the initial grinding point of the grinding cutter wheel 308 and the array substrate is the junction of the surface of the reflective layer 20 and the side surface of the substrate 1 as shown in FIG. 15a.
- the array The substrate will produce a grinding area (the area where the bevel is located) as shown in Figure 15c. Microscopic testing of this area shows that the width of the grinding area G1 is about 150um as shown in Figure 15b, and there is no reflection in this area layer 20, which seriously affects the optical performance of the array substrate.
- the preparation method further includes:
- the step of grinding the edge of the array substrate using a vertical grinding process includes:
- the process of grinding the array substrate using the vertical grinding process is shown in FIG. 16.
- the initial grinding point of the grinding wheel 308 is the side surface of the array substrate.
- the side surface of the substrate 1 and the side surface of the reflective layer 20 are ground at the same time, so that the difference between the wear degree of the reflective layer 20 at the edge of the array substrate and the wear degree of the substrate 1 can be greatly reduced, thereby reducing the grinding width of the grinding area G2 , the grinding width of the grinding area G2 of the array substrate ground by the vertical grinding process is about 100 um, and the vertical grinding process greatly improves the optical performance of the edge position of the array substrate.
- S903 the step of forming the reflective layer 20 on the device region A and the cutting region C of the motherboard substrate 400 includes:
- the orthographic projection of the first reflective sublayer 10 on the motherboard substrate 400 is located in the device region A and the cutting region C;
- the first reflective sublayer 10 is formed, and the orthographic projection of the first reflective sublayer 10 on the motherboard substrate 400 is located in the device region A and the cutting region C;
- the second reflective sublayer 11 is formed in the device region A and the cutting region C, and the orthographic projection of the second reflective sublayer 11 on the motherboard substrate 400 is located in the device region A and the cutting region C.
- the first reflective sublayer 10 covers the edge of the substrate 1, and the second reflective sublayer 11 retracts toward the device region A; so that the second reflective sublayer
- the range of distance H1 between the edge of 11 and the edge of substrate 1 (cutting line) is controlled within 0.2-2 mm.
- the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 can be 0.2mm, 0.4mm, 0.5mm, 0.8mm, 1mm, 1.5mm, 1.8mm or 2mm, the second reflective
- the specific value of the distance H1 between the edge of the sublayer 11 and the edge of the substrate 1 may be determined according to the design of the array substrate, the manufacturing process or the cutting process of the array substrate, and is not limited here.
- the materials included in the first reflective sublayer 10 and the second reflective sublayer 11 may be different, for example: the material of the first reflective sublayer 10 may include white ink, and the material of the second reflective sublayer 11 may include Silicone white glue.
- the first reflective sublayer 10 and the second reflective sublayer 11 may be made of the same material, for example: the materials of the first reflective sublayer 10 and the second reflective sublayer 11 both include white ink.
- the materials of the first reflective sublayer 10 and the second reflective sublayer 11 include white ink or silicon-based white glue
- the first reflective sublayer 10 and the second reflective sublayer 11 can be printed and formed respectively by using a screen printing process.
- the thickness range of the first reflective sub-layer 10 may be 25 ⁇ m-35 ⁇ m, for example: 25 ⁇ m, 28 ⁇ m, 30 ⁇ m, 32 ⁇ m or 35 ⁇ m.
- the thickness range of the second reflective sub-layer 11 may be 25 ⁇ m-35 ⁇ m, for example: 25 ⁇ m, 28 ⁇ m, 30 ⁇ m, 32 ⁇ m or 35 ⁇ m.
- the method also includes:
- An auxiliary reflective portion 13 is formed on the interlayer dielectric layer 30 ; wherein the auxiliary reflective portion 13 is connected to the reflective layer 20 .
- the reflective layer 20 at the edge of the hollowed out area L may be stepped, and the reflective layer 20 at the edge of the hollowed out area L exposes a part of the interlayer dielectric layer 30 , at this time, the auxiliary reflection part 13 can be set on the interlayer dielectric layer 30 to cover the part of the interlayer dielectric layer 30 exposed by the reflective layer 20 at the edge of the hollow area L, so as to make up for the part of the interlayer dielectric layer 30.
- the reflective layer 20 is not covered, so as to further increase the amount of light emitted by the array substrate along the direction perpendicular to the plane where the substrate 1 is located, thereby improving the light output efficiency of the array substrate.
- the auxiliary reflective portion 13 is provided on the sidewall of the hollowed-out area L of the reflective layer 20 , which can reduce the radial size of the hollowed-out area L and improve the dimensional accuracy of the hollowed-out area L.
- auxiliary reflection part 13 can be prepared by spraying around the edge of the hollow area, and as shown in FIG.
- the distance T2 between the surfaces of the reflective layer 20 is greater than the distance T1 between the surface of the reflective layer 20 in contact with the interlayer dielectric layer 30 and the surface of the reflective layer 20 away from the interlayer dielectric layer 30 .
- the material of the auxiliary reflective part 13 includes silicon-based white glue, and the color of the silicon-based white glue is white, so that the color of the auxiliary reflective part 13 is roughly the same as that of the reflective layer 20, so as to ensure that the auxiliary reflective part 13 is The light reflectance is close to the light reflectance of the reflective layer 20 .
- Embodiments of the present application respectively provide schematic structural diagrams of a spliced display device formed by array substrates cut by a tangent process and a back-cut process.
- FIG. 17 a shows a schematic structural view of an array substrate cut by a tangential process to form a spliced display device
- FIG. 17 b shows a schematic structural view of an array substrate cut by a back-cut process to form a spliced display device.
- the array substrate forming the light emitting device is obtained by using a tangential process, and the region where no reflective layer is provided in the light emitting device is marked as 20N.
- the distance between the display areas of two adjacent light-emitting devices in the splicing display device is 2.3 mm.
- the splicing display device displays a picture
- the array substrate forming the light emitting device is obtained by a backcut process.
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Abstract
Description
Claims (20)
- 一种阵列基板,其中,包括:器件区;与所述器件区相邻的周边区;所述器件区和所述周边区均包括衬底和位于所述衬底上的反射层;所述器件区还包括层间介质层和多个器件,所述层间介质层至少位于所述衬底和所述反射层之间;所述反射层具有沿垂直于所述衬底方向上的多个镂空区,所述器件位于所述镂空区内;其中,所述反射层位于所述器件区的部分在所述衬底上的正投影与所述层间介质层在所述衬底上的正投影部分交叠,所述反射层位于所述周边区的部分覆盖所述衬底位于所述周边区的部分,且所述衬底的外轮廓与所述周边区的外轮廓一致;所述器件至少包括发光器件。
- 根据权利要求1所述的阵列基板,其中,所述反射层包括第一反射子层和第二反射子层,所述第二反射子层位于所述第一反射子层远离所述衬底的一侧;所述第一反射子层在所述衬底上的正投影位于所述器件区和所述周边区;其中,所述第一反射子层位于所述器件区的部分在所述衬底上的正投影与所述层间介质层在所述衬底上的正投影部分交叠,且所述第一反射子层还覆盖所述衬底位于所述周边区的部分;所述第二反射子层在所述衬底上的正投影位于所述第一反射子层在所述衬底上的正投影以内。
- 根据权利要求2所述的阵列基板,其中,所述第二反射子层在所述衬底上的正投影位于所述器件区;所述第二反射子层在所述衬底上的正投影与所述第一反射子层位于所述周边区的部分在所述衬底上的正投影互不交叠。
- 根据权利要求2所述的阵列基板,其中,所述第二反射子层在所述衬底上的正投影位于所述周边区和所述器件区;所述第二反射子层位于所述周边区的部分在所述衬底上的正投影与所述第一反射子层位于所述周边区的部分在所述衬底上的正投影重 叠。
- 根据权利要求2所述的阵列基板,其中,所述第一反射子层和所述第二反射子层在沿垂直于所述衬底方向上的厚度相同。
- 根据权利要求1所述的阵列基板,其中,所述阵列基板还包括辅助反射部;所述辅助反射部位于所述层间介质层上,且所述辅助反射部和所述反射层相连。
- 根据权利要求6所述的阵列基板,其中,所述辅助反射部包括第一反射部和第二反射部,所述第一反射部和所述第二反射部为一体结构;所述镂空区暴露出所述层间介质层的部分区域,所述第一反射部在所述衬底上的正投影位于所述镂空区,且所述第一反射部与所述层间介质层直接接触;所述第二反射部与所述反射层远离所述衬底的表面直接接触,且所述第二反射部在所述衬底上的正投影与所述反射层在所述衬底上的正投影交叠。
- 根据权利要求1所述的阵列基板,其中,所述阵列基板还包括多个与所述器件对应的封装单元,所述封装单元在所述衬底上的正投影覆盖所述器件在所述衬底上的正投影,且所述封装单元在所述衬底上的正投影与所述反射层在所述衬底上的正投影部分交叠。
- 根据权利要求1所述的阵列基板,其中,所述阵列基板的所述器件区还包括位于所述衬底上依次设置的缓冲层和第一导电层,所述层间介质层位于所述第一导电层远离所述衬底的一侧;其中,所述层间介质层包括第一绝缘层和第一平坦层,所述第一平坦层至少位于所述第一绝缘层和所述反射层之间。
- 根据权利要求9所述的阵列基板,其中,所述阵列基板的所述器件区还包括位于所述缓冲层上依次层叠设置的第二导电层、第二绝缘层、第二平坦层和第三绝缘层,所述第三绝缘层位于所述第一导电层远离所述第一绝缘层的一侧。
- 根据权利要求9所述的阵列基板,其中,所述第一导电层包括 至少一个第一焊盘和至少一个第二焊盘,所述层间介质层具有沿垂直于所述衬底方向上的多个第一开口和多个第二开口,所述第一开口暴露出所述第一焊盘所在的区域,所述第二开口暴露出所述第二焊盘所在的区域;其中,所述第一焊盘通过所述第一开口和所述器件的第一焊脚电连接,所述第二焊盘通过所述第二开口和所述器件的第二焊脚电连接。
- 根据权利要求11所述的阵列基板,其中,所述阵列基板还包括多个支撑柱,所述支撑柱位于所述反射层远离所述衬底的一侧,且所述支撑柱在所述衬底上的正投影与所述器件在所述衬底上的正投影互不交叠。
- 一种发光装置,其中,包括如权利要求1-12中任一项所述的阵列基板。
- 根据权利要求13所述的发光装置,其中,所述发光装置还包括依次层叠设置的扩散板、量子点膜、扩散片和复合膜;其中,所述扩散板位于所述阵列基板的出光侧。
- 一种拼接显示装置,其中,包括至少两个如权利要求13或14所述的发光装置。
- 一种阵列基板的制备方法,其中,应用于制备如权利要求1-12中任一项所述的阵列基板,所述方法包括:提供母板衬底;所述母板衬底划分为至少一个器件区和与所述器件区相邻的切割区;在所述母板衬底的所述器件区上形成层间介质层;在所述母板衬底的所述器件区和所述切割区上形成反射层;其中,所述反射层具有沿垂直于所述母板衬底方向上的多个镂空区;所述层间介质层至少位于所述母板衬底和所述反射层之间;所述反射层位于所述器件区的部分在所述母板衬底上的正投影与所述层间介质层在所述母板衬底上的正投影部分交叠,所述反射层位于所述切割区的部分覆盖所述母板衬底的所述切割区;在所述母板衬底的所述器件区绑定多个器件;所述器件位于所述镂 空区内;从所述母板衬底的背面沿切割线切割,得到至少一个所述阵列基板;所述切割线位于所述切割区,所述背面为所述母板衬底远离所述器件的表面。
- 根据权利要求16所述的阵列基板的制备方法,其中,所述从所述母板衬底的背面沿切割线切割,得到至少一个所述阵列基板的步骤之后,所述方法还包括:采用垂直研磨工艺对所述阵列基板的边缘进行研磨。
- 根据权利要求17所述的阵列基板的制备方法,其中,所述采用垂直研磨工艺对所述阵列基板的边缘进行研磨的步骤包括:在沿垂直于所述阵列基板的方向上,同时对所述阵列基板的衬底的侧面和所述反射层的侧面进行研磨;其中,所述衬底的侧面和所述反射层的侧面共面。
- 根据权利要求16所述的阵列基板的制备方法,其中,所述在所述母板衬底的所述器件区和所述切割区上形成反射层的步骤包括:形成第一反射子层;所述第一反射子层在所述母板衬底上的正投影位于所述器件区和所述切割区内;形成第二反射子层;所述第二反射子层在所述母板衬底上的正投影位于所述器件区内;或者,形成第一反射子层;所述第一反射子层在所述母板衬底上的正投影位于所述器件区和所述切割区内;形成第二反射子层;所述第二反射子层在所述母板衬底上的正投影位于所述器件区和所述切割区内。
- 根据权利要求16所述的阵列基板的制备方法,其中,所述在所述母板衬底的所述器件区绑定多个器件的步骤之后,且在所述从所述母板衬底的背面沿切割线切割,得到至少一个所述阵列基板的步骤之前,所述方法还包括:在所述层间介质层上形成辅助反射部;其中,所述辅助反射部与所述反射层相连。
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