WO2023005609A1 - 阵列基板及其制备方法、发光装置和拼接显示装置 - Google Patents

阵列基板及其制备方法、发光装置和拼接显示装置 Download PDF

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Publication number
WO2023005609A1
WO2023005609A1 PCT/CN2022/103454 CN2022103454W WO2023005609A1 WO 2023005609 A1 WO2023005609 A1 WO 2023005609A1 CN 2022103454 W CN2022103454 W CN 2022103454W WO 2023005609 A1 WO2023005609 A1 WO 2023005609A1
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Prior art keywords
substrate
reflective
layer
array substrate
orthographic projection
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PCT/CN2022/103454
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English (en)
French (fr)
Inventor
高亮
汤海
Original Assignee
京东方科技集团股份有限公司
合肥京东方星宇科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方星宇科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2023561030A priority Critical patent/JP2024529811A/ja
Priority to US18/274,884 priority patent/US20240103316A1/en
Priority to EP22848214.7A priority patent/EP4300581A4/en
Publication of WO2023005609A1 publication Critical patent/WO2023005609A1/zh

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336Illuminating devices
    • G02F1/133602Direct backlight
    • G02F1/133603Direct backlight with LEDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • H01L33/60Reflective elements
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336Illuminating devices
    • G02F1/133602Direct backlight
    • G02F1/133605Direct backlight including specially adapted reflectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0058Processes relating to semiconductor body packages relating to optical field-shaping elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0066Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46Reflective coating, e.g. dielectric Bragg reflector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a preparation method thereof, a light emitting device and a spliced display device.
  • Mini LED Mini Light Emitting Diode, sub-millimeter light-emitting diode
  • Micro LED Micro Light Emitting Diode, micro-light-emitting diode
  • One of the advantages of Micro/mini LED display products is that it can realize large-area splicing, that is, splicing with multiple array substrates, so as to obtain super-sized display products.
  • an array substrate comprising:
  • Both the device region and the peripheral region include a substrate and a reflective layer on the substrate;
  • the device region also includes an interlayer dielectric layer and a plurality of devices, the interlayer dielectric layer is located at least between the substrate and the reflective layer; the reflective layer has a direction perpendicular to the substrate a plurality of hollowed out areas, the device is located in the hollowed out areas;
  • the orthographic projection of the reflective layer on the part of the substrate located in the device region overlaps with the orthographic projection of the interlayer dielectric layer on the substrate, and the reflective layer is located in the peripheral
  • the part of the region covers the part of the substrate located in the peripheral region, and the outer contour of the substrate is consistent with the outer contour of the peripheral region of the array substrate;
  • the device at least includes a light emitting device.
  • the reflective layer includes a first reflective sublayer and a second reflective sublayer, and the second reflective sublayer is located on a side of the first reflective sublayer away from the substrate;
  • the orthographic projection of the first reflective sublayer on the substrate is located in the device region and the peripheral region;
  • the orthographic projection of the part of the first reflective sublayer located in the device region on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate, and the first The reflective sublayer also covers the portion of the substrate located in the peripheral region;
  • the orthographic projection of the second reflective sublayer on the substrate is located within the orthographic projection of the first reflective sublayer on the substrate.
  • the orthographic projection of the second reflective sublayer on the substrate is located in the device region
  • the orthographic projection of the second reflective sublayer on the substrate does not overlap with the orthographic projection of the part of the first reflective sublayer located in the peripheral region on the substrate.
  • the orthographic projection of the second reflective sublayer on the substrate is located in the peripheral region and the device region;
  • the orthographic projection of the part of the second reflective sublayer located in the peripheral region on the substrate overlaps with the orthographic projection of the part of the first reflective sublayer located in the peripheral region on the substrate.
  • the first reflective sublayer and the second reflective sublayer have the same thickness along a direction perpendicular to the substrate.
  • the array substrate further includes an auxiliary reflection part; the auxiliary reflection part is located on the interlayer dielectric layer, and the auxiliary reflection part is connected to the reflection layer.
  • the auxiliary reflective part includes a first reflective part and a second reflective part, and the first reflective part and the second reflective part are integrated;
  • the hollow area exposes a part of the interlayer dielectric layer, and the first reflective portion
  • the orthographic projection on the substrate is located in the hollow area and is in direct contact with the interlayer dielectric layer;
  • the second reflective part is in direct contact with the surface of the reflective layer away from the substrate, and the orthographic projection of the second reflective part on the substrate is the same as the orthographic projection of the reflective layer on the substrate overlap.
  • the array substrate further includes a plurality of packaging units corresponding to the devices, and the orthographic projection of the packaging units on the substrate covers the area of the device on the substrate. Orthographic projection, and the orthographic projection of the packaging unit on the substrate partly overlaps with the orthographic projection of the reflective layer on the substrate.
  • the device region of the array substrate includes a buffer layer and a first conductive layer sequentially disposed on the substrate, and the interlayer dielectric layer is located away from the first conductive layer. one side of the substrate;
  • the interlayer dielectric layer includes a first insulating layer and a first planar layer, and the first planar layer is at least located between the first insulating layer and the reflective layer.
  • the device region of the array substrate further includes a second conductive layer, a second insulating layer, a second planar layer, and a third insulating layer that are sequentially stacked on the buffer layer,
  • the third insulating layer is located on a side of the first conductive layer away from the first insulating layer.
  • the first conductive layer includes at least one first pad and at least one second pad
  • the interlayer dielectric layer has a plurality of first pads along a direction perpendicular to the substrate. an opening and a plurality of second openings, the first opening exposes the area where the first pad is located, and the second opening exposes the area where the second pad is located;
  • the first pad is electrically connected to the first soldering leg of the device through the first opening
  • the second soldering pad is electrically connected to the second soldering leg of the device through the second opening
  • the array substrate further includes support columns, the support columns are located on the side of the reflective layer away from the substrate, and the orthographic projection of the support columns on the substrate do not overlap with the orthographic projection of the device on the substrate.
  • Embodiments of the present application also provide a light emitting device, including the above-mentioned array substrate.
  • the light-emitting device further includes a diffusion plate, a quantum dot film, a diffusion sheet, and a composite film that are sequentially stacked;
  • the diffusion plate is located on the light emitting side of the array substrate.
  • An embodiment of the present application also provides a spliced display device, comprising at least two light emitting devices as described above.
  • the embodiment of the present application also provides a method for preparing an array substrate, which is applied to prepare the above-mentioned array substrate, and the method includes:
  • the motherboard substrate is divided into at least one device region and a cutting region adjacent to the device region;
  • a reflective layer is formed on the device area and the cutting area of the motherboard substrate; wherein, the reflective layer has a plurality of hollowed-out regions along a direction perpendicular to the motherboard substrate; the interlayer The dielectric layer is located at least between the motherboard substrate and the reflective layer; the orthographic projection of the part of the reflective layer located in the device area on the motherboard substrate is the same as that of the interlayer dielectric layer in the The orthographic projections on the motherboard substrate overlap, and the part of the reflective layer located in the cutting region covers the cutting region of the motherboard substrate;
  • the method further includes:
  • the edge of the array substrate is ground by a vertical grinding process.
  • the step of grinding the edge of the array substrate using a vertical grinding process includes:
  • the side surfaces of the substrate of the array substrate and the side surfaces of the reflective layer are simultaneously ground; wherein, the side surfaces of the substrate and the side surfaces of the reflective layer are coplanar .
  • the step of forming a reflective layer on the device region and the cutting region of the motherboard substrate includes:
  • the orthographic projection of the first reflective sublayer on the motherboard substrate is located in the device region and the cutting region;
  • the orthographic projection of the first reflective sublayer on the motherboard substrate is located in the device region and the cutting region;
  • the orthographic projection of the second reflective sublayer on the motherboard substrate is located within the device region and the cutting region.
  • the method further includes:
  • An auxiliary reflection part is formed on the interlayer dielectric layer; wherein the auxiliary reflection part is connected to the reflection layer.
  • Figures 1a-5 are schematic structural views of nine types of array substrates provided by the embodiments of the present application.
  • FIG. 6 is a schematic structural diagram of a light emitting device provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a spliced display device provided by an embodiment of the present application.
  • Fig. 8a is a microscopic interferogram of scratches on the packaging unit of the array substrate and knife marks on the reflective layer in a related art provided by the embodiment of the present application;
  • Fig. 8b is a micrograph of knife marks on the reflective layer of an array substrate in a related art provided in the embodiment of the present application;
  • Fig. 8c is a schematic structural diagram of a cutting wheel provided in the embodiment of the present application.
  • Fig. 8d is a schematic diagram of a cutter wheel front cutting process provided by the embodiment of the present application.
  • FIG. 9 is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a motherboard of an array substrate provided in an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a motherboard of another array substrate provided by an embodiment of the present application.
  • Figure 12a, Figure 13a and Figure 14 are schematic diagrams of three back cutting processes provided by the embodiment of the present application.
  • Figure 12b is a schematic diagram of the position of the cutting line corresponding to the cutting process of Figure 12a;
  • Figure 13b is a schematic diagram of the position of the cutting line corresponding to the cutting process of Figure 13a;
  • Fig. 15a is a schematic diagram of a polishing process of an array substrate in a related art provided by an embodiment of the present application.
  • FIG. 15b and FIG. 15c are two structural schematic diagrams of the grinding area of the array substrate prepared by the grinding process of FIG. 15a;
  • FIG. 16 is a schematic diagram of a grinding process of an array substrate provided in an embodiment of the present application.
  • Fig. 17a is a schematic structural diagram of a splicing display device in a related art provided by an embodiment of the present application.
  • Fig. 17b is a schematic structural diagram of a spliced display device provided by an embodiment of the present application.
  • Fig. 18 is a schematic structural diagram of a vacuum chuck provided by an embodiment of the present application.
  • plural means two or more; the orientation or positional relationship indicated by the term “upper” is based on the orientation or positional relationship shown in the drawings, It is only for the convenience of describing the present application and simplifying the description, but does not indicate or imply that the structures or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect. Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • An embodiment of the present application provides an array substrate, as shown in FIG. 1a or FIG. 2a, including:
  • both the device region A and the peripheral region B include a substrate 1 and a reflective layer 20 located on the substrate 1;
  • the device region A also includes an interlayer dielectric layer 30 and a plurality of devices 12, the interlayer dielectric layer 30 is located at least between the substrate 1 and the reflective layer 20; the reflective layer 20 has a plurality of hollowed out regions along the direction perpendicular to the substrate 1 L, the device 12 is located in the hollow area L;
  • the orthographic projection of the part of the reflective layer 20 located in the device region A on the substrate 1 overlaps with the part of the orthographic projection of the interlayer dielectric layer 30 on the substrate 1, and the part of the reflective layer 20 located in the peripheral region B covers the substrate 1
  • the part located in the peripheral area B, and the outer contour of the substrate 1 is consistent with the outer contour of the peripheral area B of the array substrate.
  • a variety of devices 12 arranged in an array are arranged in the device area A on the array substrate.
  • the devices 12 include at least light-emitting devices, and may also include any one of sensor devices, micro-drive chips or other types of devices. It can be understood that , different types of devices have different numbers, or different types of devices have different array arrangement densities.
  • the peripheral area B is the area between the device area A and the boundary of the array substrate; in the actual production process, each array substrate is formed by cutting the motherboard, that is, the size of the peripheral area B can be determined according to the actual cutting process.
  • the width of the peripheral region B is the distance between the boundary of the array substrate and the device region A, and the width of the peripheral region B ranges from 0.2mm to 2mm; for example, it can be 0.2mm, 1mm, 1.2mm, 1.5 mm or 2mm.
  • the area except the peripheral area B is the device area A without considering the bonding area.
  • the distance between the geometric center of the orthographic projection of the device 12 located in the upper left corner of the array substrate on the substrate 1 along the X direction to the edge of the array substrate is 4mm, and the outer contour of the device region A
  • the distance along the X direction to the outer contour of the peripheral area B is 0.7mm;
  • the distance between the outer contour of the device region A and the outer contour of the peripheral region B along the Y direction is 0.7mm. That is, all the devices on the array substrate are located in the area where the device area A is located.
  • Substrate 1 can be rigid substrate, and the material of rigid substrate can be any one in glass, quartz, PET, plastics, and the thickness of rigid substrate can be 0.2mm-1mm, example, the thickness of rigid substrate is 0.2mm, 0.4mm, 0.5mm, 0.7mm or 1mm.
  • the light emitting device may be a submillimeter light emitting diode (Mini Light Emitting Diode, English abbreviation is Mini LED) or a micro light emitting diode (Micro Light Emitting Diode, English abbreviation is Micro LED), which is not limited here.
  • Mini LED Mini Light Emitting Diode
  • Micro LED Micro Light Emitting Diode
  • the plurality of devices 12 may all be blue-emitting submillimeter light-emitting diodes or miniature light-emitting diodes, or the plurality of devices 12 may simultaneously include three types of light-emitting diodes or micro-light emitting diodes that emit red light, green light, and blue light. diode.
  • the reflective layer 20 can reflect the light emitted by the light-emitting device to the light-emitting surface of the array substrate, so as to improve the light utilization efficiency of the light-emitting device.
  • the color of the reflective layer 20 is white, so that the reflective layer 20 has a higher reflectivity.
  • the reflective layer 20 may be a sheet structure with multiple hollowed out regions L, or the reflective layer 20 may also be fabricated on the array substrate by sputtering, coating, coating and other processes.
  • the material of the reflective layer 20 may include white ink, and the components of the white ink include resin (for example, epoxy resin, polytetrafluoroethylene resin), titanium dioxide (chemical formula TiO2) and organic solvent (for example, dipropylene glycol methyl ether )wait.
  • resin for example, epoxy resin, polytetrafluoroethylene resin
  • titanium dioxide chemical formula TiO2
  • organic solvent for example, dipropylene glycol methyl ether
  • the material of the reflective layer 20 may also include silicon-based white glue.
  • the reflective layer 20 can be formed by printing with a screen printing process, or sprayed with a glue valve spraying process to form the reflective layer 20 .
  • the distance T1 between the surface of the reflective layer 20 in contact with the interlayer dielectric layer 30 and the surface away from the interlayer dielectric layer 30 may range from 10 ⁇ m to 300 ⁇ m, for example, the thickness may be 10 ⁇ m, 50 ⁇ m, 55 ⁇ m, 60 ⁇ m, 80 ⁇ m, 155 ⁇ m, 200 ⁇ m or 300 ⁇ m.
  • the reflective layer 20 can be formed by one or more screen printing processes.
  • the portion of the reflective layer 20 located at the edge of the hollowed-out area L may be stepped.
  • the shape of the orthographic projection of the hollow area L on the substrate 1 may be a circle, a triangle, or a rectangle.
  • the part of the conductive pattern on the substrate 1 exposed by the hollow area L on the reflective layer 20 is used to connect with the device 12, and the part of the conductive pattern covered by the reflective layer 20 is used to connect with the external signal source circuit so that Electrical signals are received and transmitted to device 12 .
  • the interlayer dielectric layer 30 is located at least between the substrate 1 and the reflective layer 20 is: as shown in FIG.
  • a part of the interlayer dielectric layer 30 is provided in a part of the region between the conductive patterns (for example, between the conductive pads 71 and 72), and the part of the interlayer dielectric layer 30 is located between the substrate 1 and the substrate 1. between devices 12.
  • the interlayer dielectric layer 30 has a plurality of first openings K1 and a plurality of second openings K2 along a direction perpendicular to the substrate 1 .
  • the orthographic projection of the first opening K1 and/or the second opening K2 on the substrate 1 is within the range of the orthographic projection of the hollow area L on the substrate 1 .
  • the first opening K1 in the interlayer dielectric layer 30 exposes a part of the conductive pattern provided on the substrate 1, and the second opening K2 in the interlayer dielectric layer 30 exposes another part of the conductive pattern provided on the substrate 1, so that The device 12 is connected to the conductive pattern, and the conductive pattern is connected to an external signal source circuit to receive electrical signals.
  • both the device area A and the peripheral area B are provided with a reflective layer 20, for example: as shown in FIG. 1a or FIG. 2a, the orthographic projection of the reflective layer 20 on the array substrate does not overlap with the hollow area L .
  • the part of the reflective layer 20 disposed in the device region A is located on the side of the interlayer dielectric layer 30 away from the substrate 1, and according to the material and/or manufacturing process of the reflective layer 20, the reflective layer 20 is formed on the substrate There are different overlapping situations between the orthographic projection on the substrate 1 and the orthographic projection of the interlayer dielectric layer 30 on the substrate 1 .
  • the boundary of the reflective layer 20 at the hollow area L is stepped, and part of the interlayer dielectric layer 30 located at the hollow area L is not covered by the reflective layer 20 .
  • FIG. 3 shows a schematic structural view of an array substrate in which the reflective layer 20 is not disposed in the peripheral area B of the substrate 1.
  • the reflective layer 20 covers the device area A of the array substrate except for the hollow area L. Almost all of the area, but does not cover the peripheral area B of the substrate 1.
  • the array substrate shown in FIG. 3 emits light, there is no device 12 in the peripheral area B, and no reflective layer 20 reflects light, thus presenting a relatively dark visual effect, that is, the luminous effect is not good.
  • the outer contour of the peripheral area B of the array substrate is the outer contour of the substrate 1
  • the reflective layer 20 is located in the peripheral area B Covering the peripheral region B of the substrate 1, therefore, the part of the reflective layer 20 located in the peripheral region B can extend to the outer contour of the substrate 1, so that when the array substrate emits light, the reflective layer 20 of the peripheral region B can emit light from the device region A. And the light incident on its surface is reflected, which greatly improves the problem of the large optical brightness difference between the peripheral area B of the array substrate and the device area A, and can increase the brightness of the array substrate along the direction perpendicular to the plane where the substrate 1 is located. The amount of light output on the substrate, thereby improving the light extraction efficiency of the array substrate.
  • the reflective layer 20 includes a first reflective sublayer 10 and a second reflective sublayer 11, and the second reflective sublayer 11 is located away from the first reflective sublayer 10.
  • One side of the substrate 1; the orthographic projection of the first reflective sublayer 10 on the substrate 1 is located in the device region A and the peripheral region B;
  • the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located within the orthographic projection of the first reflective sublayer 10 on the substrate 1 .
  • the reflective layer 20 does not need to be arranged, and on the interlayer dielectric layer 30 outside the area where the device 12 is located
  • the reflective layer 20 is set so that the orthographic projection of the reflective layer 20 on the substrate 1 partially overlaps the orthographic projection of the interlayer dielectric layer 30 on the substrate 1 .
  • the orthographic projection of the part of the first reflective sublayer 10 located in the device region A on the substrate 1 overlaps with the orthographic projection of the interlayer dielectric layer 30 on the substrate 1.
  • the first reflective sublayer 10 in the reflective layer 20 may extend toward the direction in which the first reflective sublayer 10 points to the device 12, so that the first reflective sublayer 10 covers as shown in Figure 1a
  • the part of the interlayer dielectric layer 30 that is located in the hollow area L and does not overlap with the orthographic projection of the device 12 on the substrate 1 is shown in .
  • the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located within the orthographic projection of the first reflective sublayer 10 on the substrate 1 .
  • the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located in the device region A and the peripheral region B, and the part of the second reflective sublayer 11 disposed in the device region A is on the substrate 1
  • the orthographic projection of the first reflective sublayer 10 on the substrate 1 is located within the orthographic projection of the part of the first reflective sublayer 10 disposed in the device region A, and the orthographic projection of the part of the second reflective sublayer 11 located in the peripheral region B on the substrate 1 is within the same range as the first reflective sublayer 11.
  • the orthographic projections of the portion of a reflective sub-layer 10 located in the peripheral region B on the substrate 1 overlap.
  • the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located in the device area A and the peripheral area B, and the orthographic projection of the part of the second reflective sublayer 11 disposed in the device area A on the substrate 1 is located in the first reflective sublayer 11.
  • the sublayer 10 is arranged within the orthographic projection of the part of the device region A on the substrate 1, and the orthographic projection of the part of the second reflective sublayer 11 arranged on the peripheral region B on the substrate 1 is located within the part of the first reflective sublayer 10.
  • the part in the peripheral zone B is within the orthographic projection on the substrate 1 .
  • the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located in the device region A, and the second reflective sublayer 11 is not provided in the peripheral region B, and the second reflective sublayer 11 is formed on the substrate 1.
  • the orthographic projection on is located within the orthographic projection of the part of the first reflective sublayer 10 disposed on the device region A on the substrate 1 .
  • the orthographic projection of the first reflective sublayer 10 on the substrate 1 may be located within the orthographic projection of the second reflective sublayer 11 on the substrate 1 .
  • the orthographic projection of the second reflective sublayer 11 on the substrate 1 is located within the orthographic projection of the first reflective sublayer 10 on the substrate 1 as an example.
  • the first reflective sublayer 10 covers the edge of the substrate 1, and the second reflective sublayer 11 shrinks toward the device region A; so that the edge of the second reflective sublayer 11 reaches the substrate
  • the range of the distance H1 between the edges of 1 is controlled within 0.2-2mm.
  • the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 can be 0.2mm, 0.4mm, 0.5mm, 0.8mm, 1mm, 1.5mm, 1.8mm or 2mm, the second reflective
  • the specific value of the distance H1 between the edge of the sub-layer 11 and the edge of the substrate 1 may be determined according to the design of the array substrate, the manufacturing process or the cutting process of the array substrate.
  • FIG. 2d a top view of an array substrate is shown, wherein FIG. 2a is a cross-sectional view along the M1M2 direction of FIG. 2d .
  • a plurality of devices 12 are arranged in an array in the device area A, the reflective layer 20 in the device area A includes the first reflective sublayer 10 and the second reflective sublayer 11, and the reflective layer 20 in the peripheral area B includes The first reflective sublayer 10 .
  • the device 12 depicted in Figure 2d is a light emitting device.
  • the materials included in the first reflective sublayer 10 and the second reflective sublayer 11 may be different, for example: the material of the first reflective sublayer 10 may include white ink, and the material of the second reflective sublayer 11 may include Silicon-based white glue; or, the material of the first reflective sub-layer 10 may include white ink, and the material of the second reflective sub-layer 11 may include a reflective sheet.
  • the first reflective sublayer 10 and the second reflective sublayer 11 may be made of the same material, for example: the materials of the first reflective sublayer 10 and the second reflective sublayer 11 both include white ink.
  • the materials of the first reflective sublayer 10 and the second reflective sublayer 11 include white ink or silicon-based white glue
  • the first reflective sublayer 10 and the second reflective sublayer 11 can be printed and formed respectively by using a screen printing process.
  • the thickness range of the first reflective sublayer 10 along the direction perpendicular to the substrate 1 may be 25 ⁇ m-35 ⁇ m, for example: 25 ⁇ m, 28 ⁇ m, 30 ⁇ m, 32 ⁇ m or 35 ⁇ m.
  • the thickness range of the second reflective sublayer 11 along the direction perpendicular to the substrate 1 may be 25 ⁇ m-35 ⁇ m, for example: 25 ⁇ m, 28 ⁇ m, 30 ⁇ m, 32 ⁇ m or 35 ⁇ m.
  • the second reflective sublayer 11 is located in the device region A; the orthographic projection of the second reflective sublayer 11 on the substrate 1 does not overlap with the peripheral region B.
  • the peripheral area B refers to the area between the device area A and the boundary (cutting line) of the array substrate during the preparation of the array substrate
  • the first reflective sublayer is arranged on the substrate 1 in the peripheral area B 10, without setting the second reflective sub-layer 11, on the one hand, it can improve the film peeling (Peeling) problem of the reflective layer 20 caused by the cutting process when the motherboard is cut into an array substrate;
  • the first reflective sublayer 10 is set on the substrate 1, and the first reflective sublayer 10 covers the outer contour of the substrate 1, so that when the array substrate emits light, the first reflective sublayer 10 in the peripheral area B can emit light from the array substrate.
  • the light reflected from the array substrate improves the large difference in optical brightness between the peripheral area B of the array substrate and the device area A, and largely increases the amount of light output from the array substrate along the direction perpendicular to the plane where the substrate 1 is located, thereby improving The light extraction efficiency of the array substrate.
  • the materials of the first reflective sublayer 10 and the second reflective sublayer 11 both include white ink
  • the thickness range of the first reflective sublayer 10 and the second reflective sublayer 11 is 25-35 ⁇ m 2a
  • the difference in the reflectance value of the reflective layer 20 in the device area A and the reflective layer 20 in the peripheral area B to light is within 5%, which will not cause the difference between the device area A and the peripheral area B. Obvious optical difference.
  • the boundaries of the sub-layer 10 and the second reflective sub-layer 11 substantially coincide with the outer contour of the substrate 1, so that when the array substrate emits light, the first reflective sub-layer 10 and the second reflective sub-layer 11 in the peripheral area B can reflect the array substrate The emitted light is reflected, and under the dual effects of the first reflective sublayer 10 and the second reflective sublayer 11, the problem of large optical brightness difference between the peripheral area B of the array substrate and the device area A can be well improved.
  • the array substrate further includes a binding area D located on one side thereof, the reflecting layer 20 is not provided in the binding area D, and the binding area D includes a plurality of binding terminal groups 107 One end of the binding terminal group 107 is used to connect with the gold finger structure of an external circuit (circuit board or integrated circuit) to receive electrical signals, and the other end is connected to a conductive pattern on the array substrate, such as a signal line, to transmit electrical signals.
  • an external circuit circuit board or integrated circuit
  • the first reflective sublayer 10 and the second reflective sublayer 11 have the same thickness along a direction perpendicular to the substrate 1 .
  • the thicknesses of the first reflective sublayer 10 and the second reflective sublayer 11 along the direction perpendicular to the substrate 1 are both 25 ⁇ m, or both 30 ⁇ m, or both 35 ⁇ m.
  • the array substrate further includes an auxiliary reflective portion 13 ; the auxiliary reflective portion 13 is located on the interlayer dielectric layer 30 , and the auxiliary reflective portion 13 is connected to the reflective layer 20 .
  • the orthographic projection of the reflective layer 20 on the substrate 1 covers the part of the interlayer dielectric layer 30 except the hollow region L.
  • the orthographic projection of the reflective layer 20 on the substrate 1 falls into the interlayer dielectric layer 30. Therefore, in order to ensure the reflective effect, after the reflective layer 30 is provided, the auxiliary reflective part 13 is provided to enhance the reflective effect.
  • the interlayer dielectric layer 30 is located in the part of the hollow area L.
  • the auxiliary reflection part 13 can be provided on the part of the interlayer dielectric layer 30 to cover the exposed part of the interlayer dielectric layer 30 on the edge of the hollow area L. Part of the surface, so as to further increase the amount of light output from the array substrate along the direction perpendicular to the plane where the substrate 1 is located, thereby improving the light extraction efficiency of the array substrate.
  • the auxiliary reflective part 13 is provided at the sidewall of the hollowed out area L of the reflective layer 20 , which can reduce the radial size of the hollowed out area L and improve the dimensional accuracy of the hollowed out area L.
  • the radial dimension of the hollow area L is not reduced for marking.
  • the distance T2 between the surface of the auxiliary reflective portion 13 in contact with the interlayer dielectric layer 30 and the surface of the auxiliary reflective portion 13 away from the interlayer dielectric layer 30 is greater than that between the reflective layer 20 and the interlayer dielectric layer 30 .
  • the distance T1 between the surface in contact with the dielectric layer 30 and the surface of the reflective layer 20 away from the interlayer dielectric layer 30 is greater than that between the reflective layer 20 and the interlayer dielectric layer 30 .
  • the distance T2 between the surface of the auxiliary reflection part 13 in contact with the interlayer dielectric layer 30 and the surface of the auxiliary reflection part 13 away from the interlayer dielectric layer 30 may range from 50 ⁇ m to 80 ⁇ m;
  • the distance T1 between the surface in contact with the dielectric layer 30 and the surface of the reflective layer 20 away from the interlayer dielectric layer 30 may range from 30 ⁇ m to 50 ⁇ m.
  • auxiliary reflective part 13 can be provided on the edge surrounding the hollow area L through a spraying process.
  • the material of the auxiliary reflective part 13 includes silicon-based white glue, and the color of the silicon-based white glue is white, so that the color of the auxiliary reflective part 13 is roughly the same as that of the reflective layer 20, so as to ensure that the auxiliary reflective part 13 is The light reflectance is close to the light reflectance of the reflective layer 20 .
  • the auxiliary reflection part 13 includes a first reflection part 132 and a second reflection part 131 , and the first reflection part 132 and the second reflection part 131 are integrally structured.
  • the hollow area L in the reflective layer 20 exposes a part of the interlayer dielectric layer 30, the orthographic projection of the first reflective portion 132 on the substrate 1 is located in the hollow area L, and the first reflective portion 132 is directly connected to the interlayer dielectric layer 30.
  • Contact; the second reflective portion 131 is in direct contact with the surface of the reflective layer 20 away from the substrate 1 , and the orthographic projection of the second reflective portion 131 on the substrate 1 overlaps with the orthographic projection of the reflective layer 20 on the substrate 1 .
  • the second reflective part 131 covers part of the surface of the first reflective sublayer 10 away from the substrate 1, and the second reflective part 131 is in a direction parallel to the plane where the substrate 1 is located. There is a gap Z between the second reflective sub-layer 11 and the second reflective sub-layer 11 .
  • the second reflective part 131 covers part of the surface of the first reflective sublayer 10 away from the substrate 1, and the second reflective part 131 is aligned with the second reflective part 131 in a direction parallel to the plane where the substrate 1 is located.
  • the sublayers 11 are connected.
  • the second reflective part 131 covers part of the surface of the first reflective sublayer 10 away from the substrate 1
  • the second reflective part 131 also covers part of the surface of the second reflective sublayer 11 away from the substrate 1 .
  • the array substrate further includes a plurality of packaging units 14 corresponding to the device 12, and the orthographic projection of the packaging unit 14 on the substrate 1 covers the device 12 on the substrate. 1 , and the orthographic projection of the packaging unit 14 on the substrate 1 partially overlaps the orthographic projection of the reflective layer 20 on the substrate 1 .
  • each packaging unit 14 wraps one device 12 . While encapsulating the device 12, the encapsulation unit 14 can further adjust the output light of the light-emitting device included in the device 12 by designing its surface shape away from the substrate 1, for example, making it have a convex lens-like surface. angle.
  • the array substrate may further include an encapsulation layer disposed on a side of the device 12 away from the substrate 1 for protecting the device 12 .
  • the encapsulation layer may be an entire layer covering multiple devices 12 .
  • FIG. 4 shows a schematic structural view of the device region A of the array substrate.
  • the dielectric layer 30 is located on the side of the first conductive layer 7 away from the substrate 1; wherein, the interlayer dielectric layer 30 includes a first insulating layer 8 and a first planar layer 9, and the first planar layer 9 is located at least on the first insulating layer 8 and the first planar layer 9. Between the reflective layer 20.
  • the first conductive layer 7 is used to form a conductive pattern.
  • the array substrate is provided with a first conductive layer 7 , and the part of the first conductive layer 7 covered by the first insulating layer 8 constitutes a trace 73 in a conductive pattern for transmitting electrical signals. and the part of the first conductive layer 7 not covered by the first insulating layer 8 and away from the surface of the substrate 1 forms a conductive pad, which is used to electrically connect with the device 12, so as to pass the electrical signal transmitted in the wiring 73 to the device 12.
  • the array substrate may include only one conductive layer.
  • the material of the first conductive layer 7 may include any one of copper, aluminum, nickel, molybdenum and titanium or a combination of several metals arranged in layers.
  • the first conductive layer 7 may include a molybdenum-nickel-titanium alloy (MoNiTi) layer, a copper metal layer, and a molybdenum-niobium alloy (MoNb) layer that are sequentially stacked.
  • MoNiTi molybdenum-nickel-titanium alloy
  • the nucleation density of the molybdenum-niobium alloy layer plays a role in preventing the oxidation of copper metal.
  • the thickness range of the molybdenum-nickel-titanium alloy layer in the first conductive layer 7 can be For example, the thickness can be or
  • the thickness of the first conductive layer 7 may range from 1.5 ⁇ m to 7 ⁇ m, for example, the thickness may be 1.5 ⁇ m, 2 ⁇ m, 4 ⁇ m, 6.5 ⁇ m or 7 ⁇ m.
  • FIG. 5 shows another schematic structural view of the device region A of the array substrate.
  • the device region A of the array substrate also includes a second conductive layer 3 and a second insulating layer that are sequentially stacked on the buffer layer 2. 4.
  • the second flat layer 5 and the third insulating layer 6 , the third insulating layer 6 is located on the side of the first conductive layer 7 away from the first insulating layer 8 .
  • the first conductive layer 7 and the second conductive layer 3 together form a conductive pattern.
  • the first conductive layer 7 is arranged farther away from the substrate 1 than the second conductive layer 3, so the part of the surface of the first conductive layer 7 away from the substrate 1 that is not covered by the interlayer dielectric layer 30 constitutes a conductive pad for It is electrically connected with the device 12, and the part of the first conductive layer 7 covered by other film layers and the second conductive layer 3 constitute the signal line and the connecting line in the conductive pattern, which are used to receive and transmit the electrical signal from the external signal source circuit to the device 12.
  • the conductive pattern of the second conductive layer 3 is not specifically drawn, and its patterned structure may be determined according to the circuit layout design of the array substrate.
  • the material of the second conductive layer 3 may include any one of copper, aluminum, nickel, molybdenum and titanium or a combination of several metals arranged in layers.
  • the second conductive layer 3 may include a molybdenum-niobium alloy layer, a copper metal layer and a protective layer stacked in sequence, and the protective layer may include copper-nickel alloy (CuNi), nickel or indium tin oxide (Indium Tin Oxide, ITO for short).
  • the molybdenum-niobium alloy layer plays the role of improving the adhesion between the copper metal and the film layer near the substrate
  • the protective layer plays the role of preventing the oxidation of the copper metal.
  • the thickness range of the second conductive layer 3 may be 0.5-10 ⁇ m, for example, the thickness may be 0.5 ⁇ m, 1 ⁇ m, 1.8 ⁇ m, 2.7 ⁇ m or 10 ⁇ m.
  • the exposed part of the surface of the first conductive layer 7 away from the substrate 1 constitutes a conductive pad
  • the conductive pad includes at least one first pad 71, for example. and at least one second pad 72
  • the interlayer dielectric layer 30 has a plurality of first openings K1 and a plurality of second openings K2 along the direction perpendicular to the substrate 1, and the first opening K1 exposes where the first pad 71 is located. area, the second opening K2 exposes the area where the second pad 72 is located;
  • the first pad 71 is electrically connected to the first soldering leg 151 of the device 12 through the first opening K1
  • the second soldering pad 72 is electrically connected to the second soldering leg 152 of the device 12 through the second opening K2 .
  • the first pad 71 is electrically connected to the first solder pin 151 through a soldering material (such as solder, not shown in the figure) located in the first opening K1, and the second pad 72 and the second The welding legs 152 are electrically connected through the welding material located in the second opening K2 , so as to transmit electrical signals to the device 12 through the first welding 71 and the second welding pad 72 .
  • a soldering material such as solder, not shown in the figure
  • the solder material can be pre-printed on the first pad 71 and the second pad 72 , or can also be pre-fabricated on the first solder pin 151 and the second solder pin 152 .
  • the array substrate further includes a plurality of support pillars 102, and the support pillars 102 are located on the side of the reflective layer 20 away from the substrate 1, and the orthographic projection of the support pillars 102 on the substrate 1 is the same as that of the device 12.
  • the orthographic projections on the substrate 1 do not overlap each other.
  • the color of the support pillars 102 can be selected according to needs, for example, the color of the support pillars 102 can be white, so that the reflectivity of the support pillars 102 is close to the reflectivity of the reflective layer 20 .
  • the support column 102 may be transparent.
  • the peripheral region B may further include a buffer layer 2, a second conductive layer 3, a second insulating layer 4, a second flat layer 5, a third insulating layer 6, a first conductive layer 7. At least one or more film layers of the first insulating layer 8 and the first flat layer 9 .
  • other film structures that may be included in the peripheral area B may be determined according to actual design, and are not limited here.
  • the embodiment of the present application also provides a light emitting device, as shown in FIG. 6 , including the above array substrate 100 .
  • the substrate 1 in FIG. 1 a and all film layers between the substrate 1 and the reflective layer 20 constitute the substrate 101 shown in FIG.
  • a light emitting device is provided, and the light emitting device includes the array substrate provided by the embodiments of the present application.
  • the light emitting device may further include a protective substrate (or cover plate) covering the array substrate.
  • the light emitting device can be used as a backlight device, or can also be used as a display device. Specifically, if the plurality of devices 12 in the light-emitting device are all light-emitting devices that emit light of a single color, the above-mentioned light-emitting device can be used as a backlight device; if the plurality of devices 12 in the light-emitting device include light-emitting devices that emit light of different colors , such as three light-emitting devices that emit red light, green light and blue light, then the above-mentioned light-emitting device can be used as a display device.
  • the support pillars 102 may not be disposed in the array substrate 100 .
  • the light-emitting device further includes a diffusion plate 103, a quantum dot film 104, a diffusion sheet 105, and a composite film 106 that are sequentially stacked; light side.
  • a plurality of support columns 102 are used to support a plurality of optical films (including a diffusion plate 103, a quantum dot film 104, a diffusion sheet 105, and a composite film 106), so that there is a mixing between the reflective layer 20 in the array substrate 100 and the optical films.
  • the light distance can improve the light shadow produced by the array substrate and improve the display quality of the light emitting device.
  • the material of the diffuser plate 103 may include glass, polystyrene (PS), polycarbonate (PC), polyethylene (PE), polypropylene (PP), polyvinyl chloride (PVC), polypara Any of polyethylene phthalate (PET), acrylic (PMMA), and acrylic (MMA).
  • PS polystyrene
  • PC polycarbonate
  • PE polyethylene
  • PP polypropylene
  • PVC polyvinyl chloride
  • PET polypara Any of polyethylene phthalate
  • acrylic PMMA
  • MMA acrylic
  • quantum dot film is a technology that uniformly mixes quantum dot phosphors and polymers to form a film.
  • the material of quantum dot film 104 can include perovskite quantum Point material, its thickness is generally about 100um.
  • the material of the diffuser sheet 105 may be the same as that of the diffuser plate 103 .
  • the composite film 106 is used to improve light efficiency, it is also used as a protective film for the diffuser plate 103, the quantum dot film 104 and the diffuser sheet 105 to protect it from being scratched or damaged. damage.
  • the reflective layer 20 located in the peripheral area B covers the outer contour of the substrate 1, so that there is no non-reflective area on the substrate 1 in the peripheral area B, so that when the light-emitting device emits light, the reflective layer 20 in the peripheral area B can reflect
  • the light emitted by the light-emitting device is reflected, which greatly improves the problem of the large optical brightness difference between the peripheral area B of the light-emitting device and the device area A, and greatly increases the brightness of the light-emitting device along the direction perpendicular to the plane where the substrate 1 is located. The amount of light output on the surface, thereby improving the light extraction efficiency of the light emitting device.
  • An embodiment of the present application also provides a spliced display device, as shown in FIG. 7 , comprising at least two light emitting devices as described above.
  • the multiple devices 12 when used as a light-emitting device in a spliced display device, the multiple devices 12 include three types of light-emitting devices that emit red light, green light and blue light.
  • the spliced display device may further include a multi-port transponder, a power supply device, a first frame and a second frame.
  • each light-emitting device is located on the same plane, and each light-emitting device is fixed to the first frame, the first frame is fixed to the second frame, and the second frame is located far away from the first frame.
  • the multi-port transponder and the power supply equipment are fixed to the second frame; the multi-port transponder is electrically connected to the power supply equipment, and the binding terminal group 107 of each light emitting device is electrically connected to the multi-port transponder respectively.
  • the spliced display device shown in FIG. 7 is obtained by splicing light emitting devices composed of the array substrate shown in FIG. 2d.
  • the peripheral area B used as the light emitting device in the spliced display device is also provided with a reflective layer 20 (in FIG. 7, the first reflector is provided in the peripheral area B Layer 10) can reflect the light emitted by the light-emitting device, which greatly improves the problem of the large optical brightness difference between the peripheral area B of the light-emitting device and the device area A.
  • the spliced display device formed by splicing the light-emitting device In the case where the splicing width is sufficiently small and hardly detectable by the human eye, there is no optical dark area in the middle of two adjacent light-emitting devices, thereby greatly improving the display effect of the spliced display device.
  • Fig. 8d shows a schematic diagram of a cutter wheel front cutting process.
  • the substrate to be cut is located on the cutting machine table 305, and the following conditions must be met to ensure successful cutting by adopting the cutter wheel front cutting process: first, the distance d1 greater than or equal to 0.7 mm, the cutter wheel 302 can directly cut to the surface of the substrate 1 .
  • the distance d2 between the clamp 301 of the cutter wheel and the packaging unit 104 is greater than 0 mm, so as to ensure that the clamp 301 of the cutter wheel will not scratch the packaging unit 104 .
  • the distance between its axis and the edge of one side of the fixture 301 is about 3mm.
  • the embodiment of the present application provides a method for preparing an array substrate, which is applied to prepare the above-mentioned array substrate, as shown in FIG. 9 , the method includes:
  • motherboard substrate 400 as shown in FIG. 10 or FIG. 11; the motherboard substrate 400 is divided into at least one device region A and a cutting region C adjacent to the device region A;
  • peripheral area B can be obtained by cutting off the area C1 other than the cutting line in the cutting area C.
  • the motherboard substrate 400 as shown in FIG. 10 is cut along the cutting line, and at least one substrate 1 can be obtained after removing the C1 region of the motherboard substrate 400 .
  • the reflective layer 20 has a plurality of hollow areas L along the direction perpendicular to the motherboard substrate 400; the interlayer dielectric layer 30 is at least located between the motherboard substrate 400 and the reflective layer 20; the reflective layer 20 is located in the device region A Part of the orthographic projection on the motherboard substrate 400 overlaps with the orthographic projection of the interlayer dielectric layer 30 on the motherboard substrate 400, and the part of the reflective layer 20 located in the cutting region C covers the cutting region C of the motherboard substrate 400 .
  • Various devices 12 arranged in an array are arranged in the device area A, and the devices 12 include light-emitting devices, and any one of sensor devices, micro-drive chips or other types of devices.
  • the interlayer dielectric layer 30 is located at least between the substrate 1 and the reflective layer 20 is: as shown in FIG.
  • a part of the interlayer dielectric layer 30 is provided in a part of the region between the conductive patterns (between the conductive pads 71 and 72), and the part of the interlayer dielectric layer 30 is located between the substrate 1 and the device 12 between.
  • the interlayer dielectric layer 30 has a plurality of first openings K1 and a plurality of second openings K2 along a direction perpendicular to the motherboard substrate 400 .
  • the orthographic projection of the first opening K1 and/or the second opening K2 on the substrate 1 is within the range of the orthographic projection of the hollow area L on the substrate 1 .
  • the first opening K1 in the interlayer dielectric layer 30 exposes the conductive pattern 71 provided on the substrate 1
  • the second opening K2 in the interlayer dielectric layer 30 exposes the conductive pattern 72 provided on the substrate 1, so that
  • the device 12 is connected to the conductive pattern 71 and the conductive pattern 72 respectively, and the conductive pattern is connected to an external signal source circuit to receive electrical signals.
  • Both the device area A and the cutting area C are provided with a reflective layer 20.
  • a reflective layer 20 For example: as shown in FIG. 10 or FIG. There is a reflective layer 20 .
  • At least one film layer in 9 can extend to the cutting area C, which can be determined according to actual design, and is not limited here.
  • Fig. 12a shows a schematic diagram of a back cutting process.
  • the motherboard of the array substrate when cutting from the back side of the motherboard substrate 400 along the cutting line, the motherboard of the array substrate is located on the cutting machine table 305, and the cutting wheel 302 is arranged on the motherboard substrate 400. The back.
  • a roller 306 is also provided on the other side of the motherboard of the array substrate opposite to the cutter wheel 302 to counteract the cutter wheel 302. Cutting pressure generated by the wheel 302 when cutting from the backside of the mother substrate 400 .
  • the back side of the motherboard substrate 400 is not provided with the reflective layer 20, it can be cut at any position in the cutting area according to the cutting requirements. In this way, when cutting, it is not necessary to consider the distance between the axis of the cutter wheel 302 and the edge of the reflective layer 20. distance, and there is no need to consider the possible scratches and abrasions of the package unit 14 in the clamp 301 of the cutter wheel 302; There is a problem of cutting failure due to the influence of the reflective layer 20 .
  • FIG. 12a, FIG. 13a and FIG. 14a the reflective layer 20, the device 12 and the packaging unit 14 are drawn on the motherboard substrate 400, and other structures included in the motherboard of the array substrate are not shown.
  • the array substrate Other structures included in the motherboard are similar to those included in the array substrate. For details, reference may be made to the foregoing description of the structure of the array substrate, and details will not be repeated here.
  • Fig. 12b is a schematic diagram showing the position of cutting lines of the motherboard of the array substrate in Fig. 12a.
  • the position marked by the dotted line is the position of the cutting line.
  • an array substrate can be obtained.
  • the reflective layer 20 is also disposed in the region C1 outside the dicing line of the motherboard of the array substrate. However, since the backside dicing process is adopted, the reflective layer 20 will not affect the dicing process.
  • FIG. 13a a schematic diagram of another backside cutting process is shown.
  • the cutting line is located in the middle of the mother boards of the two array substrates, and the middle of the cutting machine table 305 is hollowed out to leave a space for setting the cutting wheel 302 there.
  • FIG. 13b is a schematic diagram showing the position of cutting lines of the mother board of the array substrate in FIG. 13a. Wherein, the area between the two cutting lines is the C1 area to be cut off.
  • multiple cutting wheels can be used to cut at the same time.
  • a roller 306 is provided on the side of the reflective layer 20 away from the motherboard substrate 400 to balance the cutting time of the cutting wheel 302 resulting cutting pressure.
  • the embodiment of the present application provides a vacuum chuck 500 as shown in FIG. 18
  • the vacuum chuck 500 is a soft nozzle chuck, which has a good adsorption effect on array substrates with non-flat surfaces, and is used for handling and handling during cutting. Move the motherboard of the array substrate or the array substrate.
  • the edge of the array substrate can be ground to reduce the probability of damage to the edge of the array substrate due to possible protrusions, gaps or microcracks, and improve the reliability of the array substrate.
  • the array substrate is placed on the grinding machine table 307, and the grinding knife wheel 308 rotates counterclockwise, so that the grinding knife wheel 308 first grinds to the reflective layer 20, and then grinds to the substrate 1, avoiding When the substrate 1 is polished, the reflective layer 20 is partially peeled off due to pulling.
  • the initial grinding point of the grinding cutter wheel 308 and the array substrate is the junction of the surface of the reflective layer 20 and the side surface of the substrate 1 as shown in FIG. 15a.
  • the array The substrate will produce a grinding area (the area where the bevel is located) as shown in Figure 15c. Microscopic testing of this area shows that the width of the grinding area G1 is about 150um as shown in Figure 15b, and there is no reflection in this area layer 20, which seriously affects the optical performance of the array substrate.
  • the preparation method further includes:
  • the step of grinding the edge of the array substrate using a vertical grinding process includes:
  • the process of grinding the array substrate using the vertical grinding process is shown in FIG. 16.
  • the initial grinding point of the grinding wheel 308 is the side surface of the array substrate.
  • the side surface of the substrate 1 and the side surface of the reflective layer 20 are ground at the same time, so that the difference between the wear degree of the reflective layer 20 at the edge of the array substrate and the wear degree of the substrate 1 can be greatly reduced, thereby reducing the grinding width of the grinding area G2 , the grinding width of the grinding area G2 of the array substrate ground by the vertical grinding process is about 100 um, and the vertical grinding process greatly improves the optical performance of the edge position of the array substrate.
  • S903 the step of forming the reflective layer 20 on the device region A and the cutting region C of the motherboard substrate 400 includes:
  • the orthographic projection of the first reflective sublayer 10 on the motherboard substrate 400 is located in the device region A and the cutting region C;
  • the first reflective sublayer 10 is formed, and the orthographic projection of the first reflective sublayer 10 on the motherboard substrate 400 is located in the device region A and the cutting region C;
  • the second reflective sublayer 11 is formed in the device region A and the cutting region C, and the orthographic projection of the second reflective sublayer 11 on the motherboard substrate 400 is located in the device region A and the cutting region C.
  • the first reflective sublayer 10 covers the edge of the substrate 1, and the second reflective sublayer 11 retracts toward the device region A; so that the second reflective sublayer
  • the range of distance H1 between the edge of 11 and the edge of substrate 1 (cutting line) is controlled within 0.2-2 mm.
  • the distance H1 between the edge of the second reflective sublayer 11 and the edge of the substrate 1 can be 0.2mm, 0.4mm, 0.5mm, 0.8mm, 1mm, 1.5mm, 1.8mm or 2mm, the second reflective
  • the specific value of the distance H1 between the edge of the sublayer 11 and the edge of the substrate 1 may be determined according to the design of the array substrate, the manufacturing process or the cutting process of the array substrate, and is not limited here.
  • the materials included in the first reflective sublayer 10 and the second reflective sublayer 11 may be different, for example: the material of the first reflective sublayer 10 may include white ink, and the material of the second reflective sublayer 11 may include Silicone white glue.
  • the first reflective sublayer 10 and the second reflective sublayer 11 may be made of the same material, for example: the materials of the first reflective sublayer 10 and the second reflective sublayer 11 both include white ink.
  • the materials of the first reflective sublayer 10 and the second reflective sublayer 11 include white ink or silicon-based white glue
  • the first reflective sublayer 10 and the second reflective sublayer 11 can be printed and formed respectively by using a screen printing process.
  • the thickness range of the first reflective sub-layer 10 may be 25 ⁇ m-35 ⁇ m, for example: 25 ⁇ m, 28 ⁇ m, 30 ⁇ m, 32 ⁇ m or 35 ⁇ m.
  • the thickness range of the second reflective sub-layer 11 may be 25 ⁇ m-35 ⁇ m, for example: 25 ⁇ m, 28 ⁇ m, 30 ⁇ m, 32 ⁇ m or 35 ⁇ m.
  • the method also includes:
  • An auxiliary reflective portion 13 is formed on the interlayer dielectric layer 30 ; wherein the auxiliary reflective portion 13 is connected to the reflective layer 20 .
  • the reflective layer 20 at the edge of the hollowed out area L may be stepped, and the reflective layer 20 at the edge of the hollowed out area L exposes a part of the interlayer dielectric layer 30 , at this time, the auxiliary reflection part 13 can be set on the interlayer dielectric layer 30 to cover the part of the interlayer dielectric layer 30 exposed by the reflective layer 20 at the edge of the hollow area L, so as to make up for the part of the interlayer dielectric layer 30.
  • the reflective layer 20 is not covered, so as to further increase the amount of light emitted by the array substrate along the direction perpendicular to the plane where the substrate 1 is located, thereby improving the light output efficiency of the array substrate.
  • the auxiliary reflective portion 13 is provided on the sidewall of the hollowed-out area L of the reflective layer 20 , which can reduce the radial size of the hollowed-out area L and improve the dimensional accuracy of the hollowed-out area L.
  • auxiliary reflection part 13 can be prepared by spraying around the edge of the hollow area, and as shown in FIG.
  • the distance T2 between the surfaces of the reflective layer 20 is greater than the distance T1 between the surface of the reflective layer 20 in contact with the interlayer dielectric layer 30 and the surface of the reflective layer 20 away from the interlayer dielectric layer 30 .
  • the material of the auxiliary reflective part 13 includes silicon-based white glue, and the color of the silicon-based white glue is white, so that the color of the auxiliary reflective part 13 is roughly the same as that of the reflective layer 20, so as to ensure that the auxiliary reflective part 13 is The light reflectance is close to the light reflectance of the reflective layer 20 .
  • Embodiments of the present application respectively provide schematic structural diagrams of a spliced display device formed by array substrates cut by a tangent process and a back-cut process.
  • FIG. 17 a shows a schematic structural view of an array substrate cut by a tangential process to form a spliced display device
  • FIG. 17 b shows a schematic structural view of an array substrate cut by a back-cut process to form a spliced display device.
  • the array substrate forming the light emitting device is obtained by using a tangential process, and the region where no reflective layer is provided in the light emitting device is marked as 20N.
  • the distance between the display areas of two adjacent light-emitting devices in the splicing display device is 2.3 mm.
  • the splicing display device displays a picture
  • the array substrate forming the light emitting device is obtained by a backcut process.

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Abstract

本申请提供了一种阵列基板及其制备方法、发光装置和拼接显示装置。阵列基板包括:器件区;与器件区相邻的周边区;器件区和周边区均包括衬底和位于衬底上的反射层;器件区还包括层间介质层和多个器件,层间介质层至少位于衬底和反射层之间;反射层具有沿垂直于衬底方向上的多个镂空区,器件位于镂空区内;其中,反射层位于器件区的部分在衬底上的正投影与层间介质层在衬底上的正投影部分交叠,反射层位于周边区的部分覆盖衬底位于周边区的部分,且衬底的外轮廓与阵列基板的周边区的外轮廓一致。该阵列基板的周边区能够反射光线,从而改善了阵列基板存在的不同区域光学亮度差异较大问题,提高阵列基板制备的拼接显示装置的显示效果。

Description

阵列基板及其制备方法、发光装置和拼接显示装置
本申请要求在2021年07月30日提交中国专利局、申请号为202110883921.7、名称为“一种阵列基板及其制备方法、发光装置和拼接显示装置”的中国专利申请的优先权,其全部内容通过引用结合在本公开中。
技术领域
本申请涉及显示技术领域,尤其涉及阵列基板及其制备方法、发光装置和拼接显示装置。
背景技术
随着显示技术的快速发展,Mini LED(Mini Light Emitting Diode,次毫米发光二极管)和Micro LED(Micro Light Emitting Diode,微发光二极管)的显示产品引起人们广泛的关注。Micro/mini LED显示产品的优势之一在于其能够实现大面积拼接,即用多个阵列基板进行拼接,从而获得超大尺寸的显示产品。
发明内容
本申请的实施例采用如下技术方案:
一方面,提供了一种阵列基板,包括:
器件区;
与所述器件区相邻的周边区;
所述器件区和所述周边区均包括衬底和位于所述衬底上的反射层;
所述器件区还包括层间介质层和多个器件,所述层间介质层至少位于所述衬底和所述反射层之间;所述反射层具有沿垂直于所述衬底方向上的多个镂空区,所述器件位于所述镂空区内;
其中,所述反射层在位于所述器件区的部分所述衬底上的正投影与所述层间介质层在所述衬底上的正投影部分交叠,所述反射层位于所述周边区的部分覆盖所述衬底位于所述周边区的部分,且所述衬底的外轮廓与所述阵列基板的所述周边区的外轮廓一致;所述器件至少包括发光器件。
在本申请的一些实施例中,所述反射层包括第一反射子层和第二反 射子层,所述第二反射子层位于所述第一反射子层远离所述衬底的一侧;所述第一反射子层在所述衬底上的正投影位于所述器件区和所述周边区;
其中,所述第一反射子层位于所述器件区的部分在所述衬底上的正投影与所述层间介质层在所述衬底上的正投影部分交叠,且所述第一反射子层还覆盖所述衬底位于所述周边区的部分;
所述第二反射子层在所述衬底上的正投影位于所述第一反射子层在所述衬底上的正投影以内。
在本申请的一些实施例中,所述第二反射子层在所述衬底上的正投影位于所述器件区;
所述第二反射子层在所述衬底上的正投影与所述第一反射子层位于所述周边区的部分在所述衬底上的正投影互不交叠。
在本申请的一些实施例中,所述第二反射子层在所述衬底上的正投影位于所述周边区和所述器件区;
所述第二反射子层位于所述周边区的部分在所述衬底上的正投影与所述第一反射子层位于所述周边区的部分在所述衬底上的正投影重叠。
在本申请的一些实施例中,所述第一反射子层和所述第二反射子层在沿垂直于所述衬底方向上的厚度相同。
在本申请的一些实施例中,所述阵列基板还包括辅助反射部;所述辅助反射部位于所述层间介质层上,且所述辅助反射部和所述反射层相连。
在本申请的一些实施例中,所述辅助反射部包括第一反射部和第二反射部,所述第一反射部和所述第二反射部为一体结构;
所述镂空区暴露出所述层间介质层的部分区域,所述第一反射部
在所述衬底上的正投影位于所述镂空区,且与所述层间介质层直接接触;
所述第二反射部与所述反射层远离所述衬底的表面直接接触且所述第二反射部在所述衬底上的正投影与所述反射层在所述衬底上的正 投影交叠。
在本申请的一些实施例中,所述阵列基板还包括多个与所述器件对应的封装单元,所述封装单元在所述衬底上的正投影覆盖所述器件在所述衬底上的正投影,且所述封装单元在所述衬底上的正投影与所述反射层在所述衬底上的正投影部分交叠。
在本申请的一些实施例中,所述阵列基板的所述器件区包括位于所述衬底上依次设置的缓冲层和第一导电层,所述层间介质层位于所述第一导电层远离所述衬底的一侧;
其中,所述层间介质层包括第一绝缘层和第一平坦层,所述第一平坦层至少位于所述第一绝缘层和所述反射层之间。
在本申请的一些实施例中,所述阵列基板的所述器件区还包括位于所述缓冲层上依次层叠设置的第二导电层、第二绝缘层、第二平坦层和第三绝缘层,所述第三绝缘层位于所述第一导电层远离所述第一绝缘层的一侧。
在本申请的一些实施例中,所述第一导电层包括至少一个第一焊盘和至少一个第二焊盘,所述层间介质层具有沿垂直于所述衬底方向上的多个第一开口和多个第二开口,所述第一开口暴露出所述第一焊盘所在的区域,所述第二开口暴露出所述第二焊盘所在的区域;
其中,所述第一焊盘通过所述第一开口和所述器件的第一焊脚电连接,所述第二焊盘通过所述第二开口和所述器件的第二焊脚电连接。
在本申请的一些实施例中,所述阵列基板还包括支撑柱,所述支撑柱位于所述反射层远离所述衬底的一侧,且所述支撑柱在所述衬底上的正投影与所述器件在所述衬底上的正投影互不交叠。
本申请的实施例还提供了一种发光装置,包括如上所述的阵列基板。
在本申请的一些实施例中,所述发光装置还包括依次层叠设置的扩散板、量子点膜、扩散片和复合膜;
其中,所述扩散板位于所述阵列基板的出光侧。
本申请的实施例还提供了一种拼接显示装置,包括至少两个如上所述的发光装置。
本申请的实施例还提供了一种阵列基板的制备方法,应用于制备如上所述的阵列基板,所述方法包括:
提供母板衬底;所述母板衬底划分为至少一个器件区和与所述器件区相邻的切割区;
在所述母板衬底的所述器件区上形成层间介质层;
在所述母板衬底的所述器件区和所述切割区上形成反射层;其中,所述反射层具有沿垂直于所述母板衬底方向上的多个镂空区;所述层间介质层至少位于所述母板衬底和所述反射层之间;所述反射层位于所述器件区的部分在所述母板衬底上的正投影与所述层间介质层在所述母板衬底上的正投影部分交叠,所述反射层位于所述切割区的部分覆盖所述母板衬底的所述切割区;
在所述母板衬底的所述器件区绑定多个器件;所述器件位于所述镂空区内;
从所述母板衬底的背面沿切割线切割,得到至少一个所述阵列基板;所述切割线位于所述切割区,所述背面为所述母板衬底远离所述器件的表面。
在本申请的一些实施例中,所述从所述母板衬底的背面沿切割线切割,得到至少一个所述阵列基板的步骤之后,所述方法还包括:
采用垂直研磨工艺对所述阵列基板的边缘进行研磨。
在本申请的一些实施例中,所述采用垂直研磨工艺对所述阵列基板的边缘进行研磨的步骤包括:
在沿垂直于所述阵列基板的方向上,同时对所述阵列基板的衬底的侧面和所述反射层的侧面进行研磨;其中,所述衬底的侧面和所述反射层的侧面共面。
在本申请的一些实施例中,所述在所述母板衬底的所述器件区和所述切割区上形成反射层的步骤包括:
形成第一反射子层;所述第一反射子层在所述母板衬底上的正投影位于所述器件区和所述切割区内;
形成第二反射子层;所述第二反射子层在所述母板衬底上的正投影 位于所述器件区内;
或者,形成第一反射子层;所述第一反射子层在所述母板衬底上的正投影位于所述器件区和所述切割区内;
形成第二反射子层;所述第二反射子层在所述母板衬底上的正投影位于所述器件区和所述切割区内。
在本申请的一些实施例中,所述在所述母板衬底的所述器件区绑定多个器件的步骤之后,且在所述从所述母板衬底的背面沿切割线切割,得到至少一个所述阵列基板的步骤之前,所述方法还包括:
在所述层间介质层上形成辅助反射部;其中,所述辅助反射部与所述反射层相连。
上述说明仅是本申请技术方案的概述,为了能够更清楚了解本申请的技术手段,而可依照说明书的内容予以实施,并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂,以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图。
图1a-图5为本申请实施例提供的九种阵列基板的结构示意图;
图6为本申请实施例提供的一种发光装置的结构示意图;
图7为本申请实施例提供的一种拼接显示装置的结构示意图;
图8a为本申请实施例提供的一种相关技术中阵列基板的封装单元的刮痕和反射层的刀痕的显微镜干涉图;
图8b为本申请实施例提供的一种相关技术中阵列基板的反射层刀痕的显微镜图;
图8c为本申请实施例提供的一种切割刀轮的结构示意图;
图8d为本申请实施例提供的一种刀轮正面切割工艺的示意图;
图9为本申请实施例提供的一种阵列基板的制备方法流程图;
图10为本申请实施例提供的一种阵列基板的母板的结构示意图;
图11为本申请实施例提供的另一种阵列基板的母板的结构示意图;
图12a、图13a和图14为本申请实施例提供的三种背面切割工艺的示意图;
图12b为图12a的切割工艺对应的切割线位置示意图;
图13b为图13a的切割工艺对应的切割线位置示意图;
图15a为本申请实施例提供的一种相关技术中阵列基板的研磨工艺示意图;
图15b和图15c为采用图15a的研磨工艺制备的阵列基板的研磨区的两种结构示意图;
图16为本申请实施例提供的一种阵列基板的研磨工艺示意图;
图17a为本申请实施例提供的一种相关技术中的拼接显示装置的结构示意图;
图17b为本申请实施例提供的一种拼接显示装置的结构示意图;
图18为本申请实施例提供的一种真空吸盘的结构示意图。
具体实施例
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本申请保护的范围。
除非上下文另有要求,否则,在整个说明书和权利要求书中,术语“包括”被解释为开放、包含的意思,即为“包含,但不限于”。在说明书的描述中,术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外,所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中,除非另有说明,“多个”的含义是两个或两个以上;术语“上”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的结构或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。
为了便于清楚描述本申请的实施例的技术方案,在本申请的实施例中,采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分,本领域技术人员可以理解“第一”、“第二”等字样并不对数量进行限定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中,为了清楚,放大了层和区域的厚度。因此,可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此,示例性实施方式不应解释为局限于本文示出的区域的形状,而是包括因例如制造而引起的形状偏差。例如,示为矩形的蚀刻区域通常将具有弯曲的特征。因此,附图中所示的区域本质上是示意性的,且它们的形状并非旨在示出设备的区域的实际形状,并且并非旨在限制示例性实施方式的范围。
本申请的实施例提供了一种阵列基板,参考图1a或图2a所示,包括:
器件区A;以及如图2d中所示的与器件区A相邻的周边区B;器件区A和周边区B均包括衬底1和位于衬底1上的反射层20;
器件区A还包括层间介质层30和多个器件12,层间介质层30至少位于衬底1和反射层20之间;反射层20具有沿垂直于衬底1方向上的多个镂空区L,器件12位于镂空区L内;
其中,反射层20位于器件区A的部分在衬底1上的正投影与层间介质层30在衬底1上的正投影部分交叠,反射层20位于周边区B的部分覆盖衬底1位于周边区B的部分,且衬底1的外轮廓与阵列基板的周边区B的外轮廓一致。
阵列基板上的器件区A中设置有阵列排布的多种器件12,器件12 至少包括发光器件,且还可以包括传感器件、微型驱动芯片或其它种类的器件中的任意一种,可以理解是,不同类型的器件数量不同,或者,不同类型的器件的阵列排布的密度不同。
周边区B为器件区A与阵列基板边界之间的区域;在实际生产过程中,各个阵列基板由母板切割形成,即周边区B的尺寸可以根据实际切割工艺确定。
需要说明的是,周边区B的宽度为阵列基板边界与器件区A的间距,周边区B各处的宽度取值范围为0.2mm-2mm;例如:可以是0.2mm、1mm、1.2mm、1.5mm或2mm。
在阵列基板中,参考图1a或图2a所示,在不考虑绑定区的情况下,除周边区B之外的区域为器件区A。
最靠近阵列基板边界的任意一个器件12,在衬底1上的正投影的几何中心沿平行于衬底1所在平面的方向到阵列基板的边缘(周边区B的外轮廓)之间的距离范围为1mm-5mm,例如:其距离可以是1mm、1.2mm、1.5mm、2mm、3mm、4mm、5mm。
示例地,参考图2d所示,阵列基板中位于左上角的器件12在衬底1上的正投影的几何中心沿X方向到阵列基板的边缘之间的距离为4mm,器件区A的外轮廓沿X方向到周边区B的外轮廓之间的距离为0.7mm;阵列基板中位于左上角的器件12在衬底1上的正投影的几何中心沿Y方向到阵列基板的边缘之间的距离为2mm或3mm,器件区A的外轮廓沿Y方向到周边区B的外轮廓之间的距离为0.7mm。即阵列基板上所有的器件均位于器件区A所在范围。
衬底1可以是刚性衬底,刚性衬底的材料可以是玻璃、石英、PET、塑料中的任意一种,刚性衬底的厚度可以为0.2mm-1mm,示例的,刚性衬底的厚度为0.2mm、0.4mm、0.5mm、0.7mm或1mm。
其中,发光器件可以为次毫米发光二极管(Mini Light Emitting Diode,英文缩写为Mini LED)或微型发光二极管(Micro Light Emitting Diode,英文缩写为Micro LED),在此不作限定。
示例性地,多个器件12可以均为发蓝光的次毫米发光二极管或微 型发光二极管,或者,多个器件12可以同时包括发红光、发绿光和发蓝光的三种发光二极管或微型发光二极管。
由于发光器件发射的光线射向四周,反射层20可以将发光器件发射的光线反射至阵列基板的出光面,以提高发光器件的光利用率。
示例性地,反射层20的颜色为白色,以使反射层20具有较高的反射率。
在一些实施例中,反射层20可以是具有多个镂空区L的片状结构,或者,反射层20也可以通过溅射、镀膜、涂覆等工艺制作在阵列基板上。
示例性地,反射层20的材料可包括白色油墨,白色油墨的组份包括树脂(例如,环氧树脂、聚四氟乙烯树脂)、二氧化钛(化学式TiO2)以及有机溶剂(例如,二丙二醇甲醚)等。
反射层20的材料还可包括硅系白胶。在反射层20的材料包括白色油墨或包括硅系白胶的情况下,可采用丝网印刷工艺,印刷形成反射层20,或者采用胶阀喷涂工艺,喷射涂覆形成反射层20。
示例性地,参考图2b所示,反射层20与层间介质层30接触的表面到其远离层间介质层30的表面之间的距离T1的范围可为10μm~300μm,例如,厚度可为10μm、50μm、55μm、60μm、80μm、155μm、200μm或300μm。
示例性地,反射层20可以通过一次或多次丝网印刷工艺形成。
在采用多次丝网印刷工艺制作反射层20时,反射层20位于镂空区L边缘的部分可以呈台阶状。
示例性地,镂空区L在衬底1上的正投影的形状可以是圆形、三角形或矩形等。
衬底1上的导电图案被反射层20上的镂空区L暴露出来的部分,用于与器件12相连接,而导电图案被反射层20所覆盖的部分用于与外部信号源电路相连接从而接收并向器件12传输电信号。
层间介质层30至少位于衬底1和反射层20之间的含义为:参考图1a所示,在阵列基板未设置器件12的区域中,层间介质层30位于衬 底1和反射层20之间;在镂空区L中,导电图案之间的(例如导电焊盘71和72之间)的部分区域设置有部分层间介质层30,且该部分层间介质层30位于衬底1和器件12之间。
参考图1a所示,层间介质层30具有沿垂直于衬底1方向上的多个第一开口K1和多个第二开口K2。第一开口K1和/或第二开口K2在衬底1上的正投影位于镂空区L在衬底1上的正投影范围内。
层间介质层30中的第一开口K1暴露出设置在衬底1上的一部分导电图案,层间介质层30中的第二开口K2暴露出设置在衬底1上的另一部分导电图案,以使得器件12与导电图案相连接,而导电图案与外部信号源电路相连接从而接收电信号。
在一些实施例中,器件区A和周边区B中均设置有反射层20,示例的:参考图1a或图2a所示,反射层20在阵列基板上的正投影与镂空区L无交叠。
示例性地,反射层20设置在器件区A的部分位于层间介质层30远离衬底1的一侧,且根据制作反射层20的材料和/或、制作工艺的不同,反射层20在衬底1上的正投影与层间介质层30在衬底1上的正投影存在不同的交叠情况。
例如:采用多次丝网印刷工艺制作反射层20时,反射层20位于镂空区L的边界呈现台阶状,位于镂空区L的部分层间介质层30并未被反射层20覆盖。
图3示出了一种反射层20未设置在衬底1的周边区B中的阵列基板的结构示意图,参考图3所示,反射层20覆盖阵列基板器件区A中除镂空区L之外的几乎所有区域,而并未覆盖衬底1的周边区B。在图3所示的阵列基板发光时,周边区B中无器件12,也无反射层20反射光线,从而呈现出相对较暗的视觉效果,即发光效果欠佳。
在本申请的实施例提供的如图1a或图2a所示的阵列基板中,由于阵列基板的周边区B的外轮廓即为衬底1的外轮廓,且反射层20位于周边区B的部分覆盖衬底1的周边区B,故而,反射层20位于周边区B的部分能够延伸至衬底1的外轮廓,从而在阵列基板发光时,周边区 B的反射层20能够将器件区A发出且入射到其表面的光线进行反射,很大程度上改善了阵列基板的周边区B较器件区A存在的较大光学亮度差异问题,同时能够增加阵列基板沿垂直于衬底1所在平面的方向上的出光量,从而提高阵列基板的出光效率。
在本申请的一些实施例中,参考图1a或图2a所示,反射层20包括第一反射子层10和第二反射子层11,第二反射子层11位于第一反射子层10远离衬底1的一侧;第一反射子层10在衬底1上的正投影位于器件区A和周边区B;
其中,第一反射子层10位于器件区A的部分在衬底1上的正投影与层间介质层30在衬底1上的正投影部分交叠,第一反射子层10还覆盖周边区B的衬底1;
第二反射子层11在衬底1上的正投影位于第一反射子层10在衬底1上的正投影以内。
在一些实施例中,参考图1a所示,器件12与衬底1之间的部分层间介质层30上,不需要设置反射层20,在器件12所在区域之外的层间介质层30上设置反射层20,使得反射层20在衬底1上的正投影与层间介质层30在衬底1上的正投影部分交叠。
在一些实施例中,第一反射子层10位于器件区A的部分在衬底1上的正投影与层间介质层30在衬底1上的正投影部分交叠,然而,在实际制作过程中,由于工艺误差,在阵列基板的部分区域,反射层20中的第一反射子层10可以向第一反射子层10指向器件12的方向延伸,使得第一反射子层10覆盖如图1a中所示的位于镂空区L中与器件12在衬底1上的正投影互不交叠的部分层间介质层30。
在一些实施例中,第二反射子层11在衬底1上的正投影位于第一反射子层10在衬底1上的正投影以内。
示例性地,参考图1a所示,第二反射子层11在衬底1上的正投影位于器件区A和周边区B,第二反射子层11设置在器件区A的部分在衬底1上的正投影位于第一反射子层10设置在器件区A的部分在衬底1上的正投影以内,第二反射子层11位于周边区B的部分在衬底1上 的正投影与第一反射子层10位于周边区B的部分在衬底1上的正投影交叠。
或者,第二反射子层11在衬底1上的正投影位于器件区A和周边区B,第二反射子层11设置在器件区A的部分在衬底1上的正投影位于第一反射子层10设置在器件区A的部分在衬底1上的正投影以内,且第二反射子层11设置在周边区B的部分在衬底1上的正投影位于第一反射子层10设置在周边区B的部分在衬底1上的正投影以内。
或者,参考图2a所示,第二反射子层11在衬底1上的正投影位于器件区A,周边区B中不设置第二反射子层11,第二反射子层11在衬底1上的正投影位于第一反射子层10设置于器件区A的部分在衬底1上的正投影以内。
在一些实施例中,第一反射子层10在衬底1上的正投影可位于第二反射子层11在衬底1上的正投影以内。本申请的实施例提供的附图中,以第二反射子层11在衬底1上的正投影位于第一反射子层10在衬底1上的正投影以内为例进行绘示。
在一些实施例中,参考图2a所示,第一反射子层10覆盖衬底1的边缘,第二反射子层11向器件区A内缩;使得第二反射子层11的边缘到衬底1的边缘之间的距离H1的范围控制在0.2-2mm之间。
示例性地,第二反射子层11的边缘到衬底1的边缘之间的距离H1可以为0.2mm,0.4mm、0.5mm、0.8mm、1mm、1.5mm、1.8mm或2mm,第二反射子层11的边缘到衬底1的边缘之间的距离H1的具体数值可以根据阵列基板的设计的不同、根据阵列基板制作工艺或切割工艺的不同而定。
在一些实施例中,参考图2d,示出了一种阵列基板的俯视图,其中,图2a是图2d沿M1M2方向的截面图。如图2d所示,多个器件12阵列排布在器件区A中,器件区A中的反射层20包括第一反射子层10和第二反射子层11,周边区B的反射层20包括第一反射子层10。图2d中只能看到位于器件区A表层的第二反射子层11;而第一反射子层10覆盖位于周边区B的衬底1的边缘,第二反射子层11向器件区 A内缩;使得第二反射子层11的边缘到衬底1的边缘之间的距离H1的范围控制在0.2-2mm之间。图2d中绘制的器件12为发光器件。
在一些实施例中,第一反射子层10和第二反射子层11包括的材料可以不同,例如:第一反射子层10的材料可以包括白色油墨,第二反射子层11的材料可以包括硅系白胶;或者,第一反射子层10的材料可以包括白色油墨,第二反射子层11的材料可以包括反射片。
或者,第一反射子层10和第二反射子层11包括的材料可以相同,例如:第一反射子层10和第二反射子层11的材料均包括白色油墨。在第一反射子层10和第二反射子层11的材料包括白色油墨或包括硅系白胶的情况下,可采用丝网印刷工艺,分别印刷形成第一反射子层10和第二反射子层11。
示例性地,第一反射子层10在沿垂直于衬底1方向上的厚度范围可以为25μm-35μm,例如:25μm、28μm、30μm、32μm或35μm。
示例性地,第二反射子层11在沿垂直于衬底1方向上的厚度范围可以为25μm-35μm,例如:25μm、28μm、30μm、32μm或35μm。
在本申请的一些实施例中,参考图2a所示,第二反射子层11位于器件区A;第二反射子层11在衬底1上的正投影与周边区B互不交叠。需要说明的是,由于周边区B是指在制备阵列基板的过程中,器件区A与阵列基板边界(切割线)之间的区域,在周边区B的衬底1上设置第一反射子层10,而不设置第二反射子层11,一方面,能够改善在从母板切割成阵列基板时,切割工艺造成反射层20的薄膜剥落(Peeling)问题;另一方面,由于周边区B的衬底1上设置了第一反射子层10,第一反射子层10覆盖到了衬底1的外轮廓,从而在阵列基板发光时,周边区B的第一反射子层10能够将阵列基板发出的光线反射出去,改善了阵列基板的周边区B较器件区A存在的较大光学亮度差异问题,很大程度上增加阵列基板沿垂直于衬底1所在平面的方向上的出光量,从而提高阵列基板的出光效率。
在一些实施例中,在第一反射子层10和第二反射子层11的材料均包括白色油墨,第一反射子层10和第二反射子层11厚度范围均在25- 35μm的情况下,如图2a所示的阵列基板中,器件区A的反射层20和周边区B的反射层20的对光线的反射率数值相差在5%以内,并不会造成器件区A和周边区B明显的光学差异。
在本申请的一些实施例中,参考图1a所示,第一反射子层10和第二反射子层11在衬底1上的正投影均延伸并覆盖周边区B,进一步地,第一反射子层10和第二反射子层11的边界与衬底1的外轮廓基本重合,从而在阵列基板发光时,周边区B的第一反射子层10和第二反射子层11能够将阵列基板发出的光线反射出去,在第一反射子层10和第二反射子层11的双重作用下,能够很好的改善阵列基板的周边区B较器件区A存在的较大光学亮度差异问题,另外,很大程度上增加阵列基板沿垂直于衬底1所在平面的方向上的出光量,从而提高阵列基板的出光效率。
在一些实施例中,参考图2d所示,阵列基板还包括位于其一侧的绑定区D,绑定区D中并未设置反射层20,绑定区D包括多个绑定端子组107,绑定端子组107的一端用于与外部电路(电路板或者集成电路)的金手指结构连接以接收电信号,另一端与阵列基板上的导电图案,例如信号线连接以传输电信号。
在本申请的一些实施例中,第一反射子层10和第二反射子层11在沿垂直于衬底1方向上的厚度相同。
示例性地,第一反射子层10和第二反射子层11在沿垂直于衬底1方向上的厚度均为25μm,或均为30μm,或均为35μm。
在本申请的一些实施例中,参考图1a或图2a所示,阵列基板还包括辅助反射部13;辅助反射部13位于层间介质层30上,且辅助反射部13和反射层20相连。
在工艺稳定性足够高的情况下,在器件区A中,反射层20在衬底1上的正投影覆盖层间介质层30除镂空区L的部分。然而,考虑到工艺精度和制作误差,在实际制作过程中,在器件区A中除镂空区L之外的部分区域,反射层20在衬底1上的正投影落入层间介质层30在衬底1上的正投影以内,故而,为了保证反射效果,在设置反射层30之 后,再设置辅助反射部13来增强反射效果。
在一些实施例中,采用多次丝网印刷工艺制作反射层20时,参考图1a所示,镂空区L边缘的反射层20可以呈现台阶状,镂空区L边缘附近的反射层20暴露出层间介质层30位于镂空区L的部分,此时,可以再在该部分层间介质层30上设置辅助反射部13,以覆盖镂空区L边缘的反射层20暴露出的层间介质层30的部分表面,从而进一步增加阵列基板沿垂直于衬底1所在平面的方向上的出光量,从而提高阵列基板的出光效率。
在一些实施例中,在反射层20的镂空区L侧壁处设置辅助反射部13,可以缩小镂空区L的径向尺寸,提高镂空区L的尺寸精度。附图中均以镂空区L的径向尺寸未缩小的情况进行标记。
在一些实施例中,参考图2b所示,辅助反射部13与层间介质层30接触的表面到辅助反射部13远离层间介质层30的表面之间的距离T2大于反射层20与层间介质层30接触的表面到反射层20远离层间介质层30的表面之间的距离T1。
示例性的,辅助反射部13的与层间介质层30接触的表面到辅助反射部13远离层间介质层30的表面之间的距离T2的范围可以为50μm-80μm;反射层20与层间介质层30接触的表面到反射层20远离层间介质层30的表面之间的距离T1的范围可以为30μm-50μm。
需要说明的是,可以通过喷涂工艺实现在围绕镂空区L的边缘设置辅助反射部13。
在一些实施例中,辅助反射部13的材料包括硅系白胶,硅系白胶的颜色为白色,使辅助反射部13的颜色与反射层20的颜色大致相同,以保证辅助反射部13对光线的反射率接近于反射层20对光线的反射率。
在本申请的一些实施例中,参考图1a或图2a所示,辅助反射部13包括第一反射部132和第二反射部131,第一反射部132和第二反射部131为一体结构。
反射层20中的镂空区L暴露出层间介质层30的部分区域,第一 反射部132在衬底1上的正投影位于镂空区L,且第一反射部132与层间介质层30直接接触;第二反射部131与反射层20远离衬底1的表面直接接触,且第二反射部131在衬底1上的正投影与反射层20在衬底1上的正投影交叠。
在一些实施例中,参考图2a所示,第二反射部131覆盖部分第一反射子层10远离衬底1的表面,且第二反射部131在沿平行于衬底1所在平面的方向上与第二反射子层11之间存在间隙Z。或者,参考图2b所示,第二反射部131覆盖部分第一反射子层10远离衬底1的表面,且第二反射部131在沿平行于衬底1所在平面的方向上与第二反射子层11相连。或者,参考图2c所示,第二反射部131覆盖部分第一反射子层10远离衬底1的表面,且第二反射部131还覆盖部分第二反射子层11远离衬底1的表面。
在本申请的一些实施例中,参考图1a或图2a所示,阵列基板还包括多个与器件12对应的封装单元14,封装单元14在衬底1上的正投影覆盖器件12在衬底1上的正投影,且封装单元14在衬底1上的正投影与反射层20在衬底1上的正投影部分交叠。
示例性地,如图1a或图2a所示,每个封装单元14包裹住一个器件12。封装单元14在对器件12起到封装保护作用的同时,还可通过设计其远离衬底1的表面形状,例如使其具有类凸透镜的表面,从而可以进一步地调整器件12包括的发光器件的出光角度。
在一些实施例中,阵列基板还可以包括设置于器件12远离衬底1一侧的封装层,用于保护器件12。
示例性地,封装层可以是整层的覆盖在多个器件12上。
图4示出了阵列基板的器件区A的一种结构示意图,参考图4所示,阵列基板的器件区A包括位于衬底1上依次设置的缓冲层2和第一导电层7,层间介质层30位于第一导电层7远离衬底1的一侧;其中,层间介质层30包括第一绝缘层8和第一平坦层9,第一平坦层9至少位于第一绝缘层8和反射层20之间。
第一导电层7用于形成导电图案。
示例性地,参考图4所示,阵列基板中设置了第一导电层7,第一导电层7被第一绝缘层8覆盖的部分构成了导电图案中的走线73,用于传输电信号;而第一导电层7未被第一绝缘层8覆盖且远离衬底1的表面的部分构成导电焊盘,用于与器件12电连接,以将走线73中传输的电信号传给器件12。
示例性地,在衬底1上有足够的空间排布所有导电图案的情况下,阵列基板可以只包括一层导电层。
在一些实施例中,第一导电层7的材料可以包括铜、铝、镍、钼和钛中的任意一种或者层叠设置的几种金属的组合。
示例性地,第一导电层7可以包括依次层叠设置的钼镍钛合金(MoNiTi)层、铜金属层和钼铌合金(MoNb)层,钼镍钛合金层可提高电镀工艺中铜金属晶粒的成核密度,钼铌合金层起到防止铜金属氧化的作用。第一导电层7中的钼镍钛合金层的厚度范围可为
Figure PCTCN2022103454-appb-000001
例如,厚度可为
Figure PCTCN2022103454-appb-000002
Figure PCTCN2022103454-appb-000003
在一些实施例中,第一导电层7的厚度范围可为1.5μm~7μm,例如,厚度可为1.5μm、2μm、4μm、6.5μm或7μm。
图5示出了阵列基板的器件区A的另一种结构示意图,参考5所示,阵列基板的器件区A还包括位于缓冲层2上依次层叠设置的第二导电层3、第二绝缘层4、第二平坦层5和第三绝缘层6,第三绝缘层6位于第一导电层7远离第一绝缘层8的一侧。
在一些实施例中,参考图5所示,第一导电层7和第二导电层3共同构成导电图案。其中,第一导电层7相对于第二导电层3更远离衬底1设置,所以第一导电层7远离衬底1的表面未被层间介质层30覆盖的部分构成导电焊盘,用于与器件12电连接,第一导电层7被其他膜层覆盖的部分以及第二导电层3构成导电图案中的信号线和连接线,用于接收并向器件12传输来自外部信号源电路的电信号。在本申请的实施例提供的附图中,并未具体绘制出第二导电层3的导电图案,其图案化的结构可以根据阵列基板的电路布图设计而定。
在一些实施例中,第二导电层3的材料可以包括铜、铝、镍、钼和 钛中的任意一种或者层叠设置的几种金属的组合。
在一些实施例中,第二导电层3可包括依次层叠设置的钼铌合金层、铜金属层和保护层,保护层可包括铜镍合金(CuNi)、镍或氧化铟锡(Indium Tin Oxide,简称ITO)中的任一者。其中,钼铌合金层起到提高铜金属与靠近衬底一侧膜层的粘附力的作用,保护层起到防止铜金属氧化的作用。
示例性地,第二导电层3的厚度范围可为0.5-10μm,例如,厚度可为0.5μm、1μm、1.8μm、2.7μm或10μm。
在本申请的一些实施例中,参考图1a或图2a所示,第一导电层7远离衬底1的表面被裸露的部分构成导电焊盘,导电焊盘例如包括至少一个第一焊盘71和至少一个第二焊盘72,层间介质层30具有沿垂直于衬底1方向上的多个第一开口K1和多个第二开口K2,第一开口K1暴露出第一焊盘71所在的区域,第二开口K2暴露出第二焊盘72所在的区域;
其中,第一焊盘71通过第一开K1口和器件12的第一焊脚151电连接,第二焊盘72通过第二开口K2和器件12的第二焊脚152电连接。
在一些实施例中,第一焊盘71和第一焊脚151之间通过位于第一开口K1中的焊接材料(例如焊锡,图中未示出)电连接,第二焊盘72和第二焊脚152之间通过位于第二开口K2中的焊接材料电连接,以通过第一焊接71和第二焊盘72将电信号传输给器件12。
在一些实施例中,焊接材料可预先印刷在第一焊盘71和第二焊盘72上,或者,也可预制在第一焊脚151和第二焊脚152上。
在本申请的一些实施例中,阵列基板还包括多个支撑柱102,支撑柱102位于反射层20远离衬底1的一侧,且支撑柱102在衬底1上的正投影与器件12在衬底1上的正投影互不交叠。
需要说明的是,支撑柱102的颜色可根据需要进行选择,例如,支撑柱102的颜色可以是白色,以使支撑柱102的反射率接近于反射层20的反射率。又例如,支撑柱102可以是透明的。
在一些实施例中,参考图1b所示,周边区B还可以包括缓冲层2、第二导电层3、第二绝缘层4、第二平坦层5、第三绝缘层6、第一导电层7、第一绝缘层8和第一平坦层9中的至少一个或多个膜层。周边区B除反射层20之外,可以包括的其它膜层结构可根据实际设计而定,这里不做限制。
本申请的实施例还提供了一种发光装置,参考图6所示,包括如上的阵列基板100。
其中,图1a中衬底1以及衬底1与反射层20之间的所有膜层构成图6中所示的基底101,示例性地,基底101包括衬底1以及位于衬底1上层叠设置的缓冲层2、第二导电层3、第二绝缘层4、第二平坦层5、第三绝缘层6、第一导电层7、第一绝缘层8和第一平坦层9。
阵列基板100具体包括的膜层和部件可以参考前文说明,这里不再赘述。
在一些实施例中,提供一种发光装置,该发光装置包括本申请的实施例提供的阵列基板。
在一些实施例中,该发光装置还可以包括覆盖该阵列基板的保护基板(或盖板)。
该发光装置可以用作背光装置,或者,也可以用作显示装置。具体的,若发光装置中的多个器件12均为发单一颜色光的发光器件,则上述发光装置可以用作背光装置;若发光装置中的多个器件12包括分别发不同颜色光的发光器件,例如红光、发绿光和发蓝光的三种发光器件,则上述发光装置可以用作显示装置。
在一些实施例中,在上述阵列基板100用在显示装置中时,阵列基板100中可不设置支撑柱102。
在本申请的一些实施例中,参考图6所示,发光装置还包括依次层叠设置的扩散板103、量子点膜104、扩散片105和复合膜106;其中,扩散板103位于阵列基板100的出光侧。
多个支撑柱102用于支撑多个光学膜片(包括扩散板103、量子点膜104、扩散片105和复合膜106),使阵列基板100中的反射层20与 光学膜片之间具有混光距离,可改善阵列基板所产生的灯影,提高发光装置的显示画质。
在一些实施例中,扩散板103的材料可以包括玻璃、聚苯乙烯(PS)、聚碳酸酯(PC)、聚乙烯(PE)、聚丙烯(PP)、聚氯乙烯(PVC)、聚对苯二甲酸乙二醇酯(PET)、亚克力(PMMA)、丙烯酸(MMA)中的任意一种。
具体的,量子点膜(QD Enhancement Films,简称QDEF)是将量子点荧光粉与聚合物混合均匀后制成膜片中的技术,示例性地,量子点膜104的材料可以包括钙钛矿量子点材料,其厚度一般在100um左右。
在一些实施例中,扩散片105的材料可以与扩散板103的材料相同。
在一些实施例中,复合膜106在用作提高光效的同时,还用作扩散板103、量子点膜104和扩散片105的保护膜,对其起到保护作用,以防止以刮伤或损坏。
在本申请的实施例提供的发光装置中,由于衬底1的外轮廓与阵列基板的周边区B的外轮廓一致,且位于周边区B的反射层20覆盖位于周边区B的衬底1,故而,位于周边区B的反射层20覆盖到了衬底1的外轮廓,使得周边区B的衬底1上不存在无反光区,从而在发光装置发光时,周边区B的反射层20能够将发光装置发出的光线反射出去,很大程度上改善了发光装置的周边区B较器件区A存在的较大光学亮度差异问题,很大程度上增加发光装置沿垂直于衬底1所在平面的方向上的出光量,从而提高发光装置的出光效率。
本申请的实施例还提供了一种拼接显示装置,参考图7所示,包括至少两个如上所述的发光装置。
需要说明的是,用作拼接显示装置中的发光装置,其中的多个器件12同时包括发红光、发绿光和发蓝光的三种发光器件。
在一些实施例中,拼接显示装置还可以包括多端口转发器、供电设备、第一框体和第二框体。
其中,每个发光装置的出光面均位于同一平面、且每个发光装置均与第一框体固定,第一框体与第二框体固定,且第二框体位于第一框体 远离发光装置的一侧,多端口转发器和供电设备均与第二框体固定;多端口转发器和供电设备电连接,每个发光装置的绑定端子组107分别与多端口转发器电连接。
需要说明的是,图7所示的拼接显示装置是由图2d中所示的阵列基板构成的发光装置拼接得到的。
在本申请的实施例提供的拼接显示装置中,由于用作拼接显示装置中的发光装置的周边区B中也设置有反射层20(在图7中,周边区B中设置了第一反射子层10),能够将发光装置发出的光线反射出去,很大程度上改善了发光装置的周边区B较器件区A存在的较大光学亮度差异问题,在由该发光装置拼接形成的拼接显示装置中,在拼缝宽度足够小且人眼几乎难以察觉的情况下,相邻两个发光装置中间的区域不存在光学暗区,从而大大提高了拼接显示装置的显示效果。
对于前文中所述的阵列基板,由于周边区B中的衬底1上设置有反射层20,一方面,采用常规的刀轮正面切割工艺从阵列基板的母板正面切割成阵列基板时,参考图8c所示,由于切割刀轮302固定在刀轮夹具301上,刀轮夹具301会刮伤阵列基板上的封装单元14,并在封装单元14上留下如图8a中所示的刮痕。另一方面,由于切割刀轮302直接切割到反射层20上,在反射层20上会留下如图8a和如图8b中所示的刀痕,使得局部的反射层20发生剥离,剥离掉的反射层20的碎屑掉落回反射层20上,影响反射层20的反射效果。再一方面,采用刀轮正面切割工艺会切割到反射层20,而在反射层20的影响下,切割刀轮302很难直接切割到衬底1表面上,导致切割失败。
图8d示出了一种刀轮正面切割工艺的示意图。待切割基板位于切割机台305上,采用刀轮正面切割工艺需要满足以下条件,才能确保切割成功:首先,反射层20到切割刀轮302的轴线(切割线所在位置处)之间的距离d1大于或等于0.7mm,才能使得刀轮302直接切割到衬底1的表面。其次,刀轮的夹具301到封装单元104之间的距离d2大于0mm,才能确保刀轮的夹具301不会刮伤封装单元104。实际应用中采用的刀轮,其轴线到夹具301一侧边缘之间的距离为3mm左右,在封 装单元14的半径r为1.25mm,切割工艺波动范围为0.25mm的情况下,切割刀轮302的轴线到封装单元14的在母板衬底400上的正投影的几何中心之间的距离d3满足d3≥3mm+1.25mm+0.25=4.5mm。然而,采用刀轮正面切割工艺得到的阵列基板,由于反射层20未延伸至周边区B,故周边区B较器件区A存在较大光学亮度差异的问题。
为此,本申请的实施例提供了一种阵列基板的制备方法,应用于制备如上所述的阵列基板,参考图9所示,该方法包括:
S901、提供如图10或如图11中所示的母板衬底400;母板衬底400划分为至少一个器件区A和与器件区A相邻的切割区C;
需要说明的是,通过将切割区C中切割线以外的区域C1切除之后,可以得到周边区B。
示例性地,将如图10中所示的母板衬底400沿切割线切割,去除母板衬底400的C1区域后,可以得到至少一个衬底1。
S902、在母板衬底400的器件区A上形成层间介质层30;
S903、在母板衬底400的器件区A和切割区C上形成反射层20;
其中,反射层20具有沿垂直于母板衬底400方向上的多个镂空区L;层间介质层30至少位于母板衬底400和反射层20之间;反射层20位于器件区A的部分在母板衬底400上的正投影与层间介质层30在母板衬底400上的正投影部分交叠,反射层20位于切割区C的部分覆盖母板衬底400的切割区C。
S904、在母板衬底400的器件区A绑定多个器件12;器件12位于镂空区L内;
器件区A中设置有阵列排布的多种器件12,器件12包括发光器件,且还包括传感器件、微型驱动芯片或其它种类的器件中的任意一种。
层间介质层30至少位于衬底1和反射层20之间的含义为:参考图1a所示,在阵列基板未设置器件12的区域,层间介质层30位于衬底1和反射层20之间;在镂空区L中,导电图案之间的(导电焊盘71和72之间)的部分区域设置有部分层间介质层30,且该部分层间介质层30位于衬底1和器件12之间。
结合图10和图1a所示,层间介质层30具有沿垂直于母板衬底400方向上的多个第一开口K1和多个第二开口K2。第一开口K1和/或第二开口K2在衬底1上的正投影位于镂空区L在衬底1上的正投影范围内。
层间介质层30中的第一开口K1暴露出设置在衬底1上的导电图案71,层间介质层30中的第二开口K2暴露出设置在衬底1上的导电图案72,以使得器件12分别与导电图案71和导电图案72相连接,而导电图案与外部信号源电路相连接从而接收电信号。
器件区A和切割区C中均设置有反射层20,示例的:参考图10或图11所示,在阵列基板的母板中除设置器件12的镂空区L之外的所有区域,均设置有一层反射层20。
在一些实施例中,缓冲层2、第二导电层3、第二绝缘层4、第二平坦层5、第三绝缘层6、第一导电层7、第一绝缘层8和第一平坦层9中的至少一个膜层可以延伸到切割区C,可根据实际设计而定,这里不做限制。
S905、从母板衬底400的背面沿切割线切割,得到至少一个阵列基板;切割线位于切割区C,背面为母板衬底400远离器件12的表面。
图12a示出了一种背面切工艺的示意图。
在一些实施例中,参考图12a所示,在从母板衬底400的背面沿切割线切割时,阵列基板的母板位于切割机台305上,切割刀轮302设置在母板衬底400的背面。另外,由于母板衬底400切割区附近没有切割机台305支撑,处于悬空状态,在与切割刀轮302相对的阵列基板的母板的另一侧,还设置有滚轮306,以抵消切割刀轮302在从母板衬底400的背面切割时产生的切割压力。
由于母板衬底400的背面未设置反射层20,可以根据切割需求在切割区的任意位置切割,这样,在切割时,不需要考虑切割刀轮302的轴线到反射层20的边缘之间的距离,也不需要考虑切割刀轮302的夹具301可能存在的对封装单元14的刮伤和磨损问题;且从背面进行切割,切割刀轮302可以直接接触到母板衬底400的背面,不存在反射层 20的影响导致的切割失败问题。
需要说明的是,图12a、图13a和图14a中,母板衬底400上绘制了反射层20、器件12和封装单元14,阵列基板的母板包括的其它结构均未绘示,阵列基板的母板包括的其它结构与阵列基板包括的结构类似,具体可参考前文对阵列基板的结构的说明,这里不进行赘述。
图12b示出了图12a中阵列基板的母板的切割线位置示意图。在图12b中,虚线所标记的位置为切割线所在的位置,沿切割线将切割线之外的区域C1切掉之后,可以得到阵列基板。其中,阵列基板的母板的切割线之外的区域C1中也设置有反射层20,然而,由于采用背面切割工艺,反射层20并不会对切割过程造成影响。
在一些实施例中,如图13a所示,示出了另一种背面切割工艺的示意图。图13a中,切割线位于两个阵列基板的母板的中间位置,切割机台305的中间位置挖空,以留出空间在此处设置切割刀轮302。图13b示出了图13a中阵列基板的母板的切割线位置示意图。其中,两条切割线中间的区域为需要切割掉的C1区域。
在一些实施例中,如图14所示,为了提高切割刀轮302背面切割时的切割效率,可以采用多刀轮同时切割的方式进行切割。在图14中,每一个设置切割刀轮302的位置对应的阵列基板的母板中,在反射层20远离母板衬底400的一侧均设置有滚轮306,以平衡切割刀轮302切割时产生的切割压力。
本申请的实施例提供了一种如图18所示的真空吸盘500,该真空吸盘500为软嘴吸盘,对具有非平坦表面的阵列基板有很好的吸附作用,用于在切割时搬运和移动阵列基板的母板或者阵列基板。
参考图15a所示,在切割之后还可以对阵列基板的边缘进行研磨,以降低阵列基板边缘由于可能存在的凸起、缺口或微裂纹而导致的破损的概率,提高阵列基板的可靠性。
在斜角研磨工艺中,将阵列基板放置在研磨机台307上,研磨刀轮308沿逆时针方向旋转,以使得研磨刀轮308先研磨到反射层20,再研磨到衬底1,避免先研磨衬底1时,对反射层20产生拉扯造成的反射 层20的局部剥离。其中,斜角研磨工艺在研磨时,研磨刀轮308与阵列基板的初始研磨点为如图15a中所示的反射层20的表面与衬底1的侧面的交界处,在研磨结束后,阵列基板会产生如图15c中所示的研磨区(斜角所在区域),对该区域进行显微镜测试可以看到,研磨区G1的宽度为如图15b中所示的150um左右,该区域内无反射层20,这严重影响了阵列基板的光学性能。
为此,在本申请的一些实施例中,从母板衬底400的背面沿切割线切割,得到至少一个阵列基板的步骤之后,该制备方法还包括:
S906、采用垂直研磨工艺对阵列基板的边缘进行研磨。
在本申请的一些实施例中,S906、采用垂直研磨工艺对阵列基板的边缘进行研磨的步骤包括:
S9061、参考图16所示,在沿垂直于阵列基板100的方向上,同时对阵列基板的衬底1的侧面和反射层20的侧面进行研磨;其中,衬底1的侧面和反射层20的侧面共面。
需要说明的是,在图16中,衬底1与反射层20之间的其它膜层均未绘制,具体可以参考前文中的说明。
在一些实施例中,采用垂直研磨工艺研磨阵列基板的过程参考图16所示,研磨刀轮308的初始研磨点为阵列基板的侧面,具体的,研磨刀轮308沿逆时针方向旋转,并对衬底1的侧面和反射层20的侧面同时进行研磨,从而可以很大程度上减少阵列基板边缘的反射层20的磨损程度与衬底1的磨损程度的差距,进而缩小研磨区G2的研磨宽度,采用垂直研磨工艺研磨的阵列基板的研磨区G2的研磨宽度为100um左右,垂直研磨工艺很大程度上提高了阵列基板的边缘位置光学性能。
在本申请的一些实施例中,S903、在母板衬底400的器件区A和切割区C上形成反射层20的步骤包括:
S9031、形成第一反射子层10,第一反射子层10在母板衬底400上的正投影位于器件区A和切割区C内;
S9032、形成第二反射子层11,第二射子层11在母板衬底400上的正投影位于器件区A内;
或者,形成第一反射子层10,第一反射子层10在母板衬底400上的正投影位于器件区A和切割区C内;
在器件区A和切割区C形成第二反射子层11,第二射子层11在母板衬底400上的正投影位于器件区A和切割区C内。
在一些实施例中,在一些实施例中,参考图10所示,第一反射子层10覆盖衬底1的边缘,第二反射子层11向器件区A内缩;使得第二反射子层11的边缘到衬底1的边缘(切割线)之间的距离H1的范围控制在0.2-2mm之间。
示例性地,第二反射子层11的边缘到衬底1的边缘之间的距离H1可以为0.2mm,0.4mm、0.5mm、0.8mm、1mm、1.5mm、1.8mm或2mm,第二反射子层11的边缘到衬底1的边缘之间的距离H1的具体数值可以根据阵列基板的设计的不同、根据阵列基板制作工艺或切割工艺的不同而定,这里不做限定。
在一些实施例中,第一反射子层10和第二反射子层11包括的材料可以不同,例如:第一反射子层10的材料可以包括白色油墨,第二反射子层11的材料可以包括硅系白胶。或者,第一反射子层10和第二反射子层11包括的材料可以相同,例如:第一反射子层10和第二反射子层11的材料均包括白色油墨。在第一反射子层10和第二反射子层11的材料包括白色油墨或包括硅系白胶的情况下,可采用丝网印刷工艺,分别印刷形成第一反射子层10和第二反射子层11。
示例性地,第一反射子层10的厚度范围可以为25μm-35μm,例如:25μm、28μm、30μm、32μm或35μm。
示例性地,第二反射子层11的厚度范围可以为25μm-35μm,例如:25μm、28μm、30μm、32μm或35μm。
在本申请的一些实施例中,在母板衬底400的器件区A绑定多个器件12的步骤之后,且在从母板衬底400的背面沿切割线切割,得到至少一个阵列基板的步骤之前,方法还包括:
在层间介质层30上形成辅助反射部13;其中,辅助反射部13与反射层20相连。
在一些实施例中,采用多次丝网印刷工艺制作反射层20时,镂空区L边缘的反射层20可以呈现台阶状,镂空区L边缘的反射层20暴露出层间介质层30的部分区域,此时,可以再在层间介质层30上设置辅助反射部13,以覆盖镂空区L边缘的反射层20暴露出的部分层间介质层30,这样,弥补了部分层间介质层30上未覆盖反射层20的问题,从而进一步增加阵列基板沿垂直于衬底1所在平面的方向上的出光量,从而提高阵列基板的出光效率。
在一些实施例中,在反射层20的镂空区L侧壁处设置辅助反射部13,可以减小镂空区L的径向尺寸,提高镂空区L的尺寸精度。
需要说明的是,可以通过围绕镂空区边缘采用喷涂工艺制备辅助反射部13,且参考图2b所示,辅助反射部13与层间介质层30接触的表面到辅助反射部13远离层间介质层30的表面之间的距离T2大于反射层20与层间介质层30接触的表面到反射层20远离层间介质层30的表面之间的距离T1。
在一些实施例中,辅助反射部13的材料包括硅系白胶,硅系白胶的颜色为白色,使辅助反射部13的颜色与反射层20的颜色大致相同,以保证辅助反射部13对光线的反射率接近于反射层20对光线的反射率。
本申请的实施例分别提供采用正切工艺和背切工艺切割的阵列基板形成拼接显示装置的结构示意图。图17a示出了一种正切工艺切割的阵列基板形成拼接显示装置的结构示意图,图17b示出了一种背切工艺切割的阵列基板形成拼接显示装置的结构示意图。
在图17a所示的拼接显示装置中,形成发光装置的阵列基板采用正切工艺得到,发光装置中未设置反射层的区域标记为20N,拼接显示装置包括两个发光装置,在每个发光装置中,反射层20的边缘到发光装置的边缘的距离为0.7mm,拼接显示装置的拼缝宽度d5=0.9mm,则相邻两个发光装置中间的未设置反射层的区域的宽度d6=d5+0.7mm*2=2.3mm。也即拼接显示装置中相邻两个发光装置的显示区之间的距离为2.3mm,在拼接显示装置显示画面时,会存在宽度为 2.3mm的区域不显示画面(非显示区),严重降低拼接显示装置的显示效果。
在图17b所示的拼接显示装置中,形成发光装置的阵列基板采用背切工艺得到。拼接显示装置包括两个发光装置,在每个发光装置中,用于拼接的每个发光装置不存在无反射层的区域,则相邻两个发光装置中间的未设置反射层的区域的宽度d6=d5=0.9mm,相对于正切工艺得到的拼接显示装置,采用背切工艺得到的拼接显示装置中相邻两个发光装置之间具有较小的非显示区,从而很大程度上提高了拼接显示装置的显示效果。
以上所述,仅为本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板,其中,包括:
    器件区;
    与所述器件区相邻的周边区;
    所述器件区和所述周边区均包括衬底和位于所述衬底上的反射层;
    所述器件区还包括层间介质层和多个器件,所述层间介质层至少位于所述衬底和所述反射层之间;所述反射层具有沿垂直于所述衬底方向上的多个镂空区,所述器件位于所述镂空区内;
    其中,所述反射层位于所述器件区的部分在所述衬底上的正投影与所述层间介质层在所述衬底上的正投影部分交叠,所述反射层位于所述周边区的部分覆盖所述衬底位于所述周边区的部分,且所述衬底的外轮廓与所述周边区的外轮廓一致;所述器件至少包括发光器件。
  2. 根据权利要求1所述的阵列基板,其中,所述反射层包括第一反射子层和第二反射子层,所述第二反射子层位于所述第一反射子层远离所述衬底的一侧;所述第一反射子层在所述衬底上的正投影位于所述器件区和所述周边区;
    其中,所述第一反射子层位于所述器件区的部分在所述衬底上的正投影与所述层间介质层在所述衬底上的正投影部分交叠,且所述第一反射子层还覆盖所述衬底位于所述周边区的部分;
    所述第二反射子层在所述衬底上的正投影位于所述第一反射子层在所述衬底上的正投影以内。
  3. 根据权利要求2所述的阵列基板,其中,所述第二反射子层在所述衬底上的正投影位于所述器件区;
    所述第二反射子层在所述衬底上的正投影与所述第一反射子层位于所述周边区的部分在所述衬底上的正投影互不交叠。
  4. 根据权利要求2所述的阵列基板,其中,所述第二反射子层在所述衬底上的正投影位于所述周边区和所述器件区;
    所述第二反射子层位于所述周边区的部分在所述衬底上的正投影与所述第一反射子层位于所述周边区的部分在所述衬底上的正投影重 叠。
  5. 根据权利要求2所述的阵列基板,其中,所述第一反射子层和所述第二反射子层在沿垂直于所述衬底方向上的厚度相同。
  6. 根据权利要求1所述的阵列基板,其中,所述阵列基板还包括辅助反射部;所述辅助反射部位于所述层间介质层上,且所述辅助反射部和所述反射层相连。
  7. 根据权利要求6所述的阵列基板,其中,所述辅助反射部包括第一反射部和第二反射部,所述第一反射部和所述第二反射部为一体结构;
    所述镂空区暴露出所述层间介质层的部分区域,所述第一反射部在所述衬底上的正投影位于所述镂空区,且所述第一反射部与所述层间介质层直接接触;
    所述第二反射部与所述反射层远离所述衬底的表面直接接触,且所述第二反射部在所述衬底上的正投影与所述反射层在所述衬底上的正投影交叠。
  8. 根据权利要求1所述的阵列基板,其中,所述阵列基板还包括多个与所述器件对应的封装单元,所述封装单元在所述衬底上的正投影覆盖所述器件在所述衬底上的正投影,且所述封装单元在所述衬底上的正投影与所述反射层在所述衬底上的正投影部分交叠。
  9. 根据权利要求1所述的阵列基板,其中,所述阵列基板的所述器件区还包括位于所述衬底上依次设置的缓冲层和第一导电层,所述层间介质层位于所述第一导电层远离所述衬底的一侧;
    其中,所述层间介质层包括第一绝缘层和第一平坦层,所述第一平坦层至少位于所述第一绝缘层和所述反射层之间。
  10. 根据权利要求9所述的阵列基板,其中,所述阵列基板的所述器件区还包括位于所述缓冲层上依次层叠设置的第二导电层、第二绝缘层、第二平坦层和第三绝缘层,所述第三绝缘层位于所述第一导电层远离所述第一绝缘层的一侧。
  11. 根据权利要求9所述的阵列基板,其中,所述第一导电层包括 至少一个第一焊盘和至少一个第二焊盘,所述层间介质层具有沿垂直于所述衬底方向上的多个第一开口和多个第二开口,所述第一开口暴露出所述第一焊盘所在的区域,所述第二开口暴露出所述第二焊盘所在的区域;
    其中,所述第一焊盘通过所述第一开口和所述器件的第一焊脚电连接,所述第二焊盘通过所述第二开口和所述器件的第二焊脚电连接。
  12. 根据权利要求11所述的阵列基板,其中,所述阵列基板还包括多个支撑柱,所述支撑柱位于所述反射层远离所述衬底的一侧,且所述支撑柱在所述衬底上的正投影与所述器件在所述衬底上的正投影互不交叠。
  13. 一种发光装置,其中,包括如权利要求1-12中任一项所述的阵列基板。
  14. 根据权利要求13所述的发光装置,其中,所述发光装置还包括依次层叠设置的扩散板、量子点膜、扩散片和复合膜;
    其中,所述扩散板位于所述阵列基板的出光侧。
  15. 一种拼接显示装置,其中,包括至少两个如权利要求13或14所述的发光装置。
  16. 一种阵列基板的制备方法,其中,应用于制备如权利要求1-12中任一项所述的阵列基板,所述方法包括:
    提供母板衬底;所述母板衬底划分为至少一个器件区和与所述器件区相邻的切割区;
    在所述母板衬底的所述器件区上形成层间介质层;
    在所述母板衬底的所述器件区和所述切割区上形成反射层;其中,所述反射层具有沿垂直于所述母板衬底方向上的多个镂空区;所述层间介质层至少位于所述母板衬底和所述反射层之间;所述反射层位于所述器件区的部分在所述母板衬底上的正投影与所述层间介质层在所述母板衬底上的正投影部分交叠,所述反射层位于所述切割区的部分覆盖所述母板衬底的所述切割区;
    在所述母板衬底的所述器件区绑定多个器件;所述器件位于所述镂 空区内;
    从所述母板衬底的背面沿切割线切割,得到至少一个所述阵列基板;所述切割线位于所述切割区,所述背面为所述母板衬底远离所述器件的表面。
  17. 根据权利要求16所述的阵列基板的制备方法,其中,所述从所述母板衬底的背面沿切割线切割,得到至少一个所述阵列基板的步骤之后,所述方法还包括:
    采用垂直研磨工艺对所述阵列基板的边缘进行研磨。
  18. 根据权利要求17所述的阵列基板的制备方法,其中,所述采用垂直研磨工艺对所述阵列基板的边缘进行研磨的步骤包括:
    在沿垂直于所述阵列基板的方向上,同时对所述阵列基板的衬底的侧面和所述反射层的侧面进行研磨;其中,所述衬底的侧面和所述反射层的侧面共面。
  19. 根据权利要求16所述的阵列基板的制备方法,其中,所述在所述母板衬底的所述器件区和所述切割区上形成反射层的步骤包括:
    形成第一反射子层;所述第一反射子层在所述母板衬底上的正投影位于所述器件区和所述切割区内;
    形成第二反射子层;所述第二反射子层在所述母板衬底上的正投影位于所述器件区内;
    或者,形成第一反射子层;所述第一反射子层在所述母板衬底上的正投影位于所述器件区和所述切割区内;
    形成第二反射子层;所述第二反射子层在所述母板衬底上的正投影位于所述器件区和所述切割区内。
  20. 根据权利要求16所述的阵列基板的制备方法,其中,所述在所述母板衬底的所述器件区绑定多个器件的步骤之后,且在所述从所述母板衬底的背面沿切割线切割,得到至少一个所述阵列基板的步骤之前,所述方法还包括:
    在所述层间介质层上形成辅助反射部;其中,所述辅助反射部与所述反射层相连。
PCT/CN2022/103454 2021-07-30 2022-07-01 阵列基板及其制备方法、发光装置和拼接显示装置 WO2023005609A1 (zh)

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