WO2023005578A1

WO2023005578A1 - Power device, preparation method therefor, and electronic apparatus

Info

Publication number: WO2023005578A1
Application number: PCT/CN2022/102361
Authority: WO
Inventors: 唐高飞; 黄伯宁; 王汉星; 包琦龙; 徐越
Original assignee: 华为技术有限公司
Priority date: 2021-07-27
Filing date: 2022-06-29
Publication date: 2023-02-02
Also published as: CN113707718A; CN113707718B

Abstract

The present application provides a power device, a preparation method therefor, and an electronic apparatus. The power device comprises a GaN buffer layer, a first barrier layer, a second barrier layer, a blocking layer, a first p-(Al)GaN part, and a gate. The GaN buffer layer and the first barrier layer are stacked. The first barrier layer is provided with a first through hole. The second barrier layer covers the side of the first barrier layer distant from the GaN buffer layer. The second barrier layer forms a trench at the first through hole. The blocking layer is provided on the side of the second barrier layer distant from the GaN buffer layer. The blocking layer is provided with a second through hole. The first p-(Al)GaN part is provided in the second through hole, and is in contact with the second barrier layer. The gate is provided on the side of the first p-(Al)GaN part distant from the blocking layer. The blocking layer may protect the second barrier layer when p-(Al)GaN is etched to reduce damage to the second barrier layer by etching, and prevent holes from being injected from the first p-(Al)GaN part to the second barrier layer during reverse conduction.

Description

Power device and its manufacturing method, electronic device

This application claims priority to a Chinese patent application filed with the State Intellectual Property Office of China on July 27, 2021, with application number 202110852751.6, and application title "Power device and its preparation method, electronic device", the entire contents of which are incorporated by reference in this application.

technical field

The present application relates to the technical field of semiconductor devices, in particular to a power device, a manufacturing method thereof, and an electronic device.

Background technique

The third-generation wide-bandgap semiconductor materials represented by gallium nitride (GaN) and silicon carbide (SiC) have the characteristics of high electron mobility, large bandgap width, high electron saturation drift rate, high voltage resistance, and high temperature resistance. Compared with traditional Si materials, it is more suitable for making power devices. Especially in heterostructures based on GaN materials (represented by AlGaN/GaN), the crystal itself can induce high-density two-dimensional electron gas (2DEG) due to its strong polarization effect. (density greater than 10 ¹³ cm ^-2 ), and in an electronic channel without intentional doping, the electron mobility can stably reach more than 1000 cm ² V ^-1 s ^-1 .

When preparing gallium nitride normally-off switching devices, a p-type GaN layer (p-GaN) is usually grown on the surface of AlGaN/GaN. At present, there are two main types of GaN enhancement devices: voltage-mode p-GaN gate (Schottky gate) devices and current-mode p-GaN gate (ohmic gate) devices. Among them, the current-mode p-GaN gate device is not sensitive to the parasitic parameters of the driving circuit because of its special driving method, and has a large design margin and is easy to use.

However, current mode p-GaN gate devices are used in high voltage switching applications, due to the existence of high electric field and hot electrons, electrons will be trapped by trap defects in current mode p-GaN gate devices under the action of electric field, this phenomenon is called For electron trapping (electron trapping). When the current mode p-GaN gate device is turned on again, because the trapped electrons cannot be released quickly, the on-resistance of the current mode p-GaN gate device will degrade.

In order to solve the problem that the trapped electrons cannot be released quickly when turned on, a p-GaN layer can be introduced near the drain. During the dynamic switching process of the device, the p-GaN layer on the drain side can generate holes to suppress the trapping of electrons, solve the problems of dynamic resistance degradation and high-temperature working life of long-term devices. However, since the AlGaN barrier layer in the gate region is easily damaged when the p-GaN layer is etched, the thickness of part of the AlGaN barrier layer is too thin. When the current mode p-GaN gate device conducts reversely, holes in the p-GaN layer are easily injected into the AlGaN barrier layer. The injected holes are stored in the AlGaN barrier layer and cannot be removed. However, there is no gate above the AlGaN barrier layer next to the drain, so that the electrons in the channel cannot recombine with the holes in the AlGaN barrier layer, resulting in the deterioration of the off-state characteristics of the current-mode p-GaN gate device. The current mode p-GaN gate device fails due to breakdown, thus affecting the reliability of the current mode p-GaN gate device.

Contents of the invention

Embodiments of the present application provide a power device capable of improving reliability, a manufacturing method thereof, and an electronic device.

In a first aspect, the present application provides a power device, including a GaN buffer layer, a first barrier layer, a second barrier layer, a barrier layer, a first p-(Al)GaN portion and a gate, and the GaN buffer layer stacked with the first barrier layer, the first barrier layer is provided with a first through hole penetrating through the first barrier layer, the second barrier layer includes a first part and a second part, so The first part covers the side of the first barrier layer away from the GaN buffer layer, and the second part covers the bottom wall of the first through hole and the side wall of the first through hole; The second part is bent and forms a groove in the first through hole, the barrier layer includes a third part and a fourth part, and the third part covers the second barrier layer away from On one side of the GaN buffer layer, the fourth part covers the side walls of the trench and part of the bottom wall of the trench, the fourth part includes a second through hole penetrating through the fourth part, and the fourth part At least part of a p-(Al)GaN portion is received in the second via hole and contacts the second portion of the second barrier layer, the gate is disposed on the first p-(Al) The side of the GaN portion facing away from the barrier layer.

The second potential barrier layer is bent at the first through hole and forms a groove, wherein the second potential barrier layer covers the bottom wall and the side wall of the first through hole. The first p-(Al)GaN portion is made of p-(Al)GaN. p-(Al)GaN is one of p-AlGaN and p-GaN.

In the power device provided by the present application, a barrier layer is grown after forming the second barrier layer, and the barrier layer can protect the second barrier layer when etching p-(Al)GaN, reducing the impact of etching on the second barrier layer damage, ensure that the second barrier layer can maintain the original thickness, prevent holes from being injected into the second barrier layer from the first p-(Al)GaN part when the power device is reversed, and effectively improve the reliability of the power device.

According to the first aspect, in a first possible implementation manner of the first aspect of the present application, the fourth part of the barrier layer also covers an end of the bottom wall of the trench that is close to the sidewall of the trench. Since the corner of the trench is covered with the barrier layer, the protective area of the barrier layer to the second barrier layer is increased, effectively preventing the etching gas with a larger plasma density at the sharp corner of p-(Al)GaN from An etching groove is formed on the second potential barrier layer, which further improves the reliability of the power device.

According to the first aspect or the first implementation of the first aspect of the present application, in the second possible implementation of the first aspect of the present application, the fourth part of the barrier layer includes a first connection part of the connection arrangement With the second connection part, the first connection part covers the side wall of the groove, the second connection part covers the bottom wall of the groove, and the second through hole is located at the On the second connection part, the first connection part and the second connection part enclose a storage cavity, and the first p-(Al)GaN part fills the storage cavity and the second communication A hole, the end of the first p-(Al)GaN part away from the GaN buffer layer is exposed outside the accommodation cavity. Since the end of the first p-(Al)GaN part away from the GaN buffer layer is exposed outside the accommodation cavity, it is convenient to arrange the gate on the first p-(Al)GaN part, thereby reducing the difficulty of manufacturing power devices .

According to the first aspect or the first to second possible implementations of the first aspect of the present application, in the third possible implementation of the first aspect of the present application, the third part of the barrier layer penetrates the The third part is also provided with a third through hole and a fourth through hole, and the power device further includes a source and a drain, and the source is arranged in the third through hole and contacts the second barrier layer , the drain is disposed in the fourth through hole and in contact with the second barrier layer.

According to the first aspect or the first to third possible implementations of the first aspect of the present application, in the fourth possible implementation of the first aspect of the present application, the third part of the barrier layer is further provided with There is a connection hole penetrating through the third part, the power device further includes a second p-(Al)GaN part and a hole injection electrode, the second p-(Al)GaN part is arranged in the connection hole and In contact with the first part of the second barrier layer, the hole injection electrode is arranged on the side of the second p-(Al)GaN part away from the second barrier layer, the hole injection electrode and the drain connection. The second p-(Al)GaN portion is made of p-(Al)GaN. p-(Al)GaN is one of p-AlGaN and p-GaN.

According to the first aspect or the first to fourth possible implementations of the first aspect of the present application, in the fifth possible implementation of the first aspect of the present application, the first potential barrier layer and the first potential barrier layer The materials of the two barrier layers are the same, and the material of the first barrier layer is one of AlGaN and InAlN.

According to the first aspect or the first to fifth possible implementations of the first aspect of the present application, in the sixth possible implementation of the first aspect of the present application, the thickness of the first barrier layer is greater than The thickness of the second barrier layer.

According to the first aspect or the first to sixth possible implementations of the first aspect of the present application, in the seventh possible implementation of the first aspect of the present application, the barrier layer includes silicon oxide, silicon nitride , aluminum oxide, aluminum nitride, aluminum oxynitride, silicon oxynitride in one.

In a second aspect, the present application provides a method for preparing a power device, which includes the following steps of providing a prefabricated body, the prefabricated body including a stacked GaN buffer layer and a first barrier layer, and the first barrier layer is provided with A first through hole penetrating through the first barrier layer; a second barrier layer is formed on the side of the first barrier layer away from the GaN buffer layer, and the second barrier layer includes a first part and a second barrier layer. Two parts, the first part covers the side of the first barrier layer away from the GaN buffer layer, the second part is accommodated in the first through hole and covers the first barrier layer Above, the second part is bent at the first through hole and forms a groove, and the second part covers the bottom wall of the first through hole and the side wall of the first through hole; A barrier layer is formed on the side of the second barrier layer away from the GaN buffer layer, the barrier layer includes a third part and a fourth part, and the third part covers the side of the second barrier layer away from the GaN buffer layer. One side of the GaN buffer layer, the fourth part covers the side wall of the trench and part of the bottom wall of the trench; a second via penetrating through the barrier layer is formed on the fourth part of the barrier layer hole; forming a first p-(Al)GaN portion in contact with the second portion of the second barrier layer in the second via; forming a first p-(Al)GaN portion away from the One side of the barrier layer forms a gate.

According to the second aspect, in the first possible implementation manner of the second aspect of the present application, the fourth part of the barrier layer covers the sidewall of the trench, and the fourth part also covers the sidewall of the trench. The bottom wall of the groove is close to one end of the side wall of the groove. The fourth part of the barrier layer includes a first connection part and a second connection part connected to each other, the first connection part covers the side wall of the groove, and the second connection part covers the On the bottom wall of the groove, the second through hole is located on the second connection part, the first connection part and the second connection part enclose a storage cavity, and the first p The (Al)GaN portion fills the accommodation cavity and the second accommodation hole, and an end of the first p-(Al)GaN portion away from the GaN buffer layer is exposed outside the accommodation cavity.

According to the second aspect or the first possible implementation of the second aspect of the present application, in the second possible implementation of the second aspect of the present application, the preparation method further includes: A third through hole and a fourth through hole penetrating through the barrier layer are formed on the third part, and a gate is formed on a side of the first p-(Al)GaN part away from the second potential barrier layer, It also includes forming a source in contact with the first part of the second barrier layer in the third through hole, and forming a drain in contact with the first part of the second barrier layer in the fourth through hole .

According to the second aspect or the first to second possible implementation manners of the second aspect of the present application, in the third possible implementation manner of the second aspect of the present application, the preparation method further includes, the The barrier layer is also provided with a connection hole penetrating through the third part of the barrier layer; a second p-(Al)GaN part in contact with the second potential barrier layer is formed in the connection hole; - A hole injection electrode is formed on the side of the (Al)GaN part facing away from the second potential barrier layer; the hole injection electrode is connected to the drain.

According to the second aspect or the first to third possible implementations of the second aspect of the present application, in the fourth possible implementation of the second aspect of the present application, the thickness of the first barrier layer is greater than the thickness of the second barrier layer.

In a third aspect, the present application provides an electronic device, including the power device and the circuit board provided according to the first aspect or the first to seventh possible implementation manners of the first aspect of the present application.

Description of drawings

FIG. 1 is a schematic diagram of an electronic device provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a power device provided in an embodiment of the present application;

FIG. 3 is a flowchart of a method for preparing a power device provided in an embodiment of the present application;

FIG. 4 is a schematic structural view of the prefabricated body provided in step 201 shown in FIG. 3;

FIG. 5 is a schematic structural diagram of forming a second barrier layer on the first barrier layer in step 203 shown in FIG. 3;

FIG. 6 is a schematic structural view of forming a barrier layer on the second barrier layer in step 205 shown in FIG. 3;

FIG. 7 is a flow chart of a method for manufacturing a power device provided in another embodiment of the present application.

Detailed ways

A preparation method of a normally-off switching device is to etch away the first AlGaN barrier layer in the gate region, and then epitaxially epitaxially the second AlGaN barrier layer and the p-GaN layer. The p-GaN layer in the gate region is mainly used to form a metal/p-GaN/AlGaN gate structure, and the p-GaN layer introduced next to the drain is connected to the drain for hole injection during switching. Generally, the thickness of the p-GaN layer of secondary epitaxy is relatively large (usually greater than 100nm). In order to ensure the etching margin during the p-GaN etching process, part of the second barrier layer will be etched away, and the p-GaN sharp Due to the high plasma density of the etching gas at the corner, etching trenches are often easily formed, resulting in the thickness of the second barrier layer at the sharp corner of p-GaN being too thin. When the device conducts reversely, holes are easily injected from p-GaN into the second barrier layer. The injected holes are stored in the second barrier layer. However, there is no gate above the second barrier layer next to the drain (access region), so that the electrons in the channel cannot recombine with the holes in the second barrier layer, resulting in poor off-state characteristics of the device. The device may break down and fail, thereby affecting the reliability of the device.

Based on this, the present application provides a power device, a related manufacturing method, and an electronic device. The power device comprises a GaN buffer layer, a first barrier layer, a second barrier layer, a barrier layer, a first p-(Al)GaN part and a gate, and the GaN buffer layer and the first barrier layer are stacked. The first potential barrier layer is provided with a first through hole penetrating through the first potential barrier layer. The second potential barrier layer includes a first part and a second part. The first part covers the side of the first potential barrier layer away from the GaN buffer layer. The second part covers the bottom wall of the first through hole and the side wall of the first through hole. The second part is bent and forms a groove in the first through hole. The blocking layer includes a third part and a fourth part. The third part covers the side of the first part away from the GaN buffer layer. The fourth part covers the sidewall of the trench and part of the bottom wall of the trench. The fourth part includes a second through hole passing through the fourth part. The first p-(Al)GaN portion is disposed in the second via hole and contacts the second portion of the second barrier layer. The gate is disposed on a side of the first p-(Al)GaN portion away from the barrier layer.

Referring to FIG. 1 , an embodiment of the present application provides an electronic device 100 , including a circuit board 30 and a power device 10 disposed on the circuit board 30 . The power device 10 is used for power processing, including frequency conversion, voltage conversion, current conversion, power management and so on. The electronic device 100 may be a power conversion device that needs to use the power device 10 . The power conversion device can be mounted on the power conversion equipment to complete various power functions of the equipment. For example, the power device of the present application can be applied in the field of electric vehicle power system, that is, the electric energy conversion device can be an electric vehicle, wherein the electric energy conversion device can be a motor controller, and the power device is a power conversion unit assembled in the motor controller; The power conversion device can also be an on-board charger (OBC), and the power device is an energy conversion unit; the power conversion device can also be a low-voltage control power supply, and the power device is a DC-DC conversion unit. In addition, the power device of the present application is not limited to the field of electric vehicles, and can also be widely used in traditional industrial control, communication, smart grid and other fields, for example, it can be applied to uninterruptible power supply (uninterruptible power supply, UPS), inverters for photovoltaic power generation equipment, power supplies for servers, switching power supplies for refrigerators, etc. It can be understood that the present application does not limit the electronic device 100 to a power conversion device, that is, the present application does not limit the power device 10 to perform power conversion, and the power device 10 can also be applied in the electronic device 100 to change voltage, frequency, etc. to realize circuit control .

Please refer to FIG. 2 , an embodiment of the present application provides a power device 10, including a GaN buffer layer 12, a first barrier layer 13, a second barrier layer 14, a barrier layer 15, a first p-(Al)GaN part 17 and grid 19. The GaN buffer layer 12 is stacked with the first barrier layer 13 . The first barrier layer 13 includes a first through hole 131 penetrating through the first barrier layer 13 . The second barrier layer 14 includes a first portion 141 and a second portion 143 . The first portion 141 covers a side of the first barrier layer 13 away from the GaN buffer layer 12 . The second part 143 is accommodated in the first through hole 131 . The second portion 143 of the second barrier layer 14 is bent at the first through hole 131 and forms a trench 145 . Specifically, the second portion 143 of the second barrier layer 14 covers the side walls of the first through hole 131 and the bottom wall of the first through hole 131 . The barrier layer 15 includes a third portion 150 and a fourth portion 151 . The third portion 150 covers the side of the first portion 141 of the second barrier layer 14 facing away from the GaN buffer layer 12 . The groove wall of the groove 145 includes a bottom wall 1451 and a side wall 1453 connected to each other. The fourth portion 151 covers the sidewall 1453 of the trench 145 and part of the bottom wall 1451 of the trench 145 . The fourth portion 151 includes a second through hole 152 penetrating through the fourth portion 151 of the barrier layer 15 . The first p-(Al)GaN portion 17 is accommodated in the second via hole 152 and contacts the second portion 143 of the second barrier layer 14 .

In the power device 10 provided by the present application, a barrier layer 15 is grown after the second barrier layer 14 is formed, and the barrier layer 15 can protect the second barrier layer 14 when etching p-(Al)GaN, reducing the impact of etching on the first barrier layer 14. The damage of the second potential barrier layer 14 ensures that the second potential barrier layer 14 can maintain the original thickness, which greatly reduces the hole injection from the first p-(Al)GaN part 17 to the second potential barrier when the power device 10 is reversed. Possibilities in the layer 14 effectively improve the reliability of the power device 10 . The first p-(Al)GaN portion 17 is made of p-(Al)GaN. p-(Al)GaN is one of p-AlGaN and p-GaN.

Both the first barrier layer 13 and the second barrier layer 14 are AlGaN layers. In other embodiments, the first barrier layer 13 and the second barrier layer 14 can be made of other materials, for example, InAlN and the like.

The thickness of the first barrier layer 13 is greater than the thickness of the second barrier layer 14 . It can be understood that, in other implementation manners, the thickness of the first barrier layer 13 may be less than or equal to the thickness of the second barrier layer 14 .

More specifically, the power device 10 further includes a substrate 11 disposed on a side of the GaN buffer layer 12 away from the first barrier layer 13 . The substrate 11 may be a Si substrate, a quartz substrate, a diamond substrate, etc., and the material of the substrate 11 is not limited in this application.

The bottom wall 1451 is disposed on a side of the trench 145 close to the GaN buffer layer 12 . The fourth portion 151 of the barrier layer 15 covers the sidewall 1453 and extends along the stacking direction, which is the stacking direction of the substrate 11 and the GaN buffer layer 12 (the vertical direction as shown in FIG. 2 ). Since the barrier layer 15 covers the sidewall 1453 , the first p-(Al)GaN portion 17 is effectively prevented from implanting into the second barrier layer 14 laterally (as shown in FIG. 2 ).

The barrier layer 15 is made of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum oxynitride (AlON), silicon oxynitride (SiON) kind of.

The fourth part 151 also covers the end of the bottom wall 1451 close to the side wall 1453 , that is, the corner of the trench 145 covers the barrier layer 15 , thus increasing the protection area of the barrier layer 15 to the second barrier layer 14 . When growing the p-(Al)GaN layer, the barrier layer 15 effectively prevents the etching gas with a larger plasma density at the sharp corner of the p-(Al)GaN in the trench 145 from being deposited on the second barrier layer 14 The etching trench is formed so that the thickness of the second barrier layer 14 near the sharp corner of the p-(Al)GaN in the trench 145 is not reduced, which further improves the reliability of the power device 10 .

More specifically, the fourth portion 151 is bent in the groove 145 . More specifically, the fourth portion 151 includes a first connecting portion 1511 and a second connecting portion 1513 , and the first connecting portion 1511 covers the sidewall 1453 of the trench 145 . The second connecting portion 1513 covers the bottom wall 1451 of the groove 145 , and the second through hole 152 is located on the second connecting portion 1513 . The first connecting portion 1511 and the second connecting portion 1513 enclose the receiving cavity 154 . The first p-(Al)GaN portion 17 fills the receiving cavity 154 and the second through hole 152 , and an end of the first p-(Al)GaN portion 17 away from the GaN buffer layer 12 is exposed outside the receiving cavity 154 . The first p-(Al)GaN part 17 covers the first connection part 1511 and the second connection part 1513, that is, the first p-(Al)GaN part 17 covers the bottom wall of the storage cavity 154 and the side wall of the storage cavity 154 . The first p-(Al)GaN portion 17 covers the bottom wall of the second through hole 152 and the sidewall of the second through hole 152 . It can be understood that the application does not limit the first p-(Al)GaN part 17 to the cavity 154 and the second through hole 152, and the first p-(Al)GaN part 17 contacts the second part 143 through the second through hole 152, that is, Can.

The third portion 150 of the barrier layer 15 penetrates through the barrier layer 15 and further defines a third through hole 153 and a fourth through hole 155 . The power device 10 also includes a source 21 and a drain 23, the source 21 is arranged in the third through hole 153 and is in contact with the first portion 141 of the second barrier layer 14 to form an ohmic contact, and the drain 23 is arranged in the fourth through hole 157 and is in contact with the first portion 141 of the second barrier layer 14 to form an ohmic contact.

The barrier layer 15 is further provided with a connection hole 157 penetrating through the third portion 150 of the barrier layer 15 . The power device 10 further includes a second p-(Al)GaN portion 25 and a hole injection electrode 29 . The second p-(Al)GaN portion 25 is disposed in the connection hole 157 and contacts the second barrier layer 14 . The hole injection electrode 29 is disposed on a side of the second p-(Al)GaN portion 25 away from the second barrier layer 14 and connected to the drain 23 . The hole injection electrode 29 is used for injecting holes in the second p-(Al)GaN portion 25 into the second barrier layer 14 through a voltage during the switching transient of the power device 10 . In this embodiment, the connection hole 157 is located between the second through hole 152 and the fourth through hole 155 in the direction vertical to the stacking direction, and is arranged close to the drain electrode 23, so as to facilitate the connection of the second p-(Al ) The GaN portion 25 is connected to the drain 23, thereby shortening the length of the connection line. The stacking direction is the stacking direction of the substrate 11 and the GaN buffer layer. It can be understood that the present application does not limit the positions of the second through hole 152 , the third through hole 153 , the fourth through hole 155 and the connecting hole 157 . The second p-(Al)GaN portion 25 is made of p-(Al)GaN. p-(Al)GaN is one of p-AlGaN and p-GaN.

Please refer to FIG. 3 , an embodiment of the present application also provides a method for manufacturing a power device 10, the method includes the following steps:

Step 201, please refer to FIG. 4 , provide a preform 201, the preform 201 includes a GaN buffer layer 12 and a first barrier layer 13 that are stacked, and the first barrier layer 13 is provided with a first barrier layer that penetrates the first barrier layer 13. through hole 131 . In this embodiment, the preform 201 further includes a substrate 11, a GaN buffer layer 12 is grown on the substrate 11, an AlGaN layer is grown on the side of the GaN buffer layer 12 facing away from the substrate 11, and the AlGaN layer is etched. Then the first barrier layer 13 is formed. It can be understood that the first barrier layer 13 having the first through hole 131 can be directly formed on the side of the GaN buffer layer 12 facing away from the substrate 11 .

Step 203, please refer to FIG. 5, forming a second barrier layer 14 on the side of the first barrier layer 13 away from the GaN buffer layer 12, the second barrier layer 14 is bent at the first through hole 131 and formed The trench 145 , the second barrier layer 14 covers the bottom wall of the first through hole 131 and the sidewall of the first through hole 131 .

More specifically, the second barrier layer 14 includes a first portion 141 and a second portion 143, the first portion 141 covers the side of the first barrier layer 13 away from the GaN buffer layer 12, and the second portion 143 is accommodated in the first through hole 131 inside. The second portion 143 is bent at the first through hole 131 and forms a groove 145 . The second portion 143 covers the bottom wall of the first through hole 131 and the sidewall of the first through hole 131 . The groove wall of the groove 145 includes a bottom wall 1451 and a side wall 1453 connected to each other.

In this embodiment, the second barrier layer 14 is formed on the side of the first barrier layer 13 away from the GaN buffer layer 12 by using a secondary epitaxial growth method. Both the first barrier layer 13 and the second barrier layer 14 are AlGaN layers. In other embodiments, the first barrier layer 13 and the second barrier layer 14 can be made of other materials, for example, InAlN and the like.

Step 205 , please refer to FIG. 6 , forming a barrier layer 15 on a side of the second barrier layer 14 away from the GaN buffer layer 12 . The barrier layer 15 includes a third portion 150 and a fourth portion 151 . The third portion 150 covers a side of the second barrier layer 14 away from the GaN buffer layer 12 . The fourth portion 151 covers the sidewall 1453 of the trench 145 and part of the bottom wall 1451 of the trench 145 . The fourth portion 151 includes a first connecting portion 1511 and a second connecting portion 1513 , the first connecting portion 1511 covers the sidewall 1453 of the trench 145 . The second connecting portion 1513 covers the bottom wall 1451 of the groove 145 , and the second through hole 152 is located on the second connecting portion 1513 . The first connecting portion 1511 and the second connecting portion 1513 enclose the receiving cavity 154 . The fourth portion 151 is bent in the groove 145 to form a receiving cavity 154 .

Step 207 , please refer to FIG. 6 , forming a second through hole 152 penetrating through the fourth portion 151 of the barrier layer 15 on the barrier layer 15 . In this embodiment, after the barrier layer 15 is etched, a second through hole 152 penetrating through the barrier layer 15 is formed on the second connection portion 1513 of the barrier layer 15 .

Step 209 , please refer to FIG. 2 again, forming a first p-(Al)GaN portion 17 in contact with the second barrier layer 14 in the second via hole 152 . In this embodiment, a p-(Al)GaN layer is formed on the side of the barrier layer 15 facing away from the second barrier layer 14 by a secondary epitaxy growth method, and the p-(Al)GaN layer is etched to form the first p-(Al)GaN portion 17 . The first p-(Al)GaN portion 17 is accommodated in the second through hole 152 of the accommodation cavity 154, and the end of the first p-(Al)GaN portion 17 away from the GaN buffer layer 12 is exposed outside the accommodation cavity 154, that is, the first p - The (Al)GaN portion 17 covers the bottom wall of the housing cavity 154 and the side walls of the housing cavity 154 . The p-(Al)GaN layer is etched by dry etching. Since the barrier layer 15 is arranged on the second barrier layer 14, when the p-(Al)GaN layer is etched by dry etching, the barrier layer 15 effectively protects the second barrier layer 14 below the barrier layer 15, that is, the barrier layer 15 can be used as a stop layer during etching of the p-(Al)GaN layer, reducing the possibility that the surface of the second barrier layer 14 away from the GaN buffer layer 12 is damaged during the p-(Al)GaN etching process .

Step 211 , forming a gate 19 on a side of the first p-(Al)GaN portion 17 away from the second barrier layer 14 .

In one embodiment, the preparation method further includes forming a connection hole 157 on the barrier layer 15 through the third portion 150 of the barrier layer 15; forming a second p- in contact with the second barrier layer 14 in the connection hole 157; (Al)GaN portion 25 ; forming a hole injection electrode 29 on the side of the second p-(Al)GaN portion 25 away from the second barrier layer 14 ; connecting the hole injection electrode 29 to the drain 23 .

In one embodiment, the manufacturing method further includes that the barrier layer 15 is further provided with a third through hole 153 and a fourth through hole 155 penetrating through the third portion 150 of the barrier layer 15 . The source 21 in contact with the second barrier layer 14 is formed in the third through hole 155 , so that the source 21 forms an ohmic contact with the second barrier layer 14 . The drain 23 in contact with the second barrier layer 14 is formed in the fourth through hole 155 , so that the drain 23 forms an ohmic contact with the second barrier layer 14 .

Another embodiment of the present application provides a method for manufacturing a power device 10, please refer to FIG. 7 , the method includes the following steps:

Step 301, please refer to FIG. 4 , provide a preform 201, the preform 201 includes a GaN buffer layer 12 and a first barrier layer 13 that are stacked, and the first barrier layer 13 is provided with a first barrier layer that penetrates the first barrier layer 13. through hole 131 . In this embodiment, the preform 201 further includes a substrate 11, a GaN buffer layer 12 is grown on the substrate 11, an AlGaN layer is grown on the side of the GaN buffer layer 12 facing away from the substrate 11, and the AlGaN layer is etched. Then the first barrier layer 13 is formed. It can be understood that the first barrier layer 13 having the first through hole 131 can be directly formed on the side of the GaN buffer layer 12 facing away from the substrate 11 .

Step 303, please refer to FIG. 5, forming a second barrier layer 14 on the side of the first barrier layer 13 away from the GaN buffer layer 12, the second barrier layer 14 is bent at the first through hole 131 and formed groove 145 . The second barrier layer 14 covers the bottom wall of the first through hole 131 and the sidewall of the first through hole 131 . In this embodiment, the second barrier layer 14 is formed on the side of the first barrier layer 13 away from the GaN buffer layer 12 by using a secondary epitaxial growth method.

More specifically, the second barrier layer 14 includes a first portion 141 and a second portion 143, the first portion 141 covers the side of the first barrier layer 13 away from the GaN buffer layer 12, and the second portion 143 is accommodated in the first through hole 131 inside. The second portion 143 is bent at the first through hole 131 and forms a groove 145 . The second portion 143 covers the bottom wall of the first through hole 131 and the sidewall of the first through hole 131 .

Step 305 , please refer to FIG. 6 , forming a barrier layer 15 on a side of the second barrier layer 14 away from the GaN buffer layer 12 . The barrier layer 15 includes a third portion 150 and a fourth portion 151 . The third portion 150 covers a side of the second barrier layer 14 away from the GaN buffer layer 12 . The groove walls of the groove 145 include a bottom wall 1451 and a side wall 1453 . The fourth portion 151 covers the sidewall 1453 and part of the bottom wall 1451 of the trench 145 . The fourth portion 151 includes a first connecting portion 1511 and a second connecting portion 1513 , the first connecting portion 1511 covers the sidewall 1453 of the groove 145 . The second connecting portion 1513 covers the bottom wall 1451 of the groove 145 , and the second through hole 152 is located on the second connecting portion 1513 . The first connecting portion 1511 and the second connecting portion 1513 enclose the receiving cavity 154 . The fourth portion 151 is bent in the groove 145 to form a receiving cavity 154 .

Step 307 , forming a second through hole 152 and a connection hole 157 on the barrier layer 15 , the second through hole 152 penetrates through the fourth portion 151 of the barrier layer 15 , and the connection hole 157 penetrates through the third portion 150 of the barrier layer 15 . In this embodiment, after the barrier layer 15 is etched, a second connection portion 1513 and a second through hole 152 penetrating through the fourth portion 151 are formed on the fourth portion 151 of the barrier layer 15, and a through barrier 152 is formed in the third portion 150. Connection hole 157 of layer 15.

Step 309, please refer to FIG. 2 , forming the first p-(Al)GaN part 17 in contact with the second barrier layer 14 in the second via hole 152, and forming a first p-(Al)GaN part 17 in contact with the second barrier layer 14 in the connection hole 157. The second p-(Al)GaN portion 25. In this embodiment, a p-(Al)GaN layer is formed on the side of the barrier layer 15 facing away from the second barrier layer 14 by a secondary epitaxy growth method, and the p-(Al)GaN layer is etched by dry etching After that, the first p-(Al)GaN portion 17 and the second p-(Al)GaN portion 25 are formed. The first p-(Al)GaN portion 17 is accommodated in the accommodation cavity 154 and the second through hole 152, and the end of the first p-(Al)GaN portion 17 away from the GaN buffer layer 12 is exposed outside the accommodation cavity 154, that is, the first p- The (Al)GaN portion 17 covers the bottom wall of the housing cavity 154 and the side walls of the housing cavity 154 . Since the barrier layer 15 is arranged on the second barrier layer 14, when the p-(Al)GaN layer is etched by dry etching, the barrier layer 15 effectively protects the second barrier layer 14 below the barrier layer 15, that is, the barrier layer 15 can be used as a stop layer during etching of the p-(Al)GaN layer, reducing the possibility that the surface of the second barrier layer 14 away from the GaN buffer layer 12 is damaged during the p-(Al)GaN etching process .

Step 311 , forming a third through hole 153 and a fourth through hole 155 on the barrier layer 15 . In this embodiment, after the barrier layer 15 is etched, a third through hole 153 and a fourth through hole 155 penetrating through the barrier layer 15 are formed on the barrier layer 15 .

Step 313, forming the gate 19 on the side of the first p-(Al)GaN portion 17 away from the second barrier layer 14, forming the source 21 in the third through hole 153, and forming the drain in the fourth through hole 155 electrode 23 , and a hole injection electrode 29 is formed on the side of the second p-(Al)GaN portion 21 away from the second barrier layer 14 .

Step 315 , connecting the hole injection electrode 29 to the drain 23 .

It can be understood that the sequence of some steps in the above preparation method is not limited, for example, step 311 and step 307 may be performed simultaneously.

The power device 10 and the preparation method thereof provided by the present application, since the barrier layer 15 is formed on the side of the second barrier layer 14 away from the GaN buffer layer 12, can effectively reduce the thickness of the second barrier layer 14 in the p-(Al)GaN etching process. The damage suffered during the etching process ensures that the second barrier layer 14 can maintain the original thickness, and prevents holes from being injected from the first p-(Al)GaN portion 17 into the second barrier layer when the power device 10 is reversed. In 14, the reliability of the power device 10 is effectively improved, and the manufacturing groove of the power device 10 can be improved, and the reliability of the power device 10 in soft switching and hard switching scenarios can be improved at the same time.

It should be understood that expressions such as "comprising" and "may include" that may be used in this application indicate the existence of disclosed functions, operations or constituent elements, and do not limit one or more additional functions, operation and components. In the present application, terms such as "comprising" and/or "having" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, parts or combinations thereof, but shall not be interpreted as referring to one or more other characteristics. , number, operation, constituent elements, parts, or the existence or possibility of addition of their combinations are excluded.

In addition, in this application, the expression "and/or" includes any and all combinations of the associated listed words. For example, the expression "A and/or B" may include A, may include B, or may include both A and B.

In the present application, expressions including ordinal numbers such as "first" and "second" may modify each element. However, such elements are not limited by the above expressions. For example, the above expressions do not limit the order and/or importance of elements. The above expressions are only used to distinguish one element from other elements. For example, the first user equipment and the second user equipment indicate different user equipments, although both the first user equipment and the second user equipment are user equipments. Similarly, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application.

When a component is referred to as being "connected" or "connected to" another component, it should be understood that the component is not only directly connected or connected to the other component, but there may also be another component between the component and the other component . On the other hand, when elements are referred to as being "directly connected" or "directly connected to" other elements, it should be understood that there are no elements in between.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A power device, characterized in that it comprises a GaN buffer layer, a first barrier layer, a second barrier layer, a barrier layer, a first p-(Al)GaN portion and a gate,

The GaN buffer layer and the first barrier layer are stacked, and the first barrier layer is provided with a first through hole penetrating through the first barrier layer;

The second barrier layer includes a first part and a second part, the first part covers the side of the first barrier layer away from the GaN buffer layer, and the second part covers the first via On the bottom wall of the hole and the side wall of the first through hole;

The second part is bent and forms a groove in the first through hole;

The barrier layer includes a third part and a fourth part, the third part covers the side of the second barrier layer away from the GaN buffer layer, and the fourth part covers the sidewall and the sidewall of the trench. a part of the bottom wall of the groove, the fourth part includes a second through hole passing through the fourth part;

at least a portion of the first p-(Al)GaN portion is received in the second via and contacts a second portion of the second barrier layer;

The gate is disposed on a side of the first p-(Al)GaN portion away from the barrier layer.
The power device according to claim 1, wherein the fourth portion of the barrier layer covers an end of the bottom wall of the trench that is close to the sidewall of the trench.
The power device according to claim 2, wherein the fourth part of the barrier layer includes a first connection part and a second connection part connected to each other, and the first connection part covers the trench The side wall of the groove, the second connecting part covers the bottom wall of the groove, the second through hole is located on the second connecting part, the first connecting part and the first connecting part The secondary connection part encloses a receiving cavity, the first p-(Al)GaN part fills the receiving cavity and the second through hole, and the first p-(Al)GaN part is far away from the GaN buffer layer One end is exposed outside the receiving cavity.
The power device according to claim 1, characterized in that,

The third part of the barrier layer includes a third through hole and a fourth through hole penetrating through the third part,

The power device also includes a source and a drain,

The source is disposed in the third via hole and contacts the first part of the second barrier layer,

The drain is disposed in the fourth through hole and is in contact with the first portion of the second barrier layer.
The power device according to claim 4, characterized in that,

The third part of the barrier layer is also provided with a connection hole passing through the third part,

The power device further includes a second p-(Al)GaN portion and a hole injection electrode,

at least a portion of the second p-(Al)GaN portion is accommodated in the contact hole and is in contact with the first portion of the second barrier layer,

The hole injection electrode is disposed on a side of the second p-(Al)GaN portion away from the second barrier layer, and the hole injection electrode is connected to the drain.
The power device according to any one of claims 1-5, wherein the first barrier layer is made of the same material as the second barrier layer, and the material of the first barrier layer is AlGaN and One of InAlN.
The power device according to any one of claims 1-6, wherein the barrier layer comprises one of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and silicon oxynitride.
An electronic device, characterized by comprising the power device and circuit board according to any one of claims 1-7.
A method for preparing a power device, characterized in that it comprises the following steps,

A prefabricated body is provided, the prefabricated body includes a GaN buffer layer and a first barrier layer arranged in stack, and the first barrier layer is provided with a first through hole penetrating the first barrier layer;

A second barrier layer is formed on the side of the first barrier layer away from the GaN buffer layer, the second barrier layer includes a first part and a second part, and the first part covers the first potential barrier layer. The side of the barrier layer away from the GaN buffer layer, the second part is accommodated in the first through hole and covers the first barrier layer, the second part is in the first through hole is bent and forms a groove, and the second part covers the bottom wall of the first through hole and the side wall of the first through hole;

A barrier layer is formed on the side of the second barrier layer away from the GaN buffer layer, the barrier layer includes a third part and a fourth part, and the third part covers the side of the second barrier layer away from the GaN buffer layer. One side of the GaN buffer layer, the fourth part covers the side walls of the trench and part of the bottom wall of the trench;

forming a second via hole through the barrier layer on the fourth portion of the barrier layer;

forming a first p-(Al)GaN portion in contact with a second portion of the second barrier layer within the second via;

A gate is formed on a side of the first p-(Al)GaN portion facing away from the barrier layer.
preparation method according to claim 9, is characterized in that,

The fourth part covers an end of the bottom wall of the groove close to the side wall of the groove, and the fourth part of the barrier layer includes a first connection part and a second connection part connected to each other. The first connection part covers the side wall of the groove, the second connection part covers the bottom wall of the groove, the second through hole is located on the second connection part, The first p-(Al)GaN portion fills the accommodating cavity and the second through hole, and the first p- An end of the (Al)GaN portion away from the GaN buffer layer is exposed outside the accommodation cavity.
The preparation method according to claim 9, further comprising: forming a third through hole and a fourth through hole penetrating through the barrier layer on the third part of the barrier layer,

The forming the gate on the side of the first p-(Al)GaN portion away from the second barrier layer further includes forming a first gate connected to the second barrier layer in the third via hole. A part of the source electrode is in contact with, and a drain electrode in contact with the first part of the second barrier layer is formed in the fourth via hole.
The preparation method according to claim 11, characterized in that, the preparation method further comprises,

The barrier layer is also provided with a connection hole penetrating through the third part of the barrier layer;

forming a second p-(Al)GaN portion in contact with the second barrier layer in the connection hole;

forming a hole injection electrode on a side of the second p-(Al)GaN portion away from the second barrier layer;

The hole injection electrode is connected to the drain.