WO2023005183A1 - 字线驱动器电路及存储器 - Google Patents

字线驱动器电路及存储器 Download PDF

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Publication number
WO2023005183A1
WO2023005183A1 PCT/CN2022/075238 CN2022075238W WO2023005183A1 WO 2023005183 A1 WO2023005183 A1 WO 2023005183A1 CN 2022075238 W CN2022075238 W CN 2022075238W WO 2023005183 A1 WO2023005183 A1 WO 2023005183A1
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WIPO (PCT)
Prior art keywords
word line
line driver
nmos
zeroth
transistors
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PCT/CN2022/075238
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English (en)
French (fr)
Inventor
杨桂芬
池性洙
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长鑫存储技术有限公司
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Priority to US17/813,147 priority Critical patent/US20230030836A1/en
Publication of WO2023005183A1 publication Critical patent/WO2023005183A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Definitions

  • Embodiments of the present application relate to but are not limited to a word line driver circuit and memory.
  • the word line driver is used to apply voltage to the word line in the memory cell array, and the word line can extend from the sub word line driver (SWD, Sub Wordline Driver) and pass through the entire column of memory cells.
  • the sub word line driver can selectively activate the corresponding word line in response to the row address corresponding to the word line received by the memory device, and each memory cell connected to the activated word line can output or input data.
  • the embodiment of the present application provides a new word line driver circuit and memory.
  • an embodiment of the present application provides a word line driver circuit, including: a plurality of word line drivers, each of the word line drivers includes a PMOS transistor and an NMOS transistor, and the plurality of word line drivers include a plurality of A PMOS transistor and a plurality of NMOS transistors, the plurality of PMOS transistors are arranged side by side, in the arrangement direction of the plurality of PMOS transistors, some of the plurality of NMOS transistors are located on one side of the PMOS transistor, and the other part of the plurality of NMOS transistors The NMOS transistors are located on the opposite side of the plurality of PMOS transistors.
  • the embodiment of the present application further provides a memory, including the above-mentioned word line driver circuit.
  • FIG. 1 is a schematic structural diagram of a memory provided in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a circuit structure of a word line driver circuit provided in an embodiment of the present application
  • 3 to 9 are schematic layout diagrams of the word line driver circuit provided by the embodiment of the present application.
  • Figure 1 is a schematic structural diagram of a memory provided by an embodiment of the present application
  • Figure 2 is a schematic structural diagram of a word line driver circuit provided by an embodiment of this application
  • Figures 3 to 9 are layouts of a word line driver circuit provided by an embodiment of this application Schematic.
  • the word line driver circuit includes: a plurality of word line drivers, each word line driver includes a PMOS transistor and a NMOS transistor, a plurality of word line drivers includes a plurality of PMOS transistors and a plurality of NMOS transistors, and a plurality of PMOS transistors are arranged side by side. In the arrangement direction of the PMOS transistors, part of the NMOS transistors is located on one side of the plurality of PMOS transistors, and another part of the NMOS transistors is located on the other side of the plurality of PMOS transistors.
  • word line drivers can be divided into odd word line drivers SWD_ODD and even word line drivers SWD_EVEN, and odd word line drivers SWD_ODD are used to connect odd bit word lines (such as WL1, WL3, WL5 and WL7 ), the even word line driver SWD_EVEN is used to connect even bit word lines (such as WL0, WL2, WL4 and WL6).
  • odd word line driver SWD_ODD and the even word line driver SWD_EVEN are usually arranged at intervals, and the odd bit word lines and the even bit word lines are usually arranged at intervals.
  • each word line driver circuit includes four word line drivers as an example for illustration. According to the figure, it can be seen that the types of different word line drivers in the same word line driver circuit are the same, that is, they are all odd numbers.
  • Line driver or even word line driver; each word line driver can include a PMOS transistor and two NMOS transistors, which are denoted as the zeroth PMOS transistor, the zeroth NMOS transistor and the first NMOS transistor, and the gate of the zeroth PMOS transistor and the first NMOS transistor The gate of the zeroth NMOS transistor is used to receive the first control signal MWLB (such as MWLB ⁇ n>), the source of the zeroth PMOS transistor is used to receive the second control signal FX (such as FX0, FX2, FX4, and FX6), and the zeroth PMOS transistor is used to receive the second control signal FX (such as FX0, FX2, FX4, and FX6).
  • MWLB such as MWLB ⁇ n>
  • FX such as FX0, F
  • the drain of the PMOS transistor, the drain of the zeroth NMOS transistor, and the drain of the first NMOS transistor are used to connect the corresponding word lines (such as WL0, WL2, WL4, and WL6), and the source of the zeroth NMOS transistor is connected to the first NMOS transistor.
  • the source of the transistor is grounded, and the gate of the first NMOS transistor is used to receive the second complementary control signal FXB (for example, FXB0 , FXB2 , FXB4 and FXB6 ).
  • the word line driver only includes one PMOS transistor and one NMOS transistor.
  • the time when the second control signal FX transitions to a high level is the same as the time when the second control complementary signal FXB transitions to a low level, and the time when the first control signal MWLB transitions to a low level, and the second control complementary signal MWLB transitions to a low level.
  • the time when the signal FXB transitions to a high level is later than the time when the second control signal FX transitions to a low level, and the time when the first control signal MWLB transitions to a high level is later than the time when the second control complementary signal FXB transitions to a high level.
  • the word line driver circuit includes a first word line driver SWD1, a second word line driver SWD2, a third word line driver SWD3, and a fourth word line driver SWD4, and the first word line driver SWD1 includes a PMOS transistor P10 and an NMOS transistor N10 and N11, the second word line driver SWD2 includes PMOS transistor P20 and NMOS transistors N20 and N21, the third word line driver SWD3 includes PMOS transistor P30 and NMOS transistors N30 and N31, and the fourth word line driver SWD4 includes PMOS transistor P40 and NMOS transistors Tubes N40 and N41, wherein P10, P20, P30 and P40 belong to the zeroth PMOS tube, N10, N20, N30 and N40 belong to the zeroth NMOS tube, and N11, N21, N31 and N41 belong to the first NMOS tube.
  • each PMOS transistor is composed of at least two sub-PMOS transistors; in other embodiments, each NMOS transistor is composed of at least two sub-NMOS transistors; in yet another embodiment, each PMOS transistor is composed of at least two sub-PMOS transistors; Two sub-PMOS transistors are formed, and each NMOS transistor is composed of at least two sub-NMOS transistors.
  • the zeroth PMOS transistor is composed of the zeroth first PMOS transistor and the zeroth second PMOS transistor
  • the zeroth NMOS transistor is composed of the zeroth first NMOS transistor and the zeroth second NMOS transistor
  • the first NMOS transistor is composed of the first one NMOS transistor and the first and second NMOS tubes.
  • the zero-first PMOS transistor and the zero-second PMOS transistor are NMOS transistors with identical physical characteristics, and the only difference lies in their own positions and connection relationships with other components.
  • the first and first NMOS transistors and the first and second NMOS transistors, as well as the zero and first NMOS transistors and the zero and second NMOS transistors are NMOS transistors with identical physical characteristics, and the only difference lies in their own positions and connections with other components. It is set that two sub-MOS transistors jointly form a PMOS transistor or an NMOS transistor, which is beneficial to adjust the layout of the layout.
  • each transistor or sub-transistor is not marked in FIGS. 3 to 9 .
  • the transistor at position indicates which transistor or which sub-transistor it is.
  • P10 in the first word line driver, P20 in the second word line driver, P30 in the third word line driver, and P40 in the fourth word line driver are along the first direction D1 Arranged side by side, in the first direction D1, N10 and N11 in the first word line driver and N20 and N21 in the second word line driver are located on one side of the above-mentioned multiple PMOS transistors, N30 and N21 in the third word line driver N31 and N40 and N41 in the fourth word line driver are located on the opposite side of the plurality of PMOS transistors.
  • the distance between the PMOS transistor and the NMOS transistor in the word line driver is a predetermined distance, and the predetermined distance between different word line drivers is the same.
  • the distances between the zeroth PMOS transistor, the zeroth NMOS transistor, and the first NMOS transistor in the word line driver are equal, specifically, the distances between P10, N10, and N11 are equal.
  • the spacing between P20 and N20 and N21 is equal, the spacing between P30 and N30 and N31 is equal, the spacing between P40 and N40 and N41 is equal; further, the first spacing between P10 and N10 is the same as that between P20 and N20
  • the second distance between P30 and N30, the third distance between P30 and N30, and the fourth distance between P40 and N40 are equal. Setting different preset intervals to be equal helps to make different word line drivers have the same or similar performance, so that different word line drivers apply voltages to corresponding word lines at similar times, ensuring the stability of the internal timing of the memory.
  • the two sub-PMOS transistors share the same source.
  • the PMOS transistor P10 in the first word line driver is composed of two sub-PMOS transistors P101 and P102, and P101 and P102 share the same active area for receiving the first control signal FX, specifically FX0 .
  • the arrangement direction of the plurality of PMOS transistors (that is, the first direction D1) is perpendicular to the channel length direction of the PMOS transistors, wherein the arrangement direction of the two sub-PMOS transistors is parallel to and perpendicular to the channel length direction of the PMOS transistors. in the first direction D1.
  • the arrangement direction of P101 and P102 is parallel to the channel length direction and perpendicular to the first direction D1.
  • each PMOS transistor includes a first sub-PMOS transistor and a second sub-PMOS transistor, the first sub-PMOS transistors corresponding to different PMOS transistors share the same gate, and the second sub-PMOS transistors corresponding to different PMOS transistors share the same gate. grid.
  • the PMOS transistor P20 includes P201 and P202
  • the PMOS transistor P30 includes P301 and P302
  • the PMOS transistor P40 includes P401 and P402.
  • P101, P201, P301, and P401 are arranged side by side along the first direction D1 and share the same gate.
  • P102 , P202 , P302 and P402 are arranged side by side along the first direction D1 and share another gate.
  • the first and first NMOS transistors and the first and second NMOS transistors are located between the zeroth and first NMOS transistors and the zeroth and second NMOS transistors.
  • the internal arrangements of the NMOS transistors of different word line drivers are the same.
  • the zeroth NMOS transistor N10 in the first word line driver includes the zeroth and first NMOS transistor N101 and the zeroth and second NMOS transistor.
  • the transistor N102 and the first NMOS transistor N11 include a first-NMOS transistor N111 and a first-two NMOS transistor N112, and N111 and N112 are located between N101 and N102.
  • the arrangement direction of the first and first NMOS transistors and the first and second NMOS transistors is parallel to the arrangement direction of the zeroth and first NMOS transistors and the zeroth and second NMOS transistors.
  • the arrangement direction of N111 and N112 is parallel to the arrangement direction of N101 and N102 .
  • the channel length directions of different transistors and their sub-transistors are the same, so that it is beneficial to realize that there is a unique preset distance between the PMOS transistor and the NMOS transistor in the same word line driver, so that it is beneficial to make the word line
  • the drive has a more stable and balanced performance.
  • the distance between P101 and N101 is equal to the distance between P102 and N102; wherein, in the first direction D1, the level of the gate of P101 The position is at least partly coincident with the horizontal position of the gate of N101, the distance between P101 and N101 is the distance between the gate of P101 and the gate of N101, and the same is true between P102 and N102, which will not be repeated here.
  • the distance between P101 and N111 is equal to the distance between P102 and N112; wherein, in the first direction D1, the horizontal position of the gate of P101 is the same as the horizontal position of the gate of N111 At least partially overlapped, the distance between P101 and N111 is the distance between the gate of P101 and the gate of N111 , and the same is true between P102 and N112 , which will not be repeated here.
  • the zeroth and first NMOS transistors share the same drain with the first and first NMOS transistors
  • the first and first NMOS transistors share the same source with the first and second NMOS transistors
  • the first and second NMOS transistors share the same source with the zeroth and second NMOS transistors.
  • different transistors share the same source or drain, which is beneficial to reducing the overall size of the word line driver, thereby realizing the miniaturization and miniaturization of the word line driver circuit and memory.
  • N101 and N111 share the same active area, which is connected to the zeroth word line WL0 through a contact hole
  • N111 and N112 share the same active area, and the active area is grounded or connected to low Level signals
  • N112 and N102 share the same active area, and the active area is also connected to the zeroth word line WL0 through a contact hole.
  • the first and first NMOS transistors and the first and second NMOS transistors share the same gate, and the sharing of the same gate by different transistors is beneficial to reduce the difficulty of gate fabrication and ensure the conductivity of the gate.
  • the complexity of patterned openings avoids etching defects due to complex patterns and ensures that gates can be effectively formed.
  • N111 and N112 share the same gate, or in other words, the gate of N111 and the gate of N112 are different parts of the same conductive layer, which are used to connect the gate of N111 and the gate of N112
  • Another part of the conductive layer is located on the isolation structure.
  • the isolation structure is used to isolate adjacent active regions, and the word lines can be made of doped polysilicon or metal materials, such as tungsten and molybdenum.
  • the zeroth first NMOS transistor and the zeroth second NMOS transistor are located between the first one NMOS transistor and the first two NMOS transistors; wherein, the zeroth first NMOS transistor and the zeroth second NMOS transistor can share the same gate .
  • the internal arrangements of NMOS transistors of different word line drivers are the same. Taking the first word line driver as an example, N101 and N102 are located between N111 and N112, and N101 and N102 share the same gate.
  • the arrangement direction of the zeroth and first NMOS transistors and the zeroth and second NMOS transistors in the middle position is parallel to the arrangement direction of the first and first NMOS transistors and the first and second NMOS transistors on both sides, corresponding to the 4.
  • the arrangement direction of N101 and N102 is parallel to the arrangement direction of N111 and N112.
  • the first and first NMOS transistors share the same drain with the zeroth and first NMOS transistors
  • the zeroth and first NMOS transistors share the same source with the zeroth and second NMOS transistors
  • the zeroth and second NMOS transistors share the same drain with the first and second NMOS transistors .
  • N111 and N101 share the same active area, which is connected to the zeroth word line WL0 through a contact hole
  • N101 and N102 share the same active area, which is grounded or connected to a low-level signal
  • N102 and N112 share the same active area, which is also connected to the zeroth word line WL0 through a contact hole.
  • the word line driver includes a first word line driver and a second word line driver, and the NMOS transistor N10 in the first word line driver shares the same source with the NMOS transistor N20 in the second word line driver. pole and the same grid.
  • N20 is composed of N201 and N202
  • N10 is composed of N101 and N102
  • N201, N202, N101 and N102 share the same continuous active region and the same continuous conductive layer.
  • the gates of different transistors are different parts of the same conductive layer, and other parts of the conductive layer connected to the gates of different transistors are located on the isolation structure, and the isolation structure is used to isolate adjacent active regions; in addition, the shared continuous conductive layer
  • the layers can take on various shapes depending on the arrangement of the transistors, and in some embodiments, the shared continuous conductive layer takes on the shape of a ring.
  • the first NMOS transistor included in the first word line driver shares a source with the first NMOS transistor included in the second word line driver.
  • the first NMOS transistor in the first word line driver is composed of N111 and N112
  • the first NMOS transistor in the second word line driver is composed of N111 and N112
  • N111 and N211 share the same source
  • N112 and N212 share the same source pole.
  • the NMOS transistors of the first word line driver and the second word line driver are arranged on the same side of the PMOS transistor as an example, and the description is based on this example.
  • the connection relationship between the NMOS transistors of the adjacent word line drivers located on the same side of the PMOS transistor in the word line driver circuit It can be understood that, in the embodiment shown in FIG.
  • connection relationship can also be applied to the NMOS transistor of the third word line driver and the NMOS transistor of the fourth word line driver; similarly, in other embodiments, if the first The NMOS transistor of the word line driver and the NMOS transistor of the third word line driver are located on one side of the PMOS transistor, so the expression of the above connection relationship is also applicable to the NMOS transistor of the first word line driver and the NMOS transistor of the third word line driver.
  • the first word line driver and the second word line driver are still taken as examples for description, and the applicable conditions thereof will not be repeated.
  • the arrangement direction of the first and first NMOS transistors and the first and second NMOS transistors is parallel to the arrangement direction of the zeroth and first NMOS transistors and the zeroth and second NMOS transistors; wherein, the zeroth and first NMOS transistors and the zeroth and second NMOS transistors share the same gate, and/or the first and first NMOS transistors and the first and second NMOS transistors share the same gate.
  • the word line driver includes a first word line driver and a second word line driver, and the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver
  • the transistor is located between the zeroth NMOS transistor included in the first word line driver and the zeroth NMOS transistor included in the second word line driver, that is, N11 and N21 are located between N10 and N20.
  • the word line driver includes a first word line driver and a second word line driver, the zeroth NMOS transistor included in the first word line driver and the zeroth NMOS transistor included in the second word line driver It is located between the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver, that is, N10 and N20 are located between N11 and N21; in addition, N10 and N20 share the same gate.
  • the channel length direction of the NMOS transistor in the word line driver is parallel to the channel length direction of the PMOS transistor, or in other words, the channel length direction of the PMOS transistor is parallel to the channel length direction of the NMOS transistor.
  • the length directions are the same; in some other embodiments, referring to FIG. 7 to FIG. 9 , the channel length direction of the NMOS transistor in the word line driver is perpendicular to the channel length direction of the PMOS transistor.
  • the difference between the embodiment shown in FIG. 7 and the embodiment shown in FIG. 3 lies in the overall adjustment of the channel length direction of the NMOS transistor in the word line driver circuit.
  • the embodiment shown in FIG. 8 and the embodiment shown in FIG. 6 and The main distinguishing feature of the embodiment shown in Figure 9 and Figure 5 also lies in this.
  • the channel length direction of the NMOS transistor is set to be perpendicular to the channel length direction of the PMOS transistor, which is beneficial to avoid
  • the second direction D2 perpendicular to the first direction D1 more NMOS transistors are arranged side by side, and a larger space is reserved for the extension of the drain of the NMOS transistor, so that the drain of the NMOS transistor has a larger width, which is conducive to making the drain of the NMOS transistor larger.
  • the word line extending from the drain of the PMOS transistor can be directly connected to the drain of the corresponding NMOS transistor without bending, that is, the word line is straight, reducing the resistance of the word line and the RC delay caused by the resistance, ensuring the word line driver
  • the circuit has good electrical performance.
  • a plurality of PMOS transistors are arranged side by side, and in the arrangement direction of the plurality of PMOS transistors, a plurality of NMOS transistors are located on opposite sides of the plurality of PMOS transistors.
  • the PMOS transistor and the NMOS transistor are arranged side by side, so that the PMOS transistor and the NMOS transistor have a larger space in the vertical direction, which is conducive to extending the channel length or gate width of the PMOS transistor and the NMOS transistor, and improving the electrical performance of the word line driver circuit ;
  • controlling the NMOS transistors to be located on opposite sides of the PMOS transistors is conducive to making the distance between the PMOS transistors and NMOS transistors corresponding to different word line drivers shorter, thereby shortening the wiring length, reducing wire resistance and reducing signal delay;
  • Arranging the NMOS transistors on opposite sides of the PMOS transistors is beneficial to improve the symmetry of the word line driver circuit, thereby improving the electrical performance of the word line driver circuit.
  • An embodiment of the present application further provides a memory, including the word line driver circuit described in any one of the foregoing.
  • the word line driver circuit with the above structure can have good electrical properties because of its transistors and word lines, so the word line driver circuit can have good characteristics, thereby improving the overall performance of the memory .

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Abstract

本申请实施例涉及半导体领域，提供一种字线驱动器电路及存储器，字线驱动器电路至少可以包括：多个字线驱动器，每一所述字线驱动器包含PMOS管和NMOS管，多个所述字线驱动器包含多个PMOS管和多个NMOS管，所述多个PMOS管并排设置，在所述多个PMOS管的排列方向上，部分所述NMOS管位于所述多个PMOS管的一侧，另一部分所述NMOS管位于所述多个PMOS管的相对的另一侧。

Description

字线驱动器电路及存储器
相关申请的交叉引用
本申请基于申请号为202110864945.8、申请日为2021年07月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种字线驱动器电路及存储器。
背景技术
存储器中的各种电路需要使用各种信号，用于将信号施加于信号线的信号驱动器被普遍应用。字线驱动器用于向存储单元阵列中的字线施加电压，字线可以从子字线驱动器(SWD，Sub Wordline Driver)开始延伸并穿过存储单元整列。子字线驱动器可以响应于存储设备接收到的对应于字线的行地址而选择性地激活对应的字线，与被激活字线连接的每个存储单元可以将数据输出或输入。
发明内容
本申请实施例提供一种新的字线驱动器电路及存储器。
根据本申请一些实施例，本申请实施例提供一种字线驱动器电路，包括：多个字线驱动器，每一所述字线驱动器包含PMOS管和NMOS管，多个所述字线驱动器包含多个PMOS管和多个NMOS管，所述多个PMOS管并排设置，在所述多个PMOS管的排列方向上，部分所述多个NMOS管位于所述PMOS管的一侧，另一部分所述NMOS管位于所述多个PMOS 管的相对的另一侧。
根据本申请一些实施例，本申请实施例还提供一种存储器，包含上述字线驱动器电路。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1为本申请实施例提供的存储器的结构示意图；
图2为本申请实施例提供的字线驱动器电路的电路结构示意图；
图3至图9为本申请实施例提供的字线驱动器电路的版图结构示意图。
具体实施方式
下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请实施例提供的存储器的结构示意图；图2为本申请实施例提供的字线驱动器电路的电路结构示意图；图3至图9为本申请实施例提供的字线驱动器电路的版图结构示意图。
字线驱动器电路包括：多个字线驱动器，每一字线驱动器包含PMOS管和NMOS管，多个字线驱动器包括多个PMOS管和多个NMOS管，多个PMOS管并排设置，在多个PMOS管的排列方向上，部分NMOS管位于多个PMOS管的一侧，另一部分NMOS管位于多个PMOS管的另一侧。
以下将结合附图对本申请实施例进行更为详细的说明。
参考图1，根据连接的字线不同，字线驱动器可分为奇数字线驱动器 SWD_ODD和偶数字线驱动器SWD_EVEN，奇数字线驱动器SWD_ODD用于连接奇数位字线(例如WL1、WL3、WL5以及WL7)，偶数字线驱动器SWD_EVEN用于连接偶数位字线(例如WL0、WL2、WL4以及WL6)。在存储设备中，奇数字线驱动器SWD_ODD和偶数字线驱动器SWD_EVEN通常间隔设置，奇数位字线与偶数位字线通常间隔排列。
参考图1和图2，以每一字线驱动器电路包含四个字线驱动器作为示例进行说明，根据图示可知，同一字线驱动器电路中的不同字线驱动器的类型相同，即均为奇数字线驱动器或偶数字线驱动器；每一字线驱动器可包含一个PMOS管和两个NMOS管，记为第零PMOS管、第零NMOS管和第一NMOS管，第零PMOS管的栅极和第零NMOS管的栅极用于接收第一控制信号MWLB(例如MWLB<n>)，第零PMOS管的源极用于接收第二控制信号FX(例如FX0、FX2、FX4以及FX6)，第零PMOS管的漏极、第零NMOS管的漏极以及第一NMOS管的漏极用于连接对应的字线(例如WL0、WL2、WL4以及WL6)，第零NMOS管的源极和第一NMOS管的源极接地，第一NMOS管的栅极用于接收第二控制互补信号FXB(例如FXB0、FXB2、FXB4以及FXB6)。在一些实施例，字线驱动器仅包含一个PMOS管和一个NMOS管。
其中，第二控制信号FX向高电平跳变的时刻与第二控制互补信号FXB向低电平跳变的时刻、第一控制信号MWLB向低电平跳变的时刻相同，第二控制互补信号FXB向高电平跳变的时刻晚于第二控制信号FX向低电平跳变的时刻，第一控制信号MWLB向高电平跳变的时刻晚于第二控制互补信号FXB向高电平跳变的时刻。
示例性地，字线驱动器电路包括第一字线驱动器SWD1、第二字线驱动器SWD2、第三字线驱动器SWD3以及第四字线驱动器SWD4，第一字线驱动器SWD1包括PMOS管P10与NMOS管N10和N11，第二字线驱 动器SWD2包括PMOS管P20与NMOS管N20和N21，第三字线驱动器SWD3包括PMOS管P30与NMOS管N30和N31，第四字线驱动器SWD4包括PMOS管P40与NMOS管N40和N41，其中，P10、P20、P30以及P40属于第零PMOS管，N10、N20、N30以及N40属于第零NMOS管，N11、N21、N31以及N41属于第一NMOS管。
在一些实施例中，每一PMOS管由至少两个子PMOS管构成；在另一些实施例中，每一NMOS管由至少两个子NMOS管构成；在又一实施例中，每一PMOS管由至少两个子PMOS管构成，且每一NMOS管由至少两个子NMOS管构成。示例性地，第零PMOS管由第零一PMOS管和第零二PMOS管构成，第零NMOS管由第零一NMOS管和第零二NMOS管构成，第一NMOS管由第一一NMOS管和第一二NMOS管构成。需要说明的是，本申请实施例中，第零一PMOS管和第零二PMOS管为物理特性完全相同的NMOS管，区别仅在于自身的位置不同以及与其他部件的连接关系不同，同理地，第一一NMOS管和第一二NMOS管以及第零一NMOS管和第零二NMOS管为物理特性完全相同的NMOS管，区别仅在于自身的位置不同以及与其他部件的连接关系不同。设置由两个子MOS管共同构成PMOS管或NMOS管，有利于调节版图的布局。
为了图示的简洁，图3至图9中并未标示每一晶体管或子晶体管，本领域技术人员可以根据图2中不同晶体管的栅源漏所接收的信号，确定图3至图9中不同位置的晶体管表征的是哪一晶体管或哪一子晶体管。
在一些实施例中，参考图3，第一字线驱动器中的P10、第二字线驱动器中的P20、第三字线驱动器中的P30以及第四字线驱动器中的P40沿第一方向D1并排设置，在第一方向D1上，第一字线驱动器中的N10和N11与第二字线驱动器中的N20和N21位于上述多个PMOS管的一侧，第三字线驱动器中的N30和N31与第四字线驱动器中的N40和N41位于上述多个 PMOS管的相对的另一侧。
在一些实施例中，记字线驱动器中PMOS管与NMOS管之间的间距为预设间距，不同字线驱动器之间的预设间距相同。其中，参考图3，在第一方向D1上，字线驱动器中第零PMOS管与第零NMOS管和第一NMOS管之间的间距相等，具体地，P10与N10和N11之间的间距相等，P20与N20和N21之间的间距相等，P30与N30和N31之间的间距相等，P40与N40和N41之间的间距相等；进一步地，P10与N10之间的第一间距与P20与N20之间的第二间距、P30与N30之间的第三间距以及P40与N40之间的第四间距相等。设置不同的预设间距相等，有利于使得不同字线驱动器具有相同或相近的性能，从而使得不同字线驱动器向对应的字线施加电压的时刻相近，保证存储器内部时序的稳定性。
在一些实施例中，两个子PMOS管共用同一源极。以第一字线驱动器为例，第一字线驱动器中的PMOS管P10由P101和P102两个子PMOS管构成，P101和P102共用同一有源区，用于接收第一控制信号FX，具体为FX0。
在一些实施例中，多个PMOS管的排列方向(即第一方向D1)垂直于PMOS管的沟道长度方向，其中，两个子PMOS管的排列方向平行于PMOS管的沟道长度方向且垂直于第一方向D1。继续以第一实施例作为示例，P101和P102的排列方向平行于沟道长度方向且垂直于第一方向D1。
在一些实施例中，每一PMOS管包括第一子PMOS管和第二子PMOS管，不同PMOS管对应的第一子PMOS管共用同一栅极，不同PMOS管对应的第二子PMOS管共用同一栅极。如图3所示，PMOS管P20包括P201和P202，PMOS管P30包括P301和P302，PMOS管P40包括P401和P402，P101、P201、P301以及P401沿第一方向D1并排设置且共用同一栅极，P102、P202、P302以及P402沿第一方向D1并排设置且共用另一栅极。
在一些实施例中，第一一NMOS管和第一二NMOS管位于第零一NMOS管和第零二NMOS管之间。参考图3，不同字线驱动器的NMOS管的内部排列方式相同，以第一字线驱动器为例，第一字线驱动器中的第零NMOS管N10包括第零一NMOS管N101和第零二NMOS管N102，第一NMOS管N11包括第一一NMOS管N111和第一二NMOS管N112，N111和N112位于N101和N102之间。
在一些实施例中，第一一NMOS管和第一二NMOS管的排列方向平行于第零一NMOS管和第零二NMOS管的排列方向。同样地，以第一字线驱动器为例，N111与N112的排列方向平行于N101与N102的排列方向。
在一些实施例中，不同晶体管及其子晶体管的沟道长度方向相同，如此，有利于实现同一字线驱动器中PMOS管与NMOS管之间具有唯一的预设间距，如此，有利于使得字线驱动器具有更为稳定和均衡的性能。具体地，以第一字线驱动器为例，在第一方向D1上，P101与N101之间的距离等于P102和N102之间的距离；其中，在第一方向D1上，P101的栅极的水平位置与N101的栅极的水平位置至少部分重合，P101与N101之间的距离为P101的栅极与N101的栅极之间的距离，P102与N102之间同理，在此不再进行赘述。
相应地，在第一方向D1上，P101与N111之间的距离等于P102与N112之间的距离；其中，在第一方向D1上，P101的栅极的水平位置与N111的栅极的水平位置至少部分重合，P101与N111之间的距离为P101的栅极与N111的栅极之间的距离，P102与N112之间同理，在此不再进行赘述。
在一些实施例中，第零一NMOS管与第一一NMOS管共用同一漏极，第一一NMOS管与第一二NMOS管共用同一源极，第一二NMOS管与第零二NMOS管共用同一漏极，不同晶体管共用同一源极或漏极，有利于减小字线驱动器的整体尺寸，进而实现字线驱动器电路以及存储器的小型化 和微型化。以第一字线驱动器为例，N101和N111共用同一有源区，该有源区通过接触孔与第零字线WL0连接，N111和N112共用同一有源区，该有源区接地或连接低电平信号，N112和N102共用同一有源区，该有源区同样通过接触孔与第零字线WL0连接。
其中，第一一NMOS管和第一二NMOS管共用同一栅极，不同晶体管共用同一栅极有利于降低栅极的制作难度和保证栅极的导电性能，具体来说，有利于降低掩膜的图案化开口的复杂度，避免因图案较为复杂而出现刻蚀缺陷，保证栅极能够有效形成。以第一字线实施例为例，N111和N112共用同一栅极，或者说，N111的栅极和N112的栅极为同一导电层的不同部分，用于连通N111的栅极和N112的栅极的另一部分导电层位于隔离结构上。隔离结构用于隔离相邻有源区，字线可以采用掺杂多晶硅或金属材料制成，例如钨和钼。
在一些实施例中，第零一NMOS管和第零二NMOS管位于第一一NMOS管和第一二NMOS管之间；其中，第零一NMOS管和第零二NMOS管可共用同一栅极。参考图4，不同字线驱动器的NMOS管的内部排列方式相同，以第一字线驱动器为例，N101和N102位于N111和N112之间，N101和N102共用同一栅极。
与上一实施例类似的是，位于中间位置的第零一NMOS管和第零二NMOS管的排列方向平行于位于两侧的第一一NMOS管和第一二NMOS管的排列方向，对应图4，N101与N102的排列方向平行于N111与N112的排列方向。
相应地，第一一NMOS管与第零一NMOS管共用同一漏极，第零一NMOS管与第零二NMOS管共用同一源极，第零二NMOS管与第一二NMOS管共用同一漏极。对应图4，N111和N101和共用同一有源区，该有源区通过接触孔与第零字线WL0连接，N101和N102共用同一有源区， 该有源区接地或连接低电平信号，N102和N112共用同一有源区，该有源区同样通过接触孔与第零字线WL0连接。
在一些实施例中，参考图4，字线驱动器包括第一字线驱动器和第二字线驱动器，第一字线驱动器中的NMOS管N10与第二字线驱动器中的NMOS管N20共用同一源极和同一栅极。其中，N20由N201和N202构成，N10由N101和N102构成，N201、N202、N101以及N102共用同一连续的有源区和同一连续的导电层。可以理解的是，不同晶体管的栅极为同一导电层的不同部分，连接不同晶体管的栅极的其他部分导电层位于隔离结构上，隔离结构用于隔离相邻有源区；此外，共用的连续导电层可以根据晶体管的排布呈现出各种形状，在一些实施例中，共用的连续导电层呈现环状。
相应地，第一字线驱动器包含的第一NMOS管与第二字线驱动器包括的第一NMOS管共用源极。其中，第一字线驱动器中的第一NMOS管由N111和N112构成，第二字线驱动器中的第一NMOS管由N111和N112构成，N111和N211共用同一源极，N112和N212共用同一源极。
可以理解的是，不同字线驱动器之间存在多种组合，本申请实施例以第一字线驱动器和第二字线驱动器的NMOS管设置在PMOS管的同一侧作为示例，并基于该示例说明字线驱动器电路中位于PMOS管同一侧的相邻字线驱动器的NMOS管的连接关系。可以理解的是，在图4所示实施例中，第三字线驱动器的NMOS管和第四字线驱动器的NMOS管可同样适用上述连接关系；同理，在其他实施例中，若第一字线驱动的NMOS管和第三字线驱动器的NMOS管位于PMOS管的一侧，则上述连接关系的表述还适用于第一字线驱动器的NMOS管和第三字线驱动器的NMOS管。后续仍以第一字线驱动器和第二字线驱动器作为示例进行说明，关于其适用情况不再进行赘述。
在一些实施例中，第一一NMOS管和第一二NMOS管的排列方向平行于第零一NMOS管和第零二NMOS管的排列方向；其中，第零一NMOS管和第零二NMOS管共用同一栅极，和/或第一一NMOS管和第一二NMOS管共用同一栅极。
其中，在一些实施例中，参考图5，字线驱动器包括第一字线驱动器和第二字线驱动器，第一字线驱动器包含的第一NMOS管和第二字线驱动器包含的第一NMOS管位于第一字线驱动器包含的第零NMOS管和第二字线驱动器包含的第零NMOS管之间，即N11和N21位于N10和N20之间。
在另一些实施例中，参考图6，字线驱动器包括第一字线驱动器和第二字线驱动器，第一字线驱动器包含的第零NMOS管和第二字线驱动器包含的第零NMOS管位于第一字线驱动器包含的第一NMOS管和第二字线驱动器包含的第一NMOS管之间，即N10和N20位于N11和N21之间；此外，N10和N20共用同一栅极。
在一些实施例中，参考图3至图6，字线驱动器中NMOS管的沟道长度方向平行于PMOS管的沟道长度方向，或者说，PMOS管的沟道长度方向与NMOS管的沟道长度方向相同；在另一些实施例中，参考图7至图9，字线驱动器中NMOS管的沟道长度方向垂直于PMOS管的沟道长度方向。其中，图7所示实施例与图3所示实施例的区别在于整体调整字线驱动器电路中NMOS管的沟道长度方向，相应地，图8所示实施例与图6所示实施例以及图9和图5所示实施例的主要区别特征也在于此。
由于与字线驱动器连接的字线的延伸方向一般平行于字线驱动器中PMOS管的栅极的延伸方向，设置NMOS管的沟道长度方向垂直于PMOS管的沟道长度方向，有利于避免在垂直于第一方向D1的第二方向D2上并排较多的NMOS管，为NMOS管的漏极的延伸预留更大的空间，使得NMOS管的漏极具有较大的宽度，进而有利于使得从PMOS管的漏极延伸出来的 字线无需弯折即可直接与对应的NMOS管的漏极连接，即使得字线呈现直线，降低字线的电阻和电阻导致的RC延迟，保证字线驱动器电路具有良好的电学性能。
本实施例中，多个PMOS管并排设置，且在多个PMOS管的排列方向上，多个NMOS管位于多个PMOS管的相对两侧，如此，有利于避免在垂直上述排列方向的方向上PMOS管和NMOS管并排设置，使得在垂直方向上PMOS管和NMOS管具有更大的空间，从而有利于延长PMOS管和NMOS管的沟道长度或栅极宽度，提升字线驱动器电路的电学性能；同时，控制NMOS管位于PMOS管的相对两侧，有利于使得不同字线驱动器对应的PMOS管与NMOS管之间的间距较短，从而缩短布线长度、降低导线电阻以及降低信号延迟；此外，将NMOS管设置于PMOS管的相对两侧，有利于提升字线驱动器电路的对称性，从而字线驱动器电路的电学性能。
本申请实施例还提供一种存储器，包括上述任一项所述的字线驱动器电路。在集成电路的尺寸日益微缩的情况下，采用上述结构的字线驱动器电路，由于其晶体管和字线可具有良好的电学性能，因此字线驱动器电路可具有良好的特性，从而提升存储器的整体性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (18)

  1. 一种字线驱动器电路，包括：
    多个字线驱动器，每一所述字线驱动器包含PMOS管和NMOS管，多个所述字线驱动器包含多个PMOS管和多个NMOS管，所述多个PMOS管并排设置，在所述多个PMOS管的排列方向上，部分所述NMOS管位于所述多个PMOS管的一侧，另一部分所述NMOS管位于所述多个PMOS管的相对的另一侧。
  2. 根据权利要求1所述的字线驱动器电路，其中，记所述字线驱动器中所述PMOS管与所述NMOS管之间的间距为预设间距，不同所述字线驱动器的所述预设间距相同。
  3. 根据权利要求1所述的字线驱动器电路，其中，每一所述PMOS管由至少两个子PMOS管构成。
  4. 根据权利要求1所述的字线驱动器电路，其中，每一所述NMOS管由至少两个子NMOS管构成。
  5. 根据权利要求1或4所述的字线驱动器电路，其中，所述字线驱动器包括第零PMOS管、第零NMOS管和第一NMOS管，所述第零PMOS管的栅极接收第一控制信号，源极接收第二控制信号，漏极连接字线，所述第零NMOS管的栅极接收所述第一控制信号，源极接地，漏极连接所述字线，所述第一NMOS管的栅极接收第二控制互补信号，源极接地，漏极连接所述字线，所述第零NMOS管由第零一NMOS管和第零二NMOS管构成，所述第一NMOS管由第一一NMOS管和第一二NMOS管构成。
  6. 根据权利要求5所述的字线驱动器电路，其中，所述第一一NMOS管和所述第一二NMOS管位于所述第零一NMOS管和所述第零二NMOS管之间。
  7. 根据权利要求6所述的字线驱动器电路，其中，所述第一一NMOS管和所述第一二NMOS管的排列方向平行于所述第零一NMOS管和所述第零二NMOS管的排列方向。
  8. 根据权利要求6所述的字线驱动器电路，其中，所述第零一NMOS管与所述第一一NMOS管共用同一漏极，所述第一一NMOS管与所述第一二NMOS管共用同一源极，所述第一二NMOS管与所述零二NMOS管共用同一漏极。
  9. 根据权利要求8所述的字线驱动器电路，其中，所述第一一NMOS管和所述第一二NMOS管共用同一栅极。
  10. 根据权利要求5所述的字线驱动器电路，其中，所述第零一NMOS管和所述第零二NMOS管位于所述第一一NMOS管和所述第一二NMOS管之间。
  11. 根据权利要求10所述的字线驱动器电路，其中，所述第零一NMOS管和所述第零二NMOS管共用同一栅极。
  12. 根据权利要求10所述的字线驱动器电路，其中，所述字线驱动器包括第一字线驱动器和第二字线驱动器，所述第一字线驱动器包含的所述第零NMOS管与所述第二字线驱动器包含的所述第零NMOS管共用同一源极和同一栅极，所述第一字线驱动器包含的所述第一NMOS管与所述第二字线驱动器包含的所述第一NMOS管共用源极。
  13. 根据权利要求5所述的字线驱动器电路，其中，所述第一一NMOS管和所述第一二NMOS管的排列方向平行于所述第零一NMOS管和所述第零二NMOS管的排列方向。
  14. 根据权利要求13所述的字线驱动器电路，其中，所述第零一NMOS管和所述第零二NMOS管共用同一栅极，所述第一一NMOS管和所述第一二NMOS管共用同一栅极。
  15. 根据权利要求13所述的字线驱动器电路，其中，所述字线驱动器包括第一字线驱动器和第二字线驱动器，所述第一字线驱动器包含的所述第一NMOS管和所述第二字线驱动器包含的所述第一NMOS管位于所述第一字线驱动器包含的所述第零NMOS管和所述第二字线驱动器包含的所述第零NMOS管之间。
  16. 根据权利要求13所述的字线驱动器电路，其中，所述字线驱动器包括第一字线驱动器和第二字线驱动器，所述第一字线驱动器包含的所述第零NMOS管和所述第二字线驱动器包含的所述第零NMOS管位于所述第一字线驱动器包含的所述第一NMOS管和所述第二字线驱动器包含的所述第一NMOS管之间。
  17. 根据权利要求1所述的字线驱动器电路，其中，所述NMOS管的沟道延伸方向垂直于所述PMOS管的沟道延伸方向。
  18. 一种存储器，包含权利要求1至17中任一项所述的字线驱动器电路。
PCT/CN2022/075238 2021-07-29 2022-01-30 字线驱动器电路及存储器 WO2023005183A1 (zh)

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