WO2022269860A1 - ミキサ回路 - Google Patents
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- WO2022269860A1 WO2022269860A1 PCT/JP2021/023952 JP2021023952W WO2022269860A1 WO 2022269860 A1 WO2022269860 A1 WO 2022269860A1 JP 2021023952 W JP2021023952 W JP 2021023952W WO 2022269860 A1 WO2022269860 A1 WO 2022269860A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/12—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
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- the present invention relates to circuit technology for handling high-frequency electrical signals, particularly mixer circuits with frequency conversion functions.
- Broadband THz waves are being considered for application to next-generation wireless communications (beyond 5G) and other ultra-high-speed wireless communications.
- the 300 GHz band has less absorption attenuation during atmospheric propagation in the THz band, and the transmitter (TX) and receiver (RX) are realized by electronic devices made of CMOS (Complementary Metal Oxide Semiconductor), SiGe, InP, etc. Since it is a possible frequency band, research and development are being actively pursued (see, for example, Non-Patent Document 1 and Non-Patent Document 2).
- InP which has excellent high-frequency characteristics, is a semiconductor material that can realize an amplifier with a high gain of about 20 dB even at 300 GHz. See Patent Document 3).
- FIG. 13 shows a general TX configuration.
- the TX is composed of an amplifier 100 , a mixer 101 and a power amplifier (PA: Power Amplifier) 102 .
- the mixer 101 multiplies an intermediate frequency signal (IF (Intermediate Frequency) signal) by a local oscillation signal (LO (Local Oscillator) signal) to generate a high frequency signal (RF (Radio Frequency) signal) in a desired frequency band. do.
- IF Intermediate Frequency
- LO Local Oscillator
- RF Radio Frequency
- the linearity of amplifying the RF signal output from the mixer without distortion is important.
- the 1 dB gain suppression point output (OP1dB) which is the output at which the gain is 1 dB lower than the small signal gain
- the 1 dB gain suppression point input (OP1dB) which is the input at which the gain is 1 dB lower than the small signal gain IP1dB
- the PA 102 uses a power combining technique using an in-phase splitter 1020, a plurality of amplifiers 1021, and an in-phase combiner 1022, as shown in FIG.
- the PA gain in the 300 GHz band is around 10 dB.
- the PA gain is 20 dB
- the mixer conversion gain is -10 dB.
- the mixer 101 shown in FIG. 13 can also be made highly linear in principle by using the power combining technique.
- the mixer 101 in FIG. 15 comprises an in-phase splitter 1010 for LO signals, an in-phase splitter 1011 for IF signals, a plurality of mixers 1012 and an in-phase combiner 1013 . That is, by arranging N mixers 1012 of the same performance in parallel and performing power combining on each of the LO signal, IF signal, and RF signal of each mixer 1012, the linearity can be increased N times.
- the present invention has been made to solve the above problems, and aims to make the mixer circuit highly linear.
- the mixer circuit of the present invention includes a power divider configured to divide an LO signal into N (N is an integer equal to or greater than 2) with equal amplitude and equal phase, and between an IF port to which an IF signal is input and the ground.
- N transmission lines connected in series to each other, N unit mixers whose IF signal input terminals are connected to respective ends of the N transmission lines, and N output terminals of the power divider N delay circuits respectively inserted between the LO signal input terminals of the N unit mixers and N RF signals output from the N unit mixers are combined with equal amplitude and equal phase.
- phase delay amount of each of the N transmission lines with respect to the IF signal is ⁇ IF
- N) is set to ⁇ 1 -k ⁇ IF or ⁇ 1 +k ⁇ IF (where ⁇ 1 is an arbitrary phase).
- one configuration example of the mixer circuit of the present invention includes N first amplifiers respectively inserted between the N output terminals of the power divider and the input terminals of the N delay circuits, The apparatus further comprises N second amplifiers respectively inserted between the output terminals of the N delay circuits and the LO signal input terminals of the N unit mixers. Further, one configuration example of the mixer circuit of the present invention further comprises third amplifiers respectively inserted between the RF signal output terminals of the N unit mixers and the N input terminals of the power combiner. It is characterized by
- the mixer circuit of the present invention includes: a first power divider configured to divide the LO signal into N (N is an integer equal to or greater than 2) with equal amplitude and equal phase; N transmission lines connected in series between the IF port from which the IF signal is output and the ground; and the RF signal input terminal is connected to the first N unit mixers each connected to each of N output terminals of two power dividers and having an IF signal output terminal connected to each end of each of said N transmission lines; and said first power divider.
- N is an integer equal to or greater than 2
- N transmission lines connected in series between the IF port from which the IF signal is output and the ground
- the RF signal input terminal is connected to the first N unit mixers each connected to each of N output terminals of two power dividers and having an IF signal output terminal connected to each end of each of said N transmission lines; and said first power divider.
- phase delay amount of the LO signal by the k-th delay circuit (k is an integer from 1 to N) counted from the IF port side is ⁇ 1 -(N ⁇ k+1) ⁇ IF , or ⁇ 1 +(N ⁇ k+1) ⁇ IF ( ⁇ 1 is an arbitrary phase).
- one configuration example of the mixer circuit of the present invention includes N first power dividers inserted between the N output terminals of the first power distributor and the input terminals of the N delay circuits, respectively. and N second amplifiers respectively inserted between the output terminals of the N delay circuits and the LO signal input terminals of the N unit mixers. be. Further, one configuration example of the mixer circuit of the present invention includes N unit mixers inserted between the N output terminals of the second power divider and the RF signal input terminals of the N unit mixers. 3 amplifiers.
- the mixer circuit of the present invention includes a power divider configured to divide the LO signal into N (N is an integer equal to or greater than 2) with equal amplitude and equal phase, and N transistors whose sources are connected to the ground. , N delay circuits respectively inserted between the N output terminals of the power divider and the gates of the N transistors, and N RF output from the drains of the N transistors a power combiner configured to combine signals with equal amplitude and equal phase; 2N first transmission lines connected in series between an IF port to which an IF signal is input and a ground; a connection point between the 2k ⁇ 1-th (k is an integer of 1 to N) and the 2k-th first transmission line counted from the IF port side, and k counted from the IF port side; N second transmission lines having a length of a quarter wavelength at the frequency of the LO signal inserted between the gate of the transistor and one end of the 2k-1th first transmission line and N third transmission lines having a length of a quarter wavelength at the
- the k-th A phase delay amount of the LO signal by the delay circuit is set to ⁇ 1 -k ⁇ IF or ⁇ 1 +k ⁇ IF ( ⁇ 1 is an arbitrary phase).
- the mixer circuit of the present invention includes a power divider configured to divide the LO signal into N (N is an integer equal to or greater than 2) with equal amplitude and equal phase, and N transistors whose sources are connected to the ground. , N delay circuits respectively inserted between the N output terminals of the power divider and the gates of the N transistors, and N RF output from the drains of the N transistors.
- a power combiner configured to combine signals with equal amplitude and equal phase, and a quarter wavelength at the frequency of the RF signal, connected in series between the IF port to which the IF signal is input and ground.
- 2N+1 first transmission lines having a length of 2N+1, the termination of the 2k ⁇ 1-th (k is an integer of 1 to N) counting from the IF port side, and the 2k-th first transmission line N+1 second transmission lines inserted between the input ends of the 2N+1-th transmission lines and between the terminal end of the 2N+1-th first transmission line and the ground, and one end counted from the IF port side 2i ⁇ 1 (i is an integer from 1 to N+1), connected to the connection point between the first transmission line and the i-th second transmission line and the other end is open, at the frequency of the RF signal N+1 third transmission lines each having a length of one-tenth wavelength, and one end of which is a connection point between the 2k-th first transmission line and the k-th second transmission line counted from the IF port side.
- N fourth transmission lines having a length of a quarter wavelength at the frequency of the RF signal, and the other end is open, and the 2k-1th first transmission line and the 2k
- the LO by the k-th delay circuit counted from the IF port side The phase delay amount of the signal is set to ⁇ 1 -k ⁇ IF or ⁇ 1 +k ⁇ IF ( ⁇ 1 is an arbitrary phase).
- the linearity of the mixer circuit can be increased to N times that of the individual unit mixers.
- FIG. 1 is a block diagram showing the configuration of a mixer circuit according to a first embodiment of the invention.
- FIG. 2 is a block diagram showing the configuration of a general distributed mixer.
- FIG. 3 is a block diagram showing another configuration of the mixer circuit according to the first embodiment of the invention.
- FIG. 4 is a block diagram showing the configuration of a mixer circuit according to the second embodiment of the invention.
- FIG. 5 is a block diagram showing another configuration of the mixer circuit according to the second embodiment of the invention.
- FIG. 6 is a block diagram showing the configuration of a mixer circuit according to the third embodiment of the invention.
- FIG. 7 is a block diagram showing another configuration of the mixer circuit according to the third embodiment of the invention.
- FIG. 8 is a block diagram showing the configuration of a mixer circuit according to the fourth embodiment of the invention.
- FIG. 9 is a diagram showing an outline of a gate mixer.
- FIG. 10 is a block diagram showing the configuration of a mixer circuit according to the fifth embodiment of the invention.
- FIG. 11 is a diagram showing an outline of a resistive mixer.
- FIG. 12 is a block diagram showing the configuration of a mixer circuit according to the sixth embodiment of the invention.
- FIG. 13 is a block diagram showing the configuration of a conventional transmitter.
- FIG. 14 is a block diagram showing the configuration of a power amplifier using power combining technology.
- FIG. 15 is a block diagram showing the configuration of a mixer using power combining technology.
- FIG. 1 is a block diagram showing the configuration of a mixer circuit according to this embodiment.
- the mixer circuit includes a power divider 1 that divides the LO signal by N equal amplitude and equal phase (N is an integer of 2 or more), N delay circuits 2-1 to 2-N, and N unit mixers 3. -1 to 3-N are connected in series between the IF port 41 to which the IF signal is input and the ground, and the respective ends are connected to the IF signal input terminals of the unit mixers 3-1 to 3-N.
- N transmission lines 4-1 to 4-N N transmission lines 4-1 to 4-N, a terminating resistor 5 connecting the terminal end of the transmission line 4-N at the final stage and the ground, and N units output from the unit mixers 3-1 to 3-N and a power synthesizer 6 for synthesizing these RF signals with equal amplitude and phase.
- 40 is an LO port to which the LO signal is input
- 42 is an RF port to which the RF signal is output.
- a distributed matching technique is used to achieve power combining of IF signals within a planar circuit.
- Distributed matching technology refers to the inductance of each of the N transmission lines 4-1 to 4-N and the parasitic capacitance of each of the N unit mixers 3-1 to 3-N. This is a method of realizing broadband impedance matching by forming an N-stage ladder-type pseudo transmission line by .
- a distributed matching mixer circuit is called a distributed mixer.
- Distributed mixers generally form distributed matching circuits for all of the IF signal, LO signal, and RF signal.
- FIG. 2 shows the configuration of a typical distributed mixer. 7-1 to 7-N and 8-1 to 8-N are transmission lines, and 9 and 10 are terminating resistors.
- the distributed mixer According to the distributed mixer, wide bands of IF signal, LO signal and RF signal can be secured. cannot be multiplied by N. The reason why the linearity cannot be increased by N times is due to distribution matching of the LO signal. That is, in the configuration of FIG. 2, since the input LO signal is attenuated while propagating through the transmission lines 7-1 to 7-N, the first unit mixer 3-1 counted from the IF port 41 side is driven. The power of the LO signal and the power of the LO signal driving the N-th unit mixer 3-N are significantly different.
- the linearity of the distribution mixer as a whole using N unit mixers 3-1 to 3-N is not N times as high as when one unit mixer is used.
- the linearity of the distribution mixer is approximately equal to or slightly greater than the linearity of the first unit mixer 3-1 supplied with the largest LO signal.
- the RF distributed matching circuit consisting of the transmission lines 8-1 to 8-N and the terminating resistor 10 also has a large loss for the RF signal, the conversion gain and OP1dB of the distributed mixer are higher than when one unit mixer is used. It is normal for it to be smaller.
- an IF distributed matching circuit composed of transmission lines 4-1 to 4-N and a terminating resistor 5 is used for the IF signal. Do not use distributed matching circuits. The reason why the LO distributed matching circuit and the RF distributed matching circuit are not used is to supply LO signals of the same power to all the unit mixers 3-1 to 3-N.
- phase matching of the mixer becomes a problem.
- all of the RF signal, LO signal, and IF signal are phase-matched, but in the configuration of this embodiment shown in FIG. That is, there is a possibility that the phases of the RF signals output from the unit mixers 3-1 to 3-N may be scattered, and even if the N-input 1-output power combiner 6 is used, N-fold power combining cannot be realized. .
- Delay circuits 2-1 to 2-N are applied.
- the delay circuits 2-1 to 2-N are inserted between the N output terminals of the power distributor 1 and the LO signal input terminals of the N unit mixers 3-1 to 3-N, respectively.
- the delay circuits 2-1 to 2-N can be realized by transmission lines or the like.
- Equation (1) shows the case where the frequency of the RF signal is the sum of the frequency of the LO signal and the frequency of the IF signal, that is, the case where the upper sideband is used as the RF signal.
- Equation (2) shows the case where the frequency of the RF signal is the difference between the frequency of the LO signal and the frequency of the IF signal, that is, when the lower sideband is used as the RF signal.
- the phase delay amount of the LO signal by the k-th (k is an integer from 1 to N) delay circuit 2-k counted from the IF port 41 side is ⁇ 1 -k ⁇ IF
- the phases of the RF signals output from the N unit mixers 3-1 to 3-N can all be aligned to the same value ⁇ 1 ( ⁇ 1 is an arbitrary phase).
- the phase delay amount with respect to the IF signal is set to the same value ⁇ IF for each of the transmission lines 4-1 to 4-N.
- FIG. 3 shows the configuration of the mixer circuit of this embodiment, which uses the lower sideband as the RF signal.
- the lower sideband is used as the RF signal
- the phase delay amount of the LO signal by the k-th delay circuit 2a-k counted from the IF port 41 side is set to ⁇ 1 +k ⁇ IF , then N
- the phases of the RF signals output from the unit mixers 3-1 to 3-N can all be adjusted to the same value ⁇ 1 .
- the LO signal frequency is 250 GHz or higher, and the IF signal frequency is about 25 GHz.
- the length of the delay circuits 2-1 to 2-N and 2a-1 to 2a-N required to obtain the same amount of phase delay as the IF signal is 1/10 of the length of the IF signal transmission line. .
- the fact that the delay circuits 2-1 to 2-N and 2a-1 to 2a-N for the LO signal are short also greatly differs from the distributed mixer of FIG.
- the IF signal, LO signal, and RF signal transmission lines 4-1 to 4-N, 7-1 to 7-N, and 8-1 to 8-N are generally of approximately the same physical length. have. Therefore, the loss of LO signals and RF signals with high frequencies inevitably increases.
- the LO signal delay circuits 2-1 to 2-N and 2a-1 to 2a-N are short, loss due to the delay circuits 2-1 to 2-N and 2a-1 to 2a-N is a problem. does not become
- the capacitance of the unit mixers 3-1 to 3-N and the transmission lines 4-1 to 4-N should be determined so that the characteristic impedance of the pseudo transmission line, which is composed of the inductance of , becomes a desired value (usually 50 ⁇ ).
- the phase delay amount ⁇ IF of each of the transmission lines 4-1 to 4-N is determined. It becomes possible to determine the physical parameters of 2a-1 to 2a-N. Further, from the principle of distribution matching, a wider band mixer characteristic can be obtained by arranging a 50 ⁇ resistor as the terminating resistor 5 at the terminating portion of the IF port 41 .
- this embodiment has a configuration in which the N unit mixers 3-1 to 3-N are driven by LO signals of the same power and output RF signals of the same phase, the linearity of the mixer circuit can be N times the individual unit mixers.
- the mixer circuit of this embodiment is different from the mixer circuit of the first embodiment in that LOs are connected between the N output terminals of the power distributor 1 and the input terminals of the N delay circuits 2-1 to 2-N.
- Amplifiers 11-1 to 11-N for amplifying signals are inserted, output terminals of N delay circuits 2-1 to 2-N and LO signal input terminals of N unit mixers 3-1 to 3-N.
- Amplifiers 12-1 to 12-N for amplifying LO signals are inserted between them.
- the N unit mixers 3-1 to 3-N can be driven by LO signals of completely the same power (saturation power of amplifiers 11-1 to 11-N and 12-1 to 12-N). Also, the amplifiers 11-1 to 11-N and 12-1 to 12-N generally have reverse isolation. Therefore, the impedances viewed from the unit mixers 3-1 to 3-N are not affected by the delay circuits 2-1 to 2-N.
- amplifiers 13- for amplifying RF signals are placed between the RF signal output terminals of the N unit mixers 3-1 to 3-N and the N input terminals of the power combiner 6, respectively. 1 to 13-N, the outputs of the unit mixers 3-1 to 3-N can be amplified without being affected by the excess loss of the power combiner 6, and the conversion of the mixer circuit of this embodiment is possible. Gain can be further improved.
- delay circuits 2-1 to 2-N are used in the examples of FIGS. 4 and 5, delay circuits 2a-1 to 2a are used instead of the delay circuits 2-1 to 2-N in FIGS.
- -N By providing -N, a configuration using the lower sideband as the RF signal can be realized.
- radio communications use only either the upper sideband or the lower sideband as RF signals.
- the reasons for using only one of the upper sideband and the lower sideband are to make effective use of the band and to improve the SNR.
- the lower sideband is treated as an unwanted wave called an image signal. Therefore, it may be desirable to have the ability to remove the image signal in TX.
- a mixer with the function of removing image signals is generally called an image rejection mixer.
- the design of the delay circuits 2-1 to 2-N when using the upper sideband for RF signals and the delay circuits 2a-1 to 2a-N when using the lower sideband for RF signals are different.
- the delay circuits 2-1 to 2-N and 2a-1 to 2a-N align the phases of either the upper sideband or the lower sideband in the outputs of the N unit mixers 3-1 to 3-N. Designed. This is because unless the unit mixers 3-1 to 3-N are designed to match the phases of their outputs, the power combiner 6 cannot combine the power of the N RF signals.
- the mixer circuit of the present invention inherently has an image rejection function.
- FIG. 6 is a block diagram showing the configuration of the mixer circuit according to this embodiment.
- the mixer circuit of this embodiment includes a power divider 1, unit mixers 3-1 to 3-N, transmission lines 4-1 to 4-N, a terminating resistor 5, and N outputs of the power divider 1.
- N delay circuits 14-1 to 14-N respectively inserted between the terminal and the LO signal input terminals of N unit mixers 3-1 to 3-N, and the RF signal with equal amplitude and equal phase.
- a power divider 15 for dividing and inputting to RF signal input terminals of N unit mixers 3-1 to 3-N. Since the mixer circuit of this embodiment is a down-conversion mixer, the IF port 41 serves as a port for outputting an IF signal, and the RF port 42 serves as a port for inputting an RF signal.
- the phase delay amount of the LO signal by the k-th (k is an integer from 1 to N) delay circuit 14-k counted from the IF port 41 side is ⁇ 1 -(N-k+1 ) to ⁇ IF .
- the phase of the LO signal input to the k-th unit mixer 3-k is ⁇ 1 -(N ⁇ k+1) ⁇ IF .
- the phase of the RF signal input to the k-th unit mixer 3-k is ⁇ RF .
- ⁇ RF is a constant value independent of k.
- the phase of the IF signal output from the k-th unit mixer 3-k is ⁇ RF -[ ⁇ 1 -(N ⁇ k+1) ⁇ IF ].
- FIG. 7 shows the configuration of the mixer circuit of this embodiment, which uses the lower sideband as the RF signal.
- the phase delay amount of the LO signal by the k-th delay circuit 14a-k counted from the IF port 41 side should be set to ⁇ 1 +(N ⁇ k+1) ⁇ IF . Just do it.
- FIG. 8 The configuration of FIG. 8 is shown as a more practical configuration of the third embodiment.
- the mixer circuit of this embodiment is different from the mixer circuit of the third embodiment in that LO signals are connected between the N output terminals of the power distributor 1 and the input terminals of the N delay circuits 14-1 to 14-N.
- Amplifiers 16-1 to 16-N for amplifying signals are inserted, output terminals of N delay circuits 14-1 to 14-N and LO signal input terminals of N unit mixers 3-1 to 3-N.
- Amplifiers 17-1 to 17-N for amplifying LO signals are inserted between them.
- a preamplifier 18 for amplifying the RF signal is inserted between the RF port 42 and the input terminal of the power divider 15, and the N output terminals of the power divider 15 and the N units are connected.
- Amplifiers 19-1 to 19-N for amplifying RF signals are inserted between the RF signal input terminals of the mixers 3-1 to 3-N.
- NF Noise Figure
- delay circuits 14-1 to 14-N are used. Then, a configuration using the lower sideband as the RF signal can be realized.
- a fifth embodiment of the present invention will now be described.
- the gate mixer as shown in FIG. 9, is configured to input an IF signal and an LO signal to a gate G of a source-grounded FET (Field Effect Transistor) 20 and extract an RF signal from a drain D of the FET 20 .
- FET Field Effect Transistor
- FIG. 10 is a block diagram showing the configuration of the mixer circuit according to this embodiment.
- the mixer circuit of this embodiment includes a power divider 1, delay circuits 2-1 to 2-N, a power combiner 6, amplifiers 11-1 to 11-N, 12-1 to 12-N, gates G is connected to the output terminals of amplifiers 12-1 to 12-N, the drain D is connected to the input terminal of the power combiner 6, and the source S is grounded.
- 2N transmission lines 21-1 to 21-2N connected in series between the IF port 41 and the ground, a 50 ⁇ termination resistor 22 connecting the termination of the transmission line 21-2N and the ground, an IF Counting from the port 41 side, the connection point between the 2k-1-th (k is an integer N transmission lines 23-1 to 23-N each having a length of a quarter wavelength at the frequency of the LO signal and inserted between the gate G of the FET 20-k and one end of which is an integer of .
- N transmission lines 24- each having a length of a quarter wavelength at the frequency of the LO signal, connected to the connection point between the transmission lines 21-(2k ⁇ 1) and 21-2k and the other end is open. 1 to 24-N.
- All of the transmission lines 21-1 to 21-2N constituting the IF distribution matching circuit are set to have the same phase delay amount with respect to the IF signal.
- the total phase delay amount of the two adjacent transmission lines 21-(2k-1) and 21-2k with respect to the IF signal is set to ⁇ IF .
- the gate mixer of FIG. 9 can up-convert an IF signal to an RF signal, but cannot down-convert an RF signal to an IF signal. Therefore, inevitably, the mixer circuit of this embodiment becomes an up-conversion mixer. With the configuration of this embodiment, a high linearity characteristic that is N times the linearity of a normal gate mixer can be obtained.
- a point to be noted here is the isolation of the LO signal and the IF signal.
- isolation between the LO signal and the IF signal can be achieved by the LO matching circuit 200 and the IF matching circuit 201 .
- this embodiment uses an IF distribution matching circuit composed of the transmission lines 21-1 to 21-2N and the terminating resistor 22, it is necessary to ensure isolation by a method different from that of lumped-constant gate mixers.
- transmission lines 23-1 to 23-N and 24-1 to 24-N are used.
- the transmission lines 24-1 to 24-N are open stubs. Therefore, the impedance of the connection point between the IF distributed matching circuit and the transmission lines 24-1 to 24-N (the connection point between the transmission line 21-(2k-1) and the transmission line 21-2k) is 0 (short circuit).
- the FETs 20-1 to 20-N By rotating the signal phase at the connection point between the IF distribution matching circuit and the transmission lines 24-1 to 24-N by the transmission lines 23-1 to 23-N, the FETs 20-1 to 20-N at the LO signal frequency
- the impedance from the gate G to the IF distributed matching circuit can be made infinite (open).
- the frequencies of the LO signal and the IF signal differ by about ten times, so the transmission lines 23-1 to 23-N and 24-1 to 24-N are sufficiently short for the IF signal. Therefore, it can be considered that the transmission lines 23-1 to 23-N and 24-1 to 24-N do not adversely affect the characteristics of the IF distribution matching circuit.
- the amplifiers 11-1 to 11-N and 12-1 to 12-N are not essential components.
- the input terminals of the delay circuits 2-1 to 2-N are connected, and the output terminals of the N delay circuits 2-1 to 2-N and the gates G of the N FETs 20-1 to 20-N are connected. You may make it connect.
- amplifiers for amplifying RF signals are inserted between the drains D of the N FETs 20-1 to 20-N and the N input terminals of the power combiner 6.
- FIG. 10 shows the case of using the upper sideband as the RF signal. Circuits 2a-1 to 2a-N may be provided.
- FIG. 11 inputs an LO signal to the gate G of the source-grounded FET 25, inputs an IF signal to the drain D of the FET 25, extracts an RF signal from the drain D, or outputs an RF signal to the drain D.
- a signal is input and an IF signal is taken out from the drain D.
- both up-conversion and down-conversion are possible with the resistive mixer in FIG. Therefore, in this embodiment, both the up-conversion mixer and the down-conversion can be realized.
- FIG. 12 is a block diagram showing the configuration of the mixer circuit according to this embodiment.
- the mixer circuit of this embodiment includes a power divider 1, delay circuits 2-1 to 2-N, a power combiner 6, amplifiers 11-1 to 11-N, 12-1 to 12-N, gates G is connected to the output terminal of the amplifiers 12-1 to 12-N, the drain D is connected to the input terminal of the power combiner 6, and the source S is grounded.
- N+1 transmission lines 27-1 to 27-(N+1) inserted between and the ground a termination resistor 28 connecting the termination of the transmission line 27-(N+1) and the ground, and one end of which is an IF port 41 connected to the connection point between the 2i-1 (i is an integer from 1 to N+1)-th transmission line 26-(2i-1) and the i-th transmission line 27-i counting from the side, and the other end is open, N+1 transmission lines 29-1 to 29-(N+1) each having a length of a quarter wavelength at the frequency of the RF signal, one end of which is the 2k-th transmission line 26-2k counted from the IF port 41 side, and the k-th transmission line N transmission lines 30-1 to 30-N having a length of 1/4 wavelength in the frequency of the RF signal,
- All of the transmission lines 26-1 to 26-(2N+1) have the same phase delay amount with respect to the IF signal.
- the phase delay amount with respect to the IF signal is set to the same value for each of the transmission lines 27-1 to 27-(N+1).
- the total phase delay amount with respect to the IF signal of the three transmission lines 26-(2k-1), 26-2k, and 27-k is set to ⁇ IF .
- the configuration of FIG. 12 shows an example of an upconversion mixer. With the configuration of this embodiment, linearity that is N times the linearity per resistive mixer can be obtained.
- RF and IF signals can be isolated by the RF matching circuit 202 and the IF matching circuit 201 .
- a lumped resistive mixer is used. Isolation must be ensured by a different method.
- the transmission lines 26-1 to 26-(2N+1), 29-1 to 29-(N+1), and 30-1 to 30-N each having a length of a quarter wavelength of the frequency of the RF signal are used.
- Use Transmission lines 29-1 to 29-(N+1) and 30-1 to 30-N are open stubs. Therefore, connection points between the IF distribution matching circuits and the transmission lines 29-1 to 29-(N+1) and 30-1 to 30-N (connection points between the transmission lines 26-(2i-1) and the transmission lines 27-i , the connection point between the transmission line 26-2k and the transmission line 27-k) becomes 0 (short circuit) at the frequency of the RF signal.
- the RF At the frequency of the signal, the impedance from the drains D of the FETs 25-1 to 25-N to the IF distribution matching circuit can be made infinite (open).
- the IF distributed matching circuit is arranged in two branches. 26-(2N+1), 29-1 to 29-(N+1), 30-1 to 30-N are required.
- the frequencies of the RF signal and the IF signal differ by about 10 times.
- -1 to 30-N are sufficiently short. Therefore, it can be considered that the transmission lines 26-1 to 26-(2N+1), 29-1 to 29-(N+1), and 30-1 to 30-N do not adversely affect the characteristics of the IF distributed matching circuit. .
- the amplifiers 11-1 to 11-N and 12-1 to 12-N are not essential components.
- the input terminals of the delay circuits 2-1 to 2-N are connected, and the output terminals of the N delay circuits 2-1 to 2-N and the gates G of the N FETs 25-1 to 25-N are connected. You may make it connect.
- FIG. 12 shows the case of using the upper sideband as the RF signal. Circuits 2a-1 to 2a-N may be provided.
- the present invention can be applied to mixer circuits that perform frequency conversion of signals.
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Abstract
Description
300GHz帯のように極めて高い周波数帯においては、トランジスタ一つ当たりの利得が小さいため、PAの利得を低周波帯のように大きくとることが難しい。典型的には、300GHz帯におけるPAの利得は10dB程度である。
また、本発明のミキサ回路の1構成例は、前記N個の単位ミキサのRF信号出力端子と前記電力合成器のN個の入力端子との間にそれぞれ挿入された第3の増幅器をさらに備えることを特徴とするものである。
また、本発明のミキサ回路の1構成例は、前記第2の電力分配器のN個の出力端子と前記N個の単位ミキサのRF信号入力端子との間にそれぞれ挿入されたN個の第3の増幅器をさらに備えることを特徴とするものである。
以下、本発明の実施例について図面を参照して説明する。図1は本実施例に係るミキサ回路の構成を示すブロック図である。ミキサ回路は、LO信号を等振幅・等位相でN分配(Nは2以上の整数)する電力分配器1と、N個の遅延回路2-1~2-Nと、N個の単位ミキサ3-1~3-Nと、IF信号が入力されるIFポート41とグラウンドとの間に直列に接続され、それぞれの終端が単位ミキサ3-1~3-NのIF信号入力端子と接続されたN個の伝送線路4-1~4-Nと、終段の伝送線路4-Nの終端とグラウンドとを接続する終端抵抗5と、単位ミキサ3-1~3-Nから出力されるN個のRF信号を等振幅・等位相で合成する電力合成器6とから構成される。40はLO信号が入力されるLOポート、42はRF信号が出力されるRFポートである。
θRF=θLO+θIF ・・・(1)
θRF=θLO―θIF ・・・(2)
第1の実施例では、遅延回路2-1~2-N,2a-1~2a-Nによる僅かな損失や、単位ミキサ3-1~3-NからLO信号側を見込んだインピーダンスの変化がミキサ回路の全体動作に影響を及ぼすことが考えられるため、より実用的な構成として図4の構成を示す。
第1、第2の実施例では、TXに用いるアップコンバージョンミキサの例で説明しているが、本発明はRXに用いるダウンコンバージョンミキサに適用することも可能である。ただし、この場合もLO信号の遅延量を適切に設計する必要がある。
第3の実施例の、より実用的な構成として図8の構成を示す。本実施例のミキサ回路は、第3の実施例のミキサ回路において、電力分配器1のN個の出力端子とN個の遅延回路14-1~14-Nの入力端子との間にそれぞれLO信号を増幅する増幅器16-1~16-Nを挿入し、N個の遅延回路14-1~14-Nの出力端子とN個の単位ミキサ3-1~3-NのLO信号入力端子との間にそれぞれLO信号を増幅する増幅器17-1~17-Nを挿入したものである。さらに、本実施例では、RFポート42と電力分配器15の入力端子との間にRF信号を増幅する前置増幅器18を挿入し、電力分配器15のN個の出力端子とN個の単位ミキサ3-1~3-NのRF信号入力端子との間にそれぞれRF信号を増幅する増幅器19-1~19-Nを挿入している。
次に、本発明の第5の実施例について説明する。本実施例では、単位ミキサとしてゲートミキサを使用する場合について説明する。ゲートミキサは、図9に示すように、ソース接地FET(Field Effect Transistor)20のゲートGにIF信号およびLO信号を入力し、RF信号をFET20のドレインDから取り出す構成である。
本実施例の構成により、通常のゲートミキサの線形性がN倍された高線形特性が得られる。
なお、本実施例において増幅器11-1~11-N,12-1~12-Nは必須の構成ではなく、第1の実施例と同様に、電力分配器1のN個の出力端子とN個の遅延回路2-1~2-Nの入力端子とを接続し、N個の遅延回路2-1~2-Nの出力端子とN個のFET20-1~20-NのゲートGとを接続するようにしてもよい。
次に、本発明の第6の実施例について説明する。本実施例では、単位ミキサとしてレジスティブミキサを使用する場合について説明する。レジスティブミキサは、図11に示すように、ソース接地FET25のゲートGにLO信号を入力し、FET25のドレインDにIF信号を入力し、RF信号をドレインDから取り出すか、またはドレインDにRF信号を入力し、IF信号をドレインDから取り出す構成である。
本実施例の構成により、レジスティブミキサ1個当たりの線形性をN倍した線形性が得られる。
なお、本実施例において増幅器11-1~11-N,12-1~12-Nは必須の構成ではなく、第1の実施例と同様に、電力分配器1のN個の出力端子とN個の遅延回路2-1~2-Nの入力端子とを接続し、N個の遅延回路2-1~2-Nの出力端子とN個のFET25-1~25-NのゲートGとを接続するようにしてもよい。
Claims (8)
- LO信号を等振幅・等位相でN分配(Nは2以上の整数)するように構成された電力分配器と、
IF信号が入力されるIFポートとグラウンドとの間に直列に接続されたN個の伝送線路と、
IF信号入力端子が前記N個の伝送線路のそれぞれの終端に接続されたN個の単位ミキサと、
前記電力分配器のN個の出力端子と前記N個の単位ミキサのLO信号入力端子との間にそれぞれ挿入されたN個の遅延回路と、
前記N個の単位ミキサから出力されるN個のRF信号を等振幅・等位相で合成するように構成された電力合成器とを備え、
前記N個の伝送線路のそれぞれの、IF信号に対する位相遅延量をΔθIFとしたときに、前記IFポート側から数えてk番目(kは1~Nの整数)の前記遅延回路によるLO信号の位相遅延量がθ1-kΔθIF、またはθ1+kΔθIF(θ1は任意の位相)に設定されていることを特徴とするミキサ回路。 - 請求項1記載のミキサ回路において、
前記電力分配器のN個の出力端子と前記N個の遅延回路の入力端子との間にそれぞれ挿入されたN個の第1の増幅器と、
前記N個の遅延回路の出力端子と前記N個の単位ミキサのLO信号入力端子との間にそれぞれ挿入されたN個の第2の増幅器とをさらに備えることを特徴とするミキサ回路。 - 請求項1または2記載のミキサ回路において、
前記N個の単位ミキサのRF信号出力端子と前記電力合成器のN個の入力端子との間にそれぞれ挿入された第3の増幅器をさらに備えることを特徴とするミキサ回路。 - LO信号を等振幅・等位相でN分配(Nは2以上の整数)するように構成された第1の電力分配器と、
RF信号を等振幅・等位相でN分配するように構成された第2の電力分配器と、
IF信号が出力されるIFポートとグラウンドとの間に直列に接続されたN個の伝送線路と、
RF信号入力端子が前記第2の電力分配器のN個の出力端子のそれぞれに接続され、IF信号出力端子が前記N個の伝送線路のそれぞれの終端に接続されたN個の単位ミキサと、
前記第1の電力分配器のN個の出力端子と前記N個の単位ミキサのLO信号入力端子との間にそれぞれ挿入されたN個の遅延回路とを備え、
前記N個の伝送線路のそれぞれの、IF信号に対する位相遅延量をΔθIFとしたときに、前記IFポート側から数えてk番目(kは1~Nの整数)の前記遅延回路によるLO信号の位相遅延量がθ1-(N-k+1)ΔθIF、またはθ1+(N-k+1)ΔθIF(θ1は任意の位相)に設定されていることを特徴とするミキサ回路。 - 請求項4記載のミキサ回路において、
前記第1の電力分配器のN個の出力端子と前記N個の遅延回路の入力端子との間にそれぞれ挿入されたN個の第1の増幅器と、
前記N個の遅延回路の出力端子と前記N個の単位ミキサのLO信号入力端子との間にそれぞれ挿入されたN個の第2の増幅器とをさらに備えることを特徴とするミキサ回路。 - 請求項4または5記載のミキサ回路において、
前記第2の電力分配器のN個の出力端子と前記N個の単位ミキサのRF信号入力端子との間にそれぞれ挿入されたN個の第3の増幅器をさらに備えることを特徴とするミキサ回路。 - LO信号を等振幅・等位相でN分配(Nは2以上の整数)するように構成された電力分配器と、
ソースがグラウンドに接続されたN個のトランジスタと、
前記電力分配器のN個の出力端子と前記N個のトランジスタのゲートとの間にそれぞれ挿入されたN個の遅延回路と、
前記N個のトランジスタのドレインから出力されたN個のRF信号を等振幅・等位相で合成するように構成された電力合成器と、
IF信号が入力されるIFポートとグラウンドとの間に直列に接続された2N個の第1の伝送線路と、
前記IFポート側から数えて2k-1番目(kは1~Nの整数)の前記第1の伝送線路と2k番目の前記第1の伝送線路との接続点と、前記IFポート側から数えてk番目の前記トランジスタのゲートとの間に挿入された、LO信号の周波数における四分の一波長の長さのN個の第2の伝送線路と、
一端が前記2k-1番目の第1の伝送線路と前記2k番目の第1の伝送線路との接続点に接続され他端が開放された、LO信号の周波数における四分の一波長の長さのN個の第3の伝送線路とを備え、
前記2k-1番目の第1の伝送線路と前記2k番目の第1の伝送線路の、IF信号に対する合計の位相遅延量をΔθIFとしたときに、前記IFポート側から数えてk番目の前記遅延回路によるLO信号の位相遅延量がθ1-kΔθIF、またはθ1+kΔθIF(θ1は任意の位相)に設定されていることを特徴とするミキサ回路。 - LO信号を等振幅・等位相でN分配(Nは2以上の整数)するように構成された電力分配器と、
ソースがグラウンドに接続されたN個のトランジスタと、
前記電力分配器のN個の出力端子と前記N個のトランジスタのゲートとの間にそれぞれ挿入されたN個の遅延回路と、
前記N個のトランジスタのドレインから出力されるN個のRF信号を等振幅・等位相で合成するように構成された電力合成器と、
IF信号が入力されるIFポートとグラウンドとの間に直列に接続された、RF信号の周波数における四分の一波長の長さの2N+1個の第1の伝送線路と、
前記IFポート側から数えて2k-1番目(kは1~Nの整数)の前記第1の伝送線路の終端と2k番目の前記第1の伝送線路の入力端との間、および2N+1番目の前記第1の伝送線路の終端とグラウンドとの間に挿入されたN+1個の第2の伝送線路と、
一端が前記IFポート側から数えて2i-1(iは1~N+1の整数)番目の前記第1の伝送線路とi番目の前記第2の伝送線路との接続点に接続され他端が開放された、RF信号の周波数における四分の一波長の長さのN+1個の第3の伝送線路と、
一端が前記IFポート側から数えて2k番目の前記第1の伝送線路とk番目の前記第2の伝送線路との接続点に接続され他端が開放された、RF信号の周波数における四分の一波長の長さのN個の第4の伝送線路とを備え、
前記2k-1番目の第1の伝送線路と前記2k番目の第1の伝送線路と前記k番目の第2の伝送線路の、IF信号に対する合計の位相遅延量をΔθIFとしたときに、前記IFポート側から数えてk番目の前記遅延回路によるLO信号の位相遅延量がθ1-kΔθIF、またはθ1+kΔθIF(θ1は任意の位相)に設定されていることを特徴とするミキサ回路。
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JP2014116697A (ja) * | 2012-12-06 | 2014-06-26 | Sumitomo Electric Ind Ltd | ミキサ |
WO2017216839A1 (ja) * | 2016-06-13 | 2017-12-21 | 三菱電機株式会社 | 高周波整流器 |
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JP2014116697A (ja) * | 2012-12-06 | 2014-06-26 | Sumitomo Electric Ind Ltd | ミキサ |
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