WO2022267912A1 - 一种用于神经网络存算阵列的温度补偿电路及方法 - Google Patents

一种用于神经网络存算阵列的温度补偿电路及方法 Download PDF

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WO2022267912A1
WO2022267912A1 PCT/CN2022/098349 CN2022098349W WO2022267912A1 WO 2022267912 A1 WO2022267912 A1 WO 2022267912A1 CN 2022098349 W CN2022098349 W CN 2022098349W WO 2022267912 A1 WO2022267912 A1 WO 2022267912A1
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array
voltage
floating gate
storage
calculation
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PCT/CN2022/098349
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English (en)
French (fr)
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虞致国
刘彦航
潘红兵
顾晓峰
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江南大学
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Priority to US17/973,611 priority Critical patent/US11720327B2/en
Publication of WO2022267912A1 publication Critical patent/WO2022267912A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/089—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of temperature variations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/0607—Offset or drift compensation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

Definitions

  • the invention relates to a temperature compensation circuit and method for a neural network storage and calculation array, belonging to the technical field of integrated circuits.
  • Neural networks have made significant progress in the fields of image classification, image recognition, and autonomous driving.
  • the memory-computing integration technology based on floating gate non-volatile devices uses device arrays to integrate data storage and computing, which is suitable for neural networks.
  • the weight storage can be realized by changing the threshold voltage of the floating gate device in the storage and calculation array, and finally through the storage and calculation array.
  • the subtraction of the output current of the floating gate device realizes the multiplication and accumulation operation between the input data and the weight, and the difference between the output currents of the two columns of floating gate devices after passing through the current subtraction circuit represents the result of the operation.
  • the working process of the storage and calculation array is as follows. After the array completes the multiplication and accumulation operation and performs current subtraction, the output current is:
  • ⁇ is the mobility of the floating gate device
  • C ox is the gate oxide capacitance per unit area
  • W and L are the width and length of the floating gate device
  • ⁇ V THi is the threshold voltage difference
  • n is the weight and the number of input data
  • i-th weight is the analog voltage signal obtained after the i-th input data is converted by a DAC (digital-to-analog converter).
  • I OUT is converted to an output voltage by IV (current-voltage):
  • R is the IV conversion resistor
  • V OUT is converted into output data by an analog-to-digital conversion system composed of an external reference power supply V REF , a voltage buffer (Buffer) and an analog-to-digital converter (ADC) for further transmission.
  • V REF external reference power supply
  • Buffer voltage buffer
  • ADC analog-to-digital converter
  • the output current value of the array determines the calculation result of the neural network. If the output current deviates, the output result of the ADC will also have a deviation. After this deviation is amplified by multi-layer transmission, it will Reduce the working accuracy of the entire neural network.
  • ⁇ V THi itself has eliminated the influence of the linear temperature characteristic of the device threshold voltage on the array output current, but the device mobility ⁇ changes with temperature, and the mobility refers to the unit electric field intensity.
  • the aforementioned paper by Jiang Mingfeng et al. proposed a temperature compensation circuit, which uses an operational amplifier, a floating gate device, and a resistor to form a conductance load to directly obtain an output voltage V OUT that is not affected by temperature at the output terminal.
  • a large number of operational amplifiers are used to increase the power consumption of the neural network, and the steady-state establishment time of the operational amplifier also restricts the operation speed of the neural network;
  • the device array and the peripheral circuits of the array are placed in different layers to meet the 3D stacking technology that the neural network needs to develop towards large-scale and high computing power.
  • the compensation method in this paper requires that the compensation circuit and the storage and calculation array be in the same process layer. However, this requirement cannot be met in practical applications.
  • the present invention provides a temperature compensation circuit and method for neural network storage and calculation arrays.
  • the method performs temperature compensation on the mobility temperature drift characteristics of floating gate devices, and does not directly target
  • the output current and converted voltage are temperature compensated, but the digital output of the ADC is compensated.
  • the present invention provides a reference voltage for the ADC through a reference array sparsely inserted in the storage and calculation array, so that the input voltage of the ADC has the same temperature coefficient as the reference voltage, and finally uses the ADC to perform analog-to-digital conversion, so that the digital output of the ADC is not affected by the external temperature. influence, to ensure the calculation accuracy of each layer of the network.
  • the reference array adopted by the temperature compensation circuit of the present invention has the same structure as the storage and calculation array, and each reference array includes two columns of floating gate devices to complete the multiplication and addition operation.
  • the insertion density of the reference array is related to the temperature field where the storage and calculation arrays are located.
  • One reference array can be used to provide ADC reference voltages for multiple storage and calculation arrays at the same time, minimizing the increase in area and power consumption caused by inserting the reference array.
  • the temperature compensation method in the present invention is applicable to the 3D stacking technology in which the device array and the peripheral circuits of the array are placed on the same or different layers, and meets the requirement of large-scale development of storage and computing arrays.
  • the temperature compensation circuit in the present invention is as shown in Figure 2: wherein it includes two columns of N-type floating gate devices with storage weights as a reference array, a current subtraction circuit, and an IV conversion Resistor R 1 .
  • the two columns of N-type floating gate devices used to store weights respectively include n N-type floating gate devices MR 1+ to MR n+ and n N-type floating gate devices MR 1- to MR n- ; n in the reference array
  • the gates of the N-type floating gate devices MR 1+ to MR n+ are connected to the same fixed voltage V GS
  • the drains are connected to the same fixed voltage V DS
  • the sources are connected to the fixed voltage V S and connected to the positive input of the current subtraction circuit terminal
  • the gates of the n N-type floating gate devices MR 1- to MR n- in the reference array are connected to the same fixed voltage V GS
  • the drains are connected to the same fixed voltage V DS
  • the sources are connected and connected to the fixed voltage V S and connected to the negative input terminal of the current subtraction circuit
  • the output end of the subtraction circuit is connected to one end of the IV conversion resistance R1 and is connected to the reference terminal of the analog-to-digital converter ADC connected to the storage and calculation array through a voltage buffer; the IV conversion resistance R1 The other end is grounded;
  • the parameters of the IV conversion resistor R 1 are the same as those of the IV conversion resistor R 0 in the readout circuit of the storage and calculation array.
  • the neural network storage and calculation array is composed of n N-type floating gate devices M 1+ to M n+ and n N-type floating gate devices M 1- to M n- ; the readout of the storage and calculation array
  • the circuit includes a subtraction circuit, an IV conversion resistor R 0 and an analog-to-digital converter ADC;
  • the gates of n N-type floating gate devices M 1+ -M n+ are respectively connected to voltages V GS1 -V GSn , their drains are respectively connected to input voltages V DS1 -V DSn , and their sources are connected to The fixed voltage V S is connected to the positive input terminal of the current subtraction circuit;
  • the gates of n N-type floating gate devices M 1- ⁇ M n- are respectively connected to the voltage V GS1 ⁇ V GSn , and the drains are respectively connected to the voltage V DS1 ⁇ V DSn , the source phase is connected to the fixed voltage V S and connected to the negative input terminal of the current subtraction circuit;
  • the output terminal of the current subtraction circuit is connected to one end of the IV conversion resistor R0 and connected to the data input terminal of the analog-to-digital converter ADC ; the other end of the IV conversion resistor R0 is grounded ;
  • the current subtraction circuit is used to perform a subtraction operation on the input current at the positive input terminal and the input current at the negative input terminal.
  • the temperature compensation circuit in the present invention is as shown in Figure 3: it includes a reference array composed of two columns of P-type floating gate devices that store weights, a current subtraction circuit, and an IV conversion resistor R 1 .
  • Two columns of P-type floating gate devices used to store weights respectively include n P-type floating gate devices MR 1+ to MR n+ and n P-type floating gate devices MR 1- to MR n- ; n in the reference array
  • the gates of the P-type floating gate devices MR 1+ to MR n+ are connected to the same fixed voltage V GS , the drains are connected to the same fixed voltage V DS , the sources are connected to the fixed voltage V S and connected to the positive input of the current subtraction circuit terminal;
  • the n P-type floating gate devices MR 1- to MR n- in the reference array are connected to the same fixed voltage V GS at their gates, their drains are connected and connected to the same fixed voltage V DS , and their sources are connected and connected to a fixed voltage V S , and connected to the negative input terminal of the current subtraction circuit;
  • the output end of the subtraction circuit is connected to one end of the IV conversion resistor R1 and connected to the reference terminal of the analog-to-digital converter connected to the storage array through a voltage buffer ; the other end of the IV conversion resistor R1 One end is grounded;
  • the parameters of the IV conversion resistor R 1 are the same as those of the IV conversion resistor R 0 in the readout circuit of the storage and calculation array.
  • the neural network storage and calculation array is composed of n P-type floating gate devices M 1+ to M n+ and n P-type floating gate devices M 1- to M n- ; the readout of the storage and calculation array
  • the circuit includes a subtraction circuit, an IV conversion resistor R 0 and an analog-to-digital converter ADC;
  • the gates of n P-type floating gate devices M 1+ -M n+ are respectively connected to voltages V GS1 -V GSn , their drains are respectively connected to input voltages V DS1 -V DSn , and their sources are connected to The fixed voltage V S is connected to the positive input terminal of the current subtraction circuit;
  • the gates of n P-type floating gate devices M 1- ⁇ M n- are respectively connected to the voltage V GS1 ⁇ V GSn , and the drains are respectively connected to the voltage V DS1 ⁇ V DSn , the source phase is connected to the fixed voltage V S and connected to the negative input terminal of the current subtraction circuit;
  • the output terminal of the current subtraction circuit is connected to one end of the conversion resistance R0 and connected to the data input terminal of the analog-to-digital converter ADC ; the other end of the conversion resistance R0 is grounded ;
  • the current subtraction circuit is used to perform a subtraction operation on the input current at the positive input terminal and the input current at the negative input terminal.
  • the present invention also provides a temperature compensation method for neural network storage and calculation arrays, the method can be applied to the temperature compensation circuit of the storage and calculation array composed of N-type floating gate devices according to the present invention, and can also be applied to A temperature compensation circuit for a storage and calculation array composed of P-type floating gate devices, the method comprising:
  • Step 1 Determine the number and location of the reference arrays according to the temperature field distribution during the actual operation of the storage and calculation arrays;
  • Step 2 According to the reference voltage required by the analog-to - digital converter and the value of resistor R1 , calculate the gate voltage V GS and drain Voltage V DS and threshold voltage difference ⁇ V TH ;
  • Step 3 According to the calculation result of step 2, input gate voltage V GS and drain voltage V DS to the gate and drain of the device from the outside, and adjust the threshold voltage V TH of the device to obtain the calculated value in step 2 Threshold voltage difference ⁇ V TH .
  • Step 4 According to the operation of step 3, the reference array generates a reference current I REF ; and the reference current I REF is converted into a reference voltage V REF of the analog-to-digital converter through the resistor R 1 .
  • the reference array and the storage and calculation array are in the same temperature field, and the calculated current I REF of the reference array is the same as the calculated current I OUT of the storage and calculation array.
  • the change ratio of the analog-to-digital converter keeps the ratio of the input voltage to the reference voltage of the analog-to-digital converter unchanged before and after the temperature change, ensuring the correctness of the output data of the analog-to-digital converter.
  • the method uses a reference array to provide a reference voltage for all analog-to-digital converters connected to the storage and calculation arrays under the same temperature field. Further optionally, multiple reference arrays can also be selected according to the load of the current replication circuit.
  • the insertion position of the reference array is in the middle of the storage and calculation device array under the same temperature field.
  • the reference array generates a constant current to provide a constant reference voltage for the analog-to-digital converter when the array is working normally, and adjusts the gate voltage V GS when the array is not working, so that the reference array The device in is turned off to reduce power consumption.
  • the reference array in the same temperature field as the storage and calculation array provides a reference voltage for the analog-to-digital converter connected to the storage and calculation array, so as to realize the temperature compensation in the storage and calculation array. Compensation for the mobility temperature drift characteristics of N-type or P-type floating gate devices.
  • the reference array can determine whether it works by controlling the gate voltage of the floating gate device in the reference array. When the reference array is not working, no reference current I REF is generated.
  • the working principle of the ADC is to calculate the ratio of the input voltage to the reference voltage
  • the calculated current I REF and The current I OUT after the storage and calculation array operation has the same change ratio, so that the ratio of the input voltage to the reference voltage remains unchanged before and after the temperature change, ensuring the correctness of the ADC output results, and also ensuring the correctness of the data transfer between the arrays.
  • the output current of the array or the converted output voltage is not directly temperature compensated, but the reference array is used to provide a reference voltage for the ADC so that the digital output of the ADC is not subject to changes in external temperature, Therefore, the temperature drift characteristic of the mobility of the storage and calculation device is eliminated, and temperature compensation is realized.
  • I REF and I OUT since I REF and I OUT only need to have the same variation ratio, there is no limit to the position of the peripheral circuit of the array, and the current subtraction circuit and the peripheral circuit can be in different layers or at different temperatures from the device array. field.
  • one reference array can be used to simultaneously provide the reference voltage of the ADC for multiple storage and calculation arrays under the same temperature field, and the increase in area and power consumption caused by inserting the reference array can be minimized .
  • the temperature compensation method in the present invention is applicable to the 3D stacking technology in which the device array and the peripheral circuits of the array are placed on the same or different layers, and meets the requirement of large-scale development of storage and computing arrays.
  • the temperature compensation circuit and method in the present invention provide a reference voltage for the ADC by adding a reference array in the storage and calculation array, which can accurately Eliminate the temperature drift characteristics of device mobility; in terms of power consumption, the neural network storage and calculation array for temperature compensation using the temperature compensation circuit and method of the present invention does not need to increase a large number of operational amplifiers compared with the prior art, and The power consumption produced by a reference array and peripheral circuits is close to the power consumption of a common op amp, and the number of reference arrays selected by the temperature compensation circuit and method of the present invention is far less than the number of op amps required in the prior art, which can Significantly reduce power consumption; in terms of area, the area of the reference array device and peripheral circuits increased by the temperature compensation circuit of the present invention is almost negligible compared with the area of the storage and calculation array, and in this compensation method, except for the reference array, the remaining peripheral circuits Both can
  • Fig. 1 is the structural representation of the temperature compensation circuit based on N-type floating gate device provided by the present invention
  • FIG. 2 is a schematic structural diagram of a temperature compensation circuit based on a P-type floating gate device provided by the present invention
  • FIG. 3 is a schematic structural diagram of a temperature compensation circuit based on an N-type floating gate device provided by Embodiment 1 of the present invention.
  • FIG. 4 is a schematic structural diagram of a temperature compensation circuit based on a P-type floating gate device provided by Embodiment 2 of the present invention.
  • FIG. 5 is a schematic structural diagram of a test circuit provided by Embodiment 3 of the present invention.
  • Fig. 6 is a schematic diagram of the positional relationship when one reference array corresponds to multiple neural network storage and calculation arrays provided by the present invention
  • Fig. 7 is the simulation diagram of the results of the test circuit at 25°C in Embodiment 3 of the present invention.
  • Fig. 8 is a simulation diagram of the result of the test circuit at 0°C in Embodiment 3 of the present invention.
  • FIG. 9 is a simulation diagram of the test circuit results at 100° C. in Embodiment 3 of the present invention.
  • the temperature compensation circuit provided in this embodiment is used to perform temperature compensation on the neural network storage and calculation array composed of N-type floating gate devices.
  • the neural network storage and calculation array is composed of n N-type floating gate devices M 1+ to M n+ and n N-type floating gate devices M 1- to M n- , and the gates of the n N-type floating gate devices M 1+ to M n+ are respectively connected to voltages V GS1 to V GSn , and the drains are respectively Connect to the input voltage V DS1 ⁇ V DSn , the source phase is connected to the fixed voltage V S and connected to the positive input terminal of the current subtraction circuit; the gates of n N-type floating gate devices M 1- ⁇ M n- are respectively connected to the voltage V GS1 ⁇ V GSn , the drains are respectively connected to the voltages V DS1 ⁇ V DSn , the source is connected to the fixed voltage V S and connected to the negative input of the current subtraction circuit; the current subtraction circuit is used
  • the temperature compensation circuit includes: a reference array, a current subtraction circuit, and an IV conversion resistor R 1 ; wherein the reference array includes a positive and a negative column of floating gate devices; a column of floating gate devices includes n N-type floating gate devices MR 1+ ⁇ MR n+ , another column of floating gate devices includes n N-type floating gate devices MR 1 ⁇ ⁇ MR n ⁇ .
  • the gates of the n N-type floating gate devices MR 1+ to MR n+ in the reference array are connected to the same fixed voltage V GS_REF , the drains are connected to the same fixed voltage V DS_REF , and the sources are connected to the same fixed voltage V DS_REF .
  • DS_REF is connected to the positive input terminal of the current subtraction circuit; the gates of n N-type floating gate devices MR 1- to MR n- in the reference array are connected to the same fixed voltage V GS_REF , and the drains are connected to the same fixed voltage V DS_REF , the source phase is connected to the fixed voltage V S and connected to the negative input terminal of the current subtraction circuit; the output terminal of the subtraction circuit is connected to one end of the resistor R1 and connected to the analog-to-digital converter ADC through Buffer Reference terminal; the other end of the resistor R 1 is grounded; the resistor R 1 has the same parameters as the IV conversion resistor R 0 in the readout circuit of the storage and calculation array.
  • the readout circuit of the storage and calculation array includes a subtraction circuit, an IV conversion resistor R 0 and an analog-to-digital converter ADC;
  • This embodiment also provides a temperature compensation method for a neural network storage and calculation array, the method is used to implement a temperature compensation circuit for the storage and calculation array composed of N-type floating gate devices, and the method includes:
  • Step 1 Determine the number and location of the reference arrays according to the temperature field distribution during the actual operation of the storage and calculation arrays;
  • one reference array can be set in the temperature field. If the temperature field contains multiple storage and calculation arrays, the reference array can be set in all storage and calculation arrays. The middle position, as shown in Figure 6.
  • the storage and calculation array in the storage and calculation device is in multiple temperature fields, then set a reference array for each temperature field.
  • Step 2 According to the reference voltage required by the analog - to - digital converter and the value of resistor R1, calculate the gate voltage V GS_REF and drain Voltage V DS_REF and threshold voltage difference ⁇ V THN_REF ;
  • Step 3 According to the calculation result of Step 2, input gate voltage V GS_REF and drain voltage V DS_REF from the outside to the gate and drain of the device, and adjust the threshold voltage V TH of the device through programming and erasing operations, To obtain the threshold voltage difference ⁇ V THN_REF calculated in Step 2.
  • Step 4 According to the operation of step 3, the reference array generates a reference current I REF ; and the reference current I REF is converted into a reference voltage V REF of the analog-to-digital converter through the resistor R 1 .
  • the reference array After the reference array generates the reference current I REF , it is converted to the reference voltage V REF of the analog-to-digital converter through the resistor R 1 .
  • the reference array and the storage and calculation array are in the same temperature field, and the calculated current I REF of the reference array has the same variation ratio as the calculated current I OUT of the storage and calculation array. , so that the ratio of the input voltage of the analog-to-digital converter to the reference voltage remains unchanged before and after the temperature change, thereby ensuring the correctness of the output data of the analog-to-digital converter.
  • the gate voltage V GS_REF of all floating gate devices in the reference array is grounded, and at this time, the reference array has no current output.
  • the weight values stored in the two columns of floating gate devices in the storage and calculation array are ⁇ V THN1 ⁇ ⁇ V THNn
  • the weight values stored in the two columns of floating gate devices in the reference array are both ⁇ V THN_REF
  • the storage and calculation array is obtained by the subtraction circuit Corresponding output current I OUT :
  • ⁇ N is the mobility of all N-type floating gate devices
  • C ox is the capacitance of the gate oxide layer
  • W and L are the tube width and tube length of the floating gate device, respectively;
  • the reference array obtains the reference current I REF through the subtraction circuit:
  • the ADC output digital result formula does not contain any parameters with temperature characteristics, that is, the digital output of the ADC will not change with temperature, that is to say, the temperature compensation method in the present invention eliminates the N-type floating gate device. temperature drift characteristics.
  • the method uses a reference array to provide a reference voltage for the analog-to-digital converters connected to all storage and calculation arrays under the same temperature field, and multiple Reference array.
  • the insertion position of the reference array is in the middle of the storage and calculation device array under the same temperature field.
  • the reference array generates a constant current to provide a constant reference voltage for the analog-to-digital converter when the array is working normally, and adjusts the gate voltage V GS when the array is not working, so that the reference Devices in the array are turned off to reduce power consumption.
  • the reference array in the same temperature field as the storage and calculation array provides a reference voltage for the analog-to-digital converter connected to the storage and calculation array, so as to implement the temperature compensation in the storage and calculation array. Compensation of the mobility temperature drift characteristics of N-type floating gate devices.
  • the reference array can determine whether it works by controlling the gate voltage of the floating gate device in the reference array. When the reference array is not working, no reference current I REF is generated.
  • the working principle of the ADC is to calculate the ratio of the input voltage to the reference voltage
  • the current I REF after calculation of the reference array in the same temperature field It has the same change ratio as the current I OUT after the operation of the stored and calculated array, so that the ratio of the input voltage to the reference voltage remains unchanged before and after the temperature change, ensuring the correctness of the ADC output results, and also ensuring the correctness of the data transfer between the arrays .
  • the reference array is used to provide a reference voltage for the ADC so that the digital output of the ADC is not subject to changes in external temperature , thereby eliminating the temperature drift characteristic of the mobility of the storage device and realizing temperature compensation.
  • the temperature compensation circuit and method of this embodiment since only I REF and I OUT are required to have the same variation ratio, there is no restriction on the position of the peripheral circuit of the array, and the current subtraction circuit and the peripheral circuit can be in different layers or different from the device array. In the warm field.
  • This embodiment provides a temperature compensation circuit for a neural network storage and calculation array composed of P-type floating gate devices.
  • the neural network storage and calculation array is composed of n P-type floating gate devices M 1+ ⁇ M n+ and n P-type floating gate devices M 1- ⁇ M n- , and the gates of the n P-type floating gate devices M 1+ ⁇ M n+ are respectively connected to the voltage V GS1 ⁇ V GSn , and the drains are respectively connected to the input Voltage V DS1 ⁇ V DSn , the source phase is connected to the fixed voltage V S and connected to the positive input terminal of the current subtraction circuit; the gates of n P-type floating gate devices M 1- ⁇ M n- are respectively connected to the voltage V GS1 ⁇ V GSn , the drains are respectively connected to the voltage V DS1 ⁇ V DSn , the source is connected to the fixed voltage V S and connected to the negative input terminal of the current subtraction circuit; the current subtraction circuit is used
  • the temperature compensation circuit includes: a reference array, a current subtraction circuit, and an IV conversion resistor R 1 .
  • the reference array includes two columns of floating gate devices, one positive and one negative; one column of floating gate devices includes n P-type floating gate devices MR 1+ ⁇ MR n+ , and the other column of floating gate devices includes n P-type floating gate devices MR 1- ⁇ MR n- .
  • the gates of the n P-type floating gate devices MR 1+ to MR n+ in the reference array are connected to the same fixed voltage V GS_REF , the drains are connected to the same fixed voltage V DS_REF , the sources are connected to the fixed voltage V S , and connected to the The positive input terminal of the current subtraction circuit; the gates of n P-type floating gate devices MR 1- to MR n- in the reference array are connected to the same fixed voltage V GS_REF , the drains are connected to the same fixed voltage V DS_REF , and the sources are connected in parallel
  • the fixed voltage V S is connected to the negative input terminal of the current subtraction circuit; the output terminal of the subtraction circuit is connected to one end of the resistor R 1 and connected to the reference terminal of the ADC through Buffer; the resistor R 1 The other end is grounded; the resistance R 1 has the same parameters as the IV conversion resistance R 0 in the memory array readout circuit.
  • the present invention also provides a temperature compensation method for neural network storage and calculation arrays, the method can be applied to the temperature compensation circuit of the storage and calculation array composed of N-type floating gate devices according to the present invention, and can also be applied to A temperature compensation circuit for a storage and calculation array composed of P-type floating gate devices, the method comprising:
  • Step 1 Determine the number and location of the reference arrays according to the temperature field distribution during the actual operation of the storage and calculation arrays;
  • one reference array can be set in the temperature field. If the temperature field contains multiple storage and calculation arrays, the reference array can be set in all storage and calculation arrays. The middle position, as shown in Figure 6.
  • the storage and calculation array in the storage and calculation device is in multiple temperature fields, then set a reference array for each temperature field.
  • Step 2 According to the reference voltage required by the analog - to - digital converter and the value of resistor R1, calculate the gate voltage V GS_REF and drain Voltage V DS_REF and threshold voltage difference ⁇ V THP ;
  • Step 3 According to the calculation result of Step 2, input gate voltage V GS_REF and drain voltage V DS_REF from the outside to the gate and drain of the device, and adjust the threshold voltage V TH of the device through programming and erasing operations, To obtain the threshold voltage difference ⁇ V THP calculated in the second step.
  • Step 4 According to the operation of step 3, the reference array generates a reference current I REF ; and the reference current I REF is converted into a reference voltage V REF of the analog-to-digital converter through the resistor R 1 .
  • the reference array and the storage and calculation array are in the same temperature field, and the calculated current I REF of the reference array is the same as the calculated current I OUT of the storage and calculation array.
  • the change ratio of the analog-to-digital converter keeps the ratio of the input voltage to the reference voltage of the analog-to-digital converter unchanged before and after the temperature change, ensuring the correctness of the output data of the analog-to-digital converter.
  • the gate voltage V GS_REF of all floating gate devices in the reference array is connected to VDD, and at this time, the reference array has no current output.
  • the weight values stored in the two columns of floating gate devices in the storage and calculation array are ⁇ V THP1 ⁇ ⁇ V THPn
  • the weight values stored in the two columns of floating gate devices in the reference array are both ⁇ V THP_REF
  • the storage and calculation array is obtained by the subtraction circuit Output current:
  • ⁇ P is the mobility of all P-type floating gate devices
  • C ox is the capacitance of the gate oxide layer
  • W and L are the tube width and tube length of the floating gate device, respectively;
  • the output voltage is obtained after I-V conversion:
  • the positive and negative reference array output currents are subtracted to obtain the reference currents:
  • the reference voltage is obtained after I-V conversion:
  • the formula does not contain any parameters with temperature characteristics. It can be seen that the digital output of the ADC will not change with temperature, that is, the temperature compensation method in this embodiment eliminates the temperature drift characteristic of the P-type floating gate device.
  • the temperature compensation method according to this embodiment is essentially the same as that of Embodiment 1, and can achieve the same effect, and will not be repeated here.
  • a test circuit is built by using the same principle that the linear region characteristic of the MOS transistor and the linear region characteristic of the floating gate transistor are the same, and the circuit schematic diagram is as follows As shown in Figure 5, it is illustrated by taking the storage and calculation array including 1 NMOS transistor M 1+ and 1 NMOS transistor M 1- as an example; correspondingly, the reference array in the temperature compensation circuit includes 1 NMOS transistor MR 1+ and 1 NMOS transistor MR 1- ; the drain voltages of M 1+ , M 1- , MR 1+ and MR 1- are all V DS , the source voltages are all ground, and the source voltages are V GS1+ , V GS1- , V GS2+ and V GS2- .
  • V DS Adjusts the voltages V DS , V GS1+ , V GS1- , V GS2+ and V GS2- to ensure that all NMOS transistors in the circuit are in the linear region.
  • the width and length of all NMOS transistors are the same as W and L respectively, and the mobility is ⁇ .
  • NMOS transistors M 1+ and M 1- get the output current through the subtraction circuit in Represents the weight of the storage and calculation array, V DS represents the input data of the storage and calculation array, and then the ADC input voltage is obtained through a resistor with a resistance value of R
  • the NMOS tubes MR 1+ and MR 1- are obtained after a subtraction circuit and a resistor whose resistance is R in Represents the weight of the reference array, and V DS represents the input data of the reference array.
  • Method 2 Use a constant current source I DC and a resistor with a resistance value of R to generate the ADC reference voltage V REF , which is similar to the way in which the reference voltage is directly connected from the outside in the traditional method.
  • an ideal DAC is added after the ADC.
  • the range is the same as that of the ADC.
  • the purpose is to convert the digital output of the ADC into an analog output V OUT ', and compare it with V OUT . The closer the value of V OUT ' and V OUT is, the ADC The more independent the output of the temperature is, the beneficial effect of the temperature compensation method in the present invention can be shown more intuitively.
  • the virtuoso software of Cadence Company is used for transient simulation of analog circuits, and V OUT and V OUT ' are compared at 25°C (normal temperature), 0°C (low temperature), and 100°C (high temperature). Adjust the values of parameters R, (V GS2+ -V GS2- ), V DS and I DC to make the reference voltages generated by methods 1 and 2 equal, and take V OUT ' at this time as the theoretical output. These parameters are at other temperatures remains unchanged.
  • the horizontal axis is time (T), and the vertical axis is voltage value (V).
  • the marked point M15 in the figure is the input voltage of the ADC, and the marked point M16 is the reference generated by the reference array. Voltage, the marked point M13 is the output voltage of the DAC when the method 1 is adopted, and the marked point M14 is the output voltage of the DAC when the method 2 is adopted. It can be seen that at this time, due to the temperature drift characteristic of the mobility, the ADC input voltage V OUT has seriously The offset is 181.4mV.
  • the reference voltage follows the offset to 186.8mV, and the output voltage V OUT ' of the DAC is 144.1mV at this time, indicating that the output voltage of the ADC is not affected by the temperature change.
  • the output voltage V OUT ' of the DAC has been severely deformed to 180.5mV, indicating that the output voltage of the ADC has been affected by temperature changes and has shifted.
  • the simulation results are shown in Figure 8, the horizontal axis is time (T), the vertical axis is voltage value (V), the marked point M24 in the figure is the ADC input voltage, and the marked point M23 is the reference voltage generated by the reference array , the marked point M21 is the output voltage of the DAC when the method 1 is adopted, and the marked point M22 is the output voltage of the DAC when the method 2 is adopted.
  • T time
  • V voltage value
  • V the marked point M24 in the figure
  • the marked point M23 is the reference voltage generated by the reference array
  • the marked point M21 is the output voltage of the DAC when the method 1 is adopted
  • the marked point M22 is the output voltage of the DAC when the method 2 is adopted.
  • the temperature compensation circuit and temperature compensation method for the device temperature drift characteristics of the storage and calculation array proposed by the present invention have a very good compensation effect.
  • Part of the steps in the embodiments of the present invention can be realized by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disk or a hard disk.

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Abstract

本发明公开了一种用于神经网络存算阵列的温度补偿电路及方法，通过在存算阵列中稀疏插入的参考阵列为ADC提供参考电压，使ADC的输入电压与参考电压具有相同的温度系数，最后利用ADC进行模数转换，使ADC的数字输出不受外部温度的影响，保证神经网络的运算精度。根据本发明的温度补偿电路采用的参考阵列与存算阵列结构相同，参考阵列的插入密度与存算阵列所处温场有关，可使用一个参考阵列同时为多个存算阵列提供ADC的参考电压，最大程度地降低插入参考阵列带来的面积和功耗的增加。本发明中的温度补偿方法适用于器件阵列与阵列外围电路放在相同或不同层的3D堆叠技术，符合存算阵列朝大规模方向发展的需求。

Description

一种用于神经网络存算阵列的温度补偿电路及方法
[根据细则26改正27.06.2022]
技术领域
本发明涉及一种用于神经网络存算阵列的温度补偿电路及方法，属于集成电路技术领域。
背景技术
神经网络在图片分类、图像识别、自动驾驶等领域取得了重大发展，而基于浮栅类非易失性器件的存算一体技术利用器件阵列将数据的存储和运算进行融合，适用于神经网络这种大规模数据并行运算的应用场景。浮栅类非易失性器件组成的存算阵列在工作时，可通过改变存算阵列中浮栅器件的阈值电压来实现权重的存储，最后通过存算阵列中均工作在线性区的两列浮栅器件输出电流的减法实现输入数据与权重间的乘累加运算，两列浮栅器件的输出电流经过电流减法电路之后的电流差值的大小代表了运算的结果。
存算阵列的工作过程如下，在阵列完成乘累加运算并作电流减法后，输出电流为：
Figure PCTCN2022098349-appb-000001
其中，μ是浮栅器件的迁移率，C ox是单位面积的栅氧化层电容，W、L是浮栅器件的宽、长，ΔV THi是阈值电压差，n是权重和输入数据的数量，
Figure PCTCN2022098349-appb-000002
是第i个权重，V DSi是第i个输入数据通过DAC(数模转换器)转换后得到的模拟电压信号。
I OUT通过I-V(电流-电压)转换后得到输出电压：
Figure PCTCN2022098349-appb-000003
其中，R是I-V转换电阻，最后V OUT通过外部参考电源V REF、电压缓冲器(Buffer)以及模数转换器(ADC)组成的模数转换系统转换为输出数据并进行下一步传输。
在存算阵列的工作过程中，阵列的输出电流值决定了神经网络的运算结果，若输出电流发生偏移，那么ADC的输出结果也将出现偏差，这种偏差经过多层传递放大后，会降低整个神经网络的工作精度。在前述I OUT表达式中，ΔV THi自身已经消除了器件阈值电压的线性温度特性对阵列输出电流的影响，但是器件迁移率μ是随温度变化的，迁移率是指单位电场强度下所产生的载流子(电子或空穴)平均漂移速度，而在不同的温度下，载流子的漂移速度是会发生变化的，这导致μ在0℃～100℃范围内可以发生近50％的变化(参考“蒋明峰,方毅,黄鲁.一种基于闪存的温度补偿型向量矩阵乘法器[J].微电子学,2020,50(3):344-348.”)，意味着阵列输出电流I OUT在最差情况下也会发生近50％的偏移，这对神经网络的工作精度造 成了不可忽视的影响。因此，为了使神经网络能够适应环境温度的变化，需要针对存算器件迁移率温漂特性进行温度补偿。
上述蒋明峰等的论文中提出了一种温度补偿电路，该电路利用运放、浮栅器件和电阻构成一个电导负载在输出端直接得到一个不受温度影响的输出电压V OUT。但该方法中大量地使用运算放大器额外增加了神经网络的功耗，并且运放的稳态建立时间也制约了神经网络的运算速度；同时，随着存算阵列规模的不断扩大，出现了将器件阵列与阵列外围电路放在不同层以满足神经网络朝大规模和高算力方向发展需求的3D堆叠技术，但是该论文中的补偿方法要求补偿电路和存算阵列需处在同一个工艺层中，实际应用中并不能满足这个需求。
美国加州大学圣芭芭拉分校的研究者也提出了一种温度补偿方法，利用器件自身的亚阈值电流特性，避免了迁移率和阈值电压受温度变化而给乘法器带来的影响，并且利用两列电流的减法消除阈值电压的温度特性(可参考X.Guo et al,"Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells,"2017 IEEE Custom Integrated Circuits Conference(CICC),Austin,TX,USA,2017,pp.1-4.)；但是，该论文中利用器件自身的亚阈值特性进行温度补偿的方法会造成阵列输出电流极低，甚至只有皮安(10 -12A)量级，极大地降低了神经网络的运算速度，并且极易受到噪声的影响，进而降低了神经网络的运算精度。
发明内容
针对现有技术的上述不足，本发明提供了一种用于神经网络存算阵列的温度补偿电路及方法，该方法针对浮栅器件迁移率温漂特性进行温度补偿，不直接针对存算阵列的输出电流和转换后的电压进行温度补偿，而是对ADC的数字输出进行补偿。本发明通过在存算阵列中稀疏插入的参考阵列为ADC提供参考电压，使ADC的输入电压与参考电压具有相同的温度系数，最后利用ADC进行模数转换，使ADC的数字输出不受外部温度的影响，保证每一层网络的运算精度。
根据本发明的温度补偿电路采用的参考阵列与存算阵列结构相同，每个参考阵列中包括两列浮栅器件来完成乘加运算。参考阵列的插入密度与存算阵列所处温场有关，可使用一个参考阵列同时为多个存算阵列提供ADC的参考电压，最大程度地降低插入参考阵列带来的面积和功耗的增加。本发明中的温度补偿方法适用于器件阵列与阵列外围电路放在相同或不同层的3D堆叠技术，符合存算阵列朝大规模方向发展的需求。
对于由N型浮栅器件组成的神经网络存算阵列，本发明中的温度补偿电路如图2所示：其中包括两列存储权重的N型浮栅器件作为参考阵列，电流减法电路，I-V转换电阻R 1。
两列用于存储权重的N型浮栅器件分别包括n个N型浮栅器件MR 1+～MR n+和n个N型浮栅器件MR 1-～MR n-；所述参考阵列中n个N型浮栅器件MR 1+～MR n+的栅极接同一固定电压V GS，漏极接同一固定电压V DS，源极相连并接固定电压V S并且接入所述电流减法电路的正输入端；所述参考阵列中n个N型浮栅器件MR 1-～MR n-的栅极接同一固定电压V GS，漏极接同一固定电压V DS，源极相连并接固定电压V S并且接入所述电流减法电路的负输入端；
所述减法电路的输出端与所述I-V转换电阻R 1的一端相连并通过电压缓冲器接入所述存算阵列所连接的模数转换器ADC的参考端；所述I-V转换电阻R 1的另一端接地；
所述I-V转换电阻R 1与所述存算阵列的读出电路中的I-V转换电阻R 0参数相同。
可选的，所述神经网络存算阵列由n个N型浮栅器件M 1+～M n+和n个N型浮栅器件M 1-～M n-组成；所述存算阵列的读出电路包括一个减法电路、一个I-V转换电阻R 0和模数转换器ADC；
所述神经网络存算阵列中，n个N型浮栅器件M 1+～M n+的栅极分别接电压V GS1～V GSn，漏极分别接输入电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的正输入端；n个N型浮栅器件M 1-～M n-的栅极分别接电压V GS1～V GSn，漏极分别接电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的负输入端；
所述电流减法电路的输出端与I-V转换电阻R 0的一端相连并接入模数转换器ADC的数据输入端；所述I-V转换电阻R 0的另一端接地；
所述电流减法电路用于对正输入端的输入电流和负输入端的输入电流执行减法操作。
对于由P型浮栅器件组成的神经网络存算阵列，本发明中的温度补偿电路如图3所示：包括由两列存储权重的P型浮栅器件组成的参考阵列，电流减法电路，I-V转换电阻R 1。
两列用于存储权重的P型浮栅器件分别包括n个P型浮栅器件MR 1+～MR n+和n个P型浮栅器件MR 1-～MR n-；所述参考阵列中n个P型浮栅器件MR 1+～MR n+的栅极接同一固定电压V GS，漏极接同一固定电压V DS，源极相连并接固定电压V S并且接入所述电流减法电路的正输入端；所述参考阵列中n个P型浮栅器件MR 1-～MR n-栅极接同一固定电压V GS，漏极相连并接同一固定电压V DS，源极相连并接固定电压V S，并且接入所述电流减法电路的负输入端；
所述减法电路的输出端与所述I-V转换电阻R 1的一端相连并通过电压缓冲器接入所述存算阵列所连接的模数转换器的参考端；所述I-V转换电阻R 1的另一端接地；
所述I-V转换电阻R 1与所述存算阵列的读出电路中的I-V转换电阻R 0参数相同。
可选的，所述神经网络存算阵列由n个P型浮栅器件M 1+～M n+和n个P型浮栅器件M 1-～M n-组成；所述存算阵列的读出电路包括一个减法电路、一个I-V转换电阻R 0和模数转换 器ADC；
所述神经网络存算阵列中，n个P型浮栅器件M 1+～M n+的栅极分别接电压V GS1～V GSn，漏极分别接输入电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的正输入端；n个P型浮栅器件M 1-～M n-的栅极分别接电压V GS1～V GSn，漏极分别接电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的负输入端；
所述电流减法电路的输出端与转换电阻R 0的一端相连并接入模数转换器ADC的数据输入端；所述转换电阻R 0的另一端接地；
所述电流减法电路用于对正输入端的输入电流和负输入端的输入电流执行减法操作。
本发明还提供一种用于神经网络存算阵列的温度补偿方法，所述方法能够应用于根据本发明所述的由N型浮栅器件组成的存算阵列的温度补偿电路，也能够应用于由P型浮栅器件组成的存算阵列的温度补偿电路，所述方法包括：
步骤一：根据存算阵列实际工作时的温场分布情况，确定参考阵列数量及位置；
步骤二：根据模数转换器所需参考电压和电阻R 1的值，计算出参考阵列中浮栅器件MR 1+～MR n+和MR 1-～MR n-的栅极电压V GS、漏极电压V DS以及阈值电压差ΔV TH的大小；
步骤三：根据步骤二的计算结果，将栅极电压V GS、漏极电压V DS从外部输入到器件的栅极和漏极，并调节器件的阈值电压V TH，以得到步骤二计算所得的阈值电压差ΔV TH。
步骤四：根据步骤三的操作，所述参考阵列产生参考电流I REF；并且所述参考电流I REF通过电阻R 1转换为模数转换器的参考电压V REF。
根据本发明的温度补偿方法，可选地，所述参考阵列与存算阵列处于同一温场，所述参考阵列经运算后的电流I REF与所述存算阵列运算后的电流I OUT具有相同的变化比例，使得模数转换器在温度变化前后的输入电压与参考电压的比值保持不变，保证模数转换器输出数据的正确性。
根据本发明的温度补偿方法，可选地，所述方法采用一个参考阵列为处于同一温场下所有的存算阵列所连接的模数转换器提供参考电压。进一步可选地，也能够根据电流复制电路的负载选用多个参考阵列。
根据本发明的温度补偿方法，可选地，所述参考阵列的插入位置处于同一温场下的存算器件阵列的中间位置。
根据本发明的温度补偿方法，可选地，所述参考阵列在阵列正常工作时产生恒定电流为模数转换器提供恒定参考电压，在阵列不工作时，调节栅极电压V GS，使参考阵列中的器件关闭，以降低功耗。
根据本发明的温度补偿方法，可选地，通过与存算阵列处于同一温场的参考阵列为所述存算阵列所连接的模数转换器提供参考电压，实现对所述存算阵列中的N型或P型浮栅器件迁移率温漂特性的补偿。
根据本发明的温度补偿电路及方法，可选地，参考阵列可以通过控制参考阵列中浮栅器件的栅极电压来决定其是否工作，参考阵列不工作时，不会产生参考电流I REF。
根据本发明的温度补偿电路及方法，由于ADC的工作原理是计算输入电压与参考电压的比值，而本发明的温度补偿电路及方法中，处于同一温场的参考阵列运算后的电流I REF和存算阵列运算后的电流I OUT具有相同的变化比例，使得温度变化前后输入电压与参考电压的比值保持不变，保证ADC输出结果的正确性，也就保证了阵列间数据传递的正确性。
根据本发明的温度补偿电路及方法，并未对阵列的输出电流或转换后的输出电压直接进行温度补偿，而是利用参考阵列为ADC提供参考电压使ADC的数字输出不受外界温度的变化，从而消除了存算器件迁移率的温漂特性，实现温度补偿。
根据本发明的温度补偿电路及方法，由于只需要I REF和I OUT具有相同的变化比例，因此对阵列外围电路的位置没有限制，电流减法电路及外围电路能够与器件阵列处于不同层或者不同温场中。
本发明有益效果是：
根据本发明的温度补偿电路及方法，能够使用一个参考阵列同时为处于同一温场下的多个存算阵列提供ADC的参考电压，最大程度地降低插入参考阵列带来的面积和功耗的增加。本发明中的温度补偿方法适用于器件阵列与阵列外围电路放在相同或不同层的3D堆叠技术，符合存算阵列朝大规模方向发展的需求。
根据本发明的温度补偿电路及方法，在补偿精度方面，与现有技术相比，本发明中的温度补偿电路及方法通过在存算阵列中增加参考阵列的方式为ADC提供参考电压，能够精确地消除器件迁移率的温度漂移特性；在功耗方面，采用本发明的温度补偿电路及方法进行温度补偿的神经网络存算阵列，与现有技术相比，不需要增加大量的运放，且一个参考阵列及外围电路所产生的功耗与一个普通运放的功耗相近，而本发明的温度补偿电路及方法所选用的参考阵列的数量远小于现有技术所需运放的数量，能够大幅度降低功耗；在面积方面，本发明的温度补偿电路增加的参考阵列器件和外围电路面积与存算阵列面积相比几乎可以忽略不计，并且该补偿方法中除了参考阵列以外，剩余外围电路均能够与存算阵列处于不同的工艺层，也能够节省面积，符合存算一体神经网络朝大规模、高算力、高能效比方向发展的趋 势。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的基于N型浮栅器件的温度补偿电路的结构示意图；
图2为本发明提供的基于P型浮栅器件的温度补偿电路的结构示意图；
图3为本发明的实施例一提供的基于N型浮栅器件的温度补偿电路的结构示意图；
图4为本发明的实施例二提供的基于P型浮栅器件的温度补偿电路的结构示意图；
图5是本发明的实施例三提供的测试电路的结构示意图；
图6是本发明提供的一个参考阵列对应多个神经网络存算阵列时的位置关系示意图；
图7是本发明的实施例三中25℃时测试电路的结果仿真图；
图8是本发明的实施例三中0℃时测试电路的结果仿真图；
图9是本发明的实施例三中100℃时测试电路的结果仿真图。
具体实施方式
下面结合本发明实施方式示意图，对本发明的实施方式进行清楚、完整地描述，显然，所描述的实施方式只是本发明的一部分实施方式，基于本发明中的实施方式，本领域其他人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本发明保护的范围。
实施例一：
本实施例提供的温度补偿电路用于对由N型浮栅器件组成的神经网络存算阵列进行温度补偿，如图3所示，所述神经网络存算阵列由n个N型浮栅器件M 1+～M n+和n个N型浮栅器件M 1-～M n-，且n个N型浮栅器件M 1+～M n+的栅极分别接电压V GS1～V GSn，漏极分别接输入电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的正输入端；n个N型浮栅器件M 1-～M n-的栅极分别接电压V GS1～V GSn，漏极分别接电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的负输入端；所述电流减法电路用于对正输入端的输入电流和负输入端的输入电流执行减法操作；所述电流减法电路的输出端与转换电阻R 0的一端相连并接入模数转换器ADC的输入端；所述转换电阻R 0的另一端接地。
所述温度补偿电路包括：参考阵列，电流减法电路，I-V转换电阻R 1；其中参考阵列包 含一正一负两列浮栅器件；一列浮栅器件包括n个N型浮栅器件MR 1+～MR n+，另一列浮栅器件包括n个N型浮栅器件MR 1-～MR n-。
如图3所示，所述参考阵列中n个N型浮栅器件MR 1+～MR n+的栅极接同一固定电压V GS_REF，漏极接同一固定电压V DS_REF，源极相连接固定电压V DS_REF并且接入所述电流减法电路的正输入端；所述参考阵列中n个N型浮栅器件MR 1-～MR n-的栅极接同一固定电压V GS_REF，漏极接同一固定电压V DS_REF，源极相连接固定电压V S并且接入所述电流减法电路的负输入端；所述减法电路的输出端与所述电阻R 1的一端相连并通过Buffer接入模数转换器ADC的参考端；所述电阻R 1的另一端接地；所述电阻R 1与存算阵列的读出电路中的I-V转换电阻R 0参数相同。
所述存算阵列的读出电路包括一个减法电路、一个I-V转换电阻R 0和模数转换器ADC；
本实施例还提供一种用于神经网络存算阵列的温度补偿方法，所述方法用于实现对上述由N型浮栅器件组成的存算阵列的温度补偿电路，所述方法包括：
步骤一：根据存算阵列实际工作时的温场分布情况，确定参考阵列数量及位置；
若存算设备中的存算阵列处于同一个温场，那么该温场中设置一个参考阵列即可，若该温场中包含多个存算阵列，可将该参考阵列设置在所有存算阵列的中间位置，如图6所示。
若存算设备中的存算阵列处于多个温场中，那么每个温场设置一个参考阵列。
步骤二：根据模数转换器所需参考电压和电阻R 1的值，计算出参考阵列中浮栅器件MR 1+～MR n+和MR 1-～MR n-的栅极电压V GS_REF、漏极电压V DS_REF以及阈值电压差ΔV THN_REF的大小；
步骤三：根据步骤二的计算结果，将栅极电压V GS_REF、漏极电压V DS_REF从外部输入到器件的栅极和漏极，并通过编程、擦除操作，调节器件的阈值电压V TH，以得到步骤二计算所得的阈值电压差ΔV THN_REF。
步骤四：根据步骤三的操作，所述参考阵列产生参考电流I REF；并且所述参考电流I REF通过电阻R 1转换为模数转换器的参考电压V REF。
在所述参考阵列产生参考电流I REF后，通过电阻R 1转换为模数转换器的参考电压V REF。
根据本实施例的温度补偿方法，所述参考阵列与存算阵列处于同一温场，所述参考阵列经运算后的电流I REF与所述存算阵列运算后的电流I OUT具有相同的变化比例，使得模数转换器在温度变化前后的输入电压与参考电压的比值保持不变，保证模数转换器输出数据的正确性。
本实施例的温度补偿电路具体工作过程如下：
在非读出模式下，参考阵列中所有浮栅器件栅极电压V GS_REF接地，此时，参考阵列无电流输出。
在读出模式下，存算阵列中两列浮栅器件存储的权重值为ΔV THN1～ΔV THNn，参考阵列中两列浮栅器件存储的权重值均为ΔV THN_REF，存算阵列通过减法电路得到对应的输出电流I OUT：
Figure PCTCN2022098349-appb-000004
其中，μ N为所有N型浮栅器件的迁移率，C ox为栅氧化层电容，W、L分别为浮栅器件的管宽和管长；
经过I-V转换后得到对应的输出电压V OUT：
Figure PCTCN2022098349-appb-000005
参考阵列通过减法电路得到参考电流I REF：
Figure PCTCN2022098349-appb-000006
经过I-V转换后得到参考电压V REF：
Figure PCTCN2022098349-appb-000007
假设ADC为m位ADC，那么ADC输出数字结果：
CODE＝(V OUT/V REF)×(2 m-1)
＝[(ΔV THN1V DS1+ΔV THN2V DS2+···ΔV THNnV DSn)/n(ΔV THN_REFV DS_REF)]×(2 m-1)，
可见，ADC输出数字结果式中不含有任何具有温度特性的参数，也即，ADC的数字输出不会随温度变化而变化，也就是说本发明中的温度补偿方法消除了N型浮栅器件的温度漂移特性。
根据本实施例的温度补偿方法，所述方法采用一个参考阵列为处于同一温场下所有的存算阵列所连接的模数转换器提供参考电压，也能够根据电流负载电路的负载情况选用多个参考阵列。
根据本实施例的温度补偿方法，参考阵列的插入位置处于同一温场下的存算器件阵列的中间位置。
根据本实施例的温度补偿方法，可选地，所述参考阵列在阵列正常工作时产生恒定电流为模数转换器提供恒定参考电压，在阵列不工作时，调节栅极电压V GS，使参考阵列中的器件关闭，以降低功耗。
根据本实施例的温度补偿方法，可选地，通过与存算阵列处于同一温场的参考阵列为所述存算阵列所连接的模数转换器提供参考电压，实现对所述存算阵列中的N型浮栅器件迁移率温漂特性的补偿。
根据本实施例的温度补偿电路及方法，参考阵列可以通过控制参考阵列中浮栅器件的栅极电压来决定其是否工作，参考阵列不工作时，不会产生参考电流I REF。
根据本实施例的温度补偿电路及方法，由于ADC的工作原理是计算输入电压与参考电压的比值，而本发明的温度补偿电路及方法中，处于同一温场的参考阵列运算后的电流I REF和存算阵列运算后的电流I OUT具有相同的变化比例，使得温度变化前后输入电压与参考电压的比值保持不变，保证ADC输出结果的正确性，也就保证了阵列间数据传递的正确性。
根据本实施例的温度补偿电路及方法，并未对阵列的输出电流或转换后的输出电压直接进行温度补偿，而是利用参考阵列为ADC提供参考电压使ADC的数字输出不受外界温度的变化，从而消除了存算器件迁移率的温漂特性，实现温度补偿。
根据本实施例的温度补偿电路及方法，由于只需要I REF和I OUT具有相同的变化比例，因此对阵列外围电路的位置没有限制，电流减法电路及外围电路能够与器件阵列处于不同层或者不同温场中。
实施例二
本实施例提供一种用于由P型浮栅器件组成的神经网络存算阵列的温度补偿电路，如图4所示，所述神经网络存算阵列由n个P型浮栅器件M 1+～M n+和n个P型浮栅器件M 1-～M n-，且n个P型浮栅器件M 1+～M n+的栅极分别接电压V GS1～V GSn，漏极分别接输入电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的正输入端；n个P型浮栅器件M 1-～M n-的栅极分别接电压V GS1～V GSn，漏极分别接电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的负输入端；所述电流减法电路用于对正输入端的输入电流和负输入端的输入电流执行减法操作；所述电流减法电路的输出端与转换电阻R 0的一端相连并接入模数转换器ADC的输入端；所述转换电阻R 0的另一端接地。
该温度补偿电路包括：参考阵列，电流减法电路，I-V转换电阻R 1。其中参考阵列包含一正一负两列浮栅器件；一列浮栅器件包括n个P型浮栅器件MR 1+～MR n+，另一列浮栅器件包括n个P型浮栅器件MR 1-～MR n-。
所述参考阵列中n个P型浮栅器件MR 1+～MR n+栅极接同一固定电压V GS_REF，漏极接同一固定电压V DS_REF，源极相连接固定电压V S，并且接入所述电流减法电路正输入端；所述参考阵列中n个P型浮栅器件MR 1-～MR n-栅极接同一固定电压V GS_REF，漏极相连接同一固定电压V DS_REF，源极相连并接固定电压V S，并且接入所述电流减法电路的负输入端；所述减法电路的输出端与所述电阻R 1的一端相连并通过Buffer接入ADC的参考端；所述电阻R 1 的另一端接地；所述电阻R 1与存算阵列读出电路中的I-V转换电阻R 0参数相同。
本发明还提供一种用于神经网络存算阵列的温度补偿方法，所述方法能够应用于根据本发明所述的由N型浮栅器件组成的存算阵列的温度补偿电路，也能够应用于由P型浮栅器件组成的存算阵列的温度补偿电路，所述方法包括：
步骤一：根据存算阵列实际工作时的温场分布情况，确定参考阵列数量及位置；
若存算设备中的存算阵列处于同一个温场，那么该温场中设置一个参考阵列即可，若该温场中包含多个存算阵列，可将该参考阵列设置在所有存算阵列的中间位置，如图6所示。
若存算设备中的存算阵列处于多个温场中，那么每个温场设置一个参考阵列。
步骤二：根据模数转换器所需参考电压和电阻R 1的值，计算出参考阵列中浮栅器件MR 1+～MR n+和MR 1-～MR n-的栅极电压V GS_REF、漏极电压V DS_REF以及阈值电压差ΔV THP的大小；
步骤三：根据步骤二的计算结果，将栅极电压V GS_REF、漏极电压V DS_REF从外部输入到器件的栅极和漏极，并通过编程、擦除操作，调节器件的阈值电压V TH，以得到步骤二计算所得的阈值电压差ΔV THP。
步骤四：根据步骤三的操作，所述参考阵列产生参考电流I REF；并且所述参考电流I REF通过电阻R 1转换为模数转换器的参考电压V REF。
根据本发明的温度补偿方法，可选地，所述参考阵列与存算阵列处于同一温场，所述参考阵列经运算后的电流I REF与所述存算阵列运算后的电流I OUT具有相同的变化比例，使得模数转换器在温度变化前后的输入电压与参考电压的比值保持不变，保证模数转换器输出数据的正确性。
在非读出模式下，参考阵列中所有浮栅器件栅极电压V GS_REF接VDD，此时，参考阵列无电流输出。
在读出模式下，存算阵列中两列浮栅器件存储的权重值为ΔV THP1～ΔV THPn，参考阵列中两列浮栅器件存储的权重值均为ΔV THP_REF，存算阵列通过减法电路得到输出电流：
Figure PCTCN2022098349-appb-000008
其中，μ P为所有P型浮栅器件的迁移率，C ox为栅氧化层电容，W、L分别为浮栅器件的管宽和管长；
经过I-V转换后得到输出电压：
Figure PCTCN2022098349-appb-000009
正负参考阵列输出电流经过减法后得到参考电流：
Figure PCTCN2022098349-appb-000010
经过I-V转换后得到参考电压：
Figure PCTCN2022098349-appb-000011
假设ADC为m位ADC，那么ADC输出数字结果：
CODE＝V OUT/V REF×(2 m-1)
＝[(ΔV THN1V DS1+ΔV THN2V DS2+···+ΔV THNnV DSn)/n(ΔV THP_REFV DS_REF)]×(2 m-1)，
式中不含有任何具有温度特性的参数，可见，ADC的数字输出不会随温度变化而变化，即本实施例中的温度补偿方法消除了P型浮栅器件的温度漂移特性。
根据本实施例的温度补偿方法与实施例一本质相同，并且能够取得同样的效果，此处不再赘述。
实施例三
为了证明本发明针对存算阵列中的浮栅器件的温漂特性的补偿方法的有益效果，利用MOS管的线性区特性和浮栅管线性区特性相同的原理，搭建了测试电路，电路示意图如图5所示，以存算阵列包含1个NMOS管M 1+和1个NMOS管M 1-为例进行说明；对应的，温度补偿电路中参考阵列包含1个NMOS管MR 1+和1个NMOS管MR 1-；M 1+、M 1-、MR 1+和MR 1-的漏极电压均为V DS，源极电压均为地，源极电压分别为V GS1+、V GS1-、V GS2+和V GS2-。调整电压V DS、V GS1+、V GS1-、V GS2+和V GS2-的值，保证电路中所有NMOS管均处于线性区，所有NMOS管宽、长相同分别为W、L，迁移率为μ。
NMOS管M 1+和M 1-通过减法电路得到输出电流
Figure PCTCN2022098349-appb-000012
其中
Figure PCTCN2022098349-appb-000013
代表存算阵列的权重，V DS代表存算阵列的输入数据，然后通过阻值为R的电阻得到ADC输入电压
Figure PCTCN2022098349-appb-000014
在本实施例中，ADC的参考电压V REF有两种产生方式，方法①：
采用本发明中产生参考电压V REF的方法，NMOS管MR 1+和MR 1-通过减法电路和阻值为R的电阻后得到
Figure PCTCN2022098349-appb-000015
其中
Figure PCTCN2022098349-appb-000016
代表参考阵列的权重，V DS代表参考阵列的输入数据。
方法②：利用恒流源I DC和阻值为R的电阻产生ADC参考电压V REF，类似于传统方法中直接从外部接入参考电压的方式。最后在ADC后加入一个理想的DAC，量程与ADC相同，目的是将ADC的数字输出转换为模拟输出V OUT'，并与V OUT进行比较，V OUT'与V OUT的 值越接近，说明ADC的输出越不受温度影响，以此更加直观地表现出本发明中温度补偿方法的有益效果。
本实施例通过Cadence公司的virtuoso软件进行模拟电路瞬态仿真，分别在25℃(常温)，0℃(低温)，100℃(高温)状态下对V OUT、V OUT'进行比较，在25℃下调节参数R、(V GS2+-V GS2-)、V DS和I DC的值，使方法①、②产生的参考电压相等，并将此时的V OUT'作为理论输出，这些参数在其他温度下保持不变。
在25℃时，仿真结果如图6所示，横轴为时间(T)，纵轴为电压值(V)，图中标记点M11为ADC输入电压V OUT＝145.3mV，标记点M12为参考阵列产生的参考电压，标记点M9为采用方法①时DAC的输出，标记点M10为采用方法②时DAC的输出，可以看出此时采用方法①和采用方法②时DAC的输出V OUT'相等均为144.1mV。
在0℃时，仿真结果如图7所示，横轴为时间(T)，纵轴为电压值(V)，图中标记点M15为ADC的输入电压，标记点M16为参考阵列产生的参考电压，标记点M13为采用方法①时DAC的输出电压，标记点M14为采用方法②时DAC的输出电压，可以看出，此时，由于迁移率的温度漂移特性，ADC输入电压V OUT已严重偏移为181.4mV。采用方法①时参考电压跟随偏移到186.8mV，此时DAC的输出电压V OUT'为144.1mV，说明ADC的输出电压并没有受到温度变化的影响。采用方法②时DAC的输出电压V OUT'已严重变形为180.5mV，说明ADC的输出电压受到了温度变化的影响，发生了偏移。
在100℃时，仿真结果如图8所示，横轴为时间(T)，纵轴为电压值(V)，图中标记点M24为ADC输入电压，标记点M23为参考阵列产生的参考电压，标记点M21为采用方法①时DAC的输出电压，标记点M22为采用方法②时DAC的输出电压，可以看出，此时，由于迁移率的温度漂移特性，ADC输入电压V OUT已严重偏移为75.8mV。采用方法①时参考电压跟随偏移到78.1mV，此时DAC的输出电压V OUT'为125.4mV。采用方法②时DAC的输出电压V OUT'严重偏移为73.8mV，说明采用参考阵列产生参考电压的方法有效地补偿了迁移率的温度漂移特性。
对仿真结果进行分析：未进行温度补偿前，在0℃到100℃之间，ADC数字输出的温度系数高达0.6％/℃，在进行温度补偿后，在0℃到100℃之间，ADC输出的温度系数低至0.13％/℃。
综上可以看出，本发明提出的针对存算阵列的器件温漂特性的温度补偿电路及温度补偿方法具有非常好的补偿效果。
本发明实施例中的部分步骤，可以利用软件实现，相应的软件程序可以存储在可读取的存储介质中，如光盘或硬盘等。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内

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  1. 一种用于神经网络存算阵列的温度补偿电路，其特征在于，所述温度补偿电路用于对由N型浮栅器件组成的神经网络存算阵列进行温度补偿，所述温度补偿电路包括两列用于存储权重的N型浮栅器件作为参考阵列、电流减法电路、I-V转换电阻R 1；
    两列用于存储权重的N型浮栅器件分别包括n个N型浮栅器件MR 1+～MR n+和n个N型浮栅器件MR 1-～MR n-；所述参考阵列中n个N型浮栅器件MR 1+～MR n+的栅极接同一固定电压V GS，漏极接同一固定电压V DS，源极相连并接固定电压V S并且接入所述电流减法电路的正输入端；所述参考阵列中n个N型浮栅器件MR 1-～MR n-的栅极接同一固定电压V GS，漏极接同一固定电压V DS，源极相连并接固定电压V S并且接入所述电流减法电路的负输入端；
    所述减法电路的输出端与所述I-V转换电阻R 1的一端相连并通过电压缓冲器接入所述存算阵列所连接的模数转换器ADC的参考端；所述I-V转换电阻R 1的另一端接地；
    所述I-V转换电阻R 1与所述存算阵列的读出电路中的I-V转换电阻R 0参数相同。
  2. 根据权利要求1所述的温度补偿电路，其特征在于，所述神经网络存算阵列由n个N型浮栅器件M 1+～M n+和n个N型浮栅器件M 1-～M n-组成；所述存算阵列的读出电路包括一个减法电路、一个I-V转换电阻R 0和模数转换器ADC；
    所述神经网络存算阵列中，n个N型浮栅器件M 1+～M n+的栅极分别接电压V GS1～V GSn，漏极分别接输入电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的正输入端；n个N型浮栅器件M 1-～M n-的栅极分别接电压V GS1～V GSn，漏极分别接电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的负输入端；
    所述电流减法电路的输出端与I-V转换电阻R 0的一端相连并接入模数转换器ADC的数据输入端；所述I-V转换电阻R 0的另一端接地；
    所述电流减法电路用于对正输入端的输入电流和负输入端的输入电流执行减法操作。
  3. 一种用于神经网络存算阵列的温度补偿电路，其特征在于，所述温度补偿电路用于对由P型浮栅器件组成的神经网络存算阵列进行温度补偿，所述温度补偿电路包括两列用于存储权重的P型浮栅器件组成的参考阵列、电流减法电路、I-V转换电阻R 1；
    两列用于存储权重的P型浮栅器件分别包括n个P型浮栅器件MR 1+～MR n+和n个P型浮栅器件MR 1-～MR n-；所述参考阵列中n个P型浮栅器件MR 1+～MR n+的栅极接同一固定电压V GS，漏极接同一固定电压V DS，源极相连并接固定电压V S并且接入所述电流减法电路的正输入端；所述参考阵列中n个P型浮栅器件MR 1-～MR n-栅极接同一固定电压V GS，漏极相连并接同一固定电压V DS，源极相连并接固定电压V S，并且接入所述电流减法电路的负输入端；
    所述减法电路的输出端与所述I-V转换电阻R 1的一端相连并通过电压缓冲器接入所述存算阵列所连接的模数转换器的参考端；所述I-V转换电阻R 1的另一端接地；
    所述I-V转换电阻R 1与所述存算阵列的读出电路中的I-V转换电阻R 0参数相同。
  4. 根据权利要求3所述的温度补偿电路，其特征在于，所述神经网络存算阵列由n个P型浮栅器件M 1+～M n+和n个P型浮栅器件M 1-～M n-组成；所述存算阵列的读出电路包括一个减法电路、一个I-V转换电阻R 0和模数转换器ADC；
    所述神经网络存算阵列中，n个P型浮栅器件M 1+～M n+的栅极分别接电压V GS1～V GSn，漏极分别接输入电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的正输入端；n个P型浮栅器件M 1-～M n-的栅极分别接电压V GS1～V GSn，漏极分别接电压V DS1～V DSn，源极相连接固定电压V S且接入电流减法电路的负输入端；
    所述电流减法电路的输出端与转换电阻R 0的一端相连并接入模数转换器ADC的数据输入端；所述转换电阻R 0的另一端接地；
    所述电流减法电路用于对正输入端的输入电流和负输入端的输入电流执行减法操作。
  5. 一种用于神经网络存算阵列的温度补偿方法，所述方法应用于根据权利要求1或3的任一项所述的温度补偿电路，其特征在于，所述方法包括：
    步骤一：根据存算阵列实际工作时的温场分布情况，确定参考阵列的数量及位置；
    步骤二：根据模数转换器所需参考电压和I-V转换电阻R 1的值，计算出所述参考阵列中浮栅器件MR 1+～MR n+和MR 1-～MR n-的栅极电压V GS、漏极电压V DS以及阈值电压差ΔV TH的大小；
    步骤三：根据所述步骤二的计算结果，将栅极电压V GS、漏极电压V DS从外部输入到浮栅器件的栅极和漏极，并调节浮栅器件的阈值电压V TH，以得到步骤二计算所得的阈值电压差ΔV TH；
    步骤四：根据所述步骤三的操作，所述参考阵列产生参考电流I REF；并且所述参考电流I REF通过所述电阻R 1转换为模数转换器的参考电压V REF。
  6. 根据权利要求5所述的温度补偿方法，其特征在于，所述参考阵列与所述存算阵列处于同一温场，所述参考阵列经运算后的参考电流I REF与所述存算阵列运算后的电流I OUT具有相同的变化比例，使得模数转换器在温度变化前后的输入电压与参考电压的比值保持不变，保证模数转换器输出数据的正确性。
  7. 根据权利要求5所述的温度补偿方法，其特征在于，所述方法采用一个参考阵列为处于同一温场下所有的存算阵列所连接的模数转换器提供参考电压。
  8. 根据权利要求7所述的温度补偿方法，其特征在于，当采用一个参考阵列为处于同一温场下所有的存算阵列所连接的模数转换器提供参考电压时，所述参考阵列的插入位置处于同一温场下的所有存算器件阵列的中间位置。
  9. 根据权利要求5所述的温度补偿方法，其特征在于，所述参考阵列在阵列正常工作时产生恒定电流为模数转换器提供恒定参考电压，在阵列不工作时，调节栅极电压V GS，使参考阵列中的器件关闭。
  10. 根据权利要求5所述的温度补偿方法，其特征在于，通过与存算阵列处于同一温场的参考阵列为所述存算阵列所连接的模数转换器提供参考电压，实现对所述存算阵列中的N型或P型浮栅器件迁移率温漂特性的补偿。
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