WO2022267537A1 - 驱动电路、驱动方法、显示基板和显示装置 - Google Patents

驱动电路、驱动方法、显示基板和显示装置 Download PDF

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Publication number
WO2022267537A1
WO2022267537A1 PCT/CN2022/079292 CN2022079292W WO2022267537A1 WO 2022267537 A1 WO2022267537 A1 WO 2022267537A1 CN 2022079292 W CN2022079292 W CN 2022079292W WO 2022267537 A1 WO2022267537 A1 WO 2022267537A1
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Prior art keywords
node
transistor
electrically connected
control
electrode
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PCT/CN2022/079292
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English (en)
French (fr)
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WO2022267537A9 (zh
Inventor
郭建东
吴忠山
王小元
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/026,642 priority Critical patent/US20230335065A1/en
Publication of WO2022267537A1 publication Critical patent/WO2022267537A1/zh
Publication of WO2022267537A9 publication Critical patent/WO2022267537A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the technical field of touch display, and in particular to a driving circuit, a driving method, a display substrate and a display device.
  • the first node is in a floating (floating state), because the first electrode or the second electrode is in contact with the first electrode
  • the electrically connected transistor of a node has leakage current (especially when the drive circuit adopts a-Si (amorphous silicon) transistor, when the gate-source voltage of the a-Si transistor is 0, the leakage current is large), resulting in
  • the potential of the first node will be lower than the potential of the first node of the normal row after the pit (that is, the end of the touch phase), resulting in a decrease in the gate drive capability after the pit, and insufficient pixel charging capability, resulting in LHB horizontal stripes. After the control phase is over, it cannot be displayed normally.
  • an embodiment of the present disclosure provides a driving circuit, including a first node control circuit, a second node control circuit, a third node control circuit, and an output circuit;
  • the first node control circuit is electrically connected to the first node for controlling the potential of the first node
  • the second node control circuit is electrically connected to the second node for controlling the potential of the second node
  • the third node control circuit is electrically connected to the on-off control line, the first node and the third node, and is used to control the first node under the control of the on-off control signal provided by the on-off control line. connection or disconnection between the node and the third node;
  • the output circuit is respectively electrically connected to the second node, the third node and the driving signal terminal, and is used to control the The driving signal terminal outputs a driving signal.
  • the third node control circuit includes a first transistor
  • the gate of the first transistor is electrically connected to the on-off control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node.
  • the nodes are electrically connected.
  • the on-off control line includes a first on-off control line and a second on-off control line
  • the third node control circuit includes a first control subcircuit and a second control subcircuit
  • the first control sub-circuit is respectively electrically connected to the first on-off control line, the first node and the third node, and is used to control the first on-off control signal provided by the first on-off control line , controlling the connection or disconnection between the first node and the third node;
  • the second control sub-circuit is respectively electrically connected to the second on-off control line, the first node and the third node, and is used to control the second on-off control signal provided by the second on-off control line , to control the connection or disconnection between the first node and the third node.
  • the first control subcircuit includes a first transistor
  • the second control subcircuit includes a second transistor
  • the gate of the first transistor is electrically connected to the first on-off control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first node.
  • the third node is electrically connected;
  • the gate of the second transistor is electrically connected to the second on-off control line, the first electrode of the second transistor is electrically connected to the first node, the second electrode of the second transistor is electrically connected to the The third node is electrically connected.
  • the output circuit includes a third transistor, a fourth transistor and a storage capacitor;
  • the gate of the third transistor is electrically connected to the third node, the second electrode of the third transistor is electrically connected to the clock signal line, and the first electrode of the third transistor is electrically connected to the driving signal terminal ;
  • the gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the driving signal terminal, and the second electrode of the fourth transistor is electrically connected to the first voltage line connect;
  • the first plate of the storage capacitor is electrically connected to the third node, and the second plate of the storage capacitor is electrically connected to the driving signal terminal.
  • the output circuit further includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the frame reset line, the second electrode of the fifth transistor is electrically connected to the driving signal terminal, and the first electrode of the fifth transistor is electrically connected to the first voltage line. connect.
  • the second node control circuit includes a fourth node control subcircuit and a second node control subcircuit;
  • the fourth node control subcircuit is electrically connected to the second voltage line, the fourth node and the first voltage line respectively, and the fourth node control subcircuit is also electrically connected to the first node or the third node, Under the control of the second voltage signal provided by the second voltage line, control the communication between the fourth node and the second voltage line, and at the potential of the first node or the third Under the control of the potential of the node, control the communication between the fourth node and the first voltage line;
  • the second node control subcircuit is electrically connected to the fourth node, the second voltage line, the second node and the first voltage line, and the second node control subcircuit is also connected to the first voltage line.
  • node or the third node is electrically connected, and is used to control the communication between the second node and the second voltage line under the control of the potential of the fourth node, and the potential of the first node or the Under the control of the potential of the third node, the communication between the second node and the first voltage line is controlled.
  • the fourth node control subcircuit includes a sixth transistor and a seventh transistor;
  • the gate of the sixth transistor is electrically connected to the first electrode of the sixth transistor and the second voltage line, and the second electrode of the sixth transistor is electrically connected to the fourth node;
  • the gate of the seventh transistor is electrically connected to the first node or the third node, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor electrically connected to the first voltage line;
  • the second node control subcircuit includes an eighth transistor and a ninth transistor
  • the gate of the eighth transistor is electrically connected to the fourth node, the first electrode of the eighth transistor is electrically connected to the second voltage line, and the second electrode of the eighth transistor is electrically connected to the second voltage line. node electrical connection;
  • the gate of the ninth transistor is electrically connected to the first node or the third node, the first electrode of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor It is electrically connected with the first voltage line.
  • the first node control circuit is respectively electrically connected to the input terminal, the reset terminal, the frame reset line, the second node, the first node and the first voltage line, and is used for controlling the input signal provided at the input terminal.
  • the connection between the input terminal and the first node is controlled, and under the control of the reset signal provided by the reset terminal, the connection between the first node and the first voltage line is controlled, and the connection between the first node and the first voltage line is controlled.
  • Under the control of the potential of the second node control the connection between the first node and the first voltage line, and control the connection between the first node and the first voltage line under the control of the frame reset signal provided by the frame reset line.
  • the above-mentioned first voltage lines are connected.
  • the first node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • Both the gate of the tenth transistor and the first electrode of the tenth transistor are electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first node;
  • the gate of the eleventh transistor is electrically connected to the reset terminal, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the first node. a voltage line connection;
  • the gate of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the first node, the second electrode of the twelfth transistor is electrically connected to the the first voltage line is electrically connected;
  • the gate of the thirteenth transistor is electrically connected to the frame reset line, the first electrode of the thirteenth transistor is electrically connected to the first node, and the second electrode of the thirteenth transistor is electrically connected to the first Voltage wire electrical connection.
  • An embodiment of the present disclosure also provides a driving method, which is applied to the above-mentioned driving circuit, and the driving method includes:
  • the third node control circuit controls the connection between the first node and the third node under the control of the on-off control signal
  • the third node control circuit controls the disconnection between the first node and the third node under the control of the on-off control signal.
  • the on-off control line includes a first on-off control line and a second on-off control line
  • the third node control circuit includes a first control subcircuit and a second control subcircuit
  • the step of controlling the disconnection between the first node and the third node by the third node control circuit under the control of the on-off control signal includes:
  • the first control subcircuit controls the disconnection between the first node and the third node under the control of the first on-off control signal
  • the second control subcircuit controls the disconnection between the first node and the third node under the control of the second on-off control signal disconnection between the first node and the third node.
  • An embodiment of the present disclosure also provides a display substrate, including a display area disposed on the substrate and a driving module disposed on the peripheral area of the substrate, the driving module comprising multiple stages of the above-mentioned driving circuits;
  • the third node control circuit is arranged on the side of the output circuit away from the display area, and the on-off control line is arranged on the side of the third node control circuit away from the output circuit.
  • the third node control circuit includes a first transistor
  • the first transistor includes comb-shaped first electrodes and second electrodes arranged in the same layer;
  • the first electrode of the first transistor includes a plurality of first comb-toothed electrode parts and a first comb-handle electrode part connected to the plurality of first comb-toothed electrode parts;
  • the second electrode of the first transistor includes a plurality of second comb-toothed electrode parts and a second comb-handle electrode part connected to the plurality of second comb-toothed electrode parts;
  • the first comb-toothed electrode part and the second comb-toothed electrode part are arranged at intervals.
  • the on-off control line extends along the first direction;
  • the first transistor further includes a gate, and the gate is arranged on the same layer as the on-off control line;
  • the display substrate further includes a first a conductive connection part, a second conductive connection part, a first conductive transition part and a second conductive transition part;
  • the first conductive connection part is located on the same layer as the gate of the first transistor and is electrically connected to each other, the second conductive connection part is located on the same layer as the first electrode of the first transistor, and the first conductive connection part is located on the same layer as the first electrode of the first transistor.
  • the transfer part is arranged on the same layer as the second conductive transfer part, and the first conductive transfer part is located in a different layer from the first conductive connection part and the second conductive connection part;
  • the on-off control line is electrically connected to the first conductive transition part through a first via hole, and the first conductive transition part is electrically connected to the second conductive connection part through a second via hole.
  • the second conductive connection part is electrically connected to the second conductive transfer part through the third via hole, and the second conductive transfer part is electrically connected to the first conductive connection part through the fourth via hole, so that the second conductive transfer part is electrically connected to the first conductive connection part through the fourth via hole.
  • a gate of a transistor is electrically connected with the on-off control line.
  • the drive circuit further includes a fourth transistor and a twelfth transistor;
  • the first transistor and the fourth transistor are arranged along a first direction, or the first transistor and the twelfth transistor are arranged along a first direction.
  • the third node control circuit further includes a second transistor; the second transistor includes a comb-shaped first electrode and a second electrode; the first electrode of the first transistor, the second The first electrode of the transistor and the second electrode of the second transistor are arranged in the same layer;
  • the first electrode of the second transistor includes a plurality of third comb-toothed electrode parts and a third comb-handle electrode part connected to the plurality of third comb-toothed electrode parts;
  • the second electrode of the second transistor includes a plurality of fourth comb-toothed electrode parts and a fourth comb-handle electrode part connected to the plurality of fourth comb-toothed electrode parts;
  • the third comb-teeth electrode part and the fourth comb-teeth electrode part are arranged at intervals;
  • the third comb handle electrode part is electrically connected to the first comb handle electrode part, and the fourth comb handle electrode part is electrically connected to the second comb handle part.
  • the first transistor and the second transistor are arranged along a second direction;
  • the second direction intersects the first direction.
  • the on-off control line includes a first on-off control line and a second on-off control line arranged on the same layer; the first on-off control line extends along the first direction, and the second on-off control line the line extends along the first direction;
  • the first transistor and the second transistor also include gates respectively, and the gates are arranged on the same layer as the first on-off control line;
  • the display substrate also includes a first conductive connection part, a second conductive The connection part, the first conductive transfer part, the second conductive transfer part, the third conductive connection part, the fourth conductive connection part, the third conductive transfer part and the fourth conductive transfer part; the first conductive transfer part, the second conductive transfer part, the third conductive transfer part and the fourth conductive transfer part are arranged on the same layer;
  • the first conductive connection part is located on the same layer as the gate of the first transistor and is electrically connected to each other, the second conductive connection part is located on the same layer as the first electrode of the first transistor, and the first conductive The transition part is located at a different layer from the first conductive connection part and the second conductive connection part;
  • the first on-off control line is electrically connected to the first conductive transition part through the first via hole, and the first conductive transition part is electrically connected to the second conductive connection part through the second via hole, so The second conductive connection part is electrically connected to the second conductive transition part through the third via hole, and the second conductive transition part is electrically connected to the first conductive connection part through the fourth via hole, so that the The gate of the first transistor is electrically connected to the first on-off control line
  • the third conductive connection part is located on the same layer as the gate electrode of the second transistor and is electrically connected to each other, the fourth conductive connection part is located on the same layer as the first electrode of the second transistor, and the third conductive connection part is located on the same layer as the gate electrode of the second transistor.
  • the transition part is located at a different layer from the third conductive connection part and the fourth conductive connection part;
  • the second on-off control line is electrically connected to the third conductive transition part through the fifth via hole, and the third conductive transition part is electrically connected to the fourth conductive connection part through the sixth via hole.
  • the fourth conductive connection part is electrically connected to the fourth conductive transition part through the seventh via hole, and the fourth conductive transition part is electrically connected to the third conductive connection part through the eighth via hole, so that the The gate of the second transistor is electrically connected to the second on-off control line.
  • the drive circuit further includes a fourth transistor and a twelfth transistor;
  • the first transistor and the fourth transistor are arranged along a first direction, and the second transistor and the twelfth transistor are arranged along a first direction; or,
  • the first transistor and the twelfth transistor are arranged along a first direction, and the second transistor and the fourth transistor are arranged along a first direction.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned driving circuit or the above-mentioned display substrate.
  • FIG. 1 is a structural diagram of a driving circuit described in an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a driving circuit described in an embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a driving circuit described in an embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a working sequence diagram of an embodiment of the drive circuit shown in FIG. 8;
  • FIG. 10 is a waveform diagram of the potential of P3 obtained after simulating the embodiment of the drive circuit shown in FIG. 8;
  • FIG. 11 is a circuit diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 12 is a circuit diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 13 is a circuit diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 14 is a structural diagram of an embodiment of a first electrode and a second electrode of a first transistor in a driving circuit in a display substrate according to the present disclosure
  • 15 is a structural diagram of an embodiment of the first electrode and the second electrode of the second transistor in the driving circuit in the display substrate according to the present disclosure
  • FIG. 16 is a layout diagram of the gate metal layer in FIG. 20;
  • FIG. 17 is a layout diagram of the source and drain metal layers in FIG. 20;
  • Fig. 18 is a layout diagram of the conductive layer in Fig. 20;
  • FIG. 19 is a superimposed layout diagram of the gate metal layer and the source-drain metal layer in FIG. 20;
  • FIG. 20 is a layout diagram corresponding to the embodiment of the driving circuit shown in FIG. 13 (in FIG. 20, a gate metal layer, a source-drain metal layer, a conductive layer, and a via are shown);
  • Fig. 21 is a layout diagram of an active layer.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first electrode, and the other pole is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain, and the second electrode may be a source; or, the gate may be a gate, so The first electrode may be a source, and the second electrode may be a drain.
  • the driving circuit described in the embodiment of the present disclosure includes a first node control circuit 11 , a second node control circuit 12 , a third node control circuit 13 and an output circuit 10 ;
  • the first node control circuit 11 is electrically connected to the first node P1 for controlling the potential of the first node P1;
  • the second node control circuit 12 is electrically connected to the second node P2 for controlling the potential of the second node P2;
  • the third node control circuit 13 is electrically connected to the on-off control line SW, the first node P1 and the third node P3 respectively, and is used for controlling the on-off control signal provided by the on-off control line SW, controlling the connection or disconnection between the first node P1 and the third node P3;
  • the output circuit 10 is electrically connected to the second node P2, the third node P3, and the driving signal terminal O1, respectively, for controlling the potential of the second node P2 and the potential of the third node P3 Next, the control outputs a driving signal through the driving signal terminal O1.
  • the third node control circuit 13 controls the first node P1 and the third node P1 under the control of the on-off control signal.
  • P3 is disconnected, and the leakage path of the third node P3 is closed, so that the potential of the third node P3 can be maintained in the touch stage; in the display stage, the third node control circuit 13 is controlled by the on-off control signal.
  • the first node P1 is connected to the third node P3 for normal display driving.
  • the embodiments of the present disclosure can avoid the problem that the high potential of the third node P3 cannot be maintained when the touch control period lasts too long, resulting in failure of normal display after the touch control period ends.
  • the embodiments of the present disclosure can meet the requirements of different active pen protocols for touch time, have wide applicability, and enhance the competitiveness of touch display products.
  • the embodiment of the present disclosure cuts off the leakage path of P3, so that the touch display products, especially the touch display products supporting the active pen, can maintain the potential of the third node at a high voltage after the touch phase is over, so that the driving signal can normal output.
  • Embodiments of the present disclosure can solve the problem of horizontal stripes in LHB (Long Horizontal Blank, intra-frame touch detection) mode, and are applicable to products such as mobile terminals and notebook computers, but are not limited thereto.
  • LHB Long Horizontal Blank, intra-frame touch detection
  • the third node control circuit includes a first transistor
  • the gate of the first transistor is electrically connected to the on-off control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node.
  • the nodes are electrically connected.
  • the third node control circuit 13 includes a first transistor M1;
  • the gate of M1 is electrically connected to the on-off control line SW, the first electrode of M1 is electrically connected to the first node P1, and the second electrode of M1 is electrically connected to the third node P3;
  • M1 is an n-type transistor.
  • the SW outputs a high voltage signal, and M1 is turned on; in the touch stage, the SW outputs a low voltage signal, and M1 is turned off.
  • M1 may be a-Si TFT (amorphous silicon thin film transistor). Since the a-Si TFT is in a forward bias state for a long time, its characteristic curve will shift to the right, resulting in a decrease in the turn-on current Ion. When the ratio of the duration of the display phase to the duration of the touch phase is greater than 1, M1 will be in a positive bias state. Under long-term working or reliability conditions, the characteristic curve of M1 may shift to the right, which will cause Ion to drop, resulting in insufficient drive signal output.
  • a-Si TFT amorphous silicon thin film transistor
  • At least one embodiment of the present disclosure uses the third node control circuit to include two control sub-circuits to alternately work in the display phase, so as to prevent the transistors included in the control sub-circuit from being in a forward bias state for a long time.
  • the on-off control line may include a first on-off control line and a second on-off control line;
  • the third node control circuit may include a first control sub-circuit and a second control sub-circuit circuit;
  • the first control sub-circuit is respectively electrically connected to the first on-off control line, the first node and the third node, and is used to control the first on-off control signal provided by the first on-off control line , controlling the connection or disconnection between the first node and the third node;
  • the second control sub-circuit is respectively electrically connected to the second on-off control line, the first node and the third node, and is used to control the second on-off control signal provided by the second on-off control line , to control the connection or disconnection between the first node and the third node.
  • the third node control circuit can include two control sub-circuits.
  • the two control sub-circuits work alternately (can be in each frame or every 2s (seconds) ), switch once), so as to prevent the transistors included in the control sub-circuit from being in a positive bias state for a long time and ensure the service life of the product.
  • the on-off control line may include a first on-off control line SW1 and a second on-off control line SW2;
  • the third node control circuit includes a first control subcircuit 31 and a second control subcircuit 32;
  • the first control sub-circuit 31 is electrically connected to the first on-off control line SW1, the first node P1 and the third node P3 respectively, and is used for the first on-off control line SW1 provided on the first on-off control line SW1. Under the control of a control signal, controlling the connection or disconnection between the first node P1 and the third node P3;
  • the second control sub-circuit 32 is electrically connected to the second on-off control line SW2, the first node P1 and the third node P3 respectively, and is used to provide the second on-off control line SW2. Under the control of the control signal, the connection or disconnection between the first node P1 and the third node P3 is controlled.
  • the first control sub-circuit 31 controls the first node P1 and the first node P1 under the control of the first on-off control signal
  • the third node P3 is disconnected, and the second control subcircuit 32 controls the disconnection between the first node P1 and the third node P3 under the control of the second on-off control signal;
  • the first control subcircuit 31 and the second control subcircuit work alternately to control the connection between the first node P1 and the third node P3.
  • the first control subcircuit includes a first transistor
  • the second control subcircuit includes a second transistor
  • the gate of the first transistor is electrically connected to the first on-off control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first node.
  • the third node is electrically connected;
  • the gate of the second transistor is electrically connected to the second on-off control line, the first electrode of the second transistor is electrically connected to the first node, the second electrode of the second transistor is electrically connected to the The third node is electrically connected.
  • the first control subcircuit 31 includes a first transistor M1
  • the second control subcircuit 32 includes a second transistor M2.
  • the gate of the first transistor M1 is electrically connected to the first on-off control line SW1, the first electrode of the first transistor M1 is electrically connected to the first node P1, and the second electrode of the first transistor M1 is electrically connected to the first node P1.
  • the third node P3 is electrically connected;
  • the gate of the second transistor M2 is electrically connected to the second on-off control line SW2, the first electrode of the second transistor M2 is electrically connected to the first node P1, and the second electrode of the second transistor M2 It is electrically connected with the third node P3.
  • both M1 and M2 may be n-type transistors.
  • both SW1 and SW2 output low-voltage signals, and M1 and M2 are turned off;
  • the display stage may include multiple display time periods, each display time period includes a first display time period and a second display time period set in sequence;
  • SW1 In the first display period, SW1 outputs a high voltage signal, SW2 outputs a low voltage signal, M1 is turned on, and M2 is turned off to control the connection between P1 and P3; in the second display period, SW1 outputs a low voltage signal, and SW2 outputs High voltage signal, M1 is turned off, and M2 is turned on to control the connection between P1 and P3; or,
  • SW2 In the first display period, SW2 outputs a high voltage signal, SW1 outputs a low voltage signal, M2 is turned on, and M1 is turned off to control the connection between P1 and P3; in the second display period, SW2 outputs a low voltage signal, and SW1 outputs High voltage signal, M2 is turned off, and M1 is turned on to control the communication between P1 and P3.
  • the output circuit includes a third transistor, a fourth transistor and a storage capacitor;
  • the gate of the third transistor is electrically connected to the third node, the second electrode of the third transistor is electrically connected to the clock signal line, and the first electrode of the third transistor is electrically connected to the driving signal terminal ;
  • the gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the driving signal terminal, and the second electrode of the fourth transistor is electrically connected to the first voltage line connect;
  • the first plate of the storage capacitor is electrically connected to the third node, and the second plate of the storage capacitor is electrically connected to the driving signal terminal.
  • the output circuit further includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the frame reset line, the second electrode of the fifth transistor is electrically connected to the driving signal terminal, and the first electrode of the fifth transistor is electrically connected to the first voltage line. connect.
  • the second node control circuit may include a fourth node control subcircuit and a second node control subcircuit;
  • the fourth node control subcircuit is electrically connected to the second voltage line, the fourth node and the first voltage line respectively, and the fourth node control subcircuit is also electrically connected to the first node or the third node, Under the control of the second voltage signal provided by the second voltage line, control the communication between the fourth node and the second voltage line, and at the potential of the first node or the third Under the control of the potential of the node, control the communication between the fourth node and the first voltage line;
  • the second node control subcircuit is electrically connected to the fourth node, the second voltage line, the second node and the first voltage line, and the second node control subcircuit is also connected to the first voltage line.
  • node or the third node is electrically connected, and is used to control the communication between the second node and the second voltage line under the control of the potential of the fourth node, and the potential of the first node or the Under the control of the potential of the third node, the communication between the second node and the first voltage line is controlled.
  • the second node control circuit may include a fourth node control subcircuit 51 and a second node control subcircuit 52;
  • the fourth node control sub-circuit 51 is respectively electrically connected to the second voltage line V2, the fourth node P4, the third node P3 and the first voltage line V1, and is used to provide the second voltage line V2 on the second voltage line V2. Under the control of the two voltage signals, control the communication between the fourth node P4 and the second voltage line V2, and control the potential of the third node P3 to control the communication between the fourth node P4 and the second voltage line V2.
  • the first voltage lines V1 are connected;
  • the second node control sub-circuit 52 is electrically connected to the fourth node P4, the second voltage line V2, the second node P2, the third node P3, and the first voltage line V1, for Under the control of the potential of the fourth node P4, the communication between the second node P2 and the second voltage line V2 is controlled, and under the control of the potential of the third node P3, the second node P2 is controlled It communicates with the first voltage line V1.
  • the second voltage line may be a high voltage line
  • the first voltage line may be a low voltage line, but not limited thereto.
  • the fourth node control subcircuit 51 controls the potential of the fourth node P4, and the second node control subcircuit 52 controls the potential of the second node P2.
  • the second node control circuit may include a fourth node control subcircuit 51 and a second node control subcircuit 52;
  • the fourth node control sub-circuit 51 is electrically connected to the second voltage line V2, the fourth node P4, the first node P1 and the first voltage line V1 respectively, and is used to provide the second voltage line V2 on the second voltage line V2. Under the control of the two voltage signals, control the connection between the fourth node P4 and the second voltage line V2, and control the connection between the fourth node P4 and the second voltage line V2 under the control of the potential of the first node P1.
  • the first voltage lines V1 are connected;
  • the second node control subcircuit 52 is electrically connected to the fourth node P4, the second voltage line V2, the second node P2, the first node P1, and the first voltage line V1, and is used for Under the control of the potential of the fourth node P4, the connection between the second node P2 and the second voltage line V2 is controlled, and under the control of the potential of the first node P1, the second node P2 is controlled It communicates with the first voltage line V1.
  • the second voltage line may be a high voltage line
  • the first voltage line may be a low voltage line, but not limited thereto.
  • the fourth node control subcircuit 51 controls the potential of the fourth node P4, and the second node control subcircuit 52 controls the potential of the second node P2.
  • the fourth node control subcircuit includes a sixth transistor and a seventh transistor;
  • the gate of the sixth transistor is electrically connected to the first electrode of the sixth transistor and the second voltage line, and the second electrode of the sixth transistor is electrically connected to the fourth node;
  • the gate of the seventh transistor is electrically connected to the first node or the third node, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor electrically connected to the first voltage line;
  • the second node control subcircuit includes an eighth transistor and a ninth transistor
  • the gate of the eighth transistor is electrically connected to the fourth node, the first electrode of the eighth transistor is electrically connected to the second voltage line, and the second electrode of the eighth transistor is electrically connected to the second voltage line. node electrical connection;
  • the gate of the ninth transistor is electrically connected to the first node or the third node, the first electrode of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor It is electrically connected with the first voltage line.
  • the first node control circuit is electrically connected to the input terminal, the reset terminal, the frame reset line, the second node, the first node and the first voltage line, and is used to Under the control of the input signal provided, control the communication between the input terminal and the first node, and under the control of the reset signal provided by the reset terminal, control the connection between the first node and the first voltage line Under the control of the potential of the second node, control the communication between the first node and the first voltage line, and under the control of the frame reset signal provided by the frame reset line, control the The first node communicates with the first voltage line.
  • the first node control circuit 11 is connected to the input terminal INPUT, the reset terminal RESET, the frame reset line TRST, and the second node P2 , the first node P1 is electrically connected to the first voltage line V1, and is used to control the communication between the input terminal INPUT and the first node P1 under the control of the input signal provided by the input terminal INPUT, and the Under the control of the reset signal provided by the reset terminal RESET, the connection between the first node P1 and the first voltage line V1 is controlled, and under the control of the potential of the second node P2, the connection between the first node P1 and the first voltage line V1 is controlled.
  • a voltage line V1 is connected, and under the control of the frame reset signal provided by the frame reset line TRST, the connection between the first node and the first voltage line V1 is controlled.
  • the first node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • Both the gate of the tenth transistor and the first electrode of the tenth transistor are electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first node;
  • the gate of the eleventh transistor is electrically connected to the reset terminal, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the first node. a voltage line connection;
  • the gate of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the first node, the second electrode of the twelfth transistor is electrically connected to the the first voltage line is electrically connected;
  • the gate of the thirteenth transistor is electrically connected to the frame reset line, the first electrode of the thirteenth transistor is electrically connected to the first node, and the second electrode of the thirteenth transistor is electrically connected to the first Voltage wire electrical connection.
  • the third node control circuit 13 includes a first transistor M1; the output circuit includes a third transistor M3, a fourth transistor M4 and storage capacitor C1;
  • the gate of M1 is electrically connected to the on-off control line SW, the first electrode of M1 is electrically connected to the first node P1, and the second electrode of M1 is electrically connected to the third node P3;
  • the gate of the third transistor M3 is electrically connected to the third node P3, the second electrode of the third transistor M3 is electrically connected to the clock signal line CLK, the first electrode of the third transistor M3 is electrically connected to the The drive signal terminal OUTPUT is electrically connected;
  • the gate of the fourth transistor M4 is electrically connected to the second node P2, the first electrode of the fourth transistor M4 is electrically connected to the driving signal terminal OUTPUT, and the second electrode of the fourth transistor M4 is electrically connected to the drive signal terminal OUTPUT.
  • the low voltage line VGL is electrically connected; the low voltage line VGL is used to provide a low voltage signal;
  • the first plate of the storage capacitor C1 is electrically connected to the third node P3, and the second plate of the storage capacitor C1 is electrically connected to the driving signal terminal OUTPUT;
  • the output circuit 10 also includes a fifth transistor M5;
  • the gate of the fifth transistor M5 is electrically connected to the frame reset line TRST, the second electrode of the fifth transistor M5 is electrically connected to the driving signal terminal OUTPUT, and the first electrode of the fifth transistor M5 is connected to the low voltage Wire VGL electrical connection;
  • the fourth node control subcircuit 51 includes a sixth transistor M6 and a seventh transistor M7;
  • the gate of the sixth transistor M6 is electrically connected to the first electrode of the sixth transistor M6 and the high voltage line VGH, and the second electrode of the sixth transistor M6 is electrically connected to the fourth node P4;
  • the high voltage line VGH is used to provide a high voltage signal;
  • the gate of the seventh transistor M7 is electrically connected to the third node P3, the first electrode of the seventh transistor M7 is electrically connected to the fourth node P4, and the second electrode of the seventh transistor M7 is electrically connected to the third node P3.
  • the low voltage line VGL is electrically connected;
  • the second node control subcircuit 52 includes an eighth transistor M8 and a ninth transistor M9;
  • the gate of the eighth transistor M8 is electrically connected to the fourth node P4, the first electrode of the eighth transistor M8 is electrically connected to the high voltage line VGH, and the second electrode of the eighth transistor M8 is electrically connected to the high voltage line VGH.
  • the second node P2 is electrically connected;
  • the gate of the ninth transistor M9 is electrically connected to the third node P3, the first electrode of the ninth transistor M9 is electrically connected to the second node P2, and the second electrode of the ninth transistor M9 is electrically connected to the second node P2.
  • the low voltage line VGL is electrically connected;
  • the first node control circuit 11 includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13;
  • Both the gate of the tenth transistor M10 and the first electrode of the tenth transistor M10 are electrically connected to the input terminal INPUT, and the second electrode of the tenth transistor M10 is electrically connected to the first node P1;
  • the gate of the eleventh transistor M11 is electrically connected to the reset terminal RESET, the first electrode of the eleventh transistor M11 is electrically connected to the first node P1, and the second electrode of the eleventh transistor M11 The electrodes are electrically connected to the low voltage line VGL;
  • the gate of the twelfth transistor M12 is electrically connected to the second node P2, the first electrode of the twelfth transistor M12 is electrically connected to the first node P1, and the first electrode of the twelfth transistor M12
  • the two electrodes are electrically connected to the low voltage line VGL;
  • the gate of the thirteenth transistor M13 is electrically connected to the frame reset line TRST, the first electrode of the thirteenth transistor M13 is electrically connected to the first node P1, and the second electrode of the thirteenth transistor M13 It is electrically connected to the low voltage line VGL.
  • all transistors are n-type transistors.
  • the gate of M7 and the gate of M9 are preferably both electrically connected to the first node P1, so that in the touch phase, M7 and M9 are turned on, so that the potential of P2 is a low voltage, In this way, it is ensured that M4 is turned off, and the potential of P3 is prevented from dropping due to the leakage of M4 during the touch stage.
  • SW When the embodiment of the driving circuit shown in FIG. 8 is in operation, in the display stage, SW outputs a high voltage signal, and M1 is turned on, so that P1 and P3 are connected;
  • INPUT outputs a high voltage signal
  • M10 is turned on
  • P1 is precharged through M10
  • the potential of P1 changes from low voltage to high voltage
  • SW outputs a high voltage signal at the same time
  • M1 is turned on
  • P1 and P3 are connected to charge C1 normally;
  • INPUT In the touch stage S0, INPUT outputs a low voltage signal, SW outputs a low voltage signal, and P1 and P3 are disconnected. Since the leakage path between P3 and M10, M11, M13, and M12 is cut off, the potential of P3 is maintained at a high voltage;
  • RESET provides a high voltage signal
  • SW provides a high voltage signal
  • the potentials of P1 and P3 are pulled down, and the driving circuit enters a normal display working state.
  • FIG. 10 is a waveform diagram of the potential of P3 obtained after simulating the embodiment of the driving circuit shown in FIG. 8 .
  • the one labeled S0 is the touch stage. It can be seen from FIG. 10 that in the touch phase S0, the potential of P3 can be maintained at a high voltage.
  • the difference between the embodiment of the driving circuit shown in FIG. 11 and the embodiment of the driving circuit shown in FIG. 8 is as follows: the gate of M7 and the gate of M9 are both electrically connected to the first node P1.
  • the on-off control line may include a first on-off control line SW1 and a second on-off control line SW2;
  • the third node control circuit includes a first control subcircuit 31 and a second control subcircuit 32;
  • the first control subcircuit 31 includes a first transistor M1, and the second control subcircuit 32 includes a second transistor M2;
  • the gate of the first transistor M1 is electrically connected to the first on-off control line SW1, the first electrode of the first transistor M1 is electrically connected to the first node P1, and the second electrode of the first transistor M1 is electrically connected to the first node P1.
  • the third node P3 is electrically connected;
  • the gate of the second transistor M2 is electrically connected to the second on-off control line SW2, the first electrode of the second transistor M2 is electrically connected to the first node P1, and the second electrode of the second transistor M2 It is electrically connected with the third node P3.
  • all transistors may be n-type transistors.
  • the difference between the embodiment of the driving circuit shown in FIG. 13 and the embodiment of the driving circuit shown in FIG. 12 is as follows: the gate of M7 and the gate of M9 are both electrically connected to the first node P1.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:
  • the third node control circuit controls the connection between the first node and the third node under the control of the on-off control signal
  • the third node control circuit controls the disconnection between the first node and the third node under the control of the on-off control signal.
  • the third node control circuit controls the disconnection between the first node and the third node under the control of the on-off control signal, and turns off the third node.
  • the leakage path of the node can keep the potential of the third node in the touch stage; in the display stage, the third node control circuit controls the first node and the third node under the control of the on-off control signal Connected to enable normal display drive.
  • the on-off control line may include a first on-off control line and a second on-off control line
  • the third node control circuit may include a first control sub-circuit and a second control sub-circuit
  • the display stage Including a plurality of display time periods, the display time period includes a first display time period and a second display time period set in sequence
  • the driving method includes:
  • the first control subcircuit controls the connection between the first node and the third node under the control of the first on-off control signal; during the second display period, The second control subcircuit controls the communication between the first node and the third node under the control of the second on-off control signal; or,
  • the second control subcircuit controls the connection between the first node and the third node under the control of the second on-off control signal; during the second display period, The first control subcircuit controls the connection between the first node and the third node under the control of the first on-off control signal.
  • the third node control circuit can include two control sub-circuits.
  • the two control sub-circuits work alternately (can be switched every frame or every 2s) Once), to prevent the transistors included in the control sub-circuit from being in a forward-biased state for a long time, and to ensure the service life of the product.
  • the step of controlling the disconnection between the first node and the third node by the third node control circuit under the control of the on-off control signal may include:
  • the first control subcircuit controls the disconnection between the first node and the third node under the control of the first on-off control signal
  • the second control subcircuit controls the disconnection between the first node and the third node under the control of the second on-off control signal disconnection between the first node and the third node.
  • the display substrate described in the embodiment of the present disclosure includes a display area set on the base and a driving module set on the peripheral area on the base, and the driving module includes multiple stages of the above-mentioned driving circuits;
  • the third node control circuit is arranged on the side of the output circuit away from the display area, and the on-off control line is arranged on the side of the third node control circuit away from the output circuit.
  • the pixel circuit is arranged in the display area on the substrate, the driving module is arranged in the peripheral area on the substrate, the output circuit, the third node control circuit and The on-off control lines may be arranged in sequence along a direction away from the display area.
  • the input terminal of the driving circuit is electrically connected to the driving signal terminal of the adjacent upper-level driving circuit
  • the reset terminal of the driving circuit is electrically connected to the driving signal terminal of the adjacent next-level driving circuit. connect.
  • the third node control circuit includes a first transistor
  • the first transistor includes comb-shaped first electrodes and second electrodes arranged in the same layer;
  • the first electrode of the first transistor includes a plurality of first comb-toothed electrode parts and a first comb-handle electrode part connected to the plurality of first comb-toothed electrode parts;
  • the second electrode of the first transistor includes a plurality of second comb-toothed electrode parts and a second comb-handle electrode part connected to the plurality of second comb-toothed electrode parts;
  • the first comb-toothed electrode part and the second comb-toothed electrode part are arranged at intervals.
  • the first transistor may include a comb-shaped first electrode and a second electrode
  • the first electrode of the first transistor includes the first first comb-tooth electrode part 111, the second first comb-tooth electrode part 112, and the third first comb-tooth electrode which are electrically connected to each other.
  • the second electrode of the first transistor includes a first second comb-tooth electrode portion 121, a second second comb-tooth electrode portion 122, a third second comb-tooth electrode portion 123, a fourth The second comb electrode part 124 and the second comb handle electrode part 120;
  • the tooth electrode portion 123 , the third first comb-shaped electrode portion 113 and the fourth second comb-shaped electrode portion 124 are arranged in sequence along the second direction.
  • the second direction is the lateral direction
  • gate lines are arranged in the display area, and the gate lines include portions extending in the lateral direction.
  • the structure shown in FIG. 14 is only an example of the structure of the first transistor, and is not intended to limit the structure of the first transistor.
  • the on-off control line may extend along the first direction;
  • the first transistor further includes a gate, and the gate is arranged on the same layer as the on-off control line;
  • the display substrate further includes a first conductive connection part, a second conductive connection part, a first conductive transition part and a second conductive transition part;
  • the first conductive connection part is located on the same layer as the gate of the first transistor and is electrically connected to each other, the second conductive connection part is located on the same layer as the first electrode of the first transistor, and the first conductive connection part is located on the same layer as the first electrode of the first transistor.
  • the transfer part is arranged on the same layer as the second conductive transfer part, and the first conductive transfer part is located in a different layer from the first conductive connection part and the second conductive connection part;
  • the on-off control line is electrically connected to the first conductive transition part through a first via hole, and the first conductive transition part is electrically connected to the second conductive connection part through a second via hole.
  • the second conductive connection part is electrically connected to the second conductive transfer part through the third via hole, and the second conductive transfer part is electrically connected to the first conductive connection part through the fourth via hole, so that the second conductive transfer part is electrically connected to the first conductive connection part through the fourth via hole.
  • a gate of a transistor is electrically connected with the on-off control line.
  • the first conductive connection part, the on-off control line and the gate of the first transistor are located on the same layer, and the second conductive connection part, the first electrode of the first transistor and the gate of the first transistor The second electrode is located on the same layer, and the first conductive transition part and the second conductive transition part are located on the same layer;
  • the on-off control line is electrically connected to the gate of the first transistor through the first conductive transition part and the second conductive transition part.
  • the display substrate may include an active layer, a first insulating layer, a gate metal layer, a second insulating layer, a source-drain metal layer, a third insulating layer, and a conductive layer sequentially disposed on the substrate;
  • the gate metal layer is subjected to a patterning process to form gates of transistors in the drive circuit, clock signal lines, high voltage lines, low voltage lines, on-off control lines, and first conductive connections. performing a patterning process to form the first electrode of the transistor in the driving circuit, the second electrode of the transistor in the driving circuit, and the second conductive connection part, and performing a patterning process on the conductive layer to form a first conductive connection part and the second conductive transfer part;
  • the on-off control line is electrically connected to the first conductive transition part through the first via hole penetrating through the second insulating layer and the third insulating layer, and the first conductive transition part passes through the third insulating layer
  • the second via hole is electrically connected to the second conductive connection part, and the second conductive connection part is electrically connected to the second conductive transition part through a third via hole penetrating through the third insulating layer.
  • the second conductive transition part is electrically connected to the first conductive connection part through the fourth via hole passing through the second insulating layer and the third insulating layer, so that the on-off control line is connected to the first insulating layer.
  • the gate of the transistor is electrically connected.
  • the conductive layer may be made of ITO (Indium Tin Oxide).
  • “same layer” in the embodiments of the present disclosure may refer to film layers on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • the drive circuit further includes a fourth transistor and a twelfth transistor;
  • the first transistor and the fourth transistor are arranged along a first direction, or the first transistor and the twelfth transistor are arranged along a first direction.
  • the first transistor and the fourth transistor included in the driving circuit are arranged along the first direction, or the first transistor and the twelfth transistor included in the driving circuit are arranged along the first direction, so as to narrow the peripheral
  • the width of the region along the second direction is conducive to realizing a narrow frame.
  • the first direction intersects the second direction, and multiple rows of gate lines and multiple columns of data lines are arranged in the display area; the first direction may be approximately the same as the extending direction of the data lines direction, and the second direction may be substantially the same direction as the extending direction of the gate lines.
  • the third node control circuit may further include a second transistor; the second transistor includes comb-shaped first electrodes and second electrodes; the first electrode of the first transistor, the The first electrode of the second transistor and the second electrode of the second transistor are arranged in the same layer;
  • the first electrode of the second transistor includes a plurality of third comb-toothed electrode parts and a third comb-handle electrode part connected to the plurality of third comb-toothed electrode parts;
  • the second electrode of the second transistor includes a plurality of fourth comb-toothed electrode parts and a fourth comb-handle electrode part connected to the plurality of fourth comb-toothed electrode parts;
  • the third comb-teeth electrode part and the fourth comb-teeth electrode part are arranged at intervals;
  • the third comb handle electrode part is electrically connected to the first comb handle electrode part, and the fourth comb handle electrode part is electrically connected to the second comb handle part.
  • the first electrode of the second transistor includes a first third comb-tooth electrode portion 131, a second third comb-tooth electrode portion 132, a third third comb-tooth electrode, which are electrically connected to each other.
  • the second electrode of the second transistor includes a first fourth comb-tooth electrode portion 141, a second fourth comb-tooth electrode portion 142, a fourth second comb-tooth electrode portion 143, a fourth The fourth comb electrode part 144 and the fourth comb handle electrode part 140;
  • the tooth electrode part 143 , the third and third comb-teeth electrode parts 133 and the fourth and fourth comb-teeth electrode parts 144 are arranged in sequence along the second direction.
  • the first transistor and the second transistor may be arranged along a second direction
  • the second direction intersects the first direction.
  • the on-off control line includes a first on-off control line and a second on-off control line arranged on the same layer; the first on-off control line extends along the first direction, and the second on-off control line the line extends along the first direction;
  • the first transistor and the second transistor also include gates respectively, and the gates are arranged on the same layer as the first on-off control line;
  • the display substrate also includes a first conductive connection part, a second conductive The connection part, the first conductive transfer part, the second conductive transfer part, the third conductive connection part, the fourth conductive connection part, the third conductive transfer part and the fourth conductive transfer part; the first conductive transfer part, the second conductive transfer part, the third conductive transfer part and the fourth conductive transfer part are arranged on the same layer;
  • the first conductive connection part is located on the same layer as the gate of the first transistor and is electrically connected to each other, the second conductive connection part is located on the same layer as the first electrode of the first transistor, and the first conductive connection part is located on the same layer as the first electrode of the first transistor.
  • the transition part is located at a different layer from the first conductive connection part and the second conductive connection part;
  • the first on-off control line is electrically connected to the first conductive transition part through the first via hole, and the first conductive transition part is electrically connected to the second conductive connection part through the second via hole, so The second conductive connection part is electrically connected to the second conductive transition part through the third via hole, and the second conductive transition part is electrically connected to the first conductive connection part through the fourth via hole, so that the The gate of the first transistor is electrically connected to the first on-off control line;
  • the third conductive connection part is located on the same layer as the gate electrode of the second transistor and is electrically connected to each other, the fourth conductive connection part is located on the same layer as the first electrode of the second transistor, and the third conductive connection part is located on the same layer as the gate electrode of the second transistor.
  • the transition part is located at a different layer from the third conductive connection part and the fourth conductive connection part;
  • the second on-off control line is electrically connected to the third conductive transition part through the fifth via hole, and the third conductive transition part is electrically connected to the fourth conductive connection part through the sixth via hole.
  • the fourth conductive connection part is electrically connected to the fourth conductive transition part through the seventh via hole, and the fourth conductive transition part is electrically connected to the third conductive connection part through the eighth via hole, so that the The gate of the second transistor is electrically connected to the second on-off control line.
  • the display substrate may include an active layer, a first insulating layer, a gate metal layer, a second insulating layer, a source-drain metal layer, a third insulating layer, and a conductive layer sequentially disposed on the substrate;
  • the gate metal layer is patterned to form the gate of the transistor in the drive circuit, the clock signal line, the high voltage line, the low voltage line, the first on-off control line, the second on-off control line, the first conductive
  • the connection part and the third conductive connection part, the source-drain metal layer is patterned to form the first electrode of the transistor in the drive circuit, the second electrode of the transistor in the drive circuit, the second conductive connection part and The fourth conductive connection part, performing a patterning process on the conductive layer to form a first conductive transfer part, a second conductive transfer part, a third conductive connection part and a fourth conductive connection part;
  • the first on-off control line is electrically connected to the first conductive transition part through the first via hole penetrating through the second insulating layer and the third insulating layer, and the first conductive transition part passes through the third insulating layer.
  • the second via hole in the insulating layer is electrically connected to the second conductive connection part, and the second conductive connection part is electrically connected to the second conductive transfer part through a third via hole penetrating through the third insulating layer,
  • the second conductive transition part is electrically connected to the first conductive connection part through a fourth via hole penetrating through the second insulating layer and the third insulating layer, so that the first on-off control line is connected to the first on-off control line.
  • the gate of the first transistor is electrically connected;
  • the second on-off control line is electrically connected to the third conductive transfer part through the fifth via hole passing through the second insulating layer and the third insulating layer, and the third conductive transfer part passes through the third
  • the sixth via hole in the insulating layer is electrically connected to the fourth conductive connection part, and the fourth conductive connection part is electrically connected to the fourth conductive transfer part through the seventh via hole penetrating through the third insulating layer,
  • the fourth conductive transition part is electrically connected to the third conductive connection part through the eighth via hole passing through the second insulating layer and the third insulating layer, so that the second on-off control line is connected to the third insulating layer.
  • the gate of the second transistor is electrically connected.
  • the drive circuit may further include a fourth transistor and a twelfth transistor;
  • the first transistor and the fourth transistor are arranged along a first direction, and the second transistor and the twelfth transistor are arranged along a first direction; or,
  • the first transistor and the twelfth transistor are arranged along a first direction, and the second transistor and the fourth transistor are arranged along a first direction;
  • the width of the peripheral area along the second direction is narrowed, which is beneficial to realize a narrow frame.
  • Figure 20 is a layout diagram corresponding to the embodiment of the driving circuit shown in Figure 13 (in Figure 20, a gate metal layer, a source-drain metal layer, a conductive layer, and a via are shown), and Figure 16 is a gate in Figure 20
  • the layout diagram of the metal layer, 17 is the layout diagram of the source-drain metal layer in Figure 20
  • Figure 18 is the layout diagram of the conductive layer in Figure 20
  • Figure 19 is the superposition of the gate metal layer and the source-drain metal layer in Figure 20 subsequent layout.
  • Fig. 21 is a layout diagram of an active layer.
  • the gate marked with G1 is the gate of the first transistor
  • the one marked with L1 is the first conductive connection part
  • the one marked with G2 is the gate of the second transistor
  • the one marked with L3 is the third conductive connection part.
  • the one marked SW1 is the first on-off control line
  • the one marked SW2 is the second on-off control line
  • the one marked VGL is the low voltage line
  • the one marked VGH is the high voltage line.
  • the label L2 is the second conductive connection part
  • the label L4 is the fourth conductive connection part
  • the label 181 is the electrode unit included in T1.
  • the electrode unit 181 included in T1 includes T1 in FIG. 13
  • the first electrode of T2 and the second electrode of T1 the electrode unit 182 included in T2
  • the electrode unit 182 of T2 includes the first electrode of T2 and the second electrode of T2 in FIG. 13 .
  • the one marked Z1 is the first conductive transfer part
  • the one marked Z2 is the second conductive transfer part
  • the one marked Z3 is the third conductive transfer part
  • the one marked Z4 is the fourth conductive transfer part. Connection department.
  • the one labeled H1 is the first via hole
  • the one labeled H2 is the second via hole
  • the one labeled H3 is the third via hole
  • the one labeled H4 is the fourth via hole
  • the one labeled H5 is As for the fifth via hole
  • the one labeled H6 is the sixth via hole
  • the one labeled H7 is the seventh via hole
  • the one labeled H8 is the eighth via hole.
  • the first on-off control line SW1 is electrically connected to the first conductive transition part Z1 through the first via hole H1, and the first conductive transition part Z1 is connected to the first conductive transition part Z1 through the second via hole H2.
  • the second conductive connection part L2 is electrically connected, the second conductive connection part L2 is electrically connected to the second conductive transition part Z2 through the third via hole H3, and the second conductive transition part Z2 is electrically connected to the second conductive transition part Z2 through the fourth via hole H3.
  • the via hole H4 is electrically connected to the first conductive connection portion L1, so that the gate G1 of the first transistor is electrically connected to the first on-off control line SW1;
  • the second on-off control line SW2 is electrically connected to the third conductive transition part Z3 through the fifth via hole H5, and the third conductive transition part Z3 is connected to the fourth conductive transition part through the sixth via hole H6.
  • part L4 the fourth conductive connection part L4 is electrically connected to the fourth conductive transfer part Z4 through the seventh via hole H7, and the fourth conductive transfer part Z4 is connected to the fourth conductive transfer part Z4 through the eighth via hole H8.
  • the third conductive connection portion L3 is electrically connected, so that the gate G2 of the second transistor is electrically connected with the second on-off control line SW2.
  • both the first electrodes of the transistors in the driving circuit and the second electrodes of the transistors in the driving circuit are comb electrodes.
  • the number 181 is an electrode unit included in M1, and the electrode unit 181 included in M1 includes a first electrode of M1 and a second electrode of M1;
  • the electrode unit 182 is an electrode unit included in M2, and the electrode unit 182 included in M2 includes a first electrode of M2 and a second electrode of M2;
  • the electrode unit 183 included in M3 includes a first electrode of M3 and a second electrode of M3;
  • Number 184 is an electrode unit included in M4, and the electrode unit 184 included in M4 includes a first electrode of M4 and a second electrode of M4;
  • the electrode unit 185 is an electrode unit included in M5, and the electrode unit 185 included in M5 includes a first electrode of M5 and a second electrode of M5;
  • Number 186 is an electrode unit included in M6, and the electrode unit 186 included in M6 includes a first electrode of M6 and a second electrode of M6;
  • Number 187 is an electrode unit included in M7, and the electrode unit 187 included in M7 includes a first electrode of M7 and a second electrode of M7;
  • Number 188 is an electrode unit included in M8, and the electrode unit 188 included in M8 includes a first electrode of M8 and a second electrode of M8;
  • the electrode unit 189 is an electrode unit included in M9, and the electrode unit 189 included in M9 includes a first electrode of M9 and a second electrode of M9;
  • Labeled as 1810 is the electrode unit included in M10, the electrode unit 1810 included in M10 includes the first electrode of M10 and the second electrode of M10;
  • the electrode unit 1811 is an electrode unit included in M11, and the electrode unit 1811 included in M11 includes a first electrode of M11 and a second electrode of M11;
  • the electrode unit 1812 is an electrode unit included in M12, and the electrode unit 1812 included in M12 includes a first electrode of M12 and a second electrode of M12;
  • Reference numeral 1813 is an electrode unit included in M13, and the electrode unit 1813 included in M13 includes a first electrode of M13 and a second electrode of M13.
  • the one labeled C1b is the second plate of C1
  • the one labeled OUTPUT is the driving signal terminal.
  • the symbol L6 is the sixth conductive connection part, and the sixth conductive connection part L6 is used to electrically connect the clock signal line CLK and the second electrode of M3 .
  • the grid labeled G3 is the grid of M3
  • the grid labeled G4 is the grid of M4
  • the grid labeled G5 is the grid of M5
  • the grid labeled G7 is the grid of M7
  • the grid labeled G8 is The gate of M8,
  • the gate marked G9 is the gate of M9
  • the gate marked G10 is the gate of M10
  • the gate marked G11 is the gate of M11
  • the gate marked G12 is the gate of M12
  • the gate marked G13 is Gate of M13.
  • the high voltage line VGH is multiplexed as the gate of M6, and the frame reset line is multiplexed as the gate G13 of M13 and the gate G5 of M5.
  • the gate G3 of M3 is electrically connected to the first plate C1a of C1
  • the gate G11 of M11 is electrically connected to the reset terminal RESET
  • the gate G10 of M10 is electrically connected to the input terminal INPUT.
  • the fifth conductive connection portion labeled L5 is used for electrically connecting the first electrode of the fifth transistor and the second electrode of the thirteenth transistor.
  • the gate of M1 and the gate of M12 are arranged along the first direction, and the gate of M2 and the gate of M4 are arranged along the first direction;
  • the electrode units 181 of M1 and the electrode units 1812 of M12 are arranged along the first direction, and the electrode units 182 of M2 and the electrode units 184 of M4 are arranged along the first direction;
  • M1 and M12 are arranged along the first direction, and M2 and M4 are arranged along the first direction, so as to shorten the width of the peripheral region along the second direction, which is beneficial to realize a narrow frame.
  • the second plate C1b of C1 is electrically connected to the first electrode of M3 in the electrode unit 183 of M3, and the second plate C1b of C1 is electrically connected to the driving signal terminal OUTPUT.
  • the first electrode of M1, the first electrode of M2, the first electrode of M13 and the second electrode of M10 are all electrically connected to the third node P3;
  • the second electrode of M1, the second electrode of M2, the first electrode of M12 and the first electrode of M11 are all electrically connected to the first node P1;
  • the second electrode of M8 and the first electrode of M9 are respectively electrically connected to the second node P2.
  • the active layer pattern labeled 221 is M1
  • the active layer pattern labeled 222 is M2
  • the active layer pattern labeled 223 is M3
  • the active layer pattern labeled 224 is M4.
  • Layer graphics the number 225 is the active layer graphics of M5, the number 226 is the active layer graphics of M6, the number 227 is the active layer graphics of M7, and the number 228 is the active layer graphics of M8
  • the number 229 is the active layer graphics of M9
  • the number 210 is the active layer graphics of M10
  • the number 211 is the active layer graphics of M11
  • the number 212 is the active layer graphics of M12
  • the number 213 is the active layer pattern of M13.
  • At least one embodiment of the present disclosure includes a display device including the above-mentioned driving circuit, or the display device according to at least one embodiment of the present disclosure includes the above-mentioned display substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种驱动电路、驱动方法、显示基板和显示装置。驱动电路包括第一节点控制电路（11）、第二节点控制电路（12）、第三节点控制电路（13）和输出电路（10）；第一节点控制电路（11）控制第一节点的电位；第二节点控制电路（12）控制第二节点的电位；第三节点控制电路（13）在通断控制信号的控制下，控制第一节点和第三节点之间连通或断开；输出电路（10）在第二节点的电位和第三节点的电位的控制下，控制通过驱动信号端输出驱动信号。该驱动电路避免了当触控阶段持续的时间过长时不能保持第三节点的高电位，从而导致触控阶段结束后不能正常显示的问题。

Description

驱动电路、驱动方法、显示基板和显示装置
相关申请的交叉引用
本申请主张在2021年6月22日在中国提交的中国专利申请号No.202110692448.4的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及触控显示技术领域，尤其涉及一种驱动电路、驱动方法、显示基板和显示装置。
背景技术
目前电子产品发展趋势是轻薄化、功能多样化，对显示产品的设计挑战也越来越高。随着主动笔在显示产品上的应用不断普及，内嵌式触控技术广泛应用。
现有的应用于触控显示产品的驱动电路在LHB(Long Horizontal Blank，帧内触控检测)期间，第一节点处于floating(浮空状态)，由于第一电极或第二电极与所述第一节点的电连接的晶体管存在漏电的情况(尤其是所述驱动电路采用a-Si(非晶硅)晶体管时，在a-Si晶体管的栅源电压为0时，漏电流大)，从而导致第一节点的电位在出坑(也即触控阶段结束)后会比正常行的第一节点的电位低，造成坑后栅极驱动能力降低，像素充电能力不足，导致LHB横纹，在触控阶段结束后不能正常显示。
发明内容
在一个方面中，本公开实施例提供了一种驱动电路，包括第一节点控制电路、第二节点控制电路、第三节点控制电路和输出电路；
所述第一节点控制电路与第一节点电连接，用于控制所述第一节点的电位；
所述第二节点控制电路与第二节点电连接，用于控制所述第二节点的电位；
所述第三节点控制电路分别与通断控制线、所述第一节点和第三节点电连接，用于在所述通断控制线提供的通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通或断开；
所述输出电路分别与所述第二节点、所述第三节点和驱动信号端电连接，用于在所述第二节点的电位和所述第三节点的电位的控制下，控制通过所述驱动信号端输出驱动信号。
可选的，所述第三节点控制电路包括第一晶体管；
所述第一晶体管的栅极与所述通断控制线电连接，所述第一晶体管的第一电极与所述第一节点电连接，所述第一晶体管的第二电极与所述第三节点电连接。
可选的，所述通断控制线包括第一通断控制线和第二通断控制线；所述第三节点控制电路包括第一控制子电路和第二控制子电路；
所述第一控制子电路分别与第一通断控制线、所述第一节点和第三节点电连接，用于在所述第一通断控制线提供的第一通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通或断开；
所述第二控制子电路分别与第二通断控制线、所述第一节点和第三节点电连接，用于在所述第二通断控制线提供的第二通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通或断开。
可选的，所述第一控制子电路包括第一晶体管，所述第二控制子电路包括第二晶体管；
所述第一晶体管的栅极与所述第一通断控制线电连接，所述第一晶体管的第一电极与所述第一节点电连接，所述第一晶体管的第二电极与所述第三节点电连接；
所述第二晶体管的栅极与所述第二通断控制线电连接，所述第二晶体管的第一电极与所述第一节点电连接，所述第二晶体管的第二电极与所述第三节点电连接。
可选的，所述输出电路包括第三晶体管、第四晶体管和存储电容；
所述第三晶体管的栅极与所述第三节点电连接，所述第三晶体管的第二电极与时钟信号线电连接，所述第三晶体管的第一电极与所述驱动信号端电 连接；
所述第四晶体管的栅极与所述第二节点电连接，所述第四晶体管的第一电极与所述驱动信号端电连接，所述第四晶体管的第二电极与第一电压线电连接；
所述存储电容的第一极板与所述第三节点电连接，所述存储电容的第二极板与所述驱动信号端电连接。
可选的，所述输出电路还包括第五晶体管；
所述第五晶体管的栅极与帧复位线电连接，所述第五晶体管的第二电极与所述驱动信号端电连接，所述第五晶体管的第一电极与所述第一电压线电连接。
可选的，所述第二节点控制电路包括第四节点控制子电路和第二节点控制子电路；
所述第四节点控制子电路分别与第二电压线、第四节点和第一电压线电连接，所述第四节点控制子电路还与所述第一节点或所述第三节点电连接，用于在所述第二电压线提供的第二电压信号的控制下，控制所述第四节点与所述第二电压线之间连通，并在所述第一节点的电位或所述第三节点的电位的控制下，控制所述第四节点与所述第一电压线之间连通；
所述第二节点控制子电路分别与所述第四节点、所述第二电压线、所述第二节点和第一电压线电连接，所述第二节点控制子电路还与所述第一节点或第三节点电连接，用于在所述第四节点的电位的控制下，控制所述第二节点与所述第二电压线之间连通，在所述第一节点的电位或所述第三节点的电位的控制下，控制所述第二节点与所述第一电压线之间连通。
可选的，所述第四节点控制子电路包括第六晶体管和第七晶体管；
所述第六晶体管的栅极与所述第六晶体管的第一电极与所述第二电压线电连接，所述第六晶体管的第二电极与所述第四节点电连接；
所述第七晶体管的栅极与所述第一节点或所述第三节点电连接，所述第七晶体管的第一电极与所述第四节点电连接，所述第七晶体管的第二电极与所述第一电压线电连接；
所述第二节点控制子电路包括第八晶体管和第九晶体管；
所述第八晶体管的栅极与所述第四节点电连接，所述第八晶体管的第一电极与所述第二电压线电连接，所述第八晶体管的第二电极与所述第二节点电连接；
所述第九晶体管的栅极与所述第一节点或所述第三节点电连接，所述第九晶体管的第一电极与所述第二节点电连接，所述第九晶体管的第二电极与所述第一电压线电连接。
可选的，所述第一节点控制电路分别与输入端、复位端、帧复位线、第二节点、第一节点和第一电压线电连接，用于在所述输入端提供的输入信号的控制下，控制所述输入端与所述第一节点之间连通，在所述复位端提供的复位信号的控制下，控制所述第一节点与所述第一电压线之间连通，在所述第二节点的电位的控制下，控制所述第一节点与所述第一电压线之间连通，在所述帧复位线提供的帧复位信号的控制下，控制所述第一节点与所述第一电压线之间连通。
可选的，所述第一节点控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
所述第十晶体管的栅极与所述第十晶体管的第一电极都与所述输入端电连接，所述第十晶体管的第二电极与所述第一节点电连接；
所述第十一晶体管的栅极与所述复位端电连接，所述第十一晶体管的第一电极与所述第一节点电连接，所述第十一晶体管的第二电极与所述第一电压线电连接；
所述第十二晶体管的栅极与所述第二节点电连接，所述第十二晶体管的第一电极与所述第一节点电连接，所述第十二晶体管的第二电极与所述第一电压线电连接；
第十三晶体管的栅极与所述帧复位线电连接，所述第十三晶体管的第一电极与所述第一节点电连接，所述第十三晶体管的第二电极与所述第一电压线电连接。
本公开实施例还提供了一种驱动方法，应用于上述的驱动电路，所述驱动方法包括：
在显示阶段，第三节点控制电路在通断控制信号的控制下，控制所述第 一节点与所述第三节点之间连通；
在触控阶段，第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间断开。
可选的，所述通断控制线包括第一通断控制线和第二通断控制线，所述第三节点控制电路包括第一控制子电路和第二控制子电路；
所述第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间断开步骤包括：
第一控制子电路在第一通断控制信号的控制下，控制所述第一节点和所述第三节点之间断开，第二控制子电路在第二通断控制信号的控制下，控制所述第一节点和所述第三节点之间断开。
本公开实施例还提供一种显示基板，包括设置于基底上的显示区域以及设置于基底上的周边区域的驱动模组，所述驱动模组包括多级上述的驱动电路；
第三节点控制电路设置于所述输出电路远离所述显示区域的一侧，通断控制线设置于所述第三节点控制电路远离所述输出电路的一侧。
可选的，所述第三节点控制电路包括第一晶体管；
所述第一晶体管包括同层设置的分别呈梳状的第一电极和第二电极；
所述第一晶体管的第一电极包括多个第一梳齿电极部以及连接所述多个第一梳齿电极部的第一梳柄电极部；
所述第一晶体管的第二电极包括多个第二梳齿电极部以及连接所述多个第二梳齿电极部的第二梳柄电极部；
所述第一梳齿电极部与所述第二梳齿电极部间隔排列。
可选的，所述通断控制线沿第一方向延伸；所述第一晶体管还包括栅极，所述栅极与所述通断控制线设置于同一层；所述显示基板还包括第一导电连接部、第二导电连接部、第一导电转接部和第二导电转接部；
所述第一导电连接部与所述第一晶体管的栅极位于同一层并相互电连接，所述第二导电连接部与所述第一晶体管的第一电极位于同一层，所述第一导电转接部与所述第二导电转接部同层设置，所述第一导电转接部与所述第一导电连接部和所述第二导电连接部位于不同层；
所述通断控制线通过第一过孔与所述第一导电转接部电连接，所述第一导电转接部通过第二过孔与所述第二导电连接部电连接，所述第二导电连接部通过第三过孔与所述第二导电转接部电连接，所述第二导电转接部通过第四过孔与所述第一导电连接部电连接，从而使得所述第一晶体管的栅极与所述通断控制线电连接。
可选的，所述驱动电路还包括第四晶体管和第十二晶体管；
所述第一晶体管与所述第四晶体管沿第一方向排列，或者，所述第一晶体管与所述第十二晶体管沿第一方向排列。
可选的，所述第三节点控制电路还包括第二晶体管；所述第二晶体管包括分别呈梳状的第一电极和第二电极；所述第一晶体管的第一电极、所述第二晶体管的第一电极和第二晶体管的第二电极同层设置；
所述第二晶体管的第一电极包括多个第三梳齿电极部以及连接所述多个第三梳齿电极部的第三梳柄电极部；
所述第二晶体管的第二电极包括多个第四梳齿电极部以及连接所述多个第四梳齿电极部的第四梳柄电极部；
所述第三梳齿电极部与所述第四梳齿电极部间隔排列；
所述第三梳柄电极部与所述第一梳柄电极部电连接，所述第四梳柄电极部与所述第二梳柄部电连接。
可选的，所述第一晶体管和第二晶体管沿第二方向排列；
所述第二方向与第一方向相交。
可选的，所述通断控制线包括同层设置的第一通断控制线和第二通断控制线；所述第一通断控制线沿第一方向延伸，所述第二通断控制线沿第一方向延伸；
所述第一晶体管和所述第二晶体管还分别包括栅极，所述栅极与所述第一通断控制线设置于同一层；所述显示基板还包括第一导电连接部、第二导电连接部、第一导电转接部、第二导电转接部、第三导电连接部、第四导电连接部、第三导电转接部和第四导电转接部；所述第一导电转接部、所述第二导电转接部、所述第三导电转接部和所述第四导电转接部同层设置；
所述第一导电连接部与所述第一晶体管的栅极位于同一层并相互电连接， 所述第二导电连接部与所述第一晶体管的第一电极位于同一层，所述第一导电转接部与所述第一导电连接部和所述第二导电连接部位于不同层；
所述第一通断控制线通过第一过孔与所述第一导电转接部电连接，所述第一导电转接部通过第二过孔与所述第二导电连接部电连接，所述第二导电连接部通过第三过孔与所述第二导电转接部电连接，所述第二导电转接部通过第四过孔与所述第一导电连接部电连接，从而使得所述第一晶体管的栅极与所述第一通断控制线电连接
所述第三导电连接部与所述第二晶体管的栅极位于同一层并相互电连接，所述第四导电连接部与所述第二晶体管的第一电极位于同一层，所述第三导电转接部与所述第三导电连接部和所述第四导电连接部位于不同层；
所述第二通断控制线通过第五过孔与所述第三导电转接部电连接，所述第三导电转接部通过第六过孔与所述第四导电连接部电连接，所述第四导电连接部通过第七过孔与所述第四导电转接部电连接，所述第四导电转接部通过第八过孔与所述第三导电连接部电连接，从而使得所述第二晶体管的栅极与所述第二通断控制线电连接。
可选的，所述驱动电路还包括第四晶体管和第十二晶体管；
所述第一晶体管与所述第四晶体管沿第一方向排列，所述第二晶体管与所述第十二晶体管沿第一方向排列；或者，
所述第一晶体管与所述第十二晶体管沿第一方向排列，所述第二晶体管与所述第四晶体管沿第一方向排列。
本公开实施例还提供了一种显示装置，包括上述的驱动电路或上述的显示基板。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是本公开实施例所述的驱动电路的结构图；
图3是本公开实施例所述的驱动电路的结构图；
图4是本公开实施例所述的驱动电路的结构图；
图5是本公开实施例所述的驱动电路的结构图；
图6是本公开实施例所述的驱动电路的结构图；
图7是本公开实施例所述的驱动电路的结构图；
图8是本公开实施例所述的驱动电路的结构图；
图9是图8所示的驱动电路的实施例的工作时序图；
图10是对图8所示的驱动电路的实施例进行仿真后得到的P3的电位的波形图；
图11是本公开实施例所述的驱动电路的电路图；
图12是本公开实施例所述的驱动电路的电路图；
图13是本公开实施例所述的驱动电路的电路图；
图14是本公开所述的显示基板中的驱动电路中的第一晶体管的第一电极和第二电极的一实施例的结构图；
图15是本公开所述的显示基板中的驱动电路中的第二晶体管的第一电极和第二电极的一实施例的结构图；
图16是图20中的栅金属层的布局图；
图17是图20中的源漏金属层的布局图；
图18是图20中的导电层的布局图；
图19是图20中的栅金属层与源漏金属层的叠加后的布局图；
图20是图13所示的驱动电路的实施例对应的布局图(在图20中，示出了栅金属层、源漏金属层、导电层和过孔)；
图21是有源层的布局图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一电极，另一极称为第二电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一电极可以为漏极，所述第二电极可以为源极；或者，所述栅极可以为栅极，所述第一电极可以为源极，所述第二电极可以为漏极。
如图1所示，本公开实施例所述的驱动电路包括第一节点控制电路11、第二节点控制电路12、第三节点控制电路13和输出电路10；
所述第一节点控制电路11与第一节点P1电连接，用于控制所述第一节点P1的电位；
所述第二节点控制电路12与第二节点P2电连接，用于控制所述第二节点P2的电位；
所述第三节点控制电路13分别与通断控制线SW、所述第一节点P1和第三节点P3电连接，用于在所述通断控制线SW提供的通断控制信号的控制下，控制所述第一节点P1和所述第三节点P3之间连通或断开；
所述输出电路10分别与所述第二节点P2、所述第三节点P3和驱动信号端O1电连接，用于在所述第二节点P2的电位和所述第三节点P3的电位的控制下，控制通过所述驱动信号端O1输出驱动信号。
本公开如图1所示的驱动电路的实施例在工作时，在触控阶段，第三节点控制电路13在通断控制信号的控制下，控制所述第一节点P1与所述第三节点P3之间断开，关闭第三节点P3的漏电路径，能够在触控阶段一直保持所述第三节点P3的电位；在显示阶段，第三节点控制电路13在通断控制信号的控制下，控制所述第一节点P1与所述第三节点P3之间连通，以能进行正常显示驱动。
本公开实施例能够避免当触控阶段持续的时间过长时不能保持第三节点P3的高电位，从而导致触控阶段结束后不能正常显示的问题。本公开实施例能够满足不同主动笔协议对触控时间的需求，适用性广，提升触控显示产品竞争力。
本公开实施例切断了P3的漏电路径，从而使得触控显示产品尤其是支持主动笔的触控显示产品在触控阶段结束后，使得第三节点的电位能够维持于高电压，使得驱动信号能够正常输出。本公开实施例能够解决LHB(Long Horizontal Blank，帧内触控检测)模式下的横纹问题，可适用于移动终端、 笔记本电脑等产品上，但不限于此。
可选的，所述第三节点控制电路包括第一晶体管；
所述第一晶体管的栅极与所述通断控制线电连接，所述第一晶体管的第一电极与所述第一节点电连接，所述第一晶体管的第二电极与所述第三节点电连接。
如图2所示，在图1所示的驱动电路的实施例的基础上，所述第三节点控制电路13包括第一晶体管M1；
M1的栅极与通断控制线SW电连接，M1的第一电极与第一节点P1电连接，M1的第二电极与第三节点P3电连接；
M1为n型晶体管。
图2所示的驱动电路的实施例在工作时，在显示阶段，SW输出高电压信号，M1打开；在触控阶段，SW输出低电压信号，M1关断。
在图2所示的驱动电路的至少一实施例中，M1可以为a-Si TFT(非晶硅薄膜晶体管)。由于a-Si TFT长期处于正偏压状态时，其特性曲线会发生右移，导致开启电流Ion下降。当显示阶段持续的时间与触控阶段持续的时间的比值大于1时，M1会处于正偏压状态。在长期工作或信赖性条件下，M1的特性曲线可能会发生右移，从而导致Ion下降，导致驱动信号输出不足。为避免如上问题，本公开至少一实施例通过第三节点控制电路包括两个控制子电路，以在显示阶段交替工作，以避免所述控制子电路包括的晶体管长期处于正偏压状态。
在本公开至少一实施例中，所述通断控制线可以包括第一通断控制线和第二通断控制线；所述第三节点控制电路可以包括第一控制子电路和第二控制子电路；
所述第一控制子电路分别与第一通断控制线、所述第一节点和第三节点电连接，用于在所述第一通断控制线提供的第一通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通或断开；
所述第二控制子电路分别与第二通断控制线、所述第一节点和第三节点电连接，用于在所述第二通断控制线提供的第二通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通或断开。
在优选情况下，可以采用两个通断控制线，并第三节点控制电路可以包括两个控制子电路，在显示阶段，两个控制子电路交替工作(可以在每帧或每隔2s(秒)，切换一次)，以避免所述控制子电路包括的晶体管长期处于正偏压的状态，保证产品的使用寿命。
如图3所示，在图1所示的驱动电路的实施例的基础上，所述通断控制线可以包括第一通断控制线SW1和第二通断控制线SW2；
所述第三节点控制电路包括第一控制子电路31和第二控制子电路32；
所述第一控制子电路31分别与第一通断控制线SW1、所述第一节点P1和第三节点P3电连接，用于在所述第一通断控制线SW1提供的第一通断控制信号的控制下，控制所述第一节点P1与所述第三节点P3之间连通或断开；
所述第二控制子电路32分别与第二通断控制线SW2、所述第一节点P1和第三节点P3电连接，用于在所述第二通断控制线SW2提供的第二通断控制信号的控制下，控制所述第一节点P1与所述第三节点P3之间连通或断开。
本公开如图3所示的驱动电路的至少一实施例在工作时，在触控阶段，第一控制子电路31在第一通断控制信号的控制下，控制所述第一节点P1与所述第三节点P3之间断开，第二控制子电路32在第二通断控制信号的控制下，控制所述第一节点P1与所述第三节点P3之间断开；
在显示阶段，每隔一帧时间或2s，第一控制子电路31和第二控制子电路交替工作，以控制所述第一节点P1和第三节点P3之间连通。
可选的，所述第一控制子电路包括第一晶体管，所述第二控制子电路包括第二晶体管；
所述第一晶体管的栅极与所述第一通断控制线电连接，所述第一晶体管的第一电极与所述第一节点电连接，所述第一晶体管的第二电极与所述第三节点电连接；
所述第二晶体管的栅极与所述第二通断控制线电连接，所述第二晶体管的第一电极与所述第一节点电连接，所述第二晶体管的第二电极与所述第三节点电连接。
如图4所示，在图3所示的驱动电路的至少一实施例的基础上，所述第一控制子电路31包括第一晶体管M1，所述第二控制子电路32包括第二晶体 管M2；
所述第一晶体管M1的栅极与第一通断控制线SW1电连接，所述第一晶体管M1的第一电极与第一节点P1电连接，所述第一晶体管M1的第二电极与所述第三节点P3电连接；
所述第二晶体管M2的栅极与第二通断控制线SW2电连接，所述第二晶体管M2的第一电极与所述第一节点P1电连接，所述第二晶体管M2的第二电极与所述第三节点P3电连接。
在图4所示的至少一实施例中，M1和M2可以都为n型晶体管。
本公开如图4所示的至少一实施例在工作时，在触控阶段，SW1和SW2都输出低电压信号，M1和M2关断；
显示阶段可以包括多个显示时间段，每个显示时间段包括依次设置的第一显示时间段和第二显示时间段；
在第一显示时间段，SW1输出高电压信号，SW2输出低电压信号，M1打开，M2关断，以控制P1与P3之间连通；在第二显示时间段，SW1输出低电压信号，SW2输出高电压信号，M1关断，M2打开，以控制P1与P3之间连通；或者，
在第一显示时间段，SW2输出高电压信号，SW1输出低电压信号，M2打开，M1关断，以控制P1与P3之间连通；在第二显示时间段，SW2输出低电压信号，SW1输出高电压信号，M2关断，M1打开，以控制P1与P3之间连通。
可选的，所述输出电路包括第三晶体管、第四晶体管和存储电容；
所述第三晶体管的栅极与所述第三节点电连接，所述第三晶体管的第二电极与时钟信号线电连接，所述第三晶体管的第一电极与所述驱动信号端电连接；
所述第四晶体管的栅极与所述第二节点电连接，所述第四晶体管的第一电极与所述驱动信号端电连接，所述第四晶体管的第二电极与第一电压线电连接；
所述存储电容的第一极板与所述第三节点电连接，所述存储电容的第二极板与所述驱动信号端电连接。
可选的，所述输出电路还包括第五晶体管；
所述第五晶体管的栅极与帧复位线电连接，所述第五晶体管的第二电极与所述驱动信号端电连接，所述第五晶体管的第一电极与所述第一电压线电连接。
在具体实施时，所述第二节点控制电路可以包括第四节点控制子电路和第二节点控制子电路；
所述第四节点控制子电路分别与第二电压线、第四节点和第一电压线电连接，所述第四节点控制子电路还与所述第一节点或所述第三节点电连接，用于在所述第二电压线提供的第二电压信号的控制下，控制所述第四节点与所述第二电压线之间连通，并在所述第一节点的电位或所述第三节点的电位的控制下，控制所述第四节点与所述第一电压线之间连通；
所述第二节点控制子电路分别与所述第四节点、所述第二电压线、所述第二节点和第一电压线电连接，所述第二节点控制子电路还与所述第一节点或第三节点电连接，用于在所述第四节点的电位的控制下，控制所述第二节点与所述第二电压线之间连通，在所述第一节点的电位或所述第三节点的电位的控制下，控制所述第二节点与所述第一电压线之间连通。
如图5所示，在图1所示的驱动电路的实施例的基础上，所述第二节点控制电路可以包括第四节点控制子电路51和第二节点控制子电路52；
所述第四节点控制子电路51分别与第二电压线V2、第四节点P4、所述第三节点P3和第一电压线V1电连接，用于在所述第二电压线V2提供的第二电压信号的控制下，控制所述第四节点P4与所述第二电压线V2之间连通，并在所述第三节点P3的电位的控制下，控制所述第四节点P4与所述第一电压线V1之间连通；
所述第二节点控制子电路52分别与所述第四节点P4、所述第二电压线V2、所述第二节点P2、第三节点P3和第一电压线V1电连接，用于在所述第四节点P4的电位的控制下，控制所述第二节点P2与所述第二电压线V2之间连通，在所述第三节点P3的电位的控制下，控制所述第二节点P2与所述第一电压线V1之间连通。
在本公开至少一实施例中，第二电压线可以为高电压线，第一电压线可 以为低电压线，但不以此为限。
本公开如图5所示的驱动电路的至少一实施例在工作时，第四节点控制子电路51控制第四节点P4的电位，第二节点控制子电路52控制第二节点P2的电位。
如图6所示，在图1所示的驱动电路的实施例的基础上，所述第二节点控制电路可以包括第四节点控制子电路51和第二节点控制子电路52；
所述第四节点控制子电路51分别与第二电压线V2、第四节点P4、所述第一节点P1和第一电压线V1电连接，用于在所述第二电压线V2提供的第二电压信号的控制下，控制所述第四节点P4与所述第二电压线V2之间连通，并在所述第一节点P1的电位的控制下，控制所述第四节点P4与所述第一电压线V1之间连通；
所述第二节点控制子电路52分别与所述第四节点P4、所述第二电压线V2、所述第二节点P2、第一节点P1和第一电压线V1电连接，用于在所述第四节点P4的电位的控制下，控制所述第二节点P2与所述第二电压线V2之间连通，在所述第一节点P1的电位的控制下，控制所述第二节点P2与所述第一电压线V1之间连通。
在本公开至少一实施例中，第二电压线可以为高电压线，第一电压线可以为低电压线，但不以此为限。
本公开如图6所示的驱动电路的至少一实施例在工作时，第四节点控制子电路51控制第四节点P4的电位，第二节点控制子电路52控制第二节点P2的电位。
可选的，所述第四节点控制子电路包括第六晶体管和第七晶体管；
所述第六晶体管的栅极与所述第六晶体管的第一电极与所述第二电压线电连接，所述第六晶体管的第二电极与所述第四节点电连接；
所述第七晶体管的栅极与所述第一节点或所述第三节点电连接，所述第七晶体管的第一电极与所述第四节点电连接，所述第七晶体管的第二电极与所述第一电压线电连接；
所述第二节点控制子电路包括第八晶体管和第九晶体管；
所述第八晶体管的栅极与所述第四节点电连接，所述第八晶体管的第一 电极与所述第二电压线电连接，所述第八晶体管的第二电极与所述第二节点电连接；
所述第九晶体管的栅极与所述第一节点或所述第三节点电连接，所述第九晶体管的第一电极与所述第二节点电连接，所述第九晶体管的第二电极与所述第一电压线电连接。
在本公开至少一实施例中，所述第一节点控制电路分别与输入端、复位端、帧复位线、第二节点、第一节点和第一电压线电连接，用于在所述输入端提供的输入信号的控制下，控制所述输入端与所述第一节点之间连通，在所述复位端提供的复位信号的控制下，控制所述第一节点与所述第一电压线之间连通，在所述第二节点的电位的控制下，控制所述第一节点与所述第一电压线之间连通，在所述帧复位线提供的帧复位信号的控制下，控制所述第一节点与所述第一电压线之间连通。
如图7所示，在图5所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路11分别与输入端INPUT、复位端RESET、帧复位线TRST、第二节点P2、第一节点P1和第一电压线V1电连接，用于在所述输入端INPUT提供的输入信号的控制下，控制所述输入端INPUT与所述第一节点P1之间连通，在所述复位端RESET提供的复位信号的控制下，控制所述第一节点P1与第一电压线V1之间连通，在第二节点P2的电位的控制下，控制所述第一节点P1与所述第一电压线V1之间连通，在所述帧复位线TRST提供的帧复位信号的控制下，控制所述第一节点与所述第一电压线V1之间连通。
可选的，所述第一节点控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
所述第十晶体管的栅极与所述第十晶体管的第一电极都与所述输入端电连接，所述第十晶体管的第二电极与所述第一节点电连接；
所述第十一晶体管的栅极与所述复位端电连接，所述第十一晶体管的第一电极与所述第一节点电连接，所述第十一晶体管的第二电极与所述第一电压线电连接；
所述第十二晶体管的栅极与所述第二节点电连接，所述第十二晶体管的第一电极与所述第一节点电连接，所述第十二晶体管的第二电极与所述第一 电压线电连接；
第十三晶体管的栅极与所述帧复位线电连接，所述第十三晶体管的第一电极与所述第一节点电连接，所述第十三晶体管的第二电极与所述第一电压线电连接。
如图8所示，在图7所示的驱动电路的至少一实施例的基础上，所述第三节点控制电路13包括第一晶体管M1；所述输出电路包括第三晶体管M3、第四晶体管M4和存储电容C1；
M1的栅极与通断控制线SW电连接，M1的第一电极与第一节点P1电连接，M1的第二电极与第三节点P3电连接；
所述第三晶体管M3的栅极与所述第三节点P3电连接，所述第三晶体管M3的第二电极与时钟信号线CLK电连接，所述第三晶体管M3的第一电极与所述驱动信号端OUTPUT电连接；
所述第四晶体管M4的栅极与所述第二节点P2电连接，所述第四晶体管M4的第一电极与所述驱动信号端OUTPUT电连接，所述第四晶体管M4的第二电极与低电压线VGL电连接；所述低电压线VGL用于提供低电压信号；
所述存储电容C1的第一极板与所述第三节点P3电连接，所述存储电容C1的第二极板与所述驱动信号端OUTPUT电连接；
所述输出电路10还包括第五晶体管M5；
所述第五晶体管M5的栅极与帧复位线TRST电连接，所述第五晶体管M5的第二电极与所述驱动信号端OUTPUT电连接，所述第五晶体管M5的第一电极与低电压线VGL电连接；
所述第四节点控制子电路51包括第六晶体管M6和第七晶体管M7；
所述第六晶体管M6的栅极与所述第六晶体管M6的第一电极与高电压线VGH电连接，所述第六晶体管M6的第二电极与所述第四节点P4电连接；所述高电压线VGH用于提供高电压信号；
所述第七晶体管M7的栅极与所述第三节点P3电连接，所述第七晶体管M7的第一电极与所述第四节点P4电连接，所述第七晶体管M7的第二电极与所述低电压线VGL电连接；
所述第二节点控制子电路52包括第八晶体管M8和第九晶体管M9；
所述第八晶体管M8的栅极与所述第四节点P4电连接，所述第八晶体管M8的第一电极与所述高电压线VGH电连接，所述第八晶体管M8的第二电极与所述第二节点P2电连接；
所述第九晶体管M9的栅极与所述第三节点P3电连接，所述第九晶体管M9的第一电极与所述第二节点P2电连接，所述第九晶体管M9的第二电极与所述低电压线VGL电连接；
所述第一节点控制电路11包括第十晶体管M10、第十一晶体管M11、第十二晶体管M12和第十三晶体管M13；
所述第十晶体管M10的栅极与所述第十晶体管M10的第一电极都与所述输入端INPUT电连接，所述第十晶体管M10的第二电极与所述第一节点P1电连接；
所述第十一晶体管M11的栅极与所述复位端RESET电连接，所述第十一晶体管M11的第一电极与所述第一节点P1电连接，所述第十一晶体管M11的第二电极与所述低电压线VGL电连接；
所述第十二晶体管M12的栅极与所述第二节点P2电连接，所述第十二晶体管M12的第一电极与所述第一节点P1电连接，所述第十二晶体管M12的第二电极与所述低电压线VGL电连接；
第十三晶体管M13的栅极与所述帧复位线TRST电连接，所述第十三晶体管M13的第一电极与所述第一节点P1电连接，所述第十三晶体管M13的第二电极与所述低电压线VGL电连接。
在图8所示的实施例中，所有的晶体管都为n型晶体管。
在本公开至少一实施例中，M7的栅极和M9的栅极优选为都与第一节点P1电连接，以使得在触控阶段，M7和M9打开，以使得P2的电位为低电压，从而保证M4关断，防止在触控阶段由于M4的漏电而使得P3的电位下降。
图8所示的驱动电路的实施例在工作时，在显示阶段，SW输出高电压信号，M1打开，以使得P1和P3之间连通；
如图9所示，在第一时间段S1，INPUT输出高电压信号，M10打开，通过M10对P1进行预充电，P1的电位从低电压变为高电压，同时SW输出高电压信号，M1打开，P1与P3之间连通，为C1正常充电；
在触控阶段S0，INPUT输出低电压信号，SW输出低电压信号，P1与P3之间断开，由于切断了P3与M10、M11、M13和M12的漏电路径，P3的电位维持为高电压；
在第二时间段S2，时钟信号线CLK提供的时钟信号的电位由低电压变为高电压，SW输出高电压信号，P1与P3之间连通，P3的电位被C1自举拉升，M3仍然打开，OUTPUT正常输出；
在第三时间段S3，RESET提供高电压信号，SW提供高电压信号，P1的电位和P3的电位被拉低，驱动电路进入正常的显示工作状态。
图10是对图8所示的驱动电路的实施例进行仿真后得到的P3的电位的波形图，在图10中，标号为S0的为触控阶段。由图10可知，在触控阶段S0，P3的电位能够维持为高电压。
图11所示的驱动电路的实施例与图8所示的驱动电路的实施例的区别如下：M7的栅极和M9的栅极都与第一节点P1电连接。
图12所示的驱动电路的实施例与图8所示的驱动电路的实施例的区别在于：所述通断控制线可以包括第一通断控制线SW1和第二通断控制线SW2；所述第三节点控制电路包括第一控制子电路31和第二控制子电路32；所述第一控制子电路31包括第一晶体管M1，所述第二控制子电路32包括第二晶体管M2；
所述第一晶体管M1的栅极与第一通断控制线SW1电连接，所述第一晶体管M1的第一电极与第一节点P1电连接，所述第一晶体管M1的第二电极与所述第三节点P3电连接；
所述第二晶体管M2的栅极与第二通断控制线SW2电连接，所述第二晶体管M2的第一电极与所述第一节点P1电连接，所述第二晶体管M2的第二电极与所述第三节点P3电连接。
在图12所示的实施例中，所有的晶体管都可以为n型晶体管。
图13所示的驱动电路的实施例与图12所示的驱动电路的实施例的区别如下：M7的栅极和M9的栅极都与第一节点P1电连接。
本公开实施例所述的驱动方法，应用于上述的驱动电路，所述驱动方法包括：
在显示阶段，第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间连通；
在触控阶段，第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间断开。
在本公开实施例所述的驱动方法中，在触控阶段，第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间断开，关闭第三节点的漏电路径，能够在触控阶段一直保持所述第三节点的电位；在显示阶段，第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间连通，以能进行正常显示驱动。
在具体实施时，所述通断控制线可以包括第一通断控制线和第二通断控制线，所述第三节点控制电路可以包括第一控制子电路和第二控制子电路；显示阶段包括多个显示时间段，所述显示时间段包括依次设置的第一显示时间段和第二显示时间段；所述驱动方法包括：
在所述第一显示时间段，第一控制子电路在第一通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通；在所述第二显示时间段，第二控制子电路在第二通断控制信号的控制下，控制所述第一节点与所述第三节点之间连通；或者，
在所述第一显示时间段，第二控制子电路在第二通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通；在所述第二显示时间段，第一控制子电路在第一通断控制信号的控制下，控制所述第一节点与所述第三节点之间连通。
在优选情况下，可以采用两个通断控制线，并第三节点控制电路可以包括两个控制子电路，在显示阶段，两个控制子电路交替工作(可以在每帧或每隔2s，切换一次)，以避免所述控制子电路包括的晶体管长期处于正偏压的状态，保证产品的使用寿命。
在本公开至少一实施例中，所述第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间断开步骤可以包括：
第一控制子电路在第一通断控制信号的控制下，控制所述第一节点和所述第三节点之间断开，第二控制子电路在第二通断控制信号的控制下，控制 所述第一节点和所述第三节点之间断开。
本公开实施例所述的显示基板包括设置于基底上的显示区域以及设置于基底上的周边区域的驱动模组，所述驱动模组包括多级上述的驱动电路；
第三节点控制电路设置于所述输出电路远离所述显示区域的一侧，通断控制线设置于所述第三节点控制电路远离所述输出电路的一侧。
在本公开实施例所述的显示基板中，像素电路设置于基底上的显示区域，所述驱动模组设置于所述基底上的周边区域，所述输出电路、所述第三节点控制电路和所述通断控制线可以沿着远离显示区域的方向依次排列。
在所述驱动模组中，所述驱动电路的输入端与相邻上一级驱动电路的驱动信号端电连接，所述驱动电路的复位端与相邻下一级驱动电路的驱动信号端电连接。
可选的，所述第三节点控制电路包括第一晶体管；
所述第一晶体管包括同层设置的分别呈梳状的第一电极和第二电极；
所述第一晶体管的第一电极包括多个第一梳齿电极部以及连接所述多个第一梳齿电极部的第一梳柄电极部；
所述第一晶体管的第二电极包括多个第二梳齿电极部以及连接所述多个第二梳齿电极部的第二梳柄电极部；
所述第一梳齿电极部与所述第二梳齿电极部间隔排列。
在本公开至少一实施例中，所述第一晶体管可以包括分别呈梳状的第一电极和第二电极；
如图14所示，所述第一晶体管的第一电极包括相互电连接的第一个第一梳齿电极部111、第二个第一梳齿电极部112、第三个第一梳齿电极部113和第一梳柄电极部110；
所述第一晶体管的第二电极包括相互电连接的第一个第二梳齿电极部121、第二个第二梳齿电极部122、第三个第二梳齿电极部123、第四个第二梳齿电极部124和第二梳柄电极部120；
第一个第二梳齿电极部121、第一个第一梳齿电极部111、第二个第二梳齿电极部122、第二个第一梳齿电极部112、第三个第二梳齿电极部123、第三个第一梳齿电极部113和第四个第二梳齿电极部124沿第二方向依次排列。
在图14所示的实施例中，所述第二方向为横向，在显示区域中设置有栅线，所述栅线包括沿横向延伸的部分。
图14所示的结构仅为所述第一晶体管的结构的一种实施例，并不用于限定第一晶体管的结构。
在具体实施时，所述通断控制线可以沿第一方向延伸；所述第一晶体管还包括栅极，所述栅极与所述通断控制线设置于同一层；所述显示基板还包括第一导电连接部、第二导电连接部、第一导电转接部和第二导电转接部；
所述第一导电连接部与所述第一晶体管的栅极位于同一层并相互电连接，所述第二导电连接部与所述第一晶体管的第一电极位于同一层，所述第一导电转接部与所述第二导电转接部同层设置，所述第一导电转接部与所述第一导电连接部和所述第二导电连接部位于不同层；
所述通断控制线通过第一过孔与所述第一导电转接部电连接，所述第一导电转接部通过第二过孔与所述第二导电连接部电连接，所述第二导电连接部通过第三过孔与所述第二导电转接部电连接，所述第二导电转接部通过第四过孔与所述第一导电连接部电连接，从而使得所述第一晶体管的栅极与所述通断控制线电连接。
在本公开实施例中，第一导电连接部、通断控制线与第一晶体管的栅极位于同一层，第二导电连接部、所述第一晶体管的第一电极和所述第一晶体管的第二电极位于同一层，所述第一导电转接部和所述第二导电转接部位于同一层；
所述通断控制线与所述第一晶体管的栅极通过第一导电转接部和第二导电转接部相互电连接。
可选的，所述显示基板可以包括依次设置于所述基底上的有源层、第一绝缘层、栅金属层、第二绝缘层、源漏金属层、第三绝缘层和导电层；对所述栅金属层进行构图工艺，以形成驱动电路中的晶体管的栅极、时钟信号线、高电压线、低电压线、通断控制线和第一导电连接部，对所述源漏金属层进行构图工艺，以形成驱动电路中的晶体管的第一电极、所述驱动电路中的晶体管的第二电极和第二导电连接部，对所述导电层进行构图工艺，以形成第一导电转接部和第二导电转接部；
所述通断控制线通过贯穿所述第二绝缘层和所述第三绝缘层的第一过孔与第一导电转接部电连接，第一导电转接部通过贯穿所述第三绝缘层的第二过孔与所述第二导电连接部电连接，所述第二导电连接部通过贯穿所述第三绝缘层的第三过孔与所述第二导电转接部电连接，所述第二导电转接部通过贯穿所述第二绝缘层和所述第三绝缘层的第四过孔与所述第一导电连接部电连接，以使得所述通断控制线与所述第一晶体管的栅极电连接。
在本公开至少一实施例中，所述导电层可以由ITO(氧化铟锡)制成。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
可选的，所述驱动电路还包括第四晶体管和第十二晶体管；
所述第一晶体管与所述第四晶体管沿第一方向排列，或者，所述第一晶体管与所述第十二晶体管沿第一方向排列。
在具体实施时，第一晶体管与驱动电路包括的第四晶体管沿第一方向排列，或者，所述第一晶体管与驱动电路包括的第十二晶体管沿第一方向排列，以缩窄所述周边区域沿第二方向的宽度，利于实现窄边框。
在本公开至少一实施例中，所述第一方向与第二方向相交，在显示区域中设置有多行栅线和多列数据线；第一方向可以为与数据线的延伸方向大致相同的方向，第二方向可以为与栅线的延伸方向大致相同的方向。
在具体实施时，所述第三节点控制电路还可以包括第二晶体管；所述第二晶体管包括分别呈梳状的第一电极和第二电极；所述第一晶体管的第一电极、所述第二晶体管的第一电极和第二晶体管的第二电极同层设置；
所述第二晶体管的第一电极包括多个第三梳齿电极部以及连接所述多个第三梳齿电极部的第三梳柄电极部；
所述第二晶体管的第二电极包括多个第四梳齿电极部以及连接所述多个第四梳齿电极部的第四梳柄电极部；
所述第三梳齿电极部与所述第四梳齿电极部间隔排列；
所述第三梳柄电极部与所述第一梳柄电极部电连接，所述第四梳柄电极部与所述第二梳柄部电连接。
如图15所示，所述第二晶体管的第一电极包括相互电连接的第一个第三梳齿电极部131、第二个第三梳齿电极部132、第三个第三梳齿电极部133和第三梳柄电极部130；
所述第二晶体管的第二电极包括相互电连接的第一个第四梳齿电极部141、第二个第四梳齿电极部142、第四个第二梳齿电极部143、第四个第四梳齿电极部144和第四梳柄电极部140；
第一个第四梳齿电极部141、第一个第三梳齿电极部131、第二个第四梳齿电极部142、第二个第三梳齿电极部132、第三个第四梳齿电极部143、第三个第三梳齿电极部133和第四个第四梳齿电极部144沿第二方向依次排列。
在本公开实施例中，所述第一晶体管和第二晶体管可以沿第二方向排列；
所述第二方向与第一方向相交。
可选的，所述通断控制线包括同层设置的第一通断控制线和第二通断控制线；所述第一通断控制线沿第一方向延伸，所述第二通断控制线沿第一方向延伸；
所述第一晶体管和所述第二晶体管还分别包括栅极，所述栅极与所述第一通断控制线设置于同一层；所述显示基板还包括第一导电连接部、第二导电连接部、第一导电转接部、第二导电转接部、第三导电连接部、第四导电连接部、第三导电转接部和第四导电转接部；所述第一导电转接部、所述第二导电转接部、所述第三导电转接部和所述第四导电转接部同层设置；
所述第一导电连接部与所述第一晶体管的栅极位于同一层并相互电连接，所述第二导电连接部与所述第一晶体管的第一电极位于同一层，所述第一导电转接部与所述第一导电连接部和所述第二导电连接部位于不同层；
所述第一通断控制线通过第一过孔与所述第一导电转接部电连接，所述第一导电转接部通过第二过孔与所述第二导电连接部电连接，所述第二导电连接部通过第三过孔与所述第二导电转接部电连接，所述第二导电转接部通过第四过孔与所述第一导电连接部电连接，从而使得所述第一晶体管的栅极 与所述第一通断控制线电连接；
所述第三导电连接部与所述第二晶体管的栅极位于同一层并相互电连接，所述第四导电连接部与所述第二晶体管的第一电极位于同一层，所述第三导电转接部与所述第三导电连接部和所述第四导电连接部位于不同层；
所述第二通断控制线通过第五过孔与所述第三导电转接部电连接，所述第三导电转接部通过第六过孔与所述第四导电连接部电连接，所述第四导电连接部通过第七过孔与所述第四导电转接部电连接，所述第四导电转接部通过第八过孔与所述第三导电连接部电连接，从而使得所述第二晶体管的栅极与所述第二通断控制线电连接。
可选的，所述显示基板可以包括依次设置于所述基底上的有源层、第一绝缘层、栅金属层、第二绝缘层、源漏金属层、第三绝缘层和导电层；
对所述栅金属层进行构图工艺，以形成驱动电路中的晶体管的栅极、时钟信号线、高电压线、低电压线、第一通断控制线、第二通断控制线、第一导电连接部和第三导电连接部，对所述源漏金属层进行构图工艺，以形成驱动电路中的晶体管的第一电极、所述驱动电路中的晶体管的第二电极、第二导电连接部和第四导电连接部，对所述导电层进行构图工艺，以形成第一导电转接部、第二导电转接部、第三导电连接部和第四导电连接部；
所述第一通断控制线通过贯穿所述第二绝缘层和所述第三绝缘层的第一过孔与第一导电转接部电连接，第一导电转接部通过贯穿所述第三绝缘层的第二过孔与所述第二导电连接部电连接，所述第二导电连接部通过贯穿所述第三绝缘层的第三过孔与所述第二导电转接部电连接，所述第二导电转接部通过贯穿所述第二绝缘层和所述第三绝缘层的第四过孔与所述第一导电连接部电连接，以使得所述第一通断控制线与所述第一晶体管的栅极电连接；
所述第二通断控制线通过贯穿所述第二绝缘层和所述第三绝缘层的第五过孔与第三导电转接部电连接，第三导电转接部通过贯穿所述第三绝缘层的第六过孔与所述第四导电连接部电连接，所述第四导电连接部通过贯穿所述第三绝缘层的第七过孔与所述第四导电转接部电连接，所述第四导电转接部通过贯穿所述第二绝缘层和所述第三绝缘层的第八过孔与所述第三导电连接部电连接，以使得所述第二通断控制线与所述第二晶体管的栅极电连接。
在具体实施时，所述驱动电路还可以包括第四晶体管和第十二晶体管；
所述第一晶体管与所述第四晶体管沿第一方向排列，所述第二晶体管与所述第十二晶体管沿第一方向排列；或者，
所述第一晶体管与所述第十二晶体管沿第一方向排列，所述第二晶体管与所述第四晶体管沿第一方向排列；
以缩窄所述周边区域沿第二方向的宽度，利于实现窄边框。
图20是图13所示的驱动电路的实施例对应的布局图(在图20中，示出了栅金属层、源漏金属层、导电层和过孔)，图16是图20中的栅金属层的布局图，17是图20中的源漏金属层的布局图，图18是图20中的导电层的布局图，图19是图20中的栅金属层与源漏金属层的叠加后的布局图。图21是有源层的布局图。
在图16中，标号为G1的为第一晶体管的栅极，标号为L1的为第一导电连接部，标号为G2的为第二晶体管的栅极，标号为L3的为第三导电连接部，标号为SW1的为第一通断控制线，标号为SW2的为第二通断控制线，标号为VGL的为低电压线，标号为VGH的为高电压线。
在图17中，标号为L2的为第二导电连接部，标号为L4的为第四导电连接部，标号为181的为T1包括的电极单元，T1包括的电极单元181包括图13中的T1的第一电极和T1的第二电极，标号为182的为T2包括的电极单元，T2的电极单元182包括图13中的T2的第一电极和T2的第二电极。
在图18中，标号为Z1的为第一导电转接部，标号为Z2的为第二导电转接部，标号为Z3的为第三导电转接部，标号为Z4的为第四导电转接部。
在图20中，标号为H1的为第一过孔，标号为H2的为第二过孔，标号为H3的为第三过孔，标号为H4的为第四过孔，标号为H5的为第五过孔，标号为H6的为第六过孔，标号为H7的为第七过孔，标号为H8的为第八过孔。
如图20所示，所述第一通断控制线SW1通过第一过孔H1与所述第一导电转接部Z1电连接，所述第一导电转接部Z1通过第二过孔H2与所述第二导电连接部L2电连接，所述第二导电连接部L2通过第三过孔H3与所述第二导电转接部Z2电连接，所述第二导电转接部Z2通过第四过孔H4与所 述第一导电连接部L1电连接，从而使得所述第一晶体管的栅极G1与所述第一通断控制线SW1电连接；
所述第二通断控制线SW2通过第五过孔H5与所述第三导电转接部Z3电连接，所述第三导电转接部Z3通过第六过孔H6与所述第四导电连接部L4电连接，所述第四导电连接部L4通过第七过孔H7与所述第四导电转接部Z4电连接，所述第四导电转接部Z4通过第八过孔H8与所述第三导电连接部L3电连接，从而使得所述第二晶体管的栅极G2与所述第二通断控制线SW2电连接。
如图17所示，所述驱动电路中的晶体管的第一电极和所述驱动电路中的晶体管的第二电极都为梳状电极。
在图17中，标号为181的为M1包括的电极单元，M1包括的电极单元181包括M1的第一电极和M1的第二电极；
标号为182的为M2包括的电极单元，M2包括的电极单元182包括M2的第一电极和M2的第二电极；
标号为183的为M3包括的电极单元，M3包括的电极单元183包括M3的第一电极和M3的第二电极；
标号为184的为M4包括的电极单元，M4包括的电极单元184包括M4的第一电极和M4的第二电极；
标号为185的为M5包括的电极单元，M5包括的电极单元185包括M5的第一电极和M5的第二电极；
标号为186的为M6包括的电极单元，M6包括的电极单元186包括M6的第一电极和M6的第二电极；
标号为187的为M7包括的电极单元，M7包括的电极单元187包括M7的第一电极和M7的第二电极；
标号为188的为M8包括的电极单元，M8包括的电极单元188包括M8的第一电极和M8的第二电极；
标号为189的为M9包括的电极单元，M9包括的电极单元189包括M9的第一电极和M9的第二电极；
标号为1810的为M10包括的电极单元，M10包括的电极单元1810包括 M10的第一电极和M10的第二电极；
标号为1811的为M11包括的电极单元，M11包括的电极单元1811包括M11的第一电极和M11的第二电极；
标号为1812的为M12包括的电极单元，M12包括的电极单元1812包括M12的第一电极和M12的第二电极；
标号为1813的为M13包括的电极单元，M13包括的电极单元1813包括M13的第一电极和M13的第二电极。
在图17中，标号为C1b的为C1的第二极板，标号为OUTPUT的为驱动信号端。
在图17中，标号为L6的为第六导电连接部，所述第六导电连接部L6用于电连接时钟信号线CLK和M3的第二电极。
在图16中，标号为G3的为M3的栅极，标号为G4的为M4的栅极，标号为G5的为M5的栅极，标号为G7的为M7的栅极，标号为G8的为M8的栅极，标号为G9的为M9的栅极，标号为G10的为M10的栅极，标号为G11的为M11的栅极，标号为G12的为M12的栅极，标号为G13的为M13的栅极。
如图16所示，高电压线VGH复用为M6的栅极，帧复位线复用为M13的栅极G13和M5的栅极G5。
如图16所示，M3的栅极G3与C1的第一极板C1a电连接，M11的栅极G11与复位端RESET电连接，M10的栅极G10与输入端INPUT电连接。
在图16中，标号为L5的为第五导电连接部；L5用于电连接所述第五晶体管的第一电极和所述第十三晶体管的第二电极。
如图16所示，M1的栅极和M12的栅极沿第一方向排列，M2的栅极和M4的栅极沿第一方向排列；
如图17所示，M1的电极单元181和M12的电极单元1812沿第一方向排列，M2的电极单元182和M4的电极单元184沿第一方向排列；
以使得M1和M12沿第一方向排列，M2与M4沿第一方向排列，以缩短所述周边区域沿第二方向的宽度，利于实现窄边框。
如图17所示，C1的第二极板C1b与M3的电极单元183中的M3的第 一电极电连接，C1的第二极板C1b与驱动信号端OUTPUT电连接。
如图17所示，M1的第一电极、M2的第一电极、M13的第一电极和M10的第二电极都与第三节点P3电连接；
M1的第二电极、M2的第二电极、M12的第一电极和M11的第一电极都与第一节点P1电连接；
M8的第二电极和M9的第一电极分别与第二节点P2电连接。
在图21中，标号为221的为M1的有源层图形，标号为222的为M2的有源层图形，标号为223的为M3的有源层图形，标号为224的为M4的有源层图形，标号为225的为M5的有源层图形，标号为226的为M6的有源层图形，标号为227的为M7的有源层图形，标号为228的为M8的有源层图形，标号为229的为M9的有源层图形，标号为210的为M10的有源层图形，标号为211的为M11的有源层图形，标号为212的为M12的有源层图形，标号为213的为M13的有源层图形。
本公开至少一实施例显示装置包括上述的驱动电路，或者，本公开至少一实施例所述的显示装置包括上述的显示基板。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (21)

  1. 一种驱动电路，包括第一节点控制电路、第二节点控制电路、第三节点控制电路和输出电路；
    所述第一节点控制电路与第一节点电连接，用于控制所述第一节点的电位；
    所述第二节点控制电路与第二节点电连接，用于控制所述第二节点的电位；
    所述第三节点控制电路分别与通断控制线、所述第一节点和第三节点电连接，用于在所述通断控制线提供的通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通或断开；
    所述输出电路分别与所述第二节点、所述第三节点和驱动信号端电连接，用于在所述第二节点的电位和所述第三节点的电位的控制下，控制通过所述驱动信号端输出驱动信号。
  2. 如权利要求1所述的驱动电路，其中，所述第三节点控制电路包括第一晶体管；
    所述第一晶体管的栅极与所述通断控制线电连接，所述第一晶体管的第一电极与所述第一节点电连接，所述第一晶体管的第二电极与所述第三节点电连接。
  3. 如权利要求1所述的驱动电路，其中，所述通断控制线包括第一通断控制线和第二通断控制线；所述第三节点控制电路包括第一控制子电路和第二控制子电路；
    所述第一控制子电路分别与第一通断控制线、所述第一节点和第三节点电连接，用于在所述第一通断控制线提供的第一通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通或断开；
    所述第二控制子电路分别与第二通断控制线、所述第一节点和第三节点电连接，用于在所述第二通断控制线提供的第二通断控制信号的控制下，控制所述第一节点和所述第三节点之间连通或断开。
  4. 如权利要求3所述的驱动电路，其中，所述第一控制子电路包括第一 晶体管，所述第二控制子电路包括第二晶体管；
    所述第一晶体管的栅极与所述第一通断控制线电连接，所述第一晶体管的第一电极与所述第一节点电连接，所述第一晶体管的第二电极与所述第三节点电连接；
    所述第二晶体管的栅极与所述第二通断控制线电连接，所述第二晶体管的第一电极与所述第一节点电连接，所述第二晶体管的第二电极与所述第三节点电连接。
  5. 如权利要求1至4中任一权利要求所述的驱动电路，其中，所述输出电路包括第三晶体管、第四晶体管和存储电容；
    所述第三晶体管的栅极与所述第三节点电连接，所述第三晶体管的第二电极与时钟信号线电连接，所述第三晶体管的第一电极与所述驱动信号端电连接；
    所述第四晶体管的栅极与所述第二节点电连接，所述第四晶体管的第一电极与所述驱动信号端电连接，所述第四晶体管的第二电极与第一电压线电连接；
    所述存储电容的第一极板与所述第三节点电连接，所述存储电容的第二极板与所述驱动信号端电连接。
  6. 如权利要求5所述的驱动电路，其中，所述输出电路还包括第五晶体管；
    所述第五晶体管的栅极与帧复位线电连接，所述第五晶体管的第二电极与所述驱动信号端电连接，所述第五晶体管的第一电极与所述第一电压线电连接。
  7. 如权利要求1至4中任一权利要求所述的驱动电路，其中，所述第二节点控制电路包括第四节点控制子电路和第二节点控制子电路；
    所述第四节点控制子电路分别与第二电压线、第四节点和第一电压线电连接，所述第四节点控制子电路还与所述第一节点或所述第三节点电连接，用于在所述第二电压线提供的第二电压信号的控制下，控制所述第四节点与所述第二电压线之间连通，并在所述第一节点的电位或所述第三节点的电位的控制下，控制所述第四节点与所述第一电压线之间连通；
    所述第二节点控制子电路分别与所述第四节点、所述第二电压线、所述第二节点和第一电压线电连接，所述第二节点控制子电路还与所述第一节点或第三节点电连接，用于在所述第四节点的电位的控制下，控制所述第二节点与所述第二电压线之间连通，在所述第一节点的电位或所述第三节点的电位的控制下，控制所述第二节点与所述第一电压线之间连通。
  8. 如权利要求7所述的驱动电路，其中，所述第四节点控制子电路包括第六晶体管和第七晶体管；
    所述第六晶体管的栅极与所述第六晶体管的第一电极与所述第二电压线电连接，所述第六晶体管的第二电极与所述第四节点电连接；
    所述第七晶体管的栅极与所述第一节点或所述第三节点电连接，所述第七晶体管的第一电极与所述第四节点电连接，所述第七晶体管的第二电极与所述第一电压线电连接；
    所述第二节点控制子电路包括第八晶体管和第九晶体管；
    所述第八晶体管的栅极与所述第四节点电连接，所述第八晶体管的第一电极与所述第二电压线电连接，所述第八晶体管的第二电极与所述第二节点电连接；
    所述第九晶体管的栅极与所述第一节点或所述第三节点电连接，所述第九晶体管的第一电极与所述第二节点电连接，所述第九晶体管的第二电极与所述第一电压线电连接。
  9. 如权利要求1至4中任一权利要求所述的驱动电路，其中，所述第一节点控制电路分别与输入端、复位端、帧复位线、第二节点、第一节点和第一电压线电连接，用于在所述输入端提供的输入信号的控制下，控制所述输入端与所述第一节点之间连通，在所述复位端提供的复位信号的控制下，控制所述第一节点与所述第一电压线之间连通，在所述第二节点的电位的控制下，控制所述第一节点与所述第一电压线之间连通，在所述帧复位线提供的帧复位信号的控制下，控制所述第一节点与所述第一电压线之间连通。
  10. 如权利要求9所述的驱动电路，其中，所述第一节点控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
    所述第十晶体管的栅极与所述第十晶体管的第一电极都与所述输入端电 连接，所述第十晶体管的第二电极与所述第一节点电连接；
    所述第十一晶体管的栅极与所述复位端电连接，所述第十一晶体管的第一电极与所述第一节点电连接，所述第十一晶体管的第二电极与所述第一电压线电连接；
    所述第十二晶体管的栅极与所述第二节点电连接，所述第十二晶体管的第一电极与所述第一节点电连接，所述第十二晶体管的第二电极与所述第一电压线电连接；
    第十三晶体管的栅极与所述帧复位线电连接，所述第十三晶体管的第一电极与所述第一节点电连接，所述第十三晶体管的第二电极与所述第一电压线电连接。
  11. 一种驱动方法，应用于如权利要求1至10中任一权利要求所述的驱动电路，所述驱动方法包括：
    在显示阶段，第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间连通；
    在触控阶段，第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间断开。
  12. 如权利要求11所述的驱动方法，其中，所述通断控制线包括第一通断控制线和第二通断控制线，所述第三节点控制电路包括第一控制子电路和第二控制子电路；
    所述第三节点控制电路在通断控制信号的控制下，控制所述第一节点与所述第三节点之间断开步骤包括：
    第一控制子电路在第一通断控制信号的控制下，控制所述第一节点和所述第三节点之间断开，第二控制子电路在第二通断控制信号的控制下，控制所述第一节点和所述第三节点之间断开。
  13. 一种显示基板，包括设置于基底上的显示区域以及设置于基底上的周边区域的驱动模组，所述驱动模组包括多级如权利要求1至10中任一权利要求所述的驱动电路；
    第三节点控制电路设置于所述输出电路远离所述显示区域的一侧，通断控制线设置于所述第三节点控制电路远离所述输出电路的一侧。
  14. 如权利要求13所述的显示基板，其中，所述第三节点控制电路包括第一晶体管；
    所述第一晶体管包括同层设置的分别呈梳状的第一电极和第二电极；
    所述第一晶体管的第一电极包括多个第一梳齿电极部以及连接所述多个第一梳齿电极部的第一梳柄电极部；
    所述第一晶体管的第二电极包括多个第二梳齿电极部以及连接所述多个第二梳齿电极部的第二梳柄电极部；
    所述第一梳齿电极部与所述第二梳齿电极部间隔排列。
  15. 如权利要求14所述的显示基板，其中，所述通断控制线沿第一方向延伸；所述第一晶体管还包括栅极，所述栅极与所述通断控制线设置于同一层；所述显示基板还包括第一导电连接部、第二导电连接部、第一导电转接部和第二导电转接部；
    所述第一导电连接部与所述第一晶体管的栅极位于同一层并相互电连接，所述第二导电连接部与所述第一晶体管的第一电极位于同一层，所述第一导电转接部与所述第二导电转接部同层设置，所述第一导电转接部与所述第一导电连接部和所述第二导电连接部位于不同层；
    所述通断控制线通过第一过孔与所述第一导电转接部电连接，所述第一导电转接部通过第二过孔与所述第二导电连接部电连接，所述第二导电连接部通过第三过孔与所述第二导电转接部电连接，所述第二导电转接部通过第四过孔与所述第一导电连接部电连接，从而使得所述第一晶体管的栅极与所述通断控制线电连接。
  16. 如权利要求15所述的显示基板，其中，所述驱动电路还包括第四晶体管和第十二晶体管；
    所述第一晶体管与所述第四晶体管沿第一方向排列，或者，所述第一晶体管与所述第十二晶体管沿第一方向排列。
  17. 如权利要求14所述的显示基板，其中，所述第三节点控制电路还包括第二晶体管；所述第二晶体管包括分别呈梳状的第一电极和第二电极；所述第一晶体管的第一电极、所述第二晶体管的第一电极和第二晶体管的第二电极同层设置；
    所述第二晶体管的第一电极包括多个第三梳齿电极部以及连接所述多个第三梳齿电极部的第三梳柄电极部；
    所述第二晶体管的第二电极包括多个第四梳齿电极部以及连接所述多个第四梳齿电极部的第四梳柄电极部；
    所述第三梳齿电极部与所述第四梳齿电极部间隔排列；
    所述第三梳柄电极部与所述第一梳柄电极部电连接，所述第四梳柄电极部与所述第二梳柄部电连接。
  18. 如权利要求17所述的显示基板，其中，所述第一晶体管和第二晶体管沿第二方向排列；
    所述第二方向与第一方向相交。
  19. 如权利要求17所述的显示基板，其中，所述通断控制线包括同层设置的第一通断控制线和第二通断控制线；所述第一通断控制线沿第一方向延伸，所述第二通断控制线沿第一方向延伸；
    所述第一晶体管和所述第二晶体管还分别包括栅极，所述栅极与所述第一通断控制线设置于同一层；所述显示基板还包括第一导电连接部、第二导电连接部、第一导电转接部、第二导电转接部、第三导电连接部、第四导电连接部、第三导电转接部和第四导电转接部；所述第一导电转接部、所述第二导电转接部、所述第三导电转接部和所述第四导电转接部同层设置；
    所述第一导电连接部与所述第一晶体管的栅极位于同一层并相互电连接，所述第二导电连接部与所述第一晶体管的第一电极位于同一层，所述第一导电转接部与所述第一导电连接部和所述第二导电连接部位于不同层；
    所述第一通断控制线通过第一过孔与所述第一导电转接部电连接，所述第一导电转接部通过第二过孔与所述第二导电连接部电连接，所述第二导电连接部通过第三过孔与所述第二导电转接部电连接，所述第二导电转接部通过第四过孔与所述第一导电连接部电连接，从而使得所述第一晶体管的栅极与所述第一通断控制线电连接
    所述第三导电连接部与所述第二晶体管的栅极位于同一层并相互电连接，所述第四导电连接部与所述第二晶体管的第一电极位于同一层，所述第三导电转接部与所述第三导电连接部和所述第四导电连接部位于不同层；
    所述第二通断控制线通过第五过孔与所述第三导电转接部电连接，所述第三导电转接部通过第六过孔与所述第四导电连接部电连接，所述第四导电连接部通过第七过孔与所述第四导电转接部电连接，所述第四导电转接部通过第八过孔与所述第三导电连接部电连接，从而使得所述第二晶体管的栅极与所述第二通断控制线电连接。
  20. 如权利要求19所述的显示基板，其中，所述驱动电路还包括第四晶体管和第十二晶体管；
    所述第一晶体管与所述第四晶体管沿第一方向排列，所述第二晶体管与所述第十二晶体管沿第一方向排列；或者，
    所述第一晶体管与所述第十二晶体管沿第一方向排列，所述第二晶体管与所述第四晶体管沿第一方向排列。
  21. 一种显示装置，包括如权利要求1至10中任一权利要求所述的驱动电路或如权利要求13至20中任一权利要求所述的显示基板。
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JP2019040027A (ja) * 2017-08-24 2019-03-14 株式会社半導体エネルギー研究所 表示装置、入出力装置、情報処理装置
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