WO2022267113A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022267113A1
WO2022267113A1 PCT/CN2021/106774 CN2021106774W WO2022267113A1 WO 2022267113 A1 WO2022267113 A1 WO 2022267113A1 CN 2021106774 W CN2021106774 W CN 2021106774W WO 2022267113 A1 WO2022267113 A1 WO 2022267113A1
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WO
WIPO (PCT)
Prior art keywords
pixel
driving circuit
chip
display
pixel row
Prior art date
Application number
PCT/CN2021/106774
Other languages
English (en)
French (fr)
Inventor
李德彦
陈剑鸿
杜鹏
陈小明
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/438,449 priority Critical patent/US11961437B2/en
Publication of WO2022267113A1 publication Critical patent/WO2022267113A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • Text Tuner is a software technology developed by Microsoft to improve the readability of text on existing displays, making the text on the screen appear clearer and more distinct.
  • the driver circuit board is located on the long side of the display screen, and the scan drive circuit is located on the short side of the display panel.
  • the text tuner is turned on, there may be Display problems such as font deformation.
  • Tri-gate driver architecture In order to improve the display effect, reduce the number of source driver chips used, and reduce the manufacturing cost and power consumption, a tri-gate driver architecture has been proposed by those skilled in the art.
  • the Tri-gate driver architecture although the number of chip-on-chip films used can be reduced to a certain extent to achieve the purpose of reducing the production cost, there is a corresponding problem in the driver architecture when the ClearType algorithm is used to display fonts. The font displayed on the display screen is easily deformed, and the display effect is not ideal.
  • the embodiments of the present application provide a display panel and a display device, which are used to solve the problem of font deformation in display devices in the prior art.
  • An embodiment of the present application provides a display panel, including:
  • a display substrate includes a first long side, a second long side, a first short side and a second short side, the first long side is parallel to the second long side, and the first short side is parallel to the second long side the second short side is parallel;
  • the display substrate includes gate signal lines and data signal lines arranged in an array, and pixel units arranged in the intersection area of the gate signal lines and the data signal lines, and a plurality of the pixel units are arranged on the display substrate A plurality of pixel rows are formed, each of the pixel units includes a plurality of sub-pixels, and each sub-pixel is correspondingly connected to the gate signal line and the data signal line;
  • the array substrate column scanning driving circuit is arranged in the region corresponding to the long edge of the display substrate, and correspondingly connected to the gate signal line;
  • a driving circuit board is arranged in the area corresponding to the short side edge of the display substrate, and is correspondingly connected to the data signal line;
  • a chip-on-chip film, the chip-on-chip film is arranged in the area corresponding to the short edge of the display substrate, and one end of the chip-on-chip film is connected to the display substrate, and the other end of the chip-on-chip film is connected to the drive circuit board;
  • the array substrate column scanning driving circuit includes a first array substrate column scanning driving circuit and a second array substrate column scanning driving circuit, wherein the first array substrate column scanning driving circuit is arranged on the first long side On the edge, the column scanning driving circuit of the second array substrate is disposed on the edge of the second long side.
  • the pixel row includes a first pixel row, a second pixel row and a third pixel row arranged in sequence, and the first pixel row, the second pixel row and the third pixel row are arranged correspondingly There are a first data line and a second data line;
  • the 2i-1th pixel unit in the first pixel row is connected to the first data line
  • the 2ith pixel unit in the second pixel row is connected to the first data line
  • the 2i-1th pixel unit in the second pixel row is connected to the second data line, and the 2ith pixel unit in the third pixel row is connected to the second data line; i is an integer And greater than 0.
  • a data line is arranged between two adjacent pixel rows
  • a scanning line is arranged between two adjacent pixel columns
  • each of the plurality of sub-pixels arranged along the short side corresponds to the same scanning line.
  • the driving circuit board and the chip-on-chip film are correspondingly arranged in corresponding regions of short edges on both sides of the display substrate.
  • the pixel unit includes red sub-pixels, blue sub-pixels and green sub-pixels.
  • the red sub-pixels, the blue sub-pixels and the green sub-pixels are arranged in sequence along the short side of the display substrate.
  • the embodiment of the present application also provides a display panel, including:
  • a display substrate includes a first long side, a second long side, a first short side and a second short side, the first long side is parallel to the second long side, and the first short side is parallel to the second long side the second short side is parallel;
  • the display substrate includes gate signal lines and data signal lines arranged in an array, and pixel units arranged in the intersection area of the gate signal lines and the data signal lines, and a plurality of the pixel units are arranged on the display substrate A plurality of pixel rows are formed, each of the pixel units includes a plurality of sub-pixels, and each sub-pixel is correspondingly connected to the gate signal line and the data signal line;
  • the array substrate column scanning driving circuit is arranged in the region corresponding to the long edge of the display substrate, and correspondingly connected to the gate signal line;
  • a driving circuit board is arranged in the area corresponding to the short side edge of the display substrate, and is correspondingly connected to the data signal line;
  • a chip-on-chip film, the chip-on-chip film is arranged in the area corresponding to the short edge of the display substrate, and one end of the chip-on-chip film is connected to the display substrate, and the other end of the chip-on-chip film is connected to the drive circuit board.
  • the array substrate column scanning driving circuit includes a first array substrate column scanning driving circuit and a second array substrate column scanning driving circuit, wherein the first array substrate column scanning driving circuit is arranged on the first long side On the edge, the column scanning driving circuit of the second array substrate is disposed on the edge of the second long side.
  • the pixel row includes a first pixel row, a second pixel row and a third pixel row arranged in sequence, and the first pixel row, the second pixel row and the third pixel row are arranged correspondingly There are a first data line and a second data line;
  • the 2i-1th pixel unit in the first pixel row is connected to the first data line
  • the 2ith pixel unit in the second pixel row is connected to the first data line
  • the 2i-1th pixel unit in the second pixel row is connected to the second data line, and the 2ith pixel unit in the third pixel row is connected to the second data line; i is an integer And greater than 0.
  • a data line is arranged between two adjacent pixel rows
  • a scanning line is arranged between two adjacent pixel columns
  • each of the plurality of sub-pixels arranged along the short side corresponds to the same scanning line.
  • the driving circuit board and the chip-on-chip film are correspondingly arranged in corresponding regions of short edges on both sides of the display substrate.
  • the number of the chip-on-chip films disposed in the area corresponding to the short edge of the display substrate is two or three.
  • the pixel unit includes red sub-pixels, blue sub-pixels and green sub-pixels.
  • the red sub-pixels, the blue sub-pixels and the green sub-pixels are arranged in sequence along the short side of the display substrate.
  • the embodiment of the present application also provides a display device, including a display panel, and the display panel includes:
  • a display substrate includes a first long side, a second long side, a first short side and a second short side, the first long side is parallel to the second long side, and the first short side is parallel to the second long side the second short side is parallel;
  • a plurality of pixel units are arranged in an array on the display substrate, and each of the pixel units includes a plurality of sub-pixels arranged adjacently, and forms a plurality of pixel rows;
  • the array substrate column scanning driving circuit is arranged in the region corresponding to the long edge of the display substrate, and correspondingly connected to the gate signal line;
  • a driving circuit board is arranged in the area corresponding to the short side edge of the display substrate, and is correspondingly connected to the data signal line;
  • a chip-on-chip film, the chip-on-chip film is arranged in the area corresponding to the short edge of the display substrate, and one end of the chip-on-chip film is connected to the display substrate, and the other end of the chip-on-chip film is connected to the drive circuit board.
  • the array substrate column scanning driving circuit includes a first array substrate column scanning driving circuit and a second array substrate column scanning driving circuit, wherein the first array substrate column scanning driving circuit is arranged on the first long side On the edge, the column scanning driving circuit of the second array substrate is disposed on the edge of the second long side.
  • the driving circuit board and the chip-on-chip film are correspondingly arranged in corresponding regions of short edges on both sides of the display substrate.
  • the pixel row includes a first pixel row, a second pixel row and a third pixel row, and the first pixel row, the second pixel row and the third pixel row are correspondingly provided with first a data line and a second data line;
  • the 2i-1th pixel unit in the first pixel row is connected to the first data line
  • the 2ith pixel unit in the second pixel row is connected to the first data line
  • the 2i-1th pixel unit in the second pixel row is connected to the second data line, and the 2ith pixel unit in the third pixel row is connected to the second data line; i is an integer And greater than 0.
  • a data line is arranged between two adjacent pixel rows
  • a scanning line is arranged between two adjacent pixel columns
  • each of the plurality of sub-pixels arranged along the short side corresponds to the same scanning line.
  • the driving circuit board is located on the short side of the display panel, the chip-on-chip film is connected to the driving circuit board and the display panel, the column scanning driving circuit of the array substrate is located on the long side of the display panel, and the display pixels maintain RGB color along the long side of the display panel.
  • the column scanning driving circuit of the array substrate is connected to the gate, and the driving circuit board is connected to the data line.
  • the driving circuit board is arranged on the long side of the display panel, and the column scanning driving circuit of the array substrate is arranged on the short side of the display panel.
  • the embodiment of the present application can achieve the effect of improving font deformation.
  • Fig. 1 is the structural representation of the traditional Tri-gate design that the embodiment of the present application provides;
  • FIG. 2 is a schematic diagram of a first structure of a display device provided by an embodiment of the present application
  • FIG. 3 is a second structural schematic diagram of a display device provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a corresponding display effect of an existing display panel during normal display
  • FIG. 5 is a schematic diagram of a display effect after adopting the Tri-gate-new architecture in the embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a traditional Tri-gate design provided in the embodiment of the present application.
  • FIG. 2 is a first structural schematic diagram of the display device provided by the embodiment of the present application
  • FIG. 3 is a second structural schematic diagram of the display device provided by the embodiment of the present application.
  • the display device 50 corresponding to the traditional Tri-gate structure includes a display panel 500, and the display panel 500 includes two long sides 511, two short sides 512, a first array substrate row scanning driving circuit 521 , the second array substrate row scanning driving circuit 522 , the driving circuit board 523 , the first sub-pixel row 531 and the second sub-pixel row 532 .
  • a scanning line 534 is further arranged between the first sub-pixel row 531 and the second sub-pixel row 532 .
  • each sub-pixel column includes a plurality of pixel units, and each pixel unit includes a plurality of sub-pixels, such as red sub-pixel R, green sub-pixel G, and blue sub-pixel B, so RGB three-color sub-pixels Pixels make up a pixel unit.
  • a plurality of pixel units contained therein are arranged sequentially along the short side of the display panel, and the connections of the data lines 535 to the pixel units in the column direction are misaligned left and right, as shown in FIG. 1 .
  • the embodiment of the present application provides a connection structure inside the display panel, so as to effectively improve the blurring of the display panel. Specifically, please refer to Fig. 2 and Fig. 3 .
  • the embodiment of the present application provides a new connection architecture (Tri-gate-new), and applies the Tri-gate-new architecture to a display panel or other display devices.
  • the display device provided in the embodiment of the present application may be a television, a monitor or other display devices.
  • the display device has a long side and a short side. That is to say, relative to the viewer, in the visual display of the display panel, the long side corresponds to the horizontal direction of vision, and the short side corresponds to the vertical direction of vision, or the length corresponding to the long side of the display panel is greater than that of the short side in terms of visual display. The corresponding length value.
  • a plurality of RGB three-color sub-pixels are sequentially arranged along the long side of the display panel, thereby forming the display device provided by the embodiment of the present application, as shown in FIG. 2 .
  • the display device 20 includes: a display panel 100 , a driving circuit board 400 , a chip-on-chip film 600 and an array substrate column scanning driving circuit 800 .
  • the display device 20 includes a display panel 100, the display panel 100 includes a first long side 120, a second long side 140, a first short side 160 and a second short side 180, the first long side 120 is parallel to the second long side 140 , and the first short side 160 is parallel to the second short side 180 .
  • the display panel 100 may be a rectangular structure. It can be understood that the first long side 120 , the second long side 140 , the first short side 160 and the second short side 180 are sequentially connected to form a rectangle.
  • the display area of the display device 20 includes a plurality of pixel units 21, and the plurality of pixel units 21 are arranged in an array in the display panel to form a light-emitting display area of the display panel.
  • each pixel unit 21 includes a plurality of light-emitting sub-pixels, and the plurality of light-emitting sub-pixels are arranged adjacently in sequence.
  • the red sub-pixel R, the blue sub-pixel B and the green sub-pixel G are used as examples for the description of the light-emitting sub-pixels.
  • the light-emitting sub-pixels may also be other colors, which will not be described in detail here.
  • the pixel unit 21 has a plurality of sub-pixels, and the sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.
  • the sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.
  • a plurality of pixel columns are formed in the column direction of the display panel.
  • the first pixel column 226 and the second pixel column 228 wherein the first pixel column 226 and the second pixel column 228 are adjacent.
  • a plurality of RGB three-color sub-pixels are arranged in sequence along the first long side 120 to form a plurality of pixel rows 220 , such as a first pixel row 222 and a second pixel row 224 .
  • the display device 20 further includes a driving circuit board 400 located outside the edge of the first short side 160 ; and a chip-on-chip film 600 .
  • a driving circuit board 400 located outside the edge of the first short side 160 ; and a chip-on-chip film 600 .
  • the driving circuit board 400 may only be disposed in a position corresponding to the edge of one short side of the display panel, or disposed in a position corresponding to the edges of the short sides of both sides of the display panel.
  • the display device 20 further includes an array substrate column scanning driving circuit 800 , and the array substrate column scanning driving circuit 800 is correspondingly connected to the gate signal lines of the display panel, that is, the scanning signal lines through wires.
  • the array substrate column scanning driving circuit 800 includes a first array substrate column scanning driving circuit 820 and a second array substrate column scanning driving circuit 840, wherein the first array substrate column scanning driving circuit 820 is arranged on the edge of the first long side 120, and the second The array substrate column scanning driving circuit 840 is disposed on the edge of the second long side 140 .
  • the array substrate column scanning driving circuit 800 may also only include the first array substrate column scanning driving circuit 820 , and the first array substrate column scanning driving circuit 820 is disposed on the edge of the first long side 120 .
  • the length of the array substrate column scanning driving circuit 800 is shorter than the length of the long side of the display panel 100 , and the length of the driving circuit board 400 is smaller than the length of the short side of the display panel 100 .
  • first gap 401 a between the driving circuit board 400 and the first short side 160 , and two chip-on-chip films are located in the first gap 401 a.
  • a scanning line 260 is provided between every two adjacent pixel columns, and the adjacent two pixel columns include a first pixel column 226 and a second pixel column 228 , the first The pixel row 226 is adjacent to the second pixel row 228 , and each sub-pixel in the second pixel row 228 is correspondingly connected to the scan line 260 .
  • the long side of the display panel is the first long side or the second long side; the short side of the display panel is the first short side or the second short side.
  • the traditional Tri-gate structure design requires two chip-on-chips, but this embodiment only needs two chip-on-chips, and the cost is the same; for an ultra-high-definition display device, the traditional Tri-gate The architecture design requires four chip-on-chip films, but this embodiment only needs three chip-on-chip films, which can save costs to a greater extent and effectively simplify the manufacturing process of the panel.
  • the display device 20 includes a display panel 100, the display panel 100 includes a first long side 120, a second long side 140, a first short side 160, and a second short side 180, and the first long side 120 and The second long side 140 is parallel, and the first short side 160 is parallel to the second short side 180 .
  • the display area of the display device 20 includes a plurality of pixel units 21, and the plurality of pixel units 21 are arrayed in the display panel to form a light-emitting display area of the display panel.
  • each pixel unit 21 is arranged in an array, a plurality of pixel columns are formed in the column direction of the display panel.
  • the first pixel column 226 and the second pixel column 228 wherein the first pixel column 226 and the second pixel column 228 are adjacent.
  • a plurality of RGB three-color sub-pixels are arranged in sequence along the first long side 120 to form a plurality of pixel rows 220 , such as a first pixel row 222 and a second pixel row 224 .
  • the display device 20 also includes a driving circuit board, which is correspondingly connected to the data signal lines.
  • the driving circuit board includes a first driving circuit board 420 and a second driving circuit board 440.
  • the first driving circuit board 420 is located on the side of the first short side 160. Outside the edge, the second driving circuit board 440 is located outside the edge of the second short side 180 .
  • the display device 20 also includes a chip-on-chip film, and the chip-on-chip film includes at least two first chip-on-chip films 620 and at least two second chip-on-chip films 640; the first chip-on-chip film 620 connects the first short side 160 with the first drive circuit The board 420 is connected; the second COF 640 connects the second short side 180 with the second driving circuit board 440 . Please continue to refer to FIG.
  • the display device 20 further includes an array substrate column scanning driving circuit 800
  • the array substrate column scanning driving circuit 800 includes a first array substrate column scanning driving circuit 820 and a second array substrate column scanning driving circuit 840, wherein the second The array substrate row scanning driving circuit 840 is arranged on the edge of the first long side 120 , the second array substrate row scanning driving circuit 840 is arranged on the edge of the second long side 140 , and the array substrate row scanning driving circuit 800 is correspondingly connected to the scanning lines 260 .
  • the lengths of the first array substrate column scanning driving circuit 820 and the second array substrate column scanning driving circuit 840 are the same, and both are shorter than the length of the long side of the display panel 100, and the lengths of the first driving circuit board 420 and the second driving circuit board 440 The lengths are the same, and both are smaller than the length of the short side of the display panel 100 .
  • FIG. 3 there is a first gap 401a between the first driving circuit board 420 and the first short side 160, and two first chip-on-chip films 620 are arranged at intervals in the first gap 401a; the second driving circuit There is a second gap 401 b between the board 440 and the second short side 180 , and two second chip-on-chip films 640 are disposed in the second gap 401 b at intervals.
  • a data line is provided between every two adjacent pixel rows 220 .
  • the pixel rows are illustrated by taking the first pixel row 222 , the second pixel row 224 and the third pixel row 236 as examples.
  • the first pixel row 222 , the second pixel row 224 and the third pixel row 236 are adjacently arranged.
  • the data lines between two adjacent pixel rows are described by taking the first data line 250 and the second data line 240 as examples.
  • the pixel unit 21 in the corresponding pixel row includes a plurality of RGB three-color sub-pixels.
  • the two adjacent pixel rows 220 include a first pixel row 222, a second pixel row 224, and a third pixel row 236, and the RGB three-color sub-pixels 201 and the second The data line 240 is connected, and the RGB three-color sub-pixels 201 in the even-numbered arrangement order in the second pixel row 224 are connected to the second data line 240.
  • two adjacent pixel units are respectively connected to two adjacent data lines. corresponding connection.
  • each pixel unit 21 when each pixel unit 21 is arranged and connected to the data line, for the same pixel row, the pixel units 21 are successively arranged adjacent to each other. Therefore, each pixel unit 21 can be numbered.
  • the pixel units 21 are sequentially labeled as 1, 2, 3, 4...i. Wherein, i ⁇ 1, and i is an integer.
  • the 2i-1th pixel unit (such as the 1st, 3rd, 5th%) is connected to the first data line 250, and in the second pixel row 224, in the second pixel row 224
  • the 2i-th pixel unit (such as the 2nd, 4th, 6th, 8th . . . ) is connected to the first data line 250 at the same time.
  • the 2i-1th pixel unit is equivalent to an odd-numbered sequence of pixel units
  • 2i is equivalent to an even-numbered sequence of pixel units.
  • the 2i-1th pixel unit in the second pixel row 224 is connected to the second data line 240, and the 2ith pixel unit in the third pixel row 236
  • the cells are connected to the second data line 240 at the same time.
  • the pixel units of the odd sequence and the pixel units of the even sequence are respectively connected to the data lines in different rows, thereby improving the structure of the display panel and effectively solving the problem of the display panel.
  • the displayed font is easily deformed.
  • each pixel row 220 is connected to a second data line 240 , and each multiple RGB three-color sub-pixels arranged along the long side corresponds to the same second data line 240 .
  • a scanning line 260 is arranged between every two adjacent pixel columns, and the adjacent two pixel columns include a first pixel column 226 and a second pixel column 228 , and in the second pixel column 228 Each RGB three-color sub-pixel is connected to the scan line 260 .
  • FIG. 4 is a schematic diagram of a display effect corresponding to a conventional display panel when displaying normally.
  • Figure a is a schematic diagram of the display state of the existing architecture during standard input
  • Figure b is a schematic diagram of the actual display effect of the fonts of the existing architecture during standard input.
  • each sub-pixel is a red sub-pixel 27 , a green sub-pixel 28 , a blue sub-pixel 29 and a black area 30 .
  • the arrangement of each pixel is: the red sub-pixel 27 , the green sub-pixel 28 , and the blue sub-pixel 29 are arranged in sequence, and the black area 30 is adjacent to the blue sub-pixel 29 .
  • the “vertical” area contains a group of multiple RGB three-color sub-pixels arranged along the short side of the display panel, and the blue sub-pixels in the multiple RGB three-color sub-pixels Pixel B then turns into a black state, and the width or range of the black area 30 displayed during the display process is also small.
  • the "vertical" display effect on the left side of the letter “D” will produce a jagged appearance, thereby causing the font to continue When displayed, the edges of the font appear blurred and display poorly.
  • FIG. 5 is a schematic diagram of a display effect after adopting the Tri-gate-new architecture in the embodiment of the present application.
  • figure c is a schematic diagram of the display effect in the standard display state
  • figure d is a schematic diagram of the actual display effect after adopting the Tri-gate-new architecture. Due to the change of the existing structural relationship, when displaying, the blue sub-pixel 29 adjacent to the black area 30 among the plurality of RGB three-color sub-pixels becomes black, that is, B+RGB. As shown in figure c, the blue sub-pixel 29 to the right of the green sub-pixel 28 transitions to a black state.
  • the width of the black area 30 will further increase during actual display, as shown in the actual display effect diagram in figure d, the width of the left and right sides of the black area 30 is greater than that in the standard display state The width of the corresponding black area 30 . Therefore, when displaying, the display effect of the font displayed in the embodiment of the present application will be further enhanced, and the width of the font will be increased, thereby effectively improving the problems of font deformation and poor display effect in traditional designs.
  • the driving circuit of the present invention and the corresponding chip-on-chip film are arranged on the short side of the display panel, and the scanning driving circuit is arranged in the glass substrate on the long side.
  • Font algorithm for a full HD display device, the normal architecture design requires six chip-on-films, but this embodiment only needs two chip-on-films, which can save costs to a greater extent while improving font deformation;
  • the traditional design requires four COFs, but this embodiment only needs four COFs, and the effect of improving font deformation is achieved at the same cost.

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Abstract

一种显示面板(100)及显示装置(20)，显示面板(100)包括长边、短边、显示像素、阵列基板列扫描驱动电路(800)、驱动电路板(400)以及覆晶薄膜(600)，每个覆晶薄膜(600)的一端连接短边，另一端连接驱动电路板(400)。驱动电路板(400)与阵列基板列扫描驱动电路(800)分别位于显示面板(100)的短边和长边，从而达到改善字体在显示容易变形的问题。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及显示装置。
 背景技术
文本调谐器（ClearType）是由微软开发的软件技术，用于改善现有显示屏上的文本可读性，使屏幕上的文字看起来更清晰明显。当前，对于市场上大多数的针对监视器或者电视的显示屏来说，驱动电路板位于显示屏的长边，而扫描驱动电路位于显示面板的短边，在打开文本调谐器时，有可能出现字体变形等显示问题。
为了提高显示效果并减少源极驱动芯片的使用数目，降低制造成本与使用功耗，三栅极(Tri-gate)驱动架构被本领域的技术人员提出。在Tri-gate驱动架构中，虽然能在一定程度上减少所使用的覆晶薄膜的数量，达到降低制备成本的目的，但是，其驱动架构存在着当运行ClearType算法对字体进行显示时，对应的显示屏上显示的字体容易变形，显示效果不理想等问题。
因此，有必要提供一种新的驱动架构以改善显示面板在显示时，字体容易变形的问题，同时降低面板的制备成本，提高显示效果。
 技术问题
综上所述，现有的驱动架构在对文本进行显示时，其驱动架构存在着当运行ClearType算法对字体进行显示时，对应的显示屏上显示的字体容易变形，显示效果不理想等问题。
 技术解决方案
为解决上述问题，本申请实施例提供一种显示面板及显示装置，用于解决现有技术中显示装置在显示时，存在字体变形的问题。
为解决上述技术问题，本申请实施例提供的技术方法如下：
本申请实施例提供一种显示面板，包括：
显示基板，所述显示基板包括第一长边、第二长边、第一短边和第二短边，所述第一长边与所述第二长边平行，所述第一短边与所述第二短边平行；
所述显示基板包括阵列设置的栅极信号线和数据信号线，以及设置在所述栅极信号线和所述数据信号线相交区域内的像素单元，多个所述像素单元在所述显示基板上形成多条像素行，每个所述像素单元包括多个子像素，且每个子像素对应的与所述栅极信号线和所述数据信号线连接；
阵列基板列扫描驱动电路，所述阵列基板列扫描驱动电路设置于所述显示基板的长边边缘对应区域内，并与所述栅极信号线对应连接；
驱动电路板，所述驱动电路板设置于所述显示基板的短边边缘对应区域内，并与所述数据信号线对应连接；以及，
覆晶薄膜，所述覆晶薄膜设置于所述显示基板的短边边缘对应区域内，且所述覆晶薄膜的一端连接于所述显示基板，所述覆晶薄膜的另一端连接于所述驱动电路板；
其中，所述驱动电路板与所述第一短边之间具有第一间隙，所述覆晶薄膜设置于所述第一间隙内。
进一步地，所述阵列基板列扫描驱动电路包括第一阵列基板列扫描驱动电路和第二阵列基板列扫描驱动电路，其中所述第一阵列基板列扫描驱动电路设置于所述第一长边的边缘，所述第二阵列基板列扫描驱动电路设置于所述第二长边的边缘。
进一步地，所述像素行包括依次设置的第一像素行、第二像素行以及第三像素行，所述第一像素行、所述第二像素行以及所述第三像素行之间对应设置有第一数据线和第二数据线；
其中，所述第一像素行中的第2i-1个像素单元与所述第一数据线连接，且所述第二像素行中的第2i个像素单元与所述第一数据线连接；
所述第二像素行中的第2i-1个像素单元与所述第二数据线连接，且所述第三像素行中的第2i个像素单元与所述第二数据线连接；i为整数且大于0。
进一步地，相邻两像素行之间设置有一条数据线，相邻两像素列之间设置有一条扫描线，且每一条沿短边排列的所述多个子像素对应同一条所述扫描线。
进一步地，所述驱动电路板和所述覆晶薄膜对应的设置在所述显示基板的两侧的短边边缘对应区域内。
进一步地，其中所述像素单元内包括红色子像素、蓝色子像素和绿色子像素。
进一步地，其中所述红色子像素、所述蓝色子像素和所述绿色子像素沿着所述显示基板的短边依次排列。
本申请实施例还提供一种显示面板，包括：
显示基板，所述显示基板包括第一长边、第二长边、第一短边和第二短边，所述第一长边与所述第二长边平行，所述第一短边与所述第二短边平行；
所述显示基板包括阵列设置的栅极信号线和数据信号线，以及设置在所述栅极信号线和所述数据信号线相交区域内的像素单元，多个所述像素单元在所述显示基板上形成多条像素行，每个所述像素单元包括多个子像素，且每个子像素对应的与所述栅极信号线和所述数据信号线连接；
阵列基板列扫描驱动电路，所述阵列基板列扫描驱动电路设置于所述显示基板的长边边缘对应区域内，并与所述栅极信号线对应连接；
驱动电路板，所述驱动电路板设置于所述显示基板的短边边缘对应区域内，并与所述数据信号线对应连接；以及，
覆晶薄膜，所述覆晶薄膜设置于所述显示基板的短边边缘对应区域内，且所述覆晶薄膜的一端连接于所述显示基板，所述覆晶薄膜的另一端连接于所述驱动电路板。
进一步地，所述阵列基板列扫描驱动电路包括第一阵列基板列扫描驱动电路和第二阵列基板列扫描驱动电路，其中所述第一阵列基板列扫描驱动电路设置于所述第一长边的边缘，所述第二阵列基板列扫描驱动电路设置于所述第二长边的边缘。
进一步地，所述像素行包括依次设置的第一像素行、第二像素行以及第三像素行，所述第一像素行、所述第二像素行以及所述第三像素行之间对应设置有第一数据线和第二数据线；
其中，所述第一像素行中的第2i-1个像素单元与所述第一数据线连接，且所述第二像素行中的第2i个像素单元与所述第一数据线连接；
所述第二像素行中的第2i-1个像素单元与所述第二数据线连接，且所述第三像素行中的第2i个像素单元与所述第二数据线连接；i为整数且大于0。
进一步地，相邻两像素行之间设置有一条数据线，相邻两像素列之间设置有一条扫描线，且每一条沿短边排列的所述多个子像素对应同一条所述扫描线。
进一步地，所述驱动电路板和所述覆晶薄膜对应的设置在所述显示基板的两侧的短边边缘对应区域内。
进一步地，所述显示基板的短边边缘对应区域内设置的所述覆晶薄膜数量为两个或三个。
进一步地，所述像素单元内包括红色子像素、蓝色子像素和绿色子像素。
进一步地，所述红色子像素、所述蓝色子像素和所述绿色子像素沿着所述显示基板的短边依次排列。
本申请实施例还提供一种显示装置，包括显示面板，所述显示面板包括：
显示基板，所述显示基板包括第一长边、第二长边、第一短边和第二短边，所述第一长边与所述第二长边平行，所述第一短边与所述第二短边平行；
所述显示基板上阵列设置有多个像素单元，每个所述像素单元包括相邻设置的多个子像素，并形成多条像素行；
阵列基板列扫描驱动电路，所述阵列基板列扫描驱动电路设置于所述显示基板的长边边缘对应区域内，并与所述栅极信号线对应连接；
驱动电路板，所述驱动电路板设置于所述显示基板的短边边缘对应区域内，并与所述数据信号线对应连接；以及，
覆晶薄膜，所述覆晶薄膜设置于所述显示基板的短边边缘对应区域内，且所述覆晶薄膜的一端连接于所述显示基板，所述覆晶薄膜的另一端连接于所述驱动电路板。
进一步地，所述阵列基板列扫描驱动电路包括第一阵列基板列扫描驱动电路和第二阵列基板列扫描驱动电路，其中所述第一阵列基板列扫描驱动电路设置于所述第一长边的边缘，所述第二阵列基板列扫描驱动电路设置于所述第二长边的边缘。
进一步地，所述驱动电路板和所述覆晶薄膜对应的设置在所述显示基板的两侧的短边边缘对应区域内。
进一步地，所述像素行包括第一像素行、第二像素行以及第三像素行，所述第一像素行、所述第二像素行以及所述第三像素行之间对应设置有第一数据线和第二数据线；
其中，所述第一像素行中的第2i-1个像素单元与所述第一数据线连接，且所述第二像素行中的第2i个像素单元与所述第一数据线连接；
所述第二像素行中的第2i-1个像素单元与所述第二数据线连接，且所述第三像素行中的第2i个像素单元与所述第二数据线连接；i为整数且大于0。
进一步地，相邻两像素行之间设置有一条数据线，相邻两像素列之间设置有一条扫描线，且每一条沿短边排列的所述多个子像素对应同一条所述扫描线。
 有益效果
综上所述，本申请实施例的有益效果为：
本申请实施例，驱动电路板位于显示面板的短边，覆晶薄膜连接驱动电路板与显示面板，阵列基板列扫描驱动电路位于显示面板的长边，显示像素沿显示面板的长边保持RGB的排布方式，阵列基板列扫描驱动电路连接栅极，驱动电路板连接数据线，相比现有技术将驱动电路板设于显示面板的长边，阵列基板列扫描驱动电路设于显示面板的短边，本申请实施例可以达到改善字体变形的效果。
 附图说明
图1为本申请实施例提供的传统Tri-gate设计的结构示意图；
图2为本申请实施例提供的显示装置的第一结构示意图；
图3为本申请实施例提供的显示装置的第二结构示意图；
图4为现有的显示面板在正常显示时对应的显示效果示意图；
图5为本申请实施例中采用Tri-gate-new架构后的显示效果示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
如图1所示，图1为本申请实施例提供的传统Tri-gate设计的结构示意图。以及请参阅图2至图3，图2为本申请实施例提供的显示装置的第一结构示意图，图3为本申请实施例提供的显示装置的第二结构示意图。
请参阅图1，可以理解的是，传统的Tri-gate架构对应的显示装置50包括显示面板500，显示面板500包括两个长边511、两个短边512、第一阵列基板行扫描驱动电路521、第二阵列基板行扫描驱动电路522、驱动电路板523、第一子像素行531和第二子像素行532。其中，第一子像素行531和第二子像素行532之间还设置有一扫描线534。
进一步的，在显示面板的列方向上，相邻两子像素列之间均设置有一数据线535。并且在列方向，每一子像素列中均包括多个像素单元，每个像素单元内包括多个子像素，如红色子像素R、绿色子像素G以及蓝色子像素B，因此RGB三色子像素组成一个像素单元。其中包含的多个像素单元沿显示面板的短边依次排列，并且数据线535在列方向与像素单元的连接左右错位，如图1所示。
本申请实施例中提供一种显示面板内部的连接架构，以有效的改善面板在显示时模糊不清的问题。具体的，请参阅图2和图3。
具体的，本申请实施例提供一种新的连接架构（Tri-gate-new），并将该Tri-gate-new架构应用在显示面板或其他显示设备中。本申请实施例中提供的显示装置可为电视、监视器或其他显示设备。其中，该显示设备具有长边和短边之分。即相对观察者而言，显示面板在视觉显示上，长边对应着视觉的水平方向，短边对应着视觉的竖直方向，或者显示面板在视觉显示上，其长边对应的长度大于短边对应的长度值。在设置该Tri-gate-new架构时，将多个RGB三色子像素沿显示面板的长边依次排列，从而形成本申请实施例提供的显示装置，如图2所示。
具体的，本申请实施例中，显示装置20包括：显示面板100，驱动电路板400，覆晶薄膜600和阵列基板列扫描驱动电路800。
请参阅图2，可以理解的是，显示装置20包括显示面板100，显示面板100包括第一长边120、第二长边140、第一短边160和第二短边180，第一长边120与第二长边140平行，第一短边160与第二短边180平行。
可以理解的是，显示面板100可为矩形结构。可以理解的是，第一长边120、第二长边140、第一短边160和第二短边180依次连接构成矩形。
可以理解的是，显示装置20的显示区域内包括多个像素单元21，多个像素单元21在显示面板内阵列设置，并形成显示面板的发光显示区。其中，每个像素单元21内均包括多个发光子像素，多个发光子像素依次相邻设置。本申请实施例中，发光子像素以红色子像素R、蓝色子像素B以及绿色子像素G为例进行说明。其中，发光子像素还可为其他颜色，这里不再详细赘述。
具体的，请参图2，像素单元21具有多个子像素，该子像素包括红色子像素R、绿色子像素G以及蓝色子像素B。同时，由于各个像素单元21阵列设置，因此在显示面板的列方向上，形成多个像素列。如第一像素列226和第二像素列228，其中，第一像素列226和第二像素列228相邻。而在显示面板的行方向上，多个RGB三色子像素沿第一长边120方向依次排列，并形成多个像素行220，如第一像素行222和第二像素行224等。
可以理解的是，显示装置20还包括驱动电路板400，驱动电路板400位于第一短边160的边缘的外侧；以及覆晶薄膜600。覆晶薄膜600的数量为至少两个，每个覆晶薄膜600的一端连接第一短边160，另一端连接驱动电路板400，驱动电路板400还通过引线与显示面板显示区域内的各个数据线对应连接。本申请实施例中，驱动电路板400可只设置在显示面板的一侧短边的边缘对应的位置内，或设置在显示面板的两侧的短边的边缘对应位置内。
请继续参阅图3，显示装置20还包括阵列基板列扫描驱动电路800，阵列基板列扫描驱动电路800通过引线与显示面板的栅极信号线，即扫描信号线对应连接。阵列基板列扫描驱动电路800包括第一阵列基板列扫描驱动电路820和第二阵列基板列扫描驱动电路840，其中第一阵列基板列扫描驱动电路820设置于第一长边120的边缘，第二阵列基板列扫描驱动电路840设置于第二长边140的边缘。
可以理解的是，阵列基板列扫描驱动电路800也可以只包括第一阵列基板列扫描驱动电路820，第一阵列基板列扫描驱动电路820设置于第一长边120的边缘。
其中，阵列基板列扫描驱动电路800的长度小于显示面板100长边的长度，驱动电路板400的长度小于显示面板100短边的长度。
具体地，请继续参阅图3，驱动电路板400与第一短边160之间具有第一间隙401a，两颗覆晶薄膜位于第一间隙401a内。
请继续参阅图3，本申请实施例中，每相邻两条像素列之间设有一条扫描线260，相邻的两条像素列包括第一像素列226和第二像素列228，第一像素列226与第二像素列228相邻，且第二像素列228中的每个子像素均与扫描线260对应连接。
可以理解的是，显示面板的长边为第一长边或第二长边；显示面板的短边为第一短边或第二短边。
另外，对于全高清的显示装置，传统的Tri-gate架构设计需要两个覆晶薄膜，而本实施例也只需要两个覆晶薄膜，成本相同；对于超高清显示装置，传统的Tri-gate架构设计需要四个覆晶薄膜，而本实施例却只需要三个覆晶薄膜，可以更大程度的节约成本，并有效的简化了面板的制备工艺。
进一步的，请参阅图3，显示装置20包括显示面板100，显示面板100包括第一长边120、第二长边140、第一短边160和第二短边180，第一长边120与第二长边140平行，第一短边160与第二短边180平行。
显示装置20的显示区域内包括多个像素单元21，多个像素单元21在显示面板内阵列设置，并形成显示面板的发光显示区。
由于各个像素单元21阵列设置，因此在显示面板的列方向上，形成多个像素列。如第一像素列226和第二像素列228，其中，第一像素列226和第二像素列228相邻。而在显示面板的行方向上，多个RGB三色子像素沿第一长边120方向依次排列，并形成多个像素行220，如第一像素行222和第二像素行224。
显示装置20还包括驱动电路板，驱动电路板与数据信号线对应连接，驱动电路板包括第一驱动电路板420和第二驱动电路板440，第一驱动电路板420位于第一短边160的边缘外侧，第二驱动电路板440位于第二短边180的边缘外侧。
显示装置20还包括覆晶薄膜，覆晶薄膜包括至少两个第一覆晶薄膜620和至少两个第二覆晶薄膜640；第一覆晶薄膜620将第一短边160与第一驱动电路板420连接；第二覆晶薄膜640将第二短边180与第二驱动电路板440连接。请继续参阅图3，显示装置20还包括阵列基板列扫描驱动电路800，阵列基板列扫描驱动电路800包括第一阵列基板列扫描驱动电路820和第二阵列基板列扫描驱动电路840，其中第二阵列基板列扫描驱动电路840设置于第一长边120的边缘，第二阵列基板列扫描驱动电路840设置于第二长边140的边缘，阵列基板列扫描驱动电路800与扫描线260对应连接。
其中，第一阵列基板列扫描驱动电路820和第二阵列基板列扫描驱动电路840的长度相同，且均小于显示面板100长边的长度，第一驱动电路板420和第二驱动电路板440的长度相同，且均小于显示面板100短边的长度。
具体地，请继续参阅图3，第一驱动电路板420与第一短边160之间具有第一间隙401a，两颗第一覆晶薄膜620间隔设置于第一间隙401a内；第二驱动电路板440与第二短边180之间具有第二间隙401b，两颗第二覆晶薄膜640间隔设置于第二间隙401b内。
请继续参阅图3，其中，每相邻的两条像素行220之间设有一条数据线。本申请实施例中，像素行以第一像素行222、第二像素行224以及第三像素行236为例进行说明。其中，第一像素行222、第二像素行224以及第三像素行236相邻设置。同时，相邻两像素行之间的数据线以第一数据线250和第二数据线240为例进行说明。
并且，在对应的像素行内的像素单元21中，包括多个RGB三色子像素。具体的，相邻的两条像素行220包括第一像素行222、第二像素行224以及第三像素行236，第一像素行222中位于基数排列次序的RGB三色子像素201与第二数据线240连接，第二像素行224中位于偶数排列次序的RGB三色子像素201与第二数据线240连接，同一行中，相邻的两个像素单元分别与相邻的两条数据线对应连接。
具体的，在设置各像素单元21以及与所述数据线连接时，对于同一像素行而言，像素单元21依次相邻设置。因此，可对每个像素单元21进行标号。优选的，像素单元21依次标号为1、2、3、4···i。其中，i≥1，且i为整数。
在第一像素行222中，第2i-1个像素单元（如第1、3、5···）与第一数据线250连接，且在第二像素行224中，第二像素行224中的第2i个像素单元（如第2、4、6、8···）同时与该第一数据线250连接。其中，第2i-1个像素单元即相当于奇数序列像素单元，2i相当于偶数序列的像素单元。
同时，在第二像素行224以及第三像素行236中，第二像素行224中的第2i-1个像素单元与第二数据线240连接，且第三像素行236中的第2i个像素单元同时与第二数据线240连接。这样，就形成了同一行像素中，奇数序列的像素单元和偶数序列的像素单元分别与不同行中的数据线对应连接，从而对显示面板中的架构进行改善，并有效的解决了面板在进行画面显示时，显示的字体容易变形的问题。
其中，每一像素行220连接有一条第二数据线240，每一条沿长边排列的多个RGB三色子像素对应同一条第二数据线240。
请继续参阅图3，其中，每相邻两条像素列之间设有一条扫描线260，相邻的两条像素列包括第一像素列226和第二像素列228，第二像素列228中的每个RGB三色子像素均与扫描线260连接。
进一步的，如图4所示，图4为现有的显示面板在正常显示时对应的显示效果示意图。其中，a图为现有架构在标准输入时的显示状态示意图，b图为现有架构在标准输入时字体实际的显示效果示意图。
如图4中所示，在上述像素单元中，各子像素分别为红色子像素27、绿色子像素28、蓝色子像素29以及黑色区域30。其各像素的排列为：红色子像素27、绿色子像素28、蓝色子像素29依次排列，同时，黑色区域30与蓝色子像素29相邻。
在传统Tri-gate设计的结构中，在对字体画面进行显示时，以字母“D”左边的“竖”为例进行说明。传统的Tri-gate架构设计在文本调谐器开启时，该“竖”区域包含一组沿显示面板的短边排列的多个RGB三色子像素，多个RGB三色子像素中的蓝色子像素B则转变为黑色状态，并且，显示过程中显示的黑色区域30的宽度或者范围也较小，此时字母“D”左边的“竖”的显示效果会产生锯齿状，从而造成字体在进行显示时，字体边缘看起来变模糊了，显示效果较差。
如图5所示，图5为本申请实施例中采用Tri-gate-new架构后的显示效果示意图。其中，c图为标准显示状态下显示效果示意图，d图为采用Tri-gate-new架构后的实际显示效果示意图。由于改变了现有的架构关系，因此，在显示时，该多个RGB三色子像素中的与黑色区域30相邻的蓝色子像素29则变为黑色状态，也就是为B+RGB。如c图中所示，绿色子像素28右侧的蓝色子像素29转变为黑色状态。这样，当采用Tri-gate-new架构后，在实际显示时，黑色区域30的宽度会进一步增加，如d图中的实际显示效果图，其黑色区域30左右两侧的宽度大于标准显示状态时对应的黑色区域30的宽度。因此，在显示时，本申请实施例中所显示的字体的显示效果会进一步得到加强，字体的宽度得到增加，从而有效的改善了传统设计中字体变形以及显示效果较差的问题。
本发明的驱动电路与对应的覆晶薄膜设置在显示面板的短边，扫描驱动电路设置在长边的玻璃基板内，相比于其它现有技术方案，在节省成本的同时兼容windows操作系统的字体算法，对于全高清的显示装置，正常的架构设计方案需要六个覆晶薄膜，而本实施例只需要两个覆晶薄膜，在改善字体变形的同时可以更大程度上节约成本；对于超高清显示装置，传统的设计方案需要四个覆晶薄膜，而本实施例也只需要四颗覆晶薄膜，成本相同却达到了改善字体变形的效果。
以上对本申请实施例提供的显示面板及显示装置进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，包括：
    显示基板，所述显示基板包括第一长边、第二长边、第一短边和第二短边，所述第一长边与所述第二长边平行，所述第一短边与所述第二短边平行；
    所述显示基板包括阵列设置的栅极信号线和数据信号线，以及设置在所述栅极信号线和所述数据信号线相交区域内的像素单元，多个所述像素单元在所述显示基板上形成多条像素行，每个所述像素单元包括多个子像素，且每个子像素对应的与所述栅极信号线和所述数据信号线连接；
    阵列基板列扫描驱动电路，所述阵列基板列扫描驱动电路设置于所述显示基板的长边边缘对应区域内，并与所述栅极信号线对应连接；
    驱动电路板，所述驱动电路板设置于所述显示基板的短边边缘对应区域内，并与所述数据信号线对应连接；以及，
    覆晶薄膜，所述覆晶薄膜设置于所述显示基板的短边边缘对应区域内，且所述覆晶薄膜的一端连接于所述显示基板，所述覆晶薄膜的另一端连接于所述驱动电路板；
    其中，所述驱动电路板与所述第一短边之间具有第一间隙，所述覆晶薄膜设置于所述第一间隙内。
  2. 根据权利要求1所述的显示面板，其中所述阵列基板列扫描驱动电路包括第一阵列基板列扫描驱动电路和第二阵列基板列扫描驱动电路，其中所述第一阵列基板列扫描驱动电路设置于所述第一长边的边缘，所述第二阵列基板列扫描驱动电路设置于所述第二长边的边缘。
  3. 根据权利要求1所述的显示面板，其中所述像素行包括依次设置的第一像素行、第二像素行以及第三像素行，所述第一像素行、所述第二像素行以及所述第三像素行之间对应设置有第一数据线和第二数据线；
    其中，所述第一像素行中的第2i-1个像素单元与所述第一数据线连接，且所述第二像素行中的第2i个像素单元与所述第一数据线连接；
    所述第二像素行中的第2i-1个像素单元与所述第二数据线连接，且所述第三像素行中的第2i个像素单元与所述第二数据线连接；i为整数且大于0。
  4. 根据权利要求1所述的显示面板，其中相邻两像素行之间设置有一条数据线，相邻两像素列之间设置有一条扫描线，且每一条沿短边排列的所述多个子像素对应同一条所述扫描线。
  5. 根据权利要求1所述的显示面板，其中所述驱动电路板和所述覆晶薄膜对应的设置在所述显示基板的两侧的短边边缘对应区域内。
  6. 根据权利要求1所述的显示面板，其中所述像素单元内包括红色子像素、蓝色子像素和绿色子像素。
  7. 根据权利要求6所述的显示面板，其中所述红色子像素、所述蓝色子像素和所述绿色子像素沿着所述显示基板的短边依次排列。
  8. 一种显示面板，包括：
    显示基板，所述显示基板包括第一长边、第二长边、第一短边和第二短边，所述第一长边与所述第二长边平行，所述第一短边与所述第二短边平行；
    所述显示基板包括阵列设置的栅极信号线和数据信号线，以及设置在所述栅极信号线和所述数据信号线相交区域内的像素单元，多个所述像素单元在所述显示基板上形成多条像素行，每个所述像素单元包括多个子像素，且每个子像素对应的与所述栅极信号线和所述数据信号线连接；
    阵列基板列扫描驱动电路，所述阵列基板列扫描驱动电路设置于所述显示基板的长边边缘对应区域内，并与所述栅极信号线对应连接；
    驱动电路板，所述驱动电路板设置于所述显示基板的短边边缘对应区域内，并与所述数据信号线对应连接；以及，
    覆晶薄膜，所述覆晶薄膜设置于所述显示基板的短边边缘对应区域内，且所述覆晶薄膜的一端连接于所述显示基板，所述覆晶薄膜的另一端连接于所述驱动电路板。
  9. 根据权利要求8所述的显示面板，其中所述阵列基板列扫描驱动电路包括第一阵列基板列扫描驱动电路和第二阵列基板列扫描驱动电路，其中所述第一阵列基板列扫描驱动电路设置于所述第一长边的边缘，所述第二阵列基板列扫描驱动电路设置于所述第二长边的边缘。
  10. 根据权利要求8中任一项所述的显示面板，其中所述像素行包括依次设置的第一像素行、第二像素行以及第三像素行，所述第一像素行、所述第二像素行以及所述第三像素行之间对应设置有第一数据线和第二数据线；
    其中，所述第一像素行中的第2i-1个像素单元与所述第一数据线连接，且所述第二像素行中的第2i个像素单元与所述第一数据线连接；
    所述第二像素行中的第2i-1个像素单元与所述第二数据线连接，且所述第三像素行中的第2i个像素单元与所述第二数据线连接；i为整数且大于0。
  11. 根据权利要求8中任一项所述的显示面板，其中相邻两像素行之间设置有一条数据线，相邻两像素列之间设置有一条扫描线，且每一条沿短边排列的所述多个子像素对应同一条所述扫描线。
  12. 根据权利要求8所述的显示面板，其中所述驱动电路板和所述覆晶薄膜对应的设置在所述显示基板的两侧的短边边缘对应区域内。
  13. 根据权利要求12所述的显示面板，其中所述显示基板的短边边缘对应区域内设置的所述覆晶薄膜数量为两个或三个。
  14. 根据权利要求8所述的显示面板，其中所述像素单元内包括红色子像素、蓝色子像素和绿色子像素。
  15. 根据权利要求14所述的显示面板，其中所述红色子像素、所述蓝色子像素和所述绿色子像素沿着所述显示基板的短边依次排列。
  16. 一种显示装置，包括显示面板，所述显示面板包括：
    显示基板，所述显示基板包括第一长边、第二长边、第一短边和第二短边，所述第一长边与所述第二长边平行，所述第一短边与所述第二短边平行；
    所述显示基板上阵列设置有多个像素单元，每个所述像素单元包括相邻设置的多个子像素，并形成多条像素行；
    阵列基板列扫描驱动电路，所述阵列基板列扫描驱动电路设置于所述显示基板的长边边缘对应区域内，并与所述栅极信号线对应连接；
    驱动电路板，所述驱动电路板设置于所述显示基板的短边边缘对应区域内，并与所述数据信号线对应连接；以及，
    覆晶薄膜，所述覆晶薄膜设置于所述显示基板的短边边缘对应区域内，且所述覆晶薄膜的一端连接于所述显示基板，所述覆晶薄膜的另一端连接于所述驱动电路板。
  17. 根据权利要求16所述的显示装置，其中所述阵列基板列扫描驱动电路包括第一阵列基板列扫描驱动电路和第二阵列基板列扫描驱动电路，其中所述第一阵列基板列扫描驱动电路设置于所述第一长边的边缘，所述第二阵列基板列扫描驱动电路设置于所述第二长边的边缘。
  18. 根据权利要求17所述的显示装置，其中所述驱动电路板和所述覆晶薄膜对应的设置在所述显示基板的两侧的短边边缘对应区域内。
  19. 根据权利要求16所述的显示装置，其中所述像素行包括第一像素行、第二像素行以及第三像素行，所述第一像素行、所述第二像素行以及所述第三像素行之间对应设置有第一数据线和第二数据线；
    其中，所述第一像素行中的第2i-1个像素单元与所述第一数据线连接，且所述第二像素行中的第2i个像素单元与所述第一数据线连接；
    所述第二像素行中的第2i-1个像素单元与所述第二数据线连接，且所述第三像素行中的第2i个像素单元与所述第二数据线连接；i为整数且大于0。
  20. 根据权利要求16所述的显示装置，其中相邻两像素行之间设置有一条数据线，相邻两像素列之间设置有一条扫描线，且每一条沿短边排列的所述多个子像素对应同一条所述扫描线。
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