WO2022266918A1 - 一种发光二极管及制作方法 - Google Patents

一种发光二极管及制作方法 Download PDF

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Publication number
WO2022266918A1
WO2022266918A1 PCT/CN2021/102005 CN2021102005W WO2022266918A1 WO 2022266918 A1 WO2022266918 A1 WO 2022266918A1 CN 2021102005 W CN2021102005 W CN 2021102005W WO 2022266918 A1 WO2022266918 A1 WO 2022266918A1
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Prior art keywords
layer
emitting diode
light
substrate
semiconductor epitaxial
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PCT/CN2021/102005
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English (en)
French (fr)
Inventor
沈午祺
胡蝶
吴少华
王凌飞
宁振动
谢振刚
张君逸
王笃祥
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天津三安光电有限公司
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Application filed by 天津三安光电有限公司 filed Critical 天津三安光电有限公司
Priority to PCT/CN2021/102005 priority Critical patent/WO2022266918A1/zh
Priority to CN202180003015.1A priority patent/CN113875032B/zh
Priority to CN202310121738.2A priority patent/CN116154077A/zh
Publication of WO2022266918A1 publication Critical patent/WO2022266918A1/zh
Priority to US18/543,468 priority patent/US20240120444A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table

Definitions

  • the invention relates to a light-emitting diode and a manufacturing method thereof, belonging to the field of semiconductor optoelectronic devices and technologies.
  • LEDs for short have been widely used in various light source fields such as backlighting, lighting, and landscapes because of their high luminous efficiency and longer service life. Further improving the luminous efficiency of LED chips is still the focus of current industry development.
  • the principle of surface roughening to improve the light output efficiency of the LED chip is to use the concave-convex structure of the LED light output surface to scatter or guide the light at the total reflection angle out of the chip, thereby increasing the proportion of light that can be emitted to the outside of the LED.
  • chemical deposition is generally used to deposit a layer of silicon nitride on the front of the chip to protect the chip. Protected by a transparent conductive layer on the front.
  • the electrode and light-emitting area of the chip cannot be well covered, and the strong acid solution will penetrate through the surface silicon nitride layer and the transparent conductive layer. , will cause damage to the semiconductor epitaxial stack, affect the appearance yield and photoelectric performance of the light-emitting diode, and, because the silicon nitride layer deposited on the surface needs to be removed with a solution such as hydrofluoric acid, it will leave a part of the surface of the chip containing The fluorine chemical bond causes the surface of the chip to easily absorb glue gas, which affects the wire bonding effect of the chip.
  • the present invention proposes a light-emitting diode and a manufacturing method.
  • the light-emitting diode contains an etching stopper layer, which can prevent the etchant from etching the upper surface of the semiconductor epitaxial stack in the process of roughening the sidewall, and improve
  • the appearance yield of semiconductor light-emitting diodes improves the photoelectric performance of light-emitting diodes; at the same time, it avoids the deposition of silicon nitride on the surface of the chip in order to protect the front of the chip in the prior art, and the chemical bonds left over from the removal will affect the effect of chip bonding wires, and improve LED reliability.
  • the present invention proposes a light emitting diode, comprising: a substrate having an opposite first surface and a second surface; a semiconductor epitaxial stack including a first conductivity type semiconductor layer stacked on the first surface of the substrate, The active layer and the second conductivity type semiconductor layer; the sidewall is formed on the edge of the semiconductor epitaxial stack, the sidewall has a roughened structure, and the roughened structure includes protrusions; it is characterized in that: it also includes an etching stopper layer , located on the upper surface of the semiconductor epitaxial stack far away from the substrate, the etching barrier layer can prevent etching liquid from etching the semiconductor epitaxial stack.
  • the etching barrier layer is made of acid-resistant or alkali-resistant conductive material.
  • the etching barrier layer is composed of a compound semiconductor material of the combined formula (Al X Ga —X ) Y In 1-Y P, where 0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1.
  • the etch stop layer is composed of GaP compound semiconductor material.
  • the etching barrier layer has a thickness of 30-150 nm.
  • the etching stopper layer is doped with p-type, and its doping concentration is above 1E19/cm ⁇ 3 .
  • the semiconductor epitaxial stack radiates infrared light.
  • the semiconductor epitaxial stack is composed of GaAs-based compound semiconductor materials.
  • the light emitting diode further includes an intermediate layer located between the semiconductor epitaxial stack and the etching barrier layer, and the lattice constant of the intermediate layer is between the semiconductor epitaxial stack and the etching barrier layer.
  • the intermediate layer is composed of GaInP compound semiconductor material.
  • the thickness of the intermediate layer is 20-50 nm.
  • the light emitting diode further includes a transparent conductive layer located on the etching stopper layer.
  • the transparent conductive layer is ITO or IZO.
  • the substrate is a conductive substrate.
  • the present invention also proposes a light-emitting diode package, which includes a substrate and at least one light-emitting diode mounted on the substrate, characterized in that at least one or more or all of the light-emitting diodes are any of the above-mentioned One LED.
  • the present invention also proposes a light emitting device, characterized in that: the light emitting device comprises any one of the above light emitting diodes.
  • the present invention also proposes a method for manufacturing a light-emitting diode, comprising the following steps:
  • a substrate is provided, the substrate has opposing first and second surfaces, a semiconductor epitaxial stack is formed on the first surface of the substrate, the semiconductor epitaxial stack includes a first conductive Type semiconductor layer, active layer and second conductivity type semiconductor layer;
  • the light-emitting diode and the manufacturing method described in the present invention have at least the following beneficial effects:
  • the present invention can prevent the etching of the upper surface of the semiconductor epitaxial layer by the roughening liquid during the roughening process of the side wall by etching the barrier layer, improve the appearance yield of the semiconductor light-emitting diode, and improve the photoelectric performance of the light-emitting diode;
  • FIG. 1 is a schematic structural view of a light emitting diode in the prior art before roughening
  • Fig. 2 is a schematic diagram of light-emitting diodes in the prior art when roughening liquid is applied;
  • Fig. 3 is the FIB diagram of the chip after roughening the light-emitting diode in the prior art
  • Fig. 4 is a schematic structural diagram of the light-emitting diode described in Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural diagram of the light emitting diode described in Embodiment 2 of the present invention.
  • FIGS. 6-8 are structural schematic diagrams of the light-emitting diode manufacturing method described in Embodiment 3 of the present invention.
  • Embodiment 9 is a schematic structural view of the light emitting diode described in Embodiment 4 of the present invention.
  • FIG. 10 is a schematic structural diagram of the light emitting diode described in Embodiment 5 of the present invention.
  • 100 substrate; 1: semiconductor epitaxial stack; 110: first conductivity type semiconductor layer; 120: active layer; 130: second conductivity type semiconductor layer; 140: transparent conductive layer; 150: 160: second electrode; 170: silicon nitride layer; 180: etching solution; S1: first surface of substrate; S2: second surface of substrate; 190: etching stopper layer; 200: intermediate layer .
  • a light emitting diode which includes a substrate 100, a semiconductor epitaxial stack 1, a transparent conductive layer 140, a first electrode 150 and a second electrode 160; wherein the semiconductor epitaxial stack 1 includes a first The conductive type semiconductor layer 110, the active layer 120 and the second conductive type semiconductor layer 130, the transparent conductive layer 140 is used to effectively spread the current; a first electrode 150 is formed on the transparent conductive layer 140, the second An electrode 150 is located in a part of the area above the transparent conductive layer 140 and exposes a part of the transparent conductive layer 140 .
  • the second electrode 160 is located on the backside of the substrate.
  • an etchant is generally applied to the chip to roughen the sidewall to increase the light extraction efficiency of the sidewall of the chip, as shown in FIG. 2 .
  • the roughening solution 180 will penetrate the transparent conductive layer 140 on the front of the chip or penetrate to the upper surface of the semiconductor epitaxial stack, causing certain damage to the transparent conductive layer 140 and the semiconductor epitaxial stack 1, and affecting the performance of the light emitting diode.
  • the appearance yield affects the photoelectric performance of light-emitting diodes.
  • a layer of silicon nitride layer 170 is deposited on the surface of the chip by PECVD (Plasma Enhanced Chemical Vapor Deposition) to prevent the etching solution 180 from affecting the transparent conductive layer 140 and the semiconductor epitaxial stack. 1 damage.
  • PECVD Pulsma Enhanced Chemical Vapor Deposition
  • the silicon nitride layer 170 formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) has problems such as poor adhesion and low density, and because there is a certain height difference between the first electrode 150 and the transparent conductive layer 140, The inability to form an effective coating on the front of the chip leads to a certain etching phenomenon on the transparent conductive layer 140 of the chip and even the semiconductor epitaxial stack by the etchant 180 , which affects the appearance yield of the light emitting diode.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the etchant 180 will penetrate the silicon nitride layer 170 and the transparent conductive layer 140, the upper surface of the semiconductor epitaxial stack 1 will be etched, and holes will be formed on the upper surface of the semiconductor epitaxial stack 1, as shown in the framed part in FIG. 3 display, thereby affecting the appearance yield of the light-emitting diode and affecting the photoelectric performance of the light-emitting diode.
  • the method of depositing the silicon nitride layer 170 to protect the front surface of the light-emitting diode has other disadvantages.
  • hydrofluoric acid solution is often used, which will leave fluorine on the surface of the light-emitting diode.
  • the chemical bond causes the glue gas to be adsorbed on the front of the light-emitting diode, which affects the effect of the welding wire in the later stage of the light-emitting diode.
  • the present invention provides a light emitting diode and a manufacturing method.
  • the present invention provides the following light-emitting diode, as shown in Figure 4, which includes the following stacked layers: 100: substrate; 1: semiconductor epitaxial stack; 110: first conductivity type semiconductor layer; 120: active layer ; 130: second conductivity type semiconductor layer; 140: transparent conductive layer; 150: first electrode; 160: second electrode; S1: the first surface of the substrate; S2: the second surface of the substrate; 190: etching barrier Floor.
  • the substrate 100 is used for epitaxial growth.
  • a commonly used GaAs substrate is preferred.
  • the substrate 100 is not limited to GaAs, and other materials such as GaP and InP may also be used.
  • the GaAs substrate 100 a commercially available single crystal substrate manufactured by a known manufacturing method can be used as the GaAs substrate 100 .
  • the surface of the GaAs substrate for epitaxial growth is preferably smooth. From the viewpoint of quality stability, it is preferable that the plane orientation of the surface of the GaAs substrate 100 is a (100) plane which is easy to be epitaxially grown and mass-produced, and a substrate which is shifted within ⁇ 20° from (100). Moreover, a more preferable range of the plane orientation of the GaAs substrate 100 is 15° ⁇ 5° shifted from the (100) direction to the (0-1-1) direction.
  • the dislocation density of the GaAs substrate 100 is preferably low. Specifically, for example, it is desirably 10,000 cm -2 or less, preferably 1,000 cm -2 or less.
  • the GaAs substrate 100 is n-type, generally doped with Si, preferably with a carrier concentration in the range of 1*10 17 ⁇ 5*10 18 cm ⁇ 3 .
  • the thickness of the GaAs substrate 100 has an appropriate range according to its size. If the thickness of the GaAs substrate 100 is relatively thin, cracks are likely to occur during the fabrication of the semiconductor epitaxial stack 1 . On the other hand, if the GaAs substrate 100 is too thick, the material cost will increase. Therefore, when the size of the GaAs substrate 100 is large, for example, a diameter of 75 mm, the thickness of the GaAs substrate 100 is preferably 250 to 500 ⁇ m in order to prevent cracks during fabrication. Similarly, when the diameter is 50 mm, the thickness is preferably 200 to 400 ⁇ m, and when the diameter is 100 mm, the thickness is preferably 350 to 600 ⁇ m.
  • a buffer layer (not shown in the figure) can be set between the GaAs substrate 100 and the semiconductor epitaxial stack 1 ).
  • the material of the buffer layer is preferably the same as that of the substrate on which epitaxial growth is performed. Therefore, in this embodiment, the buffer layer is preferably GaAs, which is the same material as the GaAs substrate 100 .
  • a multilayer film made of a material different from that of the GaAs substrate 100 may be used for the buffer layer.
  • the thickness of the buffer layer is preferably 0.1 ⁇ m or more, more preferably 0.2 ⁇ m or more.
  • the semiconductor epitaxial stack 1 is obtained by MOCVD or other growth methods. It is a semiconductor material that can provide conventional radiation such as ultraviolet, blue, green, yellow, red, and infrared light. Specifically, it can be a 200-950nm material, such as a common Nitride, specifically such as gallium nitride-based semiconductor epitaxial stacks, gallium nitride-based epitaxial stacks are often doped with elements such as aluminum and indium, which mainly provide radiation in the 200-550nm band; or common AlGaInP-based Or AlGaAs-based semiconductor epitaxial stacks, which mainly provide radiation in the 550 ⁇ 950nm band.
  • a common Nitride specifically such as gallium nitride-based semiconductor epitaxial stacks
  • gallium nitride-based epitaxial stacks are often doped with elements such as aluminum and indium, which mainly provide radiation in the 200-550nm band
  • the semiconductor layer of the first conductivity type 110 and the semiconductor layer of the second conductivity type 130 can be doped with n-type or doped with p-type respectively so as to provide at least electrons or holes respectively.
  • the n-type semiconductor layer may be doped with an n-type dopant such as Si, Ge or Sn
  • the p-type semiconductor layer may be doped with a p-type dopant such as Mg, Zn, Ca, Sr, Ba or C.
  • the first conductivity type semiconductor layer 110, the active layer 120, and the second conductivity type semiconductor layer 130 can specifically be aluminum gallium indium nitride, gallium nitride, aluminum gallium nitrogen, aluminum indium phosphide, aluminum gallium indium phosphide, or gallium arsenide or aluminum Made of materials such as gallium arsenic.
  • the first conductivity type semiconductor layer 110 or the second conductivity type semiconductor layer 130 includes a capping layer that provides electrons or holes, and may include other layer materials such as a current spreading layer, a window layer or an ohmic contact layer, etc., according to the doping concentration or The content of the components is different to be set as different multi-layers.
  • the active layer 120 is a region for recombination of electrons and holes to provide light radiation. Different materials can be selected according to different emission wavelengths.
  • the active layer 120 can be a periodic structure of single quantum well or multiple quantum wells. By adjusting the composition ratio of the semiconductor material in the active layer 120 , it is desired to radiate light of different wavelengths.
  • the semiconductor epitaxial stack 1 is composed of a GaAs-based material.
  • the semiconductor epitaxial stack 1 radiates infrared light.
  • the first conductivity type semiconductor layer 110 is preferably made of AlGaAs material, and the active layer 120 is formed by alternately stacking well layers and barrier layers.
  • the active layer 120 has 5-15 periods of InGaAs/AlGaAsP multiple quantum wells, the thickness of the InGaAs well layer in each period is 10-20 nm, and the thickness of the AlGaAsP barrier layer is 3-15 nm.
  • the second conductivity type semiconductor layer 110 is preferably made of AlGaAs material.
  • GaAs-based infrared light-emitting diodes have a high transmittance in GaAs materials due to the light-emitting wavelength, so that they have the characteristics that all sides of the light-emitting diode are light-emitting surfaces.
  • a roughened structure can be formed by roughening the sidewall of the semiconductor epitaxial stack 1 , and the roughened structure includes protrusions to improve the light extraction efficiency of the sidewall of the semiconductor light-emitting diode and improve the luminous efficiency of the light-emitting diode.
  • the substrate is made of GaAs material, and the sidewall of the substrate also has a roughened structure.
  • the strong acid solution used will penetrate the surface silicon nitride layer 170 and even the transparent conductive layer 140 to damage the semiconductor epitaxial stack 1 , as shown in FIG. 2 .
  • the compound semiconductor formed by the Al/Ga/As elements on the upper surface of the semiconductor epitaxial stack 1 is easy to react with a strong acid solution, resulting in the surface layer of the semiconductor epitaxial stack 1 being etched, and the appearance of a light-emitting diode appears Abnormal, resulting in loss of yield of light-emitting diodes, as shown in Figure 3.
  • the etching barrier layer 190 is an acid-resistant or alkali-resistant conductive material.
  • the etch barrier layer can be formed of inert metals, such as Au, Ti, Pt and other metals.
  • the material of the etching stopper layer 190 is composed of a compound semiconductor material of the combined formula (Al X Ga 1-X ) Y In 1-Y P, where 0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1.
  • the etch stop layer 190 is composed of GaP compound semiconductor material. Due to the good chemical stability of the GaP material, it will not be etched by the acid-base solution used in the above roughening process, and the GaP material has a large energy gap, which has good light transmission in the infrared band and will not affect Light efficiency.
  • the material of the etching stopper layer is not limited to GaP material, and may be AlGaInP, GaInP and the like.
  • the thickness of the etching barrier layer 190 is preferably 30-150 nm.
  • the etching stopper layer 190 is too thin to effectively block the etching of the semiconductor epitaxial stack 1 by the acid-base solution during the roughening process. Since the material composition of the etching barrier layer 190 is different from that of the semiconductor epitaxial stack 1, there is a lattice mismatch problem between the two. In order to ensure the lattice quality of the semiconductor epitaxial stack 1 and the etching barrier layer 190, the etching The thickness of the barrier layer 190 should not be too thick, preferably more than 30nm and less than 150nm. In this embodiment, preferably, the material of the etching barrier layer is 50-100 nm.
  • the etching stopper layer 190 is P-type doped, and the P-type dopant is preferably C.
  • the doping concentration of the etching stopper layer 190 is preferably 1E19/cm ⁇ 3 , more preferably 3E19/cm ⁇ 3 or more.
  • the etch stop layer may form an ohmic contact with the transparent conductive layer 140 .
  • the transparent conductive layer 140 is located on the etching stopper layer 190, and is used to expand the current; in order to emit the light radiated from the semiconductor epitaxial stack 1, the light transmittance of the transparent conductive layer 140 is preferably more than 70%, more preferably 90%. %above.
  • the transparent conductive layer 140 is IZO or ITO. In this embodiment, preferably, the transparent conductive layer 140 is ITO.
  • the first electrode 150 is disposed on a partial area of the transparent conductive layer 140 .
  • the first electrode 150 includes a pad electrode and an extension electrode, wherein the pad electrode is mainly used for external bonding during packaging.
  • the pad electrodes can be designed in different shapes according to the actual wire bonding needs, such as cylindrical or square or other polygonal shapes.
  • the extension electrodes may be formed in a predetermined pattern shape, and the extension electrodes may have various shapes, specifically a strip shape.
  • the light emitting diode further includes a second electrode 160 , and in this embodiment, the second electrode 160 is formed on the back side of the substrate 100 in the form of an entire surface.
  • the substrate 100 in this embodiment is a conductive substrate, and the first electrode 150 and the second electrode 160 are formed on both sides of the substrate 100 to realize vertical flow of current through the semiconductor epitaxial stack and provide a uniform current density.
  • the first electrode 150 and the second electrode 160 are preferably made of metal materials, and the metal materials are preferably one or more of Au, Ge, Ni, Cr, Al, Cu, Ti, Pt, Zn.
  • the etching barrier layer can be used to prevent the etchant from etching the upper surface of the semiconductor epitaxial stack 1 in the process of roughening the sidewall, improve the appearance yield of the semiconductor light-emitting diode, and improve the photoelectric performance of the light-emitting diode;
  • silicon nitride is deposited on the surface of the chip, and the chemical bonds left over during removal will affect the chip bonding effect.
  • the lattice constant of the intermediate layer 200 is between those of the semiconductor epitaxial stack 1 and the etching stopper layer 190 .
  • the material of the intermediate layer 200 is preferably GaInP, and the thickness of the intermediate layer is in the range of 20-50 nm.
  • a substrate 100 is provided, and the substrate 100 has a first surface S1 and a second surface S2 opposite to each other; preferably, the substrate 100 is a GaAs substrate;
  • the first conductivity type semiconductor layer 110, the active layer 120 and the second conductivity type semiconductor layer 130 are sequentially formed on the first surface S1.
  • a semiconductor epitaxial stack can be grown sequentially by MOCVD (Metal Organic Compound Chemical Vapor Deposition) process.
  • the semiconductor epitaxial stack includes an N-type layer, a quantum well layer, and a P-type layer in sequence; optionally, the N-type layer includes an N-type buffer layer and an N-type confinement layer in sequence; in this embodiment, the N-type The buffer layer is a GaAs buffer layer, which can greatly improve the growth quality of semiconductor epitaxial stacks and improve the luminous efficiency of light-emitting diodes; the N-type confinement layer is an N-type AlGaAs confinement layer; the quantum well layer is InGaAs with 5 to 15 periods /AlGaAsP multiple quantum wells, the thickness of the InGaAs well layer in each period is 10 ⁇ 20nm, and the thickness of the AlGaAsP barrier layer is 3 ⁇ 15nm.
  • the P-type layer sequentially includes a P-type confinement layer and a P-type window layer, the P-type confinement layer is a P-type AlGaAs confinement layer, and the P-type window layer is an AlGaAs window layer.
  • AlGaAs refers to the AlxGa1 - xAs material, and the functional layer components of each AlxGa1 - xAs can be adjusted according to actual requirements to achieve corresponding functions.
  • an intermediate layer 200 and an etching stopper layer 190 are formed on the upper surface of the semiconductor epitaxial stack 1 away from the substrate.
  • the intermediate layer 200 and the etch stop layer 190 may be grown sequentially by using a MOCVD (metal organic compound chemical vapor deposition) process.
  • MOCVD metal organic compound chemical vapor deposition
  • the intermediate layer 200 is preferably GaInP with a thickness of 20-50 nm; the etch stop layer 190 is preferably Gap with a thickness of 30-150 nm, more preferably more than 50 nm and less than 100 nm.
  • the etch stop layer 190 is doped with P type, and the p-type dopant is preferably C, and the P-type dopant concentration is preferably above 1E19/cm ⁇ 3 , more preferably above 3E19/cm ⁇ 3 .
  • a transparent conductive layer 140 is formed on the etching stopper layer 190 .
  • the transparent conductive layer is ITO or IZO.
  • the transparent conductive layer 140 is preferably ITO.
  • a first electrode 150 and a second electrode 160 are formed on the transparent conductive layer and the back surface of the substrate.
  • the roughening solution is one or more of hydrofluoric acid, sulfuric acid, nitric acid, hydrochloric acid or phosphoric acid; optionally, the concentration of the roughening solution is 50% to 100%; in this embodiment, using The roughening solution is nitric acid, the concentration value is 100%, and the corrosion time is 50 s.
  • the manufacturing method of the light-emitting diode described in this embodiment can effectively protect the front of the light-emitting diode from being etched by the etching solution, and ensure the appearance quality and luminous efficiency of the chip.
  • the difference between embodiment 3 and embodiment 2 is that, as shown in FIG. 9 , the second electrode 160 of the light emitting diode in embodiment 4 does not completely cover the back surface of the substrate 100, exposing part of the substrate 100. second surface.
  • the second surface S2 of the substrate not covered by the second electrode 160 has a roughened structure, which can further improve the light extraction efficiency of the light emitting diode.
  • embodiment 5 The difference between embodiment 5 and embodiment 2 is that, as shown in FIG.
  • the edge position is located on the first surface S1 of the substrate.
  • This kind of structure also has the situation that the semiconductor epitaxial stack is eroded when the side is roughened, so the present invention can also solve the problem of preventing the semiconductor epitaxial stack from being etched by increasing the etching stopper layer 190, and optionally increasing the intermediate layer 200. question.
  • the present invention provides a light-emitting diode and its preparation method.
  • the light-emitting diode includes: a substrate having opposite first and second surfaces; The first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer on the surface; sidewalls are formed on the edge of the semiconductor epitaxial stack, and the sidewalls have a roughened structure; the roughened structure includes convex It is characterized in that: it also includes an etching stopper layer located on the upper surface of the semiconductor epitaxial stack away from the substrate.
  • the invention can prevent the etchant from etching the upper surface of the semiconductor epitaxial layer by the etching barrier layer during the roughening process of the side wall, improve the appearance yield of the semiconductor light-emitting diode, and improve the photoelectric performance of the light-emitting diode; To protect the front of the chip and deposit silicon nitride on the surface of the chip, the chemical bonds left over during removal will affect the effect of chip bonding.

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Abstract

本发明公开一种发光二极管及制作方法，所述发光二极管包括：衬底，具有相对的第一表面和第二表面；半导体外延叠层，包含层叠于所述衬底的第一表面之上的第一导电类型半导体层、有源层和第二导电类型半导体层；侧壁，形成于所述半导体外延叠层的边缘，所述侧壁具有粗化结构，所述粗化结构包括凸起；其特征在于：还包含蚀刻阻挡层，位于所述半导体外延叠层远离衬底的上表面。所述蚀刻阻挡层，可防止侧壁粗化过程中蚀刻液对半导体外延叠层上表面的蚀刻，提升半导体发光二极管的外观良率，提升发光二极管的光电性能。

Description

一种发光二极管及制作方法 技术领域
本发明涉及一种发光二极管及其制作方法，属于半导体光电子器件与技术领域。
 背景技术
发光二极管(Light Emitting Diode，简称LED)因具有高的发光效率及更长的使用寿命等优点，目前已经广泛地应用在背光、照明、景观等各个光源领域。进一步提高LED芯片的发光效率仍然是当前行业发展的重点。
欲提升发光效率可通过以下几个方式，其包括改善外延生长的品质，通过增加电子和空穴结合的几率，提升内部量子效率（IQE）。另一方面，发光二极管产生的光线若无法有效被取出，部分光线因全反射因素而局限在发光二极管内部来回反射或折射，最终被电极或发光层吸收，使亮度无法提升，因此使用表面粗化或者改变结构的几何形状等，提升外量子效率（EQE），从而提升发光二极管的发光亮度和发光效率。
表面粗化提高LED芯片出光效率的原理是利用LED出光表面的凹凸结构，将全反射角度的光线散射出或者引导出芯片，从而增加可以出射到LED外部的光线比例。一般地，可以选择对芯片的正面或侧面进行粗化，以提高其外部量子效率。在对芯片的侧壁进行粗化时，由于使用的强酸性溶液对芯片正面的透明导电层会有一定的损害，一般会采用化学沉积法在芯片的正面沉积一层氮化硅层以对芯片正面的透明导电层进行保护。但是，由于制备的氮化硅层存在粘附性和致密性较差等问题，无法较好地包覆芯片的电极及发光区，强酸性溶液会穿透过表层氮化硅层和透明导电层，对半导体外延叠层产生损害，影响发光二极管的外观良率和光电性能，并且，由于表面沉积的氮化硅层后续需要使用氢氟酸等溶液去除掉，因此会在芯片的表面遗留部分含氟化学键，导致芯片表面易吸附胶气，影响芯片的焊线效果。
 技术解决方案
为了解决上述的至少一个技术问题，本发明提出一种发光二极管及制作方法，所述发光二极管含有蚀刻阻挡层，可防止侧壁粗化过程中蚀刻液对半导体外延叠层上表面的蚀刻，提升半导体发光二极管的外观良率，提升发光二极管的光电性能；同时避免在现有技术中为了保护芯片正面而在芯片表面沉积氮化硅，去除时遗留的化学键对芯片焊线效果产生的影响，提升发光二极管的可靠性。
本发明提出一种发光二极管，包括：衬底，具有相对的第一表面和第二表面；半导体外延叠层，包含层叠于所述衬底的第一表面之上的第一导电类型半导体层、有源层和第二导电类型半导体层；侧壁，形成于半导体外延叠层的边缘，所述侧壁具有粗化结构，所述粗化结构包括凸起；其特征在于：还包含蚀刻阻挡层，位于所述半导体外延叠层远离衬底的上表面，所述蚀刻阻挡层可防止蚀刻液对半导体外延叠层的蚀刻。
优选地，所述蚀刻阻挡层由耐酸性或者耐碱性的导电材料组成。
优选地，所述蚀刻阻挡层由组合式(Al XGa -X) YIn 1-YP的化合物半导体材料组成，其中0≤X≤1，0≤Y≤1。
优选地，所述蚀刻阻挡层由GaP化合物半导体材料组成。
优选地，所述蚀刻阻挡层的厚度为30~150nm。
优选地，所述蚀刻阻挡层为p型掺杂，其掺杂浓度为1E19/cm -3以上。
优选地，所述半导体外延叠层辐射红外光。
优选地，所述半导体外延叠层由GaAs基化合物半导体材料组成。
优选地，所述发光二极管还包含中间层，位于所述半导体外延叠层和蚀刻阻挡层之间，所述中间层的晶格常数介于半导体外延外延叠层和蚀刻阻挡层之间。
优选地，所述中间层由GaInP化合物半导体材料组成。
优选地，所述中间层的厚度为20~50nm。
优选地，所述发光二极管还包含透明导电层，位于所述蚀刻阻挡层之上。
优选地，所述透明导电层为ITO或者IZO。
优选地，所述衬底为导电衬底。
本发明还提出一种发光二极管封装体，所述发光二极管封装体包括基板和安装在所述基板上的至少一个发光二极管，其特征在于：所述发光二极管至少一个或者多个或者全部为前述任一项的发光二极管。
本发明还提出一种发光装置，其特征在于：所述发光装置具备前述任一项的发光二极管。
本发明还提出一种发光二极管的制作方法，包含以下步骤：
（1）提供一衬底，所述衬底具有相对的第一表面和第二表面，在所述衬底的第一表面之上形成半导体外延叠层，所述半导体外延叠层包含第一导电类型半导体层、有源层和第二导电类型半导体层；
（2）在所述半导体外延叠层远离衬底的表面上形成蚀刻阻挡层；
（3）在所述蚀刻阻挡层之上形成透明导电层；
（4）在所述透明导电层和所述衬底上形成第一电极和第二电极；
（5）对所述发光二极管进行切割形成独立的芯粒，使用酸性溶液蚀刻半导体外延叠层的侧壁，所述侧壁形成粗化结构。
 有益效果
与现有技术相比，本发明所述的发光二极管及制作方法至少具备如下有益效果：
（1）本发明通过蚀刻阻挡层，可防止侧壁粗化过程中粗化液对半导体外延层上表面的蚀刻，提升半导体发光二极管的外观良率，提升发光二极管的光电性能；
（2）避免在现有技术中为了保护芯片正面而在芯片表面沉积氮化硅，去除时遗留的化学键对芯片焊线效果产生的影响，提升发光二极管的可靠性。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
虽然在下文中将结合一些示例性实施及使用方法来描述本发明，但本领域技术人员应当理解，并不旨在将本发明限制于这些实施例。反之，旨在覆盖包含在所附的权利要求书所定义的本发明的精神与范围内的所有替代品、修正及等效物。
 附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图1为现有技术中发光二极管粗化前的结构示意图；
图2为现有技术中发光二极管在施加粗化液时的示意图；
图3为现有技术中发光二极管粗化后芯片的FIB图；
图4为本发明实施例1中所述发光二极管的结构示意图；
图5为本发明实施例2中所述的发光二极管的结构示意图；
图6-8为本发明实施例3中所述发光二极管制作方法的结构示意图；
图9为本发明实施例4中所述发光二极管的结构示意图；
图10为本发明实施例5中所述发光二极管的结构示意图。
图中元件标号说明：100：衬底；1：半导体外延叠层；110：第一导电类型半导体层；120：有源层；130：第二导电型半导体层；140：透明导电层；150：第一电极；160：第二电极；170：氮化硅层；180：蚀刻液；S1：衬底的第一表面；S2：衬底的第二表面；190：蚀刻阻挡层；200：中间层。
 本发明的实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。
参照图1，提供一种发光二极管，所述发光二极管括衬底100、半导体外延叠层1、透明导电层140，第一电极150和第二电极160；其中，半导体外延叠层1包括第一导电类型半导体层110、有源层120和第二导电类型半导体层130，所述透明导电层140用于对电流进行有效的扩展；在透明导电层140之上形成有第一电极150，该第一电极150位于透明导电层140上方的部分区域，且暴露出部分的透明导电层140。第二电极160位于衬底的背面。为了提高芯片的外量子效率，一般会对芯片施加蚀刻液对侧壁进行粗化，以增加芯片侧壁的出光效率，参照图2。在此过程中，粗化液180会穿透芯片正面的透明导电层140或渗透至半导体外延叠层的上表面，对透明导电层140及半导体外延叠层1造成一定的损伤，影响发光二极管的外观良率，影响发光二极管的光电性能。
为了解决上述问题，参照图1，目前利用PECVD（等离子体增强化学气相沉积）的方法在芯片的表面沉积一层氮化硅层170，以防止蚀刻液180对透明导电层140及半导体外延叠层1的损伤。但是，由于采用PECVD（等离子体增强化学气相沉积）形成的氮化硅层170存在粘附性差，致密度不高等问题，且由于第一电极150与透明导电层140之间存在一定的高度差，无法对芯片正面形成有效的包覆，导致了蚀刻液180对芯片的透明导电层140甚至半导体外延叠层产生一定的蚀刻现象，影响发光二极管的外观良率。由于蚀刻液180会穿透氮化硅层170和透明导电层140，会蚀刻半导体外延叠层1的上表面，在半导体外延叠层1的上表面形成孔洞，如图3中的框中部分所示，从而影响发光二极管的外观良率，影响发光二极管的光电性能。
此外，采用沉积氮化硅层170保护发光二极管正面的方法还存在其他一些不足，例如，在去除发光二极管表面的氮化硅层170时常使用氢氟酸溶液，会在发光二极管的表面遗留含氟化学键，导致发光二极管正面吸附胶气，影响发光二极管后期的焊线效果。
为了解决上述的至少一个技术问题，本发明提供一种发光二极管及制作方法。
实施例 1
本发明提供如下一种发光二极管，如图4所示的剖面示意图，其包括如下堆叠层：100：衬底；1：半导体外延叠层；110：第一导电类型半导体层；120：有源层；130：第二导电型半导体层；140：透明导电层；150：第一电极；160：第二电极； S1：衬底的第一表面；S2：衬底的第二表面；190：蚀刻阻挡层。
下面针对各结构堆叠层进行详细描述。
衬底100用于外延生长，本实施例优选常用的GaAs衬底，应当注意的是，衬底100并不局限于GaAs，也可采用其他材料，例如GaP、InP。
本实施例中，GaAs衬底100可以使用由公知的制法制作的市场上销售的单晶基板。GaAs衬底进行外延生长的表面优选是平滑的。从品质的稳定性方面出发，优选GaAs衬底100的表面的面取向为容易外延生长并量产的(100)面以及从(100)在±20°以内偏移的基板。而且，更优选的GaAs衬底100的面取向的范围为从(100)方向向(0-1-1)方向偏移15°±5°。
为了使长在GaAs衬底100上的半导体外延叠层1的晶体质量好，优选GaAs衬底100的位错密度低。具体地讲，例如，希望为10000个cm -2以下，优选的为1000个 cm -2以下。GaAs衬底100为n型的，一般掺杂Si，优选其载流子浓度为1*10 17~5*10 18cm -3的范围。
GaAs衬底100的厚度根据其尺寸有适当的范围。如果GaAs衬底100的厚度比较薄，则在半导体外延叠层1的制作过程中容易发生龟裂。另一方面，GaAs衬底100的厚度过厚，则材料的成本会增加。因此，在GaAs衬底100的尺寸大的情况下，例如，直径为75mm的情况下，为了防止制作过程中的开裂，优选GaAs衬底100的厚度为250~500μm的厚度。同样地，在直径为50mm的情况下，优选为200~400μm的厚度，在直径为100mm的情况下，优选为350~600μm的厚度。
通过根据GaAs衬底100的尺寸来增厚衬底的厚度，可以降低起因于有源层120的半导体外延叠层1的翘曲。外延生长中的温度分布变得均匀，因此可以提升有源层120的面内的波长分布的均匀性。
为了降低GaAs衬底100和半导体外延叠层1的缺陷的传播，提升半导体外延叠层1的晶体质量，可在GaAs衬底100和半导体外延叠层1之间设置缓冲层（图中未示出）。缓冲层的材质优选为与进行外延生长的衬底相同的材质。因此，在本实施例中，缓冲层优选为与GaAs衬底100的同样的材质GaAs。另外，为了降低缺陷的传播，缓冲层也可以使用由不同于GaAs衬底100的材质构成的多层膜。缓冲层的厚度优选为0.1μm以上，更优选为0.2μm以上。
半导体外延叠层1通过MOCVD或其它的生长方式获得，为能够提供常规的如紫外、蓝、绿、黄、红、红外光等辐射的半导体材料，具体的可以是200~950nm的材料，如常见的氮化物，具体的如氮化镓基半导体外延叠层，氮化镓基外延叠层常见有掺杂铝、铟等元素，主要提供200~550nm波段的辐射；或者常见的铝镓铟磷基或铝镓砷基半导体外延叠层，主要提供550~950nm波段的辐射。
所述第一导电类型半导体层110和第二导电类型半导体层130可分别通过n型掺杂或p型掺杂以实现至少分别提供电子或空穴。n型半导体层可以掺杂有诸如Si、Ge或者Sn的n型掺杂物，p型半导体层可以掺杂有诸如Mg、Zn、Ca、Sr、Ba或者C的p型掺杂物。第一导电类型半导体层110、有源层120、第二导电类型半导体层130具体可以是铝镓铟氮、氮化镓、铝镓氮、铝铟磷、铝镓铟磷或砷化镓或铝镓砷等材料制作形成。第一导电类型半导体层110或第二导电类型半导体层130中包括提供电子或空穴的覆盖层，以及可以包括其它层材料如电流扩展层、窗口层或欧姆接触层等，根据掺杂浓度或组分含量不同进行设置为不同的多层。有源层120为提供电子和空穴复合提供光辐射的区域，根据发光波长的不同可选择不同的材料，有源层120可以是单量子阱或多量子阱的周期性结构。通过调整有源层120中半导体材料的组成比，以期望辐射出不同波长的光。
在本实施例中，优选半导体外延叠层1为GaAs基材料组成。所述半导体外延叠层1辐射红外光。本实施例中，所述第一导电类型半导体层110优选为AlGaAs材料，有源层120由阱层和垒层交替层叠形成。有源层120具有5~15个周期的InGaAs/AlGaAsP多量子阱，每个周期内的InGaAs阱层的厚度为10~20nm，AlGaAsP垒层厚度为3~15nm。所述第二导电类型半导体层110优选为AlGaAs材料。
GaAs基红外发光二极管因发光波长在GaAs材料中具有较高的穿透率，使其具有发光二极管各个面均为出光面的特点。可通过对半导体外延叠层1的侧壁进行粗化，形成粗化结构，所述粗化结构包括凸起，提升半导体发光二极管的侧壁的取光效率，提升发光二极管的发光效率。在本实施例中，所述衬底为GaAs材料，所述衬底的侧壁也存在粗化结构。
在对发光二极管的侧面进行粗化时，所用到的强酸性溶液会透过表层的氮化硅层170、甚至是透明导电层140伤害到半导体外延叠层1，如图2所示。由于红外产品AlGaAs材料的特殊性，半导体外延叠层1上表面的Al/Ga/As元素形成的化合物半导体容易与强酸溶液发生反应，导致半导体外延叠层1的表层被蚀刻，出现发光二极管的外观异常，造成发光二极管的良率损失，如图3所示。
本发明中通过在半导体外延叠层1的表面形成蚀刻阻挡层190，可防止蚀刻液对半导体外延叠层的蚀刻。所述蚀刻阻挡层190为具有耐酸或耐碱性的导电材料。在一些实施例中，所述蚀刻阻挡层可为惰性金属，如Au，Ti，Pt等金属形成。
在本实施例中，所述蚀刻阻挡层190的材料由组合式(Al XGa 1-X) YIn 1-YP的化合物半导体材料组成，其中0≤X≤1，0≤Y≤1。优选所述蚀刻阻挡层190为GaP化合物半导体材料组成。由于GaP材料的化学稳定性好，不会被上述粗化工艺流程中用到的酸碱类溶液蚀刻的特点，而且GaP材料的能隙较大，对于红外波段的透光性好，不会影响出光效率。应当注意的是，蚀刻阻挡层的材料不局限于GaP材料，可以为AlGaInP、GaInP等。
所述蚀刻阻挡层190的厚度优选为30~150nm。所述蚀刻阻挡层190的厚度过薄，不能有效阻挡粗化过程中酸碱性溶液对半导体外延叠层1的蚀刻。由于蚀刻阻挡层190的材料组成不同于半导体外延叠层1的材料组成，两者之间存在晶格失配问题，为了保证半导体外延叠层1和蚀刻阻挡层190的晶格质量，所述蚀刻阻挡层190的厚度也不宜过厚，优选为30nm以上，150nm以下。本实施例中，优选所述蚀刻阻挡层的材料为50~100nm。
所述蚀刻阻挡层190为P型掺杂，P型掺杂剂优选为C，所述蚀刻阻挡层190的掺杂浓度优选为1E19/cm -3，更优选为3E19/cm -3以上。所述蚀刻阻挡层可与透明导电层140形成欧姆接触。
透明导电层140位于蚀刻阻挡层190之上，用于对电流进行扩展；为了半导体外延叠层1辐射出的光线出射，优选透明导电层140的透光率为70%以上，更优选的为90%以上。透明导电层140为IZO或者ITO。本实施例中，优选所述透明导电层140为ITO。
第一电极150配置在透明导电层140的部分区域上。在一些实施例中，所述第一电极150包括焊盘电极和延伸电极，其中所述焊盘电极主要用于封装时进行外部打线。焊盘电极可以根据实际的打线需要设计成不同的形状，具体如圆柱状或方块或其它的多边形。延伸电极可以以预定的图案形状形成，并且延伸电极可以具有各种形状，具体的如条状。
所述发光二极管还包括第二电极160，本实施例中所述第二电极160以整面的形式形成在衬底100的背面侧。本实施例的衬底100为导电性衬底，第一电极150与第二电极160形成在衬底100的两面侧，以实现电流垂直流过半导体外延叠层，提供均匀的电流密度。
第一电极150和第二电极160优选为金属材料制成，所述金属材料优选为Au、Ge、Ni、Cr、Al、Cu、Ti、Pt、Zn中的一种或多种。
本发明中通过蚀刻阻挡层可防止侧壁粗化过程中蚀刻液对半导体外延叠层1上表面的蚀刻，提升半导体发光二极管的外观良率，提升发光二极管的光电性能；同时避免在现有技术中为了保护芯片正面而在芯片表面沉积氮化硅，去除时遗留的化学键对芯片焊线效果产生的影响。
实施例 2
为了提升半导体外延叠层1和蚀刻阻挡层190的晶格质量，减小半导体外延叠层1和蚀刻阻挡层190之间的晶格失配，在所述半导体外延叠层1和蚀刻阻挡层190之间加入中间层200，如图5所示，所述中间层200的晶格常数介于半导体外延叠层1和蚀刻阻挡层190的晶格常数之间。
在一些实施例中，所述中间层200的材料优选为GaInP，所述中间层的厚度范围为20~50nm。通过加入中间层200，可减小半导体外延叠层1和蚀刻阻挡层190之间的晶格失配，可提升蚀刻阻挡层的晶体质量，提升发光二极管的发光效率。
实施例 3
下面对上述实施例2的发光二极管的制作工艺进行详细的说明。
首先，如图6所示，提供一衬底100，该衬底100具备相对设置的第一表面S1和第二表面S2；优选该衬底为100为GaAs衬底；在所述衬底100的第一表面S1上依次形成第一导电类型半导体层110，有源层120和第二导电类型半导体层130，具体地，可以采用MOCVD（金属有机化合物化学气相沉积）工艺依次生长半导体外延叠层。可选地，半导体外延叠层包括依次的N型层、量子阱层和P型层；可选地，N型层依次包括N型缓冲层和N型限制层；在本实施例中，N型缓冲层为GaAs缓冲层，可以大大提高半导体外延叠层的生长质量，提高发光二级管的发光效率；N型限制层为N型AlGaAs限制层；量子阱层为具有5~15个周期的InGaAs/AlGaAsP多量子阱，每个周期内的InGaAs阱层的厚度为10~20nm，AlGaAsP垒层厚度为3~15nm。P型层依次包括P型限制层和P型窗口层，P型限制层为P型AlGaAs限制层，P型窗口层为AlGaAs窗口层。需要说明的是，AlGaAs是指Al xGa 1-xAs材料，各Al xGa 1-xAs的功能层组分可根据实际需求分别进行调整，以实现相应的功能。
然后，如图7所示，在所述半导体外延叠层1远离衬底的上表面形成中间层200和蚀刻阻挡层190。具体地，可以采用MOCVD（金属有机化合物化学气相沉积）工艺依次生长中间层200和蚀刻阻挡层190。在本实施例中，优选所述中间层200为GaInP，厚度为20~50nm；优选蚀刻阻挡层190为Gap，厚度优选为30~150nm，更优选为50nm以上，100nm以下。所述蚀刻阻挡层190为P型掺杂，p型掺杂剂优选为C，所述P型掺杂浓度优选为1E19/cm -3以上，更优选为3E19/cm -3以上。
接着，如图8所示，在所述的蚀刻阻挡层190上形成透明导电层140。可选地，透明导电层为ITO或者IZO，本实施例中，优选所述透明导电层140为ITO。在所述透明导电层和衬底的背面上形成第一电极150和第二电极160。
最后，将所述晶圆切割成独立的芯粒，将所述芯粒转移至一支撑基板上（图中未示出），然后使用酸性溶液对所述芯粒的侧壁进行粗化处理，芯粒的侧壁形成粗化结构，得到如图5所述的发光二极管。具体地，将上述芯粒置于蚀刻液中进行粗化处理，粗化3 S~200 S后，获得具有侧壁粗化的发光二极管。可选地，粗化液为氢氟酸、硫酸、硝酸、盐酸或磷酸中的一种或多种；可选地，粗化液的浓度为50%~100%；在本实施例中，采用的粗化液为硝酸，浓度值为100%，腐蚀时间为50 S。
本实施例所述发光二极管的制作作方法能够有效地保护发光二极管的正面不被蚀刻液蚀刻，保证了芯片的外观质量及发光效率。
实施例 4
实施例3与实施例2发光二极管中的区别在于，如图9所示，实施例4中的发光二极管的第二电极160不是整面地覆盖在衬底100的背面，露出部分衬底100的第二表面。本实施例中，未被第二电极160覆盖的衬底的第二表面S2具有粗化结构，可以进一步提升发光二极管的出光效率。
实施例 5
实施例5与实施例2发光二极管中的区别在于，如图10所示，实施例5中的发光二极管的第二电极160不是覆盖在衬底100的背面，而是位于半导体外延叠层1的边缘位置，位于衬底的第一表面S1之上。此种结构在侧面粗化时同样存在着半导体外延叠层被侵蚀的情况，因此本发明通过增加蚀刻阻挡层190，可选的，增加中间层200，也能解决阻止半导体外延叠层被蚀刻的问题。
综上，本发明提供一种发光二极管及制备作方法，所述发光二极管包括：衬底，具有相对的第一表面和第二表面；半导体外延叠层，包含层叠于所述衬底的第一表面之上的第一导电类型半导体层、有源层和第二导电类型半导体层；侧壁，形成于半导体外延叠层的边缘，所述侧壁具有粗化结构；所述粗化结构包括凸起，其特征在于：还包含蚀刻阻挡层，位于所述半导体外延叠层远离衬底的上表面。本发明通过蚀刻阻挡层，可防止侧壁粗化过程中蚀刻液对半导体外延层上表面的蚀刻，提升半导体发光二极管的外观良率，提升发光二极管的光电性能；同时避免在现有技术中为了保护芯片正面而在芯片表面沉积氮化硅，去除时遗留的化学键对芯片焊线效果产生的影响。
需要说明的是，以上实施方式仅用于说明本发明，而并非用于限定本发明，本领域的技术人员，在不脱离本发明的精神和范围的情况下，可以对本发明做出各种修饰和变动，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应视权利要求书范围限定。

Claims (17)

  1. 发光二极管，包括：
    衬底，具有相对的第一表面和第二表面；
    半导体外延叠层，包含层叠于所述衬底的第一表面之上的第一导电类型半导体层、有源层和第二导电类型半导体层；
    侧壁，形成于半导体外延叠层的边缘，所述侧壁具有粗化结构，所述粗化结构包括凸起；
    其特征在于：还包含蚀刻阻挡层，位于所述半导体外延叠层远离衬底的上表面，所述蚀刻阻挡层可防止蚀刻溶液蚀刻所述半导体外延叠层。
  2. 根据权利要求1所述的发光二极管，其特征在于：所述蚀刻阻挡层由耐酸性或耐碱性的导电材料组成。
  3. 根据权利要求1所述的发光二极管，其特征在于：所述蚀刻阻挡层由组合式(Al XGa -X) YIn 1-YP的化合物半导体材料组成，其中0≤X≤1，0≤Y≤1。
  4. 根据权利要求1所述的发光二极管，其特征在于：所述蚀刻阻挡层由GaP化合物半导体材料组成。
  5. 根据权利要求4所述的发光二极管，其特征在于：所述蚀刻阻挡层的厚度为30~150nm。
  6. 根据权利要求4所述的发光二极管，其特征在于：所述蚀刻阻挡层为p型掺杂，其掺杂浓度为1E19/cm -3以上。
  7. 根据权利要求1所述的发光二极管，其特征在于：所述半导体外延叠层辐射红外光。
  8. 根据权利要求1所述的发光二极管，其特征在于：所述半导体外延叠层由GaAs基化合物半导体材料组成。
  9. 根据权利要求1所述的发光二极管，其特征在于：还包含中间层，位于所述半导体外延叠层和蚀刻阻挡层之间，所述中间层的晶格常数介于所述半导体外延叠层和蚀刻阻挡层之间。
  10. 根据权利要求9所述的发光二极管，其特征在于：所述中间层由GaInP化合物半导体材料组成。
  11. 根据权利要求9所述的发光二极管，其特征在于：所述中间层的厚度为20~50nm。
  12. 根据权利要求1所述的发光二极管，其特征在于：还包含透明导电层，位于所述蚀刻阻挡层之上。
  13. 根据权利要求12所述的发光二极管，其特征在于：所述透明导电层为ITO或者IZO。
  14. 根据权利要求1所述的发光二极管，其特征在于：所述衬底为导电衬底。
  15. 一种发光二极管封装体，包括基板和安装在所述基板上的至少一个发光二极管，其特征在于：所述发光二极管至少一个或者多个或者全部为权利要求1~14中任一项的发光二极管。
  16. 一种发光装置，其特征在于：具备权利要求1~14中任一项的发光二极管。
  17. 一种发光二极管的制作方法，包含以下步骤：
    （1）提供一衬底，所述衬底具有相对的第一表面和第二表面，在所述衬底的第一表面之上形成半导体外延叠层，所述半导体外延叠层包含第一导电类型半导体层、有源层和第二导电类型半导体层；
    （2）在所述半导体外延叠层远离衬底的表面上形成蚀刻阻挡层；
    （3）在所述蚀刻阻挡层之上形成透明导电层；
    （4）在所述透明导电层和所述衬底上形成第一电极和第二电极。
    （5）对所述发光二极管进行切割形成独立的芯粒，使用蚀刻液蚀刻半导体外延叠层的侧壁，所述侧壁形成粗化结构。
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