WO2022266818A1 - 集成电路、无线接收机和终端 - Google Patents

集成电路、无线接收机和终端 Download PDF

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Publication number
WO2022266818A1
WO2022266818A1 PCT/CN2021/101346 CN2021101346W WO2022266818A1 WO 2022266818 A1 WO2022266818 A1 WO 2022266818A1 CN 2021101346 W CN2021101346 W CN 2021101346W WO 2022266818 A1 WO2022266818 A1 WO 2022266818A1
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Prior art keywords
coupled
filter capacitor
local oscillator
transistor
input node
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PCT/CN2021/101346
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English (en)
French (fr)
Inventor
秦希
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/101346 priority Critical patent/WO2022266818A1/zh
Priority to CN202180099580.2A priority patent/CN117501146A/zh
Publication of WO2022266818A1 publication Critical patent/WO2022266818A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/03—Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver

Definitions

  • the present application relates to the field of circuit technology, in particular to an integrated circuit, a wireless receiver and a terminal.
  • the wide application of wireless receivers makes the wireless spectrum very crowded.
  • the cause of wireless spectrum congestion is usually caused by out-of-band interference and blocking, which puts forward high requirements on the linearity of wireless receivers.
  • the high-pass filter is connected to the rear stage of the passive mixer, the linearity requirement of the high-pass filter is very high.
  • the existing high-pass filter is usually implemented based on the circuit structure of an operational amplifier. A highly linear operational amplifier consumes a lot of power and occupies a large layout area, resulting in high overall power consumption of the wireless amplifier. Designed to be larger in size.
  • the present application provides an integrated circuit, a wireless receiver and a terminal.
  • the power consumption and layout area of the integrated circuit can be reduced.
  • an embodiment of the present application provides an integrated circuit, including an input node, a first passive mixer, a first amplifier, a first filter capacitor, and a second filter capacitor.
  • the input node is used to receive the radio frequency signal, and input the radio frequency signal to the first branch and the second branch, and the first branch and the second branch are coupled between the input node and the first amplifier.
  • the first passive mixer includes a first mixer switch and a second mixer switch, the first branch includes a first filter capacitor and a first mixer switch connected in series, and the first filter capacitor is coupled to the input node and the first mixer between the frequency switches; the second branch includes a second filter capacitor and a second mixer switch connected in series, and the second filter capacitor is coupled between the input node and the second mixer switch; the first passive mixer will The radio frequency signal is mixed with the local oscillator signal to input the first analog signal to the first amplifier.
  • a new connection method is provided by connecting the first filter capacitor and the first mixer switch in series on the first branch, and connecting the second filter capacitor and the second mixer switch in series on the second branch.
  • the first filter capacitor and the second filter capacitor can be used to replace the high-pass filter based on the operational amplifier in the related art, so as to save the layout area and power consumption occupied by the operational amplifier; on the other hand, compared with the related art in
  • the embodiment of the present application can also design the layout of the integrated circuit to be more compact, thereby further saving the layout area of the integrated circuit;
  • a filter capacitor is coupled between the input node and the first mixer switch, and a second filter capacitor is coupled between the input node A and the second mixer switch, so that the first filter capacitor and the second filter capacitor also have a DC blocking effect , when the integrated circuit is applied to a wireless receiver, the DC blocking capacitor in the wireless receiver can be omitted.
  • the first filter capacitor may be coupled between the first mixing switch and the first amplifier, and the second filter capacitor may be coupled between the second mixing switch and the first amplifier.
  • some of the first filter capacitors are coupled between the input node and the first mixing switch, and another part of the first filter capacitors are coupled to the first Between the mixer switch and the first amplifier, part of the second filter capacitor is coupled between the input node and the second mixer switch, and another part of the second filter capacitor is coupled between the second mixer switch and the first amplifier.
  • the first mixing switch includes a first transistor
  • the second mixing switch includes a second transistor
  • the integrated circuit further includes a first local oscillator signal input terminal and a second local oscillator signal input terminal.
  • the gate of the first transistor is coupled to the first local oscillator signal input terminal, the first pole is coupled to the input node, and the second pole is coupled to the first amplification input terminal of the first amplifier;
  • the gate of the second transistor is coupled to the second local oscillator signal input end, the first pole is coupled to the input node, and the second pole is coupled to the second amplification input end of the first amplifier.
  • the first transistor receives the first local oscillator signal from the first local oscillator signal input end
  • the second transistor receives the second local oscillator signal from the second local oscillator signal input end
  • the first local oscillator signal and the second local oscillator signal interact For high and low levels.
  • the first passive mixer of the integrated circuit of the present application may be a single balanced passive mixer to exclude spurious products of the first mixer.
  • the first passive mixer further includes a third mixing switch and a fourth mixing switch
  • the integrated circuit further includes a third filter capacitor and a fourth filter capacitor.
  • the input node includes a first differential input node and a second differential input node, the first branch and the second branch are coupled to the first differential input node; the second differential input node is used to input a radio frequency signal to the third branch and a fourth branch, the third branch and the fourth branch are coupled between the second differential input node and the first amplifier.
  • the third branch includes a third filter capacitor and a third mixer switch connected in series, and the third filter capacitor is coupled between the second differential input node and the third mixer switch;
  • the fourth branch includes a fourth filter connected in series The capacitor and the fourth mixing switch, the fourth filtering capacitor is coupled between the second differential input node and the fourth mixing switch.
  • the first passive mixer of the integrated circuit of the present application may be a double-balanced passive mixer to provide higher linearity for the integrated circuit.
  • the third filter capacitor may be coupled between the third mixing switch and the first amplifier, and the fourth filter capacitor may be coupled between the fourth mixing switch and the first amplifier.
  • part of the third filter capacitors is coupled between the input node and the third mixing switch, and another part of the third filter capacitors is coupled to the third
  • part of the fourth filter capacitor is coupled between the input node and the fourth mixer switch, and another part of the fourth filter capacitor is coupled between the fourth mixer switch and the first amplifier.
  • the third mixing switch includes a third transistor
  • the fourth mixing switch includes a fourth transistor.
  • the gate of the third transistor is coupled to the second local oscillator signal input terminal, the first pole is coupled to the second differential input node, and the second pole is coupled to the first amplification input terminal; the gate of the fourth transistor is coupled to the first The local oscillator signal input terminal, the first pole is coupled to the second differential input node, and the second pole is coupled to the second amplification input terminal.
  • the common-mode input voltage of the first amplifier is used to provide a DC bias for the transistor in the first passive mixer.
  • the above-mentioned input node is coupled with a low noise amplifier, and is used to receive a radio frequency signal output by the low noise amplifier, so that the integrated circuit receives a radio frequency signal with lower noise.
  • the above-mentioned integrated circuit further includes a fifth filter capacitor and a sixth filter capacitor.
  • the first amplifier also includes a first amplified output terminal and a second amplified output terminal; the fifth filter capacitor is coupled between the first amplified input terminal and the first amplified output terminal through a feedback amplification mode, and the sixth filter capacitor is coupled through a feedback amplified mode Between the second amplifying input terminal and the second amplifying output terminal, the first filter capacitor and the second filter capacitor, and the first filter capacitor and the third filter capacitor are respectively used to realize the band-pass filter effect.
  • the foregoing integrated circuit further includes a second passive mixer, a second amplifier, a seventh filter capacitor, and an eighth filter capacitor.
  • the input node is also used to input the radio frequency signal to the fifth branch and the sixth branch, and the fifth branch and the sixth branch are coupled between the input node and the second amplifier.
  • the second passive mixer includes a fifth mixer switch and a sixth mixer switch, the fifth branch includes a seventh filter capacitor and a fifth mixer switch connected in series, and the seventh filter capacitor is coupled to the input node and the fifth mixer between frequency switches; the sixth branch includes an eighth filter capacitor and a sixth mixer switch connected in series, and the eighth filter capacitor is coupled between the input node and the sixth mixer switch.
  • the second passive mixer mixes the radio frequency signal and the local oscillator signal to input a second analog signal to the second amplifier; wherein the second analog signal is orthogonal to the first analog signal.
  • the present application sets the second passive mixer corresponding to the first passive mixer, the fourth filter capacitor corresponding to the first filter capacitor, and uses the second passive mixer to analyze the radio frequency signal and the local oscillator signal Performing frequency mixing can improve the utilization rate of radio frequency signals.
  • the second passive mixer may be a single balanced passive mixer to reject spurious products of the first mixer.
  • the seventh filter capacitor may be coupled between the fifth mixing switch and the second amplifier, and the eighth filter capacitor may be coupled between the sixth mixing switch and the second amplifier.
  • part of the seventh filter capacitor is coupled between the input node and the fifth mixing switch, and another part of the seventh filter capacitor is coupled to the fifth Between the mixer switch and the second amplifier, part of the eighth filter capacitor is coupled between the input node and the sixth mixer switch, and another part of the eighth filter capacitor is coupled between the sixth mixer switch and the second amplifier.
  • the fifth mixing switch includes a fifth transistor
  • the sixth mixing switch includes a sixth transistor.
  • the gate of the fifth transistor is coupled to the third local oscillator signal input terminal, the first pole is coupled to the input node, and the second pole is coupled to the third amplification input terminal of the second amplifier;
  • the gate of the sixth transistor is coupled to the fourth local The vibration signal input end, the first pole is coupled to the input node, and the second pole is coupled to the fourth amplifying input end of the second amplifier.
  • the fifth transistor receives the third local oscillator signal from the third local oscillator signal input terminal
  • the sixth transistor receives the fourth local oscillator signal from the fourth local oscillator signal input terminal
  • the third local oscillator signal and the fourth local oscillator signal interact with each other. For high and low levels.
  • the second passive mixer further includes a seventh mixing switch and an eighth mixing switch
  • the integrated circuit further includes a ninth filter capacitor and a tenth filter capacitor.
  • the input node includes a first differential input node and a second differential input node
  • the fifth branch and the sixth branch are coupled to the first differential input node
  • the second differential input node is also used to input a radio frequency signal to the first differential input node
  • the seventh branch and the eighth branch, the seventh branch and the eighth branch are coupled between the second differential input node and the second amplifier.
  • the seventh branch includes a ninth filter capacitor and a seventh mixing switch connected in series, and the ninth filter capacitor is coupled between the second differential input node and the seventh mixing switch;
  • the eighth branch includes a tenth filter capacitor connected in series and The eighth mixing switch and the tenth filter capacitor are coupled between the second differential input node and the eighth mixing switch.
  • the second passive mixer of the present application may be a double-balanced passive mixer to provide higher linearity for the integrated circuit.
  • the ninth filter capacitor may be coupled between the seventh mixing switch and the second amplifier, and the tenth filter capacitor may be coupled between the eighth mixing switch and the second amplifier.
  • part of the ninth filter capacitor is coupled between the input node and the seventh mixing switch, and another part of the ninth filter capacitor is coupled to the seventh
  • part of the tenth filter capacitor is coupled between the input node and the eighth mixer switch, and another part of the tenth filter capacitor is coupled between the eighth mixer switch and the second amplifier.
  • the seventh mixing switch includes a seventh transistor
  • the eighth mixing switch includes an eighth transistor.
  • the gate of the seventh transistor is coupled to the fourth local oscillator signal input terminal, the first pole is coupled to the second differential input node, and the second pole is coupled to the third amplification input terminal; the gate of the eighth transistor is coupled to the third local oscillator The signal input terminal, the first pole is coupled to the second differential input node, and the second pole is coupled to the fourth amplifying input terminal.
  • the above-mentioned integrated circuit further includes a passive filter circuit; both the first mixing switch and the second mixing switch include two transistors connected in series, and the passive filtering circuit is coupled between the two transistors, which can By using the passive filter circuit, the first passive mixer of the present application constitutes a narrow-channel filter mixer to filter out the leakage signal in the process of sending the signal from the wireless transmitter to the wireless receiver.
  • the first filter capacitor and the second filter capacitor include MOM capacitors or MIM capacitors, so as to reduce parasitic capacitance of radio frequency nodes.
  • an embodiment of the present application provides a wireless receiver, where the wireless receiver includes any integrated circuit described in the first aspect.
  • the first mixing switch and the second mixing switch of the first passive mixer in the integrated circuit are used for down-mixing the radio frequency signal and the local oscillator signal.
  • an embodiment of the present application provides a terminal, the terminal includes an antenna and the wireless receiver described in the second aspect, and the antenna is used to provide a signal required by a low noise amplifier.
  • FIG. 1 is a schematic diagram of an application scenario of a terminal provided by an embodiment of the present application
  • Fig. 2 is a circuit diagram of an integrated circuit provided by the embodiment of the present application.
  • FIG. 3 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • Fig. 4 is a circuit diagram of a wireless receiver provided by the embodiment of the present application.
  • FIG. 5 is a circuit diagram of another wireless receiver provided by the embodiment of the present application.
  • FIG. 6 is a circuit diagram of another wireless receiver provided by the embodiment of the present application.
  • FIG. 7 is a circuit diagram of another wireless receiver provided by the embodiment of the present application.
  • FIG. 8 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 9 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 10 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • Figure 11 is a simulation comparison diagram of the output gain of the embodiment of the application and the related technology provided by the embodiment of the application;
  • FIG. 12 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 13 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 14 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 15 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 16 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 17 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 18 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 19 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 20 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 21 is a connection diagram between the first passive mixer and the second passive mixer and the local oscillator provided by the embodiment of the present application;
  • Fig. 22 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 23 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 24 is a circuit diagram of another integrated circuit provided by the embodiment of the present application.
  • first and second in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of objects.
  • first target object, the second target object, etc. are used to distinguish different target objects, rather than describing a specific order of the target objects.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.
  • the embodiment of the present application provides a terminal, which uses a filter capacitor to replace the existing high-pass filter based on an operational amplifier, and at the same time makes the filter capacitor share the amplifier coupled behind the passive mixer, which can save the time occupied by the operational amplifier in the high-pass filter. layout area and power consumption; and, integrating the filter capacitor and the passive mixer in series can also make the layout design more compact, thereby further saving the layout area.
  • FIG. 1 it shows a schematic diagram of an application scenario of the terminal 1 provided by the embodiment of the present application.
  • the terminal 1 includes a wireless receiver 10, a digital circuit 20, and a control circuit 30.
  • the digital circuit 20 and the control circuit 30 are coupled. to the output terminal of the wireless receiver 10
  • the digital circuit 20 is coupled between the wireless receiver 10 and the control circuit 30 .
  • the wireless receiver 10 includes an integrated circuit 100 integrated with a passive mixer (110 in FIG. 2 and FIG. 3 ) and a filter capacitor (120 in FIG. 2 and FIG. 3 ). .
  • the wireless receiver 10 may also include a local oscillator 101 and an analog-to-digital conversion circuit 102.
  • the integrated circuit 100 may also include an input node A, a local oscillator signal input terminal LO and an output terminal OUT.
  • the input node A of the integrated circuit 100 is coupled to the input terminal of the wireless receiver 10
  • the local oscillator signal input terminal LO is coupled to the output terminal of the local oscillator 101 .
  • the input node A can receive the radio frequency signal received by the wireless receiver 10, and the integrated circuit 100 can receive the radio frequency signal through the input node A, and receive the local oscillator signal sent by the local oscillator 101 from the local oscillator signal input terminal LO.
  • the passive mixer can be used to down-mix the radio frequency signal and the local oscillator signal to obtain an analog signal, and use the filter capacitor to filter the analog signal Carry out high-pass filtering, filter out useless signal and noise, to improve receiving signal-to-noise ratio;
  • analog-to-digital conversion circuit 102 to convert analog signal into digital signal, and digital signal is input to digital circuit 20 and control circuit 30;
  • the circuit 20 can encode and decode the digital signal, and input the processing result to the control circuit 30, and the control circuit 30 can control the terminal 1 to realize the function corresponding to the analog signal according to the received processing result.
  • different terminals 1 can realize different functions, which is not limited in this embodiment of the present application.
  • the control circuit 30 can control the mobile phone to receive calls from other people according to the received processing results, and when the user triggers the "answer" button, it will connect the phone and receive the audio signal from other people's mobile phones.
  • control circuit 30 may control the radar to detect the target signal according to the received processing result.
  • the terminal 1 may also be a computer, a tablet computer, a personal digital assistant (PDA for short), a smart wearable device, a smart home device, etc., which is not limited in this embodiment of the present application.
  • PDA personal digital assistant
  • the above integrated circuit 100 it should be noted that various devices included therein may be integrated on the same chip, and the chip may only include the integrated circuit 100 , or may include other devices besides the integrated circuit 100 .
  • the above-mentioned input node A may be a pin of the chip, or an internal node of the chip.
  • each device of the above-mentioned integrated circuit 100 may also be integrated on multiple chips, and the coupling between each device may be realized through pins of multiple chips, for example.
  • the aforementioned input node A may be a pin of one of the chips, or an internal node of one of the chips.
  • the above-mentioned terminal 1 may also include an antenna, and the wireless receiver 10 may also include other components.
  • FIGS. Pass filter 104 The antenna can be used to provide the signal required by the low noise amplifier.
  • the low noise amplifier 103 is coupled with the input node A of the integrated circuit 100, and is used as a preamplifier in the wireless receiver 10 to reduce noise.
  • the input node A can receive the output from the low noise amplifier.
  • the radio frequency signal; the low-pass filter 104 is coupled to the output terminal OUT of the integrated circuit 100, and can form a band-pass filter with the filter capacitor in the integrated circuit 100, so that the signal of a specific frequency band is output from the wireless receiver 10.
  • the wireless receiver 10 includes a local oscillator 101, an analog-to-digital conversion circuit 102, a low-noise amplifier 103, and a low-pass filter 104.
  • the wireless receiver 10 At least one of the local oscillator 101, the analog-to-digital conversion circuit 102, the low-noise amplifier 103, and the low-pass filter 104 may not be included as required, or the local oscillator 101 and the analog-to-digital conversion circuit 102 may be increased or decreased as required , low-noise amplifier 103, and the number of low-pass filters 104, which are not limited in this application.
  • the passive mixer may be a current source passive mixer, or a voltage source passive mixer.
  • the current-mode passive mixer and the voltage-mode passive mixer it can be a double-balanced passive mixer or a single-balanced passive mixer.
  • the double-balanced passive mixer has higher linearity, and the single-balanced passive mixer can eliminate the spurious products in the passive mixer.
  • the passive mixer is a single-balanced voltage-type passive mixer
  • the wireless receiver 10 may only include the above-mentioned local oscillator 101, analog-to-digital conversion circuit 102, low-noise amplifier 103, and low pass filter 104 .
  • the passive mixer is a single-balanced current-mode passive mixer
  • the wireless receiver 10 includes the above-mentioned local oscillator 101, analog-to-digital conversion circuit 102, low-noise amplifier 103, and Based on the low-pass filter 104, a transconductance circuit (gm) 105 may also be included.
  • the transconductance circuit 105 is coupled to the input node A of the integrated circuit 100 and can convert the voltage into a current so that the radio frequency signal is input to the integrated circuit 100 in the form of current.
  • the passive mixer is a double-balanced voltage-type passive mixer
  • the wireless receiver 10 includes the above-mentioned local oscillator 101, analog-to-digital conversion circuit 102, low-noise amplifier 103, and
  • a balance-unbalance converter (balance-unbalance, BALUN for short) 106 may also be included.
  • the input node A includes a first differential input node A1 and a second differential input node A2, the balun 106 is respectively coupled to the first differential input node A1 and the second differential input node A2 of the integrated circuit 100, and can wirelessly receive
  • the radio frequency signal received by the machine 10 is differentially input to the integrated circuit 100 .
  • the passive mixer is a double-balanced current-mode passive mixer
  • the wireless receiver 10 includes the above-mentioned local oscillator 101, analog-to-digital conversion circuit 102, low-noise amplifier 103, and On the basis of the low-pass filter 104 , a transconductance circuit 105 and a balun 106 may also be included.
  • the input node A includes a first differential input node A1 and a second differential input node A2, the balun 106 and the transconductance circuit 105 are coupled to the first differential input node A1 and the second differential input node A2 of the integrated circuit 100, And the transconductance circuit 105 is coupled between the balun 106 and the first differential input node A1 and the second differential input node A2 .
  • the balun 106 can differentially input the radio frequency signal received by the wireless receiver 10 to the integrated circuit 100 ;
  • circuit structure of the above-mentioned integrated circuit 100 will be specifically described below in conjunction with the terminal 1 and the wireless receiver 10 .
  • the present application takes the mixer as a single balanced passive mixer as an example, and provides an integrated circuit 100, which includes a first passive mixer 110, a first amplifier 140 , the first filter capacitor 120 and the second filter capacitor 130 .
  • the input node is used to receive the radio frequency signal, and input the radio frequency signal to the first branch and the second branch, and the first branch and the second branch are coupled between the input node A and the first amplifier 140 .
  • the first passive mixer 110 includes a first mixing switch 111 and a second mixing switch 112, the first branch includes a first filter capacitor 120 connected in series with the first mixer switch 111, and the first filter capacitor 120 is coupled to Between the input node A and the first mixing switch 111 .
  • the second branch includes a second filter capacitor 130 and a second mixer switch 112 connected in series, and the second filter capacitor 130 is coupled between the input node A and the second mixer switch 112 .
  • the first passive mixer 110 mixes the radio frequency signal and the local oscillator signal to input the first analog signal to the first amplifier 140 .
  • both the first mixing switch 111 and the second mixing switch 112 of the first passive mixer 110 may include at least one switching tube, and the switching tube may be a transistor.
  • the gate of the transistor can be coupled with the local oscillator signal input terminals (LO n and LO p in FIG. 8 )
  • the first pole can be coupled with the input node A of the integrated circuit 100
  • the second pole can be coupled with the first amplifier 140 .
  • the first amplifier 140 includes a first amplifying input terminal IN1 and a second amplifying input terminal IN2, the second pole of the transistor in the first mixing switch 111 is coupled to the first amplifying input terminal IN1, and the transistor in the second mixing switch 112 The second pole of is coupled with the second amplifying input terminal IN2.
  • the common-mode input voltage of the first amplifier 140 is used to provide a DC bias for transistors in the first passive mixer 110 .
  • the source-drain DC level of the transistor in the first mixing switch 111 is the same as the input DC level of the first amplification input terminal IN1 of the first amplifier 140
  • the source-drain DC level of the transistor in the second mixing switch 112 is the same as the input DC level of the second amplification input terminal IN2 of the first amplifier 140 .
  • the first pole of the transistor is the source, and the second pole is the drain; or, the first pole of the transistor is the drain, and the second pole is the source.
  • the first mixing switch 111 and the second mixing switch 112 both include transistors as an example for illustration.
  • the transistors of the first mixing switch 111 and the second mixing switch 112 can be both N-type transistors; or, as shown in FIG. 9, the first mixing switch 111
  • the transistors of the first mixing switch 111 and the second mixing switch 112 may also be P-type transistors; or, the transistors of the first mixing switch 111 and the second mixing switch 112 may include both N-type transistors and P-type transistors. Taking N-type transistors and P-type transistors applied to the first mixing switch 111 as an example, their working principles are as follows:
  • the local oscillator signal received at the gate of the transistor from the local oscillator signal input terminal is a high voltage relative to the source-drain voltage of the transistor.
  • the first mixing switch 111 is turned on; when the local oscillator signal received by the gate of the transistor from the local oscillator signal input terminal is at a low level relative to the source-drain voltage of the transistor, the first mixing switch 111 is turned off.
  • the first mixing switch 111 including a transistor as an example, and the transistor is a P-type transistor
  • the local oscillator signal received at the gate of the transistor from the local oscillator signal input terminal is high relative to the source-drain voltage of the transistor. level, the first mixing switch 111 is turned off; when the local oscillator signal received by the gate of the transistor from the local oscillator signal input terminal is at a low level relative to the source-drain voltage of the transistor, the first mixing switch 111 is turned on.
  • the function of each device in the integrated circuit 100 of the present application is: the first mixing switch 111 and the second mixing switch 112 are respectively used to mix the received local oscillator signal and radio frequency signal , to obtain the first analog signal, the first filter capacitor 120 and the second filter capacitor 130 are used to high-pass filter the first analog signal, and input the high-pass filtered first analog signal to the first amplifier 140, using the first Amplifier 140 amplifies the high-pass filtered first analog signal to a desired signal magnitude.
  • the first filter capacitor 120 and the first mixing switch 111 are connected in series on the first branch, and the second filter capacitor 130 and the second mixing switch 112 are connected in series on the second branch.
  • a new connection mode is provided.
  • the first filter capacitor 120 and the second filter capacitor 130 can be used to replace the operational amplifier-based high-pass filter 2000 shown in FIG.
  • the embodiment of the present application can also design the layout of the integrated circuit 100 to be more compact , thereby further saving the layout area of the integrated circuit 100; on the other hand, the present application couples the first filter capacitor 120 between the input node A and the first mixing switch 111, and the second filter capacitor 130 is coupled between the input node A and the Between the second mixing switch 112, so that the first filter capacitor 120 and the second filter capacitor 130 also have a direct blocking effect, when the integrated circuit 100 is applied to the wireless receiver 10, the isolation in the wireless receiver 10 can be omitted Straight capacitance 1000.
  • the DC blocking capacitor 1000 in the related art shown in FIG. 10 it is different from the first filter capacitor 120 and the second filter capacitor 130 in the embodiment of the present application.
  • the connection methods of the two are different.
  • the DC blocking capacitor 1000 of the related art is coupled between the input terminal of the wireless receiver 10 and the input node A, while the first filter capacitor 120 of the embodiment of the present application is coupled between the input node A and the input node A.
  • the second filter capacitor 130 is coupled between the input node A and the second mixing switch 112 .
  • the functions achieved by the two are different.
  • the DC blocking capacitor 1000 of the related art can only play the role of DC blocking, while the first filter capacitor 120 and the second filter capacitor 130 of the present application can not only play the role of DC blocking, but also can To play a role of high-pass filtering, specifically, the analysis of the high-pass filtering effect of the first filter capacitor 120, the second filter capacitor 130 and the DC blocking capacitor 1000 is as follows:
  • Fig. 11 shows the simulation comparison diagram of the related technology and the present application, wherein, the solid line is the simulation between the output gain of the wireless receiver 10 shown in Fig. 10 and the received radio frequency signal when the high-pass filter 2000 is not included relation chart. It can be seen that the wireless receiver 10 receives radio frequency signals in any frequency band, and its output gain remains unchanged. Therefore, the DC blocking capacitor 1000 in the wireless receiver 10 cannot perform high-pass filtering.
  • the dotted line in FIG. 11 is a simulation relationship diagram between the output gain of the wireless receiver 10 and the received radio frequency signal when the integrated circuit 100 of the embodiment of the present application is applied to the wireless receiver 10 .
  • the obtained first analog signal is 0 Hz, and at this time the first analog signal is a low frequency signal.
  • the output gain is greatly reduced because the first analog signal is filtered out by the first filter capacitor 120 and the second filter capacitor 130 . It can be concluded from this that the first filter capacitor 120 and the second filter capacitor 130 in the embodiment of the present application can function as a high-pass filter.
  • the scheme of coupling the DC blocking capacitor 1000 between the input terminal of the wireless receiver 10 and the input node A in the related art cannot replace the coupling of the first filter capacitor 120 between the input node A and the first hybrid in the embodiment of the present application. between the frequency switches 111 and couple the second filter capacitor 130 between the input node A and the second mixer switch 112 .
  • the number of the first filter capacitor 120 and the number of the second filter capacitor 130 can be the same, for example, the number of the first filter capacitor 120 and the number of the second filter capacitor 130 are one;
  • the number of first filter capacitors 120 connected in series with the first mixing switch 111 and the number of second filter capacitors 130 connected in series with the second mixing switch 112 may also be different, for example , the number of the first filter capacitor 120 is one, and the number of the second filter capacitor 130 is two.
  • the first filter capacitor 120 is different from that of the second filter capacitor 130, there may be a deviation in the value of the signal output from the first branch and the second branch, therefore, optionally, the first filter capacitor 120 The number is the same as that of the second filter capacitor 130 .
  • FIG. 8 and FIG. 9 show that when the number of the first filter capacitor 120 and the number of the second filter capacitor 130 are the same, the number of the first filter capacitor 120 and the number of the second filter capacitor 130 may be one or more.
  • the first mixing switch 111 is connected in series with a first filter capacitor 120
  • the second mixing switch 112 is connected in series with a second filter capacitor 130
  • the first mixing switch 111 is connected in series with a plurality of first filter capacitors 120
  • the second mixing switch 112 is connected in series with a plurality of second filter capacitors 130 .
  • both the first filter capacitor 120 and the second filter capacitor 130 can be one, so as to save the layout area of the integrated circuit 100 .
  • the first filter capacitor 120 and the second filter capacitor 130 can be any type of capacitor, for example, the first filter capacitor 120 and the second filter capacitor
  • the capacitor 130 may be a metal-oxide-metal (metal oxide metal, MOM for short) capacitor, a metal-dielectric-metal (metal insulator metal, MIM for short) capacitor, a field effect (metal-oxide-semiconductor, MOS for short) tube capacitor, etc.
  • MOM metal-oxide-metal
  • MIM metal-dielectric-metal
  • MOS field effect
  • the first filter capacitor 120 and the second filter capacitor 130 may be MOM capacitors or MIM capacitors.
  • the first filter capacitor 120 may be coupled between the first mixing switch 111 and the first amplifying input terminal IN1
  • the second filter capacitor 130 may be coupled to the second Between the mixing switch 112 and the second amplifying input terminal IN2, in this case, the source-drain DC level of the transistor in the first passive mixer 110 is the same as the input DC level of the upper stage circuit.
  • there are multiple first filter capacitors 120 and second filter capacitors 130 and some of the first filter capacitors 120 are coupled between the input node A and the first filter capacitor 130 .
  • the mixing switches 111 another part of the first filter capacitor 120 is coupled between the first mixing switch 111 and the first amplifying input terminal IN1, and part of the second filter capacitor 130 is coupled between the input node A and the second mixing switch 112 In between, another part of the second filter capacitor 130 is coupled between the second mixing switch 112 and the second amplifying input terminal IN2.
  • the first mixer The switch 111 may include a first transistor T1
  • the second mixing switch 112 may include a second transistor T2.
  • the local oscillator signal input terminals include a first local oscillator signal input terminal LO p and a second local oscillator signal input terminal LO n .
  • the gate of the first transistor T1 is coupled to the first local oscillator signal input terminal LO p , the first pole is coupled to the input node A, and the second pole is coupled to the first amplification input terminal IN1 of the first amplifier 140; the second transistor T2 The gate is coupled to the second local oscillator signal input terminal LO n , the first pole is coupled to the input node A, and the second pole is coupled to the second amplified input terminal IN2 of the first amplifier 140 .
  • the first transistor T1 receives the first local oscillator signal from the first local oscillator signal input terminal LO p
  • the second transistor T2 receives the second local oscillator signal from the second local oscillator signal input terminal LO n , the first local oscillator signal and the second local oscillator signal
  • the local oscillator signals are high and low levels. It should be noted here that the first local oscillator signal and the second local oscillator signal are high and low levels, that is, the first local oscillator signal is high level, and the second local oscillator signal is low level; or, the first local oscillator signal The local oscillator signal is at low level, and the second local oscillator signal is at high level.
  • the working process of the first passive mixer 110 , the first filter capacitor 120 and the second filter capacitor 130 will be introduced below by taking the first transistor T1 and the second transistor T2 as N-type transistors as examples. Its working process may include the first stage and the second stage, specifically:
  • the first local oscillator signal is at high level
  • the second local oscillator signal is at low level
  • the first transistor T1 is turned on
  • the second transistor T2 is turned off.
  • the first transistor T1 and the first filter capacitor 120 connected in series with the first transistor T1 receive the radio frequency signal through the input node A
  • the first transistor T1 receives the first local oscillator signal from the first local oscillator signal input terminal LO p
  • utilizes the first transistor T1 mixes the radio frequency signal and the first local oscillator signal to obtain the first analog signal
  • the first local oscillator signal is at low level
  • the second local oscillator signal is at high level
  • the first transistor T1 is turned off
  • the second transistor T2 is turned on.
  • the second transistor T2 and the second filter capacitor 130 connected in series with the second transistor T2 receive the radio frequency signal through the input node A
  • the second transistor T2 receives the second local oscillator signal from the second local oscillator signal input terminal LO n
  • the second transistor T2 receives the second local oscillator signal.
  • T2 mixes the radio frequency signal and the second local oscillator signal to obtain the first analog signal, uses the second filter capacitor 130 to perform high-pass filtering on the first analog signal to obtain the second output signal, and outputs the second output signal to the second amplified input Terminal IN2.
  • the first output signal and the second output signal form a set of differential output signals. When the first output signal is positive, the second output signal is negative; or, when the first output signal is negative, the second output signal is positive.
  • the second local oscillator signal in the first stage may be at high level
  • the first local oscillator signal may be at low level
  • the first local oscillator signal in the second stage may be The high level and the second local oscillator signal are low level, which is not limited in this embodiment of the present application.
  • the first pole is the source, and the second pole is the drain; or, the first pole is the drain, and the second pole is the source.
  • the first passive mixer 110 may also be a double-balanced passive mixer.
  • the double-balanced first passive mixer 110 further includes a third mixing switch 113 and a fourth mixing switch 114
  • the integrated circuit 100 further includes a third filter capacitor 150 and a fourth filter capacitor 160 .
  • the input node A includes a first differential input node A1 and a second differential input node A2, and the first branch and the second branch are coupled with the first differential input node A1 (it can also be said that the first branch and the second branch are coupled Between the first differential input node A1 and the first amplifier), the first differential input node A1 can input the first radio frequency signal to the first branch and the second branch.
  • the second differential input node A2 is used for inputting the second radio frequency signal to the third branch and the fourth branch, and the third branch and the fourth branch are coupled between the second differential input node A2 and the first amplifier 140 .
  • the first radio frequency signal and the second radio frequency signal form a set of differential signals, when the first radio frequency signal is positive, the second radio frequency signal is negative; or, when the first radio frequency signal is negative, the second radio frequency signal is positive.
  • the third branch includes a third filter capacitor 150 and a third mixer switch 113 connected in series, and the third filter capacitor 150 is coupled between the second differential input node A2 and the third mixer switch 113;
  • the fourth branch includes a series connection The fourth filter capacitor 160 and the fourth mixing switch 114 , the fourth filter capacitor 160 is coupled between the second differential input node A2 and the fourth mixing switch 114 .
  • the functions of each device in the integrated circuit 100 are: the first mixing switch 111, the second mixing switch 112, the third mixing switch 113, and the fourth mixing switch 114 is respectively used to mix the received local oscillator signal and radio frequency signal to obtain the first analog signal.
  • the first filter capacitor 120, the second filter capacitor 130, the third filter capacitor 150, and the fourth filter capacitor 160 are used to high-pass filter the first analog signal, and input the high-pass filtered first analog signal to the first amplifier 140.
  • the high-pass filtered first analog signal can be amplified to a desired signal magnitude by the first amplifier 140 .
  • the number of the first filter capacitor 120, the number of the second filter capacitor 130, the number of the third filter capacitor 150, and the number of the fourth filter capacitor 160 can all be the same, for example, the first filter capacitor 120, the number of the second filter capacitor 130, the number of the third filter capacitor 150, and the number of the fourth filter capacitor 160 are all one; in some possible implementations, the number of the first filter capacitor 120
  • the number, the number of the second filter capacitor 130, the number of the third filter capacitor 150, and the number of the fourth filter capacitor 160 can also be different, for example, the number of the first filter capacitor 120 and the third filter capacitor 150 The number is one, and the number of the second filter capacitor 130 and the fourth filter capacitor 160 is two.
  • the numbers of the first filter capacitor 120, the second filter capacitor 130, the third filter capacitor 150, and the fourth filter capacitor 160 are different, it may cause There are deviations in the values of the signals output by the four branches, therefore, optionally, the numbers of the first filter capacitor 120 , the second filter capacitor 130 , the third filter capacitor 150 and the fourth filter capacitor 160 are the same.
  • FIG. 14 shows that when the number of the third filter capacitor 150 and the number of the fourth filter capacitor 160 are the same, the number of the third filter capacitor 150 and the number of the fourth filter capacitor 160 may be one or more.
  • the third mixing switch 113 is connected in series with a third filter capacitor 150
  • the fourth mixing switch 114 is connected in series with a fourth filter capacitor 160; in some possible implementations Among them, as shown in FIG. 15 , the third mixing switch 113 is connected in series with a plurality of third filter capacitors 150
  • the fourth mixing switch 114 is connected in series with a plurality of fourth filter capacitors 160 .
  • both the third filter capacitor 150 and the fourth filter capacitor 160 can be one, so as to save the layout area of the integrated circuit 100 .
  • the third filter capacitor 150 and the fourth filter capacitor 160 can be any type of capacitor, for example, the third filter capacitor 150 and the fourth filter capacitor
  • the capacitor 160 may be a MOM capacitor, a MIM capacitor, a MOS tube capacitor, and the like.
  • the third filter capacitor 150 and the fourth filter capacitor 160 may be MOM capacitors or MIM capacitors.
  • the third filter capacitor 150 may be coupled between the third mixing switch 113 and the first amplifying input terminal IN1
  • the fourth filter capacitor 160 may be coupled to the fourth Between the mixing switch 114 and the second amplifying input terminal IN2, in this case, the source-drain DC level of the transistor in the first passive mixer 110 is the same as the input DC level of the upper stage circuit.
  • there are multiple third filter capacitors 150 and fourth filter capacitors 160 there are multiple third filter capacitors 150 and fourth filter capacitors 160 , and some of the third filter capacitors 150 are coupled between the input node A and the third filter capacitor 160 .
  • the first passive mixer 110 takes the first passive mixer 110 as a double-balanced passive mixer as an example to describe the specific circuit structure of the integrated circuit 100.
  • the first mixer When the frequency mixing switch 111 includes a first transistor T1, and the second frequency mixing switch 112 includes a second transistor T2, the third frequency mixing switch 113 includes a third transistor T3, and the fourth frequency mixing switch 114 includes a fourth transistor T4.
  • the gate of the third transistor T3 is coupled to the second local oscillator signal input terminal LO n , the first pole is coupled to the second differential input node A2, and the second pole is coupled to the first amplification input terminal IN1; the gate of the fourth transistor T4 It is coupled to the first local oscillator signal input terminal LO p , the first pole is coupled to the second differential input node A2 , and the second pole is coupled to the second amplification input terminal IN2 .
  • the first passive mixer 110 and the first filter capacitor 120 will be introduced below by taking the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 as N-type transistors as examples. , the working process of the second filter capacitor 130 , the third filter capacitor 150 , and the fourth filter capacitor 160 . Its working process may include the first stage and the second stage, specifically:
  • the first local oscillator signal is at a high level
  • the second local oscillator signal is at a low level
  • the first transistor T1 and the fourth transistor T4 are turned on
  • the second transistor T2 and the third transistor T3 due.
  • the first transistor T1 and the first filter capacitor 120 connected in series with the first transistor T1 receive the first radio frequency signal through the first differential input node A1, and the first transistor T1 receives the first local oscillator signal from the first local oscillator signal input terminal LO p , use the first transistor T1 to mix the first radio frequency signal and the first local oscillator signal to obtain the first analog signal, use the first filter capacitor 120 to perform high-pass filtering on the first analog signal to obtain the first output signal, and output the first The output signal is sent to the first amplifying input terminal IN1.
  • the fourth transistor T4 and the fourth filter capacitor 160 connected in series with the fourth transistor T4 receive the second radio frequency signal through the second differential input node A2, and the fourth transistor T4 receives the first local oscillator signal from the first local oscillator signal input terminal LO p , use the fourth transistor T4 to mix the second radio frequency signal and the first local oscillator signal to obtain the first analog signal, use the fourth filter capacitor 160 to perform high-pass filtering on the first analog signal to obtain the second output signal, and output the second The output signal is sent to the second amplified input terminal IN2.
  • the first local oscillator signal is at low level
  • the second local oscillator signal is at high level
  • the first transistor T1 and the fourth transistor T4 are cut off
  • the second transistor T2 and the third transistor T3 conducts.
  • the second transistor T2 and the second filter capacitor 130 connected in series with the second transistor T2 receive the first radio frequency signal through the first differential input node A1, and the second transistor T2 receives the second local oscillator signal from the second local oscillator signal input terminal LO n , use the second transistor T2 to mix the first radio frequency signal and the second local oscillator signal to obtain the first analog signal, use the second filter capacitor 130 to perform high-pass filtering on the first analog signal to obtain the second output signal, and output the second The output signal is sent to the second amplified input terminal IN2.
  • the third transistor T3 and the third filter capacitor 150 connected in series with the third transistor T3 receive the second radio frequency signal through the second differential input node A2, and the third transistor T3 receives the second local oscillator signal from the second local oscillator signal input terminal LO n , use the third transistor T3 to mix the second radio frequency signal and the second local oscillator signal to obtain the first analog signal, use the third filter capacitor 150 to perform high-pass filtering on the first analog signal to obtain the first output signal, and output the first The output signal is sent to the first amplifying input terminal IN1.
  • the second local oscillator signal in the first stage may be at high level
  • the first local oscillator signal may be at low level
  • the first local oscillator signal in the second stage may be The high level and the second local oscillator signal are low level, which is not limited in this embodiment of the present application.
  • the first pole is the source, and the second pole is the drain; or, the first pole is the drain, and the second pole is the source.
  • the integrated circuit 100 may further include a fifth filter capacitor 170 and a sixth filter capacitor 180 .
  • the first amplifier 140 also includes a first amplified output terminal OUT1 and a second amplified output terminal OUT2.
  • the fifth filter capacitor 170 is coupled between the first amplifying input terminal IN1 and the first amplifying output terminal OUT1 through feedback amplification
  • the sixth filter capacitor 180 is coupled between the second amplifying input terminal IN2 and the second amplifying output terminal through feedback amplifying.
  • first filter capacitor 120 and the second filter capacitor 130 also can be the first filter capacitor, the second filter capacitor, the third filter capacitor, and the fourth filter capacitor
  • fifth filter capacitor 170 and The sixth filter capacitor 180 achieves a band-pass filter effect.
  • the first filter capacitor 120 and the second filter capacitor 130 can be the first filter capacitor, the second filter capacitor, the third filter capacitor, and the first filter capacitor
  • Four filter capacitors can pass signals above 100 kHz, and then use the fifth filter capacitor 170 and the sixth filter capacitor 180 to pass signals below 100 MHz, that is, finally output signals between 100 kHz and 100 MHz from the integrated circuit 100 .
  • the embodiment of the present application does not limit the number of the fifth filter capacitor 170 and the sixth filter capacitor 180.
  • the number of the fifth filter capacitor 170 and the sixth filter capacitor 180 may be one, or Can be multiple.
  • multiple fifth filter capacitors 170 can be connected in series between the first amplified input terminal IIN1 and the first amplified output terminal OUT1 through feedback amplification;
  • multiple sixth filter capacitors 180 may be connected in series between the first amplification input terminal IN1 and the first amplification output terminal OUT1 through feedback amplification.
  • a fifth filter capacitor 170 with a smaller capacitance value can be used to replace multiple fifth filter capacitors 170 with a larger capacitance value
  • a sixth filter capacitor 180 with a smaller capacitance value can be used to replace multiple capacitor values.
  • Larger sixth filter capacitor 180 therefore, optionally, both the fifth filter capacitor 170 and the sixth filter capacitor 180 can be one, so as to save the layout area of the integrated circuit 100 .
  • the types of the fifth filter capacitor 170 and the sixth filter capacitor 180 are not limited, and the fifth filter capacitor 170 and the sixth filter capacitor 180 may be any type of capacitor, for example, the fifth filter capacitor 170 And the sixth filter capacitor 180 may be a MOS transistor capacitor, a MOM capacitor, a MIM capacitor, and the like.
  • the integrated circuit 100 may further include a second passive mixer 190, a second amplifier 200, and a seventh filter capacitor 210 and the eighth filter capacitor 220 .
  • the input node A is also used to input the radio frequency signal to the fifth branch and the sixth branch, and the fifth branch and the sixth branch are coupled between the input node A and the second amplifier 200 .
  • the second passive mixer 190 is a single balanced passive mixer
  • the second passive mixer 190 includes a fifth mixing switch 115 and a sixth mixing switch 116
  • the fifth branch includes a series
  • the seventh filter capacitor 210 and the fifth mixer switch 115 are coupled between the input node A and the fifth mixer switch 115
  • the sixth branch includes an eighth filter capacitor 220 connected in series with the sixth mixer switch 116 , and the eighth filter capacitor 220 is coupled between the input node A and the sixth mixer switch 116 .
  • the second passive mixer 190 mixes the radio frequency signal and the local oscillator signal to input the second analog signal to the second amplifier 200, wherein the second analog signal is orthogonal to the first analog signal, it can also be said that the first The output phase difference between the first analog signal and the second analog signal is ⁇ /2.
  • the second passive mixer 190 may also be a double-balanced passive mixer.
  • the fifth branch and the sixth branch are coupled to the first differential input node A1, which can also be said
  • the fifth branch and the sixth branch are coupled between the first differential input node A1 and the second amplifier 200
  • the first differential input node A1 is used to input the first radio frequency signal to the fifth branch and the sixth branch.
  • the second differential input node A2 is also used to input the second radio frequency signal to the seventh branch and the eighth branch
  • the seventh branch and the eighth branch are coupled between the second differential input node A2 and the second amplifier 200 .
  • the integrated circuit 100 further includes a ninth filter capacitor 230 and a tenth filter capacitor 240
  • the second passive mixer 190 further includes a seventh mixing switch 117 and an eighth mixing switch 118 .
  • the seventh branch includes the ninth filter capacitor 230 and the seventh mixing switch 117 connected in series, and the ninth filter capacitor 230 is coupled between the second differential input node A2 and the seventh mixing switch 117;
  • the eighth branch includes the series connected The tenth filter capacitor 240 and the eighth mixing switch 118 , the tenth filter capacitor 240 is coupled between the second differential input node A2 and the eighth mixing switch 118 .
  • the single-balanced second passive mixer 190 and the double-balanced passive mixer 190 can receive a local oscillator signal from the local oscillator 101 through a local oscillator signal input port.
  • the local oscillator signal input terminals may include a first local oscillator signal input terminal LO I,p , a second local oscillator signal input terminal LO I,n , a third local oscillator signal input terminal LO Q,p , and The fourth local oscillator signal input terminal LO Q,n .
  • the local oscillator 101 includes a first local oscillator signal output terminal V1 and a second local oscillator signal output terminal V2.
  • the local oscillator 101 can be time-divided from the first local oscillator signal output terminal V1 through the first local oscillator signal input terminal LO I, p to the first mixing switch 111 (also can be the first mixing switch and the fourth mixing switch) to input the first local oscillator signal, through the third local oscillator signal input terminal LO Q, p to the fifth mixing switch 115 (also can be the fifth mixing switch 115 and the eighth mixing switch 118 ) to input the third local oscillator signal, the phase difference between the first local oscillator signal and the third local oscillator signal can be ⁇ /2, so that the second analog signal is orthogonal to the first analog signal, it can also be said that the output first The phase difference between the second analog signal and the first analog signal is ⁇ /2.
  • the local oscillator 101 can time-division from the second local oscillator signal output terminal V2 through the second local oscillator signal input terminal LO I, n to the second mixing switch 112 (also can be the second mixing switch and the third mixing switch) to input the second local oscillation signal, through the fourth local oscillation signal input terminal LO Q, n to the sixth mixing switch 116 (also can be the sixth mixing switch 116 and the seventh mixing switch 117 ) input the fourth local oscillator signal, the phase difference between the second local oscillator signal and the fourth local oscillator signal can be ⁇ /2, the second analog signal is orthogonal to the first analog signal, it can also be said that the output second analog The phase difference between the signal and the first analog signal is ⁇ /2.
  • the first local oscillator signal and the second local oscillator signal are high and low levels
  • the third local oscillator signal and the fourth local oscillator signal are high and low levels
  • the first local oscillator signal and the third local oscillator signal are both high and low.
  • Level or low level, the second local oscillator signal and the fourth local oscillator signal are both low level or high level.
  • the fifth mixing switch 115 and the sixth mixing switch 116 may include at least one switch tube, and the switch tube may be a transistor.
  • the transistors in the second passive mixer 190 can all be P-type transistors; or, as shown in FIG. 20, the multiple second mixing switches 112 in the second passive mixer 190 The transistors may also all be N-type transistors; or, the plurality of transistors in the second passive mixer 190 may include both N-type transistors and P-type transistors.
  • the seventh filter capacitor 210 for the description of the number and types of the seventh filter capacitor 210, the eighth filter capacitor 220, the ninth filter capacitor 230, and the tenth filter capacitor 240, reference may be made to the first filter capacitor 120 and the second filter capacitor 130 in the foregoing embodiment. , the description of the third filter capacitor 150 , and the fourth filter capacitor 160 will not be repeated here.
  • the seventh filter capacitor 210 may be coupled between the fifth mixing switch 115 and the first amplifying input terminal IN1
  • the eighth filter capacitor 220 may be coupled between the sixth mixing switch 116 and the first amplification input terminal IN1.
  • the ninth filter capacitor 230 can be coupled between the seventh frequency mixing switch 117 and the first amplifier input terminal IN1
  • the tenth filter capacitor 240 can be coupled between the eighth frequency mixer switch 118 and the second amplifier input terminal IN1. between inputs IN2.
  • the fifth mixer The switch 115 includes a fifth transistor T5
  • the sixth mixing switch 116 includes a sixth transistor T6.
  • the gate of the fifth transistor T5 is coupled to the third local oscillator signal input terminal LO Q,p , the first pole is coupled to the input node A, and the second pole is coupled to the third amplification input terminal IN3 of the second amplifier 200; the sixth transistor The gate of T6 is coupled to the fourth local oscillator signal input terminal LO Q,n , the first pole is coupled to the input node A, and the second pole is coupled to the fourth amplifying input terminal IN4 of the second amplifier 200 .
  • the working process of the second passive mixer 190 will be described below by taking the fifth transistor T5 and the sixth transistor T6 as N-type transistors as examples. Its working process may include the third stage and the fourth stage, specifically:
  • the third local oscillator signal is at high level
  • the fourth local oscillator signal is at low level
  • the fifth transistor T5 is turned on
  • the sixth transistor T6 is turned off.
  • the fifth transistor T5 and the seventh filter capacitor 210 connected in series with the fifth transistor T5 receive the radio frequency signal through the input node A
  • the fifth transistor T5 receives the third local oscillator signal from the third local oscillator signal input terminal LO Q, p , and utilizes the
  • the five-transistor T5 mixes the radio frequency signal and the third local oscillator signal to obtain a second analog signal
  • uses the seventh filter capacitor 210 to perform high-pass filtering on the second analog signal to obtain a third output signal
  • the third local oscillator signal is at low level
  • the fourth local oscillator signal is at high level
  • the fifth transistor T5 is turned off
  • the sixth transistor T6 is turned on.
  • the sixth transistor T6 and the eighth filter capacitor 220 connected in series with the sixth transistor T6 receive the radio frequency signal through the input node A
  • the sixth transistor T6 receives the fourth local oscillator signal from the fourth local oscillator signal input terminal LO Q, n , and utilizes the The six transistors T6 mix the radio frequency signal and the fourth local oscillator signal to obtain a second analog signal
  • use the eighth filter capacitor 220 to perform high-pass filtering on the second analog signal to obtain a fourth output signal, and output the fourth output signal to the first Four amplifier input terminal IN4.
  • the third output signal and the fourth output signal form a set of differential output signals. When the third output signal is positive, the fourth output signal is negative; or, when the third output signal is negative, the fourth output signal is positive.
  • the specific circuit structure of the integrated circuit 100 is described by taking the second passive mixer 190 as a double-balanced passive mixer as an example.
  • the frequency mixing switch 115 includes a fifth transistor T5
  • the sixth mixing switch 116 includes a sixth transistor T6
  • the seventh mixing switch 117 includes a seventh transistor T7
  • the eighth mixing switch 118 includes an eighth transistor T8.
  • the gate of the seventh transistor T7 is coupled to the fourth local oscillator signal input terminal LO Q,n , the first pole is coupled to the second differential input node A2, and the second pole is coupled to the third amplification input terminal IN3; the eighth transistor T8 The gate is coupled to the third local oscillator signal input terminal LO Q,p , the first pole is coupled to the second differential input node A2, and the second pole is coupled to the fourth amplifying input terminal IN4.
  • the following describes the working process of the second passive mixer 190 by taking the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 as N-type transistors as examples. Its working process may include the third stage and the fourth stage, specifically:
  • the third local oscillator signal is high level
  • the fourth local oscillator signal is low level
  • the fifth transistor T5 and the eighth transistor T8 are turned on
  • the sixth transistor T6 and the seventh transistor T7 due.
  • the fifth transistor T5 and the seventh filter capacitor 210 connected in series with the fifth transistor T5 receive the first radio frequency signal through the first differential input node A1, and the fifth transistor T5 receives the third local oscillator signal input terminal LO Q,p from the third local oscillator signal.
  • the eighth transistor T8 and the tenth filter capacitor 240 connected in series with the eighth transistor T8 receive the second radio frequency signal through the second differential input node A2, and the eighth transistor T8 receives the third local oscillator signal input terminal LO Q,p from the third local oscillator signal.
  • the third local oscillator signal is at low level
  • the fourth local oscillator signal is at high level
  • the fifth transistor T5 and the eighth transistor T8 are cut off
  • the sixth transistor T6 and the seventh transistor T7 is turned on.
  • the sixth transistor T6 and the eighth filter capacitor 220 connected in series with the sixth transistor T6 receive the first radio frequency signal through the first differential input node A1, and the sixth transistor T6 receives the fourth local oscillator signal input terminal LO Q,n from the fourth local oscillator signal.
  • the fourth output signal is sent to the fourth amplified input terminal IN4.
  • the seventh transistor T7 and the ninth filter capacitor 230 connected in series with the seventh transistor T7 receive the second radio frequency signal through the second differential input node A2, and the seventh transistor T7 receives the fourth local oscillator signal input terminal LO Q,n from the fourth local oscillator signal.
  • the above examples only describe in detail the working process of the integrated circuit 100 in the third stage and the fourth stage.
  • its complete work process should include the first stage, the second stage, the third stage, and the fourth stage.
  • Taking a first stage, a second stage, a third stage and a fourth stage as a complete cycle as an example since the first local oscillator signal is orthogonal to the third local oscillator signal, and the second local oscillator signal is orthogonal to the fourth The four local oscillator signals are orthogonal, therefore, the time difference between the first stage and the third stage is 1/4 cycle, and the time difference between the second stage and the fourth stage is 1/4 cycle.
  • the integrated circuit 100 may operate in the order of the first stage, the third stage, the second stage, and the fourth stage.
  • the fourth local oscillator signal in the third stage is at a high level
  • the third local oscillator signal is at a low level
  • the third local oscillator signal in the fourth stage is at a high level
  • the third local oscillator signal is at a high level.
  • the four local oscillator signals are at low levels, which is not limited in this embodiment of the present application.
  • the first pole is the source, and the second pole is the drain; or, the first pole is the drain, and the second pole is the source.
  • the first amplifier 140 and the second amplifier 200 can be feedback amplifiers based on operational amplifiers such as transimpedance amplifier (transimpedance amplifier, be called for short TIA); As shown in Figure 22, the first The first amplifier 140 and the second amplifier 200 can also use a non-operational amplifier such as a transistor common-gate amplifier structure as a transimpedance stage to realize the amplification function of the first amplifier 140 and the second amplifier 200 .
  • operational amplifiers such as transimpedance amplifier (transimpedance amplifier, be called for short TIA)
  • the first The first amplifier 140 and the second amplifier 200 can also use a non-operational amplifier such as a transistor common-gate amplifier structure as a transimpedance stage to realize the amplification function of the first amplifier 140 and the second amplifier 200 .
  • the first amplifier 140 and the second amplifier 200 can be operational amplifiers; as shown in Figure 23, the first The amplifier 140 and the second amplifier 200 may also use a non-operational amplifier such as a transistor common-gate amplifier structure to realize the function of the first amplifier 140 .
  • the transimpedance amplifier may include an operational amplifier 141, a first feedback resistor 142, and a second feedback resistor. 143, the first feedback resistor 142 is coupled between the first amplifying input terminal IN1 and the first amplifying output terminal OUT1 through feedback amplification, and the second feedback resistor 143 is coupled between the second amplifying input terminal IN2 and the second amplifying input terminal OUT1 through feedback amplifying. between the output terminals OUT2.
  • the first output signal and the second output signal in the form of current can be converted into a form of voltage and output.
  • the first amplifier 140 may include a working voltage terminal VDD, a ground terminal VSS, a second
  • the ninth transistor T9 and the tenth transistor T10, the first pole of the ninth transistor T9 and the fourteenth transistor T14 are coupled to the working voltage terminal VDD, and the second pole is coupled to the ground terminal VSS, and the ninth transistor T9 and the tenth transistor can be connected to each other.
  • the source of T10 is amplified as the amplifier input.
  • FIG. 22 and 23 illustrate implementing the first amplifier 140 in a non-op-amp configuration.
  • the first amplifier 140 may include a working voltage terminal VDD, a ground terminal VSS, a second
  • the ninth transistor T9 and the tenth transistor T10, the first pole of the ninth transistor T9 and the fourteenth transistor T14 are coupled to the working voltage terminal VDD, and the second pole is coupled to the ground terminal VSS, and the ninth transistor T9 and the tenth transistor can be connected to each other.
  • the source of T10 is amplified as the amplifier input
  • the first amplifier 140 may include a working voltage terminal VDD, a ground terminal VSS, a second The ninth transistor T9, the tenth transistor T10, and the bias resistor R, the gates of the ninth transistor T9 and the tenth transistor T10 are coupled to the output of the first passive mixer 110, the first pole is coupled to the working voltage terminal VDD, The second electrode is coupled to the ground terminal VSS, and can be amplified through the gates of the ninth transistor T9 and the tenth transistor T10 as amplifier inputs.
  • the integrated circuit 100 can also include a passive filter circuit 300; a first mixing switch 111 and a second mixing switch 112 (also can be the first mixing switch, the second mixing switch Frequency switch, the third frequency mixing switch, and the fourth frequency mixing switch, or, the first frequency mixing switch, the second frequency mixing switch, the third frequency mixing switch, the fourth frequency mixing switch, the fifth frequency mixing switch, the sixth frequency mixing switch
  • the mixing switch, the seventh mixing switch, and the eighth mixing switch all include two transistors connected in series, and the passive filter circuit 300 is coupled between the two transistors connected in series.
  • the passive filter circuit 300 can be used to make the first passive mixer 110 of the present application (also the first passive mixer and the second passive mixer) device) constitutes a narrow-channel filter mixer to filter out the leakage signal in the process of sending the signal from the wireless transmitter to the wireless receiver 10.
  • the passive filter circuit 300 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, The fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the first capacitor C1 and the second capacitor C2.
  • the first resistor R1 and the second resistor R2 are connected in series between the two transistors of the first mixing switch 111, the third resistor R3 and the fourth resistor R4 are connected in series between the two transistors of the fourth mixing switch 114, and the fifth The resistor R5 and the sixth resistor R6 are connected in series between the two transistors of the second mixing switch 112 , and the seventh resistor R7 and the eighth resistor R8 are connected in series between the two transistors of the third mixing switch 113 .
  • the second end of the first resistor R1 and the first end of the second resistor R2 are coupled to the node a+, the third resistor R3 and the fourth resistor R4 are coupled to the node a-, the second end of the fifth resistor R5 is connected to the sixth
  • the first end of the resistor R6 is coupled to the node b+, the seventh resistor R7 and the eighth resistor R8 are coupled to the node b-;
  • the first capacitor C1 is coupled between the node a+ and the node a-, and the second capacitor C2 is coupled to the node b+ between node b-.
  • the signal input to the integrated circuit 100 passes through the embedded passive circuit formed by the resistor-capacitor (the above-mentioned first resistor to the eighth resistor, the first capacitor and the second capacitor). Filter section to reduce received signal leakage by low-pass filtering.

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Abstract

本申请实施例提供了一种集成电路、无线接收机和终端，涉及电路技术领域，可以减小集成电路的功耗和版图面积。该集成电路包括输入节点、第一无源混频器、第一放大器、第一滤波电容和第二滤波电容。输入节点用于接收射频信号，并将射频信号输入至第一支路和第二支路，第一支路和第二支路耦合于输入节点与第一放大器之间。第一无源混频器包括第一混频开关和第二混频开关，第一支路包括串联的第一滤波电容和第一混频开关，第一滤波电容耦合于输入节点与所述第一混频开关之间。第二支路包括串联的第二滤波电容和第二混频开关，第二滤波电容耦合于输入节点与第二混频开关之间，第一无源混频器将所述射频信号与本振信号进行混频，以向第一放大器输入第一模拟信号。

Description

集成电路、无线接收机和终端 技术领域
本申请涉及电路技术领域，尤其涉及一种集成电路、无线接收机和终端。
背景技术
无线接收机的广泛应用，使得无线频谱变得非常拥挤，无线频谱拥挤的原因通常是带外干扰、阻塞导致，这就对无线接收机的线性度提出了很高的要求。
目前，通过使用高线性度的无源混频器，以及在无线接收机的混频器后连接高通滤波器，滤除部分无用信号和噪声，以提高无线接收机的线性度。
然而，由于高通滤波器连接在无源混频器的后级，因此，对高通滤波器的线性度要求非常高。同时，现有的高通滤波器通常是基于运算放大器的电路结构实现的，高线性的运算放大器需要消耗很大的功耗并占用较大的版图面积，从而导致无线放大器的整体功耗过高、设计尺寸较大。
发明内容
为了解决上述技术问题，本申请提供一种集成电路、无线接收机和终端。可以减小集成电路的功耗和版图面积。
第一方面，本申请实施例提供一种集成电路，包括输入节点、第一无源混频器、第一放大器、第一滤波电容和第二滤波电容。输入节点用于接收射频信号，并将射频信号输入至第一支路和第二支路，第一支路和第二支路耦合于输入节点与第一放大器之间。第一无源混频器包括第一混频开关和第二混频开关，第一支路包括串联的第一滤波电容和第一混频开关，第一滤波电容耦合于输入节点与第一混频开关之间；第二支路包括串联的第二滤波电容和第二混频开关，第二滤波电容耦合于输入节点与所述第二混频开关之间；第一无源混频器将射频信号与本振信号进行混频，以向第一放大器输入第一模拟信号。
本集成电路中，通过使第一滤波电容和第一混频开关串联于第一支路上，使第二滤波电容和第二混频开关串联于第二支路上，提供了一种新的连接方式，一方面，可以利用第一滤波电容和第二滤波电容代替相关技术中基于运算放大器的高通滤波器，以省去运算放大器占用的版图面积和功耗；另一方面，相较于相关技术在整个第一无源混频器后连接高通滤波器的方案，本申请实施例还可以将集成电路的版图设计得更加紧凑，从而进一步节省集成电路的版图面积；另一方面，本申请通过将第一滤波电容耦合于输入节点与第一混频开关之间，第二滤波电容耦合于输入节点A与第二混频开关之间，以使第一滤波电容和第二滤波电容还具有隔直作用，当集成电路应用于无线接收机时，可以省去无线接收机中的隔直电容。
在一些可能实现的方式中，第一滤波电容可以耦合于第一混频开关与第一放大器之 间，第二滤波电容耦合于第二混频开关与第一放大器之间。或者，在第一滤波电容和第二滤波电容的个数为多个的情况下，部分第一滤波电容耦合于输入节点与第一混频开关之间、另一部分第一滤波电容耦合于第一混频开关与第一放大器之间，部分第二滤波电容耦合于输入节点与第二混频开关之间、另一部分第二滤波电容耦合于第二混频开关与第一放大器之间。
在一些可能实现的方式中，上述第一混频开关包括第一晶体管，第二混频开关包括第二晶体管，集成电路还包括第一本振信号输入端和第二本振信号输入端。第一晶体管的栅极耦合至第一本振信号输入端、第一极耦合至所述输入节点、第二极耦合至所述第一放大器的第一放大输入端；第二晶体管的栅极耦合至第二本振信号输入端、第一极耦合至输入节点、第二极耦合至第一放大器的第二放大输入端。其中，第一晶体管从第一本振信号输入端接收第一本振信号，第二晶体管从第二本振信号输入端接收第二本振信号，第一本振信号与第二本振信号互为高低电平。本申请集成电路的第一无源混频器可以是单平衡无源混频器，以排除第一混频器的杂散产物。
在一些可能实现的方式中，上述第一无源混频器还包括第三混频开关和第四混频开关，集成电路还包括第三滤波电容和第四滤波电容。输入节点包括第一差分输入节点和第二差分输入节点，第一支路和所述第二支路与第一差分输入节点耦合；第二差分输入节点用于将射频信号输入至第三支路和第四支路，第三支路和所述第四支路耦合于所述第二差分输入节点与所述第一放大器之间。第三支路包括串联的第三滤波电容和第三混频开关，第三滤波电容耦合于第二差分输入节点与所述第三混频开关之间；第四支路包括串联的第四滤波电容和第四混频开关，第四滤波电容耦合于第二差分输入节点与第四混频开关之间。本申请集成电路的第一无源混频器可以是双平衡无源混频器，以为集成电路提供更高的线性度。
在一些可能实现的方式中，第三滤波电容可以耦合于第三混频开关与第一放大器之间，第四滤波电容耦合于第四混频开关与第一放大器之间。或者，在第三滤波电容和第四滤波电容的个数为多个的情况下，部分第三滤波电容耦合于输入节点与第三混频开关之间、另一部分第三滤波电容耦合于第三混频开关与第一放大器之间，部分第四滤波电容耦合于输入节点与第四混频开关之间、另一部分第四滤波电容耦合于第四混频开关与第一放大器之间。
在一些可能实现的方式中，上述双平衡无源混频器中第三混频开关包括第三晶体管，第四混频开关包括第四晶体管。第三晶体管的栅极耦合至第二本振信号输入端、第一极耦合至第二差分输入节点、第二极耦合至所述第一放大输入端；第四晶体管的栅极耦合至第一本振信号输入端、第一极耦合至第二差分输入节点、第二极耦合至第二放大输入端。
在一些可能实现的方式中，上述第一放大器的共模输入电压用于提供第一无源混频器中晶体管的直流偏置。
在一些可能实现的方式中，上述输入节点与低噪声放大器耦合，用于接收低噪声放大器输出的射频信号，以使集成电路接收噪声较低的射频信号。
在一些可能实现的方式中，上述集成电路还包括第五滤波电容和第六滤波电容。第 一放大器还包括第一放大输出端和第二放大输出端；第五滤波电容通过反馈放大方式耦合于第一放大输入端与第一放大输出端之间，第六滤波电容通过反馈放大方式耦合于第二放大输入端与第二放大输出端之间，以分别利用第一滤波电容与第二滤波电容、以及第一滤波电容与第三滤波电容实现带通滤波效果。
在一些可能实现的方式中，上述集成电路还包括第二无源混频器、第二放大器、第七滤波电容和第八滤波电容。输入节点还用于将射频信号输入至第五支路和第六支路，第五支路和第六支路耦合于输入节点与第二放大器之间。第二无源混频器包括第五混频开关和第六混频开关，第五支路包括串联的第七滤波电容和第五混频开关，第七滤波电容耦合于输入节点与第五混频开关之间；第六支路包括串联的第八滤波电容和第六混频开关，第八滤波电容耦合于输入节点与第六混频开关之间。第二无源混频器将射频信号与本振信号进行混频，以向第二放大器输入第二模拟信号；其中，第二模拟信号与第一模拟信号正交。本申请通过设置与第一无源混频器对应的第二无源混频器、与第一滤波电容对应的第四滤波电容，并利用第二无源混频器对射频信号和本振信号进行混频，可以提高射频信号的利用率。并且，第二无源混频器可以是单平衡无源混频器，以排除第一混频器的杂散产物。
在一些可能实现的方式中，第七滤波电容可以耦合于第五混频开关与第二放大器之间，第八滤波电容耦合于第六混频开关与第二放大器之间。或者，在第七滤波电容和第八滤波电容的个数为多个的情况下，部分第七滤波电容耦合于输入节点与第五混频开关之间、另一部分第七滤波电容耦合于第五混频开关与第二放大器之间，部分第八滤波电容耦合于输入节点与第六混频开关之间、另一部分第八滤波电容耦合于第六混频开关与第二放大器之间。
在一些可能实现的方式中，上述第二无源混频器中第五混频开关包括第五晶体管，第六混频开关包括第六晶体管。第五晶体管的栅极耦合至第三本振信号输入端、第一极耦合至输入节点、第二极耦合至第二放大器的第三放大输入端；第六晶体管的栅极耦合至第四本振信号输入端、第一极耦合至输入节点、第二极耦合至第二放大器的第四放大输入端。其中，第五晶体管从第三本振信号输入端接收第三本振信号，第六晶体管从第四本振信号输入端接收第四本振信号，第三本振信号与第四本振信号互为高低电平。
在一些可能实现的方式中，上述第二无源混频器还包括第七混频开关和第八混频开关，集成电路还包括第九滤波电容和第十滤波电容。在输入节点包括第一差分输入节点和第二差分输入节点的情况下，第五支路和第六支路与第一差分输入节点耦合；第二差分输入节点还用于将射频信号输入至第七支路和第八支路，第七支路和第八支路耦合于第二差分输入节点与第二放大器之间。第七支路包括串联的第九滤波电容和第七混频开关，第九滤波电容耦合于第二差分输入节点与第七混频开关之间；第八支路包括串联的第十滤波电容和第八混频开关，第十滤波电容耦合于第二差分输入节点与第八混频开关之间。本申请的第二无源混频器可以是双平衡无源混频器，以为集成电路提供更高的线性度。
在一些可能实现的方式中，第九滤波电容可以耦合于第七混频开关与第二放大器之间，第十滤波电容耦合于第八混频开关与第二放大器之间。或者，在第九滤波电容和第 十滤波电容的个数为多个的情况下，部分第九滤波电容耦合于输入节点与第七混频开关之间、另一部分第九滤波电容耦合于第七混频开关与第二放大器之间，部分第十滤波电容耦合于输入节点与第八混频开关之间、另一部分第十滤波电容耦合于第八混频开关与第二放大器之间。
在一些可能实现的方式中，上述第七混频开关包括第七晶体管，所述第八混频开关包括第八晶体管。第七晶体管的栅极耦合至第四本振信号输入端、第一极耦合至第二差分输入节点、第二极耦合至第三放大输入端；第八晶体管的栅极耦合至第三本振信号输入端、第一极耦合至第二差分输入节点、第二极耦合至第四放大输入端。
在一些可能实现的方式中，上述集成电路还包括无源过滤电路；第一混频开关和第二混频开关均包括串联的两个晶体管，无源过滤电路耦合于两个晶体管之间，可以利用无源过滤电路，使本申请的第一无源混频器构成窄道滤波混频器，滤除信号从无线发射机发送到无线接收机过程中的泄漏信号。
在一些可能实现的方式中，上述第一滤波电容和所述第二滤波电容包括MOM电容或MIM电容，以减小射频节点的寄生电容。
第二方面，本申请实施例提供一种无线接收机，所述无线接收机包括第一方面中任意所述的集成电路。集成电路中第一无源混频器的第一混频开关和第二混频开关用于对射频信号和本振信号进行下混频。
第三方面，本申请实施例提供一种终端，终端包括天线和第二方面所述的无线接收机，天线用于提供低噪声放大器需要的信号。
附图说明
图1为本申请实施例提供的终端一个应用场景示意图；
图2为本申请实施例提供的一个集成电路的电路图；
图3为本申请实施例提供的又一个集成电路的电路图；
图4为本申请实施例提供的一个无线接收机的电路图；
图5为本申请实施例提供的又一个无线接收机的电路图；
图6为本申请实施例提供的另一个无线接收机的电路图；
图7为本申请实施例提供的另一个无线接收机的电路图；
图8为本申请实施例提供的另一个集成电路的电路图；
图9为本申请实施例提供的另一个集成电路的电路图；
图10为本申请实施例提供的另一个集成电路的电路图；
图11为本申请实施例提供的本申请实施例与相关技术的输出增益的仿真对比图；
图12为本申请实施例提供的另一个集成电路的电路图；
图13为本申请实施例提供的另一个集成电路的电路图；
图14为本申请实施例提供的另一个集成电路的电路图；
图15为本申请实施例提供的另一个集成电路的电路图；
图16为本申请实施例提供的另一个集成电路的电路图；
图17为本申请实施例提供的另一个集成电路的电路图；
图18为本申请实施例提供的另一个集成电路的电路图；
图19为本申请实施例提供的另一个集成电路的电路图；
图20为本申请实施例提供的另一个集成电路的电路图；
图21为本申请实施例提供的第一无源混频器和第二无源混频器与本地振荡器的连接图；
图22为本申请实施例提供的另一个集成电路的电路图；
图23为本申请实施例提供的另一个集成电路的电路图；
图24为本申请实施例提供的另一个集成电路的电路图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一目标对象和第二目标对象等是用于区别不同的目标对象，而不是用于描述目标对象的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元；多个系统是指两个或两个以上的系统。
本申请实施例提供一种终端，利用滤波电容代替现有基于运算放大器的高通滤波器，同时使滤波电容共用耦合在无源混频器后的放大器，可以省去高通滤波器中运算放大器占用的版图面积和功耗；并且，以串联的方式将滤波电容与无源混频器集成在一起，还可以将版图设计得更加紧凑，从而进一步节省版图面积。
以下对本申请实施例提供的终端的具体结构和用途进行说明。
如图1所示，其示出了本申请实施例提供的终端1的一种应用场景示意图，终端1包括无线接收机10、数字电路20、以及控制电路30，数字电路20和控制电路30耦合至无线接收机10的输出端，且数字电路20耦合于无线接收机10与控制电路30之间。其中，如图2和图3所示，无线接收机10包括集成有无源混频器(图2和图3中的110)和滤波电容(图2和图3中的120)的集成电路100。
如图4所示，对于上述无线接收机10，除了包括上述集成电路100以外，无线接收 机10还可以包括本地振荡器101和模数转换电路102。集成电路100还可以包括输入节点A、本振信号输入端LO和输出端OUT。集成电路100的输入节点A与无线接收机10的输入端耦合、本振信号输入端LO与本地振荡器101的输出端耦合。输入节点A可以接收无线接收机10接收的射频信号，集成电路100可以通过输入节点A接收该射频信号、从本振信号输入端LO接收本地振荡器101发送的本振信号。当无线接收机10接收到射频信号时，可以在本振信号的控制下，利用无源混频器对射频信号和本振信号进行下混频，得到模拟信号，并利用滤波电容对经过模拟信号进行高通滤波，滤除无用信号和噪声，以提高接收信噪比；之后，可以利用模数转换电路102将模拟信号转换为数字信号，并将数字信号输入至数字电路20和控制电路30；数字电路20接收到数字信号后，可以对数字信号进行编码、解码等处理，并将处理结果输入至控制电路30，控制电路30可以根据接收的处理结果控制终端1实现与模拟信号对应的功能。
不同的终端1在不同处理结果的驱动下，所能实现的功能不同，本申请实施例对此不作限定。
例如，终端1为手机，控制电路30可以根据接收的处理结果，控制手机收到他人打来的电话，并在用户触发“接听”按钮时，接通电话并接收他人手机发来的音频信号。
又例如，终端1为雷达，控制电路30可以根据接收的处理结果，控制雷达对目标信号进行检测。
当然，终端1还可以是电脑、平板电脑、个人数字助理(personal digital assistant，简称PDA)、智能穿戴式设备、智能家居设备等，本申请实施例对此不作限定。
对于上述集成电路100，需要说明的是，其包含的各个器件可以集成在同一芯片上，该芯片可以仅包括集成电路100，也可以是除包括集成电路100以外，还包括其他器件。此情况下，上述输入节点A可以是该芯片的管脚，也可以是该芯片的内部节点。
当然，上述集成电路100的各个器件也可以集成在多个芯片上，各个器件间例如可以通过多个芯片的管脚实现耦合。此情况下，上述输入节点A可以是其中一个芯片的管脚，也可以是其中一个芯片的内部节点。
此外，上述终端1还可以包括天线，无线接收机10还可以包括其他器件，如图4-图7所示，无线接收机10还可以包括低噪声放大器(low noise amplifier，简称LNA)103和低通滤波器104。天线可以用于提供低噪声放大器需要的信号，低噪声放大器103与集成电路100的输入节点A耦合，作为无线接收机10中的前置放大器来降低噪声，输入节点A可以接收从低噪声放大器输出的射频信号；低通滤波器104耦合至集成电路100的输出端OUT，可以与集成电路100中的滤波电容构成带通滤波器，使特定频段的信号从无线接收机10输出。图4-图7以无线接收机10同时包括本地振荡器101、模数转换电路102、低噪声放大器103、以及低通滤波器104来举例，当然，在另一些实施例中，无线接收机10还可以根据需要不包括本地振荡器101、模数转换电路102、低噪声放大器103、以及低通滤波器104中的至少一个，或者，根据需要增加或减少本地振荡器101、模数转换电路102、低噪声放大器103、以及低通滤波器104的个数，本申请对此不作限定。
对于上述无线接收机10，还可以基于无源混频器的类型，在上述器件的基础上增加 其他器件。本申请的集成电路100中，无源混频器可以是电流型无源混频器，也可以是电压型无源混频器。同时，对于电流型无源混频器和电压型无源混频器，其可以是双平衡无源混频器，也可以是单平衡无源混频器。其中，双平衡无源混频器具有更高的线性度，单平衡无源混频器可以排除无源混频器中的杂散产物。
例如，如图4所示，无源混频器为单平衡的电压型无源混频器，无线接收机10可以仅包括上述本地振荡器101、模数转换电路102、低噪声放大器103、以及低通滤波器104。
又例如，如图5所示，无源混频器为单平衡的电流型无源混频器，无线接收机10在包括上述本地振荡器101、模数转换电路102、低噪声放大器103、以及低通滤波器104的基础上，还可以包括跨导电路(gm)105。跨导电路105耦合至集成电路100的输入节点A，可以将电压转换为电流，使射频信号以电流形式输入至集成电路100。
又例如，如图6所示，无源混频器为双平衡的电压型无源混频器，无线接收机10在包括上述本地振荡器101、模数转换电路102、低噪声放大器103、以及低通滤波器104的基础上，还可以包括平衡-不平衡变换器(balance-unbalance，简称BALUN)106。输入节点A包括第一差分输入节点A1和第二差分输入节点A2，平衡-不平衡变换器106分别耦合至集成电路100的第一差分输入节点A1和第二差分输入节点A2，可以将无线接收机10接收的射频信号差分输入至集成电路100。
又例如，如图7所示，无源混频器为双平衡的电流型无源混频器，无线接收机10在包括上述本地振荡器101、模数转换电路102、低噪声放大器103、以及低通滤波器104的基础上，还可以包括跨导电路105和平衡-不平衡变换器106。输入节点A包括第一差分输入节点A1和第二差分输入节点A2，平衡-不平衡变换器106和跨导电路105耦合至集成电路100的第一差分输入节点A1和第二差分输入节点A2，且跨导电路105耦合于平衡-不平衡变换器106与第一差分输入节点A1和第二差分输入节点A2之间。平衡-不平衡变换器106可以将无线接收机10接收的射频信号差分输入至集成电路100；跨导电路105可以将电压转换为电流，使射频信号以电流形式输入至集成电路100。
以下结合终端1和无线接收机10对上述集成电路100的电路结构进行具体说明。
如图8和图9所示，本申请以混频器为单平衡无源混频器为例，提供一种集成电路100，该集成电路100包括第一无源混频器110、第一放大器140、第一滤波电容120和第二滤波电容130。输入节点用于接收射频信号，并将射频信号输入至第一支路和第二支路，第一支路和第二支路耦合于输入节点A与第一放大器140之间。第一无源混频器110包括第一混频开111和第二混频开关112，第一支路包括串联的第一滤波电容120和第一混频开关111，第一滤波电容120耦合于输入节点A与第一混频开关111之间。第二支路包括串联的第二滤波电容130和第二混频开关112，第二滤波电容130耦合于输入节点A与第二混频开关112之间。第一无源混频器110将射频信号与本振信号进行混频，以向第一放大器140输入第一模拟信号。
在一些可能实现的方式中，第一无源混频器110的第一混频开关111和第二混频开关112可以均包括至少一个开关管，该开关管可以是晶体管。其中，晶体管的栅极可以与本振信号输入端(图8中的LO n和LO p)耦合、第一极可以与集成电路100的输入节点A耦合、第二极可以与第一放大器140耦合。其中，第一放大器140包括第一放大输 入端IN1和第二放大输入端IN2，第一混频开关111中晶体管的第二极与第一放大输入端IN1耦合，第二混频开关112中晶体管的第二极与第二放大输入端IN2耦合。第一放大器140的共模输入电压用于提供第一无源混频器110中晶体管的直流偏置。以第一无源混频器110为电压型无源混频器为例，第一混频开关111中晶体管的源漏直流电平与第一放大器140的第一放大输入端IN1的输入直流电平相同，第二混频开关112中晶体管的源漏直流电平与第一放大器140的第二放大输入端IN2的输入直流电平相同。
此处需要说明的是，晶体管的第一极为源极，第二极为漏极；或者，晶体管的第一极为漏极，第二极为源极。下文除另外说明以外，以第一混频开关111和第二混频开关112均包括晶体管为例进行说明。
在一些可能实现的方式中，如图8所示，第一混频开关111和第二混频开关112的晶体管可以均为N型晶体管；或者，如图9所示，第一混频开关111和第二混频开关112的晶体管也可以均为P型晶体管；或者，第一混频开关111和第二混频开关112的晶体管可以既包括N型晶体管，也包括P型晶体管。以N型晶体管和P型晶体管应用于第一混频开关111为例，其工作原理分别为：
例如，以第一混频开关111包括一个晶体管、且该晶体管为N型晶体管为例，在晶体管的栅极从本振信号输入端接收到的本振信号相对于晶体管的源漏电压为高电平时，第一混频开关111导通；在晶体管的栅极从本振信号输入端接收到的本振信号相对于晶体管的源漏电压为低电平时，第一混频开关111截止。
又例如，以第一混频开关111包括一个晶体管、且该晶体管为P型晶体管为例，在晶体管的栅极从本振信号输入端接收到的本振信号相对于晶体管的源漏电压为高电平时，第一混频开关111截止；在晶体管的栅极从本振信号输入端接收到的本振信号相对于晶体管的源漏电压为低电平时，第一混频开关111导通。
在一些可能实现的方式中，本申请的集成电路100中各个器件的功能为：第一混频开关111和第二混频开关112分别用于对各自接收的本振信号和射频信号进行混频，以得到第一模拟信号，第一滤波电容120和第二滤波电容130用于对第一模拟信号进行高通滤波，并将高通滤波后的第一模拟信号输入至第一放大器140，利用第一放大器140将高通滤波后的第一模拟信号放大为所需的信号大小。
可以理解的是，本申请实施例通过使第一滤波电容120和第一混频开关111串联于第一支路上，使第二滤波电容130和第二混频开关112串联于第二支路上，提供了一种新的连接方式，一方面，可以利用第一滤波电容120和第二滤波电容130代替图10所示的相关技术中基于运算放大器的高通滤波器2000，以省去运算放大器占用的版图面积和功耗；另一方面，相较于相关技术在整个第一无源混频器110后连接高通滤波器200的方案，本申请实施例还可以将集成电路100的版图设计得更加紧凑，从而进一步节省集成电路100的版图面积；另一方面，本申请通过将第一滤波电容120耦合于输入节点A与第一混频开关111之间，第二滤波电容130耦合于输入节点A与第二混频开关112之间，以使第一滤波电容120和第二滤波电容130还具有隔直作用，当集成电路100应用于无线接收机10时，可以省去无线接收机10中的隔直电容1000。
对于图10所示的相关技术中的隔直电容1000，与本申请实施例中的第一滤波电容 120和第二滤波电容130的区别。第一，二者的连接方式不同，相关技术的隔直电容1000耦合在无线接收机10的输入端与输入节点A之间，而本申请实施例的第一滤波电容120耦合于输入节点A与第一混频开关111之间、第二滤波电容130耦合于输入节点A与第二混频开关112之间。第二，二者实现的作用不同，相关技术的隔直电容1000只能起到隔直作用，而本申请的第一滤波电容120和第二滤波电容130不但可以起到隔直作用，还可以起到高通滤波作用，具体的，对第一滤波电容120和第二滤波电容130与隔直电容1000的高通滤波作用分析如下：
图11示出了相关技术与本申请的仿真对比图，其中，实线为图10所示的无线接收机10在不包括高通滤波器2000时，其输出增益与接收的射频信号之间的仿真关系图。可以看出，无线接收机10接收任意频段的射频信号，其输出增益始终保持不变，因此，无线接收机10中的隔直电容1000不能起到高通滤波作用。
图11中的虚线为本申请实施例的集成电路100应用于无线接收机10时，无线接收机10的输出增益与接收的射频信号之间的仿真关系图。假设3.5GHz的射频信号与本振信号混频后，得到的第一模拟信号为0Hz，此时第一模拟信号为低频率的信号。从图11可以看出，在射频信号为3.5GHz处，由于第一滤波电容120和第二滤波电容130将第一模拟信号滤除，导致输出增益大幅降低。由此可以得出，本申请实施例的第一滤波电容120和第二滤波电容130可以起到高通滤波的作用。
基于上述，相关技术中将隔直电容1000耦合在无线接收机10的输入端与输入节点A之间的方案，不能代替本申请实施例将第一滤波电容120耦合在输入节点A与第一混频开关111之间、将第二滤波电容130耦合在输入节点A与第二混频开关112之间的方案。
此外，对于与第一混频开关111串联的第一滤波电容120的个数，和与第二混频开关112串联的第二滤波电容130的个数，在一些可能实现的方式中，如图8和图9所示，第一滤波电容120的个数与第二滤波电容130的个数可以相同，例如，第一滤波电容120的个数与第二滤波电容130的个数均为一个；在一些可能实现的方式中，与第一混频开关111串联的第一滤波电容120的个数，和与第二混频开关112串联的第二滤波电容130的个数也可以不相同，例如，第一滤波电容120的个数为一个，第二滤波电容130的个数为两个。考虑到第一滤波电容120与第二滤波电容130的个数不同，可能导致从第一支路和第二支路输出的信号的数值存在偏差，因此，可选的，与第一滤波电容120和第二滤波电容130的个数相同。
图8和图9示出了第一滤波电容120与第二滤波电容130的个数相同的情况下，第一滤波电容120和第二滤波电容130的个数可以是一个或多个。在一些可能实现的方式中，如图8所示，第一混频开关111与一个第一滤波电容120串联，第二混频开关112与一个第二滤波电容130串联；在一些可能实现的方式中，如图9所示，第一混频开关111与多个第一滤波电容120串联，第二混频开关112与多个第二滤波电容130串联。由于本申请实施例可以利用一个电容值较小的第一滤波电容120代替多个电容值较大的第一滤波电容120，利用一个电容值较小的第二滤波电容130代替多个电容值较大的第二滤波电容130，因此，可选的，第一滤波电容120和第二滤波电容130的个数可以均为一个， 以节省集成电路100的版图面积。
对于上述第一滤波电容120和第二滤波电容130的类型，本申请不作限定，第一滤波电容120和第二滤波电容130可以是任意类型的电容，例如，第一滤波电容120和第二滤波电容130可以是金属-氧化物-金属(metal oxide metal，简称MOM)电容、金属-电介质-金属(metal insulator metal，简称MIM)电容、场效应(metal-oxide-semiconductor，简称MOS)管电容等。为了减小射频节点的寄生电容，可选的，第一滤波电容120和第二滤波电容130可以是MOM电容或MIM电容。
此外，在一些可能实现的方式中，如图12所示，第一滤波电容120可以耦合于第一混频开关111与第一放大输入端IN1之间，第二滤波电容130可以耦合于第二混频开关112与第二放大输入端IN2之间，此情况下，第一无源混频器110中晶体管的源漏直流电平与其上一级电路的输入直流电平相同。或者，在另一些可能实现的方式中，如图13所示，第一滤波电容120和第二滤波电容130的个数都为多个，部分第一滤波电容120耦合于输入节点A与第一混频开关111之间、另一部分第一滤波电容120耦合于第一混频开关111与第一放大输入端IN1之间，部分第二滤波电容130耦合于输入节点A与第二混频开关112之间、另一部分第二滤波电容130耦合于第二混频开关112与第二放大输入端IN2之间。
下面以第一无源混频器110为单平衡无源混频器为例，对集成电路100的具体电路结构进行说明，在一些可能实现的方式中，如图8所示，第一混频开关111可以包括第一晶体管T1，第二混频开关112可以包括第二晶体管T2。本振信号输入端包括第一本振信号输入端LO p和第二本振信号输入端LO n。第一晶体管T1的栅极耦合至第一本振信号输入端LO p、第一极耦合至输入节点A、第二极耦合至第一放大器140的第一放大输入端IN1；第二晶体管T2的栅极耦合至第二本振信号输入端LO n、第一极耦合至输入节点A、第二极耦合至第一放大器140的第二放大输入端IN2。第一晶体管T1从第一本振信号输入端LO p接收第一本振信号，第二晶体管T2从第二本振信号输入端LO n接收第二本振信号，第一本振信号与第二本振信号互为高低电平。此处需要说明的是，第一本振信号与第二本振信号互为高低电平，即，第一本振信号为高电平，第二本振信号为低电平；或者，第一本振信号为低电平，第二本振信号为高电平。
基于上述电路结构，下面以第一晶体管T1和第二晶体管T2均为N型晶体管，来举例介绍第一无源混频器110、第一滤波电容120和第二滤波电容130的工作过程。其工作过程可以包括第一阶段和第二阶段，具体为：
在第一阶段，参考图8，第一本振信号为高电平，第二本振信号为低电平，第一晶体管T1导通，第二晶体管T2截止。第一晶体管T1和与第一晶体管T1串联的第一滤波电容120通过输入节点A接收射频信号，第一晶体管T1从第一本振信号输入端LO p接收第一本振信号，利用第一晶体管T1对射频信号与第一本振信号进行混频得到第一模拟信号，利用第一滤波电容120对第一模拟信号进行高通滤波得到第一输出信号，并输出第一输出信号至第一放大输入端IN1。
在第二阶段，请继续参考图8，第一本振信号为低电平，第二本振信号为高电平，第一晶体管T1截止，第二晶体管T2导通。第二晶体管T2和与第二晶体管T2串联的第二 滤波电容130通过输入节点A接收射频信号，第二晶体管T2从第二本振信号输入端LO n接收第二本振信号，利用第二晶体管T2对射频信号与第二本振信号进行混频得到第一模拟信号，利用第二滤波电容130对第一模拟信号进行高通滤波得到第二输出信号，并输出第二输出信号至第二放大输入端IN2。第一输出信号与第二输出信号构成一组差分输出信号，第一输出信号为正时，第二输出信号为负；或者，第一输出信号为负时，第二输出信号为正。
此处需要说明的是，在上述工作过程中，也可以是第一阶段的第二本振信号为高电平、第一本振信号为低电平，第二阶段的第一本振信号为高电平、第二本振信号为低电平，本申请实施例对此不作限定。此外，对于上述第一晶体管T1和第二晶体管T2，其第一极为源极，第二极为漏极；或者，第一极为漏极，第二极为源极。
如图14所示，在一些实施例中，第一无源混频器110也可以为双平衡无源混频器。双平衡的第一无源混频器110还包括第三混频开关113和第四混频开关114，集成电路100还包括第三滤波电容150和第四滤波电容160。输入节点A包括第一差分输入节点A1和第二差分输入节点A2，第一支路和第二支路与第一差分输入节点A1耦合(也可以说，第一支路和第二支路耦合于第一差分输入节点A1与第一放大器之间)，第一差分输入节点A1可以向第一支路和第二支路输入第一射频信号。第二差分输入节点A2用于将第二射频信号输入至第三支路和第四支路，第三支路和第四支路耦合于第二差分输入节点A2与第一放大器140之间。其中，第一射频信号与第二射频信号构成一组差分信号，第一射频信号为正时，第二射频信号为负；或者，第一射频信号为负时，第二射频信号为正。
第三支路包括串联的第三滤波电容150和第三混频开关113，第三滤波电容150耦合于第二差分输入节点A2与第三混频开关113之间；第四支路包括串联的第四滤波电容160和第四混频开关114，第四滤波电容160耦合于第二差分输入节点A2与第四混频开关114之间。
对于双平衡的第一无源混频器110，集成电路100中各个器件的功能为：第一混频开关111、第二混频开关112、第三混频开关113、以及第四混频开关114分别用于对各自接收的本振信号和射频信号进行混频，以得到第一模拟信号。第一滤波电容120、第二滤波电容130、第三滤波电容150、以及第四滤波电容160用于对第一模拟信号进行高通滤波，并将高通滤波后的第一模拟信号输入至第一放大器140。利用第一放大器140可以将高通滤波后的第一模拟信号放大为所需的信号大小。
此外，对于第一滤波电容120的个数、第二滤波电容130的个数、第三滤波电容150的个数、以及第四滤波电容160的个数，在一些可能实现的方式中，如图14所示，第一滤波电容120的个数、第二滤波电容130的个数、第三滤波电容150的个数、以及第四滤波电容160的个数可以均相同，例如，第一滤波电容120的个数、第二滤波电容130的个数、第三滤波电容150的个数、以及第四滤波电容160的个数均为一个；在一些可能实现的方式中，第一滤波电容120的个数、第二滤波电容130的个数、第三滤波电容150的个数、以及第四滤波电容160的个数也可以不相同，例如，第一滤波电容120和第三滤波电容150的个数为一个，第二滤波电容130和第四滤波电容160的个数为两个。 考虑到第一滤波电容120、第二滤波电容130、第三滤波电容150、以及第四滤波电容160的个数不同，可能导致从第一支路、第二支路、第三支路和第四支路输出的信号的数值存在偏差，因此，可选的，第一滤波电容120、第二滤波电容130、第三滤波电容150和第四滤波电容160的个数相同。
图14示出了第三滤波电容150与第四滤波电容160的个数相同的情况下，第三滤波电容150和第四滤波电容160的个数可以是一个或多个。在一些可能实现的方式中，如图14所示，第三混频开关113与一个第三滤波电容150串联，第四混频开关114与一个第四滤波电容160串联；在一些可能实现的方式中，如图15所示，第三混频开关113与多个第三滤波电容150串联，第四混频开关114与多个第四滤波电容160串联。由于本申请实施例可以利用一个电容值较小的第三滤波电容150代替多个电容值较大的第三滤波电容150，利用一个电容值较小的第四滤波电容160代替多个电容值较大的第四滤波电容160，因此，可选的，第三滤波电容150和第四滤波电容160的个数可以均为一个，以节省集成电路100的版图面积。对于双平衡的第一无源混频器110中第一滤波电容120和第二滤波电容130的说明可以参考前述实施例，在此不再赘述。
对于上述第三滤波电容150和第四滤波电容160的类型，本申请不作限定，第三滤波电容150和第四滤波电容160可以是任意类型的电容，例如，第三滤波电容150和第四滤波电容160可以是MOM电容、MIM电容、MOS管电容等。为了减小射频节点的寄生电容，可选的，第三滤波电容150和第四滤波电容160可以是MOM电容或MIM电容。
此外，在一些可能实现的方式中，如图16所示，第三滤波电容150可以耦合于第三混频开关113与第一放大输入端IN1之间，第四滤波电容160可以耦合于第四混频开关114与第二放大输入端IN2之间，此情况下，第一无源混频器110中晶体管的源漏直流电平与其上一级电路的输入直流电平相同。或者，在另一些可能实现的方式中，如图17所示，第三滤波电容150和第四滤波电容160的个数都为多个，部分第三滤波电容150耦合于输入节点A与第三混频开关113之间、另一部分第三滤波电容150耦合于第三混频开关113与第一放大输入端IN1之间，部分第四滤波电容160耦合于输入节点A与第四混频开关114之间、另一部分第四滤波电容160耦合于第四混频开关114与第二放大输入端IN2之间。
下面以第一无源混频器110为双平衡无源混频器为例，对集成电路100的具体电路结构进行说明，在一些可能实现的方式中，如图14所示，在第一混频开关111包括第一晶体管T1，第二混频开关112包括第二晶体管T2的情况下，第三混频开关113包括第三晶体管T3，第四混频开关114包括第四晶体管T4。第三晶体管T3的栅极耦合至第二本振信号输入端LO n、第一极耦合至第二差分输入节点A2、第二极耦合至第一放大输入端IN1；第四晶体管T4的栅极耦合至第一本振信号输入端LO p、第一极耦合至第二差分输入节点A2、第二极耦合至第二放大输入端IN2。
基于上述电路结构，下面以第一晶体管T1、第二晶体管T2、第三晶体管T3、以及第四晶体管T4均为N型晶体管，来举例介绍第一无源混频器110、第一滤波电容120、第二滤波电容130、第三滤波电容150、以及第四滤波电容160的工作过程。其工作过程 可以包括第一阶段和第二阶段，具体为：
在第一阶段，参考图14，第一本振信号为高电平，第二本振信号为低电平，第一晶体管T1和第四晶体管T4导通，第二晶体管T2和第三晶体管T3截止。第一晶体管T1和与第一晶体管T1串联的第一滤波电容120通过第一差分输入节点A1接收第一射频信号，第一晶体管T1从第一本振信号输入端LO p接收第一本振信号，利用第一晶体管T1对第一射频信号与第一本振信号进行混频得到第一模拟信号，利用第一滤波电容120对第一模拟信号进行高通滤波得到第一输出信号，并输出第一输出信号至第一放大输入端IN1。第四晶体管T4和与第四晶体管T4串联的第四滤波电容160通过第二差分输入节点A2接收第二射频信号，第四晶体管T4从第一本振信号输入端LO p接收第一本振信号，利用第四晶体管T4对第二射频信号与第一本振信号进行混频得到第一模拟信号，利用第四滤波电容160对第一模拟信号进行高通滤波得到第二输出信号，并输出第二输出信号至第二放大输入端IN2。
在第二阶段，请继续参考图14，第一本振信号为低电平，第二本振信号为高电平，第一晶体管T1和第四晶体管T4截止，第二晶体管T2和第三晶体管T3导通。第二晶体管T2和与第二晶体管T2串联的第二滤波电容130通过第一差分输入节点A1接收第一射频信号，第二晶体管T2从第二本振信号输入端LO n接收第二本振信号，利用第二晶体管T2对第一射频信号与第二本振信号进行混频得到第一模拟信号，利用第二滤波电容130对第一模拟信号进行高通滤波得到第二输出信号，并输出第二输出信号至第二放大输入端IN2。第三晶体管T3和与第三晶体管T3串联的第三滤波电容150通过第二差分输入节点A2接收第二射频信号，第三晶体管T3从第二本振信号输入端LO n接收第二本振信号，利用第三晶体管T3对第二射频信号与第二本振信号进行混频得到第一模拟信号，利用第三滤波电容150对第一模拟信号进行高通滤波得到第一输出信号，并输出第一输出信号至第一放大输入端IN1。
此处需要说明的是，在上述工作过程中，也可以是第一阶段的第二本振信号为高电平、第一本振信号为低电平，第二阶段的第一本振信号为高电平、第二本振信号为低电平，本申请实施例对此不作限定。此外，对于上述第一晶体管T1～第四晶体管T4，其第一极为源极，第二极为漏极；或者，第一极为漏极，第二极为源极。
在一些实施例中，为了使集成电路100输出特定频段的信号，如图18所示，集成电路100还可以包括第五滤波电容170和第六滤波电容180。第一放大器140还包括第一放大输出端OUT1和第二放大输出端OUT2。第五滤波电容170通过反馈放大方式耦合于第一放大输入端IN1与第一放大输出端OUT1之间，第六滤波电容180通过反馈放大方式耦合于第二放大输入端IN2与第二放大输出端OUT2之间，以分别利用第一滤波电容120和第二滤波电容130(也可以是第一滤波电容、第二滤波电容、第三滤波电容、以及第四滤波电容)与第五滤波电容170和第六滤波电容180实现带通滤波效果。
以输入集成电路100的射频信号的通带为100kHz以上为例，利用第一滤波电容120和第二滤波电容130(也可以是第一滤波电容、第二滤波电容、第三滤波电容、以及第四滤波电容)可以使100kHz以上的信号通过，之后再利用第五滤波电容170和第六滤波电容180，使100MHz以下的信号通过，即，最终使100kHz～100MHz之间的信号从集成电 路100输出。
在一些可能实现的方式中，本申请实施例不对第五滤波电容170和第六滤波电容180的个数进行限定，上述第五滤波电容170和第六滤波电容180的个数可以为一个，也可以为多个。在第五滤波电容170的个数为多个的情况下，多个第五滤波电容170可以通过反馈放大方式串联在第一放大输入端IIN1与第一放大输出端OUT1之间；在第六滤波电容180的个数为多个的情况下，多个第六滤波电容180可以通过反馈放大方式串联在第一放大输入端IN1与第一放大输出端OUT1之间。本申请中，可以利用一个电容值较小的第五滤波电容170，代替多个电容值较大的第五滤波电容170，利用一个电容值较小的第六滤波电容180，代替多个电容值较大的第六滤波电容180，因此，可选的，第五滤波电容170和第六滤波电容180的个数可以均为一个，以节省集成电路100的版图面积。
在一些可能实现的方式中，不对第五滤波电容170和第六滤波电容180的类型进行限定，第五滤波电容170和第六滤波电容180可以是任意类型的电容，例如，第五滤波电容170和第六滤波电容180可以是MOS管电容、MOM电容、MIM电容等。
在一些实施例中，如图19所示，为了提高射频信号的利用率，在一些应用场景中，集成电路100还可以包括第二无源混频器190、第二放大器200、第七滤波电容210和第八滤波电容220。输入节点A还用于将射频信号输入至第五支路和第六支路，第五支路和第六支路耦合于输入节点A与第二放大器200之间。在第二无源混频器190为单平衡无源混频器的情况下，第二无源混频器190包括第五混频开关115和第六混频开关116，第五支路包括串联的第七滤波电容210和第五混频开关115，第七滤波电容210耦合于输入节点A与第五混频开关115之间。第六支路包括串联的第八滤波电容220和第六混频开关116，第八滤波电容220耦合于输入节点A与第六混频开关116之间。第二无源混频器190将射频信号与本振信号进行混频，以向第二放大器200输入第二模拟信号，其中，第二模拟信号与第一模拟信号正交，也可以说，第一模拟信号与第二模拟信号的输出相位差为π/2。
当然，参考图20，第二无源混频器190也可以是双平衡无源混频器，此情况下，第五支路和第六支路与第一差分输入节点A1耦合，也可以说，第五支路和第六支路耦合于第一差分输入节点A1与第二放大器200之间，第一差分输入节点A1用于向第五支路和第六支路输入第一射频信号。第二差分输入节点A2还用于将第二射频信号输入至第七支路和第八支路，第七支路和第八支路耦合于第二差分输入节点A2与第二放大器200之间。
集成电路100还包括第九滤波电容230和第十滤波电容240，第二无源混频器190还包括第七混频开关117和第八混频开关118。第七支路包括串联的第九滤波电容230和第七混频开关117，第九滤波电容230耦合于第二差分输入节点A2与第七混频开关117之间；第八支路包括串联的第十滤波电容240和第八混频开关118，第十滤波电容240耦合于第二差分输入节点A2与第八混频开关118之间。
在一些可能实现的方式中，对于单平衡的第二无源混频器190和双平衡的无源混频器190，其可以通过本振信号输入端从本地振荡器101接收本振信号。如图21所示，本振信号输入端可以包括第一本振信号输入端LO I，p、第二本振信号输入端LO I，n、第三本振信号输入端LO Q，p、以及第四本振信号输入端LO Q，n。本地振荡器101包括第一本振 信号输出端V1和第二本振信号输出端V2。
请继续参考图21，本地振荡器101可以从第一本振信号输出端V1分时通过第一本振信号输入端LO I，p向第一混频开关111(也可以是第一混频开关和第四混频开关)输入第一本振信号，通过第三本振信号输入端LO Q，p向第五混频开关115(也可以是第五混频开关115和第八混频开关118)输入第三本振信号，第一本振信号和第三本振信号的相位差可以为π/2，以使第二模拟信号与第一模拟信号正交，也可以说，使输出的第二模拟信号与第一模拟信号的相位差为π/2。
请继续参考图21，本地振荡器101可以从第二本振信号输出端V2分时通过第二本振信号输入端LO I，n向第二混频开关112(也可以是第二混频开关和第三混频开关)输入第二本振信号，通过第四本振信号输入端LO Q，n向第六混频开关116(也可以是第六混频开关116和第七混频开关117)输入第四本振信号，第二本振信号和第四本振信号的相位差可以为π/2，第二模拟信号与第一模拟信号正交，也可以说，使输出的第二模拟信号与第一模拟信号的相位差为π/2。其中，第一本振信号与第二本振信号互为高低电平，第三本振信号与第四本振信号互为高低电平，第一本振信号与第三本振信号同为高电平或低电平，第二本振信号与第四本振信号同为低电平或高电平。
在一些可能实现的方式中，第五混频开关115和第六混频开关116(也可以是第五混频开关115、第六混频开关116、第七混频开关117、以及第八混频开关118)可以包括至少一个开关管，该开关管可以是晶体管。如图19所示，第二无源混频器190中的晶体管可以均为P型晶体管；或者，如图20所示，第二无源混频器190中多个第二混频开关112的晶体管也可以均为N型晶体管；或者，第二无源混频器190中的多个晶体管可以既包括N型晶体管，也包括P型晶体管。
此外，对于第七滤波电容210、第八滤波电容220、第九滤波电容230、以及第十滤波电容240的数量和类型的说明，可以参考前述实施例第一滤波电容120、第二滤波电容130、第三滤波电容150、以及第四滤波电容160的说明，在此不再赘述。
此外，在一些可能实现的方式中，第七滤波电容210可以耦合于第五混频开关115与第一放大输入端IN1之间，第八滤波电容220可以耦合于第六混频开关116与第二放大输入端IN2之间，第九滤波电容230可以耦合于第七混频开关117与第一放大输入端IN1之间，第十滤波电容240可以耦合于第八混频开关118与第二放大输入端IN2之间。或者，在另一些可能实现的方式中，第七滤波电容210、第八滤波电容220、第九滤波电容230、以及第十滤波电容240的个数为多个，部分第七滤波电容210耦合于输入节点A与第五混频开关115之间、另一部分第七滤波电容210耦合于第五混频开关115与第一放大输入端IN1之间，部分第八滤波电容220耦合于输入节点A与第六混频开关116之间、另一部分第八滤波电容220耦合于第六混频开关116与第二放大输入端IN2之间，部分第九滤波电容230耦合于输入节点A与第七混频开关117之间、另一部分第九滤波电容230耦合于第七混频开关117与第一放大输入端IN1之间，部分第十滤波电容240耦合于输入节点A与第八混频开关118之间、另一部分第十滤波电容240耦合于第八混频开关118与第二放大输入端IN2之间。
下面以第二无源混频器190为单平衡无源混频器为例，对集成电路100的具体电路 结构进行说明，在一些可能实现的方式中，如图19所示，第五混频开关115包括第五晶体管T5，第六混频开关116包括第六晶体管T6。第五晶体管T5的栅极耦合至第三本振信号输入端LO Q，p、第一极耦合至输入节点A、第二极耦合至第二放大器200的第三放大输入端IN3；第六晶体管T6的栅极耦合至第四本振信号输入端LO Q，n、第一极耦合至输入节点A、第二极耦合至第二放大器200的第四放大输入端IN4。
基于上述电路结构，下面以第五晶体管T5和第六晶体管T6均为N型晶体管，来举例介绍第二无源混频器190的工作过程。其工作过程可以包括第三阶段和第四阶段，具体为：
在第三阶段，参考图19，第三本振信号为高电平，第四本振信号为低电平，第五晶体管T5导通，第六晶体管T6截止。第五晶体管T5和与第五晶体管T5串联的第七滤波电容210通过输入节点A接收射频信号，第五晶体管T5从第三本振信号输入端LO Q，p接收第三本振信号，利用第五晶体管T5对射频信号与第三本振信号进行混频得到第二模拟信号，利用第七滤波电容210对第二模拟信号进行高通滤波得到第三输出信号，并输出第三输出信号至第三放大输入端IN3。
在第四阶段，请继续参考图19，第三本振信号为低电平，第四本振信号为高电平，第五晶体管T5截止，第六晶体管T6导通。第六晶体管T6和与第六晶体管T6串联的第八滤波电容220通过输入节点A接收射频信号，第六晶体管T6从第四本振信号输入端LO Q，n接收第四本振信号，利用第六晶体管T6对射频信号与第四本振信号进行混频得到第二模拟信号，并利用第八滤波电容220对第二模拟信号进行高通滤波得到第四输出信号，并输出第四输出信号至第四放大输入端IN4。第三输出信号与第四输出信号构成一组差分输出信号，第三输出信号为正时，第四输出信号为负；或者，第三输出信号为负时，第四输出信号为正。
在另一些可能实现的方式中，以第二无源混频器190为双平衡无源混频器为例，对集成电路100的具体电路结构进行说明，如图20所示，在第五混频开关115包括第五晶体管T5，第六混频开关116包括第六晶体管T6的情况下，第七混频开关117包括第七晶体管T7，第八混频开关118包括第八晶体管T8。第七晶体管T7的栅极耦合至第四本振信号输入端LO Q，n、第一极耦合至第二差分输入节点A2、第二极耦合至第三放大输入端IN3；第八晶体管T8的栅极耦合至第三本振信号输入端LO Q，p、第一极耦合至第二差分输入节点A2、第二极耦合至第四放大输入端IN4。
基于上述电路结构，下面以第五晶体管T5、第六晶体管T6、第七晶体管T7、以及第八晶体管T8均为N型晶体管，来举例介绍第二无源混频器190的工作过程。其工作过程可以包括第三阶段和第四阶段，具体为：
在第三阶段，参考图20，第三本振信号为高电平，第四本振信号为低电平，第五晶体管T5和第八晶体管T8导通，第六晶体管T6和第七晶体管T7截止。第五晶体管T5和与第五晶体管T5串联的第七滤波电容210通过第一差分输入节点A1接收第一射频信号，第五晶体管T5从第三本振信号输入端LO Q，p接收第三本振信号，利用第五晶体管T5对第一射频信号与第三本振信号进行混频得到第二模拟信号，利用第七滤波电容210对第二模拟信号进行高通滤波得到第三输出信号，并输出第三输出信号至第三放大输入 端IN3。第八晶体管T8和与第八晶体管T8串联的第十滤波电容240通过第二差分输入节点A2接收第二射频信号，第八晶体管T8从第三本振信号输入端LO Q，p接收第三本振信号，利用第八晶体管T8对第二射频信号与第三本振信号进行混频得到第二模拟信号，利用第十滤波电容240对第二模拟信号进行高通滤波得到第四输出信号，并输出第四输出信号至第四放大输入端IN4。
在第四阶段，请继续参考图20，第三本振信号为低电平，第四本振信号为高电平，第五晶体管T5和第八晶体管T8截止，第六晶体管T6和第七晶体管T7导通。第六晶体管T6和与第六晶体管T6串联的第八滤波电容220通过第一差分输入节点A1接收第一射频信号，第六晶体管T6从第四本振信号输入端LO Q，n接收第四本振信号，利用第六晶体管T6对第一射频信号与第四本振信号进行混频得到第二模拟信号，利用第八滤波电容220对第二模拟信号进行高通滤波得到第四输出信号，并输出第四输出信号至第四放大输入端IN4。第七晶体管T7和与第七晶体管T7串联的第九滤波电容230通过第二差分输入节点A2接收第二射频信号，第七晶体管T7从第四本振信号输入端LO Q，n接收第四本振信号，利用第七晶体管T7对第二射频信号与第四本振信号进行混频得到第二模拟信号，并利用第九滤波电容230对第二模拟信号进行高通滤波得到第四输出信号，并输出第四输出信号至第三放大输入端IN3。
上述示例仅详细描述了集成电路100在第三阶段和第四阶段的工作过程，可以理解的是，在集成电路100包括第一无源混频器110和第二无源混频器190的情况下，其完整的工作过程应包括第一阶段、第二阶段、第三阶段、以及第四阶段。以一个第一阶段、一个第二阶段、一个第三阶段和一个第四阶段作为一个完整的周期为例，由于第一本振信号与第三本振信号正交、第二本振信号与第四本振信号正交，因此，第一阶段与第三阶段在时间上相差1/4个周期，第二阶段与第四阶段在时间上相差1/4个周期。例如，集成电路100可以以第一阶段、第三阶段、第二阶段、第四阶段的顺序工作。
此外，在上述工作过程中，也可以是第三阶段的第四本振信号为高电平、第三本振信号为低电平，第四阶段的第三本振信号为高电平、第四本振信号为低电平，本申请实施例对此不作限定。此外，对于上述第五晶体管T5～第八晶体管T8，其第一极为源极，第二极为漏极；或者，第一极为漏极，第二极为源极。
在一些实施例中，对于前述的第一放大器140和第二放大器200，在一些可能实现的方式中，若第一无源混频器110和第二无源混频器190为电流型无源混频器，则如图19和图20所示，第一放大器140和第二放大器200可以是跨阻放大器(transimpedance amplifier，简称TIA)等基于运算放大器的反馈放大器；如图22所示，第一放大器140和第二放大器200也可以利用晶体管共栅放大器结构等非运算放大器作为跨阻级实现第一放大器140和第二放大器200的放大功能。若第一无源混频器110和第二无源混频器190为电压型无源混频器，则第一放大器140和第二放大器200可以是运算放大器；如图23所示，第一放大器140和第二放大器200也可以利用晶体管共栅放大器结构等非运算放大器实现第一放大器140功能。
图19和图20示出了第一放大器140和第二放大器200为跨阻放大器，以第一放大器140为例，跨阻放大器可以包括运算放大器141、第一反馈电阻142、以及第二反馈电 阻143，第一反馈电阻142通过反馈放大方式耦合于第一放大输入端IN1与第一放大输出端OUT1之间，第二反馈电阻143通过反馈放大方式耦合于第二放大输入端IN2与第二放大输出端OUT2之间。利用跨阻放大器，可以将电流形式的第一输出信号和第二输出信号转换为电压形式并输出。
图22和图23示出了以非运算放大器结构实现第一放大器140。在一些可能实现的方式中，如图22所示，以第一无源混频器110为电流型无源混频器为例，第一放大器140可以包括工作电压端VDD、接地端VSS、第九晶体管T9、以及第十晶体管T10，第九晶体管T9和第十四晶体管T14的第一极与工作电压端VDD耦合、第二极与接地端VSS耦合，可以通过第九晶体管T9和第十晶体管T10的源极作为放大器输入进行放大。在一些可能实现的方式中，如图23所示，以第一无源混频器110为电压型无源混频器为例，第一放大器140可以包括工作电压端VDD、接地端VSS、第九晶体管T9、第十晶体管T10、以及偏置电阻R，第九晶体管T9和第十晶体管T10的栅极与第一无源混频器110的输出耦合、第一极与工作电压端VDD耦合、第二极与接地端VSS耦合，可以通过第九晶体管T9和第十晶体管T10的栅极作为放大器输入进行放大。
在一些实施例中，如图24所示，集成电路100还可以包括无源过滤电路300；第一混频开关111和第二混频开关112(也可以是第一混频开关、第二混频开关、第三混频开关、以及第四混频开关，或者，第一混频开关、第二混频开关、第三混频开关、第四混频开关、第五混频开关、第六混频开关、第七混频开关、以及第八混频开关)均包括串联的两个晶体管，无源过滤电路300耦合于串联的所述两个晶体管之间。在集成电路100应用于无线接收机10时，可以利用无源过滤电路300，使本申请的第一无源混频器110(也可以是第一无源混频器和第二无源混频器)构成窄道滤波混频器，滤除信号从无线发射机发送到无线接收机10过程中的泄漏信号。
具体的，如图24所示，以双平衡的第一无源混频器110为例，无源过滤电路300包括第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8、第一电容C1和第二电容C2。第一电阻R1和第二电阻R2串联于第一混频开关111的两个晶体管之间，第三电阻R3和第四电阻R4串联于第四混频开关114的两个晶体管之间，第五电阻R5和第六电阻R6串联于第二混频开关112的两个晶体管之间，第七电阻R7和第八电阻R8串联于第三混频开关113的两个晶体管之间。其中，第一电阻R1的第二端和第二电阻R2的第一端耦合于节点a+，第三电阻R3和第四电阻R4耦合于节点a-，第五电阻R5的第二端和第六电阻R6的第一端耦合于节点b+，第七电阻R7和第八电阻R8耦合于节点b-；第一电容C1耦合于节点a+与节点a-之间，第二电容C2，耦合于节点b+与节点b-之间。在集成电路100应用于无线接收机10时，输入至集成电路100的信号穿过由电阻器-电容器(上述第一电阻～第八电阻、第一电容和第二电容)形成的嵌入式无源滤波区段，以通过低通滤波来减少接收的信号泄漏。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出 很多形式，均属于本申请的保护之内。

Claims (16)

  1. 一种集成电路，其特征在于，包括输入节点、第一无源混频器、第一放大器、第一滤波电容和第二滤波电容；
    所述输入节点用于接收射频信号，并将所述射频信号输入至第一支路和第二支路，所述第一支路和所述第二支路耦合于所述输入节点与所述第一放大器之间；
    所述第一无源混频器包括第一混频开关和第二混频开关，所述第一支路包括串联的所述第一滤波电容和所述第一混频开关，所述第一滤波电容耦合于所述输入节点与所述第一混频开关之间；所述第二支路包括串联的所述第二滤波电容和所述第二混频开关，所述第二滤波电容耦合于所述输入节点与所述第二混频开关之间；
    所述第一无源混频器将所述射频信号与本振信号进行混频，以向所述第一放大器输入第一模拟信号。
  2. 根据权利要求1所述的集成电路，其特征在于，所述第一混频开关包括第一晶体管，所述第二混频开关包括第二晶体管；所述集成电路还包括第一本振信号输入端和第二本振信号输入端；
    所述第一晶体管的栅极耦合至所述第一本振信号输入端、第一极耦合至所述输入节点、第二极耦合至所述第一放大器的第一放大输入端；
    所述第二晶体管的栅极耦合至所述第二本振信号输入端、第一极耦合至所述输入节点、第二极耦合至所述第一放大器的第二放大输入端；
    其中，所述第一晶体管从所述第一本振信号输入端接收第一本振信号，所述第二晶体管从所述第二本振信号输入端接收所述第二本振信号，所述第一本振信号与所述第二本振信号互为高低电平。
  3. 根据权利要求2所述的集成电路，其特征在于，所述第一无源混频器还包括第三混频开关和第四混频开关，所述集成电路还包括第三滤波电容和第四滤波电容；
    所述输入节点包括第一差分输入节点和第二差分输入节点，所述第一支路和所述第二支路与所述第一差分输入节点耦合；所述第二差分输入节点用于将所述射频信号输入至第三支路和第四支路，所述第三支路和所述第四支路耦合于所述第二差分输入节点与所述第一放大器之间；
    所述第三支路包括串联的所述第三滤波电容和所述第三混频开关，所述第三滤波电容耦合于所述第二差分输入节点与所述第三混频开关之间；所述第四支路包括串联的所述第四滤波电容和所述第四混频开关，所述第四滤波电容耦合于所述第二差分输入节点 与所述第四混频开关之间。
  4. 根据权利要求3所述的集成电路，其特征在于，所述第三混频开关包括第三晶体管，所述第四混频开关包括第四晶体管；
    所述第三晶体管的栅极耦合至所述第二本振信号输入端、第一极耦合至所述第二差分输入节点、第二极耦合至所述第一放大输入端；
    所述第四晶体管的栅极耦合至所述第一本振信号输入端、第一极耦合至所述第二差分输入节点、第二极耦合至所述第二放大输入端。
  5. 根据权利要求2-4任一项所述的集成电路，其特征在于，所述第一放大器的共模输入电压用于提供所述第一无源混频器中晶体管的直流偏置。
  6. 根据权利要求1-4任一项所述的集成电路，其特征在于，所述输入节点与低噪声放大器耦合，用于接收所述低噪声放大器输出的射频信号。
  7. 根据权利要求2-4任一项所述的集成电路，其特征在于，所述集成电路还包括第五滤波电容和第六滤波电容；所述第一放大器还包括第一放大输出端和第二放大输出端；所述第五滤波电容通过反馈放大方式耦合于所述第一放大输入端与所述第一放大输出端之间，所述第六滤波电容通过反馈放大方式耦合于所述第二放大输入端与所述第二放大输出端之间。
  8. 根据权利要求1-7任一项所述的集成电路，其特征在于，所述集成电路还包括第二无源混频器、第二放大器、第七滤波电容和第八滤波电容；
    所述输入节点还用于将所述射频信号输入至第五支路和第六支路，所述第五支路和所述第六支路耦合于所述输入节点与所述第二放大器之间；
    所述第二无源混频器包括第五混频开关和第六混频开关，所述第五支路包括串联的所述第七滤波电容和所述第五混频开关，所述第七滤波电容耦合于所述输入节点与所述第五混频开关之间；所述第六支路包括串联的所述第八滤波电容和所述第六混频开关，所述第八滤波电容耦合于所述输入节点与所述第六混频开关之间；
    所述第二无源混频器将所述射频信号与本振信号进行混频，以向所述第二放大器输入第二模拟信号；
    其中，所述第二模拟信号与所述第一模拟信号正交。
  9. 根据权利要求8所述的集成电路，其特征在于，所述第五混频开关包括第五晶体管，所述第六混频开关包括第六晶体管；
    所述第五晶体管的栅极耦合至所述第三本振信号输入端、第一极耦合至所述输入节点、第二极耦合至所述第二放大器的第三放大输入端；
    所述第六晶体管的栅极耦合至所述第四本振信号输入端、第一极耦合至所述输入节点、第二极耦合至所述第二放大器的第四放大输入端；
    其中，所述第五晶体管从所述第三本振信号输入端接收第三本振信号，所述第六晶体管从所述第四本振信号输入端接收所述第四本振信号，所述第三本振信号与所述第四本振信号互为高低电平。
  10. 根据权利要求9所述的集成电路，其特征在于，所述第二无源混频器还包括第七混频开关和第八混频开关，所述集成电路还包括第九滤波电容和第十滤波电容；
    在所述输入节点包括第一差分输入节点和第二差分输入节点的情况下，所述第五支路和所述第六支路与第一差分输入节点耦合；所述第二差分输入节点还用于将所述射频信号输入至第七支路和第八支路，所述第七支路和所述第八支路耦合于所述第二差分输入节点与所述第二放大器之间；
    所述第七支路包括串联的所述第九滤波电容和所述第七混频开关，所述第九滤波电容耦合于所述第二差分输入节点与所述第七混频开关之间；所述第八支路包括串联的所述第十滤波电容和所述第八混频开关，所述第十滤波电容耦合于所述第二差分输入节点与所述第八混频开关之间。
  11. 根据权利要求10所述的集成电路，其特征在于，所述第七混频开关包括第七晶体管，所述第八混频开关包括第八晶体管；
    所述第七晶体管的栅极耦合至所述第四本振信号输入端、第一极耦合至所述第二差分输入节点、第二极耦合至所述第三放大输入端；
    所述第八晶体管的栅极耦合至所述第三本振信号输入端、第一极耦合至所述第二差分输入节点、第二极耦合至所述第四放大输入端。
  12. 根据权利要求1-11任一项所述的集成电路，其特征在于，所述集成电路还包括无源过滤电路；
    所述第一混频开关和所述第二混频开关均包括串联的两个晶体管，所述无源过滤电路耦合于所述两个晶体管之间。
  13. 根据权利要求1-12任一项所述的集成电路，其特征在于，所述第一滤波电容和所述第二滤波电容包括MOM电容或MIM电容。
  14. 根据权利要求8-13任一项所述的集成电路，其特征在于，所述第一无源混频器和所述第二无源混频器为电流型无源混频器或电压型无源混频器。
  15. 一种无线接收机，其特征在于，包括权利要求1-14任一项所述的集成电路；
    所述集成电路中第一无源混频器的第一混频开关和第二混频开关用于对射频信号和本振信号进行下混频。
  16. 一种终端，其特征在于，包括天线和权利要求15所述的无线接收机，所述天线用于提供低噪声放大器需要的信号。
PCT/CN2021/101346 2021-06-21 2021-06-21 集成电路、无线接收机和终端 WO2022266818A1 (zh)

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