WO2022266792A1 - 斜坡发生器、图像传感器和产生斜坡电压的方法 - Google Patents

斜坡发生器、图像传感器和产生斜坡电压的方法 Download PDF

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Publication number
WO2022266792A1
WO2022266792A1 PCT/CN2021/101215 CN2021101215W WO2022266792A1 WO 2022266792 A1 WO2022266792 A1 WO 2022266792A1 CN 2021101215 W CN2021101215 W CN 2021101215W WO 2022266792 A1 WO2022266792 A1 WO 2022266792A1
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Prior art keywords
reference voltage
circuit
signal
control terminal
output switch
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PCT/CN2021/101215
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English (en)
French (fr)
Inventor
范铨奇
林永福
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迪克创新科技有限公司
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Priority to PCT/CN2021/101215 priority Critical patent/WO2022266792A1/zh
Priority to CN202180004853.0A priority patent/CN115715452A/zh
Publication of WO2022266792A1 publication Critical patent/WO2022266792A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Definitions

  • the present application relates to a slope generator, in particular to a slope generator adopting a digital-to-analog conversion structure, a related image sensor and a method for generating a slope voltage.
  • a complementary metal oxide semiconductor image sensor can adopt a column parallel analog-to-digital converter (column parallel ADC) structure to convert the analog signal output by the pixel into a digital signal.
  • the column-parallel analog-to-digital conversion structure includes a ramp generator that can be used to determine the resolution of the column-parallel analog-to-digital conversion structure.
  • the ramp generator is usually implemented using a current steering digital-to-analog converter (current steering DAC).
  • current steering DAC current steering digital-to-analog converter
  • One of the purposes of the present application is to disclose a ramp generator, a related image sensor and a method for generating a ramp voltage, so as to solve the above-mentioned problems in the prior art.
  • the ramp generator includes a current generating circuit, a plurality of circuit branches, a first control circuit and a first electric energy storage unit.
  • the current generating circuit is used to generate load current.
  • the multiple circuit branches are coupled to the current generating circuit for generating a slope voltage according to the load current.
  • a circuit branch of the plurality of circuit branches includes a resistor and an output switch connected in series with each other between the current generating circuit and a reference terminal.
  • the output switch is used for selectively allowing at least a part of the load current to flow through the resistor to generate the ramp voltage.
  • the first control circuit is used for selectively coupling at least a reference voltage to the control terminal of the output switch to generate a first control signal at the control terminal of the output switch.
  • the first electric energy storage unit is coupled to the first control circuit and the control terminal of the output switch, and is used to store the electric energy of the first control signal to generate a first storage result, and when the reference voltage is not When coupled to the control terminal of the output switch, the output switch is selectively turned on according to the first stored result.
  • the image sensing circuit includes a plurality of pixels, a comparator, the aforementioned ramp generator and a counter.
  • the comparator is coupled to the plurality of pixels for comparing the output voltage of one of the plurality of pixels with the ramp voltage to generate a comparison result.
  • the ramp generator is coupled to the comparator for generating the ramp voltage.
  • the reference voltage is coupled to the control terminal of the output switch when the comparator stops comparing the output voltage with the ramp voltage, and when the comparator compares the output voltage with the ramp voltage When the voltage is compared, it is not coupled to the control terminal of the output switch.
  • the counter is coupled to the comparator for generating a digital signal corresponding to the output voltage according to the comparison result.
  • Certain embodiments of the present application disclose a method for generating a ramp voltage.
  • the method includes: selectively outputting at least a part of N binary-weighted currents according to an N-bit digital code as a load current; When the control terminal of the circuit branch is used, the electric energy of the first control signal on the control terminal of the circuit branch is stored to generate the first storage result; when the reference voltage is not coupled to the control terminal of the circuit branch, according to The first stored result selectively turns on the circuit branches; and at least one turned-on circuit branch among the M circuit branches receives the load current to generate a ramp voltage.
  • the ramp voltage generation scheme disclosed in this application can store the power of the power supply voltage, and turn on the circuit branch according to the stored power when the power supply voltage is not coupled to the circuit branch, so as to realize the ramp with good power supply voltage rejection ratio generator.
  • the slope voltage generating scheme disclosed in this application can be applied to a digital-to-analog converter of an image sensor to improve the detection accuracy of pixel output.
  • FIG. 1 is a schematic diagram of an embodiment of an image sensing circuit of the present application.
  • FIG. 2 is a schematic diagram of an embodiment of the ramp generator shown in FIG. 1 .
  • FIG. 3 is a schematic diagram of an embodiment of at least a portion of the ramp generator shown in FIG. 2 .
  • FIG. 4 is a schematic diagram of an embodiment of signal timing involved in the ramp generator shown in FIG. 3 .
  • FIG. 5 is a schematic diagram of an embodiment of signal timing involved in the ramp generator shown in FIG. 1 .
  • FIG. 6 is a flow chart of an embodiment of the method for generating a ramp voltage of the present application.
  • the gain of the current-driven digital-to-analog converter can also be adjusted by adjusting the resistance of the current path.
  • the current path of the current-driven DAC may include multiple circuit branches. By selectively conducting at least a portion of the plurality of circuit branches, the resistance of the current path can be varied. However, when a certain circuit branch is turned on, the supply voltage will be coupled to the output terminal of the current-driven digital-to-analog converter through the parasitic capacitance of the switch of the circuit branch, resulting in a power supply rejection ratio (PSRR) ) becomes worse.
  • PSRR power supply rejection ratio
  • the ramp voltage generation scheme disclosed in this application can store the power of the power supply voltage, and turn on the circuit branch according to the stored power when the power supply voltage is not coupled to the circuit branch, so as to realize the ramp with good power supply voltage rejection ratio generator.
  • the slope voltage generating scheme disclosed in this application can be applied to a digital-to-analog converter of an image sensor to improve the detection accuracy of pixel output. Further explanation follows.
  • FIG. 1 is a schematic diagram of an embodiment of an image sensing circuit of the present application.
  • the image sensing circuit 100 may include (but not limited to) a plurality of pixels 102.1-102.K (K is a positive integer greater than 1), an analog-to-digital conversion circuit (labeled as "ADC") 110, a ramp A generator 120 , an image signal processor (image signal processor, ISP) 130 and a controller 140 .
  • the image sensing circuit 100 may adopt a column-parallel analog-to-digital conversion structure to perform analog-to-digital conversion operations on pixel outputs.
  • a plurality of pixels 102.1-102.K can be located in the same pixel column, and the analog-to-digital conversion circuit 110 can be used to process the pixel output output from the pixel column.
  • the present application is not limited thereto.
  • a plurality of pixel columns included in the image sensor circuit 100 can share the analog-to-digital conversion circuit 110 through a switch circuit.
  • Related alternative implementations are within the scope of this application.
  • a plurality of pixels 102.1-102.K may adopt the same pixel structure.
  • the pixel 102.1 may adopt (but the application is not limited thereto) a 4T pixel structure, which includes a photodiode PD, a transfer transistor MT, a reset transistor MR, an amplifying transistor MF, and a selection transistor MS.
  • the transfer transistor MT is used for selectively coupling the photodiode PD to the floating diffusion node (floating diffusion node) FN according to the transfer signal Tx.
  • the reset transistor MR is used to selectively reset the floating diffusion node FN according to the reset signal Rst.
  • the amplifying transistor MF is used to amplify the pixel signal FS on the floating diffusion node FN to generate a pixel output (ie output voltage Vpout).
  • the selection transistor MS is used to output the output voltage Vpout from the output terminal TP according to the selection signal Rsel.
  • the analog-to-digital conversion circuit 110 is used for converting the output voltage Vpout into a digital signal Vd according to the ramp voltage Vramp.
  • the analog-to-digital conversion circuit 110 includes (but not limited to) a current source 112 , a comparator 114 and a counter 116 .
  • the comparator 114 is coupled to the plurality of pixels 102.1-102.K for comparing the output voltage Vpout of the pixel 102.1 with the ramp voltage Vramp to generate a comparison result CP.
  • the counter 116 is coupled to the comparator 114 for generating a digital signal Vd corresponding to the output voltage Vpout according to the comparison result CP.
  • the ramp generator 120 is coupled to the comparator 114 for generating the ramp voltage Vramp.
  • the ramp generator 120 can generate the ramp voltage Vramp according to the digital signal DIN, wherein the level of the ramp voltage Vramp can be changed according to the signal value of the digital signal DIN.
  • the digital signal DIN can be implemented by an N-bit digital code, where N is a positive integer greater than 1.
  • N is a positive integer greater than 1.
  • the ramp generator 120 can be used as a digital-to-analog converter.
  • the ramp generator 120 can read a plurality of input signals S 0 -S (M ⁇ 1) (M is a positive integer greater than 1) by sampling the signal SH, and has a good power supply voltage rejection ratio. Relevant descriptions will be discussed later.
  • the image signal processor 130 is coupled to the counter 116 for performing related image processing according to the digital signal Vd.
  • the controller 140 is used to control the operations of the plurality of pixels 102 . 1 - 102 .K, the ADC 110 , the ramp generator 120 and the image signal processor 130 .
  • the transmission signal Tx, the reset signal Rst, the selection signal Rsel, the digital signal DIN and the sampling signal SH can all be provided by the controller 140 .
  • FIG. 2 is a schematic diagram of an embodiment of the ramp generator 120 shown in FIG. 1 .
  • the ramp generator 120 can be implemented by (but the application is not limited to) a current-driven digital-to-analog converter, and can include a current generating circuit 222, M circuit branches 224.1-224.M, and a control unit 226.
  • the current generating circuit 222 is used for generating the load current IL according to the digital signal DIN.
  • the current generating circuit 222 may include N current sources 222.1-222.N and N current switches SWI 1 -SWIN .
  • N current switches SWI 0 -SWI (N-1) are controlled by N bits B 0 -B (N-1) included in the digital signal DIN, wherein each current switch is used to selectively The binary weighted current is output to the output terminal TL.
  • the M circuit branches 224.1-224.M are coupled to the current generating circuit 222 for generating the ramp voltage Vramp according to the load current IL.
  • Each of the M circuit branches 224.1-224.M is selectively conductive to change the load resistance RL seen from the output TL.
  • each of the M circuit branches 224.1-224.M may include resistors connected in series between the current generating circuit 222 and the reference terminal TR (a plurality of resistors R 0 -R (M-1) ) and an output switch (one of a plurality of output switches SWR 0 -SWR (M-1) ).
  • the output switch is used for selectively allowing at least a part of the load current IL to flow through the resistor to generate the ramp voltage Vramp.
  • a plurality of output switches SWR 0 -SWR (M-1) can be controlled by a plurality of control signals SC 0 -SC (M-1) .
  • the output switch SWR 0 can selectively allow at least a portion of the load current IL to flow through the resistor R 0 according to the control signal SC 0 to generate the ramp voltage Vramp.
  • the control unit 226 is used to generate multiple control signals SC 0 -SC (M-1) according to the sampling signal SH and multiple input signals S 0 -S (M -1), wherein the multiple input signals S 0 -S (M- 1) can be provided by the controller 140 shown in FIG. 1 .
  • the control unit 226 can selectively sample a plurality of input signals S 0 -S (M-1) according to the sampling signal SH to generate a plurality of control signals SC 0 -SC (M-1) .
  • the control unit 226 can generate multiple control signals SC 0 -SC (M-1) according to multiple input signals S 0 -S (M-1) to control multiple output switches SWR 0 - Operation of SWR (M-1) .
  • the control unit 226 can keep the plurality of control signals SC 0 -SC (M-1) independent of the plurality of input signals S 0 -S ( M-1) effects.
  • the control signal SC 0 as an example, when the sampling signal SH is at the first logic level, the control unit 226 can generate the control signal SC 0 according to the input signal S 0 to control the output switch SWR 0 .
  • the control unit 226 can keep the control signal SC 0 from being affected by the input signal S 0 .
  • FIG. 3 is a schematic diagram of an embodiment of at least a portion of the ramp generator 120 shown in FIG. 2 .
  • FIG. 3 only shows the control structures associated with the plurality of circuit branches 224.1 and 224.2 shown in FIG. 2 .
  • the control structure of at least one other circuit branch may adopt the control structure shown in FIG. 3 without departing from the scope of the present application.
  • the control unit 226 may include (but not limited to) a first control circuit 326.1, a first energy storage unit C 0 , a second control circuit 326.2, and a first energy storage unit C 1 .
  • the first control circuit 326.1 is used for at least selectively coupling the reference voltage VR1 to the control terminal of the output switch SWR 0 to generate the control signal SC 0 at the control terminal of the output switch SWR 0 .
  • the first energy storage unit C 0 is coupled to the control terminal of the first control circuit 326.1 and the output switch SWR 0 for storing the electric energy of the control signal SC 0 to generate the first stored result SR 0 , and is not coupled to the reference voltage VR1 When at the control terminal of the output switch SWR 0 , the output switch SWR 0 is selectively turned on according to the first stored result SR 0 .
  • the first energy storage unit C0 can store power from the power supply voltage, and can output a switch when the power supply voltage is not coupled to SWR 0 , the output switch SWR 0 is turned on according to the stored electrical energy. Therefore, when the output switch SWR 0 is turned on, the noise of the power supply voltage will not (or hardly) be coupled to the output terminal TL through the parasitic capacitance C P0 . Since the path of the noise of the power supply voltage coupled to the output terminal TL through the parasitic capacitor C P0 can be blocked, the ramp generator 120 can have a good power supply voltage rejection ratio.
  • the second control circuit 326.2 is used for at least selectively coupling the reference voltage VR1 to the control terminal of the output switch SWR 1 to generate the control signal SC 1 at the control terminal of the output switch SWR 1 .
  • the second energy storage unit C 1 is coupled to the control terminal of the second control circuit 326.2 and the output switch SWR 1 for storing the electric energy of the control signal SC 1 to generate the second stored result SR 1 , and is not coupled to the reference voltage VR1
  • the output switch SWR 1 is selectively turned on according to the second stored result SR 1 .
  • the output switch SWR 0 and the output switch SWR 1 can be implemented by transistors, and the first energy storage unit C 0 and the second energy storage unit C 1 can be implemented by capacitors.
  • the present application is not limited thereto.
  • the first electric energy storage unit C 0 and/or the second electric energy storage unit C 1 may be implemented with other circuit components having electric energy storage function without departing from the scope of the present application.
  • the first control circuit 326.1 can selectively couple the reference voltage VR1 to the control terminal of the output switch SWR 0 according to the sampling signal SH and the input signal S 0 .
  • the sampling signal SH is at the first logic level
  • the first control circuit 326.1 can selectively couple the reference voltage VR1 to the control terminal of the output switch SWR 0 according to the input signal S 0 to generate the control signal SC 0 .
  • the sampling signal SH is at the second logic level
  • the first control circuit 326.1 can make the reference voltage VR1 not coupled to the control terminal of the output switch SWR 0 .
  • the output switch SWR 0 can be turned on when the sampling signal SH is at the second logic level, so that the influence of the noise of the reference voltage VR1 to the ramp voltage Vramp can be greatly reduced.
  • the second control circuit 326.2 can selectively couple the reference voltage VR1 to the control terminal of the output switch SWR1 according to the shared sampling signal SH and the input signal S1.
  • the sampling signal SH is at the first logic level
  • the second control circuit 326.2 can selectively couple the reference voltage VR1 to the control terminal of the output switch SWR 1 according to the input signal S 1 to generate the control signal SC 1 .
  • the second control circuit 326.2 can make the reference voltage VR1 not coupled to the control terminal of the output switch SWR1 .
  • the first control circuit 326.1 can also selectively couple the reference voltage VR2 to the control terminal of the output switch SWR 0 to generate the control signal SC 0 at the control terminal of the output switch SWR 0 .
  • the reference voltage VR1 and the reference voltage VR2 When one of the reference voltage VR1 and the reference voltage VR2 is coupled to the control terminal of the output switch SWR 0 , the other of the reference voltage VR1 and the reference voltage VR2 is not coupled to the control terminal of the output switch SWR 0 .
  • the first control circuit 326.1 can selectively couple the reference voltage VR1 to the control terminal of the output switch SWR 0 , and can also selectively couple the reference voltage VR2 to the control terminal of the output switch SWR 0 , wherein the control The signal SC 0 can come from the reference voltage VR1 or the reference voltage VR2.
  • the first control circuit 326.1 can selectively couple the reference voltage VR1 or the reference voltage VR2 to the control terminal of the output switch SWR 0 according to the sampling signal SH and the input signal S 0 .
  • the sampling signal SH is at the first logic level
  • the first control circuit 326.1 couples one of the reference voltage VR1 and the reference voltage VR2 to the control terminal of the output switch SWR 0 according to the input signal S 0 .
  • the sampling signal SH is at the second logic level
  • the first control circuit 326.1 makes neither the reference voltage VR1 nor the reference voltage VR2 coupled to the control terminal of the output switch SWR0 .
  • one of the reference voltage VR1 and the reference voltage VR2 may be a power supply voltage
  • the other of the reference voltage VR1 and the reference voltage VR2 may be a ground voltage.
  • the present application is not limited thereto.
  • the second control circuit 326.2 can selectively couple the reference voltage VR2 to the control terminal of the output switch SWR 1 to generate the control signal SC 1 at the control terminal of the output switch SWR 1 .
  • the other of the reference voltage VR1 and the reference voltage VR2 is not coupled to the control terminal of the output switch SWR1 .
  • the first control circuit 326.1 and the second control circuit 326.2 shown in FIG. 3 adopt an exemplary circuit structure to illustrate the slope voltage generation scheme disclosed in this application.
  • this is for illustration purposes.
  • the control circuit structure can store the electric energy of the reference voltage in the electric energy storage unit, and turn on the circuit branch according to the stored electric energy to reduce the influence of the noise of the reference voltage on the ramp voltage, all belong to the scope of the present application.
  • the first control circuit 326.1 may include a signal generating circuit 328.1, a first input switch P 0 and a second input switch N 0 .
  • the signal generating circuit 326.1 is used for generating the first auxiliary signal SCP 0 and the second auxiliary signal SCN 0 according to the sampling signal SH and the input signal S 0 .
  • the first input switch P 0 is coupled to the signal generating circuit 328.1 for selectively coupling the reference voltage VR1 to the control terminal of the output switch SWR 0 according to the first auxiliary signal SCP 0 .
  • the second input switch N 0 is coupled to the signal generating circuit 328.1 for selectively coupling the reference voltage VR2 to the control terminal of the output switch SWR 0 according to the second auxiliary signal SCN 0 .
  • the signal generating circuit 328.1 can sample the input signal S 0 , turn on one of the first input switch P 0 and the second input switch N 0 , and the first input switch P 0 is disconnected from the other one of the second input switches N 0 .
  • the signal generating circuit 328.1 may not sample the input signal S 0 , so that both the first input switch P 0 and the second input switch N 0 are turned off.
  • the signal generating circuit 328.1 may include a NAND gate A0, an inverter B0, and a NOR gate C0.
  • the NAND gate A0 is used for generating the first auxiliary signal SCP 0 according to the sampling signal SH and the input signal S 0 .
  • the inverter B0 is used for receiving the sampling signal SH to generate an inverted signal Sb0.
  • the NOR gate C0 is used for generating the second auxiliary signal SCN 0 according to the inverted signal Sb0 and the input signal S 0 .
  • the second control circuit 326.2 may include a signal generating circuit 328.2, a first input switch P 1 and a second input switch N 1 .
  • the signal generating circuit 328.2 may include a NAND gate A1, an inverter B1, and a NOR gate C1.
  • the NAND gate A1 can generate the first auxiliary signal SCP 1 .
  • the NOR gate C0 can generate the second auxiliary signal SCN 1 .
  • FIG. 4 is a schematic diagram of an embodiment of signal timing involved in the ramp generator 120 shown in FIG. 3 .
  • the sampling signal SH is at a high logic level, and the ramp generator 120 may be in the sampling mode M_S.
  • the signal generating circuit 328.1 can generate the first auxiliary signal SCP 0 and the second auxiliary signal SCN 0 according to the input signal S 0 .
  • the first input switch P 0 can be turned on according to the first auxiliary signal SCP 0 , so that the reference voltage VR1 is coupled to the output switch SWR 0 to generate the control signal SC 0 with a high logic level.
  • the first power storage unit C 0 may store the power of the control signal SC 0 to generate a first storage result SR 0 .
  • the second input switch N 0 may be turned off according to the second auxiliary signal SCN 0 .
  • the signal generating circuit 328.2 can generate the first auxiliary signal SCP 1 and the second auxiliary signal SCN 1 according to the input signal S 1 .
  • the second energy storage unit C 1 may store the energy of the control signal SC 1 at a high logic level to generate a second storage result SR 1 .
  • the sampling signal SH is switched to a low logic level, and the ramp generator 120 can be in the hold mode M_H. Both the first input switch P 0 and the second input switch N 0 are turned off. At time point t2, both the input signal S0 and the input signal S1 switch to a low logic level. Since the ramp generator 120 is in the hold mode M_H, the signal levels of the first auxiliary signal SCP 0 and the second auxiliary signal SCN 0 remain unchanged, so that the first input switch P 0 and the second input switch N 0 are still at Disconnected state. It should be noted that since the first input switch P 0 and the second input switch N 0 can be maintained in the off state in the hold mode M_H, when the comparator 114 shown in FIG.
  • the ramp generator 120 uses the ramp voltage Vramp to perform the comparison operation When , the noise of the reference voltage VR1/VR2 will not (or hardly) be coupled to the output terminal TL through the parasitic capacitance C P0 . That is, the ramp generator 120 can have a good supply voltage rejection ratio.
  • the sampling signal SH switches to a low logic level, and the ramp generator 120 is in the sampling mode M_S.
  • the signal generating circuit 328.1 can generate the first auxiliary signal SCP 0 and the second auxiliary signal SCN 0 according to the input signal S 0 . Therefore, the second auxiliary signal SCN 0 may switch to a high logic level.
  • the first input switch P 0 may be turned off according to the first auxiliary signal SCP 0 .
  • the second input switch N 0 can be turned on according to the second auxiliary signal SCN 0 , so that the reference voltage VR2 is coupled to the output switch SWR 0 to generate the control signal SC 0 at a low logic level.
  • control signal SC 1 can be switched to a low logic level.
  • the sampling signal SH is switched to a low logic level, and the ramp generator 120 can be in the hold mode M_H. Both the first input switch P 0 and the second input switch N 0 are turned off.
  • the ramp generator disclosed in this application can operate in a sampling mode or a holding mode. Since the ramp voltage can be provided to the comparator of the ADC in the hold mode to reduce the noise interference of the power supply voltage, the ADC can obtain more accurate conversion results.
  • FIG. 5 is a schematic diagram of an embodiment of signal timing involved in the ramp generator 120 shown in FIG. 1 .
  • the ramp generator 120 can adopt the circuit structure shown in FIG. 2 or FIG. 3 and operate in the sampling mode or the holding mode.
  • the selection transistor MS can be turned on according to the selection signal Rsel to enable the pixel 102.1.
  • the reset transistor MR can be turned on according to the reset signal Rst to reset the floating diffusion node FN.
  • the analog-to-digital converter 110 can convert the reset level of the output voltage Vpout.
  • the transfer transistor MT can be turned on according to the transfer signal Tx to transfer the conversion result of the photodiode PD to the floating diffusion node FN.
  • the analog-to-digital converter 110 can convert the signal level of the output voltage Vpout.
  • the reference voltage VR1 can be coupled to the control terminal of the output switch SWR 0 /SWR 1 when the comparator 114 stops comparing the output voltage Vpout with the ramp voltage Vramp.
  • the ramp generator 120 can couple the reference voltage VR1 to the control terminal of the output switch SWR 0 to store the first electric energy Cell C0 may store electrical energy from reference voltage VR1.
  • the comparator 114 compares the output voltage Vpout with the ramp voltage Vramp, it is not coupled to the control terminal of the output switch SWR 0 .
  • the ramp generator 120 can make the reference voltage VR1 not coupled to the control terminal of the output switch SWR 0 , so that the output switch SWR 0 means that SR 0 is turned on according to the first storage result, so as to reduce the interference of the noise of the reference voltage VR1 on the ramp voltage Vramp.
  • the reference voltage VR1 can be coupled to the control terminal of the output switch SWR 0 before the pixel 102.1 is enabled.
  • the sampling signal SH can be at a high logic level during the time interval TI1 to couple the reference voltage VR1 to the control terminal of the output switch SWR0 .
  • the reference voltage VR1 may be coupled to the control terminal of the output switch SWR 0 after the pixel 102.1 is enabled.
  • the sampling signal SH can be at a high logic level during the time interval TI2 to couple the reference voltage VR1 to the control terminal of the output switch SWR 0 .
  • the reference voltage VR1 may be coupled to the control terminal of the output switch SWR 0 after the pixel 102.1 is enabled and before the comparator 114 compares the output voltage Vpout with the ramp voltage Vramp.
  • the sampling signal SH can be at a high logic level during the time interval TI3 to couple the reference voltage VR1 to the control terminal of the output switch SWR 0 . That is to say, the controller 140 may generate the sampling signal SH at a high logic level during one of the time interval TI1 , the time interval TI2 and the time interval TI3 .
  • FIG. 6 is a flow chart of an embodiment of the method for generating a ramp voltage of the present application. If the obtained results are substantially the same, the steps do not have to be performed in the order shown in FIG. 6 .
  • the method 600 shown in FIG. 3 may further include other steps.
  • the ramp voltage generating scheme disclosed in the present application can adopt alternative implementations based on the method 600 without departing from the spirit and scope of the present application.
  • the method 600 shown in FIG. 6 is described below with the ramp generator 120 shown in FIGS. 2 and 3 .
  • the present application is not limited thereto. It is also feasible to apply the method 600 to the ramp generator 120 shown in FIG. 1 .
  • step 602 at least a part of the N binary-weighted currents is selectively output as the load current according to the N-bit digital code.
  • the current generating circuit 222 can selectively output at least a part of the N binary weighted currents I 0 -I (N ⁇ 1) as the load current IL according to the digital signal DIN.
  • step 604 for each of the M circuit branches coupled in parallel to each other, storing the value of the first control signal on the control terminal of the circuit branch when the reference voltage is coupled to the control terminal of the circuit branch electrical energy to generate the first stored result.
  • the first energy storage unit C0 can store the energy of the control signal SC0 to generate the first storage result SR 0 .
  • the first energy storage unit C 0 can store the electrical energy of the control signal SC 0 to generate the first storage result SR0 .
  • step 606 for the circuit branch, selectively turn on the circuit branch according to the first stored result when the reference voltage is not coupled to the control terminal of the circuit branch.
  • the first energy storage unit C 0 can selectively turn on the circuit branch according to the first storage result SR 0 224.1.
  • the reference voltage VR2 is not coupled to the control terminal of the circuit branch 224.1 (that is, the control terminal of the output switch SWR 0 )
  • the first energy storage unit C 0 can selectively turn on the circuit according to the first storage result SR 0 Branch 224.1.
  • the circuit branch 224.1 can be turned on according to the first storage result SR 0 corresponding to the reference voltage VR1, and according to the first storage result corresponding to the reference voltage VR2 As a result SR 0 is disconnected.
  • step 608 use at least one of the M circuit branches that is turned on to receive the load current to generate a ramp voltage.
  • the switched-on circuit branches among the M circuit branches 224.1-224.1 can be used to receive the load current IL to generate the ramp voltage Vramp.
  • the reference voltage can be selectively coupled to the control terminal of the circuit branch according to the sampling signal and the first input signal.
  • the reference voltage VR1 can be selectively coupled to the control terminal of the circuit branch 224.1 according to the sampling signal SH and the input signal S0 .
  • the sampling signal SH is at the first logic level
  • the reference voltage VR1 can be selectively coupled to the control terminal of the circuit branch 224.1 according to the input signal S0 .
  • the sampling signal SH is at the second logic level
  • the reference voltage VR1 is not coupled to the control terminal of the circuit branch 224.1.
  • another reference voltage can be selectively coupled to the control terminal of the circuit branch.
  • the reference voltage VR2 can be selectively coupled to the control terminal of the circuit branch 224.1.
  • the other of the reference voltage VR1 and the reference voltage VR2 is not coupled to the control terminal of the circuit branch 224.1.
  • one of the reference voltage VR1 and the reference voltage VR2 may be a power supply voltage
  • the other of the reference voltage VR1 and the reference voltage VR2 may be a ground voltage.
  • the reference voltage or the other reference voltage can be selectively coupled to the control terminal of the circuit branch according to the sampling signal and the first input signal.
  • the reference voltage VR1 or the reference voltage VR2 can be selectively coupled to the control terminal of the circuit branch 224.1 according to the sampling signal SH and the input signal S0 .
  • the sampling signal SH is at the first logic level
  • one of the reference voltage VR1 and the reference voltage VR2 can be coupled to the control terminal of the circuit branch 224.1 according to the input signal S0 ; when the sampling signal SH is at the second logic level, Neither the reference voltage VR1 nor the reference voltage VR2 is coupled to the control terminal of the circuit branch 224.1.

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Abstract

一种斜坡发生器（120）、图像传感电路和产生斜坡电压的方法。所述斜坡发生器（120）包括电流产生电路（222）、多个电路分支（224.1，224.2）、控制电路（326.1，326.2）和电能存储单元。所述电流产生电路（222）用以产生负载电流。所述多个电路分支（224.1，224.2）根据所述负载电流产生斜坡电压。所述多个电路分支（224.1，224.2）的一个电路分支（224.1，224.2）包括彼此串联的电阻与输出开关。所述输出开关选择性地允许所述负载电流的至少一部分流经所述电阻。所述控制电路（326.1，326.2）将参考电压选择性地耦接于所述输出开关的控制端，以在所述控制端产生控制信号。所述电能存储单元存储所述控制信号的电能，并且在所述参考电压未耦接于所述控制端时，根据所存储的电能选择性地导通所述输出开关。所述斜坡发生器（120）能够具有良好的电源电压抑制比。

Description

斜坡发生器、图像传感器和产生斜坡电压的方法 技术领域
本申请涉及斜坡发生器，尤其涉及一种采用数模转换结构的斜坡发生器，以及相关的图像传感器和产生斜坡电压的方法。
背景技术
互补式金属氧化物半导体图像传感器(CMOS image sensor,CIS)可采用列并行模数转换结构(column parallel analog-to-digital converter，column parallel ADC)，将像素输出的模拟信号转换为数字信号。列并行模数转换结构包括斜坡发生器，其可用于决定列并行模数转换结构的分辨率。斜坡发生器通常利用电流驱动型数模转换器(current steering digital-to-analog converter，current steering DAC)来实现。通过调整单位电流源的电流，可调整电流驱动型数模转换器的增益。然而，为了提高增益而降低单位电流源的电流，会造成电流失配以及非线性的数模转换。
发明内容
本申请的目的之一在于公开一种斜坡发生器，以及相关的图像传感器和产生斜坡电压的方法，来解决现有技术中的上述问题。
本申请的某些实施例公开了一种斜坡发生器。所述斜坡发生器包括电流产生电路、多个电路分支、第一控制电路和第一电能存储单元。所述电流产生电路用以产生负载电流。所述多个电路分支耦接于所述电流产生电路，用以根据所述负载电流产生斜坡电压。所 述多个电路分支中的一个电路分支包括彼此串联于所述电流产生电路与参考端之间的电阻与输出开关。所述输出开关用以选择性地允许所述负载电流的至少一部分流经所述电阻以产生所述斜坡电压。所述第一控制电路用以至少将参考电压选择性地耦接于所述输出开关的控制端，以在所述输出开关的控制端产生第一控制信号。所述第一电能存储单元耦接于所述第一控制电路与所述输出开关的控制端，用以存储所述第一控制信号的电能以产生第一存储结果，并且在所述参考电压未耦接于所述输出开关的控制端时，根据所述第一存储结果选择性地导通所述输出开关。
本申请的某些实施例公开了一种图像传感电路。所述图像传感电路包括多个像素、比较器、上述斜坡发生器和计数器。所述比较器耦接于所述多个像素，用以将所述多个像素中的一个像素的输出电压与斜坡电压作比较，以产生比较结果。所述斜坡发生器耦接于所述比较器，用以产生所述斜坡电压。所述参考电压是在所述比较器停止將所述输出电压与所述斜坡电压作比较时耦接于所述输出开关的控制端，并且在所述比较器将所述输出电压与所述斜坡电压作比较时未耦接于所述输出开关的控制端。所述计数器耦接于所述比较器，用以根据所述比较结果产生所述输出电压相应的数字信号。
本申请的某些实施例公开了一种产生斜坡电压的方法。所述方法包括：根据N位数字码选择性地输出N个二进制权电流的至少一部分，作为负载电流；针对彼此并联耦接M个电路分支的每一电路分支，于参考电压耦接于所述电路分支的控制端时，存储所述电路分支的控制端上的第一控制信号的电能，以产生第一存储结果；于所述参考电压未耦接于所述电路分支的控制端时，根据所述第一存储结果选择性地导通所述电路分支；以及利用M个电路分支中至少一导通的电路分支接收所述负载电流，以产生斜坡电压。
本申请所公开的斜坡电压产生方案可通过存储电源电压的电能，并且在电源电压未耦接于电路分支的情形下根据所存储的电能导通 电路分支，实现具有良好的电源电压抑制比的斜坡发生器。此外，本申请所公开的斜坡电压产生方案可应用于图像传感器的数模转换器，提升像素输出的检测精度。
附图说明
图1是本申请的图像传感电路的一实施例的示意图。
图2是图1所示的斜坡发生器的一实施方式的示意图。
图3是图2所示的斜坡发生器的至少一部分的一实施方式的示意图。
图4是图3所示的斜坡发生器所涉及的信号时序的一实施例的示意图。
图5是图1所示的斜坡发生器所涉及的信号时序的一实施例的示意图。
图6是本申请的产生斜坡电压的方法的一实施例的流程图。
具体实施方式
以下提供了用于实施本申请的不同特征的多种实施方式或示例。下文将描述元件与配置的具体例子以简化本申请。当然，这些叙述仅为示例，其本意并非用于限制本申请。此外，本申请可能会在多个实施例中重复使用元件符号和/或标号。此种重复使用是出于简洁与清楚的目的，本身不代表所讨论的不同实施例和/或配置之间的关系。再者，应可理解若文中描述一元件“连接(connected to)”或“耦接(coupled to)”到另一元件，所述元件可能是直接连接或耦接到所述另一元件，或通过其它元件间接地连接或耦接到所述另一元件。
除了调整单位电流源的电流，还可通过调整电流路径的电阻， 来调整电流驱动型数模转换器的增益。例如，电流驱动型数模转换器的电流路径可包括多个电路分支(circuit branch)。通过选择性地导通多个电路分支的至少一部分，可改变电流路径的电阻。然而，在某个电路分支导通时，电源电压会通过所述电路分支的开关的寄生电容耦合到电流驱动型数模转换器的的输出端，导致电源电压抑制比(power supply rejection ratio，PSRR)变差。
本申请所公开的斜坡电压产生方案可通过存储电源电压的电能，并且在电源电压未耦接于电路分支的情形下根据所存储的电能导通电路分支，实现具有良好的电源电压抑制比的斜坡发生器。此外，本申请所公开的斜坡电压产生方案可应用于图像传感器的数模转换器，提升像素输出的检测精度。进一步的说明如下。
图1是本申请的图像传感电路的一实施例的示意图。于此实施例中，图像传感电路100可包含(但不限于)多个像素102.1-102.K(K是大于1的正整数)、模数转换电路(标记为“ADC”)110、斜坡发生器120、图像信号处理器(image signal processor，ISP)130以及控制器140。图像传感电路100可采用列并行模数转换结构来对像素输出进行模数转换操作。举例来说，多个像素102.1-102.K可位于同一像素列，而模数转换电路110可用以处理所述像素列所输出的像素输出。然而，本申请并不以此为限。例如，图像传感电路100所包括的多个像素列可通过一开关电路共享模数转换电路110。相关的替代实施方式均属于本申请的范围。
多个像素102.1-102.K可采用相同的像素结构。以像素102.1为例，像素102.1可采用(但本申请不限于此)4T像素结构，其包括光电二极管PD、传输晶体管MT、复位晶体管MR、放大晶体管MF以及选择晶体管MS。传输晶体管MT用以根据传输信号Tx选择性地将光电二极管PD耦接于浮动扩散节点(floating diffusion node)FN。复位晶体管MR用以根据复位信号Rst选择性地复位浮动扩散节点FN。放大晶体管MF用以放大浮动扩散节点FN上的像素信号FS 以产生一像素输出(即输出电压Vpout)。选择晶体管MS用以根据选择信号Rsel将输出电压Vpout从输出端TP输出。
模数转换电路110用以根据斜坡电压Vramp将输出电压Vpout转换为数字信号Vd。于此实施例中，模数转换电路110包括(但不限于)电流源112、比较器114以及计数器116。比较器114耦接于多个像素102.1-102.K，用以将像素102.1的输出电压Vpout与斜坡电压Vramp作比较，以产生比较结果CP。计数器116耦接于比较器114，用以根据比较结果CP产生输出电压Vpout相应的数字信号Vd。
斜坡发生器120耦接于比较器114，用以产生斜坡电压Vramp。斜坡发生器120可根据数字信号DIN产生斜坡电压Vramp，其中斜坡电压Vramp的电平可根据数字信号DIN的信号值而改变。例如，数字信号DIN可由N位数字码来实施，其中N是大于1的正整数。在数字信号DIN的信号值递增的期间，斜坡电压Vramp的电平逐渐上升。在数字信号DIN的信号值递减的期间，斜坡电压Vramp的电平逐渐下降。也就是说，斜坡发生器120可作为数模转换器。于此实施例中，斜坡发生器120可通过采样信号SH读取多个输入信号S 0-S (M-1)(M是大于1的正整数)，而具有良好的电源电压抑制比。相关的说明容后再叙。
图像信号处理器130耦接于计数器116，用以根据数字信号Vd进行相关的图像处理。控制器140用以控制多个像素102.1-102.K、模数转换器110、斜坡发生器120和图像信号处理器130的操作。例如，传输信号Tx、复位信号Rst、选择信号Rsel、数字信号DIN及采样信号SH均可由控制器140提供。
图2是图1所示的斜坡发生器120的一实施方式的示意图。于此实施例中，斜坡发生器120可采用(但本申请不限于此)电流驱动型数模转换器来实施，并可包括电流产生电路222、M个电路分支224.1-224.M以及控制单元226。电流产生电路222用以根据数字信 号DIN产生负载电流IL。举例来说，电流产生电路222可包括N个电流源222.1-222.N和N个电流开关SWI 1-SWI N。N个电流源222.1-222.N分别用以产生N个二进制权电流I 0-I (N-1)，其中电流源222.i所产生的二进制权电流I i可表示为I i＝I U×2 i，i是0到(N-1)之间的任一整数，I U是单位电流。N个电流开关SWI 0-SWI (N-1)由的数字信号DIN包括的N个位B 0-B (N-1)所控制，其中每一电流开关用以根据相应的位，选择性地将二进制权电流输出到输出端TL。
M个电路分支224.1-224.M耦接于电流产生电路222，用以根据负载电流IL产生斜坡电压Vramp。M个电路分支224.1-224.M中的每一电路分支可选择性地导通，以改变从输出端TL看进去的负载电阻RL。举例来说(但本申请不限于此)，M个电路分支224.1-224.M中的每一电路分支均可包括彼此串联于电流产生电路222与参考端TR之间的电阻(多个电阻R 0-R (M-1)其中的一个)与输出开关(多个输出开关SWR 0-SWR (M-1)其中的一个)。所述输出开关用以选择性地允许负载电流IL的至少一部分流经所述电阻以产生斜坡电压Vramp。于此实施例中，多个输出开关SWR 0-SWR (M-1)可由多个控制信号SC 0-SC (M-1)控制。例如，输出开关SWR 0可根据控制信号SC 0选择性地允许负载电流IL的至少一部分流经电阻R 0以产生斜坡电压Vramp。
控制单元226用以根据采样信号SH和多个输入信号S 0-S (M-1)产生多个控制信号SC 0-SC (M-1)，其中多个输入信号S 0-S (M-1)可由图1所示的控制器140提供。举例来说，控制单元226可根据采样信号SH选择性地采样多个输入信号S 0-S (M-1)，据以产生多个控制信号SC 0-SC (M-1)。当采样信号SH处于第一逻辑电平时，控制单元226可根据多个输入信号S 0-S (M-1)产生多个控制信号SC 0-SC (M-1)，以控制多个输出开关SWR 0-SWR (M-1)的操作。当采样信号SH处于不同于所述第一逻辑电平的第二逻辑电平时，控制单元226可保持多个控制信号SC 0-SC (M-1)不受多个输入信号S 0-S (M-1)的影响。以控制信号SC 0为例，当采样信号SH处于第一逻辑电平时，控制单元226可根据输入信号S 0产生控制信号SC 0，据以控制输出开关SWR 0。当采样信号SH处于 不同于所述第一逻辑电平的第二逻辑电平时，控制单元226可保持控制信号SC 0不受输入信号S 0的影响。
图3是图2所示的斜坡发生器120的至少一部分的一实施方式的示意图。出于说明的目的，图3仅示出图2所示的多个电路分支224.1和224.2相关的控制结构。在图2所示的电路分支的个数大于2的情形下，其他至少一电路分支的控制结构可采用图3所示的控制结构，而不会背离本申请的范围。控制单元226可包括(但不限于)第一控制电路326.1、第一电能存储单元C 0、第二控制电路326.2以及第一电能存储单元C 1。
第一控制电路326.1用以至少将参考电压VR1选择性地耦接于输出开关SWR 0的控制端，以在输出开关SWR 0的控制端产生控制信号SC 0。第一电能存储单元C 0耦接于第一控制电路326.1与输出开关SWR 0的控制端，用以存储控制信号SC 0的电能以产生第一存储结果SR 0，并且在参考电压VR1未耦接于输出开关SWR 0的控制端时，根据第一存储结果SR 0选择性地导通输出开关SWR 0。举例来说，在参考电压VR1是由电源电压来实施的情形下，第一电能存储单元C 0可存储将来自所述电源电压的电能，并可于所述电源电压未耦接于时输出开关SWR 0，根据所存储的电能导通输出开关SWR 0。因此，当输出开关SWR 0导通时，所述电源电压的噪声不会(或几乎不会)通过寄生电容C P0耦合到输出端TL。由于所述电源电压的噪声通过寄生电容C P0耦合到输出端TL的路径可被阻断，因此，斜坡发生器120可具有良好的电源电压抑制比。
相似地，第二控制电路326.2用以至少将参考电压VR1选择性地耦接于输出开关SWR 1的控制端，以在输出开关SWR 1的控制端产生控制信号SC 1。第二电能存储单元C 1耦接于第二控制电路326.2与输出开关SWR 1的控制端，用以存储控制信号SC 1的电能以产生第二存储结果SR 1，并且在参考电压VR1未耦接于输出开关SWR 1的控制端时，根据第二存储结果SR 1选择性地导通输出开关SWR 1。当输出 开关SWR 0导通时，参考电压VR1的噪声不会(或几乎不会)通过寄生电容C P1耦合到输出端TL。于此实施例中，输出开关SWR 0和输出开关SWR 1可晶体管来实施，以及第一电能存储单元C 0和第二电能存储单元C 1可由电容来实施。然而，本申请并不以此为限。例如，第一电能存储单元C 0和/或第二电能存储单元C 1可采用其他具有电能存储功能的电路部件来实施，而不会背离本申请的范围。
举例来说，第一控制电路326.1可根据采样信号SH与输入信号S 0将参考电压VR1选择性地耦接于输出开关SWR 0的控制端。当采样信号SH处于第一逻辑电平时，第一控制电路326.1可根据输入信号S 0将参考电压VR1选择性地耦接于输出开关SWR 0的控制端，据以产生控制信号SC 0。当采样信号SH处于第二逻辑电平时，第一控制电路326.1可使参考电压VR1未耦接于输出开关SWR 0的控制端。因此，输出开关SWR 0可在采样信号SH处于第二逻辑电平的期间导通，使斜坡电压Vramp受到参考电压VR1的噪声的影响可大幅减少。相似地，第二控制电路326.2可根据共享的采样信号SH与输入信号S 1将参考电压VR1选择性地耦接于输出开关SWR 1的控制端。当采样信号SH处于第一逻辑电平时，第二控制电路326.2可根据输入信号S 1将参考电压VR1选择性地耦接于输出开关SWR 1的控制端，据以产生控制信号SC 1。当采样信号SH处于第二逻辑电平时，第二控制电路326.2可使参考电压VR1未耦接于输出开关SWR 1的控制端。
第一控制电路326.1还可将参考电压VR2选择性地耦接于输出开关SWR 0的控制端，以在输出开关SWR 0的控制端产生控制信号SC 0。当参考电压VR1与参考电压VR2其中的一个耦接于输出开关SWR 0的控制端时，参考电压VR1与参考电压VR2其中的另一个未耦接于输出开关SWR 0的控制端。也就是说，第一控制电路326.1可将参考电压VR1选择性地耦接于输出开关SWR 0的控制端，也可将参考电压VR2选择性地耦接于输出开关SWR 0的控制端，其中控制信号SC 0可来自参考电压VR1或参考电压VR2。
例如，第一控制电路326.1可根据采样信号SH与输入信号S 0将参考电压VR1或参考电压VR2选择性地耦接于输出开关SWR 0的控制端。当采样信号SH处于第一逻辑电平时，第一控制电路326.1根据输入信号S 0将参考电压VR1与参考电压VR2其中的一个耦接于输出开关SWR 0的控制端。当采样信号SH处于第二逻辑电平时，第一控制电路326.1使参考电压VR1与参考电压VR2均未耦接于输出开关SWR 0的控制端。于此实施例中，参考电压VR1与参考电压VR2其中的一个可以是电源电压，参考电压VR1与参考电压VR2其中的另一个可以是接地电压。然而，本申请并不以此为限。
相似地，第二控制电路326.2还可将参考电压VR2选择性地耦接于输出开关SWR 1的控制端，以在输出开关SWR 1的控制端产生控制信号SC 1。当参考电压VR1与参考电压VR2其中的一个耦接于输出开关SWR 1的控制端时，参考电压VR1与参考电压VR2其中的另一个未耦接于输出开关SWR 1的控制端。
为方便理解，图3所示的第一控制电路326.1和第二控制电路326.2采用一示范性电路结构来说明本申请所公开的斜坡电压产生方案。然而，这是出于说明的目的。只要是可将参考电压的电能存储于电能存储单元，并根据所存储的电能导通电路分支以减少参考电压的噪声影响斜坡电压的控制电路结构，均属于本申请的范围。
于图3所示的实施例中，第一控制电路326.1可包括信号产生电路328.1、第一输入开关P 0以及第二输入开关N 0。信号产生电路326.1用以根据采样信号SH与输入信号S 0产生第一辅助信号SCP 0与第二辅助信号SCN 0。第一输入开关P 0耦接于信号产生电路328.1，用以根据第一辅助信号SCP 0将参考电压VR1选择性地耦接于输出开关SWR 0的控制端。第二输入开关N 0耦接于信号产生电路328.1，用以根据第二辅助信号SCN 0将参考电压VR2选择性地耦接于输出开关SWR 0的控制端。当采样信号SH处于第一逻辑电平时，信号产生电路328.1可采样输入信号S 0，使第一输入开关P 0与所述第二输入开关 N 0其中的一个导通，以及第一输入开关P 0与所述第二输入开关N 0其中的另一个断开。当采样信号SH处于第二逻辑电平时，信号产生电路328.1可不对输入信号S 0进行采样，使第一输入开关P 0与所述第二输入开关N 0均断开。
举例来说，信号产生电路328.1可包括与非门A0、反相器B0以及或非门C0。与非门A0用以根据采样信号SH与输入信号S 0产生第一辅助信号SCP 0。反相器B0用以接收采样信号SH以产生反相信号Sb0。或非门C0用以根据反相信号Sb0与输入信号S 0产生第二辅助信号SCN 0。相似地，第二控制电路326.2可包括信号产生电路328.2、第一输入开关P 1以及第二输入开关N 1。信号产生电路328.2可包括与非门A1、反相器B1以及或非门C1。与非门A1可产生第一辅助信号SCP 1。或非门C0可产生第二辅助信号SCN 1。
请连同图3参阅图4。图4是图3所示的斜坡发生器120所涉及的信号时序的一实施例的示意图。在时间点t 1之前，采样信号SH处于高逻辑电平，斜坡发生器120可处于采样模式M_S中。信号产生电路328.1可根据输入信号S 0产生第一辅助信号SCP 0和第二辅助信号SCN 0。于此实施例中，第一输入开关P 0可根据第一辅助信号SCP 0导通，使参考电压VR1耦接于输出开关SWR 0以产生具有高逻辑电平的控制信号SC 0。第一电能存储单元C 0可存储控制信号SC 0的电能，以产生第一存储结果SR 0。此外，第二输入开关N 0可根据第二辅助信号SCN 0断开。相似地，信号产生电路328.2可根据输入信号S 1产生第一辅助信号SCP 1和第二辅助信号SCN 1。第二电能存储单元C 1可存储处于高逻辑电平的控制信号SC 1的电能，以产生第二存储结果SR 1。
于时间点t1，采样信号SH切换至低逻辑电平，斜坡发生器120可处于保持模式M_H中。第一输入开关P 0与第二输入开关N 0均断开。于时间点t2，输入信号S 0与输入信号S 1均切换至低逻辑电平。由于斜坡发生器120处于保持模式M_H，因此，第一辅助信号SCP 0和 第二辅助信号SCN 0的信号电平仍维持不变，使第一输入开关P 0与第二输入开关N 0仍处于断开状态。值得注意的是，由于第一输入开关P 0与第二输入开关N 0可在保持模式M_H中维持在断开状态，因此，当图1所示的比较器114采用斜坡电压Vramp以进行比较操作时，参考电压VR1/VR2的噪声不会(或几乎不会)通过寄生电容C P0耦合到输出端TL。也就是说，斜坡发生器120可具有良好的电源电压抑制比。
于时间点t3，采样信号SH切换至低逻辑电平，斜坡发生器120处于采样模式M_S中。信号产生电路328.1可根据输入信号S 0产生第一辅助信号SCP 0和第二辅助信号SCN 0。因此，第二辅助信号SCN 0可切换至高逻辑电平。第一输入开关P 0可根据第一辅助信号SCP 0断开。第二输入开关N 0可根据第二辅助信号SCN 0导通，使参考电压VR2耦接于输出开关SWR 0以产生处于低逻辑电平的控制信号SC 0。相似地，控制信号SC 1可切换至低逻辑电平。于时间点t4，采样信号SH切换至低逻辑电平，斜坡发生器120可处于保持模式M_H中。第一输入开关P 0与第二输入开关N 0均断开。
通过本申请所公开的斜坡电压产生方案，本申请所公开的斜坡发生器可操作在采样模式或保持模式。由于斜坡电压可在保持模式中提供给模数转换器的比较器，以减少电源电压的噪声干扰，因此，模数转换器可得到更精确的转换结果。
请连同图1和图3参阅图5。图5是图1所示的斜坡发生器120所涉及的信号时序的一实施例的示意图。于此实施例中，斜坡发生器120可采用图2或图3所示的电路结构，而操作在采样模式或保持模式。于时间点T1，选择晶体管MS可根据选择信号Rsel导通，以启用像素102.1。于时间点T2，复位晶体管MR可根据复位信号Rst导通，以复位浮动扩散节点FN。在时间点T3与时间点T4之间，模数转换器110可对输出电压Vpout的复位电平进行转换。于时间点T4，传输晶体管MT可根据传输信号Tx导通，以将光电二极管PD 的转换结果传输至浮动扩散节点FN。在时间点T5与时间点T6之间，模数转换器110可对输出电压Vpout的信号电平进行转换。
于此实施例中，参考电压VR1可在比较器114停止將输出电压Vpout与斜坡电压Vramp作比较时耦接于输出开关SWR 0/SWR 1的控制端。例如，在模数转换器110未对输出电压Vpout的复位电平和信号电平进行转换的期间，斜坡发生器120可将参考电压VR1耦接于输出开关SWR 0的控制端，使第一电能存储单元C 0可存储来自参考电压VR1的电能。此外，在比较器114将输出电压Vpout与斜坡电压Vramp作比较时未耦接于输出开关SWR 0的控制端。例如，在模数转换器110对输出电压Vpout的复位电平或信号电平进行转换的期间，斜坡发生器120可使参考电压VR1未耦接于输出开关SWR 0的控制端，使输出开关SWR 0是根据第一存储结果SR 0导通，从而减少参考电压VR1的噪声对斜坡电压Vramp造成的干扰。
在某些实施例中，参考电压VR1可在像素102.1启用之前耦接于输出开关SWR 0的控制端。例如，采样信号SH可在时间区间TI 1处于高逻辑电平，以将参考电压VR1耦接于输出开关SWR 0的控制端。在某些实施例中，参考电压VR1可在像素102.1结束启用之后耦接于输出开关SWR 0的控制端。例如，采样信号SH可在时间区间TI2处于高逻辑电平，以将参考电压VR1耦接于输出开关SWR 0的控制端。在某些实施例中，参考电压VR1可在像素102.1启用之后以及比较器114将输出电压Vpout与斜坡电压Vramp作比较之前，耦接于输出开关SWR 0的控制端。例如，采样信号SH可在时间区间TI3处于高逻辑电平，以将参考电压VR1耦接于输出开关SWR 0的控制端。也就是说，控制器140可在时间区间TI1、时间区间TI2与时间区间TI3其中的一个时间区间产生处于高逻辑电平的采样信号SH。
图6是本申请的产生斜坡电压的方法的一实施例的流程图。假若所得到的结果实质上大致相同，则步骤不一定要按照图6所示的顺序来进行。举例来说，图3所示的方法600还可包括其他步骤。 本申请所公开的斜坡电压产生方案可采用基于方法600所进行的替代实施方式，而不致背离本申请的精神与范围。出于说明的目的，以下搭配图2与图3所示的斜坡发生器120来说明图6所示的方法600。然而，本申请并不以此为限。将方法600应用于图1所示的斜坡发生器120也是可行的。
于步骤602中，根据N位数字码选择性地输出N个二进制权电流的至少一部分，作为负载电流。例如，电流产生电路222可根据数字信号DIN选择性地输出N个二进制权电流I 0-I (N-1)的至少一部分，作为负载电流IL。
于步骤604中，针对彼此并联耦接M个电路分支的每一电路分支，于参考电压耦接于所述电路分支的控制端时，存储所述电路分支的控制端上的第一控制信号的电能，以产生第一存储结果。例如，当参考电压VR1耦接于电路分支224.1的控制端(即输出开关SWR 0的控制端)时，第一电能存储单元C 0可存储控制信号SC 0的电能，以产生第一存储结果SR 0。又例如，当参考电压VR2耦接于电路分支224.1的控制端(即输出开关SWR 0的控制端)时，第一电能存储单元C 0可存储控制信号SC 0的电能，以产生第一存储结果SR 0。
于步骤606中，针对所述电路分支，于所述参考电压未耦接于所述电路分支的控制端时，根据所述第一存储结果选择性地导通所述电路分支。例如，当参考电压VR1未耦接于电路分支224.1的控制端(即输出开关SWR 0的控制端)时，第一电能存储单元C 0可根据第一存储结果SR 0选择性地导通电路分支224.1。又例如，当参考电压VR2未耦接于电路分支224.1的控制端(即输出开关SWR 0的控制端)时，第一电能存储单元C 0可根据第一存储结果SR 0选择性地导通电路分支224.1。在参考电压VR1与参考电压VR2分别由电源电压与接地电压来实施的情形下，电路分支224.1可根据参考电压VR1相应的第一存储结果SR 0导通，以及根据参考电压VR2相应的第一存储结果SR 0断开。
于步骤608中，利用M个电路分支中至少一导通的电路分支接收所述负载电流，以产生斜坡电压。例如，可利用M个电路分支224.1-224.1中所导通的电路分支接收负载电流IL，以产生斜坡电压Vramp。
在某些实施例中，所述参考电压可根据采样信号与第一输入信号选择性地耦接于所述电路分支的控制端。于图3所示的实施例中，参考电压VR1可根据采样信号SH与输入信号S 0选择性地耦接于电路分支224.1的控制端。举例来说，当采样信号SH处于第一逻辑电平时，参考电压VR1可根据输入信号S 0选择性地耦接于电路分支224.1的控制端。当采样信号SH处于第二逻辑电平时，参考电压VR1未耦接于电路分支224.1的控制端。
在某些实施例中，另一参考电压可选择性地耦接于所述电路分支的控制端。于图3所示的实施例中，参考电压VR2可选择性地耦接于电路分支224.1的控制端。当参考电压VR1与参考电压VR2其中的一个耦接于电路分支224.1的控制端时，参考电压VR1与参考电压VR2其中的另一个未耦接于电路分支224.1的控制端。举例来说，参考电压VR1与参考电压VR2其中的一个可以是电源电压，参考电压VR1与参考电压VR2其中的另一个可以是接地电压。
此外，所述参考电压或所述另一参考电压可根据采样信号与第一输入信号选择性地耦接于所述电路分支的控制端。于图3所示的实施例中，参考电压VR1或参考电压VR2可根据采样信号SH与输入信号S 0选择性地耦接于电路分支224.1的控制端。例如，当采样信号SH处于第一逻辑电平时，参考电压VR1与参考电压VR2其中的一个可根据输入信号S 0耦接于电路分支224.1的控制端；当采样信号SH处于第二逻辑电平时，参考电压VR1与参考电压VR2均未耦接于所述电路分支224.1的控制端。
由于本领域的技术人员在阅读上述关于图1至图5的段落说明之后，应可了解图6所示的方法600的每一步骤的操作细节及其相 关的替代实施方式，因此，进一步的说明在此便不赘述。
上文的叙述简要地提出了本申请某些实施例的特征，使本领域的技术人员可更全面地理解本申请的多个层面。本领域的技术人员应可了解，其可轻易地利用本申请作为基础，来设计或更动其他流程与结构，以实现与上文所述的实施方式相同的目的和/或达到相同的优点。本领域的技术人员应当明白，这些等效的实施方式仍属于本申请的精神与范围，且其可进行各种改变、替代与更改，而不会背离本申请的精神与范围。

Claims (18)

  1. 一种斜坡发生器，其特征在于，包括：
    电流产生电路，用以产生负载电流；
    多个电路分支，耦接于所述电流产生电路，用以根据所述负载电流产生斜坡电压，其中所述多个电路分支中的一个电路分支包括彼此串联于所述电流产生电路与参考端之间的电阻与输出开关，所述输出开关用以选择性地允许所述负载电流的至少一部分流经所述电阻以产生所述斜坡电压；
    第一控制电路，用以至少将参考电压选择性地耦接于所述输出开关的控制端，以在所述输出开关的控制端产生第一控制信号；以及
    第一电能存储单元，耦接于所述第一控制电路与所述输出开关的控制端，用以存储所述第一控制信号的电能以产生第一存储结果，并且在所述参考电压未耦接于所述输出开关的控制端时，根据所述第一存储结果选择性地导通所述输出开关。
  2. 如权利要求1所述的斜坡发生器，其特征在于，所述参考电压是电源电压。
  3. 如权利要求1或2所述的斜坡发生器，其特征在于，所述第一控制电路用以根据采样信号与第一输入信号将所述参考电压选择性地耦接于所述输出开关的控制端，其中当所述采样信号处于第一逻辑电平时，所述第一控制电路根据所述第一输入信号将所述参考电压选择性地耦接于所述输出开关的控制端，以及当所述采样信号处于第二逻辑电平时，所述第一控制电路使所述参考电压未耦接于所述输出开关的控制端。
  4. 如权利要求3所述的斜坡发生器，其特征在于，所述多个电路分支中的另一电路分支包括彼此串联于所述电流产生电路与所述参考端之间的另一电阻与另一输出开关，所述另一输出开关用以选择性地允许所述负载电流的至少一部分流经所述另一电阻 以产生所述斜坡电压；所述斜坡发生器还包括：
    第二控制电路，用以将所述参考电压选择性地耦接于所述另一输出开关的控制端，以在所述另一输出开关的控制端产生第二控制信号；以及
    第二电能存储单元，耦接于所述第二控制电路与所述另一输出开关的控制端，用以存储所述第二控制信号的电能以产生第二存储结果，并且在所述参考电压未耦接于所述另一输出开关的控制端时，根据所述第二存储结果选择性地导通所述另一输出开关；
    其中所述第二控制电路用以根据所述采样信号与第二输入信号将所述参考电压选择性地耦接于所述另一输出开关的控制端，其中当所述采样信号处于所述第一逻辑电平时，所述第二控制电路根据所述第二输入信号将所述参考电压选择性地耦接于所述另一输出开关的控制端，以及当所述采样信号处于所述第二逻辑电平时，所述第二控制电路使所述参考电压未耦接于所述另一输出开关的控制端。
  5. 如权利要求1所述的斜坡发生器，其特征在于，所述第一控制电路还用以将另一参考电压选择性地耦接于所述输出开关的控制端，以在所述输出开关的控制端产生所述第一控制信号，其中当所述参考电压与所述另一参考电压其中的一个耦接于所述输出开关的控制端时，所述参考电压与所述另一参考电压其中的另一个未耦接于所述输出开关的控制端。
  6. 如权利要求5所述的斜坡发生器，其特征在于，所述参考电压是电源电压，以及所述另一参考电压是接地电压。
  7. 如权利要求5或6所述的斜坡发生器，其特征在于，所述第一控制电路用以根据采样信号与第一输入信号将所述参考电压或所述另一参考电压选择性地耦接于所述输出开关的控制端，其中 当所述采样信号处于第一逻辑电平时，所述第一控制电路根据所述第一输入信号将所述参考电压与所述另一参考电压其中的一个耦接于所述输出开关的控制端；当所述采样信号处于第二逻辑电平时，所述第一控制电路使所述参考电压与所述另一参考电压均未耦接于所述输出开关的控制端。
  8. 如权利要求7所述的斜坡发生器，其特征在于，所述第一控制电路包括：
    信号产生电路，用以根据所述采样信号与所述第一输入信号产生第一辅助信号与第二辅助信号；
    第一输入开关，耦接于所述信号产生电路，用以根据所述第一辅助信号将所述参考电压选择性地耦接于所述输出开关的控制端；以及
    第二输入开关，耦接于所述信号产生电路，用以根据所述第二辅助信号将所述另一参考电压选择性地耦接于所述输出开关的控制端；
    其中当所述采样信号处于所述第一逻辑电平时，所述第一输入开关与所述第二输入开关其中的一个导通，以及所述第一输入开关与所述第二输入开关其中的另一个断开；当所述采样信号处于所述第二逻辑电平时，所述第一输入开关与所述第二输入开关均断开。
  9. 如权利要求8所述的斜坡发生器，其特征在于，所述信号产生电路包括：
    与非门，用以根据所述采样信号与所述第一输入信号产生所述第一辅助信号；
    反相器，用以接收所述采样信号以产生反相信号；以及
    或非门，用以根据所述反相信号与所述第一输入信号产生所述 第二辅助信号。
  10. 一种图像传感电路，其特征在于，包括：
    多个像素；
    比较器，耦接于所述多个像素，用以将所述多个像素中的一个像素的输出电压与斜坡电压作比较，以产生比较结果；
    如权利要求1至9中任一项所述的斜坡发生器，耦接于所述比较器，用以产生所述斜坡电压，其中所述参考电压是在所述比较器停止將所述输出电压与所述斜坡电压作比较时耦接于所述输出开关的控制端，并且在所述比较器将所述输出电压与所述斜坡电压作比较时未耦接于所述输出开关的控制端；以及
    计数器，耦接于所述比较器，用以根据所述比较结果产生所述输出电压相应的数字信号。
  11. 如权利要求10所述的图像传感电路，其特征在于，所述参考电压是在所述像素启用之前耦接于所述输出开关的控制端。
  12. 如权利要求10所述的图像传感电路，其特征在于，所述参考电压是在所述像素结束启用之后耦接于所述输出开关的控制端。
  13. 如权利要求10所述的图像传感电路，其特征在于，所述参考电压是在所述像素启用之后以及所述比较器将所述输出电压与所述斜坡电压作比较之前，耦接于所述输出开关的控制端。
  14. 一种产生斜坡电压的方法，其特征在于，包括：
    根据N位数字码选择性地输出N个二进制权电流的至少一部分，作为负载电流；以及
    针对彼此并联耦接M个电路分支的每一电路分支：
    于参考电压耦接于所述电路分支的控制端时，存储所述电路 分支的控制端上的第一控制信号的电能，以产生第一存储结果；以及
    于所述参考电压未耦接于所述电路分支的控制端时，根据所述第一存储结果选择性地导通所述电路分支；以及
    利用M个电路分支中至少一导通的电路分支接收所述负载电流，以产生斜坡电压。
  15. 如权利要求14所述的方法，其特征在于，还包括：
    根据采样信号与第一输入信号将所述参考电压选择性地耦接于所述电路分支的控制端；
    其中当所述采样信号处于第一逻辑电平时，所述参考电压根据所述第一输入信号选择性地耦接于所述电路分支的控制端；当所述采样信号处于第二逻辑电平时，所述参考电压未耦接于所述电路分支的控制端。
  16. 如权利要求14所述的方法，其特征在于，还包括：
    将另一参考电压选择性地耦接于所述电路分支的控制端；
    其中当所述参考电压与所述另一参考电压其中的一个耦接于所述电路分支的控制端时，所述参考电压与所述另一参考电压其中的另一个未耦接于所述电路分支的控制端。
  17. 如权利要求16所述的方法，其特征在于，所述参考电压与所述另一参考电压其中的一个是电源电压，以及所述参考电压与所述另一参考电压其中的另一个是接地电压。
  18. 如权利要求16所述的方法，其特征在于，还包括：
    根据采样信号与第一输入信号将所述参考电压或所述另一参考电压选择性地耦接于所述电路分支的控制端；
    其中当所述采样信号处于第一逻辑电平时，所述参考电压与所 述另一参考电压其中的一个根据所述第一输入信号耦接于所述电路分支的控制端；当所述采样信号处于第二逻辑电平时，所述参考电压与所述另一参考电压均未耦接于所述电路分支的控制端。
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