WO2022262584A1 - 一种通信方法及装置 - Google Patents

一种通信方法及装置 Download PDF

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Publication number
WO2022262584A1
WO2022262584A1 PCT/CN2022/096686 CN2022096686W WO2022262584A1 WO 2022262584 A1 WO2022262584 A1 WO 2022262584A1 CN 2022096686 W CN2022096686 W CN 2022096686W WO 2022262584 A1 WO2022262584 A1 WO 2022262584A1
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Prior art keywords
sequence
subcarrier
signal
mapped
signals
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PCT/CN2022/096686
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English (en)
French (fr)
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黄煌
马千里
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华为技术有限公司
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Publication of WO2022262584A1 publication Critical patent/WO2022262584A1/zh
Priority to US18/541,050 priority Critical patent/US20240121068A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0091—Signaling for the administration of the divided path
    • H04L5/0094—Indication of how sub-channels of the path are allocated
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0224—Channel estimation using sounding signals
    • H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/0055—ZCZ [zero correlation zone]
    • H04J13/0059—CAZAC [constant-amplitude and zero auto-correlation]
    • H04J13/0062—Zadoff-Chu
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits
    • H04L27/362—Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0044—Arrangements for allocating sub-channels of the transmission path allocation of payload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
    • H04L5/0051—Allocation of pilot signals, i.e. of signals known to the receiver of dedicated pilots, i.e. pilots destined for a single user or terminal

Definitions

  • the embodiments of the present application relate to the communication field, and in particular, to a communication method and device.
  • High frequency (such as the frequency band above 6 GHz) has become a research and development hot spot in the industry to solve the growing communication demand due to its abundant frequency band resources. Notable features include high bandwidth, highly integrated antenna arrays for high throughput, and severe mid-radio frequency distortion issues.
  • phase noise as an example, as the frequency band increases, the higher the power spectral density of phase noise, the greater the impact on the received signal, that is, the higher the operating frequency, the greater the phase noise.
  • high-order modulation is often used, such as 16 quadrature amplitude modulation (QAM), 64QAM, 256QAM, etc. High-order modulation is often easily affected by phase noise.
  • the demodulation performance of data with different modulation orders in the same frequency band will also be affected by phase noise. The higher the modulation order, the more sensitive to phase noise. Similarly, under the same modulation order, the demodulation performance of data with different code rates will also be affected by phase noise.
  • Embodiments of the present application provide a communication method and device to improve data demodulation performance.
  • a communication method wherein the multiple signals included in the first sequence are mapped to M subcarrier blocks used to transmit reference signals; wherein, the mth subcarrier block includes Q m subcarriers , Q m is an integer greater than or equal to 2, m takes an integer from 1 to M, and M is an integer greater than or equal to 2; the first sequence includes a plurality of signals, and the position in the mth subcarrier block is close to The multiple signals mapped on the subsequent multiple consecutive sub-carriers are the same as the multiple signals mapped on the front multiple consecutive sub-carriers in the mod(m, M)+1th sub-carrier block; wherein, mod(m , M) is the remainder of m divided by M. Then, the mapped signal is transmitted on each of the subcarrier blocks.
  • the reference signal may be used for phase tracking, or the reference signal may be used for estimating phase noise.
  • the reference signal includes but is not limited to a phase tracking reference signal (phase tracking reference signal, PTRS).
  • the present application jointly designs signals transmitted on multiple reference signal subcarrier blocks, and constitutes a cyclic redundancy feature in multiple reference signal (eg, PTRS) subcarrier blocks.
  • the length of the first sequence is longer, so as to construct a larger cyclic shift matrix than the prior art for estimating the ICI coefficients generated by phase noise, which can improve the estimation accuracy of the ICI coefficients, thereby improving the performance of data demodulation .
  • the multiple signals mapped on any subcarrier block are different.
  • the first sequence when mapping the first sequence to M subcarrier blocks used to transmit reference signals, the first sequence may be mapped in the order of increasing subcarrier index and increasing signal index to M subcarrier blocks for transmitting reference signals; or, in the order of increasing subcarrier index and decreasing signal index, mapping the first sequence to M subcarrier blocks for transmitting reference signals.
  • mapping the first sequence when mapping the first sequence to M subcarrier blocks used to transmit reference signals, the first sequence may be mapped in the order of increasing subcarrier index and increasing signal index to M subcarrier blocks for transmitting reference signals; or, in the order of increasing subcarrier index and decreasing signal index, mapping the first sequence to M subcarrier blocks for transmitting reference signals.
  • the mth subcarrier block includes: a first subcarrier with a length of p1 m arranged in sequence, a second subcarrier with a length of L m , and a third subcarrier with a length of p2 m ; wherein, The signals mapped on the second subcarriers in the M subcarrier blocks are continuous in the first sequence.
  • the first sequence may first be sequentially mapped to the second subcarrier in the M subcarrier blocks. Then, according to the way that the signal mapped on each subcarrier block is cyclically continuous, the signal in the first sequence is mapped to the first subcarrier and the third subcarrier in the M subcarrier blocks, so as to realize the
  • the multiple signals mapped on multiple consecutive subcarriers at the rear in the mth subcarrier block and the multiple signals mapped on the multiple consecutive subcarriers at the front in the mod(m, M)+1th subcarrier block The signals are the same.
  • floor is rounded down
  • ceil is rounded up
  • N is the length of the first sequence.
  • the value of m is a partial integer or all integers from 1 to M. That is, among the M subcarrier blocks, the lengths of the second subcarriers in all the subcarrier blocks may satisfy the formula, or the lengths of the second subcarriers in a part of the subcarrier blocks may satisfy the formula.
  • the length L of the second subcarriers in different subcarrier blocks is the same as possible. When the lengths of the second subcarriers in all subcarrier blocks are the same, the cycle characteristic is better, and the demodulation performance can be further improved.
  • the difference between the p1 m and the p2 m is less than or equal to 1, and m is a partial integer or all integers from 1 to M. That is, among the M subcarrier blocks, the difference between the length of the first subcarrier and the length of the third subcarrier in all or part of the subcarrier blocks may be less than or equal to 1. Redundancy on both sides of a subcarrier block is as equal as possible, which can improve phase noise estimation performance and further improve demodulation performance.
  • the value of Q m is determined based on the values of p1 m and/or p2 m .
  • m is a partial integer or all integers from 1 to M.
  • the values of p1 m and p2 m are associated with at least one of Q m , M, and N.
  • m is a partial integer or all integers from 1 to M.
  • the Q m a*q, wherein, q is the number of subcarriers of a resource block RB, a is an integer greater than or equal to 1, and m is a partial integer from 1 to M or all integers.
  • resource scheduling it is usually scheduled according to resource blocks.
  • the value of Q is an integer multiple of the number of subcarriers in a resource block RB, which is easy to schedule.
  • the first sequence may be any of the following sequences: a ZC sequence, a quadrature amplitude modulation QAM sequence, a complementary sequence, and a pseudo-random sequence.
  • the cyclic shift of the ZC sequence is orthogonal, so each column of the matrix of the first sequence is orthogonal, and the ICI coefficient of the inter-subcarrier interference coefficient generated by the phase noise can be better estimated.
  • Time-domain/frequency-domain QAM sequences are simple to implement, and can share a signal modulation generator with data QAM modulation.
  • the pseudo-random sequence is the same as the sequence generation method in the existing cellular communication system, and the generator can be shared. Complementary sequences are simple to implement.
  • a communication device in a second aspect, has a function of realizing the above-mentioned first aspect and any possible implementation of the first aspect.
  • These functions may be implemented by hardware, or may be implemented by executing corresponding software through hardware.
  • the hardware or software includes one or more functional modules corresponding to the above functions.
  • the apparatus includes: a processing module, configured to map the first sequence to M subcarrier blocks used to transmit reference signals; wherein, the mth subcarrier block includes Q m subcarriers, Q m is an integer greater than or equal to 2, m takes an integer from 1 to M, and the M is an integer greater than or equal to 2; the first sequence includes a plurality of signals, and the position of the mth subcarrier block is later
  • the multiple signals mapped on multiple consecutive subcarriers in the mod(m, M)+1th subcarrier block are the same as the multiple signals mapped on the front multiple consecutive subcarriers in the subcarrier block; where mod(m, M) is a remainder of dividing m by M;
  • a sending module configured to send the mapped signal on each of the subcarriers.
  • the processing module may be configured to map the first sequence to M subcarrier blocks used to transmit reference signals in order of increasing subcarrier index, or it may also be used to The first sequence is mapped to M subcarrier blocks used for transmitting reference signals in the order of increasing subcarrier index and decreasing signal index.
  • a communication device including a processor, and optionally, a memory; the processor is coupled to the memory; the memory stores computer programs or instructions; the processor is configured to execute Part or all of the computer programs or instructions in the memory, when the part or all of the computer programs or instructions are executed, are used to implement the above first aspect and the functions in any possible implementation method of the first aspect.
  • the apparatus may further include a transceiver, where the transceiver is configured to send a signal processed by the processor, or receive a signal input to the processor.
  • the transceiver may perform the sending action or receiving action performed in the first aspect and any possible implementation of the first aspect.
  • the present application provides a system-on-a-chip, which includes one or more processors (also referred to as processing circuits), and the electrical coupling between the processors and memories (also referred to as storage media)
  • the memory may or may not be located in the chip system; the memory is used to store computer programs or instructions; the processor is used to execute part or all of the memory
  • Computer programs or instructions, when part or all of the computer programs or instructions are executed, are used to implement the above first aspect and the functions in any possible implementation methods of the first aspect.
  • the chip system may further include an input and output interface (also referred to as a communication interface), the input and output interface is used to output the signal processed by the processor, or receive an input to the signal to the processor.
  • the input-output interface may perform the sending action or receiving action performed in the first aspect and any possible implementation of the first aspect. Specifically, the output interface can perform a sending action, and the input interface can perform a receiving action.
  • system-on-a-chip may consist of chips, or may include chips and other discrete devices.
  • a computer-readable storage medium for storing a computer program, the computer program including instructions for realizing the functions in the above-mentioned first aspect and any possible implementation of the first aspect.
  • a computer program product includes computer program code, and when the computer program code is run on a computer, the computer executes the above first aspect and any possible implementation of the first aspect method executed in .
  • Figure 1a is a schematic diagram of the influence of phase noise on a received signal in the frequency domain provided in an embodiment of the present application
  • FIG. 1b is a schematic diagram of the influence of phase noise on a received signal in the frequency domain provided in an embodiment of the present application
  • FIG. 1c is a schematic diagram of the influence of phase noise on a received signal in the frequency domain provided in an embodiment of the present application
  • FIG. 2a is a schematic diagram of a communication system provided in an embodiment of the present application.
  • FIG. 2b is a schematic diagram of a communication system provided in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of transmitting PTRS in a subcarrier provided in an embodiment of the present application
  • FIG. 4a is a schematic diagram of a method for transmitting signals provided in an embodiment of the present application.
  • FIG. 4b is a schematic diagram of a method for transmitting signals provided in an embodiment of the present application.
  • Figure 5a is a schematic diagram of a sequence provided in the embodiment of the present application.
  • Figure 5b is a schematic diagram of a sequence provided in the embodiment of the present application.
  • Figure 5c is a schematic diagram of a sequence provided in the embodiment of the present application.
  • FIG. 6 is a schematic diagram of a signal mapping provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a data demodulation performance provided in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a communication device provided in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a communication device provided in an embodiment of the present application.
  • Network equipment which has a device capable of providing random access functions for terminal devices or a chip that can be set on the device, including but not limited to: evolved Node B (evolved Node B, eNB), wireless network controller (radio network controller, RNC), node B (Node B, NB), base station controller (base station controller, BSC), base transceiver station (base transceiver station, BTS), home base station (for example, home evolved NodeB, or home Node B, HNB), baseband unit (baseband unit, BBU), access point (access point, AP) in wireless fidelity (wireless fidelity, WIFI) system, wireless relay node, wireless backhaul node, transmission point ( transmission and reception point, TRP or transmission point, TP), etc., can also be 5G, such as NR, gNB in the system, or transmission point (TRP or TP), one or a group of base stations in the 5G system (including Multiple antenna panels) Antenna panels, or, can also be a network no
  • Terminal equipment also known as user equipment (UE), mobile station (mobile station, MS), mobile terminal (mobile terminal, MT), terminal, etc.
  • UE user equipment
  • MS mobile station
  • MT mobile terminal
  • terminal device includes a handheld device with a wireless connection function, a vehicle-mounted device, and the like.
  • the terminal equipment can be: mobile phone (mobile phone), tablet computer, notebook computer, palmtop computer, mobile Internet device (mobile internet device, MID), wearable device, virtual reality (virtual reality, VR) equipment, augmented reality (augmented reality (AR) equipment, wireless terminals in industrial control (for example, sensors, etc.), wireless terminals in self-driving (self-driving), wireless terminals in remote medical surgery, smart Wireless terminals in smart grid, wireless terminals in transportation safety, wireless terminals in smart city, or wireless terminals in smart home, or with vehicles and vehicles ( Vehicle-to-Vehicle, V2V means) public wireless terminals, etc.
  • Phase noise refers to the random change in the phase of the system output signal caused by the system (such as various radio frequency devices) under the action of various noises.
  • Phase noise can be fluctuations in the phase of a signal that occur over a short period of time. In this case, phase noise can interrupt the reception of the signal because it randomly changes the phase of the received signal in the time domain.
  • Phase noise can occur randomly, however, phase noise can show a certain correlation between adjacent time samples, which will lead to common phase error (CPE) and inter sub-carrier interference (inter sub-carrier interference) in the frequency domain.
  • CPE common phase error
  • inter sub-carrier interference inter sub-carrier interference
  • phase noise When the power spectral density of the phase noise (the phase noise will be abbreviated as phase noise later) reaches a certain level, when the modulation order is high, in addition to the common phase error CPE, the inter sub-carrier interference (inter sub-carrier interference) caused by the phase noise , ICI) can not be ignored.
  • Figure 1a, Figure 1b and Figure 1c introduce the influence of different phase noises on the received signal in frequency domain, Figure 1a shows the influence of no phase noise; Figure 1b shows the influence of weak phase noise, and Figure 1c shows the influence of strong phase noise. As the frequency band increases, the higher the power spectral density of the phase noise is, the greater the impact on the received signal can be seen.
  • OFDM orthogonal frequency division multiplexing
  • R i is the received signal on the i-th subcarrier
  • S i is the transmitted signal on the i-th sub-carrier
  • mod is a remainder operation
  • k can refer to ij in the above formula.
  • E 0 is called the common phase error CPE
  • other E (such as E1, E2) is called the inter-subcarrier interference coefficient
  • other E will bring interference to the received signal of the i subcarrier to the signal of other subcarriers, that is, the inter-subcarrier interfere with ICI.
  • the common phase error CPE and the inter-subcarrier interference ICI are collectively referred to as phase noise ICI coefficients.
  • system architecture provided by the embodiments of the present application. It can be understood that the system architecture described in the embodiments of the present application is for more clearly illustrating the technical solutions of the embodiments of the present application, and does not constitute a limitation on the technical solutions provided by the embodiments of the present application.
  • the technical solutions of the embodiments of the present application can be applied to various communication systems, such as satellite communication systems and traditional mobile communication systems.
  • the satellite communication system may be integrated with a traditional mobile communication system (ie, a ground communication system).
  • Communication systems such as: wireless local area network (wireless local area network, WLAN) communication system, long term evolution (long term evolution, LTE) system, LTE frequency division duplex (frequency division duplex, FDD) system, LTE time division duplex (time division duplex) , TDD), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX) Communication System, Fifth Generation (5th Generation, 5G) System or New Radio (new radio , NR), the sixth generation (6th generation, 6G) system, and future communication systems, etc.
  • WLAN wireless local area network
  • LTE long term evolution
  • LTE frequency division duplex frequency division duplex
  • FDD frequency division duplex
  • time division duplex time division duplex
  • TDD Time division duplex
  • UMTS Universal Mobile T
  • the communication system shown in Fig. 2a includes network devices and terminal devices, for example, includes single or multiple network devices, and single or multiple terminal devices.
  • a single network device may transmit data or control signaling (eg (a)) to a single or multiple terminal devices.
  • Multiple network devices can also simultaneously transmit data or control signaling for a single terminal device (eg (b)).
  • the terminal device 10 includes: at least one processor 101 and at least one transceiver 103 , and optionally, at least one memory 102 may also be included.
  • the memory 102 may exist independently, or the memory 102 may also be integrated with the processor 101, for example, integrated into one chip.
  • the memory 102 can store program codes for executing the technical solutions of the embodiments of the present application, and the execution is controlled by the processor 101 , and various types of computer program codes to be executed can also be regarded as drivers for the processor 101 .
  • the processor 101 is configured to execute computer program codes stored in the memory 102, so as to implement the technical solutions in the embodiments of the present application.
  • the transceiver 103 includes a transmitter 1031 , a receiver 1032 and an antenna 1033 .
  • the receiver 1032 can be used to receive data or control signaling from the network device 20 through the antenna 1033
  • the transmitter 1031 can be used to send information to the network device 20 through the antenna 1033 .
  • the network device 20 includes: at least one processor 201 and at least one transceiver 203 , and optionally, at least one memory 202 may also be included.
  • the memory 202 may exist independently, or the memory 202 may also be integrated with the processor 201, for example, integrated into one chip.
  • the memory 202 can store program codes for executing the technical solutions of the embodiments of the present application, and the execution is controlled by the processor 201 , and various types of computer program codes to be executed can also be regarded as drivers for the processor 201 .
  • the processor 201 is configured to execute computer program codes stored in the memory 202, so as to implement the technical solutions in the embodiments of the present application.
  • the transceiver 203 includes a transmitter 2031 , a receiver 2032 and an antenna 2033 .
  • the transmitter 2031 may be used to send data or control signaling to the terminal device 10 through the antenna 2033
  • the receiver 2032 may be used to receive information of the terminal device 10 through the antenna 2033 .
  • the terminal device can send to the network device: a reference signal known to the network device, such as a phase tracking reference signal (phase tracking reference signal, PTRS).
  • a reference signal known to the network device such as a phase tracking reference signal (phase tracking reference signal, PTRS).
  • PTRS phase tracking reference signal
  • Network equipment can estimate phase noise according to PTRS, and then perform corresponding phase compensation to improve data demodulation performance. The higher the density of PTRS in the time domain, the more accurate the estimation of phase noise.
  • a schematic diagram of PTRS transmission in subcarriers is provided, and multiple consecutive subcarriers used to transmit PTRS are called a PTRS subcarrier block, such as PTRS block 1, PTRS block 2, PTRS block 3.
  • a PTRS includes in order: a cyclic redundancy sequence 1 (circular sequence part1) of length p1, a base sequence (base sequence) of length L, and a cyclic redundancy sequence 2 (circular sequence part2) of length p2.
  • a PTRS subcarrier block includes sequentially arranged: the first subcarrier with a length of p1 (the first subcarrier is used to transmit the cyclic redundancy sequence 1), and the second subcarrier with a length of L (the second subcarrier is used for based on the transmission base sequence), the third subcarrier with a length of p2 (the third subcarrier is used to transmit the cyclic redundancy sequence 2).
  • the L signals in the base sequence are signals S 1 to S L .
  • the p1 signals in the cyclic redundancy sequence 1 preceding the base sequence are respectively SL-p1+1 to SL .
  • the p2 signals in the cyclic redundant sequence 2 following the base sequence are respectively S 1 to S p2 .
  • the received signal of the subcarrier where the signal S 1 -S L is located can be obtained as follows:
  • Residual ICI is ICI caused by E other than E -2 , E -1 , E 0 , E 1 , E 2 .
  • the base sequence is a ZC (Zadoff–Chu) sequence
  • ZC Zero-C
  • each column of the S matrix is orthogonal due to the added cyclic redundancy sequence. Therefore, the performance of estimating E -2 , E -1 , E 0 , E 1 , E 2 from the received signal r is better.
  • each PTRS subcarrier block When subcarriers transmit multiple PTRS, the cyclic redundancy characteristics of each PTRS subcarrier block are the same and independent, that is, the signals at the corresponding positions in PTRS block 1, PTRS block 2, and PTRS block 3 in Figure 3 Are the same. Although multiple PTRS sub-carrier blocks all have the cyclic redundancy feature, in fact only one PTRS sub-carrier block constitutes the cyclic redundancy feature. Since the length L of the base sequence is short, the estimation performance of E ⁇ 2 , E ⁇ 1 , E 0 , E 1 , E 2 (inter-subcarrier interference coefficient ICI) is limited.
  • the present application proposes a scheme of forming cyclic redundancy characteristics in multiple reference signal (eg, PTRS) subcarrier blocks.
  • the present application jointly designs the base sequence transmitted on multiple reference signal subcarrier blocks, and the corresponding cyclic redundancy transmission scheme.
  • the longer sequence length can improve the estimation accuracy of the inter-subcarrier interference coefficient ICI generated by the phase noise, thereby improving the data demodulation performance.
  • FIG. 4a a schematic diagram of a method for sending a signal is provided, including the following steps:
  • Step 401 the first device acquires a first sequence.
  • the first device may be a terminal device or a network device.
  • the first device may generate the first sequence by itself, or obtain the first sequence from other devices.
  • the length of the first sequence is N, that is, the first sequence includes N signals.
  • the first sequence is used to generate a reference signal, for example, the reference signal is a reference signal for phase tracking, or the reference signal is a reference signal for estimating phase noise.
  • the reference signal includes but not limited to PTRS.
  • the first sequence may be a ZC (Zadoff–Chu) sequence.
  • the ZC sequence satisfies the following formula:
  • S n exp(-j* ⁇ *u*(n+a)*(n+b)/N); S n is the first sequence.
  • the greatest common multiple of u and N may be constrained to be 1, that is, u and N are mutually prime.
  • the magnitude of the characteristic root of the matrix S n above is the same, which can better estimate the ICI coefficient E of the inter-subcarrier interference coefficient generated by the phase noise.
  • the first sequence is the truncation of the ZC (Zadoff–Chu) root sequence, which is also a case of the ZC sequence.
  • the above-mentioned ZC sequence generated by constraining the length N of the first sequence to be a prime number is called a root sequence.
  • the sequence length required by the system is not a prime number, but other integers.
  • the actually used sequence length needs to be the same as the resource configuration length, and for the low PAPR sequence used for channel estimation, the sequence length needs to be equal to a multiple of 12. (The length of a transmission resource block Resource Block defined by the protocol in 5G/4G is 12). Therefore, the generated prime number root sequence is usually truncated to obtain the desired sequence length.
  • the truncation method can be: [1:K] pieces of the root sequence of length N, or [N-K+1:N] of the root sequence of length N, or [A:A+K-] of the root sequence of length N. 1] pcs.
  • a ZC sequence with a length of 48 is required in practice.
  • the first sequence may be a time-domain quadrature amplitude modulation (QAM) sequence.
  • QAM quadrature amplitude modulation
  • the first sequence may be defined in the time domain, for example, the signal included in the first sequence is a modulation symbol in the time domain.
  • the modulation symbol is a standard BPSK signal, or a signal scaled by the standard BPSK, and there are 2 N kinds of sequence combinations.
  • the modulation symbol is a pi/2BPSK signal, or a signal scaled by pi/2BPSK, and there are 2 N types of sequence combinations.
  • the modulation symbol is a QPSK signal, or a signal obtained by scaling the QPSK signal, and there are 4 N types of sequence combinations.
  • the N-point Fourier transform is used to transform to the frequency domain, and the sequence with a relatively stable amplitude response in the frequency domain is selected as an effective sequence output.
  • this application transforms 4 N kinds of sequence combinations into the frequency domain through N-point Fourier transform, and selects the sequence with a relatively stable amplitude response in the frequency domain as an effective sequence output.
  • an effective sequence set is selected from among the plurality of effective sequences.
  • the first P groups are selected as the effective sequence set of the time-domain QPSK sequence in order of small to large amplitude variance values, and the larger N is, the more stable the selected sequence is.
  • the selected effective sequence set in the time domain can include the sequences in Figure 5a, Figure 5b, and Figure 5c, and the corresponding OFDM subcarrier frequency domain sequences are the sequences in Figure 5a, Figure 5b, and Figure 5c Sequence after FFT.
  • a certain sequence may be selected as the first sequence in the valid sequence set.
  • which time-domain QAM sequence is selected by the terminal device as the first sequence may be configured by the network device to the terminal device, or may be determined by the terminal device based on at least one The parameters are calculated.
  • the first sequence may also be a frequency-domain QAM sequence.
  • the first sequence may be defined in the frequency domain, for example, the signal included in the first sequence is a modulation symbol in the frequency domain.
  • the modulation symbol is a standard BPSK signal, or a signal scaled by the standard BPSK, and there are 2 N kinds of sequence combinations.
  • the modulation symbol is a pi/2BPSK signal, or a signal scaled by pi/2BPSK, and there are 2 N types of sequence combinations.
  • the modulation symbol is a QPSK signal, or a signal obtained by scaling the QPSK signal, and there are 4 N types of sequence combinations.
  • Which frequency domain QAM sequence the terminal device selects as the first sequence can be configured by the network device to the terminal device, or can be calculated by the terminal device based on at least one parameter such as the cell ID, terminal device ID, subframe number where the PTRS is located, and the symbol where the PTRS is located. get.
  • the first sequence may be a complementary sequence.
  • Two complementary sequences are respectively denoted as S1 and S2, and S1 and S2 have the same length, and both are N/2.
  • Sequences S1 and S2 are spliced into a new sequence [S1S2] to form a first sequence of length N.
  • b B [1, 1, 1, 1, -1, 1, 1, 1, 1, 1, 1, -1, -1, -1, 1, -1, 1, 1, -1 ];
  • b A and b B are added after DFT modulation, and they are complementary sequences in the frequency domain.
  • C is a constant
  • Which complementary sequence the terminal device selects as the first sequence may be configured by the network device to the terminal device, or may be calculated by the terminal device based on at least one parameter such as the cell ID, the terminal device ID, the subframe number where the PTRS is located, and the symbol where the PTRS is located.
  • the first sequence may be a pseudo-random sequence.
  • QPSK modulation obtains the first sequence, and the first sequence is as follows:
  • x 1 (n+31) (x 1 (n+3)+x 1 (n)) mod 2
  • x 2 (n+31) (x 2 (n+3)+x 2 (n+2)+x 2 (n+1)+x 2 (n)) mod 2
  • N C 1600
  • c init is determined by at least one parameter such as the cell ID, the terminal device ID, the subframe number where the PTRS is located, and the symbol where the PTRS is located.
  • the above sequence is only an example, and the first sequence may also be other sequences.
  • the first sequence in the present application includes but is not limited to the sequences listed above.
  • Different first sequences may be applicable to different application scenarios due to their own different characteristics.
  • the cyclic shift of the ZC sequence is orthogonal, so each column of the above S matrix is orthogonal, and the ICI coefficient of the inter-subcarrier interference coefficient generated by the phase noise can be better estimated.
  • time-domain/frequency-domain QAM sequences are simple to implement and can share a signal modulation generator with data QAM modulation.
  • the pseudo-random sequence can share the same generator as the sequence generation method in the existing cellular communication system.
  • Step 402 The first device maps the first sequence to M subcarrier blocks used for transmitting reference signals.
  • adjacent subcarrier blocks for transmitting reference signals include subcarrier blocks for transmitting data.
  • M may be an integer greater than or equal to 2.
  • subcarrier block used to transmit reference signals will be referred to as “subcarrier block” for short, and the “subcarrier block used to transmit reference signals” will be referred to as “subcarrier” for short.
  • the mth subcarrier block includes Q m subcarriers, and Q m is an integer greater than 2.
  • the m takes positive integers from 1 to M in turn.
  • the numbers of subcarriers included in different subcarrier blocks may be the same or different.
  • the difference in the number of subcarriers included in different subcarrier blocks is less than or equal to 1.
  • the difference between Q m and Q m+1 is less than or equal to 1.
  • the difference between Q m and Q m+2 is less than or equal to 1.
  • the length N of the first sequence is greater than the number of subcarriers included in any subcarrier block, and N is smaller than the sum of the numbers of subcarriers included in M subcarrier blocks. That is, N is greater than Q m , and N is less than the sum of Q 1 , Q 2 , . . . , Q m-1 , and Q m .
  • each signal in the first sequence is mapped to a subcarrier, for any subcarrier block, the multiple signals mapped to the subcarrier block are different.
  • consecutive multiple (for example, Q) signals in the first sequence may be mapped to one subcarrier block (for example, Q m subcarriers).
  • a plurality of cyclically continuous signals (for example, Q signals) in the first sequence may be mapped to one subcarrier block (for example, Q m subcarriers). Cyclic continuous, it can be understood that when the last signal in the first sequence is mapped to a certain subcarrier a, then the first signal in the first sequence is mapped to the next subcarrier of subcarrier a (the The method is to perform mapping in the order of increasing subcarrier index and increasing signal index).
  • the last signal in the first sequence is mapped to the next subcarrier of subcarrier a (this method is based on the subcarrier index Incrementing, signal index-decreasing order is mapped).
  • the first sequence may be mapped to M (for example, M consecutive) subcarrier blocks in the order of increasing subcarrier index and increasing signal index.
  • the first sequence may also be mapped to M (for example, M consecutive) subcarrier blocks in the order of increasing subcarrier index and decreasing signal index.
  • the multiple (for example i) signals mapped on multiple (for example i) consecutive subcarriers in the mth subcarrier block are the same as those in the m+1th subcarrier block
  • the multiple (eg i) signals mapped on multiple (eg i) consecutive subcarriers are the same, and m takes any integer from 1 to M-1. i is an integer greater than or equal to 1.
  • the 3 signals mapped on the last 3 subcarriers of the previous (mth) subcarrier block are the same as those mapped on the first 3 subcarriers of the next (m+1th) subcarrier block.
  • the indices of the nine signals mapped on the subcarrier block 1 in the first sequence are: 13, 14, 0, 1, 2, 3, 4, 5, 6;
  • the indices of the nine signals mapped on subcarrier block 2 in the first sequence are: 4, 5, 6, 7, 8, 9, 10, 11, 12;
  • the indices of the nine signals mapped on subcarrier block 3 in the first sequence are: 10, 11, 12, 13, 14, 0, 1, 2, and 3, respectively.
  • a plurality of (for example i) signals mapped on multiple (for example i) consecutive subcarriers in the mth subcarrier block and the position in the m+1th subcarrier block Multiple (such as i) consecutive subcarriers mapped to the same multiple (such as i) signals, and multiple (such as i) consecutive subcarriers in the Mth (last) subcarrier block.
  • the multiple (for example, i) signals mapped to above are the same as the multiple (for example, i) signals mapped to the first multiple (for example, i) consecutive subcarriers in the first subcarrier block.
  • the multiple signals mapped on the multiple consecutive sub-carriers positioned at the rear in the mth sub-carrier block are the same as the multiple consecutive signals mapped at the front in the mod(m, M)+1th sub-carrier block
  • Multiple signals to which subcarriers are mapped are the same.
  • mod(m, M) is the remainder of dividing m by M.
  • the 4 signals mapped on the last 4 subcarriers on the previous (mth) subcarrier block are the same as the first ones in the next (mod(m, M)+1) subcarrier block
  • the indices of the nine signals mapped on the subcarrier block 1 in the first sequence are: 13, 14, 0, 1, 2, 3, 4, 5, 6;
  • the indices of the nine signals mapped on the subcarrier block 2 in the first sequence are: 3, 4, 5, 6, 7, 8, 9, 10, 11;
  • the indices of the nine signals mapped on subcarrier block 3 in the first sequence are: 8, 9, 10, 11, 12, 13, 14, 0, 1, respectively.
  • the mth subcarrier block includes the first subcarrier with length p1 m in turn (the first subcarrier is used to transmit cyclic redundancy sequence 1), and the second subcarrier with length L m (the second subcarrier The carrier is used to transmit the base sequence), and the third subcarrier with a length of p2 m (the third subcarrier is used to transmit the cyclic redundancy sequence 2).
  • the first subcarrier is used to transmit the cyclic redundancy sequence 1 in the PTRS
  • the second subcarrier is used to transmit the base sequence in the PTRS
  • the third subcarrier is used to transmit the cyclic redundancy sequence 2 in the PTRS.
  • the PTRS includes sequentially arranged: a cyclic redundancy sequence 1 with a length of p1, a base sequence with a length of L, and a cyclic redundancy sequence 2 with a length of p2.
  • the cyclic redundancy sequence and the base sequence are only for convenience of description, and should not limit the solution.
  • the length L of the second subcarrier in different subcarrier blocks can be constrained (the length L of the second subcarrier in the subcarrier block can also be understood as: the length of the base sequence in PTRS length L) as equal as possible.
  • L m N/M
  • L m floor(N/M)
  • L m ceil(N/M)+1
  • L m ceil(N/M)-1
  • L m is the rounded integer of N/M.
  • floor rounded down, ceil is rounded up.
  • the value of m is a partial integer or all integers from 1 to M. That is, among the M subcarrier blocks, the lengths of the second subcarriers in all the subcarrier blocks may satisfy the formula, or the lengths of the second subcarriers in a part of the subcarrier blocks may satisfy the formula.
  • the difference in the length L of the second subcarriers in different subcarrier blocks may be constrained to be less than or equal to 1.
  • the length L of the second subcarriers in different subcarrier blocks is the same as possible.
  • the cycle characteristic is better, and the demodulation performance can be further improved.
  • the length Q of different subcarrier blocks may be constrained to be as equal as possible.
  • the length Q of each subcarrier block can be made equal by adjusting the value of the length p1 of the first subcarrier and/or the length p2 of the third subcarrier in the subcarrier block.
  • m is a partial integer or all integers from 1 to M. That is, among the M subcarrier blocks, the difference between the length of the first subcarrier and the length of the third subcarrier in all or part of the subcarrier blocks may be less than or equal to 1. Redundancy on both sides of a subcarrier block is as equal as possible, which can improve phase noise estimation performance and further improve demodulation performance.
  • the length p1 is as equal as possible, and the length p2 is also as equal as possible.
  • the following method when the first sequence is mapped to M subcarrier blocks, the following method may be used:
  • the first sequence is sequentially mapped to the second subcarrier in the M subcarrier blocks.
  • the signals mapped on the second subcarriers in the M subcarrier blocks are continuous in the first sequence.
  • the first sequence When the first sequence is sequentially mapped to the second subcarrier in M subcarrier blocks, for example, the first sequence can be mapped to M (continuous) on the second subcarrier in the subcarrier block; or, the first sequence may be mapped to the second subcarrier in the M (continuous) subcarrier blocks in the order of increasing subcarrier index and decreasing signal index superior.
  • the signals in the first sequence are mapped to the first subcarrier and the third subcarrier in the M subcarrier blocks in such a manner that the signals mapped on each subcarrier block are cyclically continuous.
  • Cyclically continuous it can be understood that when the signal mapped on a certain subcarrier a is the last signal in the first sequence, the next subcarrier of the subcarrier a is mapped to the first signal in the subcarrier ( This method is to perform mapping in the order of increasing subcarrier index and increasing signal index).
  • the signal mapped on the first subcarrier in the second subcarrier is the zth signal in the first sequence (referred to as signal S 1 ), and the last signal in the second subcarrier
  • the signal mapped on one subcarrier is the xth signal in the first sequence (referred to as signal SL ).
  • z is smaller than x.
  • the signal mapped on the jth subcarrier before the first subcarrier in the second subcarrier is the first The (zj)th signal in the sequence; if zj is less than or equal to 0, replace zj with z-j+N.
  • the signal mapped on the jth subcarrier after the last subcarrier in the second subcarrier is the (x+j)th signal of the first sequence signals; if x+j is greater than N, replace x+j with x+jN.
  • the number of subcarrier blocks M 3.
  • the length p2 2.
  • the 15 signals are divided into 3 parts, the first part is signal 0 to signal 4, the second part is signal 5 to signal 9, and the third part is signal 10 to signal 14. These 3 shares are mapped to the second subcarrier in the 3 subcarrier blocks in the order of increasing subcarrier index and increasing signal index.
  • the five signals mapped on the second subcarrier in subcarrier block 1 are the first to fifth signals in the first sequence, namely signal 0 to signal 4; the second subcarrier in subcarrier block 2
  • the 5 signals mapped on are the 6th to 10th signals in the first sequence, that is, signal 5 to signal 9; the 5 signals mapped on the second subcarrier in subcarrier block 3 are respectively The 11th to 15th signals in a sequence, that is, signal 10 to signal 14.
  • subcarrier block 1 Take subcarrier block 1 as an example for illustration:
  • the signal mapped on the jth subcarrier before the first subcarrier in the second subcarrier is the first The (z+j)th signal in the sequence, if z+j is greater than N, replace z+j with z+jN.
  • the signal mapped on the jth subcarrier after the last subcarrier in the second subcarrier is the (xj)th signal of the first sequence , if zj is less than or equal to 0, replace xj with x-j+N.
  • the influence of phase noise on the received signal of each subcarrier is introduced above, and the received signal on the subcarrier transmitting the base sequence can satisfy the following formula:
  • the S matrix is a matrix formed by a cyclic shift of a base sequence (second subcarrier).
  • E -n E -n+N .
  • Residual ICI is ICI caused by E other than E -2 , E -1 , E 0 , E 1 , E 2 .
  • E 12 , E -1 , E 0 , E 1 , E 2 can be estimated.
  • any subcarrier for example, S13, or S14, or S2, etc.
  • the coefficients of the ICI are the same at the locations of these signals.
  • the sending signal corresponding to the same position at the sending end is S 0 , but r 0 will be affected by 5 signals, the former signal is S 14 , and the latter signal is S 1 .
  • r 0 S 13 *E ⁇ 2 +S 14 *E ⁇ 1 +S 0 *E 0 +S 1 *E 1 +S 2 *E 2 .
  • the sent signal corresponding to r 1 is S 1 .
  • r 1 S 14 *E ⁇ 2 +S 0 *E ⁇ 1 +S 1 *E 0 +S 2 *E 1 +S 3 *E 2 .
  • a received signal r is equal to the product sum of the first vector and the [E_(positional relationship)] vector.
  • the first vector is a vector composed of one or more transmitted signals before the location of the received signal, the transmitted signal at the location of the received signal, and one or more signals behind the location of the received signal.
  • resource scheduling it is usually scheduled according to resource blocks.
  • the value of Q is an integer multiple of the number of subcarriers in a resource block RB, which is easy to schedule.
  • the value of Q m is determined by the value of p1 m or p2 m , and it can also be understood that the value of Q m is determined based on the value of p1 m and/or p2 m .
  • m is a partial integer or all integers from 1 to M.
  • values of p1 m and p2 m are associated with values of at least one of Q m , M, and N.
  • m is a partial integer or all integers from 1 to M.
  • the values of p1 m and p2 m are associated with the value range of Q m .
  • the values of p1 m and p2 m are associated with the value range of N.
  • One or more parameters among the parameters such as p1 m , p2 m , Q m , M, L m , and N mentioned in this document may be specified by the protocol, or configured by the network device to the terminal device.
  • the network device configures parameters for the terminal device, only a part of the parameters can be configured, and the terminal device can obtain other parameters according to the correlation characteristics between the parameters.
  • the network device does not need to configure all the parameters, which can reduce the overhead.
  • the base station After assigning one or two parameters, the base station can know other parameters, which can reduce overhead.
  • step 402 may also be divided into two steps: step 402a and step 402b.
  • Step 402a the first device maps the first sequence to M reference signals.
  • Step 402b The first device maps the M reference signals to M subcarriers for transmitting the reference signals. Specifically, the mth reference signal is mapped to the mth subcarrier used for transmitting the reference signal.
  • mapping the first sequence to M reference signals is similar to the process of mapping the first sequence to M subcarriers used to transmit reference signals introduced in step 402.
  • the "Subcarriers used to transmit reference signals" can be replaced with "reference signals”.
  • the m th reference signal includes Q m signals, where Q m is an integer greater than 2.
  • the value of m is 1 to M.
  • the number of signals included in different reference signals (the length of the reference signal) may be the same or different.
  • the difference in the number of signals included in different reference signals is less than or equal to 1.
  • the difference between Q m and Q m+1 is less than or equal to 1.
  • the difference between Q m and Q m+2 is less than or equal to 1.
  • the length N of the first sequence is greater than the number of signals included in any reference signal, and N is smaller than the sum of the numbers of signals included in the M reference signals. That is, N is greater than Q m , and N is less than the sum of Q 1 , Q 2 , . . . , Q m-1 , and Q m .
  • multiple (for example, Q) consecutive signals in the first sequence may be mapped to one reference signal.
  • a plurality of cyclically continuous signals (for example, Q) in the first sequence may be mapped to one reference signal.
  • the first sequence When the first sequence is mapped to M (for example, M consecutive) reference signals, the first sequence may be mapped to in the order in which the position index in the reference signal increases and the signal index in the first sequence increases. M (for example, M consecutive) reference signals. The first sequence may also be mapped to M (for example, M consecutive) reference signals in an order of increasing position index in the reference signal and decreasing signal index in the first sequence.
  • the multiple (for example i) signals at the back position in the mth reference signal are the same as the multiple (for example i) signals at the front position in the m+1th reference signal, m takes a value from 1 to M. i is an integer greater than or equal to 1.
  • the multiple (for example, i) signals at the rear of the mth reference signal are the same as the multiple (for example, i) signals at the front of the m+1th reference signal
  • multiple (for example, i) signals at a later position in the Mth (last) reference signal are the same as multiple (for example, i) signals at an earlier position in the first reference signal. It can also be understood as: multiple signals at a later position in the m th reference signal are the same as multiple signals at an earlier position in the mod(m, M)+1 th reference signal. Wherein, mod(m, M) is the remainder of dividing m by M.
  • the mth reference signal includes, arranged in sequence: a cyclic redundancy sequence 1 with a length of p1 m , a base sequence with a length of L m , and a cyclic redundancy sequence 2 with a length of p2 m .
  • the length L of base sequences in different reference signals may be constrained to be as equal as possible.
  • L m N/M
  • the difference in the length L of base sequences in different reference signals may be constrained to be less than or equal to 1.
  • the lengths Q of different reference signals may be constrained to be as equal as possible.
  • the length Q of each reference signal can be made equal by adjusting the value of the length p1 of the cyclic redundancy sequence 1 and/or the length p2 of the cyclic redundancy sequence 2 in the reference signal.
  • the length p1 is as equal as possible, and the length p2 is also as equal as possible.
  • mapping the first sequence to M reference signals when mapping the first sequence to M reference signals, the following method may be used:
  • the first sequence is sequentially mapped to the base sequences in the M reference signals.
  • the signals mapped on the base sequences among the M reference signals are continuous in the first sequence.
  • the first sequence is sequentially mapped to the base sequences in the M reference signals, for example, the first sequence is mapped to the M on the base sequence in (consecutive) reference signals; or, according to the order in which the position index in the base sequence increases and the signal index in the first sequence decreases, the first sequence is mapped to M (consecutive) reference on the base sequence in the signal.
  • the signals in the first sequence are mapped to the cyclic redundancy sequence 1 and the cyclic redundancy sequence 2 among the M reference signals in such a manner that the signals mapped on each reference signal are cyclically continuous.
  • the signal mapped to the first position in the base sequence is the zth signal in the first sequence (called signal S 1 ), and the signal mapped to the last position in the base sequence is The signal is the xth signal in the first sequence (referred to as signal SL ).
  • the first sequence is mapped to the base sequence in M (continuous) reference signals in the order of increasing position index in the base sequence and increasing signal index in the first sequence, then z less than x.
  • the signal mapped to the j-th position before the first position in the base sequence is the j-th signal in the first sequence (zj) signals; if zj is less than or equal to 0, replace zj with z-j+N.
  • the signal mapped to the jth position after the last position in the base sequence is the (x+j)th signal of the first sequence; If x+j is greater than N, replace x+j with x+jN.
  • the signal mapped to the j-th position before the first position in the base sequence is the j-th signal in the first sequence (z+j) signals, if z+j is greater than N, replace z+j with z+jN.
  • the signal mapped at the jth position after the last position in the base sequence is the (xj)th signal of the first sequence, if zj If it is less than or equal to 0, replace xj with x-j+N.
  • Step 403 the first device sends the mapped signal on each subcarrier.
  • the present application jointly designs signals transmitted on multiple reference signal subcarrier blocks, and forms a scheme of cyclic redundancy characteristics in multiple reference signal (eg, PTRS) subcarrier blocks.
  • the length of the first sequence is longer, so as to construct a larger cyclic shift matrix than the prior art for estimating the ICI coefficient generated by the phase noise, which can improve the ICI of the inter-subcarrier interference coefficient generated by the phase noise Estimation accuracy, thereby improving data demodulation performance.
  • Step 41 The sending end generates a PTRS base sequence.
  • Step 42 The sending end generates a PTRS based on the PTRS base sequence.
  • steps 41 and 42 reference may be made to the introduction at step 402a above.
  • the process of step 41 may include: sequentially mapping the first sequence to base sequences in the M reference signals.
  • the signals mapped on the base sequences among the M reference signals are continuous in the first sequence.
  • the first sequence is sequentially mapped to the base sequences in the M reference signals, for example, the first sequence is mapped to the M on the base sequence in (consecutive) reference signals; or, according to the order in which the position index in the base sequence increases and the signal index in the first sequence decreases, the first sequence is mapped to M (consecutive) reference on the base sequence in the signal.
  • step 42 may include: mapping the signal in the first sequence to the cyclic redundancy sequence 1 among the M reference signals and the cyclic redundancy On sequence 2.
  • the signal mapped to the first position in the base sequence is the zth signal in the first sequence (called signal S 1 ), and the signal mapped to the last position in the base sequence is The signal is the xth signal in the first sequence (referred to as signal SL ).
  • the first sequence is mapped to the base sequence in M (continuous) reference signals in the order of increasing position index in the base sequence and increasing signal index in the first sequence, then z less than x.
  • the signal mapped to the j-th position before the first position in the base sequence is the j-th signal in the first sequence (zj) signals; if zj is less than or equal to 0, replace zj with z-j+N.
  • the signal mapped to the jth position after the last position in the base sequence is the (x+j)th signal of the first sequence; If x+j is greater than N, replace x+j with x+jN.
  • the signal mapped to the j-th position before the first position in the base sequence is the j-th signal in the first sequence (z+j) signals, if z+j is greater than N, replace z+j with z+jN.
  • the signal mapped at the jth position after the last position in the base sequence is the (xj)th signal of the first sequence, if zj If it is less than or equal to 0, replace xj with x-j+N.
  • Step 43 The sending end generates an OFDM signal based on the PTRS.
  • the PTRS is placed on the corresponding OFDM subcarrier, for example, the PTRS and data are combined to generate an OFDM signal.
  • Step 44 The sending end sends the OFDM signal.
  • Step 45 The receiving end receives the OFDM signal.
  • Step 46 The receiving end equalizes the OFDM signal, that is, removes the influence of the channel. This step is optional.
  • Step 47 The receiving end estimates the influence of phase noise based on the PTRS, and demodulates the OFDM signal.
  • the ICI coefficient caused by the phase noise is estimated through the PTRS, so as to demodulate the data transmitted by the OFDM signal.
  • the receiving end needs to know the information of the reference signal (such as PTRS), including but not limited to: the position and number of subcarriers, the transmitted reference signal (such as PTRS) itself and so on. In this way, the receiver can estimate the impact of phase noise based on the PTRS.
  • the sending end may be a terminal device, and the receiving end may be a network device; or, the sending end may be a network device, and the receiving end may be a terminal device.
  • PTRS information can be configured to terminal devices through network devices, for example, through downlink control information (DCI), media access control (media access control, MAC), radio resource control (radio resource control, RRC) signaling to configure.
  • DCI downlink control information
  • media access control media access control
  • MAC radio resource control
  • RRC radio resource control
  • FIG. 7 a comparative schematic diagram of data demodulation performance is provided.
  • the thick line represents a high-complexity demodulation scheme
  • the thin line represents a low-complexity demodulation scheme. It can be seen that the performance of the present application is better than that of the prior art (traditional block scheme) no matter in the high-complexity or low-complexity demodulation scheme.
  • the method in the embodiment of the present application is introduced above, and the device in the embodiment of the present application will be introduced in the following.
  • the method and the device are based on the same technical concept. Since the principles of the method and the device to solve problems are similar, the implementation of the device and the method can be referred to each other, and the repetition will not be repeated.
  • the embodiment of the present application may divide the device into functional modules according to the above method example, for example, each function may be divided into each functional module, or two or more functions may be integrated into one module.
  • These modules can be implemented not only in the form of hardware, but also in the form of software function modules. It should be noted that the division of the modules in the embodiment of the present application is schematic, and is only a logical function division, and there may be another division manner during specific implementation.
  • the device 800 may include: a processing module 810, and optionally, a receiving module 820a, a sending module 820b, and a storage module 830 .
  • the processing module 810 may be connected to the storage module 830 and the receiving module 820a and the sending module 820b respectively, and the storage module 830 may also be connected to the receiving module 820a and the sending module 820b.
  • the above-mentioned receiving module 820a and sending module 820b may also be integrated together and defined as a transceiver module.
  • the apparatus 800 may be the first device, or may be a chip or a functional unit applied in the first device.
  • the apparatus 800 has any function of the first device in the above-mentioned method, for example, the apparatus 800 can execute the steps performed by the first device in the methods of FIG. 4a and FIG. 4b above.
  • the receiving module 820a may perform the receiving action performed by the first device in the above method embodiments.
  • the sending module 820b may execute the sending action performed by the first device in the above method embodiment.
  • the processing module 810 may perform actions other than the sending action and the receiving action among the actions performed by the first device in the above method embodiments.
  • the processing module 810 is configured to map the first sequence to M subcarrier blocks used to transmit reference signals; wherein, the mth subcarrier block includes Q m subcarriers, and Q m is an integer greater than or equal to 2, m takes an integer from 1 to M, and the M is an integer greater than or equal to 2; the first sequence includes a plurality of signals, and the position in the mth subcarrier block is close to
  • the multiple signals mapped on the subsequent multiple consecutive sub-carriers are the same as the multiple signals mapped on the front multiple consecutive sub-carriers in the mod(m, M)+1th sub-carrier block; wherein, mod(m , M) is the remainder of m divided by M.
  • the sending module 820b is configured to send the mapped signal on each of the subcarriers.
  • the processing module 810 is specifically configured to: map the first sequence to M subcarrier blocks used to transmit reference signals in the order of increasing subcarrier index and increasing signal index; or, The first sequence is mapped to M subcarrier blocks used for transmitting reference signals in the order of increasing subcarrier index and decreasing signal index.
  • the receiving module 820a is configured to receive the first sequence sent by other devices.
  • the storage module 830 may store computer-executed instructions of the method executed by the first device, so that the processing module 810, the receiving module 820a, and the sending module 820b execute the method executed by the first device in the above examples.
  • the storage module 830 may include one or more memories, and the memories may be one or more devices in devices and circuits for storing programs or data.
  • the storage module may be a register, cache or RAM, etc., and the storage module may be integrated with the processing module.
  • the storage module can be ROM or other types of static storage devices that can store static information and instructions, and the storage module can be independent from the processing module.
  • the receiving module 820a and the sending module 820b may be input or output interfaces, pins or circuits, and the like.
  • the processing module 810 in FIG. 8 may be implemented by a processing circuit.
  • the receiving module 820a and the sending module 820b in FIG. 8 can be implemented through input and output interfaces. Alternatively, the input-output interface is divided into an input interface and an output interface, the input interface performs the function of the receiving module, and the output interface performs the function of the sending module.
  • the storage module 830 in FIG. 8 may be implemented by a storage medium.
  • the device applied to the first device according to the embodiment of the present application is described above, and possible product forms of the device applied to the first device are introduced below. It should be understood that any product in any form having the characteristics of the device applied to the first device described above in FIG. 8 falls within the scope of protection of the present application. It should also be understood that the following introduction is only an example, and the product form of the device applied to the first device in the embodiment of the present application should not be limited thereto.
  • the device can be realized by a general bus architecture.
  • FIG. 9 a schematic block diagram of a communication device 900 is provided.
  • the apparatus 900 may include a processor 910 , and optionally, a transceiver 920 and a memory 930 .
  • the transceiver 920 can be used to receive programs or instructions and transmit them to the processor 910, or the transceiver 920 can be used for the device 900 to communicate with other communication devices, such as interactive control signaling and/or service data etc.
  • the transceiver 920 may be a code and/or data read/write transceiver, or the transceiver 920 may be a signal transmission transceiver between the processor 910 and the transceiver 920 .
  • the processor 910 is electrically coupled to the memory 930 .
  • the apparatus 900 may be the first device, or may be a chip applied in the first device. It should be understood that the apparatus has any function of the first device in the above method, for example, the apparatus 900 can execute the various steps performed by the first device in the methods of FIG. 4a and FIG. 4b above.
  • the memory 930 is used to store computer programs; the processor 910 can be used to call the computer programs or instructions stored in the memory 930 to execute the method performed by the first device in the above examples, or to use the The transceiver 920 performs the method performed by the first device in the above example.
  • the device may be implemented by a general-purpose processor (a general-purpose processor may also be referred to as a chip or system-on-a-chip).
  • the general processor implementing the apparatus applied to the first device includes: a processing circuit (the processing circuit may also be referred to as a processor).
  • the device 900 further includes an input-output interface and a storage medium (storage medium may also be referred to as a memory) that are internally connected and communicated with the processing circuit, and the storage medium is used to store instructions executed by the processing circuit to execute the above-mentioned The method performed by the first device in the example.
  • the device of the embodiment of the present application can also be realized using the following: one or more FPGAs (Field Programmable Gate Arrays), PLDs (Programmable Logic Devices), controllers, state machines, Any combination of gate logic, discrete hardware components, any other suitable circuitry, or circuitry capable of performing the various functions described throughout this application.
  • FPGAs Field Programmable Gate Arrays
  • PLDs Programmable Logic Devices
  • controllers state machines, Any combination of gate logic, discrete hardware components, any other suitable circuitry, or circuitry capable of performing the various functions described throughout this application.
  • the embodiment of the present application also provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a computer, the computer can be used to execute the above method for sending a signal.
  • the computer program includes instructions for implementing the above-mentioned method for sending a signal.
  • the embodiment of the present application also provides a computer program product, including: computer program code, when the computer program code is run on the computer, the computer can execute the signal sending method provided above.
  • processors mentioned in the embodiment of the present application may be a central processing unit (central processing unit, CPU), a baseband processor, and the baseband processor and the CPU may be integrated or separated, or may be a network processor (network processing unit).
  • processor NP
  • processors may further include hardware chips or other general-purpose processors.
  • the aforementioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof.
  • the above PLD can be complex programmable logic device (complex programmable logic device, CPLD), field programmable logic gate array (field-programmable gate array, FPGA), general array logic (generic array logic, GAL) and other programmable logic devices , discrete gate or transistor logic devices, discrete hardware components, etc., or any combination thereof.
  • CPLD complex programmable logic device
  • FPGA field programmable logic gate array
  • GAL general array logic
  • GAL generator array logic
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the memory mentioned in the embodiments of the present application may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories.
  • the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electronically programmable Erase Programmable Read-Only Memory (Electrically EPROM, EEPROM) or Flash.
  • the volatile memory can be Random Access Memory (RAM), which acts as external cache memory.
  • RAM Static Random Access Memory
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • Synchronous Dynamic Random Access Memory Synchronous Dynamic Random Access Memory
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM DDR SDRAM
  • enhanced SDRAM Enhanced SDRAM, ESDRAM
  • Synch link DRAM SLDRAM
  • Direct Memory Bus Random Access Memory Direct Rambus RAM, DR RAM
  • the transceiver mentioned in the embodiment of the present application may include a separate transmitter and/or a separate receiver, or the transmitter and the receiver may be integrated. Transceivers can operate under the direction of corresponding processors.
  • the transmitter may correspond to the transmitter in the physical device, and the receiver may correspond to the receiver in the physical device.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of software products, and the computer software products are stored in a storage medium
  • several instructions are included to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

本申请涉及通信技术领域，提供了一种通信方法及装置，用以提高数据解调性能。将第一序列包括的多个信号映射至M个用于传输参考信号的子载波块上；其中，第m个所述子载波块包括Q m个子载波；所述第m个子载波块中位置靠后的多个连续子载波上所映射的多个信号与第mod(m，M)+1个子载波块中位置靠前的多个连续子载波所映射的多个信号相同。本申请联合设计多个参考信号子载波块上传输的信号，在多个参考信号(例如PTRS)子载波块中构成循环冗余特性。第一序列长度较长，从而构建一个相对于现有技术更大的循环移位矩阵用于对由相噪产生的ICI系数的估计，可以提升对ICI系数的估计精度，进而提升数据解调性能。

Description

一种通信方法及装置
相关申请的交叉引用
本申请要求在2021年06月17日提交中国专利局、申请号为202110670099.6、申请名称为“一种通信方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信领域，尤其涉及一种通信方法及装置。
背景技术
高频(例如6GHz以上频段)因其丰富的频段资源，成为业界用于解决日益增长的通信需求而研究和开发的热点。其显著特点除了包括大带宽、高集成天线阵列，以实现高吞吐量外，同时还包括严重的中射频失真问题。
以相位噪声为例，随着频段的增加，相位噪声功率谱密度越高，对接收信号影响越大，即工作频率越高，相位噪声越大。另外，为了提高传输的有效性，往往会使用高阶调制，如16正交幅度调制(quadrature amplitude modulation，QAM)、64QAM、256QAM等，高阶调制往往容易受到相位噪声的影响。再另外，同一个频段，不同的调制阶数的数据的解调性能，也会受到相位噪声的影响，调制阶数越高，对相位噪声越敏感。类似的，同一调制阶数下，不同的码率的数据的解调性能，也会受到相位噪声的影响。
在高频或相位噪声较严重的系统中，如何提高数据解调性能，是亟待解决的问题。
发明内容
本申请实施例提供一种通信方法及装置，用以提高数据解调性能。
第一方面，提供了一种通信方法，将第一序列包括的多个信号映射至M个用于传输参考信号的子载波块上；其中，第m个所述子载波块包括Q m个子载波，Q m为大于或等于2的整数，m取遍1至M中的整数，M为大于或等于2的整数；所述第一序列包括多个信号，所述第m个子载波块中位置靠后的多个连续子载波上所映射的多个信号与第mod(m，M)+1个子载波块中位置靠前的多个连续子载波所映射的多个信号相同；其中，mod(m，M)为m除以M的余数。然后，在各个所述子载波块上发送所映射的信号。
可选的，所述参考信号可用于相位跟踪，或者，所述参考信号可用于估计相位噪声。所述参考信号包括但不限于相位跟踪参考信号(phase tracking reference signal，PTRS)。
本申请联合设计多个参考信号子载波块上传输的信号，在多个参考信号(例如PTRS)子载波块中构成循环冗余特性。第一序列长度较长，从而构建一个相对于现有技术更大的循环移位矩阵用于对由相噪产生的ICI系数的估计，可以提升对ICI系数的估计精度，进而提升数据解调性能。
在一种可能的实现中，任一子载波块上所映射的多个信号不同。
在一种可能的实现中，在将第一序列映射至M个用于传输参考信号的子载波块上时， 可以是按照子载波索引递增，信号索引递增的顺序，将所述第一序列映射至M个用于传输参考信号的子载波块上；或者，按照子载波索引递增，信号索引递减的顺序，将所述第一序列映射至M个用于传输参考信号的子载波块上。以实现所述第m个子载波块中位置靠后的多个连续子载波上所映射的多个信号与第mod(m，M)+1个子载波块中位置靠前的多个连续子载波所映射的多个信号相同。
在一种可能的实现中，第m个子载波块包括：依次排列的长度为p1 m的第一子载波、长度为L m的第二子载，长度为p2 m的第三子载波；其中，M个子载波块中的第二子载波上所映射的信号在所述第一序列中连续。
可以先将第一序列依次映射至M个子载波块中的第二子载波上。然后，按照每一个子载波块上所映射的信号是循环连续的方式，将第一序列中的信号映射至M个子载波块中的第一子载波上和第三子载波上，以实现所述第m个子载波块中位置靠后的多个连续子载波上所映射的多个信号与第mod(m，M)+1个子载波块中位置靠前的多个连续子载波所映射的多个信号相同。
在一种可能的实现中，M个子载波块中分别包括的第二子载波的长度之和为所述第一序列的长度。即L 1+L 2+…+L M-1+L M＝N，N为所述第一序列的长度。
在一种可能的实现中，所述L m满足：L m＝N/M，或，L m＝floor(N/M)，或L m＝floor(N/M)+1，或L m＝ceil(N/M)，或L m＝ceil(N/M)-1。其中，floor为向下取整，ceil为向上取整，N为所述第一序列的长度。所述m取值为1至M中的部分整数或者全部整数。也就是M个子载波块中，可以是全部的子载波块中的第二子载波的长度满足该公式，也可以是一部分子载波块中的第二子载波的长度满足该公式。不同的子载波块中的第二子载波的长度L尽量相同。所有子载波块中的第二子载波的长度相同时，循环特性较好，可以进一步提升解调性能。
在一种可能的实现中，所述p1 m与所述p2 m的差值小于或等于1，m取值为1至M中的部分整数或者全部整数。也就是M个子载波块中，可以是全部的或一部分子载波块中的第一子载波的长度和第三子载波的长度之差小于或等于1。一个子载波块的两边的冗余尽量相等，可以提高相噪估计性能，进一步地提升解调性能。
在一种可能的实现中，所述Q m的取值基于p1 m和/或p2 m的取值确定。m取值为1至M中的部分整数或者全部整数。
在一种可能的实现中，p1 m和p2 m的取值与Q m、M、N中的至少之一关联。m取值为1至M中的部分整数或者全部整数。网络设备在向终端设备配置参数时，可以只配置一部分参数，终端设备可以根据参数之间的关联特性，得到其他的参数，网络设备无需配置全部的参数，可以降低开销。基站分配一两个参数，就可以知道其他的参数，可以降低开销。
在一种可能的实现中，所述Q m＝a*q，其中，q为一个资源块RB的子载波数量，a为大于或等于1的整数，m取值为1至M中的部分整数或者全部整数。在进行资源调度时，通常是按照资源块进行调度的，本申请中Q的取值为一个资源块RB的子载波数量的整数倍，容易调度。
在一种可能的实现中，所述第一序列可为以下任一序列：ZC序列，正交幅度调制QAM序列，互补序列，伪随机序列。ZC序列循环移位是正交的，因此第一序列的矩阵的每一列是正交的，可以更好的估计出由相噪产生的子载波间干扰系数ICI系数。时域/频域QAM序列实现简单，可以和数据QAM调制共用信号调制生成器。伪随机序列和现有蜂窝通信 系统中的序列生成方法一样，可以共用生成器。互补序列实现简单。
第二方面，提供了一种通信装置，所述装置具有实现上述第一方面及第一方面任一可能的实现中的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的功能模块。
示例的，所述装置包括：处理模块，用于将第一序列映射至M个用于传输参考信号的子载波块上；其中，第m个所述子载波块包括Q m个子载波，Q m为大于或等于2的整数，m取遍1至M中的整数，所述M为大于或等于2的整数；所述第一序列包括多个信号，所述第m个子载波块中位置靠后的多个连续子载波上所映射的多个信号与第mod(m，M)+1个子载波块中位置靠前的多个连续子载波所映射的多个信号相同；其中，mod(m，M)为m除以M的余数；发送模块，用于在各个所述子载波上发送所映射的信号。
一种示例中，所述处理模块，可以用于按照子载波索引递增，信号索引递增的顺将所述第一序列映射至M个用于传输参考信号的子载波块上；或者也可以用于按照子载波索引递增，信号索引递减的顺序，将所述第一序列映射至M个用于传输参考信号的子载波块上。
第三方面，提供了一种通信装置，包括处理器，可选的，还包括存储器；所述处理器和所述存储器耦合；所述存储器存储计算机程序或指令；所述处理器，用于执行所述存储器中的部分或者全部计算机程序或指令，当所述部分或者全部计算机程序或指令被执行时，用于实现上述第一方面及第一方面任一可能的实现的方法中的功能。
在一种可能的实现中，所述装置还可以包括收发器，所述收发器，用于发送所述处理器处理后的信号，或者接收输入给所述处理器的信号。所述收发器可以执行上述第一方面及第一方面任一可能的实现中执行的发送动作或接收动作。
第四方面，本申请提供了一种芯片系统，该芯片系统包括一个或多个处理器(也可以称为处理电路)，所述处理器与存储器(也可以称为存储介质)之间电耦合；所述存储器可以位于所述芯片系统中，也可以不位于所述芯片系统中；所述存储器，用于存储计算机程序或指令；所述处理器，用于执行所述存储器中的部分或者全部计算机程序或指令，当所述部分或者全部计算机程序或指令被执行时，用于实现上述第一方面及第一方面任一可能的实现的方法中的功能。
在一种可能的实现中，所述芯片系统还可以包括输入输出接口(也可以称为通信接口)，所述输入输出接口，用于输出所述处理器处理后的信号，或者接收输入给所述处理器的信号。所述输入输出接口可以执行第一方面及第一方面任一可能的实现中执行的发送动作或接收动作。具体的，输出接口可执行发送动作，输入接口可执行接收动作。
在一种可能的实现中，该芯片系统，可以由芯片构成，也可以包括芯片和其他分立器件。
第五方面，提供了一种计算机可读存储介质，用于存储计算机程序，所述计算机程序包括用于实现上述第一方面及第一方面任一可能的实现中的功能的指令。
第六方面，提供了一种计算机程序产品，所述计算机程序产品包括计算机程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行上述第一方面及第一方面任一可能的实现中执行的方法。
上述第二方面至第六方面的技术效果可以参照第一方面中的相关描述，重复之处不再赘述。
附图说明
图1a为本申请实施例中提供的一种相位噪声对频域接收信号的影响示意图；
图1b为本申请实施例中提供的一种相位噪声对频域接收信号的影响示意图；
图1c为本申请实施例中提供的一种相位噪声对频域接收信号的影响示意图；
图2a为本申请实施例中提供的一种通信系统示意图；
图2b为本申请实施例中提供的一种通信系统示意图；
图3为本申请实施例中提供的一种子载波中传输PTRS的示意图；
图4a为本申请实施例中提供的一种传输信号的方法过程示意图；
图4b为本申请实施例中提供的一种传输信号的方法过程示意图；
图5a为本申请实施例中提供的一种序列示意图；
图5b为本申请实施例中提供的一种序列示意图；
图5c为本申请实施例中提供的一种序列示意图；
图6为本申请实施例中提供的一种信号映射示意图；
图7为本申请实施例中提供的一种数据解调性能示意图；
图8为本申请实施例中提供的一种通信装置结构示意图；
图9为本申请实施例中提供的一种通信装置结构示意图。
具体实施方式
为便于理解本申请实施例，以下对本申请实施例的部分用语进行解释说明，以便于本领域技术人员理解。
1)、网络设备，具有能够为终端设备提供随机接入功能的设备或可设置于该设备的芯片，该设备包括但不限于：演进型节点B(evolved Node B，eNB)、无线网络控制器(radio network controller，RNC)、节点B(Node B，NB)、基站控制器(base station controller，BSC)、基站收发台(base transceiver station，BTS)、家庭基站(例如，home evolved NodeB，或home Node B，HNB)、基带单元(baseband unit，BBU)，无线保真(wireless fidelity，WIFI)系统中的接入点(access point，AP)、无线中继节点、无线回传节点、传输点(transmission and reception point，TRP或者transmission point，TP)等，还可以为5G，如，NR，系统中的gNB，或，传输点(TRP或TP)，5G系统中的基站的一个或一组(包括多个天线面板)天线面板，或者，还可以为构成gNB或传输点的网络节点，如基带单元(BBU)，或，分布式单元(DU，distributed unit)等。
2)、终端设备，又称之为用户设备(user equipment，UE)、移动台(mobile station，MS)、移动终端(mobile terminal，MT)、终端等，是一种向用户提供语音和/或数据连通性的设备。例如，终端设备包括具有无线连接功能的手持式设备、车载设备等。目前，终端设备可以是：手机(mobile phone)、平板电脑、笔记本电脑、掌上电脑、移动互联网设备(mobile internet device，MID)、可穿戴设备，虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、工业控制(industrial control)中的无线终端(例如，传感器等)、无人驾驶(self-driving)中的无线终端、远程手术(remote medical surgery)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端，或智慧家庭(smart home)中的无线 终端，或具有车与车(Vehicle-to-Vehicle，V2V就)公共的无线终端等。
3)、相位噪声(phase noise)，是指系统(如各种射频器件)在各种噪声的作用下引起的系统输出信号相位的随机变化。相位噪声可以是在短时间内发生的信号相位上的波动。在这种情况下，由于相位噪声在时域中随机改变所接收的信号的相位，因此相位噪声可以中断信号的接收。相位噪声可以随机发生，然而，相位噪声可以在相邻时间样本之间示出某个相关性，这将导致频域中的公共相位误差(common phase error，CPE)和子载波间干扰(inter sub-carrier interference，ICI)。当相位噪声(后续将相位噪声简写为相噪)功率谱密度达到一定水平后，当调制阶数较高时，除了公共相位误差CPE，因相噪引起的子载波间干扰(inter sub-carrier interference，ICI)也不可忽略。图1a、图1b和图1c介绍了不同相位噪声对频域接收信号的影响，图1a为无相噪的影响；图1b为弱相噪的影响，图1c为强相噪的影响。随着频段的增加，相位噪声功率谱密度越高，可见对接收信号影响越大。
假设一个正交频分复用(orthogonal frequency division multiplexing，OFDM)时域信号上的相位噪声为：θ n，其中n＝0，...，N c-1，其中，N c为OFDM逆快速傅里叶变换(inverse fast Fourier transform，IFFT)长度，也就是子载波个数。
对θ n做N c点的离散傅里叶变换(discrete fourier transform，DFT)和/或快速傅里叶变换(fast fourier transform，FFT)，得到其频域响应E n，其中，n＝0，...，N c-1。进而该相噪对OFDM频域信号(各个子载波)的影响可以表示为：
Figure PCTCN2022096686-appb-000001
其中，R i为第i个子载波上的接收信号，S i为第i个子载波上的发射信号，
Figure PCTCN2022096686-appb-000002
mod为取余操作，k可以指代上述公式中的i-j。E 0称为公共相位误差CPE，其他E(例如E1、E2)称为子载波间干扰系数，其他E会给i子载波的接收信号带来其它子载波的信号的干扰，也就是子载波间干扰ICI。本申请中，将公共相位误差CPE和子载波间干扰ICI统一称为相噪ICI系数。
为便于理解本申请实施例的技术方案，下面将对本申请实施例提供的系统架构进行简要说明。可理解的，本申请实施例描述的系统架构是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定。
本申请实施例的技术方案可以应用于各种通信系统，例如：卫星通信系统、传统的移动通信系统。其中，所述卫星通信系统可以与传统的移动通信系统(即地面通信系统)相融合。通信系统例如：无线局域网(wireless local area network，WLAN)通信系统，长期演进(long term evolution，LTE)系统、LTE频分双工(frequency division duplex，FDD)系统、LTE时分双工(time division duplex，TDD)、通用移动通信系统(universal mobile telecommunication system，UMTS)、全球互联微波接入(worldwide interoperability for microwave access，WiMAX)通信系统、第五代(5th generation，5G)系统或新无线(new radio，NR)，第六代(6th generation，6G)系统，以及未来通信系统等。
如图2a所示的通信系统，包括网络设备和终端设备，例如包括单个或多个网络设备，和单个或多个终端设备。单个网络设备可以向单个或多个终端设备传输数据或控制信令(例如(a))。多个网络设备也可以同时为单个终端设备传输数据或控制信令(例如(b))。
通信系统中每个网络设备和每个终端设备之间的通信还可以用另一种形式来表示。如图2b所示：终端设备10包括：至少一个处理器101和至少一个收发器103，可选的，还可以包括至少一个存储器102。存储器102可以是独立存在，或者存储器102也可以和处理器101集成在一起，例如集成在一个芯片之内。其中，存储器102能够存储执行本申请实施例的技术方案的程序代码，并由处理器101来控制执行，被执行的各类计算机程序代 码也可被视为是处理器101的驱动程序。例如，处理器101用于执行存储器102中存储的计算机程序代码，从而实现本申请实施例中的技术方案。收发器103包括发射机1031、接收机1032和天线1033。接收机1032可以用于通过天线1033接收来自网络设备20的数据或控制信令，发射机1031可以用于通过天线1033向网络设备20发送信息。
网络设备20包括：至少一个处理器201和至少一个收发器203，可选的，还可以包括至少一个存储器202。存储器202可以是独立存在，或者存储器202也可以和处理器201集成在一起，例如集成在一个芯片之内。其中，存储器202能够存储执行本申请实施例的技术方案的程序代码，并由处理器201来控制执行，被执行的各类计算机程序代码也可被视为是处理器201的驱动程序。例如，处理器201用于执行存储器202中存储的计算机程序代码，从而实现本申请实施例中的技术方案。收发器203包括发射机2031、接收机2032和天线2033。发射机2031可以用于通过天线2033向终端设备10发送数据或控制信令，接收机2032可以用于通过天线2033接收终端设备10的信息。
为便于理解本申请实施例，接下来对本请的应用场景进行介绍，本申请实施例描述的系统架构以及业务场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
网络设备和终端设备之间在进行无线通信时，为了减少或消除相位噪声对数据解调性能的影响，终端设备可以向网络设备送：网络设备已知的参考信号，例如相位跟踪参考信号(phase tracking reference signal，PTRS)。网络设备可以根据PTRS，对相位噪声进行估计，然后进行相应的相位补偿，以提高数据解调性能。PTRS在时域上的密度越高，相位噪声的估计越准确。
如图3所示，提供了一种子载波中传输PTRS的示意图，将用于传输PTRS的多个连续的子载波称为一个PTRS子载波块，例如图3中的PTRS块1、PTRS块2、PTRS块3。
一个PTRS包括依次排列的：长度为p1的循环冗余序列1(circular sequence part1)，长度为L的基序列(base sequence)，长度为p2的循环冗余序列2(circular sequence part2)。
相应的，一个PTRS子载波块包括依次排列的：长度为p1的第一子载波(第一子载波用于传输循环冗余序列1)，长度为L为第二子载波(第二子载波用于传输基序列)，长度为p2的第三子载波(第三子载波用于传输循环冗余序列2)。
PTRS的长度为Q，即PTRS中包括Q个信号，PTRS子载波块中包括Q个子载波，每个子载波上传输一个信号。可以理解的是Q＝L+p1+p2。
假设，基序列中的L个信号分别为信号S 1至S L。基序列前面的循环冗余序列1中的p1个信号分别为S L-p1+1至S L。基序列后面的循环冗余序列2中的p2个信号分别为S 1至S p2。
以p1＝p2＝2为例，信号S 1-S L所在的子载波的接收信号可以得到如下表达式：
Figure PCTCN2022096686-appb-000003
其中，
Figure PCTCN2022096686-appb-000004
残留的ICI为除E -2，E -1，E 0，E 1，E 2以外的E造成的ICI。
如果基序列为ZC(Zadoff–Chu)序列，由于ZC序列正交的特性，可以看出由于添加的循环冗余序列的作用，S矩阵的每一列都是正交的。因此，从接收信号r估计E -2，E -1，E 0，E 1，E 2的性能较好。
子载波传输多个PTRS时，每一个PTRS子载波块的循环冗余特性是相同的，是独立的，即图3中的PTRS块1、PTRS块2、PTRS块3中的相应位置上的信号是相同的。虽然多个PTRS子载波块均具有循环冗余特性，但实际上只在一个PTRS子载波块中构成循环冗余的特性。由于基序列的长度L较短，因此E -2，E -1，E 0，E 1，E 2(子载波间干扰系数ICI)的估计性能受限。
基于此，本申请提出了在多个参考信号(例如PTRS)子载波块中构成循环冗余特性的方案。本申请联合设计多个参考信号子载波块上传输的基序列，以及相应的循环冗余发送方案。序列长度较长，可以提升对由相噪产生的子载波间干扰系数ICI的估计精度，进而提升数据解调性能。
接下来将结合附图对方案进行详细介绍。附图中以虚线标识的特征或内容可理解为本申请实施例的可选操作或者可选结构。
图4a所示，提供了一种发送信号的方法过程示意图，包括以下步骤：
步骤401：第一设备获取第一序列。
第一设备可以是终端设备，也可以是网络设备。
第一设备可以是自己生成第一序列，也可以是从其它设备处获取第一序列。
第一序列的长度为N，即第一序列包括N个信号。所述第一序列用于生成参考信号，例如，所述参考信号为用于进行相位跟踪的参考信号，或者，所述参考信号为用于估计相位噪声的参考信号。所述参考信号包括但不限于为PTRS。
在一种示例a中，第一序列可为ZC(Zadoff–Chu)序列。
一种示例a1中，ZC序列满足以下公式：
S n＝exp(-j*π*u*(n+a)*(n+b)/N)；S n即为第一序列。
其中，exp是高等数学里以自然常数e为底的指数函数，n＝0，1，...，N-1；u，a，b为整数。u，a，b可以由网络设备配置给终端设备，也可以由终端设备根据小区ID、终端设备ID、PTRS所在子帧号、PTRS所在符号等参数计算得到。j为复数符号，即j＝√(-1)。
在一种可选的示例中，可以约束u和N的最大公倍数为1，也就是u和N互质。
在一种可选的示例中，可以约束第一序列的长度N为质数，示例性的，N＝7，11，13，17，19，23，29，31，37，41，43。
上述矩阵S n的特征根幅度相同，可以更好的估计由相噪产生的子载波间干扰系数ICI系数E。
第一示例a2中，第一序列为ZC(Zadoff–Chu)根序列的截断，这也属于ZC序列的一种情况。上文所述约束第一序列的长度N为质数所产生出来的ZC序列称之为根序列。在某些情况下，系统需要的序列长度不是质数，而是其他整数。例如，实际使用的序列长度需要与资源配置的长度相同，用于做信道估计所使用的低PAPR序列，则序列长度需要等于12的倍数。(5G/4G中协议定义的1个传输资源块Resource Block的长度为12)。因此，通常会对产生出的质数根序列进行截断，获得想要的序列长度。
截断方法可以为：长度N的根序列截取[1：K]个，或者长度N的根序列截取[N-K+1:N]个，或者长度N的根序列截取[A：A+K-1]个。A为正整数，A+K-1<＝N。
例如，实际中需要长度为48的ZC序列。会产生一个长度和48最接近的根序列，例如S n＝exp(-j*π*u*(n+a)*(n+b)/N)，N＝53。
然后选取1：48，或者按照如上规则选取其中的48个序列，产生实际使用的第一序列。
在一种示例b中，第一序列可为时域正交幅度调制QAM序列。
该第一序列可定义在时域，例如，第一序列包括的信号为时域的调制符号。例如，调制符号为标准BPSK信号，或标准BPSK按比例缩放后的信号，序列组合为2 N种。再例如，调制符号为pi/2BPSK信号，或pi/2BPSK按比例缩放后的信号，序列组合为2 N种。
再例如，调制符号为QPSK信号，或QPSK信号按比例缩放后的信号，序列组合为4 N种。
在多种序列组合中，通过N点傅里叶变换到频域，选择频域幅度响应较稳定的序列作为有效序列输出。以QPSK信号为例，本申请将4 N种序列组合分别通过N点傅里叶变换到频域后，选择频域幅度响应较稳定的序列作为有效序列输出。
然后，在多个有效序列中选择有效序列集合。例如按幅度方差值从小到大的顺序，选择前P组作为时域QPSK序列的有效序列集合，且N越大，选出来的序列越稳定。比如当序列长度为8时，所选择的时域有效序列集合可包含图5a、图5b、图5c中的序列，其对应的OFDM子载波频域序列为图5a、图5b、图5c中序列FFT后的序列。
然后，可以在有效序列集合中，选择某一序列作为第一序列。例如，终端设备选择哪个时域QAM序列作为第一序列，可以由网络设备配置给终端设备，也可以由终端设备根据小区ID、终端设备ID、PTRS所在子帧号、PTRS所在符号等至少一种参数计算得到。
在一种示例c中，所述第一序列也可以是频域QAM序列。
与时域QAM序列类似，该第一序列可定义在频域，例如，第一序列包括的信号为频域的调制符号。例如，调制符号为标准BPSK信号，或标准BPSK按比例缩放后的信号，序列组合为2 N种。再例如，调制符号为pi/2BPSK信号，或pi/2BPSK按比例缩放后的信号，序列组合为2 N种。再例如，调制符号为QPSK信号，或QPSK信号按比例缩放后的信号，序列组合为4 N种。
终端设备选择哪个频域QAM序列作为第一序列，可以由网络设备配置给终端设备，也可以由终端设备根据小区ID、终端设备ID、PTRS所在子帧号、PTRS所在符号等至少一种参数计算得到。
在一种示例d中，所述第一序列可以是互补序列。两个互补序列(complementary sequences，该现有技术，不再累述)分别记为S1和S2，S1和S2具有相同的长度，且均为N/2。将序列S1和S2拼接成一个新的序列[S1S2]，从而组成长度为N的第一序列。
例如，一对互补序列的例子，其中：
b A＝[1，1，1，1，-1，1，-1，-1，-1，1，1，-1，-1，1，1，-1，1，-1，-1，1]；
b B＝[1，1，1，1，-1，1，1，1，1，1，-1，-1，-1，1，-1，1，-1，1，1，-1]；
b A和b B进行DFT调制后相加，在频域上为互补序列。
例如，对b A和b B进行pi/2-BPSK调制，可得到：
Figure PCTCN2022096686-appb-000005
Figure PCTCN2022096686-appb-000006
其中，C为常数，j为复数符号，即j＝√(-1)。
终端设备选择哪个互补序列作为第一序列，可以由网络设备配置给终端设备，也可以由终端设备根据小区ID、终端设备ID、PTRS所在子帧号、PTRS所在符号等至少一种参数 计算得到。
在一种示例e中，所述第一序列可以是伪随机序列。
QPSK调制得到第一序列，第一序列如下所示：
Figure PCTCN2022096686-appb-000007
其中：
c(n)＝(x 1(n+N C)+x 2(n+N C))mod 2
x 1(n+31)＝(x 1(n+3)+x 1(n))mod 2
x 2(n+31)＝(x 2(n+3)+x 2(n+2)+x 2(n+1)+x 2(n))mod 2
其中，N C＝1600，x 1(0)＝1,x 1(n)＝0,n＝1,2,...,30，
Figure PCTCN2022096686-appb-000008
c init由小区ID、终端设备ID、PTRS所在子帧号、PTRS所在符号等至少一种参数确定。
上述序列仅为举例，第一序列还可以是其他序列，本申请中的第一序列包括但不限于上述所列举的序列。
不同的第一序列由于其自身带来的不同的特性，可适用于不同的应用场景。
例如，ZC序列循环移位是正交的，因此上述S矩阵的每一列是正交的，可以更好的估计出由相噪产生的子载波间干扰系数ICI系数。
例如，时域/频域QAM序列实现简单，可以和数据QAM调制共用信号调制生成器。
例如，伪随机序列和现有蜂窝通信系统中的序列生成方法一样，可以共用生成器。
例如，互补序列实现简单。
步骤402：第一设备将第一序列映射至M个用于传输参考信号的子载波块上。
例如，将第一序列映射至M个连续的用于传输参考信号的子载波块上时，相邻的用于传输参考信号的子载波块之间包括用于传输数据的子载波块。M可为大于或等于2的整数。
为了方便描述，后续将“用于传输参考信号的子载波块”简称为“子载波块”，将“用于传输参考信号的子载波”简称为“子载波”。
例如，第m个子载波块包括Q m个子载波，Q m为大于2的整数。所述m依次取遍1至M中的正整数。不同的子载波块包括的子载波的数量，可以相同，也可以不同。可选的，不同的子载波块包括的子载波的数量差值小于或等于1。例如，Q m与Q m+1的差值小于或等于1。再例如，Q m与Q m+2的差值小于或等于1。
第一序列的长度N大于任一子载波块包括的子载波的数量，且N小于M个子载波块包括的子载波的数量之和。即N大于Q m，且N小于Q 1、Q 2、…、Q m-1，Q m之和。
第一序列中的每个信号映射至一个子载波上时，针对任一子载波块，该子载波块上所映射的多个信号不同。
在一种示例中，可以将第一序列中连续多个(例如Q个)信号映射至一个子载波块(例如Q m个子载波)上。具体的，可以将第一序列中循环连续的多个信号(例如Q个)映射至一个子载波块(例如Q m个子载波)上。循环连续，可以理解为，当第一序列中的最后一个信号映射至某一子载波a上后，再将第一序列中的第一个信号映射至子载波a的下一个子载波上(该方式为按照子载波索引递增，信号索引递增的顺序进行映射)。或者，第 一序列中的第1个信号映射至某一子载波a上后，再将第一序列中的最后一个信号映射至子载波a的下一个子载波上(该方式为按照子载波索引递增，信号索引递减的顺序进行映射)。
在将第一序列映射至M个(例如M个连续的)子载波块上时：
一种示例中，可以按照子载波索引递增，信号索引递增的顺序，将所述第一序列映射至M个(例如M个连续的)子载波块上。
另一种示例中，也可以按照子载波索引递增，信号索引递减的顺序，将所述第一序列映射至M个(例如M个连续的)子载波块上。
在一种示例中，第m个子载波块中位置靠后的多个(例如i个)连续子载波上所映射的多个(例如i个)信号与第m+1个子载波块中位置靠前的多个(例如i个)连续子载波上所映射的多个(例如i个)信号相同，m取遍1至M-1中的任一整数。i为大于或等于1的整数。
例如，第一序列包括15个(N＝15)信号，分别为信号0至14。子载波块的数量M＝3，每个子载波块中包括的子载波的数量均为9。例如，前一个(第m个)子载波块上位置靠后的3个子载波上所映射的3个信号与后一个(第m+1个)子载波块中位置靠前的3个子载波上所映射的3个信号相同，即i＝3。例如：
子载波块1上所映射的9个信号在第一序列中的索引分别为：13、14、0、1、2、3、4、5、6；
子载波块2上所映射的9个信号在第一序列中的索引分别为：4、5、6、7、8、9、10、11、12；
子载波块3上所映射的9个信号在第一序列中的索引分别为:10、11、12、13、14、0、1、2、3。
再一种示例中，第m个子载波块中位置靠后的多个(例如i个)连续子载波上所映射的多个(例如i个)信号与第m+1个子载波块中位置靠前的多个(例如i个)连续子载波所映射的多个(例如i个)信号相同，且第M个(最后一个)子载波块中位置靠后的多个(例如i个)连续子载波上所映射的多个(例如i个)信号与第1个子载波块中位置靠前的多个(例如i个)连续子载波所映射的多个(例如i个)信号相同。也可以理解为：所述第m个子载波块中位置靠后的多个连续子载波上所映射的多个信号与第mod(m，M)+1个子载波块中位置靠前的多个连续子载波所映射的多个信号相同。其中，mod(m，M)为m除以M的余数。
如图6所示，第一序列包括15个(N＝15)信号，分别为信号0至14。子载波块的数量M＝3，每个子载波块中包括的子载波的数量为9。例如，前一个(第m个)子载波块上位置靠后的4个子载波上所映射的4个信号与后一个(第mod(m，M)+1个)子载波块中位置靠前的4个子载波上所映射的4个信号相同，即i＝4。例如：
子载波块1上所映射的9个信号在第一序列中的索引分别为：13、14、0、1、2、3、4、5、6；
子载波块2上所映射的9个信号在第一序列中的索引分别为：3、4、5、6、7、8、9、10、11；
子载波块3上所映射的9个信号在第一序列中的索引分别为:8、9、10、11、12、13、14、0、1。
在一种示例中，第m个子载波块依次包括长度为p1 m的第一子载波(第一子载波用于传输循环冗余序列1)，长度为L m为第二子载波(第二子载波用于传输基序列)，长度为p2 m的第三子载波(第三子载波用于传输循环冗余序列2)。例如，第一子载波用于传输PTRS中的循环冗余序列1，第二子载波用于传输PTRS中的基序列，第三子载波用于传输PTRS中的循环冗余序列2。可以理解的是，PTRS中包括依次排列的：长度为p1的循环冗余序列1，长度为L的基序列，长度为p2的循环冗余序列2。此处的循环冗余序列、基序列只是为了方便描述，不应造成对方案的限定。
可以理解的是，Q＝L+p1+p2。
在一种可选的示例中，可以约束不同的子载波块中的第二子载波的长度L(子载波块中的第二子载波的长度L，也可以理解为：PTRS中的基序列的长度L)尽量相等。例如，N可以被M整除时，L m＝N/M；再例如，N不能被M整除时，L m＝floor(N/M)，或L m＝floor(N/M)+1，或L m＝ceil(N/M)，或L m＝ceil(N/M)-1，或者，L m为对N/M的四舍五入取整。floor为向下取整，ceil为向上取整。所述m取值为1至M中的部分整数或者全部整数。也就是M个子载波块中，可以是全部的子载波块中的第二子载波的长度满足该公式，也可以是一部分子载波块中的第二子载波的长度满足该公式。
可选的，可以约束不同的子载波块中的第二子载波的长度L的差距小于或等于1。不同的子载波块中的第二子载波的长度L尽量相同。所有子载波块中的第二子载波的长度相同时，循环特性较好，可以进一步提升解调性能。
一种可选的示例中，M个子载波块中分别包括的第二子载波的长度之和为所述第一序列的长度。即，即L 1+L 2+…+L M-1+L M＝N。
在一种示例中，可以约束不同的子载波块的长度Q尽量相等。例如，可以通过调整子载波块中的第一子载波的长度p1和/或第三子载波的长度p2的取值，使得每个子载波块的长度Q相等。
在一种示例中，在任一子载波块中，p1和p2的差距小于或等于1，即abs(p1 m-p2 m)<＝1。m取值为1至M中的部分整数或者全部整数。也就是M个子载波块中，可以是全部的或一部分子载波块中的第一子载波的长度和第三子载波的长度之差小于或等于1。一个子载波块的两边的冗余尽量相等，可以提高相噪估计性能，进一步地提升解调性能。
在不同的子载波块中，长度p1尽量相等，长度p2也尽量相等。
在一种示例中，在将第一序列映射至M个子载波块上时，可以采用以下方法：
首先，将第一序列依次映射至M个子载波块中的第二子载波上。所述M个子载波块中的第二子载波上所映射的信号在第一序列中连续。
可以理解为：将长度为N的第一序列分成M份子序列，第m分子序列的长度为L m。将这M份子序列分别映射到M个子载波块中的第二子载波上。第m份子序列映射至第m个子载波块中的第二子载波上。
在将第一序列依次映射至M个子载波块中的第二子载波上时，例如，可以按照子载波索引递增，信号索引递增的顺序，将所述第一序列映射至M个(连续的)子载波块中的第二子载波上；或者，也可以按照子载波索引递增，信号索引递减的顺序，将所述第一序列映射至M个(连续的)子载波块中的第二子载波上。
然后，按照每一个子载波块上所映射的信号是循环连续的方式，将第一序列中的信号映射至M个子载波块中的第一子载波上和第三子载波上。循环连续，可以理解为，当某一 子载波a上映射的信号为第一序列中的最后一个信号时，该子载波a的下一个子载波上映射的是子载波中的第1个信号(该方式为按照子载波索引递增，信号索引递增的顺序进行映射)。或者，当某一子载波a上映射的信号为第一序列中的第1个信号时，该子载波a的下一个子载波上映射的是子载波中的最后一个信号(该方式为按照子载波索引递增，信号索引递减的顺序进行映射)。
假设，针对任一子载波块，第二子载波中的第一个子载波上所映射的信号为第一序列中的第z个信号(称为信号S 1)，第二子载波中的最后一个子载波上所映射的信号为第一序列中的第x个信号(称为信号S L)。
一种示例中，如果按照子载波索引递增，信号索引递增的顺序，将所述第一序列映射至M个(连续的)子载波块中的第二子载波上，则z小于x。
针对任一子载波块，第二子载波中的第一个子载波之前的第j个子载波上所映射的信号(也可以理解为映射之后，信号S 1之前的第j个信号)为第一序列中的第(z-j)个信号；如果z-j小于或等于0，则将z-j替换为z-j+N。第二子载波中的最后一个子载波之后的第j个子载波上所映射的信号(也可以理解为映射之后，信号S L之后的第j个信号)为第一序列的第(x+j)个信号；如果x+j大于N，则将x+j替换为x+j-N。
如图6所示，第一序列包括15个(N＝15)信号，分别为信号0至14。子载波块的数量M＝3。每个子载波块的长度Q＝9，第二子载波(基序列)的长度L＝5，第一子载波(循环冗余序列1)的长度p1＝2，第三子载波(循环冗余序列2)的长度p2＝2。
将15个信号分为3份，第一份为信号0至信号4，第二份为信号5至信号9，第三份为信号10至信号14。按照子载波索引递增，信号索引递增的顺序，将这3份映射至3个子载波块中的第二子载波上。
子载波块1中的第二子载波上所映射的5个信号分别为第一序列中的第1个至第5个信号，即信号0至信号4；子载波块2中的第二子载波上所映射的5个信号分别为第一序列中的第6个至第10个信号，即信号5至信号9；子载波块3中的第二子载波上所映射的5个信号分别为第一序列中的第11个至第15个信号，即信号10至信号14。
以子载波块1为例进行说明：
子载波块1中的第二子载波中的第一个子载波上所映射的信号为第一序列中的第1(z＝1)个信号：信号0。
第一个子载波之前的第1(j＝1)个子载波上所映射的信号为第一序列中的第15(z-j+N＝1-1+15＝15)个信号：信号14。
第一个子载波之前的第2(j＝2)个子载波上所映射的信号为第一序列中的第14(z-j+N＝1-2+15＝14)个信号：信号13。
子载波块1中的第二子载波中的最后一个子载波上所映射的信号为第一序列中的第5(x＝5)个信号：信号4。
最后一个子载波之后的第1(j＝1)个子载波上所映射的信号为第一序列中的第6(x+j＝5+1＝6)个信号：信号5。
最后一个子载波之后的第2(j＝2)个子载波上所映射的信号为第一序列中的第7(x+j＝5+2＝7)个信号：信号6。
以子载波块2为例进行说明：
子载波块2中的第二子载波中的第一个子载波上所映射的信号为第一序列中的第6 (z＝6)个信号：信号5。
第一个子载波之前的第1(j＝1)个子载波上所映射的信号为第一序列中的第5(z-j＝6-1＝5)个信号：信号4。
第一个子载波之前的第2(j＝2)个子载波上所映射的信号为第一序列中的第4(z-j＝6-2＝4)个信号：信号3。
子载波块2中的第二子载波中的最后一个子载波上所映射的信号为第一序列中的第10(x＝10)个信号：信号9。
最后一个子载波之后的第1(j＝1)个子载波上所映射的信号为第一序列中的第11(x+j＝10+1＝11)个信号：信号10。
最后一个子载波之后的第2(j＝2)个子载波上所映射的信号为第一序列中的第12(x+j＝10+2＝12)个信号：信号11。
以子载波块3为例进行说明：
子载波块3中的第二子载波中的第一个子载波上所映射的信号为第一序列中的第11(z＝11)个信号：信号10。
第一个子载波之前的第1(j＝1)个子载波上所映射的信号为第一序列中的第10(z-j＝11-1＝10)个信号：信号9。
第一个子载波之前的第2(j＝2)个子载波上所映射的信号为第一序列中的第9(z-j＝11-2＝8)个信号：信号8。
子载波块2中的第二子载波中的最后一个子载波上所映射的信号为第一序列中的第15(x＝15)个信号：信号14。
最后一个子载波之后的第1(j＝1)个子载波上所映射的信号为第一序列中的第1(x+j-N＝15+1-15＝1)个信号：信号0。
最后一个子载波之后的第2(j＝2)个子载波上所映射的信号为第一序列中的第2(x+j-N＝10+2-15＝2)个信号：信号1。
另一种示例中，如果按照子载波索引递增，信号索引递减的顺序，将所述第一序列映射至M个(连续的)子载波块中的第二子载波上，则z大于x。
针对任一子载波块，第二子载波中的第一个子载波之前的第j个子载波上所映射的信号(也可以理解为映射之后，信号S 1之前的第j个信号)为第一序列中的第(z+j)个信号，如果z+j大于N，则将z+j替换为z+j-N。第二子载波中的最后一个子载波之后的第j个子载波上所映射的信号(也可以理解为映射之后，信号S L之后的第j个信号)为第一序列的第(x-j)个信号，如果z-j小于或等于0，则将x-j替换为x-j+N。
在一种可选的示例中，上文介绍了相噪对各子载波接收信号的影响，传输基序列的子载波上的接收信号可以满足如下公式：
Figure PCTCN2022096686-appb-000009
Noise为噪声，可见S矩阵为一个基序列(第二子载波)的循环移位构成的一个矩阵。
其中，E -n＝E -n+N。残留的ICI为除E -2，E -1，E 0，E 1，E 2以外的E造成的ICI。
从接收信号r，可以估计出E 12，E -1，E 0，E 1，E 2。
对于任意的子载波上的信号，例如S13，或者S14，或者S2等。这些信号所在位置上的ICI的系数是相同的。
例如：公式的第一行，对于接收信号r 0，发送端对应相同位置的发送信号是S 0，但r 0会受到5个信号的影响，前一个信号是S 14，后一个信号是S 1。
r 0＝S 13*E -2+S 14*E -1+S 0*E 0+S 1*E 1+S 2*E 2。
例如，公式第二行，r 1对应的发送信号为S 1。r 1＝S 14*E -2+S 0*E -1+S 1*E 0+S 2*E 1+S 3*E 2。
因此，根据公式可以得到，一个接收信号r，等于第一向量，和[E_(位置关系)]向量，的乘积和。第一向量为这个接收信号所在位置的前面的一个或多个发送信号，和这个接收信号所在位置的发送信号，和这个接收信号位置的后面一个或多个信号，组成的向量。
在一种可选的示例中，第m个子载波块的长度Q m为整数个RB，例如，RB的子载波数目为q，一个子载波块的子载波数量Q为数量q的整数倍，例如，Qm＝αq，其中α＝1，2，3，...。典型的，q＝12，Q的取值为12，24，36，48等。m取遍为1至M中的部分整数或者全部整数。在进行资源调度时，通常是按照资源块进行调度的，本申请中Q的取值为一个资源块RB的子载波数量的整数倍，容易调度。
在一种可选的示例中，通过p1 m或p2 m的取值来确定Q m的取值，也可以理解为所述Q m的取值基于p1 m和/或p2 m的取值来确定。m取值为1至M中的部分整数或者全部整数。
例如，当p1 m＝p2 m＝2时，Q m的取值分别为8，20，32，44。当p1 m＝p2 m＝3时，Q m的取值分别为6，18，30，42。
在一种可选的示例中，p1 m和p2 m的取值与Q m、M、N中至少之一的取值相关联。m取值为1至M中的部分整数或者全部整数。
例如，p1 m和p2 m的取值与Q m所在的取值范围关联。当Q m<＝Q1(例如Q1＝12)时，p1 m＝p2 m＝U0(例如U0＝2)；当Q m>Q1时，p1 m＝p2 m＝P1(例如P1＝3)。
例如，p1 m和p2 m的取值与N所在的取值范围关联。当N<＝N1(例如N1＝24)时，p1 m＝p2 m＝U0(例如U0＝2)；当N>N1时，p1 m＝p2 m＝P1(例如P1＝3)。
本文提及的p1 m、p2 m、Q m、M、L m、N等参数中的一项或多项参数，可以是协议规定的，也可以是网络设备配置给终端设备的。网络设备在向终端设备配置参数时，可以只配置一部分参数，终端设备可以根据参数之间的关联特性，得到其他的参数，网络设备无需配置全部的参数，可以降低开销。基站分配一两个参数，就可以知道其他的参数，可以降低开销。
接下来介绍几种Q、L、p1和p2的取值的示例(为了方便描述，省略了m)：
当Q＝12时，L＝7，则可以有p1＝3和p2＝2或p1＝2和p2＝3；
当Q＝24时，L＝19，则可以有p1＝3和p2＝2或p1＝2和p2＝3；
当Q＝24时，L＝17，则可以有p1＝3和p2＝4或p1＝4和p2＝3；
当Q＝36时，L＝31，则可以有p1＝3和p2＝2或p1＝2和p2＝3；
当Q＝36时，L＝29，则可以有p1＝3和p2＝4或p1＝4和p2＝3；
当Q＝48时，L＝43，则可以有p1＝3和p2＝2或p1＝2和p2＝3；
当Q＝48时，L＝41，则可以有p1＝3和p2＝4或p1＝4和p2＝3；
当Q＝48时，L＝37，则可以有p1＝5和p2＝6或p1＝6和p2＝5。
在一种可选的示例中，上述的步骤402也可以拆分为两个步骤：步骤402a和步骤402b。
步骤402a：第一设备将所述第一序列映射至M个参考信号上。
步骤402b：第一设备将所述M个参考信号映射至M个用于传输所述参考信号的子载波上。具体的，将第m个参考信号映射至第m个用于传输所述参考信的子载波上。
上述步骤402a中的，将第一序列映射至M个参考信号上，与步骤402中介绍的将第一序列映射至M个用于传输参考信号的子载波上的过程类似，将步骤402中的“用于传输参考信号的子载波”替换为“参考信号”即可。
例如，第m个参考信号包括Q m个信号，Q m为大于2的整数。所述m取值为1至M。不同的参考信号包括的信号的数量(参考信号的长度)，可以相同，也可以不同。可选的，不同的参考信号包括的信号的数量差值小于或等于1。例如，Q m与Q m+1的差值小于或等于1。再例如，Q m与Q m+2的差值小于或等于1。
第一序列的长度N大于任一参考信号包括的信号的数量，且N小于M个参考信号包括的信号的数量之和。即N大于Q m，且N小于Q 1、Q 2、…、Q m-1，Q m之和。
在一种示例中，可以将第一序列中连续多个(例如Q个)信号映射至一个参考信号上。具体的，可以将第一序列中循环连续的多个信号(例如Q个)映射至一个参考信号上。
在将第一序列映射至M个(例如M个连续的)参考信号上时，可以按照参考信号中的位置索引递增，第一序列中的信号索引递增的顺序，将所述第一序列映射至M个(例如M个连续的)参考信号上。也可以按照参考信号中的位置索引递增，第一序列中的信号索引递减的顺序，将所述第一序列映射至M个(例如M个连续的)参考信号上。
在一种示例中，映射之后，第m个参考信号中位置靠后的多个(例如i个)信号与第m+1个参考信号中位置靠前的多个(例如i个)信号相同，m取值为1至M。i为大于或等于1的整数。
再一种示例中，映射之后，第m个参考信号中位置靠后的多个(例如i个)信号与第m+1个参考信号中位置靠前的多个(例如i个)信号相同，且第M个(最后一个)参考信号中位置靠后的多个(例如i个)信号与第1个参考信号中位置靠前的多个(例如i个)信号相同。也可以理解为：所述第m个参考信号中位置靠后的多个信号与第mod(m，M)+1个参考信号中位置靠前的多个信号相同。其中，mod(m，M)为m除以M的余数。
在一种示例中，第m个参考信号中包括依次排列的：长度为p1 m的循环冗余序列1，长度为L m的基序列，长度为p2 m的循环冗余序列2。此处的循环冗余序列、基序列只是为了方便描述，不应造成对方案的限定。可以理解的是，Q＝L+p1+p2。
在一种可选的示例中，可以约束不同的参考信号中的基序列的长度L尽量相等。例如，N可以被M整除时，L m＝N/M；再例如，N不能被M整除时，L m＝floor(N/M)，或L m＝floor(N/M)+1，或L m＝ceil(N/M)，或L m＝ceil(N/M)-1，或者，L m为对N/M的四舍五入取整。floor为向下取整，ceil为向上取整。可选的，可以约束不同的参考信号中的基序列的长度L的差距小于或等于1。
一种可选的示例中，M个参考信号中分别包括的基序列的长度之和为所述第一序列的长度。即，即L 1+L 2+…+L M-1+L M＝N。
在一种示例中，可以约束不同的参考信号的长度Q尽量相等。例如，可以通过调整参考信号中的循环冗余序列1的长度p1和/或循环冗余序列2的长度p2的取值，使得每个参 考信号的长度Q相等。
在一种示例中，在任一参考信号中，p1和p2的差距小于或等于1，即abs(p1 m-p2 m)<＝1。在不同的参考信号中，长度p1尽量相等，长度p2也尽量相等。
在一种示例中，在将第一序列映射至M个参考信号上时，可以采用以下方法：
首先，将第一序列依次映射至M个参考信号中的基序列上。所述M个参考信号中的基序列上所映射的信号在第一序列中连续。
可以理解为：将长度为N的第一序列分成M份子序列，第m分子序列的长度为L m。将这M份子序列分别映射到M个参考信号中的基序列上。第m份子序列映射至第m个参考信号中的基序列上。
在将第一序列依次映射至M个参考信号中的基序列上时，例如，按照基序列中的位置索引递增，第一序列中的信号索引递增的顺序，将所述第一序列映射至M个(连续的)参考信号中的基序列上；或者，按照基序列中的位置索引递增，第一序列中的信号索引递减的顺序，将所述第一序列映射至M个(连续的)参考信号中的基序列上。
然后，按照每一个参考信号上所映射的信号是循环连续的方式，将第一序列中的信号映射至M个参考信号中的循环冗余序列1上和循环冗余序列2上。
假设，针对任一参考信号，基序列中的第一个位置上所映射的信号为第一序列中的第z个信号(称为信号S 1)，基序列中的最后一个位置上所映射的信号为第一序列中的第x个信号(称为信号S L)。
一种示例中，如果按照基序列中的位置索引递增，第一序列中的信号索引递增的顺序，将所述第一序列映射至M个(连续的)参考信号中的基序列上，则z小于x。
针对任一参考信号，基序列中的第一个位置之前的第j个位置上所映射的信号(也可以理解为映射之后，信号S 1之前的第j个信号)为第一序列中的第(z-j)个信号；如果z-j小于或等于0，则将z-j替换为z-j+N。基序列中的最后一个位置之后的第j个位置上所映射的信号(也可以理解为映射之后，信号S L之后的第j个信号)为第一序列的第(x+j)个信号；如果x+j大于N，则将x+j替换为x+j-N。
另一种示例中，如果按照基序列中的位置索引递增，第一序列中的信号索引递减的顺序，将所述第一序列映射至M个(连续的)参考信号中的基序列上，则z大于x。
针对任一参考信号，基序列中的第一个位置之前的第j个位置上所映射的信号(也可以理解为映射之后，信号S 1之前的第j个信号)为第一序列中的第(z+j)个信号，如果z+j大于N，则将z+j替换为z+j-N。基序列中的最后一个位置之后的第j个位置上所映射的信号(也可以理解为映射之后，信号S L之后的第j个信号)为第一序列的第(x-j)个信号，如果z-j小于或等于0，则将x-j替换为x-j+N。
步骤403：第一设备在各个子载波上发送所映射的信号。
本申请中具体到设备(网元)改动，终端设备和网络设备中生成参考信号的方法(将第一序列映射至子载波块的方法)不同。
本申请联合设计多个参考信号子载波块上传输的信号，在多个参考信号(例如PTRS)子载波块中构成循环冗余特性的方案。第一序列长度较长，从而构建一个相对于现有技术更大的循环移位矩阵用于对由相噪产生的ICI系数的估计，可以提升对由相噪产生的子载波间干扰系数ICI的估计精度，进而提升数据解调性能。
如图4b所示，以OFDM系统、参考信号为PTRS为例，介绍一种传输OFDM信号的示例，下文介绍的发送端可以是图4a中的第一设备，包括以下步骤：
步骤41：发送端生成PTRS基序列。
步骤42：发送端基于PTRS基序列生成PTRS。
例如，步骤41和步骤42可以参考前文步骤402a处的介绍。
例如，步骤41的过程可以包括：将第一序列依次映射至M个参考信号中的基序列上。所述M个参考信号中的基序列上所映射的信号在第一序列中连续。
可以理解为：将长度为N的第一序列分成M份子序列，第m分子序列的长度为L m。将这M份子序列分别映射到M个参考信号中的基序列上。第m份子序列映射至第m个参考信号中的基序列上。
在将第一序列依次映射至M个参考信号中的基序列上时，例如，按照基序列中的位置索引递增，第一序列中的信号索引递增的顺序，将所述第一序列映射至M个(连续的)参考信号中的基序列上；或者，按照基序列中的位置索引递增，第一序列中的信号索引递减的顺序，将所述第一序列映射至M个(连续的)参考信号中的基序列上。
例如，步骤42的过程可以包括：按照每一个参考信号上所映射的信号是循环连续的方式，将第一序列中的信号映射至M个参考信号中的循环冗余序列1上和循环冗余序列2上。
假设，针对任一参考信号，基序列中的第一个位置上所映射的信号为第一序列中的第z个信号(称为信号S 1)，基序列中的最后一个位置上所映射的信号为第一序列中的第x个信号(称为信号S L)。
一种示例中，如果按照基序列中的位置索引递增，第一序列中的信号索引递增的顺序，将所述第一序列映射至M个(连续的)参考信号中的基序列上，则z小于x。
针对任一参考信号，基序列中的第一个位置之前的第j个位置上所映射的信号(也可以理解为映射之后，信号S 1之前的第j个信号)为第一序列中的第(z-j)个信号；如果z-j小于或等于0，则将z-j替换为z-j+N。基序列中的最后一个位置之后的第j个位置上所映射的信号(也可以理解为映射之后，信号S L之后的第j个信号)为第一序列的第(x+j)个信号；如果x+j大于N，则将x+j替换为x+j-N。
另一种示例中，如果按照基序列中的位置索引递增，第一序列中的信号索引递减的顺序，将所述第一序列映射至M个(连续的)参考信号中的基序列上，则z大于x。
针对任一参考信号，基序列中的第一个位置之前的第j个位置上所映射的信号(也可以理解为映射之后，信号S 1之前的第j个信号)为第一序列中的第(z+j)个信号，如果z+j大于N，则将z+j替换为z+j-N。基序列中的最后一个位置之后的第j个位置上所映射的信号(也可以理解为映射之后，信号S L之后的第j个信号)为第一序列的第(x-j)个信号，如果z-j小于或等于0，则将x-j替换为x-j+N。
步骤43：发送端基于PTRS生成OFDM信号。
例如，将PTRS放在相应的OFDM子载波上，例如，联合PTRS和数据，生成OFDM信号。
步骤44：发送端发送OFDM信号。
步骤45：接收端接收OFDM信号。
步骤46：接收端对OFDM信号进行均衡，也就是去掉信道的影响。该步骤为可选的 步骤。
步骤47：接收端基于PTRS估计相噪影响，并解调OFDM信号。
例如，通过PTRS估计相噪带来的ICI系数，从而解调出OFDM信号传输的数据。
可以理解的是：接收端需要知道参考信号(例如PTRS)的信息，包括但不限于：子载波位置、个数、发送的参考信号(例如PTRS)本身等等。这样接收端才能够基于PTRS估计相噪带来的影响。发送端可以是终端设备，接收端可以是网络设备；或者，发送端是网络设备，接收端是终端设备。PTRS的信息可以通过网络设备配置给终端设备的，例如通过下行控制信息(downlink control information，DCI)、媒体接入控制(media access control，MAC)、无线资源控制(radio resource control，RRC)信令进行配置。
如图7所示，提供了一种数据解调性能的对比示意图。采用ZC序列作为第一序列为ZC序列，粗线代表复杂度高的解调方案，细线代表复杂度低的解调方案。可以看到：本申请不管是在高复杂度还是低复杂度解调方案下，都比现有技术(传统块状方案)性能好。
前文介绍了本申请实施例的方法，下文中将介绍本申请实施例中的装置。方法、装置是基于同一技术构思的，由于方法、装置解决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。
本申请实施例可以根据上述方法示例，对装置进行功能模块的划分，例如，可以对应各个功能划分为各个功能模块，也可以将两个或两个以上的功能集成在一个模块中。这些模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，具体实现时可以有另外的划分方式。
基于与上述方法的同一技术构思，参见图8，提供了一种通信装置800结构示意图，该装置800可以包括：处理模块810，可选的，还包括接收模块820a、发送模块820b、存储模块830。处理模块810可以分别与存储模块830和接收模块820a和发送模块820b相连，所述存储模块830也可以与接收模块820a和发送模块820b相连。
在一种示例中，上述的接收模块820a和发送模块820b也可以集成在一起，定义为收发模块。
在一种示例中，该装置800可以为第一设备，也可以为应用于第一设备中的芯片或功能单元。该装置800具有上述方法中第一设备的任意功能，例如，该装置800能够执行上述图4a、图4b的方法中由第一设备执行的各个步骤。
所述接收模块820a，可以执行上述方法实施例中第一设备执行的接收动作。所述发送模块820b，可以执行上述方法实施例中第一设备执行的发送动作。
所述处理模块810，可以执行上述方法实施例中第一设备执行的动作中，除发送动作和接收动作外的其它动作。在一种示例中，所述处理模块810，用于将第一序列映射至M个用于传输参考信号的子载波块上；其中，第m个所述子载波块包括Q m个子载波，Q m为大于或等于2的整数，m取遍1至M中的整数，所述M为大于或等于2的整数；所述第一序列包括多个信号，所述第m个子载波块中位置靠后的多个连续子载波上所映射的多个信号与第mod(m，M)+1个子载波块中位置靠前的多个连续子载波所映射的多个信号相同；其中，mod(m，M)为m除以M的余数。
所述发送模块820b，用于在各个所述子载波上发送所映射的信号。
一种示例中，所述处理模块810，具体用于：按照子载波索引递增，信号索引递增的 顺序，将所述第一序列映射至M个用于传输参考信号的子载波块上；或者，按照子载波索引递增，信号索引递减的顺序，将所述第一序列映射至M个用于传输参考信号的子载波块上。
一种示例中，所述接收模块820a，用于接收其它设备发送的第一序列。
在一种示例中，所述存储模块830，可以存储第一设备执行的方法的计算机执行指令，以使处理模块810和接收模块820a和发送模块820b执行上述示例中第一设备执行的方法。
示例的，存储模块830可以包括一个或者多个存储器，存储器可以是一个或者多个设备、电路中用于存储程序或者数据的器件。存储模块可以是寄存器、缓存或者RAM等，存储模块可以和处理模块集成在一起。存储模块可以是ROM或者可存储静态信息和指令的其他类型的静态存储设备，存储模块可以与处理模块相独立。
所述接收模块820a和发送模块820b可以是输入或者输出接口、管脚或者电路等。
图8中的处理模块810可以通过处理电路来实现。图8中的接收模块820a和发送模块820b可以通过输入输出接口来实现。或者，输入输出接口分为输入接口和输出接口，输入接口执行接收模块的功能，输出接口执行发送模块的功能。图8中的存储模块830可以通过存储介质来实现。
以上介绍了本申请实施例的应用于第一设备的装置，以下介绍所述应用于第一设备的装置可能的产品形态。应理解，但凡具备上述图8所述的应用于第一设备的装置的特征的任何形态的产品，都落入本申请的保护范围。还应理解，以下介绍仅为举例，不应限制本申请实施例的应用于第一设备的装置的产品形态仅限于此。
作为一种可能的产品形态，装置可以由一般性的总线体系结构来实现。如图9所示，提供了一种通信装置900的示意性框图。该装置900可以包括处理器910，可选的，还包括收发器920、存储器930。该收发器920，可以用于接收程序或指令并传输至所述处理器910，或者，该收发器920可以用于该装置900与其他通信设备进行通信交互，比如交互控制信令和/或业务数据等。该收发器920可以为代码和/或数据读写收发器，或者，该收发器920可以为处理器910与收发器920之间的信号传输收发器。所述处理器910和所述存储器930之间电耦合。
一种示例中，该装置900可以为第一设备，也可以为应用于第一设备中的芯片。应理解，该装置具有上述方法中第一设备的任意功能，例如，所述装置900能够执行上述图4a、图4b的方法中由第一设备执行的各个步骤。示例的，所述存储器930，用于存储计算机程序；所述处理器910，可以用于调用所述存储器930中存储的计算机程序或指令，执行上述示例中第一设备执行的方法，或者通过所述收发器920执行上述示例中第一设备执行的方法。
作为一种可能的产品形态，装置可以由通用处理器(通用处理器也可以称为芯片或芯片系统)来实现。一种可能的实现方式中，实现应用于第一设备的装置的通用处理器包括：处理电路(处理电路也可以称为处理器)。可选的，该装置900还包括与所述处理电路内部连接通信的输入输出接口、存储介质(存储介质也可以称为存储器)，所述存储介质用于存储处理电路执行的指令，以执行上述示例中第一设备执行的方法。
作为一种可能的产品形态，本申请实施例的装置，还可以使用下述来实现：一个或多个FPGA(现场可编程门阵列)、PLD(可编程逻辑器件)、控制器、状态机、门逻辑、分立硬件部件、任何其它适合的电路、或者能够执行本申请通篇所描述的各种功能的电路的 任意组合。
本申请实施例还提供了一种计算机可读存储介质，存储有计算机程序，该计算机程序被计算机执行时，可以使得所述计算机用于执行上述发送信号的方法。或者说：所述计算机程序包括用于实现上述发送信号的方法的指令。
本申请实施例还提供了一种计算机程序产品，包括：计算机程序代码，当所述计算机程序代码在计算机上运行时，使得计算机可以执行上述提供的发送信号的方法。
另外，本申请实施例中提及的处理器可以是中央处理器(central processing unit，CPU)，基带处理器，基带处理器和CPU可以集成在一起，或者分开，还可以是网络处理器(network processor，NP)或者CPU和NP的组合。处理器还可以进一步包括硬件芯片或其他通用处理器。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)及其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等或其任意组合。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
本申请实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synch link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。应注意，本申请描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
本申请实施例中提及的收发器中可以包括单独的发送器，和/或，单独的接收器，也可以是发送器和接收器集成一体。收发器可以在相应的处理器的指示下工作。可选的，发送器可以对应物理设备中发射机，接收器可以对应物理设备中的接收机。
本领域普通技术人员可以意识到，结合本文中所公开的实施例中描述的各方法步骤和单元，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各实施例的步骤及组成。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域普通技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示 或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请中的“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。本申请中所涉及的多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包括这些改动和变型在内。

Claims (16)

  1. 一种通信方法，其特征在于，包括：
    将第一序列映射至M个用于传输参考信号的子载波块上；其中，第m个所述子载波块包括Q m个子载波，Q m为大于或等于2的整数，m取遍1至M中的整数，所述M为大于或等于2的整数；所述第一序列包括多个信号，所述第m个子载波块中位置靠后的多个连续子载波上所映射的多个信号与第mod(m，M)+1个子载波块中位置靠前的多个连续子载波所映射的多个信号相同；其中，mod(m，M)为m除以M的余数；
    在各个所述子载波上发送所映射的信号。
  2. 如权利要求1所述的方法，其特征在于，将第一序列映射至M个用于传输参考信号的子载波块上，包括：
    按照子载波索引递增，信号索引递增的顺序，将所述第一序列映射至M个用于传输参考信号的子载波块上；或者，
    按照子载波索引递增，信号索引递减的顺序，将所述第一序列映射至M个用于传输参考信号的子载波块上。
  3. 如权利要求1或2所述的方法，其特征在于，第m个所述子载波块包括：依次排列的：长度为p1 m的第一子载波、长度为L m的第二子载波，长度为p2 m的第三子载波；
    其中，M个所述子载波块中的第二子载波上所映射的信号在所述第一序列中连续。
  4. 如权利要求3所述的方法，其特征在于，M个子载波块中分别包括的第二子载波的长度之和为所述第一序列的长度。
  5. 如权利要求3或4所述的方法，其特征在于，所述L m满足：L m＝N/M，或，L m＝floor(N/M)，或L m＝floor(N/M)+1，或L m＝ceil(N/M)，或L m＝ceil(N/M)-1；
    其中，floor为向下取整，ceil为向上取整，N为所述第一序列的长度，所述m取值为1至M中的部分整数或全部整数。
  6. 如权利要求3-5任一项所述的方法，其特征在于，所述p1 m与所述p2 m的差值小于或等于1，所述m取值为1至M中的部分整数或者全部整数。
  7. 如权利要求4-6任一项所述的方法，其特征在于，所述Q m的取值基于p1 m和/或p2 m的取值确定。
  8. 如权利要求4-6任一项所述的方法，其特征在于，p1 m和p2 m的取值与Q m、M、N中的至少之一关联，所述m取值为1至M中的部分整数或者全部整数。
  9. 如权利要求1-8任一项所述的方法，其特征在于，所述Q m＝a*q，其中，q为一个资源块RB的子载波数量，a为大于或等于1的整数，所述m取值为1至M中的部分整数或者全部整数。
  10. 如权利要求1-9任一项所述的方法，其特征在于，所述第一序列为以下任一序列：
    ZC序列，正交幅度调制QAM序列，互补序列，伪随机序列。
  11. 一种通信装置，其特征在于，包括：执行如权利要求1-10任一项所述的方法的功能模块。
  12. 一种通信装置，其特征在于，包括处理器，所述处理器与存储器耦合；
    所述存储器存储计算机程序或指令；
    所述处理器，用于执行所述存储器中的部分或者全部计算机程序或指令，当所述部分 或者全部计算机程序或指令被执行时，用于实现如权利要求1-10任一项所述的方法。
  13. 一种通信装置，其特征在于，包括处理器和存储器；
    所述存储器存储计算机程序或指令；
    所述处理器，用于执行所述存储器中的部分或者全部计算机程序或指令，当所述部分或者全部计算机程序或指令被执行时，用于实现如权利要求1-10任一项所述的方法。
  14. 一种芯片系统，其特征在于，包括处理电路；所述处理电路与存储介质耦合；
    所述处理电路，用于执行所述存储介质中的部分或者全部计算机程序或指令，当所述部分或者全部计算机程序或指令被执行时，用于实现如权利要求1-10任一项所述的方法。
  15. 一种计算机可读存储介质，其特征在于，用于存储计算机程序，所述计算机程序包括用于实现权利要求1-10任一项所述的方法的指令。
  16. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序代码，当所述计算机程序代码在计算机上运行时，使得所述计算机执行如权利要求1-10任一项所述的方法。
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