WO2022257092A1 - 集成器件、半导体器件以及集成器件的制作方法 - Google Patents

集成器件、半导体器件以及集成器件的制作方法 Download PDF

Info

Publication number
WO2022257092A1
WO2022257092A1 PCT/CN2021/099575 CN2021099575W WO2022257092A1 WO 2022257092 A1 WO2022257092 A1 WO 2022257092A1 CN 2021099575 W CN2021099575 W CN 2021099575W WO 2022257092 A1 WO2022257092 A1 WO 2022257092A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal layer
capacitor
gallium nitride
integrated device
Prior art date
Application number
PCT/CN2021/099575
Other languages
English (en)
French (fr)
Inventor
唐高飞
包琦龙
王汉星
蒋其梦
欧阳东法
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180088904.2A priority Critical patent/CN116745914A/zh
Priority to EP21944601.0A priority patent/EP4325581A1/en
Priority to PCT/CN2021/099575 priority patent/WO2022257092A1/zh
Publication of WO2022257092A1 publication Critical patent/WO2022257092A1/zh
Priority to US18/533,315 priority patent/US20240113103A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

Definitions

  • the present application relates to a microelectronic technology, in particular to an integrated device, a semiconductor device and a manufacturing method of the integrated device.
  • Gallium nitride (GaN) power devices have great potential in the field of power conversion due to their small on-resistance and fast turn-on speed.
  • the peak voltage (10V) that the gate of this device can withstand is smaller than that of traditional silicon devices, and the threshold voltage is relatively small (between 1.0 and 2.5V)
  • the gate drive waveform is prone to oscillation, which may cause overvoltage damage to the gate of the device or false turn-on of the device.
  • the gate drive circuit can be monolithically integrated with a single transistor on the GaN device platform.
  • capacitor plates such as field plate layers, gate metal layers
  • the integration of capacitors is limited by the chip area.
  • Embodiments of the present application provide an integrated device, a semiconductor device, and a manufacturing method of the integrated device, which are used to increase the capacitance integration density of the integrated device.
  • the first aspect of the present application provides an integrated device, comprising: a first metal layer; a first dielectric layer disposed on the first metal layer; a second dielectric layer disposed on the first dielectric layer; A gate metal layer between a dielectric layer and a second dielectric layer; and, a second metal layer disposed on the second dielectric layer; wherein, the first metal layer, the first dielectric layer and the gate metal layer are used for Constitute the first capacitor; the second metal layer, the second dielectric layer and the gate metal layer are used to constitute the second capacitor; the first metal layer and the second metal layer are connected through the first conductor structure, so that the first capacitor and the second The capacitors are connected in parallel.
  • the gate metal layer, the first dielectric layer and the first metal layer constitute the first capacitor
  • the gate metal layer, the second dielectric layer and the second metal layer constitute the second capacitor, that is, in an integrated device
  • Two capacitors are formed at the same time, and the first metal layer and the second metal layer are connected through the first conductor structure, so that the first capacitor and the second capacitor are connected in parallel, so that the capacitance capacity in the integrated device is increased, that is, the capacitance of the integrated device is increased. Integration density.
  • the polarity of the gate metal layer is opposite to that of the first metal layer, and the polarity of the second metal layer is opposite to that of the gate metal layer.
  • the integrated device further includes a third metal layer, a P-type conductive layer arranged under the first metal layer; an aluminum gallium nitride layer arranged under the P-type conductive layer; an aluminum gallium nitride layer Two-dimensional electron gas is included under the layer; the first metal layer, P-type conductive layer and two-dimensional electron gas are used to form the third capacitor; the third metal layer passes through the second dielectric layer, the first dielectric layer and aluminum gallium nitride The layer is connected to the two-dimensional electron gas, and the third metal layer is connected to the gate metal layer through the second conductor structure, so that the first capacitor, the second capacitor and the third capacitor are connected in parallel.
  • the two-dimensional electron gas is located under the AlGaN layer, and the two-dimensional electron gas is generated when the voltage between the third metal layer and the gate metal layer is within a preset range.
  • the first metal layer, the P-type conductive layer, and the two-dimensional electron gas form the third capacitor, and three capacitors are formed on the integrated device at the same time, and the third metal layer is connected to the gate metal layer through the second conductor structure, so that the first The parallel connection of the capacitor, the second capacitor and the third capacitor can further increase the capacitor integration density of the integrated device.
  • the polarity of the third metal layer is opposite to that of the first metal layer.
  • the aluminum gallium nitride layer is disposed on the aluminum nitride layer, and the two-dimensional electron gas is located below the aluminum nitride layer.
  • the two-dimensional electron gas is located between the aluminum nitride layer and the gallium nitride layer, which can increase the electron concentration of the two-dimensional electron gas.
  • the P-type conductive layer includes P-type gallium nitride or P-type aluminum gallium nitride.
  • the first metal layer includes titanium nitride or tungsten.
  • materials of the first conductor structure and the second conductor structure include copper or aluminum.
  • the second aspect of the present application provides an integrated device, including: an aluminum gallium nitride layer; a first dielectric layer disposed on the aluminum gallium nitride layer; a second dielectric layer disposed on the first dielectric layer; A gate metal layer between the first dielectric layer and the second dielectric layer; and, a second metal layer disposed on the second dielectric layer; wherein, two-dimensional electron gas is included under the aluminum gallium nitride layer; two The dimensional electron gas, the first dielectric layer and the gate metal layer are used to form the first capacitor; the second metal layer, the second dielectric layer and the gate metal layer are used to form the second capacitor; the second metal layer passes through the second dielectric layer, the first dielectric layer, and the AlGaN layer are in contact with the two-dimensional electron gas, so that the first capacitor is connected in parallel with the second capacitor.
  • the two-dimensional electron gas is located under the AlGaN layer, and the two-dimensional electron gas is generated when the voltage between the second metal layer and the gate metal layer is within a predetermined range.
  • the gate metal layer, the first dielectric layer and the two-dimensional electron gas form the first capacitor
  • the gate metal layer, the second dielectric layer and the second metal layer form the second capacitor
  • two capacitors are formed on the integrated device at the same time, and the two The dimensional electron gas is connected to the second metal layer, so that the first capacitor and the second capacitor are connected in parallel, thereby increasing the capacitor integration density of the integrated device.
  • the polarity of the second metal layer is opposite to that of the gate metal layer.
  • the first dielectric layer includes P-type GaN or P-type Aluminum Gallium Nitride
  • the gate metal layer passes through the first dielectric layer and is formed on P-type GaN or P-type Aluminum Gallium Nitride. over aluminum gallium.
  • the aluminum gallium nitride layer is disposed on the aluminum nitride layer, and the two-dimensional electron gas is located below the aluminum nitride layer.
  • the material of the conductor structure includes copper or aluminum.
  • the third aspect of the present application provides a semiconductor device, including the integrated device provided in the aforementioned first aspect or any optional manner of the first aspect, and a semiconductor composition formed on the integrated device.
  • the fourth aspect of the present application provides a semiconductor device, including the integrated device provided in the aforementioned second aspect or any optional manner of the second aspect, and a semiconductor composition formed on the integrated device.
  • the fifth aspect of the present application provides a manufacturing method of an integrated device, including: forming a first dielectric layer on the first metal layer; forming a gate metal layer on the first dielectric layer; forming a second dielectric layer on the gate metal layer A dielectric layer; forming a second metal layer on the second dielectric layer; wherein, the first metal layer, the first dielectric layer and the gate metal layer are used to form the first capacitor; the second metal layer, the second dielectric layer and the gate The metal layer is used to form the second capacitor; the first metal layer is connected to the second metal layer through the first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.
  • the method further includes: the polarity of the gate metal layer is opposite to that of the first metal layer, and the polarity of the second metal layer is opposite to that of the gate metal layer.
  • the method further includes: forming the first metal layer on the P-type conductive layer, the P-type conductive layer is formed on the aluminum gallium nitride layer, and the aluminum gallium nitride layer includes a two-dimensional Electron gas, the first metal layer, P-type conductive layer and two-dimensional electron gas are used to form the third capacitor; the third metal layer is formed on the second dielectric layer, and the third metal layer passes through the second dielectric layer, the first dielectric layer The layer and the aluminum gallium nitride layer are connected to the two-dimensional electron gas; the third metal layer is connected to the gate metal layer through the second conductor structure, so that the first capacitor, the second capacitor and the third capacitor are connected in parallel.
  • the polarity of the third metal layer is opposite to that of the first metal layer.
  • the aluminum gallium nitride layer is formed on the aluminum nitride layer, and the two-dimensional electron gas is located below the aluminum nitride layer.
  • the P-type conductive layer includes P-type gallium nitride or P-type aluminum gallium nitride.
  • the first metal layer includes titanium nitride or tungsten.
  • materials of the first conductor structure and the second conductor structure include copper or aluminum.
  • the sixth aspect of the present application provides a method for manufacturing an integrated device, including: forming a first dielectric layer on an aluminum gallium nitride layer; forming a gate metal layer on the first dielectric layer; forming a second dielectric layer on the gate metal layer Two dielectric layers; a second metal layer is formed on the second dielectric layer; a two-dimensional electron gas is included under the aluminum gallium nitride layer, and the two-dimensional electron gas, the first dielectric layer and the gate metal layer are used to form the first capacitor; The second metal layer, the second dielectric layer and the gate metal layer are used to form the second capacitor; the second metal layer passes through the second dielectric layer, the first dielectric layer and the aluminum gallium nitride layer, and is connected to the two-dimensional electron gas , so that the first capacitor is connected in parallel with the second capacitor.
  • the polarity of the second metal layer is opposite to that of the gate metal layer.
  • the first dielectric layer includes P-type GaN or P-type Aluminum Gallium Nitride
  • the gate metal layer passes through the first dielectric layer and is formed on P-type GaN or P-type Aluminum Gallium Nitride. over aluminum gallium.
  • the aluminum gallium nitride layer is formed on the aluminum nitride layer, and the two-dimensional electron gas is located below the aluminum nitride layer.
  • the seventh aspect of the present application provides a driving circuit, including: a gate driver, and an integrated device according to any one of the first and second aspects, or implemented using any one of the fifth and sixth aspects
  • the integrated device obtained by the method; wherein: the gate driver provides current for the gate in the above integrated device.
  • the eighth aspect of the present application provides an electronic device, the electronic device includes the integrated device according to any one of the first aspect and the second aspect, or uses the method of any one of the fifth aspect and the sixth aspect The resulting integrated device.
  • FIG. 1 is a power amplification architecture diagram provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of an integrated device provided in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an equivalent circuit diagram of an integrated device provided in an embodiment of the present application.
  • Fig. 4 is another structural schematic diagram of the integrated device provided by the embodiment of the present application.
  • FIG. 5 is another schematic diagram of an equivalent circuit diagram of an integrated device provided in an embodiment of the present application.
  • FIG. 6 is another structural schematic diagram of an integrated device provided by an embodiment of the present application.
  • FIG. 7 is another schematic diagram of an equivalent circuit diagram of an integrated device provided in an embodiment of the present application.
  • FIG. 8 is another structural schematic diagram of an integrated device provided by an embodiment of the present application.
  • FIG. 9 is another schematic diagram of an equivalent circuit diagram of an integrated device provided in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of an embodiment of a manufacturing method of an integrated device provided in an embodiment of the present application.
  • Fig. 11 is a schematic diagram of another embodiment of the manufacturing method of the integrated device provided by the embodiment of the present application.
  • Fig. 12 is a schematic diagram of another embodiment of the manufacturing method of the integrated device provided by the embodiment of the present application.
  • Fig. 13 is a schematic diagram of another embodiment of the manufacturing method of the integrated device provided by the embodiment of the present application.
  • Fig. 14 is a schematic diagram of another embodiment of the manufacturing method of the integrated device provided by the embodiment of the present application.
  • FIG. 15 is a schematic diagram of a driving circuit provided by an embodiment of the present application.
  • FIG. 16 is a schematic diagram of an electronic device provided by an embodiment of the present application.
  • Embodiments of the present application provide an integrated device, a semiconductor device, and a manufacturing method of the integrated device, which are used to increase the capacitance integration density of the integrated device.
  • a and B can be in direct contact or not, for example: A and B can include C, wherein, C can not completely separate A and B, or can completely separate A and B .
  • Gallium Nitride (GaN) is a semiconductor with a large bandgap width, which belongs to the wide bandgap semiconductor.
  • Gallium nitride is an excellent material for microwave power transistors and a new type of semiconductor material for the development of microelectronic devices and optoelectronic devices. It has a wide direct band gap, strong atomic bonds, high thermal conductivity, and good chemical stability (almost not Any acid corrosion) and other properties and strong radiation resistance.
  • Two-dimensional electron gas refers to the phenomenon that the electron gas can move freely in the two-dimensional direction, but is restricted in the third dimension.
  • the two-dimensional electron gas is located in the aluminum nitride device platform of the gallium nitride Between the gallium layer and the gallium nitride layer, the two-dimensional electron gas can also be called channel electrons. It is the basis for the operation of many field effect devices (eg MOSFET, HEMT).
  • Metal-insulators-metal (metal-insulators-metal, MIM) capacitance also called inter-board capacitance
  • MIM capacitors cause the least interference to transistors, and can provide better linearity (Linearity) and symmetry (Symmetry), so It has been widely used, especially in the field of mixed signal and radio frequency.
  • FIG. 1 is a power amplifier architecture diagram provided by an embodiment of the present application, and the architecture diagram includes an input module 11 , a power amplifier 12 and an output module 13 .
  • the power amplifier 12 can amplify the output power of the input module 11 and then output it to the output module 13 . Since the voltage of power grids in various countries in the world varies greatly, for example, the AC voltage of country A is 220V, which is relatively stable. However, the grid voltage of country B fluctuates greatly, ranging from 90VAC to 350VAC.
  • Gallium nitride (GaN) devices can be used to increase the switching frequency, thereby reducing the size of the transformer, that is, the power amplifier 12 is a gallium nitride (GaN) device, and the GaN device has larger bandwidth, higher amplifier gain, higher energy efficiency, Smaller semiconductor devices.
  • GaN devices can work at high temperatures above 200°C, can carry higher energy density, and have higher reliability; larger bandgap and insulation damage
  • the electric field reduces the on-resistance of the device, which is conducive to improving the overall energy efficiency of the device; the fast electron saturation speed and high carrier mobility allow the device to work at high speed.
  • the metal layers available in the process flow are usually used to form the plates of the capacitor (such as the field plate layer and the gate metal layer). Therefore, the integration of the capacitor is limited by the thickness of the dielectric layer, and the dielectric layer It often occupies most of the structure of the chip, and the integration of capacitors is limited by the chip area.
  • an embodiment of the present application provides an integrated device, and the structure of the integrated device is described below.
  • FIG. 2 it is a schematic structural diagram of an integrated device provided by an embodiment of the present application, the integrated device includes a semiconductor substrate 21, a gallium nitride (GaN) layer 22, and an aluminum gallium nitride (AlGaN) layer 23 , P-type conductive layer 24 , first metal layer 25 , first dielectric layer 26 , gate metal layer 27 , second dielectric layer 28 and second metal layer 29 .
  • GaN gallium nitride
  • AlGaN aluminum gallium nitride
  • semiconductor substrate 21 the material of this semiconductor substrate 21 can be silicon (Si) substrate, sapphire (Al2O3) substrate, silicon-on-insulator (SOI) substrate, gallium nitride (GaN) substrate, gallium arsenide ( GaAs) substrate, indium phosphide (InP) substrate, aluminum nitride (AlN) substrate, silicon carbide (SiC) substrate, quartz (SiO2) substrate or diamond (C) substrate.
  • Si silicon
  • Al2O3 silicon-on-insulator
  • SOI silicon-on-insulator
  • GaN gallium nitride
  • GaAs gallium arsenide
  • InP indium phosphide
  • AlN aluminum nitride
  • SiC silicon carbide
  • SiO2 quartz
  • C diamond
  • a gallium nitride layer 22 is disposed on the semiconductor substrate 21, and the gallium nitride layer 22 is preferably a gallium nitride layer without doping (magnesium Mg can be used as a dopant for doping).
  • An aluminum gallium nitride layer 23 is disposed on the gallium nitride layer 22 , and the aluminum gallium nitride layer 23 is preferably an undoped aluminum gallium nitride layer.
  • a P-type conductive layer 24 is arranged on the aluminum gallium nitride layer 23, and the P-type conductive layer 24 is located on the active area of the aluminum gallium nitride layer 23.
  • the P-type conductive layer 24 can be P-type gallium nitride or P-type nitrogen Aluminum Gallium Chloride.
  • the P-type GaN may be a beryllium-doped GaN layer, a Zn-doped GaN layer or a Mg-doped GaN layer.
  • the P-type conductive layer 24 is provided with a first metal layer 25, preferably, the material of the first metal layer can be titanium nitride (TiN) or tungsten (W), wherein, titanium nitride is a transition metal nitride, it Composed of ionic bonds, metal bonds and covalent bonds, it has high strength, high hardness, high temperature resistance, acid and alkali corrosion resistance, wear resistance and good electrical and thermal conductivity, as an excellent material for ohmic contact metals .
  • TiN titanium nitride
  • W tungsten
  • a first dielectric layer 26 is disposed on the first metal layer 25 , and the first dielectric layer 26 covers the first metal layer 25 , the P-type conductive layer 24 and the AlGaN layer 23 at the same time.
  • a gate metal layer 27 is disposed on the first dielectric layer 26 , a second dielectric layer 28 is disposed on the gate metal layer 27 , and a second metal layer 29 is disposed on the second dielectric layer 28 .
  • the first dielectric layer 26 can separate the gate metal layer 27 and the first metal layer 25, and the polarities of the first metal layer 25 and the gate metal layer 27 are opposite, so that the gate metal layer 27, the first dielectric layer 26 and the second A metal layer 25 constitutes the first capacitor (MIM), the second dielectric layer 28 separates the gate metal layer 27 and the second metal layer 29, and the polarities of the second metal layer 29 and the gate metal layer 27 are opposite, so that , the gate metal layer 27, the second dielectric layer 28 and the second metal layer 29 form a second capacitor (MIM).
  • MIM first capacitor
  • the first metal layer 25 and the second metal layer 29 are connected through the first conductor structure (not shown in the figure), the first end of the first capacitor is interconnected with the first end of the second capacitor, and the first end of the first capacitor is interconnected.
  • the two terminals are interconnected with the second terminal of the second capacitor, that is, the first capacitor and the second capacitor are connected in parallel, then the equivalent circuit diagram of the integrated device can be shown in FIG. 3 , and the dotted line connection in the circuit diagram indicates the same polarity.
  • the first capacitor and the second capacitor may be connected in parallel through other connection manners, and the first capacitor and the second capacitor may be connected in series through other connection manners, which are not limited herein.
  • the gate metal layer may be a positive electrode layer
  • the second metal layer may be a negative electrode layer.
  • the first conductor structure can be shown in FIG. 4 , the first metal layer 25 is connected to the metal M1 through the conductor D1 in the etching hole of the dielectric layer on it, and the second metal layer 29 is connected to the metal M1 through the conductor D1 of the dielectric layer on it.
  • the conductor D2 in the etched hole is connected to the metal M1, wherein the two metals M1 belong to the same piece of metal (not shown in the figure).
  • the gate metal layer and the titanium nitride layer can be separated by the first dielectric layer
  • the second dielectric layer can separate the gate metal layer and the second metal layer
  • the first metal layer and the second metal layer can be separated by the first conductor structure.
  • the second metal layer is connected, so that the first capacitor and the second capacitor are connected in parallel, so that the capacitance of the integrated device is increased, the withstand voltage of the integrated device is improved, and high voltage and high capacitance density are realized at the same time.
  • the application provides another structural schematic diagram of an integrated device as shown in Figure 5, the integrated device includes a semiconductor substrate 21, gallium nitride (GaN) layer 22 , aluminum gallium nitride (AlGaN) layer 23 , P-type conductive layer 24 , first metal layer 25 , first dielectric layer 26 , gate metal layer 27 , second dielectric layer 28 and second metal layer 29 .
  • GaN gallium nitride
  • AlGaN aluminum gallium nitride
  • semiconductor substrate 21 the material of this semiconductor substrate 21 can be silicon (Si) substrate, sapphire (Al2O3) substrate, silicon-on-insulator (SOI) substrate, gallium nitride (GaN) substrate, gallium arsenide ( GaAs) substrate, indium phosphide (InP) substrate, aluminum nitride (AlN) substrate, silicon carbide (SiC) substrate, quartz (SiO2) substrate or diamond (C) substrate.
  • Si silicon
  • Al2O3 silicon-on-insulator
  • SOI silicon-on-insulator
  • GaN gallium nitride
  • GaAs gallium arsenide
  • InP indium phosphide
  • AlN aluminum nitride
  • SiC silicon carbide
  • SiO2 quartz
  • C diamond
  • a gallium nitride layer 22 is disposed on the semiconductor substrate 21, and the gallium nitride layer 22 is preferably a gallium nitride layer without doping (magnesium Mg can be used as a dopant for doping).
  • An aluminum gallium nitride layer 23 is disposed on the gallium nitride layer 22 , and the aluminum gallium nitride layer 23 is preferably an undoped aluminum gallium nitride layer.
  • a P-type conductive layer 24 is arranged on the aluminum gallium nitride layer 23, and the P-type conductive layer 24 is located on the active area of the aluminum gallium nitride layer 23.
  • the P-type conductive layer 24 can be P-type gallium nitride or P-type nitrogen Aluminum Gallium Chloride. Taking p-type gallium nitride as an example, the p-type gallium nitride may be a beryllium-doped gallium nitride layer, a zinc-doped gallium nitride layer or a magnesium-doped gallium nitride layer;
  • the material of the first metal layer can be titanium nitride (TiN) or tungsten (W), wherein, titanium nitride is a transition metal nitride, it Composed of ionic bonds, metal bonds and covalent bonds, it has high strength, high hardness, high temperature resistance, acid and alkali corrosion resistance, wear resistance and good electrical and thermal conductivity, as an excellent material for ohmic contact metals .
  • a first dielectric layer 26 is disposed on the first metal layer 25 , and the first dielectric layer 26 covers the first metal layer 25 , the P-type conductive layer 24 and the AlGaN layer 23 at the same time.
  • a gate metal layer 27 is disposed on the first dielectric layer 26 , a second dielectric layer 28 is disposed on the gate metal layer 27 , and a second metal layer 29 is disposed on the second dielectric layer 28 .
  • the integrated device also includes a third metal layer 210, the third metal layer 210 and the aluminum gallium nitride layer 23, wherein the third metal layer 210 also passes through the first dielectric layer 26, the second dielectric layer 28 and the nitride
  • the AlGa layer 23 is connected to the GaN layer 22 .
  • the first dielectric layer 26 can separate the gate metal layer 27 and the first metal layer 25, and the polarities of the first metal layer 25 and the gate metal layer 27 are opposite, so that the gate metal layer 27, the first dielectric layer 26 and the second A metal layer 25 constitutes the first capacitor (MIM), the second dielectric layer 28 separates the gate metal layer 27 and the second metal layer 29, and the polarities of the second metal layer 29 and the gate metal layer 27 are opposite, so that , the gate metal layer 27, the second dielectric layer 28 and the second metal layer 29 constitute the second capacitor (MIM), and the first metal layer 25, the P-type conductive layer 24 and the two-dimensional electron gas 211 constitute the third capacitor (CJ).
  • MIM first capacitor
  • CJ third capacitor
  • the two-dimensional electron gas 211 is generated when the voltage between the gate metal layer 57 and the third metal layer 210 is within a preset range, and the voltage range of the junction capacitance is 5-7V.
  • the third metal layer 210 is in contact with the two-dimensional electron gas, and the polarity of the third metal layer 210 is opposite to that of the first metal layer 25 .
  • an aluminum nitride layer is further included between the gallium nitride layer and the aluminum gallium nitride layer, and the two-dimensional electron gas is located between the aluminum nitride layer and the gallium nitride layer, which can increase the electron concentration of the two-dimensional electron gas.
  • the first conductor structure and the second conductor structure can be copper or aluminum
  • the first end of the first capacitor, the first end of the second capacitor and the first end of the third capacitor are interconnected, and the second end of the first capacitor 1.
  • the second end of the second capacitor is interconnected with the second end of the third capacitor, that is, the first capacitor, the second capacitor and the third capacitor are connected in parallel, then the equivalent circuit diagram of the integrated device can be shown in reference 6.
  • first conductor and second conductor can refer to the relevant description of the first conductor in FIG. M2.
  • the two-dimensional electron gas corresponding to the first metal layer, the P-type conductive layer, and the third metal layer forms a third capacitor
  • the third metal layer is connected to the gate metal layer through the second conductor structure, so that The first capacitor, the second capacitor and the third capacitor are connected in parallel, so that the capacitance capacity of the integrated device is increased, the withstand voltage of the integrated device is improved, and the capacitance integration density of the integrated device can be further increased.
  • the integrated device includes a semiconductor substrate 21, a gallium nitride (GaN) layer 22, an aluminum gallium nitride (AlGaN) layer 23 , first dielectric layer 26 , gate metal layer 27 , second dielectric layer 28 and second metal layer 29 .
  • GaN gallium nitride
  • AlGaN aluminum gallium nitride
  • semiconductor substrate 21 the material of this semiconductor substrate 21 can be silicon (Si) substrate, sapphire (Al2O3) substrate, silicon-on-insulator (SOI) substrate, gallium nitride (GaN) substrate, gallium arsenide ( GaAs) substrate, indium phosphide (InP) substrate, aluminum nitride (AlN) substrate, silicon carbide (SiC) substrate, quartz (SiO2) substrate or diamond (C) substrate.
  • Si silicon
  • Al2O3 silicon-on-insulator
  • SOI silicon-on-insulator
  • GaN gallium nitride
  • GaAs gallium arsenide
  • InP indium phosphide
  • AlN aluminum nitride
  • SiC silicon carbide
  • SiO2 quartz
  • C diamond
  • a gallium nitride layer 22 is disposed on the semiconductor substrate 21, and the gallium nitride layer 22 is preferably a gallium nitride layer without doping (magnesium Mg can be used as a dopant for doping).
  • An aluminum gallium nitride layer 23 is disposed on the gallium nitride layer 22 , and the aluminum gallium nitride layer 23 is preferably an undoped aluminum gallium nitride layer.
  • a first dielectric layer 26 is disposed on the AlGaN layer 23, wherein the first dielectric layer 26 may include a fourth metal layer 261, wherein the fourth metal layer 261 may be P-type GaN or P-type AlN Ga, the fourth metal layer 261 is located on the active area of the AlGaN layer 23 .
  • the P-type GaN may be a GaN layer doped with Beryllium (Be), a GaN layer doped with Zinc (Zn), or a GaN layer doped with Magnesium (Mg).
  • the fourth metal layer may also include titanium nitride or tungsten, wherein the titanium nitride or tungsten completely separates the P-type gallium nitride and the gate metal layer 27 .
  • a gate metal layer 27 is disposed on the first dielectric layer 26 , a second dielectric layer 28 is disposed on the gate metal layer 27 , and a second metal layer 29 is disposed on the second dielectric layer 28 .
  • the first dielectric layer 26 is etched to expose the fourth metal layer 261 , and the gate metal layer 27 is formed on the etching hole formed by the etching.
  • the first dielectric layer 26 can separate the gate metal layer 27 and the aluminum gallium nitride layer 23, and the two-dimensional electron gas 211 under the aluminum gallium nitride layer 23 is connected to the second metal layer 29, since the first dielectric layer includes the second metal layer Four metal layers 261, the fourth metal layer 261 can be P-type gallium nitride or P-type aluminum gallium nitride, and the polarities of the second metal layer 29 and the gate metal layer 27 are opposite, so that the gate metal layer 27,
  • the first capacitance formed by the first dielectric layer 26 and the two-dimensional electron gas 211 is junction capacitance (CJ)
  • the second dielectric layer 28 separates the gate metal layer 27 and the second metal layer 29, and the second metal layer 29 and
  • the polarity of the gate metal layer 27 is opposite, so that the gate metal layer 27 , the second dielectric layer 28 and the second metal layer 29 form a second capacitor (MIM).
  • the two-dimensional electron gas 211 is generated when the voltage between the gate metal layer
  • an aluminum nitride layer is further included between the gallium nitride layer and the aluminum gallium nitride layer, and the two-dimensional electron gas is located between the aluminum nitride layer and the gallium nitride layer, which can increase the electron concentration of the two-dimensional electron gas.
  • the second metal layer passes through the second dielectric layer 28, the first dielectric layer 26 and the aluminum gallium nitride layer 23, and is in contact with the two-dimensional electron gas 211. At this time, the first terminal of the first capacitor is connected to the first terminal of the second capacitor.
  • the terminals are interconnected, the second terminal of the first capacitor is connected with the second terminal of the second capacitor, that is, the first capacitor and the second capacitor are connected in parallel, then the equivalent circuit diagram of the integrated device can be shown in FIG. 8 .
  • the first capacitor and the second capacitor may be connected in parallel through other connection manners, and the first capacitor and the second capacitor may be connected in series through other connection manners, which are not limited herein.
  • the gate metal layer may be a positive electrode layer
  • the second metal layer may be a negative electrode layer.
  • the gate metal layer, the first dielectric layer and the two-dimensional electron gas constitute the first capacitor
  • the gate metal layer, the second dielectric layer and the second metal layer constitute the second capacitor
  • the two-dimensional electron gas and the second The metal layers are related, so that the first capacitor and the second capacitor are connected in parallel, so that the capacitance capacity of the integrated device is increased, the withstand voltage of the integrated device is improved, and the capacitance integration density of the integrated device is increased.
  • the embodiment of the present application also provides another structural schematic diagram of an integrated device as shown in FIG. 9, the integrated device includes a semiconductor substrate 21, a nitrogen GaN layer 22 , AlGaN layer 23 , first dielectric layer 26 , gate metal layer 27 , second dielectric layer 28 and second metal layer 29 .
  • semiconductor substrate 21 the material of this semiconductor substrate 21 can be silicon (Si) substrate, sapphire (Al2O3) substrate, silicon-on-insulator (SOI) substrate, gallium nitride (GaN) substrate, gallium arsenide ( GaAs) substrate, indium phosphide (InP) substrate, aluminum nitride (AlN) substrate, silicon carbide (SiC) substrate, quartz (SiO2) substrate or diamond (C) substrate.
  • Si silicon
  • Al2O3 silicon-on-insulator
  • SOI silicon-on-insulator
  • GaN gallium nitride
  • GaAs gallium arsenide
  • InP indium phosphide
  • AlN aluminum nitride
  • SiC silicon carbide
  • SiO2 quartz
  • C diamond
  • a gallium nitride layer 22 is disposed on the semiconductor substrate 21, and the gallium nitride layer 22 is preferably a gallium nitride layer without doping (magnesium Mg can be used as a dopant for doping).
  • An aluminum gallium nitride layer 23 is disposed on the gallium nitride layer 22 , and the aluminum gallium nitride layer 23 is preferably an undoped aluminum gallium nitride layer.
  • a first dielectric layer 26 is arranged on the AlGaN layer 23, a gate metal layer 27 is arranged on the first dielectric layer 26, a second dielectric layer 28 is arranged on the gate metal layer 27, and a second dielectric layer 28 is arranged on the second dielectric layer 28. There is a second metal layer 29 .
  • the first dielectric layer 26 can separate the gate metal layer 27 and the aluminum gallium nitride layer 23.
  • the first dielectric layer 26 in the embodiment of the present application can be a common dielectric material, and the two-dimensional electron gas under the aluminum gallium nitride layer 23 211 is connected to the second metal layer 29, and the polarities of the second metal layer 29 and the gate metal layer 27 are opposite, so that the first capacitance formed by the gate metal layer 27, the first dielectric layer 26 and the two-dimensional electron gas 211
  • MIM inter-plate capacitance
  • the second dielectric layer 28 separates the gate metal layer 27 and the second metal layer 29, and the polarities of the second metal layer 29 and the gate metal layer 27 are opposite, so that the gate metal layer 27.
  • the second dielectric layer 28 and the second metal layer 29 form a second capacitor (MIM).
  • the two-dimensional electron gas 211 is generated when the voltage between the gate metal layer 27 and the second metal layer 29 is within a preset range, and the voltage range of the junction capacitance is 5-7V.
  • an aluminum nitride layer is further included between the gallium nitride layer and the aluminum gallium nitride layer, and the two-dimensional electron gas is located between the aluminum nitride layer and the gallium nitride layer, which can increase the electron concentration of the two-dimensional electron gas.
  • the second metal layer passes through the second dielectric layer 28, the first dielectric layer 26 and the aluminum gallium nitride layer 23, and connects with the two-dimensional electron gas 211. At this time, the first end of the first capacitor and the two ends of the second capacitor are connected, that is, the first capacitor and the second capacitor are connected in parallel, then the equivalent circuit diagram of the integrated device can be shown in FIG. 10 .
  • first capacitor and the second capacitor may be connected in parallel through other connection manners, and the first capacitor and the second capacitor may be connected in series through other connection manners, which are not limited herein.
  • the gate metal layer may be a positive electrode layer
  • the second metal layer may be a negative electrode layer.
  • the gate metal layer, the first dielectric layer and the two-dimensional electron gas constitute the first capacitor
  • the gate metal layer, the second dielectric layer and the second metal layer constitute the second capacitor
  • the two-dimensional electron gas and the second The potential of the two metal layers is the same, so that the first capacitance and the second capacitance are connected in parallel, and there is no junction capacitance, so that the capacitance capacity of the integrated device is increased, and the withstand voltage of the integrated device is improved, which can not only increase the capacitance integration density of the integrated device, but also realize High working voltage.
  • the number of capacitors in the integrated device is not limited to 2-3 or more than 3.
  • the integrated device may also include a fourth dielectric layer and a fourth metal layer, so that the integrated device One more capacitor can be added, or the gallium nitride layer and the aluminum gallium nitride layer can be divided into two parts, and the two-dimensional electron gas can be provided by different negative electrodes, that is, the integrated device can also include another junction capacitor or plate Between capacitors, whether to connect them in parallel or in series, you can connect the two ends of the capacitors through a conductor structure according to requirements, which is not limited here.
  • FIG. 11 is an embodiment of a manufacturing method of an integrated device provided by an embodiment of the present application.
  • the material of the semiconductor substrate may be silicon (Si) substrate, sapphire (Al2O3) substrate, silicon-on-insulator (SOI) substrate, gallium nitride (GaN) substrate, gallium arsenide ( GaAs) substrate, indium phosphide (InP) substrate, aluminum nitride (AlN) substrate, silicon carbide (SiC) substrate, quartz (SiO2) substrate or diamond (C) substrate.
  • a gallium nitride epitaxial wafer is grown on a semiconductor substrate as a buffer layer.
  • the gallium nitride layer is preferably a gallium nitride layer without doping (magnesium Mg can be used as a dopant for doping).
  • the thickness of the aluminum gallium nitride layer may be 25 nm to 35 nm, and the specific formation method may be to grow on the gallium nitride layer at a temperature of about 1100 ° C.
  • the aluminum gallium nitride layer is preferably undoped doped AlGaN layer.
  • a P-type conductive layer is formed on the active region of the AlGaN layer, and the P-type conductive layer is used to deplete the surface state negative electrons on the AlGaN layer and neutralize the AlGaN layer Hanging keys on layers.
  • the P-type conductive layer may be P-type GaN or P-type AlGaN.
  • the active area of the AlGaN layer is the area where the gate electrode, the source electrode, the drain electrode and/or the electrodes will be formed in the future.
  • photoresist is used to cover the area outside the active area, and then a P-type conductive layer is formed on the active area, and then the photoresist and the P-type conductive layer outside the active area are removed; in another In one implementation, a P-type conductive layer is formed on the AlGaN layer, and then a layer of photoresist is formed on the active area, and then the P-type conductive layer outside the active area is removed, and finally the photoresist is removed. glue.
  • the specific forming method can be selected according to actual needs, and will not be repeated here.
  • the first metal layer only covers the P-type conductive layer, and the first metal layer may be titanium nitride or tungsten, which can provide good conductivity.
  • titanium nitride is a transition metal nitride, which is composed of ionic bonds, metal bonds and covalent bonds. It has high strength, high hardness, high temperature resistance, acid and alkali corrosion resistance, wear resistance and good electrical conductivity. and thermal conductivity, as an excellent material for ohmic contact metals.
  • the first dielectric layer is formed on the first metal layer, and the first dielectric layer also covers the P-type conductive layer and the aluminum gallium nitride layer.
  • the first dielectric layer is used to separate the layers and maintain the insulation.
  • a layer of photoresist is covered on the first dielectric layer, and the photoresist is left in an uncovered area at the same position as the active area of the AlGaN layer, and then a gate is formed on the uncovered area.
  • the electrode metal layer, and then remove the photoresist and the gate metal layer outside the active area may also be another implementation manner in step 1101, which will not be repeated here.
  • the polarity of the gate metal layer and the first metal layer are opposite, and the gate metal layer and the first metal layer separated by the first dielectric layer form a first capacitor, and at this time, the first capacitor is an inter-plate capacitor.
  • a second dielectric layer is formed on the gate metal layer, and the second dielectric layer covers the first dielectric layer at the same time.
  • the second metal layer is directly formed on the second dielectric layer, the polarity of the second metal layer and the gate metal layer are opposite, and the gate metal layer and the second metal layer separated by the second dielectric layer layer constitutes the second capacitor.
  • the second capacitance is the inter-board capacitance.
  • the first conductor structure is used to connect the first metal layer and the second metal layer, so that the first end of the first capacitor and the first end of the second capacitor can be interconnected, and the second end of the first capacitor and the second end of the second capacitor can be interconnected.
  • the second terminals of the second capacitor are interconnected, that is, the first capacitor and the second capacitor are connected in parallel to realize an integrated device with high voltage range and high capacitance density.
  • the material of the first conductor structure may be copper or aluminum.
  • the gate metal layer and the titanium nitride layer can be separated by the first dielectric layer
  • the second dielectric layer can separate the gate metal layer and the second metal layer
  • the first metal layer and the second metal layer can be separated by the first conductor structure.
  • the second metal layer is connected, so that the first capacitor and the second capacitor are connected in parallel, so that the capacitance of the integrated device is increased, the withstand voltage of the integrated device is improved, and high voltage and high capacitance density are realized at the same time.
  • FIG. 12 is another embodiment of a manufacturing method of an integrated device provided by an embodiment of the present application.
  • a semiconductor substrate is provided.
  • steps 1201-1210 reference may be made to the related descriptions of steps 1101-1110 in the method shown in FIG. 12 , which will not be repeated here.
  • the first dielectric layer, the second dielectric layer, and the aluminum gallium nitride layer outside the P-type conductive layer area can be etched until the gallium nitride layer is exposed, and an etching hole is obtained, and then the etching hole can be obtained.
  • the third metal layer is formed by etching holes, and the polarity of the third metal layer is opposite to that of the first metal layer.
  • a second metal layer is generated under the aluminum gallium nitride layer.
  • the third metal layer is connected to the two-dimensional electron gas, that is, the polarity of the two-dimensional electron gas is opposite to that of the first metal layer.
  • the two-dimensional electron gas is located between the aluminum nitride layer and the gallium nitride layer.
  • the electron concentration of the two-dimensional electron gas can be increased.
  • the first metal layer, the P-type conductive layer and the two-dimensional electron gas together constitute a third capacitor.
  • the P-type conductive layer includes P-type gallium nitride or P-type aluminum gallium nitride
  • the third capacitor is a junction capacitor, and a second conductor structure can be used to connect the third metal layer and the gate metal layer, so that the first capacitor, the second capacitor, and the third capacitor are connected in parallel to obtain an integration with a higher capacitance density. device.
  • the material of the first conductor structure and the second conductor structure may be copper or aluminum.
  • the two-dimensional electron gas corresponding to the first metal layer, the P-type conductive layer, and the third metal layer forms a third capacitor
  • the third metal layer is connected to the gate metal layer through the second conductor structure, so that The first capacitor, the second capacitor and the third capacitor are connected in parallel, so that the capacitance capacity of the integrated device is increased, the withstand voltage of the integrated device is improved, and the capacitance integration density of the integrated device can be further increased.
  • FIG. 13 is another embodiment of a manufacturing method of an integrated device provided by an embodiment of the present application.
  • a semiconductor substrate is provided.
  • steps 1301-1303 reference may be made to the relevant description of steps 1101-1103 in the method shown in FIG. 11 , and details are not repeated here.
  • the first dielectric layer is formed on the AlGaN layer, wherein the first dielectric layer may include P-type GaN or P-type AlGaN.
  • the first dielectric layer is etched until the P-type gallium nitride or P-type aluminum gallium nitride in the first dielectric layer is exposed. Specifically, when the P-type gallium nitride or the P-type aluminum gallium nitride When titanium nitride is also provided on the aluminum gallium, it is only necessary to etch the first dielectric layer until the titanium nitride is exposed.
  • a gate metal layer is formed in the etching hole etched in the first dielectric layer, and the gate metal layer is connected to P-type gallium nitride or P-type aluminum gallium nitride.
  • the gate metal layer is connected with the titanium nitride.
  • a second dielectric layer is formed on the gate metal layer.
  • the second dielectric layer covers both the first dielectric layer and the gate metal layer.
  • the first dielectric layer, the second dielectric layer, and the aluminum gallium nitride layer outside the area of the gate metal layer can be etched to obtain an etching hole, and the gallium nitride is exposed at the bottom of the etching hole layer, and then a second metal layer can be formed on the etching hole and the second dielectric layer, the polarity of the second metal layer and the gate metal layer are opposite, and the gate metal layer separated by the second dielectric layer and the second metal layer form a first capacitance, the first capacitance is an inter-plate capacitance, and when the voltage between the gate metal layer and the second metal layer is within a preset range, a two-dimensional electron gas is generated under the aluminum gallium nitride layer, The two-dimensional electron gas is connected to the second metal layer, and the gate metal layer, the first dielectric layer and the two-dimensional electron gas together form a third capacitance (junction capacitance).
  • the potential of the second metal layer is the same as that of
  • the two-dimensional electron gas is located between the aluminum nitride layer and the gallium nitride layer.
  • the electron concentration of the two-dimensional electron gas can be increased.
  • the gate metal layer may be a positive electrode layer
  • the second metal layer may be a negative electrode layer.
  • the gate metal layer, the first dielectric layer and the two-dimensional electron gas constitute the first capacitor
  • the gate metal layer, the second dielectric layer and the second metal layer constitute the second capacitor
  • the two-dimensional electron gas and the second The metal layers are related, so that the first capacitor and the second capacitor are connected in parallel, so that the capacitance capacity of the integrated device is increased, the withstand voltage of the integrated device is improved, and the capacitance integration density of the integrated device is increased.
  • FIG. 14 is another embodiment of a manufacturing method of an integrated device provided by an embodiment of the present application.
  • a semiconductor substrate is provided.
  • steps 1401-1403 reference may be made to the relevant description of steps 1101-1103 in the method shown in FIG. 11 , and details are not repeated here.
  • the first dielectric layer covers the AlGaN layer, and the material of the first dielectric layer is a dielectric structure in the inter-board capacitor, which is used to separate different levels and provide insulation.
  • the gate metal layer is directly formed on the first dielectric layer, and then the gate metal layer on the active region of the aluminum gallium nitride layer is partially covered with photoresist, and then removed Gate metal layer not covered with photoresist, then remove photoresist.
  • the photoresist is covered on the first dielectric layer except the part above the active region of the aluminum gallium nitride layer, and then the gate is formed at the position of the first dielectric layer above the active region of the aluminum gallium nitride layer. electrode metal layer, and then remove the photoresist and the gate metal layer outside the active area.
  • the second dielectric layer is directly formed on the gate metal layer, and the second dielectric layer covers both the gate metal layer and the first dielectric layer.
  • the first dielectric layer, the second dielectric layer, and the aluminum gallium nitride layer outside the area of the gate metal layer can be etched to obtain an etching hole, and the gallium nitride is exposed at the bottom of the etching hole layer, and then a second metal layer can be formed on the etching hole and the second dielectric layer, the polarity of the second metal layer and the gate metal layer are opposite, and the gate metal layer separated by the second dielectric layer and the second metal layer form a first capacitance, the first capacitance is an inter-plate capacitance, and when the voltage between the gate metal layer and the second metal layer is within a preset range, a two-dimensional electron gas is generated under the aluminum gallium nitride layer, The second metal layer is connected to the two-dimensional electron gas.
  • the gate metal layer, the first dielectric layer and the two-dimensional electron gas together form a third capacitor.
  • the first dielectric layer does not include P-type gallium nitride or P-type aluminum nitride. gallium, the third capacitor is the inter-board capacitor.
  • the potential of the second metal layer is the same as that of the two-dimensional electron gas, so that both ends of the first capacitor and the second capacitor are interconnected, that is, the first capacitor and the second capacitor are connected in parallel.
  • the two-dimensional electron gas is located between the aluminum nitride layer and the gallium nitride layer.
  • the electron concentration of the two-dimensional electron gas can be increased.
  • the gate metal layer, the first dielectric layer and the two-dimensional electron gas constitute the first capacitor
  • the gate metal layer, the second dielectric layer and the second metal layer constitute the second capacitor
  • the two-dimensional electron gas and the second The potential of the two metal layers is the same, so that the first capacitor and the second capacitor are connected in parallel, and there is no junction capacitance, so that the capacitance capacity of the integrated device is increased, and the withstand voltage of the integrated device is improved, which can not only increase the capacitance integration density of the integrated device, but also achieve high operating voltage.
  • FIG. 15 is a schematic diagram of a possible structure of the driving circuit 150 provided by the embodiment of the present application.
  • the drive circuit 150 includes a gate driver 1501 and an integrated device 1502, wherein the gate drive device 1501 may include multiple current sources, and one or more of the multiple current sources may be the gate metal in the integrated device 1502 layer provides current to change the voltage of the gate metal layer.
  • the integrated device 1502 may be any one of the integrated devices shown in FIG. 2 , FIG. 5 , FIG. 7 and FIG. 9 .
  • FIG. 16 is a schematic diagram of a possible structure of an electronic device 160 provided by an embodiment of the present application.
  • the electronic device may be an adapter or a server.
  • the adapter may include the drive circuit 150 shown in FIG. , any of the integrated devices in Figure 7 and Figure 9.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种集成器件、半导体器件以及集成器件的制作方法，用于提高集成器件电容集成密度。本申请实施例集成器件包括：第一金属层上设置有第一介质层，第一金属层、第一介质层和第一介质层之上的栅极金属层构成第一电容，且栅极金属层、栅极金属层之上的第二介质层和第二介质层之上的第二金属层构成第二电容，采用第一导体结构连接第一金属和第二金属层，使得第一电容和第二电容并联连接。

Description

集成器件、半导体器件以及集成器件的制作方法 技术领域
本申请涉及一种微电子技术，尤其涉及一种集成器件、半导体器件以及集成器件的制作方法。
背景技术
氮化镓(GaN)功率器件因其导通电阻小，开通速度快等优点，在电源转换领域极具潜力。但是由于该器件栅极可承受的尖峰电压(10V)小于传统的硅器件，且阈值电压偏小(1.0～2.5V之间)，在快速开通过程中，由于板上寄生电感的缘故，使得器件栅极驱动波形容易发生振荡，进而造成器件栅极过压损坏或者器件误导通。为了解决该问题，可以在氮化镓器件的平台上，将栅极驱动电路和单管单片集成。
当前在单管工艺平台上，通常使用工艺流程中可获取的金属层来形成电容的极板(如场板层、栅金属层)，电容的集成受限于芯片面积。
该芯片面积中由于介质层厚度往往占用大面积，使得电容集成受到限制。
发明内容
本申请实施例提供了一种集成器件、半导体器件以及集成器件的制作方法，用于提高集成器件电容集成密度。
本申请第一方面提供了一种集成器件，包括：第一金属层；设于第一金属层之上的第一介质层；设于第一介质层之上的第二介质层；设于第一介质层与第二介质层之间的栅极金属层；以及，设于第二介质层之上的第二金属层；其中，第一金属层、第一介质层以及栅极金属层用于构成第一电容；第二金属层、第二介质层以及栅极金属层用于构成第二电容；第一金属层与第二金属层通过第一导体结构连接，以使得第一电容与第二电容并联连接。
上述第一方面中，栅极金属层、第一介质层和第一金属层构成第一电容，栅极金属层、第二介质层和第二金属层构成第二电容，即在一个集成器件中同时形成两个电容，且通过第一导体结构将第一金属层和第二金属层连接，使得第一电容和第二电容并联连接，使得集成器件中电容容量提高，即提高了集成器件的电容集成密度。
在一个可能的实施方式中，栅极金属层与第一金属层极性相反，第二金属层与栅极金属层极性相反。
在一个可能的实施方式中，集成器件还包括第三金属层，设于第一金属层之下的P型导电层；设于P型导电层之下的氮化铝镓层；氮化铝镓层之下包括二维电子气；第一金属层、P型导电层以及二维电子气用于构成第三电容；第三金属层穿过第二介质层、第一介质层和氮化铝镓层，与二维电子气相接，第三金属层与栅极金属层通过第二导体结构连接，以使得第一电容、第二电容和第三电容并联连接。
上述可能的实施方式中，二维电子气位于氮化铝镓层之下，该二维电子气由第三金属层和栅极金属层间的电压在预设范围内时生成。第一金属层、P型导电层以及二维电子气 构成第三电容，在集成器件上同时构成三个电容，且通过第二导体结构将第三金属层和栅极金属层相连，使得第一电容、第二电容和第三电容并联，可以进一步提高集成器件电容集成密度。
在一个可能的实施方式中，第三金属层与第一金属层极性相反。
在一个可能的实施方式中，氮化铝镓层设置在氮化铝层之上，二维电子气位于所述氮化铝层之下。
上述可能的实施方式中，二维电子气位于氮化铝层和氮化镓层之间，可以提高二维电子气的电子浓度。
在一个可能的实施方式中，P型导电层包括P型氮化镓或P型氮化铝镓。
在一个可能的实施方式中，第一金属层包括氮化钛或钨。
在一个可能的实施方式中，第一导体结构和第二导体结构的材料包括铜或铝。
本申请第二方面提供了一种集成器件，包括：氮化铝镓层；设于氮化铝镓层之上的第一介质层；设于第一介质层之上的第二介质层；设于第一介质层与第二介质层之间的栅极金属层；以及，设于第二介质层之上的第二金属层；其中，氮化铝镓层之下包括二维电子气；二维电子气、第一介质层以及栅极金属层用于构成第一电容；第二金属层、第二介质层以及栅极金属层用于构成第二电容；第二金属层穿过第二介质层、第一介质层和所述氮化铝镓层，与所述二维电子气相接，以使得所述第一电容与所述第二电容并联连接。
上述第二方面中，二维电子气位于氮化铝镓层之下，该二维电子气由第二金属层和栅极金属层间的电压在预设范围内时生成。栅极金属层、第一介质层和二维电子气构成第一电容，栅极金属层、第二介质层和第二金属层构成第二电容，同时在集成器件上形成两个电容，且二维电子气与第二金属层相连接，使得第一电容和第二电容并联，提高集成器件电容集成密度。
在一个可能的实施方式中，第二金属层与栅极金属层极性相反。
在一个可能的实施方式中，第一介质层包括P型氮化镓或P型氮化铝镓，栅极金属层穿过第一介质层，并形成于P型氮化镓或P型氮化铝镓之上。
在一个可能的实施方式中，氮化铝镓层设置在氮化铝层之上，二维电子气位于氮化铝层之下。
在一个可能的实施方式中，导体结构的材料包括铜或铝。
本申请第三方面提供了一种半导体器件，包括前述第一方面或第一方面任一种可选方式提供的集成器件，以及在集成器件上形成的半导体构成。
本申请第四方面提供了一种半导体器件，包括前述第二方面或第二方面任一种可选方式提供的集成器件，以及在集成器件上形成的半导体构成。
本申请第五方面提供了一种集成器件的制作方法，包括：在第一金属层上形成第一介质层；在第一介质层上形成栅极金属层；在栅极金属层上形成第二介质层；在第二介质层上形成第二金属层；其中，第一金属层、第一介质层以及栅极金属层用于构成第一电容；第二金属层、第二介质层以及栅极金属层用于构成第二电容；通过第一导体结构将第一金属层与第二金属层相连，以使得第一电容与第二电容并联连接。
在一个可能的实施方式中，该方法还包括：栅极金属层与第一金属层极性相反，第二金属层与栅极金属层极性相反。
在一个可能的实施方式中，该方法还包括：第一金属层形成于P型导电层之上，P型导电层形成于氮化铝镓层之上，氮化铝镓层之下包括二维电子气，第一金属层、P型导电层以及二维电子气用于构成第三电容；在第二介质层上形成第三金属层，第三金属层穿过第二介质层、第一介质层和氮化铝镓层，与二维电子气相接；通过第二导体结构将第三金属层与栅极金属层相连，以使得第一电容、第二电容和第三电容并联连接。
在一个可能的实施方式中，第三金属层与第一金属层极性相反。
在一个可能的实施方式中，氮化铝镓层形成于氮化铝层之上，二维电子气位于氮化铝层之下。
在一个可能的实施方式中，P型导电层包括P型氮化镓或P型氮化铝镓。
在一个可能的实施方式中，第一金属层包括氮化钛或钨。
在一个可能的实施方式中，第一导体结构和第二导体结构的材料包括铜或铝。
本申请第六方面提供了一种集成器件的制作方法，包括：在氮化铝镓层上形成第一介质层；在第一介质层上形成栅极金属层；在栅极金属层上形成第二介质层；在第二介质层上形成第二金属层；氮化铝镓层之下包括二维电子气，二维电子气、第一介质层以及栅极金属层用于构成第一电容；第二金属层、第二介质层以及栅极金属层用于构成第二电容；通过第二金属层穿过第二介质层、第一介质层和氮化铝镓层，与二维电子气相接，以使得第一电容与第二电容并联连接。
在一个可能的实施方式中，第二金属层与栅极金属层极性相反。
在一个可能的实施方式中，第一介质层包括P型氮化镓或P型氮化铝镓，栅极金属层穿过第一介质层，并形成于P型氮化镓或P型氮化铝镓之上。
在一个可能的实施方式中，氮化铝镓层形成于氮化铝层之上，二维电子气位于氮化铝层之下。
本申请第七方面提供了一种驱动电路，包括：栅极驱动器，以及第一方面和第二方面的任一种实施方式的集成器件，或使用第五方面和第六方面的任一种实施方式的方法所得到的集成器件；其中：该栅极驱动器为上述集成器件中的栅极提供电流。
本申请第八方面提供了一种电子设备，该电子设备包括第一方面和第二方面的任一种实施方式的集成器件，或使用第五方面和第六方面的任一种实施方式的方法所得到的集成器件。
附图说明
图1为本申请实施例提供的功率放大架构图；
图2为本申请实施例提供的集成器件的一结构示意图；
图3为本申请实施例提供的集成器件的等效电路图一示意图；
图4为本申请实施例提供的集成器件的另一结构示意图；
图5为本申请实施例提供的集成器件的等效电路图另一示意图；
图6为本申请实施例提供的集成器件的另一结构示意图；
图7为本申请实施例提供的集成器件的等效电路图另一示意图；
图8为本申请实施例提供的集成器件的另一结构示意图；
图9为本申请实施例提供的集成器件的等效电路图另一示意图；
图10为本申请实施例提供的集成器件的制作方法一实施例示意图；
图11为本申请实施例提供的集成器件的制作方法另一实施例示意图；
图12为本申请实施例提供的集成器件的制作方法另一实施例示意图；
图13为本申请实施例提供的集成器件的制作方法另一实施例示意图；
图14为本申请实施例提供的集成器件的制作方法另一实施例示意图；
图15为本申请实施例提供的驱动电路示意图；
图16为本申请实施例提供的电子设备示意图。
具体实施方式
本申请实施例提供了一种集成器件、半导体器件以及集成器件的制作方法，用于提高集成器件电容集成密度。
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例中所谓的“上”和“下”是基于功率器件的工艺流程来说的，以“衬底”作为底面，相对于“衬底”，延竖直路径背离“衬底”的方向为“上”，同时，延“衬底”没有设置其他层级的竖直路径的方向为“下”。
应理解，关于例如“A设于B之上”的相关表述，仅体现A在空间意义上位于B的上方，并不限定A和B之间的连接关系，示例性的，在A设于B之上的情况下，A和B可以直接接触；也可以不直接接触，例如：A和B之间可以包括C，其中，C可以不完全隔开A和B，也可以完全隔开A和B。
下面对本申请实施例中的一些关键术语进行解释。
氮化镓(GaN)：氮化镓(GaN)是一种具有较大禁带宽度的半导体，属于宽禁带半导体之列。氮化镓是微波功率晶体管的优良材料，是研制微电子器件、光电子器件的新型半导体材料，具有宽的直接带隙、强的原子键、高的热导率、化学稳定性好(几乎不被任何酸腐蚀)等性质和强的抗辐照能力。
二维电子气(Two-dimensional electron gas，2DEG)：是指电子气可以自由在二维方向移动，而在第三维上受到限制的现象，二维电子气位于氮化镓器件平台中氮化铝镓层和氮化镓层之间，该二维电子气也可以称为沟道电子。它是许多场效应器件(例如MOSFET、HEMT)工作的基础。
金属-介质-金属(metal-insulators-metal，MIM)电容(也叫板间电容)，MIM电容器对晶体管造成的干扰最小，且可以提供较好的线形度(Linearity)和对称度(Symmetry)，因此得到了更加广泛的应用，特别是混合信号和射频领域。
本申请实施例的集成器件可以应用于任何提高集成电容密度的场景，本申请实施例以氮化镓器件为例。请参阅图1，图1为本申请实施例提供的功率放大架构图，该架构图包括输入模块11，功率放大器12和输出模块13。功率放大器12可以对输入模块11的输出功率进行放大，然后再输出到输出模块13。由于世界各国的电网电压变化很大，比如国家A的交流电电压为220V，相对比较稳定。而国家B的电网电压波动比较大，从90VAC至350VAC不等。宽输入电压范围工作要求输入滤波电容具有更大的容量(低压时)，以及更高的耐压额定值(高压时)。为支持更高的耐压，电容制造商必须增加电容的尺寸，导致体积增加很多。采用氮化镓(GaN)器件可以提升开关频率，从而降低变压器的尺寸，即，功率放大器12为氮化镓(GaN)器件，GaN器件是具有更大带宽、更高放大器增益、更高能效、尺寸更小的半导体器件。相对于其他功率放大器，由于GaN禁带宽度大、导热率高，GaN器件可在200℃以上的高温下工作，能够承载更高的能量密度，可靠性更高；较大禁带宽度和绝缘破坏电场，使得器件导通电阻减少，有利于提升器件整体的能效；电子饱和速度快，以及较高的载流子迁移率，可让器件高速地工作。
目前在单管工艺平台上，通常使用工艺流程中可获取的金属层次来形成电容的极板(如场板层、栅金属层)，因此，电容的集成受限于介质层厚度，而介质层往往占用芯片的大部分结构，电容的集成受限于芯片面积。
为了解决上述问题，本申请实施例提供了一种集成器件，下面对该集成器件的结构进行描述。
请参阅图2，如图2所示为本申请实施例提供的集成器件的结构示意图，该集成器件包括半导体衬底21、氮化镓(GaN)层22、氮化铝镓(AlGaN)层23、P型导电层24、第一金属层25、第一介质层26、栅极金属层27、第二介质层28和第二金属层29。
半导体衬底21，该半导体衬底21的材料可以是硅(Si)衬底、蓝宝石(Al2O3)衬底、绝缘体上硅(SOI)衬底、氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底、氮化铝(AlN)衬底、碳化硅(SiC)衬底、石英(SiO2)衬底或金刚石(C)衬底。
半导体衬底21上设置有氮化镓层22，该氮化镓层22优选为不掺杂(掺杂可以是采用镁Mg作为掺杂剂)的氮化镓层。
氮化镓层22上设置有氮化铝镓层23，该氮化铝镓层23优选为不掺杂的氮化铝镓层。
氮化铝镓层23上设置有P型导电层24，P型导电层24位于氮化铝镓层23的有源区上，该P型导电层24可以是P型氮化镓或P型氮化铝镓。以P型氮化镓为例，该P型氮化镓可以为掺铍的氮化镓层、掺锌的氮化镓层或掺镁的氮化镓层。
P型导电层24上设置有第一金属层25，优选地，该第一金属层的材料可以为氮化钛(TiN)或钨(W)，其中，氮化钛是过渡金属氮化物，它由离子键、金属键和共价键混合而成，它具有高强度、高硬度、耐高温、耐酸碱侵蚀、耐磨损以及良好的导电性和导热性，作为欧姆接触金属的极佳材料。
第一金属层25上设置有第一介质层26，该第一介质层26同时覆盖在第一金属层25、P型导电层24和氮化铝镓层23上。
第一介质层26上设置有栅极金属层27，栅极金属层27上设置有第二介质层28，第二介质层28上设置有第二金属层29。
第一介质层26可以分隔栅极金属层27和第一金属层25，且第一金属层25和栅极金属层27的极性相反，使得栅极金属层27、第一介质层26和第一金属层25构成第一电容(MIM)，第二介质层28分隔开栅极金属层27和第二金属层29，且第二金属层29和栅极金属层27的极性相反，使得，栅极金属层27、第二介质层28和第二金属层29构成第二电容(MIM)。当第一金属层25与第二金属层29通过第一导体结构(图中未示出)连接，此时第一电容的第一端与第二电容的第一端互联，第一电容的第二端和第二电容的第二端互联，即第一电容和第二电容并联连接，则该集成器件的等效电路图可以参照图3所示，电路图中虚线连接表示极性相同。其中，也可以通过其他连接方式使得第一电容和第二电容并联连接，也可以通过其他连接方式使得第一电容和第二电容串联连接，此处不作限定。本申请实施例中，栅极金属层可以是正电极层，第二金属层为负电极层。
具体的，第一导体结构可以参照图4所示，第一金属层25通过其上的介质层的刻蚀孔中的导体D1连接到金属M1，第二金属层29通过其上的介质层的刻蚀孔中的导体D2连接到金属M1，其中，两个金属M1属于同一块金属(图中未示出)。
本申请实施例通过第一介质层可以分隔栅极金属层和氮化钛层，第二介质层分隔开栅极金属层和第二金属层，且通过第一导体结构使得第一金属层和第二金属层相连，使得第一电容和第二电容并联，使得集成器件的电容容量增大，提高集成器件的耐压性，同时实现了高电压与高电容密度。
对于不需要限制电压范围的集成器件，为实现更高的电容密度，本申请提供了如图5所示的集成器件另一结构示意图，该集成器件包括半导体衬底21、氮化镓(GaN)层22、氮化铝镓(AlGaN)层23、P型导电层24、第一金属层25、第一介质层26、栅极金属层27、第二介质层28和第二金属层29。
半导体衬底21，该半导体衬底21的材料可以是硅(Si)衬底、蓝宝石(Al2O3)衬底、绝缘体上硅(SOI)衬底、氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底、氮化铝(AlN)衬底、碳化硅(SiC)衬底、石英(SiO2)衬底或金刚石(C)衬底。
半导体衬底21上设置有氮化镓层22，该氮化镓层22优选为不掺杂(掺杂可以是采用镁Mg作为掺杂剂)的氮化镓层。
氮化镓层22上设置有氮化铝镓层23，该氮化铝镓层23优选为不掺杂的氮化铝镓层。
氮化铝镓层23上设置有P型导电层24，P型导电层24位于氮化铝镓层23的有源区 上，该P型导电层24可以是P型氮化镓或P型氮化铝镓。以P型氮化镓为例，该P型氮化镓可以为掺铍的氮化镓层、掺锌的氮化镓层或掺镁的氮化镓层；
P型导电层24上设置有第一金属层25，优选的，该第一金属层的材料可以为氮化钛(TiN)或钨(W)，其中，氮化钛是过渡金属氮化物，它由离子键、金属键和共价键混合而成，它具有高强度、高硬度、耐高温、耐酸碱侵蚀、耐磨损以及良好的导电性和导热性，作为欧姆接触金属的极佳材料。
第一金属层25上设置有第一介质层26，该第一介质层26同时覆盖在第一金属层25、P型导电层24和氮化铝镓层23上。
第一介质层26上设置有栅极金属层27，栅极金属层27上设置有第二介质层28，第二介质层28上设置有第二金属层29。
集成器件还包括第三金属层210，该第三金属层210与氮化铝镓层23，其中，该第三金属层210还穿过第一介质层26、第二介质层28和该氮化铝镓层23，与氮化镓层22相连接。
第一介质层26可以分隔栅极金属层27和第一金属层25，且第一金属层25和栅极金属层27的极性相反，使得栅极金属层27、第一介质层26和第一金属层25构成第一电容(MIM)，第二介质层28分隔开栅极金属层27和第二金属层29，且第二金属层29和栅极金属层27的极性相反，使得，栅极金属层27、第二介质层28和第二金属层29构成第二电容(MIM)，第一金属层25、P型导电层24和二维电子气211构成第三电容(CJ)，二维电子气211由栅极金属层57和第三金属层210间的电压在预设范围内时生成，结电容的电压使用范围为5～7V。第三金属层210与二维电子气相接，且第三金属层210与第一金属层25的极性相反。
可选的，氮化镓层和氮化铝镓层之间还包括氮化铝层，二维电子气位于氮化铝层和氮化镓层之间，可以提高二维电子气的电子浓度。当第一金属层25通过第一导体结构(图中未示出)与第二金属层29相连，且第三金属层210与栅极金属层27通过第二导体结构(图中未示出)相连时，第一导体结构和第二导体结构可以是铜或铝，第一电容的第一端、第二电容的第一端和第三电容的第一端互联，第一电容的第二端、第二电容的第二端和第三电容的第二端互联，即，第一电容、第二电容和第三电容并联，则该集成器件的等效电路图可以参照6所示。
上述第一导体和第二导体可以参照图4中第一导体的相关描述，第一金属层25和第二金属层29分别连接金属M1，第三金属层210与栅极金属层27分别连接金属M2。
本申请实施例中，第一金属层、P型导电层和第三金属层对应的二维电子气构成第三电容，且通过第二导体结构将第三金属层和栅极金属层相连，使得第一电容、第二电容和第三电容并联，使得集成器件的电容容量增大，提高集成器件的耐压性，可以进一步提高集成器件电容集成密度。
请参阅图7，如图7所示为本申请实施例提供的集成器件的另一结构示意图，该集成器件包括半导体衬底21、氮化镓(GaN)层22、氮化铝镓(AlGaN)层23、第一介质层26、 栅极金属层27、第二介质层28和第二金属层29。
半导体衬底21，该半导体衬底21的材料可以是硅(Si)衬底、蓝宝石(Al2O3)衬底、绝缘体上硅(SOI)衬底、氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底、氮化铝(AlN)衬底、碳化硅(SiC)衬底、石英(SiO2)衬底或金刚石(C)衬底。
半导体衬底21上设置有氮化镓层22，该氮化镓层22优选为不掺杂(掺杂可以是采用镁Mg作为掺杂剂)的氮化镓层。
氮化镓层22上设置有氮化铝镓层23，该氮化铝镓层23优选为不掺杂的氮化铝镓层。
氮化铝镓层23上设置有第一介质层26，其中，第一介质层26可以包括第四金属层261，其中，第四金属层261可以是P型氮化镓或P型氮化铝镓，第四金属层261位于氮化铝镓层23的有源区上。以P型氮化镓为例，该P型氮化镓可以为掺铍(Be)的氮化镓层、掺锌(Zn)的氮化镓层或掺镁(Mg)的氮化镓层。可选的，该第四金属层还可以包括氮化钛或钨，其中，该氮化钛或钨完全隔开P型氮化镓和栅极金属层27。
第一介质层26上设置有栅极金属层27，栅极金属层27上设置有第二介质层28，第二介质层28上设置有第二金属层29。此时，第一介质层26经刻蚀露出上述第四金属层261，栅极金属层27为在该刻蚀形成的刻蚀孔上形成的。
第一介质层26可以分隔栅极金属层27和氮化铝镓层23，氮化铝镓层23之下的二维电子气211与第二金属层29相连接，由于第一介质层包括第四金属层261，该第四金属层261可以是P型氮化镓或P型氮化铝镓，且第二金属层29和栅极金属层27的极性相反，使得栅极金属层27、第一介质层26和二维电子气211构成的第一电容为结电容(CJ)，第二介质层28分隔开栅极金属层27和第二金属层29，且第二金属层29和栅极金属层27的极性相反，使得栅极金属层27、第二介质层28和第二金属层29构成第二电容(MIM)。二维电子气211由栅极金属层27和第二金属层29间的电压在预设范围内时生成，结电容的电压使用范围为5～7V。
可选的，氮化镓层和氮化铝镓层之间还包括氮化铝层，二维电子气位于氮化铝层和氮化镓层之间，可以提高二维电子气的电子浓度。第二金属层穿过第二介质层28、第一介质层26和氮化铝镓层23，与二维电子气211相接，此时第一电容的第一端与第二电容的第一端互联，第一电容的第二端和第二电容的第二端互联，即第一电容和第二电容并联连接，则该集成器件的等效电路图可以参照图8所示。其中，也可以通过其他连接方式使得第一电容和第二电容并联连接，也可以通过其他连接方式使得第一电容和第二电容串联连接，此处不作限定。
本申请实施例中，栅极金属层可以是正电极层，第二金属层为负电极层。本申请实施例通过栅极金属层、第一介质层和二维电子气构成第一电容，栅极金属层、第二介质层和第二金属层构成第二电容，二维电子气与第二金属层相关，使得第一电容和第二电容并联，使得集成器件的电容容量增大，提高集成器件的耐压性，提高集成器件电容集成密度。
对于图2所示的既满足高电压使用又具备高电容密度的电容器，本申请实施例还提供了如图9所示的集成器件的另一结构示意图，该集成器件包括半导体衬底21、氮化镓层22、 氮化铝镓层23、第一介质层26、栅极金属层27、第二介质层28和第二金属层29。
半导体衬底21，该半导体衬底21的材料可以是硅(Si)衬底、蓝宝石(Al2O3)衬底、绝缘体上硅(SOI)衬底、氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底、氮化铝(AlN)衬底、碳化硅(SiC)衬底、石英(SiO2)衬底或金刚石(C)衬底。
半导体衬底21上设置有氮化镓层22，该氮化镓层22优选为不掺杂(掺杂可以是采用镁Mg作为掺杂剂)的氮化镓层。
氮化镓层22上设置有氮化铝镓层23，该氮化铝镓层23优选为不掺杂的氮化铝镓层。
氮化铝镓层23上设置有第一介质层26，第一介质层26上设置有栅极金属层27，栅极金属层27上设置有第二介质层28，第二介质层28上设置有第二金属层29。
第一介质层26可以分隔栅极金属层27和氮化铝镓层23，本申请实施例的第一介质层26可以是普通的介质材料，氮化铝镓层23之下的二维电子气211与第二金属层29相连接，且第二金属层29和栅极金属层27的极性相反，使得栅极金属层27、第一介质层26和二维电子气211构成的第一电容为板间电容(MIM)，第二介质层28分隔开栅极金属层27和第二金属层29，且第二金属层29和栅极金属层27的极性相反，使得栅极金属层27、第二介质层28和第二金属层29构成第二电容(MIM)。二维电子气211由栅极金属层27和第二金属层29间的电压在预设范围内时生成，结电容的电压使用范围为5～7V。
可选的，氮化镓层和氮化铝镓层之间还包括氮化铝层，二维电子气位于氮化铝层和氮化镓层之间，可以提高二维电子气的电子浓度。第二金属层穿过第二介质层28、第一介质层26和氮化铝镓层23，与二维电子气211相接，此时第一电容的第一端和第二电容的两端相连，即第一电容和第二电容并联连接，则该集成器件的等效电路图可以参照图10所示。其中，也可以通过其他连接方式使得第一电容和第二电容并联连接，也可以通过其他连接方式使得第一电容和第二电容串联连接，此处不作限定。本申请实施例中，栅极金属层可以是正电极层，第二金属层为负电极层。
本申请实施例中，栅极金属层、第一介质层和二维电子气构成第一电容，栅极金属层、第二介质层和第二金属层构成第二电容，二维电子气与第二金属层电位相同，使得第一电容和第二电容并联，且没有结电容，使得集成器件的电容容量增大，提高集成器件的耐压性，既可以提高集成器件电容集成密度，又可以实现高工作电压。
本申请实施例中，集成器件中的电容数量不限于2-3个或3个以上，示例性的，该集成器件上还可以包括一个第四介质层和一个第四金属层，使得该集成器件集多一个电容，又或者还可以将氮化镓层和氮化铝镓层分成两部分，分别由不同的负电极提供二维电子气，即该集成器件上还可以包括另外的结电容或板间电容，具体要并联还是串联可以根据需求通过导体结构连接电容的两端，此处不作限定。
请参阅图11，图11为本申请实施例提供的一种集成器件的制作方法一实施例。
1101.提供半导体衬底。
本申请实施例中，该半导体衬底的材料可以是硅(Si)衬底、蓝宝石(Al2O3)衬底、 绝缘体上硅(SOI)衬底、氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底、氮化铝(AlN)衬底、碳化硅(SiC)衬底、石英(SiO2)衬底或金刚石(C)衬底。
1102.在半导体衬底上形成氮化镓层。
本申请实施例中，在半导体衬底上生长氮化镓外延片，作为一个缓冲层。该氮化镓层优选为不掺杂(掺杂可以是采用镁Mg作为掺杂剂)的氮化镓层。
1103.在氮化镓层上形成氮化铝镓层。
本申请实施例中，该氮化铝镓层的厚度可以为25nm～35nm，具体形成方法可以是在大约1100℃的温度中生长在氮化镓层上，该氮化铝镓层优选为不掺杂的氮化铝镓层。
1104.在氮化铝镓层上形成P型导电层。
本申请实施例中，在氮化铝镓层的有源区上形成P型导电层，该P型导电层用于耗尽氮化铝镓层上的表面态负电子并中和氮化铝镓层上的悬挂键。P型导电层可以是P型氮化镓或P型氮化铝镓。
氮化铝镓层的有源区即为将来要形成栅电极、源电极、漏电极和/或各电极之间的区域。
在一种实现方式下，采用光刻胶覆盖有源区以外的区域，然后再在有源区上形成P型导电层，接着去除光刻胶以及有源区以外的P型导电层；在另一种实现方式下，在氮化铝镓层上形成P型导电层，然后在有源区上形成一层光刻胶，接着将有源区以外的P型导电层去除，最后再去除光刻胶。具体形成方式可以根据实际需要进行选择，在此不再赘述。
1105.在P型导电层上形成第一金属层。
本申请实施例中，第一金属层只覆盖P型导电层，该第一金属层可以是氮化钛或钨，可以提供良好的导电性。其中，氮化钛是过渡金属氮化物，它由离子键、金属键和共价键混合而成，它具有高强度、高硬度、耐高温、耐酸碱侵蚀、耐磨损以及良好的导电性和导热性，作为欧姆接触金属的极佳材料。
1106.在第一金属层上形成第一介质层。
本申请实施例中，在第一金属层上形成第一介质层，该第一介质层同时也覆盖P型导电层和氮化铝镓层，该第一介质层用于分隔层级并保持层级间的绝缘性。
1107.在第一介质层上形成栅极金属层。
本申请实施例中，在第一介质层上覆盖一层光刻胶，将该光刻胶保留氮化铝镓层有源区相同位置的一个未覆盖区，然后再在未覆盖区上形成栅极金属层，接着去除光刻胶以及有源区以外的栅极金属层。也可以是步骤1101中的另一种实现方式，此处不再赘述。
栅极金属层和第一金属层的极性相反，由第一介质层分隔的栅极金属层和第一金属层构成第一电容，此时，第一电容为板间电容。
1108.在栅极金属层上形成第二介质层。
本申请实施例中，在栅极金属层上形成第二介质层，该第二介质层同时覆盖第一介质层。
1109.在第二介质层上形成第二金属层。
本申请实施例中，直接在第二介质层上形成第二金属层，第二金属层和栅极金属层的极性相反，由第二介质层分隔开的栅极金属层和第二金属层构成第二电容。第二电容为板 间电容。
1110.通过第一导体结构将第一金属层和第二金属层相连。
本申请实施例中，采用第一导体结构连接第一金属层和第二金属层，可以使得第一电容的第一端和第二电容的第一端互连，第一电容的第二端和第二电容的第二端互连，即第一电容和第二电容并联连接，实现高电压范围与高电容密度的集成器件。
可选的，第一导体结构的材料可以是铜或铝等。
本申请实施例通过第一介质层可以分隔栅极金属层和氮化钛层，第二介质层分隔开栅极金属层和第二金属层，且通过第一导体结构使得第一金属层和第二金属层相连，使得第一电容和第二电容并联，使得集成器件的电容容量增大，提高集成器件的耐压性，同时实现了高电压与高电容密度。
请参阅图12，图12为本申请实施例提供的一种集成器件的制作方法另一实施例。
1201.提供半导体衬底。
1202.在半导体衬底上形成氮化镓层。
1203.在氮化镓层上形成氮化铝镓层。
1204.在氮化铝镓层上形成P型导电层。
1205.在P型导电层上形成第一金属层。
1206.在第一金属层上形成第一介质层。
1207.在第一介质层上形成栅极金属层。
1208.在栅极金属层上形成第二介质层。
1209.在第二介质层上形成第二金属层。
1210.通过第一导体结构将第一金属层和第二金属层相连。
本申请实施例中，步骤1201-1210可以参照图12所示的方法中步骤1101-1110的相关描述，此处不再赘述。
1211.在氮化铝镓层上形成第三金属层。
本申请实施例可以对P型导电层区域外的第一介质层、第二介质层和氮化铝镓层进行刻蚀，直到露出氮化镓层，并获得刻蚀孔，然后可以在该刻蚀孔形成第三金属层，第三金属层与第一金属层的极性相反，由栅极金属层和第三金属层间的电压在预设范围内时在氮化铝镓层下生成二维电子气，此时第三金属层与二维电子气相连，即二维电子气和第一金属层的极性相反。
可选的，氮化铝镓层与氮化镓器件平台中的氮化镓层之间还可以有氮化铝层，此时二维电子气位于氮化铝层和氮化镓层之间，可以提高二维电子气的电子浓度。
1212.通过第二导体结构将第三金属层与栅极金属层相连。
本申请实施例中，第一金属层、P型导电层和二维电子气共同构成了一个第三电容，由于该P型导电层中包括P型氮化镓或P型氮化铝镓，则该第三电容为结电容，可以采用一个第二导体结构将第三金属层和栅极金属层相连，以使得第一电容、第二电容和第三电容并联，得到一个更高电容密度的集成器件。第一导体结构和第二导体结构的材料可以是 铜或铝。
本申请实施例中，第一金属层、P型导电层和第三金属层对应的二维电子气构成第三电容，且通过第二导体结构将第三金属层和栅极金属层相连，使得第一电容、第二电容和第三电容并联，使得集成器件的电容容量增大，提高集成器件的耐压性，可以进一步提高集成器件电容集成密度。
请参阅图13，图13为本申请实施例提供的一种集成器件的制作方法另一实施例。
1301.提供半导体衬底。
1302.在半导体衬底上形成氮化镓层。
1303.在氮化镓层上形成氮化铝镓层。
本申请实施例中，步骤1301-1303可以参照图11所示方法中步骤1101-1103的相关描述，此处不再赘述。
1304.在氮化铝镓层上形成第一介质层。
本申请实施例中，在氮化铝镓层上形成第一介质层，其中，第一介质层可以包含P型氮化镓或P型氮化铝镓。
1305.通过在第一介质层上刻蚀，露出P型氮化镓或P型氮化铝镓。
本申请实施例中，对第一介质层进行刻蚀，直到露出第一介质层中的P型氮化镓或P型氮化铝镓，具体的，当P型氮化镓或P型氮化铝镓上还设有氮化钛时，只需要对第一介质层刻蚀直到露出氮化钛。
1306.在P型氮化镓或P型氮化铝镓上形成栅极金属层。
本申请实施例中，在第一介质层刻蚀出的刻蚀孔中形成栅极金属层，该栅极金属层与P型氮化镓或P型氮化铝镓相连。当P型氮化镓或P型氮化铝镓上还设有氮化钛时，该栅极金属层与氮化钛相连。
1307.在栅极金属层上形成有第二介质层。
本申请实施例中，该第二介质层同时覆盖第一介质层和栅极金属层。
1308.在第二介质层上形成第二金属层。
本申请实施例中，可以对栅极金属层区域外的第一介质层、第二介质层和氮化铝镓层进行刻蚀，以获得刻蚀孔，该刻蚀孔底端露出氮化镓层，然后可以在这个刻蚀孔以及第二介质层上形成第二金属层，第二金属层和栅极金属层的极性相反，此时由第二介质层分隔开的栅极金属层和第二金属层构成第一电容，第一电容为板间电容，栅极金属层和第二金属层间的电压在预设范围内时在氮化铝镓层下生成了二维电子气，该二维电子气与第二金属层相连，栅极金属层、第一介质层和二维电子气共同构成了一个第三电容(结电容)。第二金属层和二维电子气电位相同，使得第一电容和第二电容的两端互连，即得第一电容和第二电容并联连接。
可选的，氮化铝镓层与氮化镓器件平台中的氮化镓层之间还可以有氮化铝层，此时二维电子气位于氮化铝层和氮化镓层之间，可以提高二维电子气的电子浓度。
本申请实施例中，栅极金属层可以是正电极层，第二金属层为负电极层。本申请实施 例通过栅极金属层、第一介质层和二维电子气构成第一电容，栅极金属层、第二介质层和第二金属层构成第二电容，二维电子气与第二金属层相关，使得第一电容和第二电容并联，使得集成器件的电容容量增大，提高集成器件的耐压性，提高集成器件电容集成密度。
请参阅图14，图14为本申请实施例提供的一种集成器件的制作方法另一实施例。
1401.提供半导体衬底。
1402.在半导体衬底上形成氮化镓层。
1403.在氮化镓层上形成氮化铝镓层。
本申请实施例中，步骤1401-1403可以参照图11所示方法中步骤1101-1103的相关描述，此处不再赘述。
1404.在氮化铝镓层上形成第一介质层。
本申请实施例中，第一介质层覆盖氮化铝镓层，该第一介质层的材料为板间电容中的介质结构，用于分隔不同层级并提供绝缘性。
1405.在第一介质层上形成栅极金属层。
本申请实施例中，一种实施方式，直接在第一介质层上形成栅极金属层，然后对处于氮化铝镓层有源区之上的栅极金属层部分覆盖光刻胶，再去除没有覆盖光刻胶的栅极金属层，然后去除光刻胶。
另一种实施方式，在第一介质层上覆盖除了氮化铝镓层有源区之上部分的光刻胶，然后在氮化铝镓层有源区之上的第一介质层位置形成栅极金属层，然后去除光刻胶以及有源区外的栅极金属层。
1406.在栅极金属层上形成第二介质层。
本申请实施例中，直接在栅极金属层上形成第二介质层，该第二介质层同时覆盖栅极金属层和第一介质层。
1407.在第二介质层上形成第二金属层。
本申请实施例中，可以对栅极金属层区域外的第一介质层、第二介质层和氮化铝镓层进行刻蚀，以获得刻蚀孔，该刻蚀孔底端露出氮化镓层，然后可以在这个刻蚀孔以及第二介质层上形成第二金属层，第二金属层和栅极金属层的极性相反，此时由第二介质层分隔开的栅极金属层和第二金属层构成第一电容，第一电容为板间电容，栅极金属层和第二金属层间的电压在预设范围内时在氮化铝镓层下生成了二维电子气，第二金属层与二维电子气相连接，栅极金属层、第一介质层和二维电子气共同构成了一个第三电容，第一介质层不包括P型氮化镓或P型氮化铝镓，则第三电容为板间电容。
第二金属层和二维电子气电位相同，使得第一电容和第二电容的两端互连，即得第一电容和第二电容并联连接。
可选的，氮化铝镓层与氮化镓器件平台中的氮化镓层之间还可以有氮化铝层，此时二维电子气位于氮化铝层和氮化镓层之间，可以提高二维电子气的电子浓度。
本申请实施例中，栅极金属层、第一介质层和二维电子气构成第一电容，栅极金属层、第二介质层和第二金属层构成第二电容，二维电子气与第二金属层电位相同，使得第一电 容和第二电容并联连接，且没有结电容，使得集成器件的电容容量增大，提高集成器件的耐压性，既可以提高集成器件电容集成密度，又可以实现高工作电压。
图15所示，为本申请的实施例提供的驱动电路150的一种可能的结构示意图。该驱动电路150包括栅极驱动器1501和集成器件1502，其中，栅极驱动器件1501中可以包括多个电流源，该多个电流源中的一个或多个可以为集成器件1502中的栅极金属层提供电流，以改变栅极金属层的电压。该集成器件1502可以是图2、图5、图7和图9中的集成器件中任一个。
图16所示，为本申请的实施例提供的电子设备160的一种可能的结构示意图。该电子设备可以是一个适配器或服务器，以适配器为例，该适配器可以包括图15所示的驱动电路150，即包括栅极驱动器1501和集成器件1502，该集成器件1502可以是图2、图5、图7和图9中的集成器件中的任一个。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (27)

  1. 一种集成器件，其特征在于，包括：
    第一金属层；
    设于所述第一金属层之上的第一介质层；
    设于所述第一介质层之上的第二介质层；
    设于所述第一介质层与所述第二介质层之间的栅极金属层；以及，
    设于所述第二介质层之上的第二金属层；其中，
    所述第一金属层、所述第一介质层以及所述栅极金属层用于构成第一电容；
    所述第二金属层、所述第二介质层以及所述栅极金属层用于构成第二电容；
    所述第一金属层与所述第二金属层通过第一导体结构连接，以使得所述第一电容与所述第二电容并联连接。
  2. 根据权利要求1所述的集成器件，其特征在于，所述栅极金属层与所述第一金属层极性相反，所述第二金属层与所述栅极金属层极性相反。
  3. 根据权利要求1所述的集成器件，其特征在于，所述集成器件还包括第三金属层，
    设于所述第一金属层之下的P型导电层；
    设于所述P型导电层之下的氮化铝镓层；
    所述氮化铝镓层之下包括二维电子气；
    所述第一金属层、所述P型导电层以及所述二维电子气用于构成第三电容；
    所述第三金属层穿过所述第二介质层、所述第一介质层和所述氮化铝镓层，与所述二维电子气相接，所述第三金属层与所述栅极金属层通过第二导体结构连接，以使得所述第一电容、所述第二电容和所述第三电容并联连接。
  4. 根据权利要求3所述的集成器件，其特征在于，所述第三金属层与所述第一金属层极性相反。
  5. 根据权利要求3所述的集成器件，其特征在于，所述氮化铝镓层设置在氮化铝层之上，所述二维电子气位于所述氮化铝层之下。
  6. 根据权利要求1至5任一项所述的集成器件，其特征在于，所述P型导电层包括P型氮化镓或P型氮化铝镓。
  7. 根据权利要求1至5任一项所述的集成器件，其特征在于，所述第一金属层包括氮化钛或钨。
  8. 根据权利要求2至5任一项所述的集成器件，其特征在于，所述第一导体结构和所述第二导体结构的材料包括铜或铝。
  9. 一种集成器件，其特征在于，包括：
    氮化铝镓层；
    设于所述氮化铝镓层之上的第一介质层；
    设于所述第一介质层之上的第二介质层；
    设于所述第一介质层与所述第二介质层之间的栅极金属层；以及，
    设于所述第二介质层之上的第二金属层；其中，
    所述氮化铝镓层之下包括二维电子气；
    所述二维电子气、所述第一介质层以及所述栅极金属层用于构成第一电容；
    所述第二金属层、所述第二介质层以及所述栅极金属层用于构成第二电容；
    所述第二金属层穿过所述第二介质层、所述第一介质层和所述氮化铝镓层，与所述二维电子气相接，以使得所述第一电容与所述第二电容并联连接。
  10. 根据权利要求9所述的集成器件，其特征在于，所述第二金属层与所述栅极金属层极性相反。
  11. 根据权利要求9-10任一项所述的集成器件，其特征在于，所述第一介质层包括P型氮化镓或P型氮化铝镓，所述栅极金属层穿过所述第一介质层，并形成于所述P型氮化镓或所述P型氮化铝镓之上。
  12. 根据权利要求9-10任一项所述的集成器件，其特征在于，所述氮化铝镓层设置在氮化铝层之上，所述二维电子气位于所述氮化铝层之下。
  13. 一种半导体器件，其特征在于，包括权利要求1～12中任一项所述的集成器件，以及在所述集成器件上形成的半导体构成。
  14. 一种集成器件的制作方法，其特征在于，包括：
    在第一金属层上形成第一介质层；
    在所述第一介质层上形成栅极金属层；
    在所述栅极金属层上形成第二介质层；
    在所述第二介质层上形成第二金属层；其中，
    所述第一金属层、所述第一介质层以及所述栅极金属层用于构成第一电容；
    所述第二金属层、所述第二介质层以及所述栅极金属层用于构成第二电容；
    通过第一导体结构将所述第一金属层与所述第二金属层相连，以使得所述第一电容与所述第二电容并联连接。
  15. 根据权利要求14所述的集成器件的制作方法，其特征在于，所述栅极金属层与所述第一金属层极性相反，所述第二金属层与所述栅极金属层极性相反。
  16. 根据权利要求14所述的集成器件的制作方法，其特征在于，所述第一金属层形成于P型导电层之上，所述P型导电层形成于氮化铝镓层之上，所述氮化铝镓层之下包括二维电子气，所述第一金属层、所述P型导电层以及所述二维电子气用于构成第三电容；
    在所述第二介质层上形成第三金属层，所述第三金属层穿过所述第二介质层、所述第一介质层和所述氮化铝镓层，与所述二维电子气相接；
    通过第二导体结构将所述第三金属层与所述栅极金属层相连，以使得所述第一电容、所述第二电容和所述第三电容并联连接。
  17. 根据权利要求16所述的集成器件的制作方法，其特征在于，所述第三金属层与所述第一金属层极性相反。
  18. 根据权利要求16所述的集成器件的制作方法，其特征在于，所述氮化铝镓层形成于氮化铝层之上，所述二维电子气位于所述氮化铝层之下。
  19. 根据权利要求16至18任一项所述的集成器件的制作方法，其特征在于，所述P 型导电层包括P型氮化镓或P型氮化铝镓。
  20. 根据权利要求14至18任一项所述的集成器件的制作方法，其特征在于，所述第一金属层包括氮化钛或钨。
  21. 根据权利要求16至18任一项所述的集成器件的制作方法，其特征在于，所述第一导体结构和所述第二导体结构的材料包括铜或铝。
  22. 一种集成器件的制作方法，其特征在于，包括：
    在氮化铝镓层上形成第一介质层；
    在所述第一介质层上形成栅极金属层；
    在所述栅极金属层上形成第二介质层；
    在所述第二介质层上形成第二金属层；
    所述氮化铝镓层之下包括二维电子气，所述二维电子气、所述第一介质层以及所述栅极金属层用于构成第一电容；
    所述第二金属层、所述第二介质层以及所述栅极金属层用于构成第二电容；
    通过所述第二金属层穿过所述第二介质层、所述第一介质层和所述氮化铝镓层，与所述二维电子气相接，以使得所述第一电容与所述第二电容并联连接。
  23. 根据权利要求22所述的集成器件的制作方法，其特征在于，所述第二金属层与所述栅极金属层极性相反。
  24. 根据权利要求22所述的集成器件的制作方法，其特征在于，所述第一介质层包括P型氮化镓或P型氮化铝镓，所述栅极金属层穿过所述第一介质层，并形成于所述P型氮化镓或所述P型氮化铝镓之上。
  25. 根据权利要求22至24任一项所述的集成器件的制作方法，其特征在于，所述氮化铝镓层形成于氮化铝层之上，所述二维电子气位于所述氮化铝层之下。
  26. 一种驱动电路，其特征在于，包括：
    栅极驱动器和如权利要求1至12中任一项所述的集成器件，或使用如权利要求14至25任一项所述的集成器件的制作方法所得到的集成器件；其中：所述栅极驱动器用于为所述集成器件提供电流。
  27. 一种电子设备，其特征在于，包括如权利要求1至12中任一项所述的集成器件，或使用如权利要求14至25任一项所述的集成器件的制作方法所得到的集成器件。
PCT/CN2021/099575 2021-06-11 2021-06-11 集成器件、半导体器件以及集成器件的制作方法 WO2022257092A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202180088904.2A CN116745914A (zh) 2021-06-11 2021-06-11 集成器件、半导体器件以及集成器件的制作方法
EP21944601.0A EP4325581A1 (en) 2021-06-11 2021-06-11 Integrated device, semiconductor device, and integrated device manufacturing method
PCT/CN2021/099575 WO2022257092A1 (zh) 2021-06-11 2021-06-11 集成器件、半导体器件以及集成器件的制作方法
US18/533,315 US20240113103A1 (en) 2021-06-11 2023-12-08 Integrated device, semiconductor device, and integrated device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/099575 WO2022257092A1 (zh) 2021-06-11 2021-06-11 集成器件、半导体器件以及集成器件的制作方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/533,315 Continuation US20240113103A1 (en) 2021-06-11 2023-12-08 Integrated device, semiconductor device, and integrated device manufacturing method

Publications (1)

Publication Number Publication Date
WO2022257092A1 true WO2022257092A1 (zh) 2022-12-15

Family

ID=84425567

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/099575 WO2022257092A1 (zh) 2021-06-11 2021-06-11 集成器件、半导体器件以及集成器件的制作方法

Country Status (4)

Country Link
US (1) US20240113103A1 (zh)
EP (1) EP4325581A1 (zh)
CN (1) CN116745914A (zh)
WO (1) WO2022257092A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057828A1 (en) * 2007-08-29 2009-03-05 Myung-Il Kang Metal-insulator-metal capacitor and method for manufacturing the same
CN103730450A (zh) * 2013-11-22 2014-04-16 上海和辉光电有限公司 有机电激发光二极体储存电容结构及其制备方法
CN104536223A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 液晶显示面板及其阵列基板
CN104795428A (zh) * 2015-04-10 2015-07-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法以及显示装置
CN111344774A (zh) * 2017-11-21 2020-06-26 索尼半导体解决方案公司 像素电路、显示装置和电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057828A1 (en) * 2007-08-29 2009-03-05 Myung-Il Kang Metal-insulator-metal capacitor and method for manufacturing the same
CN103730450A (zh) * 2013-11-22 2014-04-16 上海和辉光电有限公司 有机电激发光二极体储存电容结构及其制备方法
CN104536223A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 液晶显示面板及其阵列基板
CN104795428A (zh) * 2015-04-10 2015-07-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法以及显示装置
CN111344774A (zh) * 2017-11-21 2020-06-26 索尼半导体解决方案公司 像素电路、显示装置和电子设备

Also Published As

Publication number Publication date
CN116745914A (zh) 2023-09-12
EP4325581A1 (en) 2024-02-21
US20240113103A1 (en) 2024-04-04

Similar Documents

Publication Publication Date Title
US10541324B2 (en) Semiconductor device with a recessed ohmic contact and methods of fabrication
TWI598945B (zh) 製造半導體裝置之方法
JP5990976B2 (ja) 半導体装置及び半導体装置の製造方法
TWI515874B (zh) 半導體裝置及其製造方法、電源供應器與高頻放大器
US8445341B2 (en) Semiconductor device and fabrication method for the same
US20180197999A1 (en) High-linearity transistors
CN104183638B (zh) 半导体装置和制造半导体装置的方法
US20140042452A1 (en) Iii-nitride enhancement mode transistors with tunable and high gate-source voltage rating
JP5685917B2 (ja) 半導体装置及び半導体装置の製造方法
JP2021504955A (ja) 高電子移動度トランジスタ及び高電子移動度トランジスタを製造する方法
JP2018085414A (ja) 化合物半導体装置
JP2019165172A (ja) 半導体装置及びその製造方法
JP7009952B2 (ja) 半導体装置及び半導体装置の製造方法
JP2020027911A (ja) 化合物半導体装置、化合物半導体装置の製造方法及び増幅器
CN112185959A (zh) 一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法
WO2022257092A1 (zh) 集成器件、半导体器件以及集成器件的制作方法
JP7363507B2 (ja) 半導体装置
JP2024520787A (ja) 集積デバイス、半導体デバイス、および集積デバイスの製造方法
JP2022016950A (ja) 半導体装置
US11824108B2 (en) Semiconductor device
CN211529952U (zh) 具有集成续流二极管的氮化镓半导体器件
JP2015018998A (ja) 化合物半導体装置及びその製造方法
US20230261054A1 (en) Radio frequency transistor amplifiers having self-aligned double implanted source/drain regions for improved on-resistance performance and related methods
WO2024001693A1 (zh) 一种器件、模组和设备
JP2017085006A (ja) 化合物半導体装置及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21944601

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180088904.2

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2021944601

Country of ref document: EP

Ref document number: 21944601.0

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2021944601

Country of ref document: EP

Effective date: 20231114

ENP Entry into the national phase

Ref document number: 2023575712

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE