WO2022252219A1 - 一种相变存储器及电子设备 - Google Patents

一种相变存储器及电子设备 Download PDF

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WO2022252219A1
WO2022252219A1 PCT/CN2021/098367 CN2021098367W WO2022252219A1 WO 2022252219 A1 WO2022252219 A1 WO 2022252219A1 CN 2021098367 W CN2021098367 W CN 2021098367W WO 2022252219 A1 WO2022252219 A1 WO 2022252219A1
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phase
layer
change
phase change
electrode
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PCT/CN2021/098367
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English (en)
French (fr)
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秦青
周雪
焦慧芳
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华为技术有限公司
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Priority to PCT/CN2021/098367 priority Critical patent/WO2022252219A1/zh
Publication of WO2022252219A1 publication Critical patent/WO2022252219A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Definitions

  • the present application relates to the field of storage technology, in particular to a phase-change memory and electronic equipment.
  • Phase Change Memory is a non-volatile memory, which mainly uses phase change materials, such as chalcogenide compounds, to store data due to the huge difference in conductivity between crystalline and amorphous states. Phase-change materials can switch between two states with different structures and different resistivities under specific pulses. These two states are amorphous states with high resistivity and crystalline states with low resistivity. The difference distinguishes two logical states “0" and "1". Phase change memory has the characteristics of high speed, high density and low power consumption, and is widely used in storage applications of electronic devices.
  • phase change materials such as chalcogenide compounds
  • the phase-change memory layer in order to increase the phase-change speed of the phase-change memory material, the phase-change memory layer mostly adopts a superlattice structure or a multi-layer film stack structure.
  • the phase change material layer can be composed of two layers of different materials, and can have N repeating units, specifically, two layers of phase change material film layers are taken as an example, the first film layer and the second film layer are stacked, When laying on the substrate of the phase change memory, the first film layer is laid on the substrate, the second film layer is laid on the first film layer, and the direction of the current flowing through the phase change memory is parallel to the stacking direction.
  • phase change temperature of the phase change film layer is high, and the diffusion between the film layers will be intensified under the action of the current, thereby affecting the components between the film layers, blurring the boundary between the film layers, and easily leading to phase change.
  • the failure of the function of the change material layer shortens the service life of the phase change memory.
  • the present application provides a phase-change memory and electronic equipment, which solves the problems of the existing phase-change memory that the diffusion between film layers is intensified under the action of current, resulting in functional failure and shortening the service life of the phase-change memory.
  • the first aspect of the present application provides a phase-change memory, including: a first electrode, a second electrode, and a phase-change memory cell, the phase-change memory cell is located between the first electrode and the second electrode;
  • the phase change memory unit includes a phase change memory layer, the phase change memory layer includes a stacked first phase change layer and a second phase change layer, the first end of the first phase change layer on the same side is coupled To the first electrode, second ends on the other side of the first phase change layer and the second phase change layer are coupled to the second electrode.
  • the current can pass through the phase change memory unit from the second electrode and then flow out from the first electrode to form a loop.
  • the direction of the current flowing through the phase change storage layer is parallel to the extension direction of the first phase change layer and the second phase change layer, and perpendicular to the stacking direction of the phase change storage layer, so that the phase change under the action of the current
  • the phase change material molecules in the layer tend to diffuse along the current direction, that is, along the extension direction of the phase change layer where they are located, which reduces the occurrence of phase change material molecules in the phase change layer along the lamination direction under the action of current. Diffusion between layers reduces the degree of blurring of boundaries between phase change layers, ensures the function of the phase change storage layer, thereby improving the cycle durability of the phase change memory and ensuring its service life.
  • the first phase change layer is located between two layers of the second phase change layer, and the phase change temperature of the second phase change layer is higher than that of the first phase change layer. change temperature.
  • the first phase change layer undergoes a phase change, and the second phase change layer does not undergo a phase change due to the higher required phase change temperature.
  • the existence of the second phase change layer can control the crystallization process of the first phase change layer. Playing an inductive role, the second phase change layer can be used as a template for the crystallization of the first phase change layer, making it crystallize along the extension direction of the second phase change layer to form a film layer, which helps to increase the crystallization speed of the first phase change layer , thereby increasing storage speed.
  • the temperature difference between the phase transition temperature of the second phase change layer and the phase transition temperature of the first phase change layer is greater than or equal to 100°C.
  • the extension direction of the first electrode is perpendicular to the extension direction of the second electrode, and the phase change memory cell is connected to the extension direction of the first electrode and the extension direction of the second electrode.
  • the extension directions are all vertical.
  • the storage unit further includes an electrical connector, the second terminal is connected to the second electrode through the electrical connector, and the electrical connector is used to connect or disconnect the The connection between the second end and the second electrode.
  • the electrical connector can be used as a switch, and the electrical connector can communicate with the phase-change storage layer and the second electrode, so that the current flows through the second electrode and the phase-change storage layer, and then flows out through the first electrode to form a loop.
  • the electrical connector may also disconnect the phase-change storage layer from the second electrode, so that current cannot be conducted through the phase-change storage layer.
  • the electrical connector acts as a switch to selectively conduct the required phase-change memory cells to realize data storage.
  • the electrical connection layer includes a gate tube.
  • each of the first electrode, the second electrode and the phase-change memory unit is multiple, and the multiple first electrodes are arranged in parallel with each other, A plurality of the second electrodes are arranged parallel to each other;
  • the first insulating layer surrounds and covers the outer periphery of the phase-change memory unit, and the first insulating layer is provided between two adjacent phase-change memory units. That is to say, the gaps between the phase-change memory cells are filled with the first insulating layer, so as to ensure the insulation between the phase-change memory cells and at the same time improve the setting stability of the phase-change memory cells and improve the stability of the entire device.
  • a second insulating layer is further included, and the second insulating layer is provided between two adjacent first electrodes and between two adjacent second electrodes. In this way, the insulation between the first electrode and the first electrode, and between the second electrode and the second electrode can be ensured, so as to avoid the change of the current direction caused by the connection.
  • molding materials of the first phase change layer and the second phase change layer both include at least a chalcogenide compound.
  • a second aspect of the present application provides an electronic device, including a casing and any one of the phase-change memories described above, where the phase-change memory is disposed in the casing.
  • the direction of the current flowing through the phase-change memory unit in the phase-change memory is parallel to the extension direction of the phase-change layer included in the phase-change memory unit, and perpendicular to the stacking direction of the phase-change layer, so that it can Reduce the mutual diffusion of elements between the phase change layers caused by the action of current, reduce the blurring degree of the boundary between the phase change layers, and ensure the function of the phase change memory unit, thereby improving the cycle durability of the phase change memory and ensuring its service life. In turn, it helps to improve the durability of electronic devices and enhance user experience.
  • FIG. 1 is a schematic diagram of a thermal state transition of a phase change material provided in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a phase change memory provided by an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional structure diagram of an existing phase-change memory
  • Fig. 4 is a schematic diagram of a partial structure of a phase change memory section along A-A in Fig. 2 provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of a phase-change storage layer provided by an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional structure diagram of another phase-change memory provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another phase-change memory provided by an embodiment of the present application.
  • Fig. 8 is a schematic diagram of another phase-change memory according to the embodiment of the present application along the section B-B in Fig. 7;
  • FIG. 9 is a schematic cross-sectional structure diagram of another phase-change memory provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a phase-change storage layer in state 1 during the manufacturing process provided by the embodiment of the present application.
  • Fig. 11 is a schematic diagram of state 2 during the manufacturing process of a phase-change storage layer provided by an embodiment of the present application;
  • FIG. 12 is a schematic diagram of state three during the manufacturing process of a phase-change storage layer provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a phase-change storage layer in state four during the manufacturing process provided by the embodiment of the present application.
  • FIG. 14 is a schematic diagram of a phase-change storage layer in state five during the manufacturing process provided by the embodiment of the present application.
  • Fig. 15 is a schematic diagram of a phase-change storage layer in state six during the manufacturing process provided by the embodiment of the present application;
  • Fig. 16 is a schematic diagram of a phase-change storage layer in state 7 during the manufacturing process provided by the embodiment of the present application;
  • Fig. 17 is a schematic diagram of state 1 during the manufacturing process of another phase-change storage layer provided by the embodiment of the present application.
  • Fig. 18 is a schematic diagram of another state in state 2 during the manufacturing process of another phase-change storage layer provided by the embodiment of the present application;
  • Fig. 19 is a schematic diagram of another phase-change storage layer in state three during the manufacturing process provided by the embodiment of the present application.
  • Fig. 20 is a schematic diagram of another phase-change storage layer in state four during the manufacturing process provided by the embodiment of the present application.
  • Fig. 21 is a schematic diagram of another phase-change storage layer in state five during the manufacturing process provided by the embodiment of the present application.
  • Fig. 22 is a schematic diagram of another phase-change storage layer in state six during the manufacturing process provided by the embodiment of the present application.
  • Fig. 23 is a schematic diagram of another phase-change storage layer in state 7 during the manufacturing process provided by the embodiment of the present application.
  • Fig. 24 is a schematic diagram of another phase-change storage layer in state eight during the manufacturing process provided by the embodiment of the present application.
  • Fig. 25 is a schematic diagram of state nine during the manufacturing process of another phase-change storage layer provided by the embodiment of the present application.
  • Fig. 26 is a schematic diagram of another phase change storage layer in state ten during the manufacturing process provided by the embodiment of the present application.
  • Fig. 27 is a schematic diagram of another phase change memory in state eleven during the manufacturing process provided by the embodiment of the present application.
  • Fig. 28 is a schematic diagram of state 1 during the manufacturing process of another phase-change storage layer provided by the embodiment of the present application.
  • Fig. 29 is a schematic diagram of another phase-change storage layer in the second state during the manufacturing process provided by the embodiment of the present application.
  • Fig. 30 is a schematic diagram of another phase-change storage layer in state three during the manufacturing process provided by the embodiment of the present application.
  • Fig. 31 is a schematic diagram of another phase-change storage layer in state 4 during the manufacturing process provided by the embodiment of the present application.
  • Fig. 32 is a schematic diagram of another phase-change storage layer in state five during the manufacturing process provided by the embodiment of the present application.
  • Fig. 33 is a schematic diagram of another phase-change storage layer in state six during the manufacturing process provided by the embodiment of the present application.
  • Fig. 34 is a schematic diagram of another phase-change storage layer in state 7 during the manufacturing process provided by the embodiment of the present application.
  • Fig. 35 is a schematic side view of another phase-change storage layer in state eight during the manufacturing process provided by the embodiment of the present application.
  • Fig. 36 is a schematic top view of another phase-change storage layer in state eight during the manufacturing process provided by the embodiment of the present application;
  • Fig. 37 is a schematic top view of another phase-change storage layer in state nine during the manufacturing process provided by the embodiment of the present application.
  • FIG. 38 is a schematic top view of another phase-change storage layer in state ten during the manufacturing process provided by the embodiment of the present application.
  • 31-phase change storage layer 31a-phase change storage layer one; 31c-phase change storage layer three;
  • 311-first phase change layer 311a-first phase change layer one; 311b-first phase change layer two;
  • 312-second phase change layer 312a-second phase change layer one; 312b-second phase change layer two;
  • 32-electrical connector 32a-electrical connector one; 32c-electrical connector two;
  • Phase-change memory has the characteristics of high speed, high density, low power consumption, and non-volatility, so it is gradually used in electronic devices, such as UAB flash drives, computers, and mobile phones, as storage units.
  • Phase-change memory stores data by using the difference in conductivity of special materials when they transform between crystalline and amorphous states.
  • Phase-change materials such as chalcogenides, under specific pulses, will switch between the high-resistivity amorphous state and the low-resistivity crystalline state, thereby realizing "0/1" storage.
  • the amorphous state can correspond to "0", which is a high-resistance state
  • the crystallized state can correspond to "1", which is a low-resistance state.
  • a phase-change memory usually includes an upper electrode, a lower electrode, and a phase-change storage layer between the upper electrode and the lower electrode. The phase-change storage layer is fed with current through the upper electrode and the lower electrode, and the Joule heat generated makes the phase-change storage layer The temperature of the phase change material rises rapidly in a short period of time to realize the transformation of the state.
  • Fig. 1 shows a schematic diagram of a phase change material heated state transition, as shown in Fig. 1, when the generated Joule heat causes the temperature of the phase change material to rise sharply, after exceeding the melting temperature, quenching (removal of the current), will Keep the phase change material in an amorphous state, so as to realize the programming of "0", also called reset operation or writing "0".
  • phase change material When the generated Joule heat temperature does not exceed the melting temperature of the phase change material, but is higher than the crystallization temperature, the phase change material begins to crystallize. The phase change material finally maintains the crystallization device to realize the writing of "1", also called set operation or writing "1". In this way, binary form storage can be realized by writing "0" and "1".
  • phase change memory provided by the embodiment of the present application will be described in detail below in conjunction with the accompanying drawings.
  • FIG. 2 is a schematic structural diagram of a phase change memory provided by an embodiment of the present application.
  • a phase change memory provided by an embodiment of the present application includes a plurality of first electrodes 10 , a plurality of second electrodes 20 and a plurality of phase change memory cells 30 .
  • a plurality of first electrodes 10 can be arranged parallel to each other and arranged side by side
  • a plurality of second electrodes 20 can be arranged parallel to each other and arranged side by side
  • the first electrode 10 can be located above the second electrode 20
  • the extension direction of the first electrode 10 (such as The x direction in the figure) may be perpendicular to the extending direction of the second electrode 20 (the y direction in the figure).
  • the phase-change memory cell 30 is located between the first electrode 10 and the second electrode 20, and there is one phase-change memory cell 30 between each first electrode 10 and one second electrode 20, that is, each phase-change memory cell 30 Two ends of each are electrically connected to a first electrode 10 and a second electrode 20 respectively.
  • the extension direction of the phase change memory unit 30 (z direction in the figure) can be perpendicular to the extension direction of the first electrode 10 and the extension direction of the second electrode 20, so that the first electrode 10, the second electrode 20 and the phase change Layout settings between memory cells 30 .
  • the phase change memory unit 30 includes a phase change memory layer 31, the phase change memory layer 31 is a film layer formed of a phase change material, which can realize the conversion between the crystalline state and the amorphous state under the action of Joule heat of the current. .
  • the current can pass through the phase change memory unit 30 from the second electrode 20 and then flow out from the first electrode 10 to form a loop.
  • the Joule heat generated by the current passing through the phase change memory unit 30 will cause the phase change material of the phase change memory layer 31 to change state. Conversion, when the phase change material is in the amorphous state, it is in the high resistance state, and "0" can be written. When the phase change material is in the crystalline state, it is in the low resistance state, and "1" can be written, so that it can be passed through binary
  • the numbers "1" and "0" are used to store information.
  • phase-change memory cells 30 there are multiple phase-change memory cells 30, it should be noted that, when a certain phase-change memory cell 30 is used for data storage, only the corresponding connection of the phase-change memory cell 30 can be turned on.
  • the first electrode 10 and the second electrode 20 make the current flow from the corresponding second electrode 20 through the phase change memory unit 30 and then flow out from the first electrode 10 to form a loop.
  • FIG. 3 is a schematic cross-sectional structure diagram of a conventional phase change memory.
  • the phase-change memory layer 31 mostly adopts a superlattice structure or a multi-layer film stack structure.
  • the phase-change storage layer 31 includes two or more superimposed phase-change layers, as shown in FIG.
  • the phase change materials of the first phase change layer 311 and the second phase change layer 312 may both be chalcogenide compound phase change materials, wherein the phase change material forming the first phase change layer 311 and the phase change material forming the second phase change layer 312 Different phase change materials require different phase change temperatures for the first phase change layer 311 and the second phase change layer 312 to undergo phase change.
  • the first phase change layer 311 is disposed on the second electrode 20
  • the second phase change layer 312 is laid on the first phase change layer 311
  • the first electrode is disposed on the second phase change layer 312 . That is, the first phase change layer 311 close to the second electrode 20 is electrically coupled to the second electrode 20, the second phase change layer 312 close to the first electrode 10 is electrically coupled to the first electrode 10, and the first phase change layer 311
  • the stacking direction of the second phase change layer 312 is the direction in which the second electrode 20 points to the first electrode 10 .
  • the current passes through the second electrode 20 and flows out from the first electrode 10 after passing through the phase change storage layer 31, then the direction of the current flowing through the phase change storage layer is the direction from the second electrode 20 to the first electrode 10, as shown in the figure
  • the i direction in that is to say, the direction of the current flowing through the phase change memory layer is parallel to the stacking direction of the phase change memory layer.
  • phase change storage layer itself is heated, molecular diffusion of the phase change material will occur between the stacked film layers.
  • the direction of the current flowing through the phase-change storage layer is parallel to the stacking direction of the phase-change storage layer, the molecules of the phase-change material will tend to diffuse along the current direction under the guidance of the current, that is, diffuse along the stacking direction. , which will intensify the interdiffusion of molecules between the film layers, affect the components of each film layer, cause the boundary between the film layers to gradually blur, and reduce the functional stability of the phase change memory.
  • severe blurring will easily lead to the failure of the function of the phase-change memory layer and shorten the service life of the phase-change memory.
  • FIG. 4 is a schematic diagram of a partial structure of a phase-change memory provided by an embodiment of the present application along the section A-A in FIG. 2
  • FIG. 5 is a schematic structural diagram of a phase-change memory layer provided by an embodiment of the present application.
  • the phase change storage layer 31 in the phase change storage at least includes a stacked first phase change layer 311 and a second phase change layer 312, and the first phase change layer 311 and the second phase change layer
  • Both of the change layers 312 are film layers formed by phase change materials, wherein the phase change material forming the first phase change layer 311 is different from the phase change material forming the second phase change layer 312, so that the first phase change layer 311 undergoes phase change.
  • the phase change temperature required for the phase change is different from the phase change temperature required for the phase change of the second phase change layer 312 .
  • the phase change material forming the first phase change layer 311 and the second phase change layer 312 may be a chalcogenide compound, such as GeTe, Sb 2 Te 3 , Ge 2 Sb 2 Te 5 , PbGeSb, GeTeAs, BiTe, AgInSbTe, Ge 1 Sb 2 Te 4 etc.
  • a chalcogenide compound such as GeTe, Sb 2 Te 3 , Ge 2 Sb 2 Te 5 , PbGeSb, GeTeAs, BiTe, AgInSbTe, Ge 1 Sb 2 Te 4 etc.
  • the chalcogenide compound can maintain stable amorphous and crystalline states.
  • the Joule heat generated will make the chalcogenide compound change from the amorphous state to the crystalline state, and can also be converted from The crystalline state is converted into an amorphous state, and when the chalcogenide compound reaches the amorphous state and the crystalline state, the state can be maintained without applying additional external influences, thus enabling nonvolatile storage.
  • Chalcogenides have different resistance values in the amorphous state and the crystalline state, so that the crystalline state (low resistance) and the amorphous state (high resistance) represent binary numbers "1" and "0" respectively to realize information storage.
  • the first end of the first phase change layer 311 and the second phase change layer 312 on the same side are coupled to the first electrode 10, such as the phase change storage layer 31 close to the first electrode
  • One side of the electrode 10 is the first side 310a, and the first ends of the first phase change layer 311 and the second phase change layer 312 are located at the first side 310a, and both are electrically connected to the first electrode 10 .
  • the second end 31b on the other side of the first phase change layer 311 and the second phase change layer 312 is coupled to the second electrode 20, such as the side of the phase change storage layer 31 close to the second electrode 20 is the second side 310b ( Opposite to the first side 310a), the second end of the first phase change layer 311 and the second end of the second phase change layer 312 are both located on the second side 310b, and both are electrically connected to the second electrode 20 .
  • the extension direction of the first phase change layer 311 can be from the second electrode 20 to the direction of the first electrode 10 (such as the z direction in Figure 2)
  • the extension direction of the second phase change layer 312 can be from the second electrode 20
  • the stacking direction of the phase-change storage layer is a direction perpendicular to the first phase-change layer 311 and the second phase-change layer 312 , such as the x direction in the figure.
  • the current can pass through the phase change memory unit 30 from the second electrode 20 and then flow out from the first electrode 10 to form a loop, then the direction of the current flowing through the phase change memory layer 31 of the phase change memory unit 30 is the same as
  • the extension directions of the first phase change layer 311 and the second phase change layer 312 are parallel to the stacking direction of the phase change storage layer 31 , and the current direction is i direction in the figure.
  • the current direction i flowing through the phase change storage layer 31 is parallel to the extension direction z of the first phase change layer and the second phase change layer included in the phase change storage layer, and is consistent with the stacking of the phase change storage layer 31
  • the direction x is perpendicular to each other, so that under the action of the current, the molecules of the phase change material in the phase change layer tend to diffuse along the direction of the current, that is, they diffuse along the extension direction of the phase change layer where they are located, which reduces the pressure of the phase change layer under the action of the current.
  • phase change material molecules between the film layers along the stacking direction reduces the degree of blurring of the boundaries between the phase change layers, ensures the storage function of the phase change storage layer 31, and improves the performance of the phase change memory 100. Cycle durability guarantees its service life.
  • the phase change temperature of the second phase change layer 312 may be greater than the phase change temperature of the first phase change layer 311, specifically, the phase change temperature is the temperature required for the transition between the amorphous state and the crystalline state.
  • the phase change temperature can include crystallization temperature (Tc) and melting temperature (Tm), the crystallization temperature refers to the temperature required for the phase change material to change from the amorphous state to the crystalline state, and the melting temperature refers to the phase change material from the crystalline state to the amorphous state State the desired temperature.
  • the phase transition temperature of the first phase change layer 311 is lower than that of the second phase change layer 312 , that is, the second phase change layer 312 has better thermal stability than the first phase change layer 311 .
  • the first phase change layer 311 undergoes a phase change during the storage process of writing "0" and "1", and the second phase change layer 312 has a higher phase change temperature due to the required phase change. No phase transition occurs.
  • the existence of the second phase change layer 312 can induce the crystallization process of the first phase change layer 311, and the second phase change layer 312 can be used as the crystallization of the first phase change layer 311 template, so that it crystallizes along the extension direction of the second phase change layer 311 to form a film layer, which helps to increase the crystallization speed of the first phase change layer 311, accelerates the operation of writing "1", thereby increasing the storage speed.
  • the molding materials of the first phase change layer 311 and the second phase change layer 312 can be chalcogenide compound phase change materials, specifically, the phase change material of the first phase change layer 311 can be a Sb n Te m type compound , the phase change material of the second phase change layer 312 may be a compound of Ge a Sb n Te m type. Alternatively, the phase change material of the first phase change layer 311 can be a Ge a Sb n Te m type compound, and the phase change material of the second phase change layer 312 can be a Ge a Sb n Te m type compound doped with carbon elements or the like. compound.
  • the phase change material of the second phase change layer 312 and the first phase change layer 311 can be selected and set according to the magnitude of the Joule heat generated by the current flowing through the phase change memory, which is not limited in the embodiment of the present application, and the second phase change layer can be ensured. It is sufficient that the phase transition temperature of the first phase transition layer is higher than that of the first phase transition layer.
  • the temperature difference between the phase transition temperature of the second phase transition layer 312 and the phase transition temperature of the first phase transition layer 311 may be greater than or equal to 100°C.
  • the phase change temperature difference between the two is small, it is easy to cause a certain phase change in the second phase change layer 312 while the first phase change layer 311 is in phase change, so that the second phase change layer 312 cannot be the first phase change layer.
  • the crystallization process of the phase change layer 311 acts as a good template, so when the temperature difference between the two is greater than or equal to 100° C., the phase change memory layer 31 can ensure a better storage speed.
  • the phase-change storage layer 31 may only include a first phase-change layer 311 and a second phase-change layer 312 .
  • the phase-change storage layer 31 may have multiple layers of first phase-change layers 311 and multiple layers of second phase-change layers 312 , and the first phase-change layers 311 and the second phase-change layers 312 may be alternately stacked.
  • the phase-change storage layer 31 may only include three layers, namely a first phase-change layer 311 and a second phase-change layer 312 located on both sides of the first phase-change layer 311 .
  • the phase-change storage layer 31 may also include four layers, which are two first phase-change layers 311 and two second phase-change layers 312 respectively, and the first phase-change layers 311 and the second phase-change layers 312 are alternately stacked. .
  • the size of the phase change layer storage layer 31 includes multiple layers of the first phase change layer 311 and multiple layers of the second phase change layer 312, and the size width of the first phase change layer 311 and the second phase change layer 312 It will be relatively small, so that the phase change of the first phase change layer 311 can be facilitated, which helps to increase the phase change speed, reduce power consumption, and improve storage capacity.
  • the first phase change layer 311 can be between two layers of second phase change layers 312.
  • the second phase change layers 312 on both sides can be in the state of the first phase change layer 311.
  • the conversion provides better templating effect, which further increases the crystallization speed and improves the storage speed.
  • the second phase change layer 312 also generates heat when the current flows through, and the generated heat is helpful for the reorganization of molecules in the first phase change layer 311, which can play a role in the first phase change layer 311 A certain repairing effect further contributes to the state transition of the first phase change layer 311 .
  • the phase change storage layer 31 is alternately arranged in this order by the second phase change layers 312, the first phase change layers 311, and the second phase change layers 312.
  • the second phase change layer 312 has higher thermal stability, which will hinder the heat dissipation of the first phase change layer 311 to a certain extent, so that the heat of the first phase change layer 311 is not easy to dissipate, thus It helps to reduce the power consumption required by the first phase change layer 311 to complete a phase change, that is, reduces the writing power consumption, and reduces the storage power consumption of the phase change memory 100 .
  • the phase-change materials of the second layer may be the same, that is, the phase-change temperature of the second phase-change layer 312 of the two layers may be the same.
  • the phase change material forming the second phase change layer 1 and the phase change material forming the second phase change layer 2 are different, that is, the phase change temperatures of the two layers of the second phase change layer 312 may be different.
  • the first phase change layer 311 can have only one layer, and a layer of second phase change layer 312 is respectively arranged on both sides, or the first phase change layer 311 can also include two or more layers, and the first phase change layer 311 has two layers. Each side has a second phase change layer 312 , and the first phase change layer 311 and the second phase change layer 312 are alternately arranged to form a phase change storage layer 31 .
  • the phase-change storage layer 31 may be a rectangular columnar structure as shown in FIG. 4 , and the two sides of the first phase-change layer 311 are respectively provided with second phase-change layers 312 .
  • the phase-change storage layer 31 may also be a columnar structure, for example, the first phase-change layer 311 forms an annular columnar structure, and there are second phase-change layers 312 on the inner and outer circumferential sides of the first phase-change layer 311 .
  • the phase-change storage layer 31 may also be in other shapes, and the specific structural shape is not limited in this embodiment of the present application.
  • end surfaces of the formed first phase change layer 311 and the second phase change layer 312 can be flat horizontal surfaces, or the end surfaces can also be twisted surfaces with convex or concave structures, etc., which are not made in this embodiment. limit.
  • FIG. 6 is a schematic cross-sectional structure diagram of another phase change memory provided by an embodiment of the present application.
  • a first insulating layer 50 may be provided around the outer periphery of the phase-change memory unit 30, and the first insulating layer 50 may ensure that the phase-change memory cells 30 between adjacent phase-change memory units The insulation between the storage unit 30 and the external environment is changed.
  • the first insulating layer 50 can be provided between any two adjacent phase-change memory cells 30, that is, the gap between the phase-change memory cells 30 is filled with the first insulating layer 50 to ensure that the phase-change memory cells 30 While improving the insulation between them, the setting stability of the phase-change memory unit 30 is improved, and the stability of the entire device is improved.
  • the first insulating layer 50 can also play the role of insulating and isolating two adjacent phase-change memories 100 , ensuring that the phase-change memories 100 will not affect each other.
  • a second insulating layer 40 may be disposed between two adjacent first electrodes 10 and between two adjacent second electrodes 20 , that is, between the gaps between two adjacent first electrodes 10 .
  • the second insulating layer 40 is filled between the two adjacent second electrodes 20, and the second insulating layer 40 can also be filled between the gaps between two adjacent second electrodes 20, so that it can be ensured that between the first electrode 10 and the first electrode 10, and the second
  • the insulation between the electrode 20 and the second electrode 20 is used to avoid the change of the current direction caused by the connection.
  • Fig. 7 is a schematic structural diagram of another phase-change memory provided by an embodiment of the present application
  • Fig. 8 is a schematic diagram of a partial structure of another phase-change memory provided by an embodiment of the present application along B-B in Fig. 7
  • Fig. 9 is a schematic diagram of the present application A schematic cross-sectional structure diagram of another phase-change memory provided in the embodiment.
  • the phase-change memory unit 30 may also include an electrical connector 32, one end of the phase-change memory layer 31, that is, the first end of the first phase-change layer 311 and the second phase-change layer 312 are connected to The first electrode 10 is electrically connected, and the other end of the phase-change storage layer 31, that is, the second end 31b of the first phase-change layer 311 and the second phase-change layer 312 is connected to the electrical connector 32, and the electrical connector 32 is connected to the second electrode. 20 connections.
  • the electrical connector 32 is used to connect or disconnect the second ends of the first phase change layer 311 and the second phase change layer 312 with the second electrode 20, that is, the electrical connector 32 can be used as a switch, and the electrical connector 32 can be The phase-change storage layer 31 and the second electrode 20 are connected, so that the current flows through the second electrode 20 and the phase-change storage layer 31 and flows out through the first electrode 10 to form a loop.
  • the electrical connector 32 may also disconnect the phase-change storage layer 31 from the second electrode 20 , so that current cannot be conducted through the phase-change storage layer 31 .
  • the electrical connector 32 serves as a switch to selectively conduct the required phase-change memory cells 30 to realize data storage.
  • the electrical connector 32 serves as a switch to selectively conduct the required phase-change memory cells 30 to realize data storage.
  • phase-change memory cell between electrode one 10a and electrode three 20a, which is phase-change memory cell one 30a, and there is a phase-change memory cell between electrode one 10a and electrode four 20b, which is phase-change memory cell two 30b, and electrode one 10a
  • phase-change memory cell between the electrode five 20c, and the phase-change memory cell three 30c is used as an example for illustration.
  • each phase change memory cell 30 includes a phase change memory layer 31 and an electrical connector 32, such as a phase change memory cell 1 30a includes a phase change memory layer 1 31a and an electrical connector 32a, and a phase change memory cell 2 30b includes a phase change memory cell 30a.
  • the second phase change storage layer and the second electrical connector, the third phase change memory unit 30c includes the third phase change storage layer 31c and the third electrical connector 32c.
  • the current passes through the third electrode 20a and then flows through the first electrical connector 32a and the first phase-change storage layer 31a, and then flows out from the first electrode 10a to form a loop, thereby realizing data storage by using the state transition of the first phase-change storage layer 31a.
  • the third electrical connector 32c can be connected to the third phase-change storage layer 31c and the fifth electrode 20c, so that the current passes through the fifth electrode 20c and then flows through the third electrical connector 32c and the third phase-change storage layer 31c flow out from the first electrode 10a to form a loop, thereby realizing data storage by using the state transition of the first phase-change storage layer 31a.
  • the phase-change storage layer 31 includes stacked multi-layer first phase-change layers 311 and second phase-change layers 312, both the first phase-change layers 311 and the second phase-change layers 312 are connected to the electrical connectors 32 connect.
  • the electrical connector 32 may be a gating tube, and the forming material of the gating tube may be Ge, Te, Se or the like.
  • a first insulating layer 50 may also be provided around the outer periphery of the phase-change memory cell 30 , between two adjacent first electrodes 10 and between two adjacent second electrodes 20 Both may be provided with a second insulating layer 40 .
  • the phase-change storage layer 31 includes a first phase-change layer 311, and the formation process of a structure having a second phase-change layer 312 on the two layers of the first phase-change layer 311 is as follows: Example to illustrate.
  • FIG. 10 is a schematic diagram of state 1 during the manufacturing process of a phase-change storage layer provided by an embodiment of the present application.
  • a first phase-change material film layer 33 can be formed on the second electrode 20, wherein the first phase-change material film layer 33 can be a chalcogenide compound on the second electrode 20 by deposition or the like. formed film layer.
  • FIG. 11 is a schematic diagram of state 2 during the manufacturing process of a phase-change storage layer provided by an embodiment of the present application.
  • the first phase-change material film layer 33 can be etched by photolithography, etc., so that the first phase-change material film layer 33 forms at least one first phase-change layer 311, and the formed first phase
  • the extending direction of the variable layer 311 may be perpendicular to the extending direction of the second electrode 20 .
  • a plurality of first phase change layers 311 arranged at intervals along the x direction and/or y direction can be formed on the second electrode 20.
  • the first phase change layer 311 is described as an example.
  • FIG. 12 is a schematic diagram of state three during the manufacturing process of a phase-change storage layer provided by an embodiment of the present application.
  • the second electrode 20 and the first phase-change layer 311 are covered with a second phase-change material film layer 34, wherein the second phase-change material film layer 34 can also be formed by deposition of a chalcogenide compound, etc. film layer, and the phase transition temperature of the second phase change material film layer 34 is higher than the phase transition temperature of the first phase change material film layer 33 .
  • FIG. 13 is a schematic diagram of state four during the manufacturing process of a phase-change storage layer provided by an embodiment of the present application.
  • an etching stopper layer 60 is provided on the second phase-change material film layer 34.
  • the first region a and the second region b can be divided on the second electrode 20, wherein, the first phase
  • the area opposite to the change layer 311 and the second phase change material film layer 34 surrounding the outer periphery of the first phase change layer 311 is the first area a, and the area between the two first areas a is the second area b.
  • One region a is covered with an etch barrier layer 60, the second region b and other regions are not covered, and then the second phase-change material film layer 34 can be etched by photolithography, so that the first phase-change The two sides of the layer 311 and the second phase change material film layer 34 above the first phase change layer 311 will not be etched away.
  • FIG. 14 is a schematic diagram of a phase-change storage layer in state five during the manufacturing process provided by the embodiment of the present application.
  • the etching stopper layer 60 is removed, and then the insulating material layer 70 is covered on the second electrode 20 and the second phase-change material film layer 34 .
  • FIG. 15 is a schematic diagram of a phase-change storage layer in state six during the manufacturing process provided by the embodiment of the present application.
  • the insulating material layer 70 is covered with an etching stopper layer 60. Specifically, as shown in FIG. b covers the etch stop layer 60, and then can be etched by photolithography to form the second phase change layer 312 on both sides of the first phase change layer 311, and make the first phase change layer 311 and the second phase change layer 312 The phase change layer 312 is exposed.
  • Fig. 16 is a schematic diagram of state 7 during the manufacturing process of a phase-change storage layer provided by an embodiment of the present application.
  • part of the insulating material layer 70 is removed to form the first insulating layer 50 , and the height of the first insulating layer 50 formed after removal remains flush with the first phase change layer 311 and the second phase change layer 312 .
  • two phase-change memory layers 31 are formed that are separated from each other by the first insulating layer 50 , and the first electrode 10 and the like are formed on them to form the phase-change memory layer 100 .
  • the electrical connector 32 can be formed on the second electrode first, and then the phase change storage layer 31 is formed on the electrical connector in the above-mentioned manner.
  • phase-change storage layer 31 composed of a plurality of first phase-change layers and second phase-change layers.
  • the phase-change storage layer 31 includes multiple layers of first phase-change layers 311 and second phase-change layers 312, and the first phase-change layers 311 and the second phase-change layers 312 are alternately arranged
  • the formation process of the structure is described as an example.
  • FIG. 17 is a schematic diagram of state 1 during the manufacturing process of another phase-change storage layer provided by the embodiment of the present application.
  • a first phase-change material film layer 33 is formed on the second electrode 20, wherein the first phase-change material film layer 33 can be formed on the second electrode 20 by means of deposition or the like. film layer.
  • FIG. 18 is a schematic diagram of another phase-change storage layer in state 2 during the manufacturing process provided by the embodiment of the present application.
  • the first phase-change material film layer 33 can be etched by photolithography, etc., so that the first phase-change material film layer 33 forms at least one first phase-change layer 311.
  • the layer is the first phase change layer 311a, wherein the extension direction of the first phase change layer 311a is perpendicular to the extension direction of the first electrode 10 .
  • the first phase-change layer 311a formed by etching to form two intervals is taken as an example for illustration.
  • FIG. 19 is a schematic diagram of state three in another manufacturing process of a phase-change storage layer provided by an embodiment of the present application.
  • the second electrode 20 and the first phase-change layer 311a are covered with a second phase-change material film layer 34, wherein the second phase-change material film layer 34 can also be a chalcogenide compound by deposition or the like.
  • the formed film layer, and the phase transition temperature of the second phase change material film layer 34 is higher than the phase transition temperature of the first phase change material film layer 33 .
  • FIG. 20 is a schematic diagram of another phase-change storage layer in state 4 during the manufacturing process provided by the embodiment of the present application.
  • the second phase-change material film layer 34 can be etched by photolithography, so that the second phase-change material film layer 34 remains on both sides of the first phase-change layer-311a, and the remaining parts
  • the second phase-change material film layer 34 is etched, thereby forming the second phase-change layer 312 on both sides of the first phase-change layer 311a, and at the same time the first phase-change layer 311a is exposed, and the second phase-change layer 311a is exposed.
  • the phase change layer 312 is a second phase change layer 1 312a.
  • the second phase change material film layer 34 in FIG. 19 when the second phase change material film layer 34 in FIG. 19 is directly etched by photoetching, it is located at the end of the first phase change layer one 311a away from the second electrode 20, due to the influence of photoetching , the four corners of the end are easily etched by photoetching, and the etching speed is fast, so that the end face of the end is elliptical.
  • FIG. 21 is a schematic diagram of another phase-change storage layer in state five during the manufacturing process provided by the embodiment of the present application.
  • the first phase change material film layer 33 is covered on the second electrode 20 , the second phase change layer one 312 a and the first phase change layer one 311 a.
  • Fig. 22 is a schematic diagram of another phase-change storage layer in state six during the manufacturing process provided by the embodiment of the present application.
  • the first phase-change material film layer 33 can be etched by photolithography to form the first phase-change layer 311 on both sides of the second phase-change layer-312a, and make the second phase-change layer 312a Both the first phase change layer 312a and the first phase change layer 311a are exposed, and the first phase change layer 311 is referred to as the first phase change layer two 311b.
  • both the second phase change layer 312a and the first phase change layer 311a may not be exposed, and a part of the end of the phase change storage layer 31 is finally removed (refer to FIG. 27 ), so that each phase change layer is exposed.
  • Fig. 23 is a schematic diagram of another phase-change storage layer in state 7 during the manufacturing process provided by the embodiment of the present application.
  • the second phase change material film layer 34 is covered on the second electrode 20 and the first phase change layer 2 311b.
  • FIG. 24 is a schematic diagram of state eight in another phase change storage layer manufacturing process provided by the embodiment of the present application.
  • the second phase-change material film layer 34 can be etched by photolithography to form the second phase-change layer 312b on both sides of the first phase-change layer 311b, and the The first phase change layer 2 311b, the second phase change layer 1 312a and the first phase change layer 311a are exposed, so that two phase change storage layers 31 are formed on the second electrode 20, and each phase change storage layer 31 It includes multiple layers of first phase change layer 311 and second phase change layer 312 .
  • FIG. 25 is a schematic diagram of state nine in another manufacturing process of a phase change storage layer provided by an embodiment of the present application.
  • an insulating material layer 70 is covered on the first electrode 10 and the formed phase-change storage layer 31 .
  • FIG. 26 is a schematic diagram of another phase-change storage layer in state ten during the manufacturing process provided by the embodiment of the present application.
  • part of the insulating material layer 70 is removed to form the first insulating layer 50 and expose the phase change storage layer 31 .
  • two phase-change memory layers 31 are formed that are separated from each other by the first insulating layer 50 , and the first electrode 10 and the like are formed on them to form the phase-change memory layer 100 .
  • Fig. 27 is a schematic diagram of another phase-change storage layer in the state eleven during the manufacturing process provided by the embodiment of the present application.
  • phase-change storage layer 31 when removing the insulating material layer 70 to form the first insulating layer 50 between the phase-change storage layers 31, a part of the end of the phase-change storage layer 31 can be appropriately removed, so that the phase-change storage layer 31 Each phase-change layer in the electrode 20 is exposed, so that a phase-change storage layer is formed on the second electrode 20 .
  • FIG. 28 is a schematic diagram of state 1 during the manufacturing process of another phase-change storage layer provided by the embodiment of the present application.
  • a first insulating layer 50 may be formed on the second electrode 20 .
  • the first insulating layer 50 may be formed by etching a strip-shaped first insulating layer 50 as shown in FIG. 28 after depositing a layer of insulating material 70 on the second electrode 20 .
  • a plurality of stripe-shaped first insulating layers 50 may be formed by etching on the second electrode 20 (refer to FIG. 36 ).
  • FIG. 29 is a schematic diagram of another phase-change storage layer in the second state during the manufacturing process provided by the embodiment of the present application.
  • the second phase change material film layer 34 is covered on the second electrode 20 and the first insulating layer 50 .
  • the second phase-change material film layer 34 may be a film layer formed by deposition of a chalcogenide compound.
  • FIG. 30 is a schematic diagram of another phase-change storage layer in state three during the manufacturing process provided by the embodiment of the present application.
  • the second phase-change material film layer can be etched by photolithography, so that the second phase-change material film layer 34 remains on both sides of the first insulating layer 50, and the second phase-change material film layer 34 on the remaining part
  • the phase-change material film layers 34 are all etched, so that the second phase-change layer 312 is formed on both sides of the first insulating layer 50, and the second phase-change layer 312 is referred to as a second phase-change layer 1 312a.
  • FIG. 31 is a schematic diagram of another phase-change storage layer in state four during the manufacturing process provided by the embodiment of the present application.
  • the first phase-change material film layer 33 is covered on the second electrode 20 and the second phase-change material layer one 312a.
  • the first phase-change material film layer 33 may be a film layer formed by deposition of a chalcogenide compound, and the phase transition temperature of the first phase-change material film layer 33 is lower than that of the second phase-change material film layer 34 change temperature.
  • FIG. 32 is a schematic diagram of yet another phase-change storage layer in state five during the manufacturing process provided by the embodiment of the present application.
  • the first phase-change material film layer 33 can be etched by photolithography to form the first phase-change layer 311 on both sides of the second phase-change layer 312a, and make the second phase-change layer 312a Phase change layer one 312a is exposed.
  • Fig. 33 is a schematic diagram of another phase change storage layer in state six during the manufacturing process provided by the embodiment of the present application.
  • the second phase change material film layer 34 is covered on the second electrode 20 , the first phase change layer 312 a and the first phase change layer 311 .
  • FIG. 34 is a schematic diagram of another phase-change storage layer in state 7 during the manufacturing process provided by the embodiment of the present application.
  • the second phase-change material film layer 34 can be etched by photolithography to form the second phase-change layer 312 b on both sides of the first phase-change layer 311 .
  • phase-change storage layer 31 includes multiple layers of the first phase-change layer 311 and the second phase-change layer 312 , alternate deposition and etching may be continued to form the multi-layer phase-change storage layer 31 .
  • Figure 35 is a schematic side view of another phase change storage layer in state eight during the manufacturing process provided by the embodiment of the present application
  • Figure 36 is a side view of another phase change storage layer in state eight in the manufacturing process provided by the embodiment of the present application
  • the schematic diagram of the top view is a schematic side view of another phase change storage layer in state eight during the manufacturing process provided by the embodiment of the present application.
  • phase-change storage layer 31 As shown in FIG. 35 , a part of the end portion of the entire formed phase-change storage layer is properly removed, so that each phase-change layer in the phase-change storage layer 31 is exposed.
  • FIG. 36 two strip-shaped phase-change storage layers 31 are formed on the second electrode 20 and are separated from each other by the first insulating layer 50 .
  • FIG. 37 is a schematic top view of another phase-change storage layer in state nine during the manufacturing process provided by the embodiment of the present application.
  • a plurality of gaps 80 can be formed at intervals in the extending direction of the strip-shaped first insulating layer 50 and the phase-change storage layer 31 by etching, thus forming multiple rows and columns of spaced phase-change Storage layer 31.
  • FIG. 38 is a schematic top view of another phase-change storage layer in state ten during the manufacturing process provided by the embodiment of the present application.
  • an insulating material is deposited in the gap 80 to form the first insulating layer 50, thus forming a plurality of phase-change storage layers 31 isolated from each other by the first insulating layer 50, and the first electrode 10 is continuously formed thereon. etc., the phase change memory 100 can be formed.
  • the embodiment of the present application also provides an electronic device, which may include but not limited to mobile phones, tablet computers, notebook computers, ultra-mobile personal computers (ultra-mobile personal computer, UMPC), handheld computers, walkie-talkies, netbooks, POS Fixed terminals or mobile terminals with storage functions such as mobile phones, personal digital assistants (PDA), wearable devices, smart TVs, virtual reality devices, etc.
  • PDA personal digital assistants
  • the electronic device may include a housing, the phase change memory may be disposed in the housing, and the phase change memory may be electrically connected to the controller of the electronic device.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a An indirect connection through an intermediary may be an internal connection between two elements or an interaction relationship between two elements.

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Abstract

本申请实施例提供一种相变存储器及电子设备，该相变存储器包括第一电极和第二电极，以及位于第一电极和第二电极之间的相变存储单元，相变存储单元包括相变存储层，相变存储层至少包括层叠的第一相变层和第二相变层，第一相变层和第二相变层的位于同侧的第一端与第一电极耦合电连接，第一相变层和第二相变层的处于另一侧的第二端与第二电极耦合电连接，电流经过第二电极流经相变存储单元后从第一电极流出，即流经相变存储层上的电流方向与相变存储层的层叠方向垂直，降低了在电流作用下相变层中相变材料分子沿层叠方向而在膜层之间发生的扩散，保证相变存储单元的功能，从而提升相变存储器的循环耐久性。

Description

一种相变存储器及电子设备 技术领域
本申请涉及存储技术领域，特别涉及一种相变存储器及电子设备。
背景技术
相变存储器(Phase Change Memory，简称PCM)为非易失性存储器，主要利用相变材料，如硫系化合物在晶态和非晶态巨大的导电性差异来存储数据。相变材料可以在特定的脉冲下，在具有不同结构和不同电阻率的两种状态间转换，这两种状态即为高电阻率的非晶态和低电阻率的晶态，从而利用电阻的差别区分两种逻辑状态“0”和“1”。相变存储器具有高速、高密度以及低功耗等特点，而被广泛的使用于电子设备的存储应用中。
目前，现有的相变存储器，为提高相变存储材料的相变速度，相变存储层多采用超晶格结构或多层膜层叠结构。具体的，如相变材料层可以由两层不同的材料组成，并且可以有N个重复单元，具体的，两层相变材料膜层为例，第一膜层和第二膜层层叠设置，在相变存储器的衬底上铺设时，第一膜层铺设在衬底上，第二膜层铺设在第一膜层上，流经相变存储器的电流方向与层叠方向相平行。
然而，相变膜层的相变温度较高，膜层之间的扩散又会在电流的作用下加剧，从而影响各膜层之间的组分，使膜层间分界模糊化，易导致相变材料层功能的失效，缩短相变存储器的使用寿命。
发明内容
本申请提供一种相变存储器及电子设备，解决了现有的相变存储器，膜层之间的扩散在电流作用下加剧而导致功能失效，缩短相变存储器使用寿命的问题。
本申请的第一方面提供一种相变存储器，包括：第一电极、第二电极和相变存储单元，所述相变存储单元位于所述第一电极和所述第二电极之间；
所述相变存储单元包括相变存储层，所述相变存储层包括层叠的第一相变层和第二相变层，所述第一相变层的处于同一侧的第一端被耦合至所述第一电极，所述第一相变层和所述第二相变层的处于另一侧的第二端被耦合至所述第二电极。电流可从第二电极通入经过相变存储单元后从第一电极流出形成回路。
也就是说，流经相变存储层的电流方向与第一相变层和第二相变层的延伸方向相平行，与相变存储层的层叠方向相垂直，这样在电流的作用下相变层中相变材料分子倾向于沿着电流方向扩散，也就沿着各自所在的相变层的延伸方向扩散，降低了在电流作用下相变层中相变材料分子沿层叠方向而发生在膜层之间的扩散，从而减小了各相变层间分界的模糊化程度，保证相变存储层的功能，从而提升相变存储器的循环耐久性，保证其使用寿命。
在一种可能的实现方式中，所述第一相变层处于两层所述第二相变层之间，所述第二相变层的相变温度大于所述第一相变层的相变温度。当加热时第一相变层发生相变，第二相变层由于所需的相变温度更高，不会发生相变，第二相变层的存在可以对第一相变层的结晶过程起到诱导作用，第二相变层可以作为第一相变层结晶的模板，使其沿第二相变层的延伸方向结晶形成膜层，有助于提升第一相变层的晶化速度，从而提高存储速度。
在一种可能的实现方式中，所述第二相变层的相变温度与所述第一相变层的相变温度之间的温度差大于等于100℃。
在一种可能的实现方式中，所述第一电极的延伸方向与所述第二电极的延伸方向垂直，所述相变存储单元与所述第一电极的延伸方向和所述第二电极的延伸方向均垂直。
在一种可能的实现方式中，所述存储单元还包括电连接件，所述第二端通过所述电连接件与所述第二电极连接，所述电连接件用于连通或断开所述第二端与所述第二电极之间的连接。
这样电连接件可以作为开关使用，电连接件可以连通相变存储层和第二电极，从而使电流经过第二电极并流经相变存储层后通过第一电极流出形成回路。或者电连接件也可以使相变存储层和第二电极断开，电流无法导通经过相变存储层。当相变存储单元为多个，电连接件作为开关可以选择性的导通所需的相变存储单元，实现数据的存储。
在一种可能的实现方式中，所述电连接层包括选通管。
在一种可能的实现方式中，还包括第一绝缘层，所述第一电极、所述第二电极和所述相变存储单元均为多个，多个所述第一电极相互平行设置，多个所述第二电极相互平行设置；
所述第一绝缘层环绕覆盖在所述相变存储单元的外周上，相邻的两相变存储单元之间均具有所述第一绝缘层。也即相变存储单元之间的间隙内均填充有第一绝缘层，保证相变存储单元之间绝缘性的同时，提高相变存储单元的设置稳定性，提升整个器件的稳定性。
在一种可能的实现方式中，还包括第二绝缘层，相邻的两个所述第一电极之间以及相邻的两个所述第二电极之间均具有所述第二绝缘层。这样可以保证第一电极与第一电极之间，以及第二电极与第二电极之间的绝缘性，以避免连通而导致电流走向的改变。
在一种可能的实现方式中，所述第一相变层和所述第二相变层的成型材质均至少包括硫系化合物。
本申请的第二方面提供一种电子设备，包括壳体和上述任一所述的相变存储器，所述相变存储器设置在所述壳体内。
通过包括相变存储器，该相变存储器中流经相变存储单元上的电流方向与相变存储单元中包含的相变层的延伸方向相平行，与相变层的层叠方向相垂直，这样就能够降低电流作用下导致的相变层间元素的相互扩散，减小相变层间分界的模糊化程度，保证相变存储单元的功能，从而提升相变存储器的循环耐久性，保证其使用寿命，进 而有助于提升电子设备的耐久性，并提升用户使用体验。
附图说明
图1为本申请实施例提供的一种相变材料受热状态转换的示意图；
图2为本申请实施例提供的一种相变存储器的结构示意图；
图3为一种现有的相变存储器的剖面结构示意图；
图4为本申请实施例提供的一种相变存储器沿图2中A-A的剖面局部结构示意图；
图5为本申请实施例提供的一种相变存储层的结构示意图；
图6为本申请实施例提供的另一种相变存储器的剖面结构示意图；
图7为本申请实施例提供的另一种相变存储器的结构示意图；
图8为本申请实施例提供的另一种相变存储器沿图7中B-B的剖面局部结构示意图；
图9为本申请实施例提供的另一种相变存储器的剖面结构示意图；
图10为本申请实施例提供的一种相变存储层制造过程中处于状态一时的示意图；
图11为本申请实施例提供的一种相变存储层制造过程中处于状态二时的示意图；
图12为本申请实施例提供的一种相变存储层制造过程中处于状态三时的示意图；
图13为本申请实施例提供的一种相变存储层制造过程中处于状态四时的示意图；
图14为本申请实施例提供的一种相变存储层制造过程中处于状态五时的示意图；
图15为本申请实施例提供的一种相变存储层制造过程中处于状态六时的示意图；
图16为本申请实施例提供的一种相变存储层制造过程中处于状态七时的示意图；
图17为本申请实施例提供的另一种相变存储层制造过程中处于状态一时的示意图；
图18为本申请实施例提供的另一种相变存储层制造过程中处于状态二时的示意图；
图19为本申请实施例提供的另一种相变存储层制造过程中处于状态三时的示意图；
图20为本申请实施例提供的另一种相变存储层制造过程中处于状态四时的示意图；
图21为本申请实施例提供的另一种相变存储层制造过程中处于状态五时的示意图；
图22为本申请实施例提供的另一种相变存储层制造过程中处于状态六时的示意图；
图23为本申请实施例提供的另一种相变存储层制造过程中处于状态七时的示意图；
图24为本申请实施例提供的另一种相变存储层制造过程中处于状态八时的示意图；
图25为本申请实施例提供的另一种相变存储层制造过程中处于状态九时的示意图；
图26为本申请实施例提供的另一种相变存储层制造过程中处于状态十时的示意 图；
图27为本申请实施例提供的另一种相变存储器制造过程中处于状态十一时的示意图；
图28为本申请实施例提供的又一种相变存储层制造过程中处于状态一时的示意图；
图29为本申请实施例提供的又一种相变存储层制造过程中处于状态二时的示意图；
图30为本申请实施例提供的又一种相变存储层制造过程中处于状态三时的示意图；
图31为本申请实施例提供的又一种相变存储层制造过程中处于状态四时的示意图；
图32为本申请实施例提供的又一种相变存储层制造过程中处于状态五时的示意图；
图33为本申请实施例提供的又一种相变存储层制造过程中处于状态六时的示意图；
图34为本申请实施例提供的又一种相变存储层制造过程中处于状态七时的示意图；
图35为本申请实施例提供的又一种相变存储层制造过程中处于状态八时的侧视示意图；
图36为本申请实施例提供的又一种相变存储层制造过程中处于状态八时的俯视示意图；
图37为本申请实施例提供的又一种相变存储层制造过程中处于状态九时的俯视示意图；
图38为本申请实施例提供的又一种相变存储层制造过程中处于状态十时的俯视示意图。
附图标记说明：
100-相变存储器；           10-第一电极；             10a-电极一；
10b-电极二；               20-第二电极；             20a-电极三；
20b-电极四；               20c-电极五；              30-相变存储单元；
30a-相变存储单元一；       30b-相变存储单元二；      30c-相变存储单元三；
31-相变存储层；            31a-相变存储层一；        31c-相变存储层三；
311-第一相变层；           311a-第一相变层一；       311b-第一相变层二；
312-第二相变层；           312a-第二相变层一；       312b-第二相变层二；
32-电连接件；              32a-电连接件一；          32c-电连接件二；
33-第一相变材料膜层；      34-第二相变材料膜层；     40-第二绝缘层；
50-第一绝缘层；            60-刻蚀阻挡层；           70-绝缘材料层。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非 旨在限定本申请。
相变存储器具有高速、高密度、低功耗以及非易失等特性而逐渐被应用于电子设备，如UAB闪存盘、电脑以及手机等中作为存储单元使用。相变存储器是利用特殊材料在晶态和非晶态之间相互转化时所表现出来的导电性差异来存储数据的。如硫系化合物等相变材料，在特定的脉冲下，会在高电阻率的非晶态和低电阻率的晶态之间相互转换，从而实现“0/1”的存储。
比如，非晶状态可以对应“0”，为高阻态，晶化状态可以对应“1”，为低阻态。相变存储器中通常包括上电极、下电极和位于上电极和下电极之间的相变存储层，通过上电极和下电极对相变存储层通入电流，产生的焦耳热使相变存储层的相变材料在短时间内温度迅速升高，实现状态的转换。
具体的，图1示出了一种相变材料受热状态转换的示意图，参见图1所示，当产生的焦耳热使相变材料温度急剧上升，超过熔融温度后，淬火(撤去电流)，会使相变材料保持非晶状态，从而实现“0”的编程，也叫复位操作或写“0”。
当产生的焦耳热温度不超过相变材料的熔融温度，但是高于晶化温度时，相变材料开始晶化，当一定体积的相变材料实现晶化后，撤去电流脉冲，降温就能够使相变材料最终保持晶化装置，实现“1”的写入，也叫置位操作或写“1”。这样通过写“0”和“1”就能够实现二进制形式存储。
基于以上原理，以下结合附图，对本申请实施例提供的相变存储器进行详细的说明。
图2为本申请实施例提供的一种相变存储器的结构示意图。
参见图2所示，本申请实施例提供的一种相变存储器，包括多个第一电极10、多个第二电极20和多个相变存储单元30。其中，多个第一电极10可以相互平行且并列设置，多个第二电极20可以相互平行且并列设置，第一电极10可以位于第二电极20的上方，第一电极10的延伸方向(如图中的x方向)可以与第二电极20的延伸方向(如图中的y方向)相垂直。
相变存储单元30位于第一电极10和第二电极20之间，每一个第一电极10与一个第二电极20之间对应具有一个相变存储单元30，也即每个相变存储单元30的两端分别与一个第一电极10和一个第二电极20电连接。相变存储单元30的延伸方向(如图中的z方向)可以与第一电极10的延伸方向、第二电极20的延伸方向均垂直，以便于第一电极10、第二电极20以及相变存储单元30之间的布局设置。
其中，相变存储单元30中包括有相变存储层31，相变存储层31为由相变材料形成的膜层，在电流的焦耳热作用下能够实现晶态和非晶态之间的转换。
电流可从第二电极20通入经过相变存储单元30后从第一电极10流出形成回路，电流经过相变存储单元30产生的焦耳热会使相变存储层31的相变材料发生状态的转换，当相变材料处于非晶状态时，即为高阻态，可以实现写“0”，当相变材料处于晶态，即为低阻态，可以实现写“1”，从而可以通过二进制数字“1”和“0”来实现信息的存储。
其中，如图2中所示，相变存储单元30为多个，需要说明的是，在使用某一相变存储单元30进行数据的存储时，可仅导通该相变存储单元30对应连接的第一电极10 和第二电极20，使电流从对应的第二电极20经过该相变存储单元30后从第一电极10流出形成回路。
图3为一种现有的相变存储器的剖面结构示意图。
现有的相变存储器中，相变存储层31多采用超晶格结构或多层膜层叠加结构。具体的，相变存储层31包括两层及以上个叠加的相变层，参见图3所示，以相变存储层31包括第一相变层311和第二相变层312为例，形成第一相变层311和第二相变层312的相变材料可以均为硫系化合物相变材料，其中，形成第一相变层311的相变材料和形成第二相变层312的相变材料不同，使第一相变层311和第二相变层312发生相变所需的相变温度不同。
第一相变层311设置在第二电极20上，第二相变层312铺设在第一相变层311上，第一电极设置在第二相变层312上。也即靠近第二电极20的第一相变层311与第二电极20电耦合连接，靠近第一电极10的第二相变层312与第一电极10电耦合连接，第一相变层311和第二相变层312的层叠方向即为第二电极20指向第一电极10的方向。
电流从第二电极20通入并经过相变存储层31后从第一电极10流出，则流经相变存储层的电流的方向为从第二电极20指向第一电极10的方向，如图中的i方向，也就是说，流经相变存储层上的电流方向与相变存储层的层叠方向相平行。
然而，由于相变存储层本身受热后，相变材料在叠加的膜层之间就会发生分子的扩散。而当流经相变存储层上的电流方向与相变存储层的层叠方向相平行时，相变材料分子会在电流的引导下倾向于沿着电流方向发生扩散，也即沿着层叠方向扩散，这样就会加剧膜层之间分子的相互扩散，影响各膜层的组分，导致膜层之间的分界逐渐模糊化，降低相变存储器的功能稳定性。随着使用时间增加，模糊化严重易导致相变存储层的功能失效，缩短相变存储器的使用寿命。
图4为本申请实施例提供的一种相变存储器沿图2中A-A的剖面局部结构示意图，图5为本申请实施例提供的一种相变存储层的结构示意图。
为解决上述问题，本申请实施例提供的相变存储其中的相变存储层31，至少包括层叠的第一相变层311和第二相变层312，第一相变层311和第二相变层312均为由相变材料形成的膜层，其中，形成第一相变层311的相变材料和形成第二相变层312的相变材料不同，使第一相变层311发生相变所需的相变温度和第二相变层312发生相变所需的相变温度不同。
具体的，形成第一相变层311和第二相变层312的相变材料可以是硫系化合物，如GeTe、Sb 2Te 3、Ge 2Sb 2Te 5、PbGeSb、GeTeAs、BiTe、AgInSbTe、Ge 1Sb 2Te 4等。
硫系化合物在室温条件下，能够保持稳定的非晶态和晶态，当电流通过相变存储层31时，产生的焦耳热会使硫系化合物可以从非晶体转换成晶态，还可以从晶态转换成非晶态，在硫系化合物达到非晶态和晶态时，在不施加额外的外界影响的情况下可保持该状态，因此可以实现非易失性的存储。硫系化合物在非晶态和晶态时具有不同的电阻值，从而利用其晶态(低电阻)和非晶态(高电阻)分别代表二进制数字“1”和“0”实现信息的存储。
参见图4所示，本申请实施例中，第一相变层311和第二相变层312处于同一侧 的第一端被耦合至第一电极10，如相变存储层31靠近第一电极10的一侧为第一侧310a，第一相变层311和第二相变层312的第一端均位于第一侧310a处，并均与第一电极10电连接。
第一相变层311和第二相变层312处于另一侧的第二端31b被耦合至第二电极20，如相变存储层31靠近第二电极20的一侧为第二侧310b(与第一侧310a相对)，第一相变层311的第二端和第二相变层312的第二端均位于第二侧310b，并均与第二电极20电连接。
这样第一相变层311的延伸方向可以为从第二电极20指向第一电极10的方向(如图2中的z方向)，第二相变层312的延伸方向可以为从第二电极20指向第一电极10的方向，相变存储层的层叠方向为与第一相变层311和第二相变层312相垂直的方向，如图中的x方向。
电流可以从第二电极20通入经过相变存储单元30后从第一电极10流出形成回路，则流经相变存储单元30的相变存储层31的电流方向，与相变存储层31中第一相变层311和第二相变层312的延伸方向平行，与相变存储层31的层叠方向垂直，电流方向如图中的i方向。
也就是说，流经相变存储层31上的电流方向i与相变存储层中包含的第一相变层和第二相变层的延伸方向z相平行，与相变存储层31的层叠方向x相垂直，这样在电流的作用下相变层中相变材料分子倾向于沿着电流方向扩散，也就是沿着各自所在的相变层延伸方向扩散，降低了在电流作用下相变层中相变材料分子沿层叠方向而在膜层之间发生的扩散，从而减小了各相变层间分界的模糊化程度，保证相变存储层31的存储功能，从而提升相变存储器100的循环耐久性，保证其使用寿命。
其中，第二相变层312的相变温度可以大于第一相变层311的相变温度，具体的，相变温度是发生状态转换，即非晶态和晶态之间转换所需的温度，可以包括有结晶温度(Tc)和熔融温度(Tm)，结晶温度是指相变材料从非晶状态转换为结晶状态所需的温度，熔融温度时指相变材料从结晶状态转换为非晶状态所需的温度。
第一相变层311的相变温度小于第二相变层312的相变温度，也即第二相变层312相对于第一相变层311具有更好的热稳定性。可以通过控制焦耳热的大小，使在写“0”以及写“1”的存储过程中，第一相变层311发生相变，第二相变层312由于所需的相变温度更高，不会发生相变。
如从非晶态转换为结晶态时，第二相变层312的存在可以对第一相变层311的结晶过程起到诱导作用，第二相变层312可以作为第一相变层311结晶的模板，使其沿第二相变层311的延伸方向结晶形成膜层，有助于提升第一相变层311的晶化速度，加快写“1”的操作，从而提高存储速度。
第一相变层311和第二相变层312的成型材质可以均为硫系化合物的相变材料，具体的，如第一相变层311的相变材料可以是Sb nTe m类型的化合物，第二相变层312的相变材料可以是Ge aSb nTe m类型的化合物。或者，第一相变层311的相变材料可以是Ge aSb nTe m类型的化合物，第二相变层312的相变材料可以是碳元素等掺杂的Ge aSb nTe m类型的化合物。第二相变层312和第一相变层311的相变材料可根据流经相变存储器的电流产生的焦耳热大小选择设定，在本申请实施例中不做限制，能够保证 第二相变层的相变温度大于第一相变层的相变温度即可。
其中，第二相变层312的相变温度和第一相变层311的相变温度之间的温度差值可以大于等于100℃。当两者的相变温度差值较小时，容易导致在第一相变层311相变的同时，第二相变层312也发生一定的相变，使第二相变层312不能为第一相变层311的晶化过程起到很好的模板作用，因此当两者的温度差值大于等于100℃时，能够保证相变存储层31具有较好的存储速度。
本申请实施例中，相变存储层31可以只包括有一层第一相变层311和一层第二相变层312。
或者，相变存储层31中可以具有多层第一相变层311和多层第二相变层312，第一相变层311和第二相变层312可以交替层叠设置。如相变存储层31可以只包括有三层，分别为第一相变层311以及位于第一相变层311两侧的第二相变层312。或者，相变存储层31也可以包括有四层，分别为两层第一相变层311和两层第二相变层312，第一相变层311和第二相变层312交替层叠设置。
其中，在相变层存储层31尺寸固定的情况下，包括多层第一相变层311和多层第二相变层312，第一相变层311和第二相变层312的尺寸宽度就会相对较小，这样就能够便于第一相变层311发生相变，有助于提升相变速度，降低功耗，提高存储的能力。
其中，参见图5所示，第一相变层311可以处于两层第二相变层312之间，一方面，位于两侧的第二相变层312能够为第一相变层311的状态转换提供更好的模板作用，进一步提升晶化速度，提高存储速度。另一方面，第二相变层312在电流流经的过程中也会产热，产生的热量有助于第一相变层311中分子的重构，对于第一相变层311能够起到一定的修复作用，进而有助于第一相变层311的状态转换。
另外，使第一相变层311两侧均有第二相变层312，相变存储层31由第二相变层312、第一相变层311、第二相变层312这样依次交替排列的方式形成，第二相变层312具有更高的热稳定性，对第一相变层311的散热会起到一定的妨碍作用，使第一相变层311的热量不容易散出，这样有助于降低第一相变层311完成一次相变所需的功耗也即降低了写入功耗，降低了相变存储器100的存储功耗。
第一相变层311两侧的第二相变层312，如分别为第二相变层一和第二相变层二，形成第二相变层一的相变材料和形成第二相变层二的相变材料可以相同，也即两层的第二相变层312的相变温度可以相同。或者，形成第二相变层一的相变材料和形成第二相变层二的相变材料不同，也即两层第二相变层312的相变温度可以不同。
第一相变层311可以只有一层，两侧分别设置一层第二相变层312，或者，第一相变层311也可以包括有两层及两层以上，第一相变层311两侧均具有第二相变层312，第一相变层311和第二相变层312交替排列形成相变存储层31。
其中，相变存储层31可以是如图4中所示的长方形柱状结构，第一相变层311的两侧分别设置有第二相变层312。或者，相变存储层31也可以是圆柱状结构，如第一相变层311形成环形柱状结构，在第一相变层311的内侧以及外侧周向上分别具有第二相变层312。或者，相变存储层31也可以是其他形状，具体形成的结构形状在本申请实施例中不做限制。
另外，形成的第一相变层311和第二相变层312的端面可以是平整的水平面，或者，端面也可以是具有凸起或凹陷结构的扭曲面等，在本申请实施例中不做限制。
图6为本申请实施例提供的另一种相变存储器的剖面结构示意图。
本申请实施例中，参见图6所示，相变存储单元30的外周上可以环绕设置有第一绝缘层50，第一绝缘层50可以保证相邻的相变存储单元30之间、以及相变存储单元30与外环境之间的绝缘性。
可以使任意相邻的两个相变存储单元30之间均具有第一绝缘层50，也即相变存储单元30之间的间隙内均填充有第一绝缘层50，保证相变存储单元30之间绝缘性的同时，提高相变存储单元30的设置稳定性，提升整个器件的稳定性。
同时，在电子设备中具有多个相变存储器100的情况下，第一绝缘层50也能够起到绝缘隔离相邻两个相变存储器100的作用，保证相变存储器100不会相互影响。
另外，在相邻的两个第一电极10之间、以及相邻的两个第二电极20之间可以设置有第二绝缘层40，也即相邻的两个第一电极10的间隙之间填充有第二绝缘层40，相邻的两个第二电极20的间隙之间也可以填充有第二绝缘层40，这样可以保证第一电极10与第一电极10之间，以及第二电极20与第二电极20之间的绝缘性，以避免连通而导致电流走向的改变。
图7为本申请实施例提供的另一种相变存储器的结构示意图，图8为本申请实施例提供的另一种相变存储器沿图7中B-B的剖面局部结构示意图，图9为本申请实施例提供的另一种相变存储器的剖面结构示意图。
结合图7和图8所示，相变存储单元30还可以包括电连接件32，相变存储层31的一端，也即第一相变层311和第二相变层312的第一端与第一电极10电连接，相变存储层31的另一端，即第一相变层311和第二相变层312的第二端31b与电连接件32连接，电连接件32与第二电极20连接。
电连接件32用于使第一相变层311和第二相变层312的第二端与第二电极20连通或断开，也即电连接件32可以作为开关使用，电连接件32可以连通相变存储层31和第二电极20，从而使电流经过第二电极20并流经相变存储层31后通过第一电极10流出形成回路。或者电连接件32也可以使相变存储层31和第二电极20断开，电流无法导通经过相变存储层31。
参见图7所示，当相变存储单元30为多个，电连接件32作为开关可以选择性的导通所需的相变存储单元30，实现数据的存储。具体的，如图7所示，以第一电极10有两个，分别为电极一10a和电极二10b，第二电极20有三个，分别为电极三20a、电极四20b和电极五20c，电极一10a与电极三20a之间具有一个相变存储单元，为相变存储单元一30a，电极一10a与电极四20b之间具有一个相变存储单元，为相变存储单元二30b，电极一10a与电极五20c之间具有一个相变存储单元，为相变存储单元三30c为例来说明。
其中，每个相变存储单元30包括相变存储层31和电连接件32，如相变存储单元一30a包括相变存储层一31a和电连接件一32a，相变存储单元二30b包括相变存储层二和电连接件二，相变存储单元三30c包括相变存储层三31c和电连接件三32c。当需要使用相变存储单元一30a进行数据存储时，可以使电连接件一32a连通相变存储层 一31a和电极三20a，而其余不需要进行存储的相变存储单元中电连接件32断开，这样电流经过电极三20a并依次流经电连接件一32a和相变存储层一31a后从电极一10a中流出形成回路，从而利用相变存储层一31a的状态转换实现数据的存储。
相应的，当需要使用相变存储单元三30c进行数据存储时，可以使电连接件三32c连通相变存储层三31c和电极五20c，这样电流经过电极五20c并依次流经电连接件三32c和相变存储层三31c后从电极一10a中流出形成回路，从而利用相变存储层一31a的状态转换实现数据的存储。
参见图8所示，相变存储层31包括层叠的多层第一相变层311和第二相变层312时，第一相变层311和第二相变层312均与电连接件32连接。其中，电连接件32可以是选通管，选通管的成型材料可以为Ge、Te、Se等。
参见图9所示，相变存储单元30的外周上也可以环绕设置有第一绝缘层50，在相邻的两个第一电极10之间、以及相邻的两个第二电极20之间均可以设置有第二绝缘层40。
以下结合附图，对本申请实施例中的相变存储层31的成型方式一进行详细的说明。
在一种可能的实施方式中，以相变存储层31包括有一个第一相变层311，在第一相变层311的两层分别具有一第二相变层312的结构的形成过程为例进行说明。
图10为本申请实施例提供的一种相变存储层制造过程中处于状态一时的示意图。
参见图10所示，首先可以在第二电极20上形成第一相变材料膜层33，其中，该第一相变材料膜层33可以是硫系化合物通过沉积等方式在第二电极20上形成的膜层。
图11为本申请实施例提供的一种相变存储层制造过程中处于状态二时的示意图。
参见图11所示，可通过光刻蚀等方式对第一相变材料膜层33刻蚀，以使第一相变材料膜层33形成至少一个第一相变层311，形成的第一相变层311的延伸方向可以与第二电极20的延伸方向垂直。其中，可以在第二电极20上形成多个沿着x方向和/或y方向间隔排布的第一相变层311，在图11中，以在y方向上刻蚀形成有两个间隔的第一相变层311为例进行说明。
图12为本申请实施例提供的一种相变存储层制造过程中处于状态三时的示意图。
参见图12所示，在第二电极20以及第一相变层311上覆盖第二相变材料膜层34，其中，第二相变材料膜层34也可以是硫系化合物通过沉积等方式形成的膜层，且第二相变材料膜层34的相变温度高于第一相变材料膜层33的相变温度。
图13为本申请实施例提供的一种相变存储层制造过程中处于状态四时的示意图。
参见图13所示，在第二相变材料膜层34上设置刻蚀阻挡层60，具体的，可以在第二电极20上划分第一区域a和第二区域b，其中，与第一相变层311以及环绕在第一相变层311外周上的第二相变材料膜层34相对的区域为第一区域a，两个第一区域a之间的区域为第二区域b，在第一区域a上方覆盖有刻蚀阻挡层60，第二区域b以及其他区域均不覆盖，然后可通过光刻蚀的方式对第二相变材料膜层34进行刻蚀，这样位于第一相变层311两侧、以及位于第一相变层311上方的第二相变材料膜层34就不会被刻蚀掉。
图14为本申请实施例提供的一种相变存储层制造过程中处于状态五时的示意图。
参见图14所示，去除刻蚀阻挡层60，然后在第二电极20和第二相变材料变膜层34上覆盖绝缘材料层70。
图15为本申请实施例提供的一种相变存储层制造过程中处于状态六时的示意图。
参见图15所示，在绝缘材料层70上覆盖刻蚀阻挡层60，具体的，如图15中所示，在第一区域a以及其他区域上方不覆盖刻蚀阻挡层60，在第二区域b上方覆盖刻蚀阻挡层60，然后可通过光刻蚀的方式进行刻蚀，以在第一相变层311两侧形成第二相变层312，并使第一相变层311和第二相变层312暴露出来。
图16为本申请实施例提供的一种相变存储层制造过程中处于状态七时的示意图。
参见图16所示，去除部分的绝缘材料层70，以形成第一绝缘层50，去除后形成的第一绝缘层50的高度与第一相变层311、第二相变层312保持平齐。这样就形成两个通过第一绝缘层50相互隔离的相变存储层31，在其上继续形成第一电极10等，即可形成相变存储器100。
其中，电连接件32可首先在第二电极上形成，然后再用上述方式在电连接件上形成相变存储层31。
需要说明的是，上述的成型方式也可以适用于由多个第一相变层和第二相变层组成的相变存储层31的成型。
在另一种可能的实施方式中，以相变存储层31包括有多层第一相变层311和第二相变层312，第一相变层311与第二相变层312交替排列的结构的形成过程为例进行说明。
图17为本申请实施例提供的另一种相变存储层制造过程中处于状态一时的示意图。
参见图17所示，首先在第二电极20上形成第一相变材料膜层33，其中，该第一相变材料膜层33可以是硫系化合物通过沉积等方式在第二电极20上形成的膜层。
图18为本申请实施例提供的另一种相变存储层制造过程中处于状态二时的示意图。
参见图18所示，可通过光刻蚀等方式对第一相变材料膜层33刻蚀，以使第一相变材料膜层33形成至少一个第一相变层311，该第一相变层为第一相变层一311a，其中，第一相变层一311a的延伸方向与第一电极10的延伸方向垂直。在图18中，以刻蚀形成有两个间隔的第一相变层一311a为例进行说明。
图19为本申请实施例提供的另一种相变存储层制造过程中处于状态三时的示意图。
参见图19所示，在第二电极20以及第一相变层一311a上覆盖第二相变材料膜层34，其中，第二相变材料膜层34也可以是硫系化合物通过沉积等方式形成的膜层，且第二相变材料膜层34的相变温度高于第一相变材料膜层33的相变温度。
图20为本申请实施例提供的另一种相变存储层制造过程中处于状态四时的示意图。
参见图20所示，可以通过光刻蚀的方式，对第二相变材料膜层34进行刻蚀，使第一相变层一311a两侧保留有第二相变材料膜层34，其余部位的第二相变材料膜层34均被刻蚀，从而在第一相变层一311a的两侧形成第二相变层312，同时将第一相变 层一311a暴露出来，以该第二相变层312为第二相变层一312a。
其中，通过光刻蚀的方式直接对图19中的第二相变材料膜层34进行刻蚀时，位于第一相变层一311a背离第二电极20的一端，由于受光刻蚀的影响，端部的四角处容易被光刻蚀掉，刻蚀速度较快，而使该端部的端面呈椭圆形。
图21为本申请实施例提供的另一种相变存储层制造过程中处于状态五时的示意图。
参见图21所示，在第二电极20、第二相变层一312a以及第一相变层一311a上覆盖第一相变材料膜层33。
图22为本申请实施例提供的另一种相变存储层制造过程中处于状态六时的示意图。
参见图22，可以通过光刻蚀的方式，对第一相变材料膜层33进行刻蚀，以在第二相变层一312a的两侧形成第一相变层311，并使第二相变层一312a和第一相变层一311a均暴露出来，以该第一相变层311为第一相变层二311b。
其中，应当理解的是，在刻蚀后，也可以不使第二相变层一312a和第一相变层一311a均暴露出来，而在最后去除相变存储层31端部的一部分(参照图27)，使各相变层均暴露出来。
图23为本申请实施例提供的另一种相变存储层制造过程中处于状态七时的示意图。
参见图23所示，在第二电极20、第一相变层二311b上覆盖第二相变材料膜层34。
图24为本申请实施例提供的另一种相变存储层制造过程中处于状态八时的示意图。
参见图24所示，可以通过光刻蚀的方式，对第二相变材料膜层34进行刻蚀，以在第一相变层二311b的两侧形成第二相变层二312b，并将第一相变层二311b、第二相变层一312a和第一相变层一311a暴露出来，从而在第二电极20上形成两个相变存储层31，且每个相变存储层31包括多层第一相变层311和第二相变层312。
图25为本申请实施例提供的另一种相变存储层制造过程中处于状态九时的示意图。
参见图25所示，在第一电极10和形成的相变存储层31上覆盖绝缘材料层70。
图26为本申请实施例提供的另一种相变存储层制造过程中处于状态十时的示意图。
参见图26所示，去除部分的绝缘材料层70，以形成第一绝缘层50，并将相变存储层31暴露出来。这样就形成两个通过第一绝缘层50相互隔离的相变存储层31，在其上继续形成第一电极10等，即可形成相变存储器100。
图27为本申请实施例提供的另一种相变存储层制造过程中处于状态十一时的示意图。
参见图27所示，在去除绝缘材料层70，以在相变存储层31之间形成第一绝缘层50时，可以适当的去除相变存储层31端部的一部分，使相变存储层31中的各相变层均暴露出来，这样在第二电极20上就形成相变存储层。
以下结合附图，对本申请实施例中的相变存储层31的成型方式二进行详细的说明。
图28为本申请实施例提供的又一种相变存储层制造过程中处于状态一时的示意图。
参见图28所示，首先可以在第二电极20上形成第一绝缘层50。其中，第一绝缘层50可以是通过在第二电极20上沉积一层绝缘材料层70后，通过刻蚀的方式形成如图28中条状的第一绝缘层50。其中，在第二电极20上可以刻蚀形成多条条状的第一绝缘层50(参照图36)。
图29为本申请实施例提供的又一种相变存储层制造过程中处于状态二时的示意图。
参见图29所示，在第二电极20以及第一绝缘层50上覆盖第二相变材料膜层34。其中，第二相变材料膜层34可以是硫系化合物通过沉积等方式形成的膜层。
图30为本申请实施例提供的又一种相变存储层制造过程中处于状态三时的示意图。
参见图30所示，可以通过光刻蚀的方式，对第二相变材料膜层进行刻蚀，使第一绝缘层50两侧保留有第二相变材料膜层34，其余部分的第二相变材料膜层34均被刻蚀，这样在第一绝缘层50两侧就形成第二相变层312，以该第二相变层312为第二相变层一312a。
图31为本申请实施例提供的又一种相变存储层制造过程中处于状态四时的示意图。
参见图31所示，在第二电极20、第二相变材料层一312a上覆盖第一相变材料膜层33。其中，该第一相变材料膜层33可以是硫系化合物通过沉积等方式形成的膜层，且第一相变材料膜层33的相变温度低于第二相变材料膜层34的相变温度。
图32为本申请实施例提供的又一种相变存储层制造过程中处于状态五时的示意图。
参见图32所示，可以通过光刻蚀的方式，对第一相变材料膜层33进行刻蚀，在第二相变层一312a的两侧形成第一相变层311，并使第二相变层一312a暴露出来。
图33为本申请实施例提供的又一种相变存储层制造过程中处于状态六时的示意图。
参见图33所示，在第二电极20、第二相变层一312a和第一相变层311上覆盖第二相变材料膜层34。
图34为本申请实施例提供的又一种相变存储层制造过程中处于状态七时的示意图。
参见图34所示，可以通过光刻蚀的方式，对第二相变材料膜层34进行刻蚀，在第一相变层311的两侧形成第二相变层二312b。
当相变存储层31包括多层的第一相变层311和第二相变层312时，可以继续交替沉积并刻蚀形成多层的相变存储层31。
图35为本申请实施例提供的又一种相变存储层制造过程中处于状态八时的侧视示意图，图36为本申请实施例提供的又一种相变存储层制造过程中处于状态八时的俯视示意图。
参见图35所示，适当的去除形成的相变存储层整体的端部的一部分，使相变存储层31中的各相变层均暴露出来。其中，参见图36所示，在第二电极20上就形成了通过第一绝缘层50相互隔离的两个条状的相变存储层31。
图37为本申请实施例提供的又一种相变存储层制造过程中处于状态九时的俯视示意图。
参见图37所示，可以通过刻蚀的方式，在条状的第一绝缘层50和相变存储层31的延伸方向上间隔形成多个间隙80，这样就形成多排多列间隔的相变存储层31。
图38为本申请实施例提供的又一种相变存储层制造过程中处于状态十时的俯视示意图。
参见图38所示，在间隙80内沉积绝缘材料以形成第一绝缘层50，这样就形成多个通过第一绝缘层50相互隔离的相变存储层31，在其上继续形成第一电极10等，即可形成相变存储器100。
本申请实施例还提供一种电子设备，该电子设备可以包括但不限于为手机、平板电脑、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、手持计算机、对讲机、上网本、POS机、个人数字助理(personal digital assistant，PDA)、可穿戴设备、智能电视、虚拟现实设备等具有存储功能的固定终端或移动终端。
具体的，电子设备可以包括有壳体，相变存储器可以设置在壳体内，相变存储器可以与电子设备的控制器电连接。
在本申请实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应作广义理解，例如，可以是固定连接，也可以是通过中间媒介间接相连，可以是两个元件内部的相连或者两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请实施例中的具体含义。
本申请实施例的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
最后应说明的是：以上各实施例仅用以说明本申请实施例的技术方案，而非对其限制；尽管参照前述各实施例对本申请实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请实施例各实施例技术方案的范围。

Claims (10)

  1. 一种相变存储器，其特征在于，包括：第一电极(10)、第二电极(20)和相变存储单元(30)，所述相变存储单元(30)位于所述第一电极(10)和所述第二电极(20)之间；
    所述相变存储单元(30)包括相变存储层(31)，所述相变存储层(31)包括层叠的第一相变层(311)和第二相变层(312)，所述第一相变层(311)和所述第二相变层(312)的处于同侧的第一端被耦合至所述第一电极(10)，所述第一相变层(311)和所述第二相变层(312)的处于另一侧的第二端被耦合至所述第二电极(20)。
  2. 根据权利要求1所述的相变存储器，其特征在于，所述第一相变层(311)处于两层所述第二相变层(312)之间，所述第二相变层(312)的相变温度大于所述第一相变层(311)的相变温度。
  3. 根据权利要求2所述的相变存储器，其特征在于，所述第二相变层(312)的相变温度与所述第一相变层(311)的相变温度之间的温度差大于等于100℃。
  4. 根据权利要求1-3任一所述的相变存储器，其特征在于，所述第一电极(10)的延伸方向与所述第二电极(20)的延伸方向垂直，所述相变存储单元(30)与所述第一电极(10)的延伸方向和所述第二电极(20)的延伸方向均垂直。
  5. 根据权利要求1-4任一所述的相变存储器，其特征在于，所述存储单元还包括电连接件(32)，所述第二端通过所述电连接件(32)与所述第二电极(20)连接，所述电连接件(32)用于连通或断开所述第二端与所述第二电极(20)之间的连接。
  6. 根据权利要求5所述的相变存储器，其特征在于，所述电连接件(32)包括选通管。
  7. 根据权利要求1-6任一所述的相变存储器，其特征在于，还包括第一绝缘层(50)，所述第一电极(10)、所述第二电极(20)和所述相变存储单元(30)均为多个，多个所述第一电极(10)相互平行设置，多个所述第二电极(20)相互平行设置；
    所述第一绝缘层(50)环绕覆盖在所述相变存储单元(30)的外周上，相邻的两相变存储单元(30)之间均具有所述第一绝缘层(50)。
  8. 根据权利要求1-7任一所述的相变存储器，其特征在于，还包括第二绝缘层(40)，相邻的两个所述第一电极(10)之间以及相邻的两个所述第二电极(20)之间均具有所述第二绝缘层(40)。
  9. 根据权利要求1-8任一所述的相变存储器，其特征在于，所述第一相变层(311)和所述第二相变层(312)的成型材质均至少包括硫系化合物。
  10. 一种电子设备，其特征在于，包括壳体和上述权利要求1-9任一所述的相变存储器(100)，所述相变存储器设置在所述壳体内。
PCT/CN2021/098367 2021-06-04 2021-06-04 一种相变存储器及电子设备 WO2022252219A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140246646A1 (en) * 2011-10-07 2014-09-04 Yoshitaka Sasago Semiconductor storage device and method of fabricating same
CN112436028A (zh) * 2020-11-23 2021-03-02 长江先进存储产业创新中心有限责任公司 一种三维存储器及三维存储器的形成方法
CN112768491A (zh) * 2021-02-10 2021-05-07 长江先进存储产业创新中心有限责任公司 一种三维存储器及三维存储器的形成方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140246646A1 (en) * 2011-10-07 2014-09-04 Yoshitaka Sasago Semiconductor storage device and method of fabricating same
CN112436028A (zh) * 2020-11-23 2021-03-02 长江先进存储产业创新中心有限责任公司 一种三维存储器及三维存储器的形成方法
CN112768491A (zh) * 2021-02-10 2021-05-07 长江先进存储产业创新中心有限责任公司 一种三维存储器及三维存储器的形成方法

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